Fix OmniNX brand rendering after ini_parse change

ini_parse() return-code semantics changed upstream; Nyx treated success as failure so OmniNX manifest data was ignored.

Made-with: Cursor

Makefile

@@ -60,7 +60,7 @@ CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -
 CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_VER_RL=$(NYXVERSION_REL)
 
 # BDK defines.
-CUSTOMDEFINES += -DBDK_MALLOC_NO_DEFRAG -DBDK_MC_ENABLE_AHB_REDIRECT -DBDK_EMUMMC_ENABLE
+CUSTOMDEFINES += -DBDK_MALLOC_NO_DEFRAG -DBDK_EMUMMC_ENABLE
 CUSTOMDEFINES += -DBDK_WATCHDOG_FIQ_ENABLE -DBDK_RESTART_BL_ON_WDT
 CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC)
 

README.md

@@ -66,7 +66,7 @@ Custom Graphical Nintendo Switch bootloader, firmware patcher, tools, and many m
 
 ## Bootloader configuration
 
-The bootloader can be configured via 'bootloader/hekate_ipl.ini' (if it is present on the SD card). Each ini section represents a boot entry, except for the special section 'config' that controls the global configuration.
+The bootloader can be configured via `Nyx` -> `Options` or 'bootloader/hekate_ipl.ini'. The special section 'config' controls the actual global configuration. Any other ini section represents a boot entry and can only be edited manually via the ini.
 
 
 There are four possible type of entries. "**[ ]**": Boot entry, "**{ }**": Caption, "**#**": Comment, "*newline*": .ini cosmetic newline.
@@ -75,22 +75,27 @@ There are four possible type of entries. "**[ ]**": Boot entry, "**{ }**": Capti
 **You can find a template [Here](./res/hekate_ipl_template.ini)**
 
 
-### hekate Global Configuration keys/values (when entry is *[config]*):
+### hekate Configuration keys/values (section *[config]*)
+
+Use `Options` in Nyx to edit the following configuration:
 
 | Config option      | Description                                                    |
 | ------------------ | -------------------------------------------------------------- |
 | autoboot=0         | 0: Disable, #: Boot entry number to auto boot.                 |
 | autoboot_list=0    | 0: Read `autoboot` boot entry from hekate_ipl.ini, 1: Read from ini folder (ini files are ASCII ordered). |
 | bootwait=3         | 0: Disable (It also disables bootlogo. Having **VOL-** pressed since injection goes to menu.), #: Time to wait for **VOL-** to enter menu. Max: 20s. |
-| noticker=0         | 0: Animated line is drawn during custom bootlogo, signifying time left to skip to menu. 1: Disable. |
 | autohosoff=1       | 0: Disable, 1: If woke up from HOS via an RTC alarm, shows logo, then powers off completely, 2: No logo, immediately powers off.|
 | autonogc=1         | 0: Disable, 1: Automatically applies nogc patch if unburnt fuses found and a >= 4.0.0 HOS is booted. |
-| bootprotect=0      | 0: Disable, 1: Protect bootloader folder from being corrupted by disallowing reading or editing in HOS. |
 | updater2p=0        | 0: Disable, 1: Force updates (if needed) the reboot2payload binary to be hekate. |
 | backlight=100      | Screen backlight level. 0-255.                                 |
+| ------------------ | --------- *The following can be edited via ini only* --------- |
+| noticker=0         | 0: Animated line is drawn during custom bootlogo, signifying time left to skip to menu. 1: Disable. |
+| bootprotect=0      | 0: Disable, 1: Protect bootloader folder from being corrupted by disallowing reading or editing in HOS. |
 
 
-### Boot entry key/value combinations:
+### Boot entry key/value combinations
+
+A boot entry needs to be manually added/edited with the user's chosen key/value combos.
 
 | Config option          | Description                                                |
 | ---------------------- | ---------------------------------------------------------- |
@@ -140,7 +145,9 @@ You can define `kip1` to load an extra kip or many via the wildcard (`/*`) usage
 That's in case the kips are incompatible between them. If compatible, you can override `pkg3`/`fss0` kips with no issues (useful for testing with intermediate kip changes). In such cases, the `kip1` line must be **after** `pkg3`/`fss0` line.
 
 
-### Boot entry key/value combinations for Exosphère:
+### Boot entry key/value combinations for Exosphère
+
+The following can be paired together with a HOS boot entry:
 
 | Config option          | Description                                                |
 | ---------------------- | ---------------------------------------------------------- |
@@ -149,6 +156,7 @@ That's in case the kips are incompatible between them. If compatible, you can ov
 | cal0blank=1            | Overrides Exosphère config `blank_prodinfo_{sys/emu}mmc`. If that key doesn't exist, `exosphere.ini` will be used. |
 | cal0writesys=1         | Overrides Exosphère config `allow_writing_to_cal_sysmmc`. If that key doesn't exist, `exosphere.ini` will be used. |
 | usb3force=1            | Overrides system settings mitm config `usb30_force_enabled`. If that key doesn't exist, `system_settings.ini` will be used. |
+| memmode=1              | Enables boot config memory mode for retail units. By default, max ram is limited to 4GB. Enabling this will automatically choose size. |
 
 
 **Note**: `cal0blank`, `cal0writesys`, `usb3force`, as stated override the `exosphere.ini` or `system_settings.ini`. 0: Disable, 1: Enable, Key Missing: Use original value.
@@ -157,7 +165,7 @@ That's in case the kips are incompatible between them. If compatible, you can ov
 **Note2**: `blank_prodinfo_{sys/emu}mmc`, `allow_writing_to_cal_sysmmc` and `usb30_force_enabled` in `exosphere.ini` and `system_settings.ini` respectively, are the only atmosphere config keys that can affect hekate booting configuration externally, **if** the equivalent keys in hekate config are missing.
 
 
-### Payload storage:
+## Payload storage
 
 hekate has a boot storage in the binary that helps it configure it outside of BPMP environment:
 
@@ -168,23 +176,25 @@ hekate has a boot storage in the binary that helps it configure it outside of BP
 | '0x96' autoboot_list    | If `Force AutoBoot` and `autoboot` then it boots from ini folder. |
 | '0x97' extra_cfg        | When menu is forced: bit5: `Run UMS`.                             |
 | '0x98' xt_str[128]      | Depends on the set cfg bits.                                      |
-| '0x98' ums[1]           | When `Run UMS` is set, it will launch the selected UMS. 0: SD, 1: eMMC BOOT0, 2: eMMC BOOT1, 3: eMMC GPP, 4: emuMMC BOOT0, 5: emuMMC BOOT1, 6: emuMMC GPP,  |
+| '0x98' ums[1]           | When `Run UMS` is set, it will launch the selected UMS. 0: SD, 1/2/3: eMMC BOOT0/BOOT1/GPP, 4/5/6: emuMMC BOOT0/BOOT1/GPP,  |
 | '0x98' id[8]            | When `Boot from ID` is set, it will search all inis automatically and find the boot entry with that id and boot it. Must be NULL terminated. |
 | '0xA0' emummc_path[120] | When `Boot to emuMMC` is set, it will override the current emuMMC (boot entry or emummc.ini). Must be NULL terminated. |
 
 
-### Nyx Configuration keys/values (nyx.ini):
+## Nyx Configuration keys/values (nyx.ini)
+
+Use `Nyx Settings` in Nyx to edit the following configuration:
 
 | Config option      | Description                                                |
 | ------------------ | ---------------------------------------------------------- |
-| themebg=2d2d2d     | Sets Nyx background color in HEX. EXPERIMENTAL.            |
+| themebg=2d2d2d     | Sets Nyx background color in HEX. 0x0B0B0B to 0xC7C7C7.    |
 | themecolor=167     | Sets Nyx color of text highlights.                         |
 | entries5col=0      | 1: Sets Launch entry columns from 4 to 5 per line. For a total of 10 entries. |
-| timeoffset=100     | Sets time offset in HEX. Must be in epoch format           |
-| timedst=0          | Enables automatic daylight saving hour adjustment          |
+| timeoffset=0       | Sets time offset in HEX. Must be in epoch format           |
+| timedst=1          | Enables automatic daylight saving hour adjustment          |
 | homescreen=0       | Sets home screen. 0: Home menu, 1: All configs (merges Launch and More configs), 2: Launch, 3: More Configs. |
 | verification=1     | 0: Disable Backup/Restore verification, 1: Sparse (block based, fast and mostly reliable), 2: Full (sha256 based, slow and 100% reliable). |
-| ------------------ | ------- The following options can only be edited in nyx.ini ------- |
+| ------------------ | ----- *The following can be edited via nyx.ini only* ----- |
 | umsemmcrw=0        | 1: eMMC/emuMMC UMS will be mounted as writable by default. |
 | jcdisable=0        | 1: Disables Joycon driver completely.                      |
 | jcforceright=0     | 1: Forces right joycon to be used as main mouse control.   |

Versions.inc

@@ -1,11 +1,11 @@
 # IPL Version.
 BLVERSION_MAJOR := 6
 BLVERSION_MINOR := 5
-BLVERSION_HOTFX := 1
+BLVERSION_HOTFX := 2
 BLVERSION_REL   := 0
 
 # Nyx Version.
 NYXVERSION_MAJOR := 1
 NYXVERSION_MINOR := 9
-NYXVERSION_HOTFX := 1
+NYXVERSION_HOTFX := 2
 NYXVERSION_REL   := 0

bdk/display/di.c

@@ -24,7 +24,6 @@
 #include <soc/fuse.h>
 #include <soc/gpio.h>
 #include <soc/hw_init.h>
-#include <soc/i2c.h>
 #include <soc/pinmux.h>
 #include <soc/pmc.h>
 #include <soc/timer.h>

bdk/display/vic.c

@@ -1,5 +1,5 @@
 /*
- * VIC driver for Tegra X1
+ * VIC (4.0) driver for Tegra X1
  *
  * Copyright (c) 2018-2024 CTCaer
  *
@@ -45,9 +45,10 @@
 #define VIC_FC_CFG_STRUCT_SLOT_CFG2            0x10B0C
 #define  CACHE_WIDTH(n) ((n) << 16)
 #define  CACHE_WIDTH_16BX16                     0 // Block Linear.
-#define  CACHE_WIDTH_32BX8                      1 // Block Linear. Recommended for Block Linear.
-#define  CACHE_WIDTH_64BX4                      2 // Block Linear, Pitch. Recommended for Pitch.
+#define  CACHE_WIDTH_32BX8                      1 // Block Linear.
+#define  CACHE_WIDTH_64BX4                      2 // Block Linear, Pitch. Recommended.
 #define  CACHE_WIDTH_128BX2                     3 // Block Linear, Pitch.
+#define  CACHE_WIDTH_256BX1                     4 // Pitch.
 #define  OUTPUT_FLIP_X                          BIT(20)
 #define  OUTPUT_FLIP_Y                          BIT(21)
 #define  OUTPUT_TRANSPOSE                       BIT(22)
@@ -374,7 +375,7 @@ static void _vic_write_priv(u32 addr, u32 data)
 		VIC(PVIC_FALCON_ADDR) = 0;
 }
 
-static int _vic_wait_idle()
+int vic_wait_idle()
 {
 	u32 timeout_count = 15000; // 150ms.
 
@@ -384,7 +385,7 @@ static int _vic_wait_idle()
 
 		timeout_count--;
 		if (!timeout_count)
-			return -1;
+			return 1;
 	};
 
 	return 0;
@@ -508,7 +509,7 @@ void vic_set_surface(const vic_surface_t *sfc)
 	_vic_write_priv(VIC_SC_PRAMSIZE, sizeof(vic_config_t) >> 6);
 
 	// Wait for surface cache to get ready.
-	_vic_wait_idle();
+	vic_wait_idle();
 
 	// Set slot mapping.
 	_vic_write_priv(VIC_FC_SLOT_MAP, 0xFFFFFFF0);
@@ -523,13 +524,13 @@ void vic_set_surface(const vic_surface_t *sfc)
 	_vic_write_priv(VIC_BL_CONFIG, SLOTMASK(0x1F) | PROCESS_CFG_STRUCT_TRIGGER | SUBPARTITION_MODE);
 
 	// Wait for surface cache to get ready.
-	_vic_wait_idle();
+	vic_wait_idle();
 }
 
 int vic_compose()
 {
 	// Wait for surface cache to get ready. Otherwise VIC will hang.
-	int res = _vic_wait_idle();
+	int res = vic_wait_idle();
 
 	// Start composition of a single frame.
 	_vic_write_priv(VIC_FC_COMPOSE, COMPOSE_START);
@@ -551,7 +552,7 @@ int vic_init()
 	// Start Fetch Control Engine.
 	_vic_write_priv(VIC_FC_FCE_CTRL, START_TRIGGER);
 
-	return _vic_wait_idle();
+	return vic_wait_idle();
 }
 
 void vic_end()

bdk/display/vic.h

@@ -59,6 +59,7 @@ typedef struct _vic_surface_t
 } vic_surface_t;
 
 void vic_set_surface(const vic_surface_t *sfc);
+int  vic_wait_idle();
 int  vic_compose();
 int  vic_init();
 void vic_end();

bdk/exception_handlers.S

@@ -41,9 +41,9 @@
  * 11111  | SYS  | r0–r7, SP,     LR,     PC, CPSR           | r0–r14,                   PC, CPSR
  */
 
-#define EXCP_EN_ADDR   0x4003FFFC
-#define EXCP_TYPE_ADDR 0x4003FFF8
-#define EXCP_LR_ADDR   0x4003FFF4
+#define EXCP_EN_ADDR   0x4003FF1C
+#define EXCP_TYPE_ADDR 0x4003FF18
+#define EXCP_LR_ADDR   0x4003FF14
 
 #define EXCP_VEC_BASE  0x6000F000
 #define EVP_COP_RESET_VECTOR          0x200

bdk/ianos/elfload/elfload.c

@@ -21,7 +21,7 @@
 
 el_status el_pread(el_ctx *ctx, void *def, size_t nb, size_t offset)
 {
-	return ctx->pread(ctx, def, nb, offset) ? EL_OK : EL_EIO;
+	return ctx->pread(ctx, def, nb, offset);
 }
 
 #define EL_PHOFF(ctx, num) (((ctx)->ehdr.e_phoff + (num) *(ctx)->ehdr.e_phentsize))

bdk/ianos/elfload/elfload.h

@@ -53,7 +53,7 @@ typedef enum
 
 typedef struct el_ctx
 {
-	bool (*pread)(struct el_ctx *ctx, void *dest, size_t nb, size_t offset);
+	el_status (*pread)(struct el_ctx *ctx, void *dest, size_t nb, size_t offset);
 
 	/* base_load_* -> address we are actually going to load at
 	 */
@@ -61,6 +61,9 @@ typedef struct el_ctx
 		base_load_paddr,
 		base_load_vaddr;
 
+	/* original memory of binary */
+	Elf_Addr eaddr;
+
 	/* size in memory of binary */
 	Elf_Addr memsz;
 

bdk/ianos/ianos.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 M4xw
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -21,103 +21,141 @@
 #include "elfload/elfload.h"
 #include <module.h>
 #include <mem/heap.h>
-#include <power/max7762x.h>
 #include <storage/sd.h>
 #include <utils/types.h>
 
 #include <gfx_utils.h>
 
-#define IRAM_LIB_ADDR 0x4002B000
-#define DRAM_LIB_ADDR 0xE0000000
-
 extern heap_t _heap;
 
-void *elfBuf = NULL;
-void *fileBuf = NULL;
+static bdk_params_t _bdk_params = {
+	.gfx_con = (void *)&gfx_con,
+	.gfx_ctx = (void *)&gfx_ctxt,
+	.heap    = &_heap,
+	.memcpy  = (memcpy_t)&memcpy,
+	.memset  = (memset_t)&memset,
 
-static void _ianos_call_ep(moduleEntrypoint_t entrypoint, void *moduleConfig)
-{
-	bdkParams_t bdkParameters = (bdkParams_t)malloc(sizeof(struct _bdkParams_t));
-	bdkParameters->gfxCon = (void *)&gfx_con;
-	bdkParameters->gfxCtx = (void *)&gfx_ctxt;
-	bdkParameters->memcpy = (memcpy_t)&memcpy;
-	bdkParameters->memset = (memset_t)&memset;
-	bdkParameters->sharedHeap = &_heap;
-
-	// Extra functions.
-	bdkParameters->extension_magic = IANOS_EXT0;
-	bdkParameters->reg_voltage_set = (reg_voltage_set_t)&max7762x_regulator_set_voltage;
-
-	entrypoint(moduleConfig, bdkParameters);
-}
+	.extension_magic = 0
+};
 
 static void *_ianos_alloc_cb(el_ctx *ctx, Elf_Addr phys, Elf_Addr virt, Elf_Addr size)
 {
-	(void)ctx;
-	(void)phys;
-	(void)size;
 	return (void *)virt;
 }
 
-static bool _ianos_read_cb(el_ctx *ctx, void *dest, size_t numberBytes, size_t offset)
+static el_status _ianos_read_cb(el_ctx *ctx, void *dest, size_t nb, size_t offset)
 {
-	(void)ctx;
+	memcpy(dest, (void *)(ctx->eaddr + offset), nb);
 
-	memcpy(dest, fileBuf + offset, numberBytes);
-
-	return true;
+	return EL_OK;
 }
 
 //TODO: Support shared libraries.
-uintptr_t ianos_loader(char *path, elfType_t type, void *moduleConfig)
+int ianos_loader(ianos_lib_t *lib, char *path)
 {
 	el_ctx ctx;
-	uintptr_t epaddr = 0;
+	lib->buf = NULL;
+	if (!lib->bdk)
+		lib->bdk = &_bdk_params;
 
 	// Read library.
-	fileBuf = sd_file_read(path, NULL);
-
-	if (!fileBuf)
-		goto out;
+	ctx.eaddr = (Elf_Addr)sd_file_read(path, NULL);
+	if (!ctx.eaddr)
+		goto error;
 
 	ctx.pread = _ianos_read_cb;
 
 	if (el_init(&ctx))
-		goto out;
+		goto error;
+
+	if (lib->type & IA_SHARED_LIB)
+		goto error; // No support for shared libs now.
 
 	// Set our relocated library's buffer.
-	switch (type & 0xFFFF)
+	switch (lib->type & ~IA_SHARED_LIB)
 	{
-	case EXEC_ELF:
-	case AR64_ELF:
-		elfBuf = (void *)DRAM_LIB_ADDR;
+	case IA_DRAM_LIB:
+		lib->buf = malloc(ctx.memsz); // Aligned to 0x10 by default.
 		break;
+
+	case IA_IRAM_LIB:
+		break;
+
+	case IA_AUTO_LIB: // Default to DRAM for now.
 	default:
-		elfBuf = malloc(ctx.memsz); // Aligned to 0x10 by default.
+		lib->buf = malloc(ctx.memsz); // Aligned to 0x10 by default.
+		break;
 	}
 
-	if (!elfBuf)
-		goto out;
+	if (!lib->buf)
+		goto error;
 
 	// Load and relocate library.
-	ctx.base_load_vaddr = ctx.base_load_paddr = (uintptr_t)elfBuf;
+	ctx.base_load_vaddr = ctx.base_load_paddr = (Elf_Addr)lib->buf;
 	if (el_load(&ctx, _ianos_alloc_cb))
-		goto out_free;
+		goto error;
 
 	if (el_relocate(&ctx))
-		goto out_free;
+		goto error;
+
+	free((void *)ctx.eaddr);
 
 	// Launch.
-	epaddr = ctx.ehdr.e_entry + (uintptr_t)elfBuf;
-	moduleEntrypoint_t ep = (moduleEntrypoint_t)epaddr;
+	Elf_Addr epaddr = ctx.ehdr.e_entry + (Elf_Addr)lib->buf;
+	moduleEntrypoint ep = (moduleEntrypoint)epaddr;
+	ep(lib->private, lib->bdk);
 
-	_ianos_call_ep(ep, moduleConfig);
+	return 0;
 
-out_free:
-	free(fileBuf);
-	elfBuf = NULL;
-	fileBuf = NULL;
+error:
+	free((void *)ctx.eaddr);
+	free(lib->buf);
 
-out:
-	return epaddr;
-}
+	return 1;
+}
+
+uintptr_t ianos_static_module(char *path, void *private)
+{
+	el_ctx ctx;
+	Elf_Addr buf = 0;
+	Elf_Addr epaddr = 0;
+
+	// Read library.
+	ctx.eaddr = (Elf_Addr)sd_file_read(path, NULL);
+	if (!ctx.eaddr)
+		goto error;
+
+	ctx.pread = _ianos_read_cb;
+
+	// Initialize elfload context.
+	if (el_init(&ctx))
+		goto error;
+
+	// Set our relocated library's buffer.
+	buf = (Elf_Addr)malloc(ctx.memsz); // Aligned to 0x10 by default.
+	if (!buf)
+		goto error;
+
+	// Load and relocate library.
+	ctx.base_load_vaddr = ctx.base_load_paddr = buf;
+	if (el_load(&ctx, _ianos_alloc_cb))
+		goto error;
+
+	if (el_relocate(&ctx))
+		goto error;
+
+	free((void *)ctx.eaddr);
+
+	// Launch.
+	epaddr = ctx.ehdr.e_entry + buf;
+	moduleEntrypoint ep = (moduleEntrypoint)epaddr;
+	ep(private, &_bdk_params);
+
+	return (uintptr_t)epaddr;
+
+error:
+	free((void *)ctx.eaddr);
+	free((void *)buf);
+
+	return 0;
+}

bdk/ianos/ianos.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 M4xw
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -19,16 +19,26 @@
 #define IANOS_H
 
 #include <utils/types.h>
+#include <module.h>
 
 typedef enum
 {
-	DRAM_LIB = 0, // DRAM library.
-	EXEC_ELF = 1, // Executable elf that does not return.
-	DR64_LIB = 2, // AARCH64 DRAM library.
-	AR64_ELF = 3, // Executable elf that does not return.
-	KEEP_IN_RAM = (1 << 31)  // Shared library mask.
-} elfType_t;
+	IA_DRAM_LIB   = 0, // DRAM library.
+	IA_IRAM_LIB   = 1, // IRAM library. No support for now.
+	IA_AUTO_LIB   = 2, // AUTO library. Defaults to DRAM for now.
+	IA_SHARED_LIB = BIT(7) // Shared library mask. No support for now.
+} ianos_type_t;
 
-uintptr_t ianos_loader(char *path, elfType_t type, void* config);
+typedef struct _ianos_lib_t
+{
+	uintptr_t epaddr;
+	void *buf;
+	void *private;
+	ianos_type_t type;
+	bdk_params_t *bdk;
+} ianos_lib_t;
 
-#endif
+int       ianos_loader(ianos_lib_t *lib, char *path);
+uintptr_t ianos_static_module(char *path, void *private); // Session-lived DRAM lib.
+
+#endif

bdk/input/touch.c

@@ -2,7 +2,7 @@
  * Touch driver for Nintendo Switch's STM FingerTip S (FTM4CD60DA1BE/FTM4CD50TA1BE) touch controller
  *
  * Copyright (c) 2018 langerhans
- * Copyright (c) 2018-2023 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,10 +29,6 @@
 #include <utils/btn.h>
 #include "touch.h"
 
-
-#include <gfx_utils.h>
-#define DPRINTF(...) gfx_printf(__VA_ARGS__)
-
 static touch_panel_info_t _panels[] =
 {
 	{  0,  1, 1, 1,  "NISSHA NFT-K12D" },// 0.
@@ -43,39 +39,52 @@ static touch_panel_info_t _panels[] =
 	{ -1,  1, 0, 1,  "GiS VA 6.2\""    } // 2.
 };
 
-static int touch_command(u8 cmd, u8 *buf, u8 size)
+static touch_info_t _touch_info = { 0 };
+static touch_panel_info_t _touch_panel_info = { 0 };
+
+static int _touch_command(u8 cmd, u8 *buf, u8 size)
 {
-	int res = i2c_send_buf_small(I2C_3, STMFTS_I2C_ADDR, cmd, buf, size);
-	if (!res)
-		return 1;
-	return 0;
+	return i2c_send_buf_small(I2C_3, FTS4_I2C_ADDR, cmd, buf, size);
 }
 
-static int touch_read_reg(u8 *cmd, u32 csize, u8 *buf, u32 size)
+static int _touch_read_reg(u8 *cmd, u32 csize, u8 *buf, u32 size)
 {
-	int res = i2c_send_buf_small(I2C_3, STMFTS_I2C_ADDR, cmd[0], &cmd[1], csize - 1);
-	if (res)
-		res = i2c_recv_buf(buf, size, I2C_3, STMFTS_I2C_ADDR);
-	if (!res)
-		return 1;
-
-	return 0;
+	return i2c_xfer_packet(I2C_3, FTS4_I2C_ADDR, cmd, csize, buf, size);
 }
 
-static int touch_wait_event(u8 event, u8 status, u32 timeout, u8 *buf)
+int touch_get_event_count()
+{
+	u8 cmd[3] = { FTS4_CMD_HW_REG_READ, 0, FTS4_HW_REG_EVENT_COUNT };
+	u8 buf[2];
+
+	if (_touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf)))
+		return 0;
+
+	return (buf[1] >> 1);
+}
+
+static int _touch_wait_event(u8 event, u8 status, u32 timeout, u8 *buf)
 {
 	u32 timer = get_tmr_ms() + timeout;
 	while (true)
 	{
-		u8 tmp[8] = {0};
-		i2c_recv_buf_small(tmp, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_READ_ONE_EVENT);
-		if (tmp[1] == event && tmp[2] == status)
+		if (!touch_get_event_count())
+			goto retry;
+
+		u8 tmp[FTS4_EVENT_SIZE];
+		int res = i2c_recv_buf_big(tmp, FTS4_EVENT_SIZE, I2C_3, FTS4_I2C_ADDR, FTS4_CMD_READ_ONE_EVENT);
+
+		// Check that event type and status match.
+		if (!res && tmp[0] == event && tmp[1] == status)
 		{
 			if (buf)
-				memcpy(buf, &tmp[3], 5);
+				memcpy(buf, &tmp[2], 6);
 			return 0;
 		}
 
+retry:
+		usleep(500);
+
 		if (get_tmr_ms() > timer)
 			return 1;
 	}
@@ -85,7 +94,7 @@ static int touch_wait_event(u8 event, u8 status, u32 timeout, u8 *buf)
 #define Y_REAL_MAX 704
 #define EDGE_OFFSET 15
 
-static void _touch_compensate_limits(touch_event *event, bool touching)
+static void _touch_compensate_limits(touch_event_t *event, bool touching)
 {
 	event->x  = MAX(event->x, EDGE_OFFSET);
 	event->x  = MIN(event->x, X_REAL_MAX);
@@ -103,116 +112,102 @@ static void _touch_compensate_limits(touch_event *event, bool touching)
 	}
 }
 
-static void _touch_process_contact_event(touch_event *event, bool touching)
+static void _touch_process_contact_event(touch_event_t *event, bool touching)
 {
-	event->x = (event->raw[2] << 4) | ((event->raw[4] & STMFTS_MASK_Y_LSB) >> 4);
+	event->x = (event->raw[1] << 4) | ((event->raw[3] & FTS4_MASK_Y_LSB) >> 4);
 
 	// Normally, GUI elements have bigger horizontal estate.
 	// Avoid parsing y axis when finger is removed to minimize touch noise.
 	if (touching)
 	{
-		event->y = (event->raw[3] << 4) | (event->raw[4] & STMFTS_MASK_X_MSB);
+		event->y = (event->raw[2] << 4) | (event->raw[3] & FTS4_MASK_X_MSB);
 
-		event->z = event->raw[5] | (event->raw[6] << 8);
+		event->z = event->raw[4] | (event->raw[5] << 8);
 		event->z = event->z << 6;
 
 		u16 tmp = 0x40;
-		if ((event->raw[7] & 0x3F) != 1 && (event->raw[7] & 0x3F) != 0x3F)
-			tmp = event->raw[7] & 0x3F;
+		if ((event->raw[6] & 0x3F) != 1 && (event->raw[6] & 0x3F) != 0x3F)
+			tmp = event->raw[6] & 0x3F;
 		event->z /= tmp + 0x40;
 
-		event->fingers = ((event->raw[1] & STMFTS_MASK_TOUCH_ID) >> 4) + 1;
+		event->finger = ((event->raw[0] & FTS4_MASK_TOUCH_ID) >> 4) + 1;
 	}
 	else
-		event->fingers = 0;
+		event->finger = 0;
 
 	_touch_compensate_limits(event, touching);
 }
 
-static void _touch_parse_event(touch_event *event)
+static int _touch_parse_input_event(touch_event_t *event)
 {
-	event->type = event->raw[1] & STMFTS_MASK_EVENT_ID;
-
-	switch (event->type)
+	switch (event->raw[0] & FTS4_MASK_EVENT_ID)
 	{
-	case STMFTS_EV_MULTI_TOUCH_ENTER:
-	case STMFTS_EV_MULTI_TOUCH_MOTION:
+	case FTS4_EV_MULTI_TOUCH_ENTER:
+	case FTS4_EV_MULTI_TOUCH_MOTION:
 		_touch_process_contact_event(event, true);
-		if (event->z < 255) // Reject palm rest.
+		if (event->z < 500) // Reject palm rest.
 			event->touch = true;
 		else
-		{
 			event->touch = false;
-			event->type = STMFTS_EV_MULTI_TOUCH_LEAVE;
-		}
-		break;
-	case STMFTS_EV_MULTI_TOUCH_LEAVE:
+		return 0;
+
+	case FTS4_EV_MULTI_TOUCH_LEAVE:
 		event->touch = false;
 		_touch_process_contact_event(event, false);
-		break;
-	case STMFTS_EV_NO_EVENT:
-		if (event->touch)
-			event->type = STMFTS_EV_MULTI_TOUCH_MOTION;
-		break;
+		return 0;
+
 	default:
-		if (event->touch && event->raw[0] == STMFTS_EV_MULTI_TOUCH_MOTION)
-			event->type = STMFTS_EV_MULTI_TOUCH_MOTION;
-		else
-			event->type = STMFTS_EV_MULTI_TOUCH_LEAVE;
+		return 1; // No event.
+	}
+}
+
+int touch_poll(touch_event_t *event)
+{
+	u8 cmd = !_touch_info.clone ? FTS4_CMD_LATEST_EVENT : FTS4_CMD_READ_ONE_EVENT;
+
+	int res = i2c_recv_buf_big(event->raw, FTS4_EVENT_SIZE, I2C_3, FTS4_I2C_ADDR, cmd);
+	if (!res)
+		res = _touch_parse_input_event(event);
+
+	return res;
+}
+
+touch_info_t *touch_get_chip_info()
+{
+	u8 buf[7] = { 0 };
+
+	// Get chip info.
+	u8 cmd[3] = { FTS4_CMD_HW_REG_READ, 0, FTS4_HW_REG_CHIP_ID_INFO };
+	if (_touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf)))
+	{
+		memset(&_touch_info, 0, sizeof(touch_info_t));
+		goto exit;
 	}
 
-	// gfx_con_setpos(0, 300);
-	// DPRINTF("x = %d    \ny = %d    \nz = %d  \n", event->x, event->y, event->z);
-	// DPRINTF("0 = %02X\n1 = %02X\n2 = %02X\n3 = %02X\n", event->raw[0], event->raw[1], event->raw[2], event->raw[3]);
-	// DPRINTF("4 = %02X\n5 = %02X\n6 = %02X\n7 = %02X\n", event->raw[4], event->raw[5], event->raw[6], event->raw[7]);
-}
+	_touch_info.chip_id    = buf[1] << 8 | buf[2];
+	_touch_info.fw_ver     = buf[3] << 8 | buf[4];
+	_touch_info.config_id  = buf[5];
+	_touch_info.config_ver = buf[6];
 
-void touch_poll(touch_event *event)
-{
-	i2c_recv_buf_small(event->raw, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_LATEST_EVENT);
+	// Validate that device is genuine or proper.
+	cmd[2] = 2;
+	_touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf));
+	_touch_info.clone = _touch_info.chip_id != (buf[3] << 8 | buf[4]);
 
-	_touch_parse_event(event);
-}
-
-touch_event touch_poll_wait()
-{
-	touch_event event;
-	do
-	{
-		touch_poll(&event);
-	} while (event.type != STMFTS_EV_MULTI_TOUCH_LEAVE);
-
-	return event;
-}
-
-touch_info touch_get_info()
-{
-	touch_info info;
-	u8 buf[8];
-	memset(&buf, 0, 8);
-	i2c_recv_buf_small(buf, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_READ_INFO);
-
-	info.chip_id = buf[0] << 8 | buf[1];
-	info.fw_ver = buf[2] << 8 | buf[3];
-	info.config_id = buf[4];
-	info.config_ver = buf[5];
-
-	//DPRINTF("ID: %04X, FW Ver: %d.%02d\nCfg ID: %02X, Cfg Ver: %d\n",
-	//	info.chip_id, info.fw_ver >> 8, info.fw_ver & 0xFF, info.config_id, info.config_ver);
-
-	return info;
+exit:
+	return &_touch_info;
 }
 
 touch_panel_info_t *touch_get_panel_vendor()
 {
-	u8 buf[5] = {0};
-	u8 cmd = STMFTS_VENDOR_GPIO_STATE;
-	static touch_panel_info_t panel_info = { -2,  0, 0, 0,  ""};
+	_touch_panel_info.idx = -2;
 
-	if (touch_command(STMFTS_VENDOR, &cmd, 1))
+	u8 cmd = FTS4_VENDOR_GPIO_STATE;
+	if (_touch_command(FTS4_CMD_VENDOR, &cmd, 1))
 		return NULL;
 
-	if (touch_wait_event(STMFTS_EV_VENDOR, STMFTS_VENDOR_GPIO_STATE, 2000, buf))
+	u8 buf[6] = { 0 };
+	if (_touch_wait_event(FTS4_EV_VENDOR, FTS4_VENDOR_GPIO_STATE, 2000, buf))
 		return NULL;
 
 	for (u32 i = 0; i < ARRAY_SIZE(_panels); i++)
@@ -223,37 +218,33 @@ touch_panel_info_t *touch_get_panel_vendor()
 	}
 
 	// Touch panel not found, return current gpios.
-	panel_info.gpio0 = buf[0];
-	panel_info.gpio1 = buf[1];
-	panel_info.gpio2 = buf[2];
+	_touch_panel_info.gpio0 = buf[0];
+	_touch_panel_info.gpio1 = buf[1];
+	_touch_panel_info.gpio2 = buf[2];
 
-	return &panel_info;
+	return &_touch_panel_info;
 }
 
 int touch_get_fw_info(touch_fw_info_t *fw)
 {
-	u8 buf[8] = {0};
+	u8 buf[9] = { 0 };
 
 	memset(fw, 0, sizeof(touch_fw_info_t));
 
 	// Get fw address info.
-	u8 cmd[3] = { STMFTS_RW_FRAMEBUFFER_REG, 0, 0x60 };
-	int res = touch_read_reg(cmd, 3, buf, 3);
+	u8 cmd[3] = { FTS4_CMD_FB_REG_READ, 0, 0x60 };
+	int res = _touch_read_reg(cmd, sizeof(cmd), buf, 3);
 	if (!res)
 	{
 		// Get fw info.
 		cmd[1] = buf[2]; cmd[2] = buf[1];
-		res = touch_read_reg(cmd, 3, buf, 8);
+		res = _touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf));
 		if (!res)
 		{
 			fw->fw_id   = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4];
-			fw->ftb_ver = (buf[6] << 8) | buf[5];
+			fw->ftb_ver = (buf[6] <<  8) |  buf[5];
+			fw->fw_rev  = (buf[8] <<  8) |  buf[7];
 		}
-
-		cmd[2]++;
-		res = touch_read_reg(cmd, 3, buf, 8);
-		if (!res)
-			fw->fw_rev = (buf[7] << 8) | buf[6];
 	}
 
 	return res;
@@ -261,16 +252,17 @@ int touch_get_fw_info(touch_fw_info_t *fw)
 
 int touch_sys_reset()
 {
-	u8 cmd[3] = { 0, 0x28, 0x80 }; // System reset cmd.
+	u8 cmd[3] = { 0, FTS4_HW_REG_SYS_RESET, 0x80 }; // System reset cmd.
 	for (u8 retries = 0; retries < 3; retries++)
 	{
-		if (touch_command(STMFTS_WRITE_REG, cmd, 3))
+		if (_touch_command(FTS4_CMD_HW_REG_WRITE, cmd, 3))
 		{
 			msleep(10);
 			continue;
 		}
 		msleep(10);
-		if (touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20, NULL))
+
+		if (_touch_wait_event(FTS4_EV_CONTROLLER_READY, 0, 20, NULL))
 			continue;
 		else
 			return 0;
@@ -281,36 +273,25 @@ int touch_sys_reset()
 
 int touch_panel_ito_test(u8 *err)
 {
-	int res = 0;
+	// Check that touch IC is supported.
+	touch_info_t *info = touch_get_chip_info();
+	if (info->chip_id != FTS4_I2C_CHIP_ID || info->clone)
+		return 1;
 
 	// Reset touchscreen module.
 	if (touch_sys_reset())
-		return res;
+		return 1;
 
 	// Do ITO Production test.
-	u8 cmd[2] = { 1, 0 };
-	if (touch_command(STMFTS_ITO_CHECK, cmd, 2))
-		return res;
+	if (_touch_command(FTS4_CMD_ITO_CHECK, NULL, 0))
+		return 1;
 
-	u32 timer = get_tmr_ms() + 2000;
-	while (true)
+	u8 buf[6] = { 0 };
+	int res = _touch_wait_event(FTS4_EV_ERROR, FTS4_EV_ERROR_ITO_TEST, 2000, buf);
+	if (!res && err)
 	{
-		u8 tmp[8] = {0};
-		i2c_recv_buf_small(tmp, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_READ_ONE_EVENT);
-		if (tmp[1] == 0xF && tmp[2] == 0x5)
-		{
-			if (err)
-			{
-				err[0] = tmp[3];
-				err[1] = tmp[4];
-			}
-
-			res = 1;
-			break;
-		}
-
-		if (get_tmr_ms() > timer)
-			break;
+		err[0] = buf[0];
+		err[1] = buf[1];
 	}
 
 	// Reset touchscreen module.
@@ -321,20 +302,19 @@ int touch_panel_ito_test(u8 *err)
 
 int touch_get_fb_info(u8 *buf)
 {
-	u8 tmp[5];
-
-	u8 cmd[3] = { STMFTS_RW_FRAMEBUFFER_REG, 0, 0 };
+	u8 cmd[3] = { FTS4_CMD_FB_REG_READ, 0, 0 };
 	int res = 0;
 
-
 	for (u32 i = 0; i < 0x10000; i += 4)
 	{
 		if (!res)
 		{
 			cmd[1] = (i >> 8) & 0xFF;
 			cmd[2] = i & 0xFF;
-			memset(tmp, 0xCC, 5);
-			res = touch_read_reg(cmd, 3, tmp, 5);
+
+			u8 tmp[5];
+			memset(tmp, 0xCC, sizeof(tmp));
+			res = _touch_read_reg(cmd, sizeof(cmd), tmp, sizeof(tmp));
 			memcpy(&buf[i], tmp + 1, 4);
 		}
 	}
@@ -342,70 +322,97 @@ int touch_get_fb_info(u8 *buf)
 	return res;
 }
 
+int touch_switch_sense_mode(u8 mode, bool gis_6_2)
+{
+	// Set detection config.
+	u8 cmd[3] = { 1, 0x64, 0 };
+
+	switch (mode)
+	{
+	case FTS4_STYLUS_MODE:
+		cmd[2] = !gis_6_2 ? 0xC8 : 0xAD;
+		break;
+	case FTS4_FINGER_MODE:
+		cmd[2] = !gis_6_2 ? 0x8C : 0x79;
+		break;
+	}
+
+	if (_touch_command(FTS4_CMD_DETECTION_CONFIG, cmd, 3))
+		return 1;
+
+	// Sense mode.
+	cmd[0] = mode;
+
+	return _touch_command(FTS4_CMD_SWITCH_SENSE_MODE, cmd, 1);
+}
+
 int touch_sense_enable()
 {
 	// Switch sense mode and enable multi-touch sensing.
-	u8 cmd = STMFTS_FINGER_MODE;
-	if (touch_command(STMFTS_SWITCH_SENSE_MODE, &cmd, 1))
-		return 0;
+	u8 cmd = FTS4_FINGER_MODE;
+	if (_touch_command(FTS4_CMD_SWITCH_SENSE_MODE, &cmd, 1))
+		return 1;
 
-	if (touch_command(STMFTS_MS_MT_SENSE_ON, NULL, 0))
-		return 0;
+	if (_touch_command(FTS4_CMD_MS_MT_SENSE_ON, NULL, 0))
+		return 1;
 
-	if (touch_command(STMFTS_CLEAR_EVENT_STACK, NULL, 0))
-		return 0;
+	if (_touch_command(FTS4_CMD_CLEAR_EVENT_STACK, NULL, 0))
+		return 1;
 
-	return 1;
+	return 0;
 }
 
 int touch_execute_autotune()
 {
+	u8 buf[6] = { 0 };
+
 	// Reset touchscreen module.
 	if (touch_sys_reset())
-		return 0;
+		return 1;
 
 	// Trim low power oscillator.
-	if (touch_command(STMFTS_LP_TIMER_CALIB, NULL, 0))
-		return 0;
+	if (_touch_command(FTS4_CMD_LP_TIMER_CALIB, NULL, 0))
+		return 1;
+
 	msleep(200);
 
 	// Apply Mutual Sense Compensation tuning.
-	if (touch_command(STMFTS_MS_CX_TUNING, NULL, 0))
-		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_MS_CX_TUNING_DONE, 2000, NULL))
-		return 0;
+	if (_touch_command(FTS4_CMD_MS_CX_TUNING, NULL, 0))
+		return 1;
+	if (_touch_wait_event(FTS4_EV_STATUS, FTS4_EV_STATUS_MS_CX_TUNING_DONE, 2000, buf) || buf[0] || buf[1])
+		return 1;
 
 	// Apply Self Sense Compensation tuning.
-	if (touch_command(STMFTS_SS_CX_TUNING, NULL, 0))
-		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_SS_CX_TUNING_DONE, 2000, NULL))
-		return 0;
+	if (_touch_command(FTS4_CMD_SS_CX_TUNING, NULL, 0))
+		return 1;
+	if (_touch_wait_event(FTS4_EV_STATUS, FTS4_EV_STATUS_SS_CX_TUNING_DONE, 2000, buf) || buf[0] || buf[1])
+		return 1;
 
 	// Save Compensation data to EEPROM.
-	if (touch_command(STMFTS_SAVE_CX_TUNING, NULL, 0))
-		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_WRITE_CX_TUNE_DONE, 2000, NULL))
-		return 0;
+	if (_touch_command(FTS4_CMD_SAVE_CX_TUNING, NULL, 0))
+		return 1;
+	if (_touch_wait_event(FTS4_EV_STATUS, FTS4_EV_STATUS_WRITE_CX_TUNE_DONE, 2000, buf) || buf[0] || buf[1])
+		return 1;
 
 	return touch_sense_enable();
 }
 
 static int touch_init()
 {
+	// Check that touch IC is supported.
+	touch_info_t *info = touch_get_chip_info();
+	if (info->chip_id != FTS4_I2C_CHIP_ID)
+		return 1;
+
 	// Initialize touchscreen module.
 	if (touch_sys_reset())
-		return 0;
+		return 1;
 
 	return touch_sense_enable();
 }
 
 int touch_power_on()
 {
-	// Configure Touscreen and GCAsic shared GPIO.
-	PINMUX_AUX(PINMUX_AUX_CAM_I2C_SDA) = PINMUX_LPDR | PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 2;
-	PINMUX_AUX(PINMUX_AUX_CAM_I2C_SCL) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_TRISTATE | PINMUX_PULL_DOWN | 2; // Unused.
-	gpio_config(GPIO_PORT_S, GPIO_PIN_3, GPIO_MODE_GPIO); // GC detect.
-
 	// Configure touchscreen Touch Reset pin.
 	PINMUX_AUX(PINMUX_AUX_DAP4_SCLK) = PINMUX_PULL_DOWN | 1;
 	gpio_direction_output(GPIO_PORT_J, GPIO_PIN_7, GPIO_LOW);
@@ -426,13 +433,13 @@ int touch_power_on()
 	usleep(10000);
 
 	// Wait for the touchscreen module to get ready.
-	touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20, NULL);
+	_touch_wait_event(FTS4_EV_CONTROLLER_READY, 0, 20, NULL);
 
 	// Check for forced boot time calibration.
 	if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN))
 	{
 		u8 err[2];
-		if (touch_panel_ito_test(err))
+		if (!touch_panel_ito_test(err))
 			if (!err[0] && !err[1])
 				return touch_execute_autotune();
 	}
@@ -441,12 +448,12 @@ int touch_power_on()
 	u32 retries = 3;
 	while (retries)
 	{
-		if (touch_init())
-			return 1;
+		if (!touch_init())
+			return 0;
 		retries--;
 	}
 
-	return 0;
+	return 1;
 }
 
 void touch_power_off()

bdk/input/touch.h

@@ -2,7 +2,7 @@
  * Touch driver for Nintendo Switch's STM FingerTip S (4CD60D) touch controller
  *
  * Copyright (c) 2018 langerhans
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -22,92 +22,100 @@
 
 #include <utils/types.h>
 
-#define STMFTS_I2C_ADDR 0x49
+#define FTS4_I2C_ADDR 0x49
 
-/* I2C commands */
-#define STMFTS_READ_INFO               0x80
-#define STMFTS_READ_STATUS             0x84
-#define STMFTS_READ_ONE_EVENT          0x85
-#define STMFTS_READ_ALL_EVENT          0x86
-#define STMFTS_LATEST_EVENT            0x87
-#define STMFTS_SLEEP_IN                0x90
-#define STMFTS_SLEEP_OUT               0x91
-#define STMFTS_MS_MT_SENSE_OFF         0x92
-#define STMFTS_MS_MT_SENSE_ON          0x93
-#define STMFTS_SS_HOVER_SENSE_OFF      0x94
-#define STMFTS_SS_HOVER_SENSE_ON       0x95
-#define STMFTS_LP_TIMER_CALIB          0x97
-#define STMFTS_MS_KEY_SENSE_OFF        0x9A
-#define STMFTS_MS_KEY_SENSE_ON         0x9B
-#define STMFTS_SYSTEM_RESET            0xA0
-#define STMFTS_CLEAR_EVENT_STACK       0xA1
-#define STMFTS_FULL_FORCE_CALIBRATION  0xA2
-#define STMFTS_MS_CX_TUNING            0xA3
-#define STMFTS_SS_CX_TUNING            0xA4
-#define STMFTS_ITO_CHECK               0xA7
-#define STMFTS_RELEASEINFO             0xAA
-#define STMFTS_WRITE_REG               0xB6
-#define STMFTS_SWITCH_SENSE_MODE       0xC3
-#define STMFTS_NOISE_WRITE             0xC7
-#define STMFTS_NOISE_READ              0xC8
-#define STMFTS_RW_FRAMEBUFFER_REG      0xD0
-#define STMFTS_SAVE_CX_TUNING          0xFC
+#define FTS4_I2C_CHIP_ID 0x3670
 
-#define STMFTS_DETECTION_CONFIG        0xB0
-#define STMFTS_REQU_COMP_DATA          0xB8
-#define STMFTS_VENDOR                  0xCF
-#define STMFTS_FLASH_UNLOCK            0xF7
-#define STMFTS_FLASH_WRITE_64K         0xF8
-#define STMFTS_FLASH_STATUS            0xF9
-#define STMFTS_FLASH_OP                0xFA
-#define STMFTS_UNK5 0x62
+/* I2C commands. */
+#define FTS4_CMD_READ_INFO           0x80
+#define FTS4_CMD_READ_STATUS         0x84
+#define FTS4_CMD_READ_ONE_EVENT      0x85
+#define FTS4_CMD_READ_ALL_EVENT      0x86
+#define FTS4_CMD_LATEST_EVENT        0x87 // Clears event stack.
+#define FTS4_CMD_SLEEP_IN            0x90
+#define FTS4_CMD_SLEEP_OUT           0x91
+#define FTS4_CMD_MS_MT_SENSE_OFF     0x92
+#define FTS4_CMD_MS_MT_SENSE_ON      0x93
+#define FTS4_CMD_SS_HOVER_SENSE_OFF  0x94
+#define FTS4_CMD_SS_HOVER_SENSE_ON   0x95
+#define FTS4_CMD_LP_TIMER_CALIB      0x97
+#define FTS4_CMD_MS_KEY_SENSE_OFF    0x9A
+#define FTS4_CMD_MS_KEY_SENSE_ON     0x9B
+#define FTS4_CMD_SYSTEM_RESET        0xA0
+#define FTS4_CMD_CLEAR_EVENT_STACK   0xA1
+#define FTS4_CMD_FULL_FORCE_CALIB    0xA2
+#define FTS4_CMD_MS_CX_TUNING        0xA3
+#define FTS4_CMD_SS_CX_TUNING        0xA4
+#define FTS4_CMD_ITO_CHECK           0xA7
+#define FTS4_CMD_RELEASEINFO         0xAA
+#define FTS4_CMD_HW_REG_READ         0xB6                 // u16be address offset. Any size read.
+#define FTS4_CMD_HW_REG_WRITE        FTS4_CMD_HW_REG_READ // u16be address offset, bytes to write.
+#define FTS4_CMD_SWITCH_SENSE_MODE   0xC3
+#define FTS4_CMD_NOISE_WRITE         0xC7
+#define FTS4_CMD_NOISE_READ          0xC8
+#define FTS4_CMD_FB_REG_READ         0xD0
+#define FTS4_CMD_FB_REG_WRITE        FTS4_CMD_FB_REG_READ
+#define FTS4_CMD_SAVE_CX_TUNING      0xFC
 
-/* cmd parameters */
-#define STMFTS_VENDOR_GPIO_STATE       0x01
-#define STMFTS_VENDOR_SENSE_MODE       0x02
-#define STMFTS_STYLUS_MODE             0x00
-#define STMFTS_FINGER_MODE             0x01
-#define STMFTS_HOVER_MODE              0x02
+#define FTS4_CMD_DETECTION_CONFIG    0xB0
+#define FTS4_CMD_REQ_CX_DATA         0xB8
+#define FTS4_CMD_VENDOR              0xCF
+#define FTS4_CMD_FLASH_UNLOCK        0xF7
+#define FTS4_CMD_FLASH_WRITE_64K     0xF8
+#define FTS4_CMD_FLASH_STATUS        0xF9
+#define FTS4_CMD_FLASH_OP            0xFA
+#define FTS4_CMD_UNK_62 0x62
 
-/* events */
-#define STMFTS_EV_NO_EVENT             0x00
-#define STMFTS_EV_MULTI_TOUCH_DETECTED 0x02
-#define STMFTS_EV_MULTI_TOUCH_ENTER    0x03
-#define STMFTS_EV_MULTI_TOUCH_LEAVE    0x04
-#define STMFTS_EV_MULTI_TOUCH_MOTION   0x05
-#define STMFTS_EV_HOVER_ENTER          0x07
-#define STMFTS_EV_HOVER_LEAVE          0x08
-#define STMFTS_EV_HOVER_MOTION         0x09
-#define STMFTS_EV_KEY_STATUS           0x0e
-#define STMFTS_EV_ERROR                0x0f
-#define STMFTS_EV_NOISE_READ           0x17
-#define STMFTS_EV_NOISE_WRITE          0x18
-#define STMFTS_EV_VENDOR               0x20
+/* Command parameters. */
+#define FTS4_VENDOR_GPIO_STATE       0x01
+#define FTS4_VENDOR_SENSE_MODE       0x02
+#define FTS4_STYLUS_MODE             0x00
+#define FTS4_FINGER_MODE             0x01
+#define FTS4_HOVER_MODE              0x02
 
-#define STMFTS_EV_CONTROLLER_READY     0x10
-#define STMFTS_EV_STATUS               0x16
-#define STMFTS_EV_DEBUG                0xDB
+/* HW Registers */
+#define FTS4_HW_REG_CHIP_ID_INFO     0x0004
+#define FTS4_HW_REG_EVENT_COUNT      0x0023
+#define FTS4_HW_REG_SYS_RESET        0x0028
 
-#define STMFTS_EV_STATUS_MS_CX_TUNING_DONE  1
-#define STMFTS_EV_STATUS_SS_CX_TUNING_DONE  2
-#define STMFTS_EV_STATUS_WRITE_CX_TUNE_DONE 4
+/* FB Addresses */
+#define FTS4_FB_REG_FW_INFO_ADDRESS  0x0060
 
-/* multi touch related event masks */
-#define STMFTS_MASK_EVENT_ID   0x0F
-#define STMFTS_MASK_TOUCH_ID   0xF0
-#define STMFTS_MASK_LEFT_EVENT 0x0F
-#define STMFTS_MASK_X_MSB      0x0F
-#define STMFTS_MASK_Y_LSB      0xF0
+/* Events. */
+#define FTS4_EV_NO_EVENT             0x00
+#define FTS4_EV_MULTI_TOUCH_DETECTED 0x02
+#define FTS4_EV_MULTI_TOUCH_ENTER    0x03
+#define FTS4_EV_MULTI_TOUCH_LEAVE    0x04
+#define FTS4_EV_MULTI_TOUCH_MOTION   0x05
+#define FTS4_EV_HOVER_ENTER          0x07
+#define FTS4_EV_HOVER_LEAVE          0x08
+#define FTS4_EV_HOVER_MOTION         0x09
+#define FTS4_EV_KEY_STATUS           0x0E
+#define FTS4_EV_ERROR                0x0F
+#define FTS4_EV_CONTROLLER_READY     0x10
+#define FTS4_EV_STATUS               0x16
+#define FTS4_EV_NOISE_READ           0x17
+#define FTS4_EV_NOISE_WRITE          0x18
+#define FTS4_EV_VENDOR               0x20
+#define FTS4_EV_DEBUG                0xDB
 
-/* key related event masks */
-#define STMFTS_MASK_KEY_NO_TOUCH 0x00
-#define STMFTS_MASK_KEY_MENU     0x01
-#define STMFTS_MASK_KEY_BACK     0x02
+/* FTS4_EV_STATUS Events. */
+#define FTS4_EV_STATUS_MS_CX_TUNING_DONE  0x01
+#define FTS4_EV_STATUS_SS_CX_TUNING_DONE  0x02
+#define FTS4_EV_STATUS_WRITE_CX_TUNE_DONE 0x04
 
-#define STMFTS_EVENT_SIZE     8
-#define STMFTS_STACK_DEPTH   32
-#define STMFTS_DATA_MAX_SIZE (STMFTS_EVENT_SIZE * STMFTS_STACK_DEPTH)
-#define STMFTS_MAX_FINGERS   10
+#define FTS4_EV_ERROR_ITO_TEST            0x05
+
+/* Multi touch related event masks. */
+#define FTS4_MASK_EVENT_ID   0x0F
+#define FTS4_MASK_TOUCH_ID   0xF0
+#define FTS4_MASK_X_MSB      0x0F
+#define FTS4_MASK_Y_LSB      0xF0
+
+#define FTS4_EVENT_SIZE     8
+#define FTS4_STACK_DEPTH   32 // Actual 128.
+#define FTS4_DATA_MAX_SIZE (FTS4_EVENT_SIZE * FTS4_STACK_DEPTH)
+#define FTS4_MAX_FINGERS   10
 
 typedef enum _touch_ito_error {
 	ITO_NO_ERROR = 0,
@@ -130,15 +138,13 @@ typedef enum _touch_ito_error {
 	ITO_MAX_ERR_REACHED = 0xFF
 } touch_ito_error;
 
-typedef struct _touch_event {
-	u8   raw[8];
-	u16  type; // Event type.
-	u16  x;    // Horizontal coordinates.
-	u16  y;    // Vertical coordinates.
-	u32  z;
-	u8   fingers;
+typedef struct _touch_event_t {
+	u8   raw[FTS4_EVENT_SIZE];
+	u16  x, y; // Coordinates.
+	u32  z;    // Orientation.
 	bool touch;
-} touch_event;
+	int  finger;
+} touch_event_t;
 
 typedef struct _touch_panel_info_t
 {
@@ -149,12 +155,13 @@ typedef struct _touch_panel_info_t
 	char *vendor;
 } touch_panel_info_t;
 
-typedef struct _touch_info {
-	u16 chip_id;
-	u16 fw_ver;
-	u16 config_id;
-	u16 config_ver;
-} touch_info;
+typedef struct _touch_info_t {
+	u16  chip_id;
+	u16  fw_ver;
+	u16  config_id;
+	u16  config_ver;
+	bool clone;
+} touch_info_t;
 
 typedef struct _touch_fw_info_t {
 	u32 fw_id;
@@ -162,15 +169,16 @@ typedef struct _touch_fw_info_t {
 	u16 fw_rev;
 } touch_fw_info_t;
 
-void touch_poll(touch_event *event);
-touch_event touch_poll_wait();
+int touch_poll(touch_event_t *event);
+touch_info_t *touch_get_chip_info();
 touch_panel_info_t *touch_get_panel_vendor();
 int touch_get_fw_info(touch_fw_info_t *fw);
-touch_info touch_get_info();
+int touch_get_event_count();
 int touch_panel_ito_test(u8 *err);
 int touch_execute_autotune();
+int touch_switch_sense_mode(u8 mode, bool gis_6_2);
 int touch_sense_enable();
 int touch_power_on();
 void touch_power_off();
 
-#endif /* __TOUCH_H_ */
+#endif /* __TOUCH_H_ */

bdk/libs/lv_conf.h

@@ -346,7 +346,7 @@
 #define USE_LV_KB       0
 
 /*Check box (dependencies: lv_btn, lv_label)*/
-#define USE_LV_CB       1
+#define USE_LV_CB       0
 
 /*List (dependencies: lv_page, lv_btn, lv_label, (lv_img optionally for icons ))*/
 #define USE_LV_LIST     1
@@ -370,7 +370,7 @@
 #define USE_LV_SLIDER    1
 
 /*Switch (dependencies: lv_slider)*/
-#define USE_LV_SW        1
+#define USE_LV_SW        0
 
 #endif /*LV_CONF_H*/
 

bdk/libs/lvgl/lv_objx/lv_line.c

@@ -1,3 +1,19 @@
+/*
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
 /**
  * @file lv_line.c
  *

bdk/libs/lvgl/lv_objx/lv_slider.c

@@ -1,3 +1,18 @@
+/*
+ * Copyright (c) 2026 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
 
 /**
  * @file lv_slider.c
@@ -437,16 +452,17 @@ static lv_res_t lv_slider_signal(lv_obj_t * slider, lv_signal_t sign, void * par
         lv_indev_get_point(param, &p);
         int16_t tmp = 0;
         if(w > h) {
-            lv_coord_t knob_w = h;
-            p.x -= slider->coords.x1 + h / 2;    /*Modify the point to shift with half knob (important on the start and end)*/
-            tmp = (int32_t)((int32_t) p.x * (ext->bar.max_value - ext->bar.min_value + 1)) / (w - knob_w);
-            tmp += ext->bar.min_value;
+			lv_coord_t knob_w = h;
+			lv_coord_t offset = (ext->knob_in == 0) ? w : w - knob_w;
+			p.x -= slider->coords.x1 + ((ext->knob_in == 0) ? 0 : knob_w / 2);
+			tmp = ((int32_t)p.x * (ext->bar.max_value - ext->bar.min_value) + offset / 2) / offset;
         } else {
-            lv_coord_t knob_h = w;
-            p.y -= slider->coords.y1 + w / 2;    /*Modify the point to shift with half knob (important on the start and end)*/
-            tmp = (int32_t)((int32_t) p.y * (ext->bar.max_value - ext->bar.min_value + 1)) / (h - knob_h);
-            tmp = ext->bar.max_value - tmp;     /*Invert the value: smaller value means higher y*/
+			lv_coord_t knob_h = w;
+			lv_coord_t offset = (ext->knob_in == 0) ? h : h - knob_h;
+			p.y -= slider->coords.y1 + ((ext->knob_in == 0) ? 0 : knob_h / 2);
+			tmp = ((int32_t)p.y * (ext->bar.max_value - ext->bar.min_value) + offset / 2) / offset;
         }
+		tmp += ext->bar.min_value;
 
         if(tmp < ext->bar.min_value) tmp = ext->bar.min_value;
         else if(tmp > ext->bar.max_value) tmp = ext->bar.max_value;

bdk/libs/lvgl/lv_themes/lv_theme.h

@@ -82,13 +82,6 @@ typedef struct {
     } label;
 #endif
 
-#if USE_LV_IMG != 0
-    struct {
-        lv_style_t *light;
-        lv_style_t *dark;
-    } img;
-#endif
-
 #if USE_LV_LINE != 0
     struct {
         lv_style_t *decor;

bdk/libs/lvgl/lv_themes/lv_theme_hekate.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -25,22 +25,27 @@
  *      DEFINES
  *********************/
 #define DEF_RADIUS             4
-#define COLOR_SHADOW_LIGHT     LV_COLOR_HEX(0xAAAAAA)
-#define COLOR_SHADOW_DARK      LV_COLOR_HEX(0x1F1F1F)
-#define COLOR_HOS_TURQUOISE    (lv_color_hsv_to_rgb(_hue, 100, 100)) // 0x00FFC9
-#define COLOR_HOS_TEAL_LIGHTER (lv_color_hsv_to_rgb(_hue, 100,  93)) // 0x00EDBA
-#define COLOR_HOS_TEAL_LIGHT   (lv_color_hsv_to_rgb(_hue, 100,  72)) // 0x00B78F
-#define COLOR_HOS_TEAL         (lv_color_hsv_to_rgb(_hue, 100,  64)) // 0x00A273
+
+#define COLOR_HOS_TURQUOISE    (_hue ? lv_color_hsv_to_rgb(_hue, 100, 100) : lv_color_hsv_to_rgb(53, 8, 90)) // 0x00FFC9
+#define COLOR_HOS_TEAL_LIGHTER (_hue ? lv_color_hsv_to_rgb(_hue, 100,  93) : lv_color_hsv_to_rgb(53, 8, 81)) // 0x00EDBA
+#define COLOR_HOS_TEAL_LIGHT   (_hue ? lv_color_hsv_to_rgb(_hue, 100,  72) : lv_color_hsv_to_rgb(53, 8, 65)) // 0x00B78F
+#define COLOR_HOS_TEAL         (_hue ? lv_color_hsv_to_rgb(_hue, 100,  64) : lv_color_hsv_to_rgb(53, 8, 58)) // 0x00A273
 #define COLOR_HOS_ORANGE       LV_COLOR_HEX(0xFF5500)
 #define COLOR_HOS_TXT_WHITE    LV_COLOR_HEX(0xFBFBFB)
 
-#define COLOR_BG_DARKER        LV_COLOR_HEX(theme_bg_color ? (theme_bg_color - 0x121212) : 0x0B0B0B) // 0x1B1B1B.
 #define COLOR_BG_DARK          LV_COLOR_HEX(theme_bg_color ? (theme_bg_color - 0x0B0B0B) : 0x121212) // 0x222222.
 #define COLOR_BG               LV_COLOR_HEX(theme_bg_color)                                          // 0x2D2D2D.
 #define COLOR_BG_LIGHT         LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x101010) : 0x2D2D2D) // 0x3D3D3D.
 #define COLOR_BG_LIGHTER       LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x191919) : 0x363636) // 0x464646.
-#define COLOR_LIGHT_BORDER     LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x202020) : 0x3D3D3D) // 0x4D4D4D.
 
+#define COLOR_INACTIVE         LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x171717) : 0x343434) // 0x444444.
+#define COLOR_BAR              LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x202020) : 0x3D3D3D) // 0x4D4D4D.
+#define COLOR_PRESS            LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x232323) : 0x404040) // 0x505050.
+#define COLOR_LINE             LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x383838) : 0x555555) // 0x656565.
+
+#define COLOR_SHADOW_LIGHT     LV_COLOR_HEX(0xAAAAAA)
+#define COLOR_SHADOW           LV_COLOR_HEX(theme_bg_color ? theme_bg_color : 0x181818) // 0x2D2D2D.
+#define COLOR_SHADOW_DARK      LV_COLOR_HEX(theme_bg_color ? 0x1F1F1F : 0x0A0A0A)
 
 /**********************
  *      TYPEDEFS
@@ -92,9 +97,9 @@ static void basic_init(void)
 	lv_style_copy(&panel, &def);
 	panel.body.radius = DEF_RADIUS;
 	panel.body.main_color = COLOR_BG;
-	panel.body.grad_color = COLOR_BG;
+	panel.body.grad_color = panel.body.main_color;
 	panel.body.border.width = 1;
-	panel.body.border.color = COLOR_LIGHT_BORDER;
+	panel.body.border.color = COLOR_BAR;
 	panel.body.border.opa = LV_OPA_COVER;
 	panel.body.shadow.color = COLOR_SHADOW_LIGHT;
 	panel.body.shadow.type = LV_SHADOW_BOTTOM;
@@ -106,7 +111,7 @@ static void basic_init(void)
 
 	lv_style_copy(&sb, &def);
 	sb.body.main_color = LV_COLOR_BLACK;
-	sb.body.grad_color = LV_COLOR_BLACK;
+	sb.body.grad_color = sb.body.grad_color;
 	sb.body.opa = LV_OPA_40;
 	sb.body.padding.hor = LV_DPI / 25;
 
@@ -147,7 +152,7 @@ static void btn_init(void)
 	//rel.text.color = COLOR_HOS_TXT_WHITE;
 
 	lv_style_copy(&pr, &rel);
-	pr.body.main_color = LV_COLOR_HEX(0x505050);
+	pr.body.main_color = COLOR_PRESS;
 	pr.body.grad_color = pr.body.main_color;
 	pr.body.shadow.width = 0;
 	pr.body.border.color = COLOR_HOS_TEAL_LIGHTER;
@@ -159,7 +164,7 @@ static void btn_init(void)
 	tgl_rel.body.border.width = 4;
 
 	lv_style_copy(&tgl_pr, &tgl_rel);
-	tgl_pr.body.main_color = LV_COLOR_HEX(0x505050);
+	tgl_pr.body.main_color = COLOR_PRESS;
 	tgl_pr.body.grad_color = tgl_pr.body.main_color;
 	tgl_pr.text.color = COLOR_HOS_TURQUOISE;
 	tgl_pr.body.shadow.width = 0;
@@ -201,30 +206,12 @@ static void label_init(void)
 #endif
 }
 
-static void img_init(void)
-{
-#if USE_LV_IMG != 0
-	static lv_style_t img_light, img_dark;
-	lv_style_copy(&img_light, &def);
-	img_light.image.color = LV_COLOR_WHITE;
-	img_light.image.intense = LV_OPA_80;
-
-	lv_style_copy(&img_dark, &def);
-	img_dark.image.color = COLOR_BG_DARKER;
-	img_dark.image.intense = LV_OPA_80;
-
-
-	theme.img.light = &def;
-	theme.img.dark = &def;
-#endif
-}
-
 static void line_init(void)
 {
 #if USE_LV_LINE != 0
 	static lv_style_t line;
 	lv_style_copy(&line, &def);
-	line.line.color = LV_COLOR_HEX(0x656565);
+	line.line.color = COLOR_LINE;
 	theme.line.decor = &line;
 #endif
 }
@@ -239,7 +226,7 @@ static void led_init(void)
 	led.body.border.width = LV_DPI / 30;
 	led.body.border.opa = LV_OPA_30;
 	led.body.main_color = lv_color_hsv_to_rgb(_hue, 100, 100);
-	led.body.grad_color = lv_color_hsv_to_rgb(_hue, 100, 100);
+	led.body.grad_color = led.body.main_color;
 	led.body.border.color = lv_color_hsv_to_rgb(_hue, 60, 60);
 	led.body.shadow.color = lv_color_hsv_to_rgb(_hue, 100, 100);
 
@@ -253,7 +240,7 @@ static void bar_init(void)
 	static lv_style_t bar_bg, bar_indic;
 
 	lv_style_copy(&bar_bg, &def);
-	bar_bg.body.main_color = COLOR_LIGHT_BORDER;
+	bar_bg.body.main_color = COLOR_BAR;
 	bar_bg.body.grad_color = bar_bg.body.main_color;
 	bar_bg.body.radius = 3;
 	bar_bg.body.border.width = 0;
@@ -402,7 +389,7 @@ static void calendar_init(void)
 	static lv_style_t week_box;
 	lv_style_copy(&week_box, &def);
 	week_box.body.main_color = lv_color_hsv_to_rgb(_hue, 40, 100);
-	week_box.body.grad_color = lv_color_hsv_to_rgb(_hue, 40, 100);
+	week_box.body.grad_color = week_box.body.main_color;
 	week_box.body.padding.ver = LV_DPI / 20;
 	week_box.body.padding.hor = theme.panel->body.padding.hor;
 	week_box.body.border.color = theme.panel->body.border.color;
@@ -413,7 +400,7 @@ static void calendar_init(void)
 	static lv_style_t today_box;
 	lv_style_copy(&today_box, &def);
 	today_box.body.main_color = LV_COLOR_WHITE;
-	today_box.body.grad_color = LV_COLOR_WHITE;
+	today_box.body.grad_color = today_box.body.main_color;
 	today_box.body.padding.ver = LV_DPI / 20;
 	today_box.body.radius = 0;
 
@@ -541,7 +528,7 @@ static void mbox_init(void)
 	lv_style_copy(&bg, theme.panel);
 	bg.body.main_color = COLOR_BG_LIGHTER;
 	bg.body.grad_color = bg.body.main_color;
-	bg.body.shadow.color = COLOR_BG;
+	bg.body.shadow.color = COLOR_SHADOW;
 	bg.body.shadow.type = LV_SHADOW_FULL;
 	bg.body.shadow.width = 8;
 
@@ -617,13 +604,13 @@ static void list_init(void)
 	rel.body.padding.hor = LV_DPI / 8;
 	rel.body.padding.ver = LV_DPI / 6;
 	rel.body.radius = 0;
-	rel.body.border.color = LV_COLOR_HEX(0x444444);
+	rel.body.border.color = COLOR_INACTIVE;
 	rel.body.border.width = 1;
 	rel.body.border.part = LV_BORDER_BOTTOM;
 
 	lv_style_copy(&pr, &rel);
 	pr.glass = 0;
-	pr.body.main_color = LV_COLOR_HEX(0x505050);
+	pr.body.main_color = COLOR_PRESS;
 	pr.body.grad_color = pr.body.main_color;
 	//pr.body.border.width = 1;
 	pr.body.empty = 0;
@@ -637,7 +624,7 @@ static void list_init(void)
 	tgl_rel.text.color = COLOR_HOS_TEAL_LIGHTER;
 
 	lv_style_copy(&tgl_pr, &tgl_rel);
-	tgl_pr.body.main_color = LV_COLOR_HEX(0x505050);
+	tgl_pr.body.main_color = COLOR_PRESS;
 	tgl_pr.body.grad_color = tgl_pr.body.main_color;
 	tgl_pr.body.border.width = 0;
 
@@ -692,7 +679,7 @@ static void roller_init(void)
 	roller_bg.text.line_space = LV_DPI / 8;
 	roller_bg.text.font = _font;
 	roller_bg.glass = 0;
-	roller_bg.text.color = LV_COLOR_HEX(0x444444);
+	roller_bg.text.color = COLOR_INACTIVE;
 
 	lv_style_copy(&roller_sel, &roller_bg);
 	roller_sel.text.color = COLOR_HOS_TURQUOISE;
@@ -866,7 +853,6 @@ lv_theme_t * lv_theme_hekate_init(uint32_t bg_color, uint16_t hue, lv_font_t * f
 	cont_init();
 	btn_init();
 	label_init();
-	img_init();
 	line_init();
 	led_init();
 	bar_init();

bdk/libs/lvgl/lv_themes/lv_theme_hekate.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -35,14 +35,17 @@ extern "C" {
 /*********************
  *      DEFINES
  *********************/
-#define COLOR_HOS_BG_BASE_DEFAULT 0x1B1B1B
-#define COLOR_HOS_BG_BASE_BLACK   0x000000
+#define COLOR_BG_BASE_MIN      0x0B0B0B
+#define COLOR_BG_BASE_MAX      0xC7C7C7
 
-#define COLOR_HOS_BG_DARKER    0x1B1B1B
-#define COLOR_HOS_BG_DARK      0x222222
-#define COLOR_HOS_BG           0x2D2D2D
-#define COLOR_HOS_BG_LIGHT     0x3D3D3D
-#define COLOR_HOS_LIGHT_BORDER 0x4D4D4D
+#define COLOR_HOS_BG_DARKER    LV_COLOR_HEX(0x1B1B1B)
+#define COLOR_HOS_BG_DARK      LV_COLOR_HEX(0x222222)
+#define COLOR_HOS_BG           LV_COLOR_HEX(0x2D2D2D)
+#define COLOR_HOS_BG_RGB       0x2D2D2D
+#define COLOR_HOS_BG_LIGHT     LV_COLOR_HEX(0x3D3D3D)
+#define COLOR_HOS_BG_LIGHTER   LV_COLOR_HEX(0x4D4D4D)
+
+#define COLOR_HOS_TURQUOISE_EX(hue) (hue ? lv_color_hsv_to_rgb(hue, 100, 100) : lv_color_hsv_to_rgb(53, 8, 90)) // 0x00FFC9
 
 /**********************
  *      TYPEDEFS

bdk/mem/heap.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2025 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,

bdk/mem/mc.c

@@ -107,13 +107,13 @@ void mc_config_carveout_hos()
 }
 
 // SDMMC, TSEC, XUSB and probably more need it to access < DRAM_START.
-void mc_enable_ahb_redirect()
+void mc_enable_ahb_redirect(u32 offset)
 {
 	// Bypass ARC clock gating.
 	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19);
 	//MC(MC_IRAM_REG_CTRL) &= ~BIT(0);
 	MC(MC_IRAM_BOM) = IRAM_BASE;
-	MC(MC_IRAM_TOM) = DRAM_START; // Default is only IRAM: 0x4003F000.
+	MC(MC_IRAM_TOM) = DRAM_START - offset; // Default is only IRAM: 0x4003F000.
 }
 
 void mc_disable_ahb_redirect()
@@ -149,9 +149,6 @@ void mc_enable()
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
 	usleep(5);
 
-#ifdef BDK_MC_ENABLE_AHB_REDIRECT
-	mc_enable_ahb_redirect();
-#else
-	mc_disable_ahb_redirect();
-#endif
+	// Enable redirection by default.
+	mc_enable_ahb_redirect(1);
 }

bdk/mem/mc.h

@@ -22,7 +22,7 @@
 
 void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock);
 void mc_config_carveout_hos();
-void mc_enable_ahb_redirect();
+void mc_enable_ahb_redirect(u32 offset);
 void mc_disable_ahb_redirect();
 bool mc_client_has_access(void *address);
 void mc_enable();

bdk/mem/minerva.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2025 CTCaer
+ * Copyright (c) 2019-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -37,7 +37,7 @@ static bool no_table = false;
 static mtc_config_t *mtc_cfg = NULL;
 void (*mtc_call)(mtc_config_t *mtc_cfg, void *);
 
-u32 minerva_init(minerva_str_t *mtc_str)
+int minerva_init(minerva_str_t *mtc_str)
 {
 	mtc_call = NULL;
 	mtc_cfg  = (mtc_config_t *)&mtc_str->mtc_cfg;
@@ -52,8 +52,7 @@ u32 minerva_init(minerva_str_t *mtc_str)
 	{
 		// Load library and do a periodic training if needed.
 		mtc_cfg->train_mode = OP_PERIODIC_TRAIN;
-		u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
-		mtc_call = (void *)ep_addr;
+		mtc_call = (void *)ianos_static_module("bootloader/sys/libsys_minerva.bso", (void *)mtc_cfg);
 
 		return !mtc_call ? 1 : 0;
 	}
@@ -67,7 +66,7 @@ u32 minerva_init(minerva_str_t *mtc_str)
 		mtc_tmp.init_done  = !no_table ? MTC_NEW_MAGIC : MTC_IRB_MAGIC;
 
 		// Load library and get table.
-		u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)&mtc_tmp);
+		u32 ep_addr = ianos_static_module("bootloader/sys/libsys_minerva.bso", (void *)&mtc_tmp);
 
 		// Ensure that Minerva is initialized.
 		if (mtc_tmp.init_done == MTC_INIT_MAGIC)
@@ -88,7 +87,7 @@ u32 minerva_init(minerva_str_t *mtc_str)
 	mtc_cfg->sdram_id   = fuse_read_dramid(false);
 	mtc_cfg->init_done  = !no_table ? MTC_NEW_MAGIC : MTC_IRB_MAGIC;
 
-	u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
+	u32 ep_addr = ianos_static_module("bootloader/sys/libsys_minerva.bso", (void *)mtc_cfg);
 
 	// Ensure that Minerva is initialized.
 	if (mtc_cfg->init_done == MTC_INIT_MAGIC)

bdk/mem/minerva.h

@@ -72,7 +72,7 @@ typedef enum
 } minerva_freq_t;
 
 extern void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
-u32  minerva_init(minerva_str_t *mtc_str);
+int  minerva_init(minerva_str_t *mtc_str);
 void minerva_deinit();
 void minerva_change_freq(minerva_freq_t freq);
 void minerva_sdmmc_la_program(void *table, bool t210b01);

bdk/mem/sdram.c

@@ -85,9 +85,9 @@ static const u8 dram_encoding_t210b01[] = {
 #include "sdram_config.inl"
 #include "sdram_config_t210b01.inl"
 
-static bool _sdram_wait_emc_status(u32 reg_offset, u32 bit_mask, bool updated_state, s32 emc_channel)
+static int _sdram_wait_emc_status(u32 reg_offset, u32 bit_mask, bool updated_state, s32 emc_channel)
 {
-	bool err = true;
+	int err = 1;
 
 	for (s32 i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++)
 	{
@@ -98,13 +98,13 @@ static bool _sdram_wait_emc_status(u32 reg_offset, u32 bit_mask, bool updated_st
 
 			if (((EMC_CH1(reg_offset) & bit_mask) != 0) == updated_state)
 			{
-				err = false;
+				err = 0;
 				break;
 			}
 		}
 		else if (((EMC(reg_offset) & bit_mask) != 0) == updated_state)
 		{
-			err = false;
+			err = 0;
 			break;
 		}
 		usleep(1);

bdk/mem/sdram_config.inl

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020-2025 CTCaer
+ * Copyright (c) 2020-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -497,7 +497,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	.mc_emem_adr_cfg_bank_mask2                      = 0x4B9C1000,
 	/*
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
-	 * size (in KBytes)
+	 * size (in MBytes)
 	 */
 	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.
 
@@ -685,5 +685,7 @@ static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210[] = {
 	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0)         }, // 1024MB Chip 0 density.
 	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1)         }, // 1024MB Chip 1 density.
 	{ 0x00002000, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_cfg)                  }, // 8GB total density. Max 8GB.
+	{ 0x00000007, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_arb_timing_rfcpb)     },
+	{ 0x72A30504, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_arb_misc0)            },
 };
 #undef DCFG_OFFSET_OF

bdk/mem/sdram_config_t210b01.inl

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2025 CTCaer
+ * Copyright (c) 2020-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -550,7 +550,7 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
 	.mc_emem_adr_cfg_bank_mask2                      = 0x4B9C1000,
 	/*
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
-	 * size (in KBytes)
+	 * size (in MBytes)
 	 */
 	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.
 

bdk/mem/smmu.c

@@ -156,6 +156,7 @@ void smmu_disable()
 	smmu_enable_payload[SMMU_PAYLOAD_EN_SHIFT] = SMMU_PAYLOAD_EN_SET;
 
 	smmu_enabled = false;
+	smmu_heap    = (void *)SMMU_HEAP_ADDR;
 }
 
 void smmu_reset_heap()
@@ -163,7 +164,7 @@ void smmu_reset_heap()
 	smmu_heap = (void *)SMMU_HEAP_ADDR;
 }
 
-void *smmu_init_domain(u32 dev_base, u32 asid)
+void *smmu_domain_init(u32 dev_base, u32 asid)
 {
 	void *ptb = _smmu_pdir_alloc();
 
@@ -178,7 +179,7 @@ void *smmu_init_domain(u32 dev_base, u32 asid)
 	return ptb;
 }
 
-void smmu_deinit_domain(u32 dev_base, u32 asid)
+void smmu_domain_deinit(u32 dev_base, u32 asid)
 {
 	MC(MC_SMMU_PTB_ASID) = asid;
 	MC(MC_SMMU_PTB_DATA) = 0;

bdk/mem/smmu.h

@@ -15,9 +15,11 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <assert.h>
+#ifndef _SMMU_H_
+#define _SMMU_H_
 
 #include <utils/types.h>
+#include <assert.h>
 
 #define MC_SMMU_AVPC_ASID            0x23C
 #define MC_SMMU_TSEC_ASID            0x294
@@ -65,8 +67,10 @@ void  smmu_init();
 void  smmu_enable();
 void  smmu_disable();
 void  smmu_reset_heap();
-void *smmu_init_domain(u32 dev_base, u32 asid);
-void  smmu_deinit_domain(u32 dev_base, u32 asid);
+void *smmu_domain_init(u32 dev_base, u32 asid);
+void  smmu_domain_deinit(u32 dev_base, u32 asid);
 void  smmu_domain_bypass(u32 dev_base, bool bypass);
 void  smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr);
 void  smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr);
+
+#endif

bdk/memory_map.h

@@ -29,6 +29,7 @@
 #define SECMON_MIN_START  0x4002B000 // Minimum reserved address for secmon.
 
 #define SDRAM_PARAMS_ADDR 0x40030000 // SDRAM extraction buffer during sdram init.
+#define  SDRAM_PARAMS_SZ       0x838
 
 /* start.S / exception_handlers.S */
 #define SYS_STACK_TOP_INIT 0x4003FF00
@@ -36,7 +37,7 @@
 #define IRQ_STACK_TOP      0x40040000
 #define IPL_RELOC_ADDR     0x4003FF00
 #define  IPL_RELOC_SZ            0x10
-#define EXCP_STORAGE_ADDR  0x4003FFF0
+#define EXCP_STORAGE_ADDR  0x4003FF10
 #define  EXCP_STORAGE_SZ         0x10
 
 /* --- DRAM START --- */
@@ -71,9 +72,9 @@
 //#define DRAM_LIB_ADDR    0xE0000000
 /* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading.
 
-// SDMMC DMA buffers 1
-#define SDMMC_UPPER_BUFFER 0xE5000000
-#define  SDMMC_UP_BUF_SZ      SZ_128M
+// SDMMC DMA buffer. Used for unaligned DMA buffer address.
+#define SDMMC_ALT_DMA_BUFFER 0xE5000000
+#define  SDMMC_ALT_DMA_BUF_SZ   SZ_128M
 
 // Nyx buffers. !Do not change!
 #define NYX_STORAGE_ADDR 0xED000000
@@ -81,10 +82,10 @@
 #define NYX_RES_ADDR     0xEE000000
 #define  NYX_RES_SZ          SZ_16M
 
-// SDMMC DMA buffers 2
-#define SDXC_BUF_ALIGNED   0xEF000000
-#define MIXD_BUF_ALIGNED   0xF0000000
-#define EMMC_BUF_ALIGNED   MIXD_BUF_ALIGNED
+// SDMMC Application DMA aligned buffers.
+#define SDXC_BUF_ALIGNED   0xEF000000 // Also used by UMS.
+#define EMMC_BUF_ALIGNED   0xF0000000
+#define MIXD_BUF_ALIGNED   EMMC_BUF_ALIGNED
 #define  SDMMC_DMA_BUF_SZ      SZ_16M // 4MB currently used.
 
 // Nyx LvGL buffers.

bdk/module.h

@@ -1,6 +1,7 @@
 /*
  * Common Module Header
  * Copyright (c) 2018 M4xw
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -21,7 +22,7 @@
 #include <stddef.h>
 #include <mem/heap.h>
 
-#define IANOS_EXT0 0x304E4149
+#define IANOS_EXT1 0x314E4149
 
 // Module Callback
 typedef void (*cbMainModule_t)(const char *s);
@@ -31,16 +32,15 @@ typedef int  (*reg_voltage_set_t)(u32, u32);
 
 typedef struct _bdkParams_t
 {
-	void *gfxCon;
-	void *gfxCtx;
-	heap_t *sharedHeap;
+	void *gfx_con;
+	void *gfx_ctx;
+	heap_t *heap;
 	memcpy_t memcpy;
 	memset_t memset;
 	u32 extension_magic;
-	reg_voltage_set_t reg_voltage_set;
-} *bdkParams_t;
+} bdk_params_t;
 
-// Module Entrypoint
-typedef void (*moduleEntrypoint_t)(void *, bdkParams_t);
+// Module Caller.
+typedef void (*moduleEntrypoint)(void *, bdk_params_t *);
 
 #endif

bdk/power/bm92t36.c

@@ -1,7 +1,7 @@
 /*
  * USB-PD driver for Nintendo Switch's TI BM92T36
  *
- * Copyright (c) 2020-2025 CTCaer
+ * Copyright (c) 2020-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -55,9 +55,14 @@
 #define STATUS1_INSERT      BIT(7)  // Cable inserted.
 
 #define VER_36     0x36
-#define MAX_ROHM  0x4B5
+#define MAN_ROHM  0x4B5
 #define DEV_BM92T 0x3B0
 
+#define PDO_TYPE_FIXED  0
+#define PDO_TYPE_BATT   1
+#define PDO_TYPE_VAR    2
+#define PDO_TYPE_APDO   3
+
 typedef struct _pd_object_t {
 	unsigned int amp:10;
 	unsigned int volt:10;
@@ -84,13 +89,13 @@ int bm92t36_get_version(u32 *value)
 	if (value)
 		*value = (dev << 16) | version;
 
-	if (version == VER_36 && man == MAX_ROHM && dev == DEV_BM92T)
+	if (version == VER_36 && man == MAN_ROHM && dev == DEV_BM92T)
 	 	return 0;
 	else
-		return -1;
+		return 1;
 }
 
-void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd)
+void bm92t36_get_source_info(bool *inserted, usb_pd_objects_t *usb_pd)
 {
 	u8 buf[32];
 	pd_object_t pdos[7];
@@ -112,15 +117,22 @@ void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd)
 		if (usb_pd->pdo_no > 7)
 			usb_pd->pdo_no = 7;
 
+		u32 idx = 0;
 		for (u32 i = 0; i < usb_pd->pdo_no; i++)
 		{
-			usb_pd->pdos[i].amperage = pdos[i].amp * 10;
-			usb_pd->pdos[i].voltage = (pdos[i].volt * 50) / 1000;
+			// Parse fixed type pdos only.
+			if (pdos[i].type != PDO_TYPE_FIXED)
+				continue;
+
+			usb_pd->pdos[idx].amperage =  pdos[i].amp  * 10;
+			usb_pd->pdos[idx].voltage  = (pdos[i].volt * 50) / 1000;
+			idx++;
 		}
+		usb_pd->pdo_no = idx;
 
 		_bm92t36_read_reg(buf, 5, CURRENT_PDO_REG);
 		memcpy(pdos, &buf[1], 4);
-		usb_pd->selected_pdo.amperage = pdos[0].amp * 10;
-		usb_pd->selected_pdo.voltage = (pdos[0].volt * 50) / 1000;
+		usb_pd->selected_pdo.amperage =  pdos[0].amp  * 10;
+		usb_pd->selected_pdo.voltage  = (pdos[0].volt * 50) / 1000;
 	}
 }

bdk/power/bm92t36.h

@@ -37,6 +37,6 @@ typedef struct _usb_pd_objects_t
 } usb_pd_objects_t;
 
 int  bm92t36_get_version(u32 *value);
-void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd);
+void bm92t36_get_source_info(bool *inserted, usb_pd_objects_t *usb_pd);
 
 #endif

bdk/power/bq24193.c

@@ -34,7 +34,7 @@ int bq24193_get_version(u32 *value)
 	if (data == 0x2F)
 		return 0;
 	else
-		return -1;
+		return 1;
 }
 
 int bq24193_get_property(enum BQ24193_reg_prop prop, int *value)
@@ -162,7 +162,7 @@ int bq24193_get_property(enum BQ24193_reg_prop prop, int *value)
 		*value = (data & BQ24193_VENDORPART_PN_MASK) >> 3;
 		break;
 	default:
-		return -1;
+		return 1;
 	}
 	return 0;
 }

bdk/power/max17050.c

@@ -69,7 +69,7 @@ int max17050_get_version(u32 *value)
 	if (data == 0x00AC)
 		return 0;
 	else
-		return -1;
+		return 1;
 }
 
 int max17050_get_property(enum MAX17050_reg reg, int *value)
@@ -138,7 +138,7 @@ int max17050_get_property(enum MAX17050_reg reg, int *value)
 		*value = (int)(s16)data * 15625 / ADJ_RSENSE_MOHM / 10; /* Units of LSB = 1.5625uV / Rsense = 156.25uA */
 		break;
 	default:
-		return -1;
+		return 1;
 	}
 	return 0;
 }
@@ -147,18 +147,14 @@ static int _max17050_write_verify_reg(u8 reg, u16 value)
 {
 	int retries = 8;
 	int ret;
-	u16 read_value;
 
 	do
 	{
 		ret = i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, reg, (u8 *)&value, 2);
-		read_value = max17050_get_reg(reg);
-		if (read_value != value)
-		{
-			ret = -1;
-			retries--;
-		}
-	} while (retries && read_value != value);
+		u16 read_value = max17050_get_reg(reg);
+		if (!ret && read_value == value)
+			break;
+	} while (--retries);
 
 	return ret;
 }
@@ -251,7 +247,7 @@ static void _max17050_set_por_bit(u16 value)
 	_max17050_write_verify_reg(MAX17050_STATUS, value);
 }
 
-int max17050_fix_configuration()
+void max17050_fix_configuration()
 {
 	/* Init phase, set the POR bit */
 	_max17050_set_por_bit(STATUS_POR_BIT);
@@ -285,8 +281,6 @@ int max17050_fix_configuration()
 
 	// Sets POR, BI, BR.
 	_max17050_set_por_bit(0x8801);
-
-	return 0;
 }
 
 void max17050_dump_regs(void *buf)

bdk/power/max17050.h

@@ -121,7 +121,7 @@ enum MAX17050_reg {
 
 int  max17050_get_version(u32 *value);
 int  max17050_get_property(enum MAX17050_reg reg, int *value);
-int  max17050_fix_configuration();
+void max17050_fix_configuration();
 void max17050_dump_regs(void *buf);
 
 #endif /* __MAX17050_H_ */

bdk/power/max7762x.c

@@ -137,7 +137,7 @@ static void _max7762x_set_reg(u8 addr, u8 reg, u8 val)
 	u32 retries = 100;
 	while (retries)
 	{
-		if (i2c_send_byte(I2C_5, addr, reg, val))
+		if (!i2c_send_byte(I2C_5, addr, reg, val))
 			break;
 
 		usleep(50);
@@ -166,7 +166,7 @@ int max77620_regulator_get_status(u32 id)
 int max77620_regulator_config_fps(u32 id)
 {
 	if (id > REGULATOR_LDO8)
-		return 0;
+		return 1;
 
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
@@ -177,22 +177,22 @@ int max77620_regulator_config_fps(u32 id)
 		(reg->fps.pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) |
 		(reg->fps.pd_period << MAX77620_FPS_PD_PERIOD_SHIFT));
 
-	return 1;
+	return 0;
 }
 
 int max7762x_regulator_set_voltage(u32 id, u32 uv)
 {
 	if (id > REGULATOR_MAX)
-		return 0;
+		return 1;
 
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
 	if (uv < reg->uv_min || uv > reg->uv_max)
-		return 0;
+		return 1;
 
 	u8 addr = _max7762x_get_i2c_address(id);
 	if (!addr)
-		return 0;
+		return 1;
 
 	// Calculate voltage multiplier.
 	u32 mult = (uv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
@@ -209,7 +209,7 @@ int max7762x_regulator_set_voltage(u32 id, u32 uv)
 	// Wait for ramp up/down delay.
 	usleep(1000);
 
-	return 1;
+	return 0;
 }
 
 int max7762x_regulator_enable(u32 id, bool enable)
@@ -220,7 +220,7 @@ int max7762x_regulator_enable(u32 id, bool enable)
 	u8 enable_shift;
 
 	if (id > REGULATOR_MAX)
-		return 0;
+		return 1;
 
 	const max77620_regulator_t *reg = &_pmic_regulators[id];
 
@@ -252,12 +252,12 @@ int max7762x_regulator_enable(u32 id, bool enable)
 		enable_shift = reg->enable.shift;
 		break;
 	default:
-		return 0;
+		return 1;
 	}
 
 	u8 addr = _max7762x_get_i2c_address(id);
 	if (!addr)
-		return 0;
+		return 1;
 
 	// Read and enable/disable.
 	u8 val = i2c_recv_byte(I2C_5, addr, reg_addr);
@@ -272,7 +272,7 @@ int max7762x_regulator_enable(u32 id, bool enable)
 	// Wait for enable/disable ramp delay.
 	usleep(1000);
 
-	return 1;
+	return 0;
 }
 
 void max77620_config_gpio(u32 gpio_id, bool enable)

bdk/sec/se.c

@@ -88,7 +88,7 @@ static int _se_op_wait()
 		(SE(SE_ERR_STATUS_REG) != 0)
 	   )
 	{
-		return 0;
+		return 1;
 	}
 
 	// WAR: Coherency flushing.
@@ -104,7 +104,7 @@ static int _se_op_wait()
 			while (SE(SE_STATUS_REG) & SE_STATUS_MEM_IF_BUSY)
 			{
 				if (!retries)
-					return 0;
+					return 1;
 				usleep(1);
 				retries--;
 			}
@@ -115,13 +115,13 @@ static int _se_op_wait()
 		while (AHB_GIZMO(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID) & MEM_WRQUE_SE_MST_ID)
 		{
 			if (!retries)
-				return 0;
+				return 1;
 			usleep(1);
 			retries--;
 		}
 	}
 
-	return 1;
+	return 0;
 }
 
 static int _se_execute_finalize()
@@ -137,7 +137,7 @@ static int _se_execute_finalize()
 static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size, bool is_oneshot)
 {
 	if (dst_size > SE_LL_MAX_SIZE || src_size > SE_LL_MAX_SIZE)
-		return 0;
+		return 1;
 
 	ll_src_ptr = NULL;
 	ll_dst_ptr = NULL;
@@ -170,7 +170,7 @@ static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src
 	if (is_oneshot)
 		return _se_execute_finalize();
 
-	return 1;
+	return 0;
 }
 
 static int _se_execute_oneshot(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size)
@@ -186,7 +186,7 @@ static int _se_execute_aes_oneshot(void *dst, const void *src, u32 size)
 
 	u32 size_aligned = ALIGN_DOWN(size, SE_AES_BLOCK_SIZE);
 	u32 size_residue = size % SE_AES_BLOCK_SIZE;
-	int res = 1;
+	int res = 0;
 
 	// Handle initial aligned message.
 	if (size_aligned)
@@ -197,7 +197,7 @@ static int _se_execute_aes_oneshot(void *dst, const void *src, u32 size)
 	}
 
 	// Handle leftover partial message.
-	if (res && size_residue)
+	if (!res && size_residue)
 	{
 		// Copy message to a block sized buffer in case it's partial.
 		u32 block[SE_AES_BLOCK_SIZE / sizeof(u32)] = {0};
@@ -380,7 +380,6 @@ int se_aes_crypt_ctr(u32 ks, void *dst, const void *src, u32 size, void *ctr)
 
 int se_aes_crypt_xts_sec(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, void *dst, void *src, u32 secsize)
 {
-	int res = 0;
 	u32 tmp[SE_AES_BLOCK_SIZE / sizeof(u32)];
 	u8 *tweak = (u8 *)tmp;
 	u8 *pdst = (u8 *)dst;
@@ -392,27 +391,27 @@ int se_aes_crypt_xts_sec(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, void *dst
 		tweak[i] = sec & 0xFF;
 		sec >>= 8;
 	}
-	if (!se_aes_crypt_ecb(tweak_ks, ENCRYPT, tweak, tweak, SE_AES_BLOCK_SIZE))
-		goto out;
+	if (se_aes_crypt_ecb(tweak_ks, ENCRYPT, tweak, tweak, SE_AES_BLOCK_SIZE))
+		return 1;
 
 	// We are assuming a 0x10-aligned sector size in this implementation.
 	for (u32 i = 0; i < secsize / SE_AES_BLOCK_SIZE; i++)
 	{
 		for (u32 j = 0; j < SE_AES_BLOCK_SIZE; j++)
 			pdst[j] = psrc[j] ^ tweak[j];
-		if (!se_aes_crypt_ecb(crypt_ks, enc, pdst, pdst, SE_AES_BLOCK_SIZE))
-			goto out;
+
+		if (se_aes_crypt_ecb(crypt_ks, enc, pdst, pdst, SE_AES_BLOCK_SIZE))
+			return 1;
+
 		for (u32 j = 0; j < SE_AES_BLOCK_SIZE; j++)
 			pdst[j] = pdst[j] ^ tweak[j];
+
 		_se_ls_1bit(tweak);
 		psrc += SE_AES_BLOCK_SIZE;
 		pdst += SE_AES_BLOCK_SIZE;
 	}
 
-	res = 1;
-
-out:
-	return res;
+	return 0;
 }
 
 int se_aes_crypt_xts_sec_nx(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, u8 *tweak, bool regen_tweak, u32 tweak_exp, void *dst, void *src, u32 sec_size)
@@ -428,8 +427,8 @@ int se_aes_crypt_xts_sec_nx(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, u8 *tw
 			tweak[i] = sec & 0xFF;
 			sec >>= 8;
 		}
-		if (!se_aes_crypt_ecb(tweak_ks, ENCRYPT, tweak, tweak, SE_AES_BLOCK_SIZE))
-			return 0;
+		if (se_aes_crypt_ecb(tweak_ks, ENCRYPT, tweak, tweak, SE_AES_BLOCK_SIZE))
+			return 1;
 	}
 
 	// tweak_exp allows using a saved tweak to reduce _se_ls_1bit_le calls.
@@ -450,8 +449,8 @@ int se_aes_crypt_xts_sec_nx(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, u8 *tw
 		pdst += sizeof(u32);
 	}
 
-	if (!se_aes_crypt_ecb(crypt_ks, enc, dst, dst, sec_size))
-		return 0;
+	if (se_aes_crypt_ecb(crypt_ks, enc, dst, dst, sec_size))
+		return 1;
 
 	pdst = (u32 *)dst;
 	ptweak = (u32 *)orig_tweak;
@@ -464,7 +463,7 @@ int se_aes_crypt_xts_sec_nx(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, u8 *tw
 		pdst += sizeof(u32);
 	}
 
-	return 1;
+	return 0;
 }
 
 int se_aes_crypt_xts(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, void *dst, void *src, u32 secsize, u32 num_secs)
@@ -473,10 +472,10 @@ int se_aes_crypt_xts(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, void *dst, vo
 	u8 *psrc = (u8 *)src;
 
 	for (u32 i = 0; i < num_secs; i++)
-		if (!se_aes_crypt_xts_sec(tweak_ks, crypt_ks, enc, sec + i, pdst + secsize * i, psrc + secsize * i, secsize))
-			return 0;
+		if (se_aes_crypt_xts_sec(tweak_ks, crypt_ks, enc, sec + i, pdst + secsize * i, psrc + secsize * i, secsize))
+			return 1;
 
-	return 1;
+	return 0;
 }
 
 static void _se_sha_hash_256_get_hash(void *hash)
@@ -498,7 +497,7 @@ static int _se_sha_hash_256(void *hash, u64 total_size, const void *src, u32 src
 			0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C, 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55
 		};
 		memcpy(hash, null_hash, SE_SHA_256_SIZE);
-		return 1;
+		return 0;
 	}
 
 	// Increase leftover size if not last message. (Engine will always stop at src_size.)
@@ -530,7 +529,7 @@ static int _se_sha_hash_256(void *hash, u64 total_size, const void *src, u32 src
 	// Trigger the operation. src vs total size decides if it's partial.
 	int res = _se_execute(SE_OP_START, NULL, 0, src, src_size, is_oneshot);
 
-	if (res && is_oneshot)
+	if (!res && is_oneshot)
 		_se_sha_hash_256_get_hash(hash);
 
 	return res;
@@ -550,7 +549,7 @@ int se_sha_hash_256_partial_start(void *hash, const void *src, u32 size, bool is
 {
 	// Check if aligned SHA256 block size.
 	if (size % SE_SHA2_MIN_BLOCK_SIZE)
-		return 0;
+		return 1;
 
 	return _se_sha_hash_256(hash, 0, src, size, is_oneshot);
 }
@@ -559,7 +558,7 @@ int se_sha_hash_256_partial_update(void *hash, const void *src, u32 size, bool i
 {
 	// Check if aligned to SHA256 block size.
 	if (size % SE_SHA2_MIN_BLOCK_SIZE)
-		return 0;
+		return 1;
 
 	return _se_sha_hash_256(hash, size - 1, src, size, is_oneshot);
 }
@@ -600,7 +599,7 @@ int se_rng_pseudo(void *dst, u32 size)
 	}
 
 	// Handle leftover partial message.
-	if (res && size_residue)
+	if (!res && size_residue)
 	{
 		// Copy message to a block sized buffer in case it's partial.
 		u32 block[SE_RNG_BLOCK_SIZE / sizeof(u32)] = {0};
@@ -610,8 +609,7 @@ int se_rng_pseudo(void *dst, u32 size)
 		res = _se_execute_oneshot(SE_OP_START, block, SE_RNG_BLOCK_SIZE, NULL, 0);
 
 		// Copy result back.
-		if (res)
-			memcpy(dst + size_aligned, block, size_residue);
+		memcpy(dst + size_aligned, block, size_residue);
 	}
 
 	return res;
@@ -682,8 +680,8 @@ int se_aes_hash_cmac(u32 ks, void *hash, const void *src, u32 size)
 
 	// Generate sub key (CBC with zeroed IV, basically ECB).
 	se_aes_iv_clear(ks);
-	if (!se_aes_crypt_cbc(ks, ENCRYPT, subkey, subkey, SE_KEY_128_SIZE))
-		return 0;
+	if (se_aes_crypt_cbc(ks, ENCRYPT, subkey, subkey, SE_KEY_128_SIZE))
+		return 1;
 
 	// Generate K1 subkey.
 	_se_ls_1bit(subkey);
@@ -700,8 +698,8 @@ int se_aes_hash_cmac(u32 ks, void *hash, const void *src, u32 size)
 	{
 		SE(SE_CRYPTO_LAST_BLOCK_REG) = num_blocks - 2;
 
-		if (!_se_execute_oneshot(SE_OP_START, NULL, 0, src, size))
-			return 0;
+		if (_se_execute_oneshot(SE_OP_START, NULL, 0, src, size))
+			return 1;
 
 		// Use updated IV for next OP as a continuation.
 		SE(SE_CRYPTO_CONFIG_REG) |= SE_CRYPTO_IV_SEL(IV_UPDATED);
@@ -721,15 +719,13 @@ int se_aes_hash_cmac(u32 ks, void *hash, const void *src, u32 size)
 
 	SE(SE_CRYPTO_LAST_BLOCK_REG) = (SE_AES_BLOCK_SIZE >> 4) - 1;
 
-	int res = _se_execute_oneshot(SE_OP_START, NULL, 0, last_block, SE_AES_BLOCK_SIZE);
+	if (_se_execute_oneshot(SE_OP_START, NULL, 0, last_block, SE_AES_BLOCK_SIZE))
+		return 1;
 
 	// Copy output hash.
-	if (res)
-	{
-		u32 *hash32 = (u32 *)hash;
-		for (u32 i = 0; i < (SE_AES_CMAC_DIGEST_SIZE / sizeof(u32)); i++)
-			hash32[i] = SE(SE_HASH_RESULT_REG + sizeof(u32) * i);
-	}
+	u32 *hash32 = (u32 *)hash;
+	for (u32 i = 0; i < (SE_AES_CMAC_DIGEST_SIZE / sizeof(u32)); i++)
+		hash32[i] = SE(SE_HASH_RESULT_REG + sizeof(u32) * i);
 
-	return res;
+	return 0;
 }

bdk/sec/tsec.c

@@ -44,9 +44,9 @@ static int _tsec_dma_wait_idle()
 
 	while (!(TSEC(TSEC_DMATRFCMD) & TSEC_DMATRFCMD_IDLE))
 		if (get_tmr_ms() > timeout)
-			return 0;
+			return 1;
 
-	return 1;
+	return 0;
 }
 
 static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offset)
@@ -97,7 +97,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 		pmc_domain_pwrgate_set(POWER_RAIL_CE3, DISABLE);
 
 		// Enable AHB aperture and set it to full mmio.
-		mc_enable_ahb_redirect();
+		mc_enable_ahb_redirect(0);
 	}
 
 	// Configure Falcon.
@@ -116,7 +116,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 		TSEC_IRQDEST_SWGEN0    |
 		TSEC_IRQDEST_SWGEN1;
 	TSEC(TSEC_ITFEN) = TSEC_ITFEN_CTXEN | TSEC_ITFEN_MTHDEN;
-	if (!_tsec_dma_wait_idle())
+	if (_tsec_dma_wait_idle())
 	{
 		res = -1;
 		goto out;
@@ -136,7 +136,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 
 	for (u32 addr = 0; addr < tsec_ctxt->size; addr += 0x100)
 	{
-		if (!_tsec_dma_pa_to_internal_100(false, addr, addr))
+		if (_tsec_dma_pa_to_internal_100(false, addr, addr))
 		{
 			res = -2;
 			goto out_free;
@@ -146,7 +146,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 	if (type == TSEC_FW_TYPE_EMU)
 	{
 		// Init SMMU translation for TSEC.
-		ptb = smmu_init_domain(MC_SMMU_TSEC_ASID, 1);
+		ptb = smmu_domain_init(MC_SMMU_TSEC_ASID, 1);
 		smmu_init();
 
 		// Enable SMMU.
@@ -230,7 +230,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 		if (kidx != 8)
 		{
 			res = -6;
-			smmu_deinit_domain(MC_SMMU_TSEC_ASID, 1);
+			smmu_domain_deinit(MC_SMMU_TSEC_ASID, 1);
 
 			goto out_free;
 		}
@@ -241,7 +241,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 		memcpy(tsec_keys, &key, 0x20);
 		memcpy(tsec_ctxt->pkg1, iram, 0x30000);
 
-		smmu_deinit_domain(MC_SMMU_TSEC_ASID, 1);
+		smmu_domain_deinit(MC_SMMU_TSEC_ASID, 1);
 
 		// for (int i = 0; i < kidx; i++)
 		// 	gfx_printf("key %08X\n", key[i]);
@@ -257,7 +257,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 	}
 	else
 	{
-		if (!_tsec_dma_wait_idle())
+		if (_tsec_dma_wait_idle())
 		{
 			res = -3;
 			goto out_free;
@@ -307,10 +307,8 @@ out:
 	bpmp_mmu_enable();
 	bpmp_clk_rate_relaxed(false);
 
-#ifdef BDK_MC_ENABLE_AHB_REDIRECT
 	// Re-enable AHB aperture.
-	mc_enable_ahb_redirect();
-#endif
+	mc_enable_ahb_redirect(1);
 
 	return res;
 }

bdk/soc/bpmp.h

@@ -51,7 +51,7 @@ typedef enum
 	BPMP_CLK_SUPER_BOOST, // 576MHz 41% - 144MHz APB.
 	BPMP_CLK_HYPER_BOOST, // 589MHz 44% - 147MHz APB.
 	//BPMP_CLK_DEV_BOOST, // 608MHz 49% - 152MHz APB.
-	BPMP_CLK_NUM 
+	BPMP_CLK_NUM
 } bpmp_freq_t;
 
 typedef enum

bdk/soc/clock.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2025 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -89,14 +89,14 @@ static const clk_rst_t _clock_uart[] = {
 	{ RST_DEV_Y_SET, CLK_ENB_Y_SET, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, CLK_Y_UARTAPE, 0, CLK_SRC_DIV(2) }
 };
 
-//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26.
+// I2C Fout = Fin / (TLOW + THIGH + 2) / FM_DIV). Default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 6.
 static const clk_rst_t _clock_i2c[] = {
-	{ RST_DEV_L_SET, CLK_ENB_L_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, CLK_L_I2C1, 0, CLK_SRC_DIV(10.5) }, // 20.4 MHz -> 100 KHz
-	{ RST_DEV_H_SET, CLK_ENB_H_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, CLK_H_I2C2, 0, CLK_SRC_DIV(3)    }, // 81.6 MHz -> 400 KHz
-	{ RST_DEV_U_SET, CLK_ENB_U_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, CLK_U_I2C3, 0, CLK_SRC_DIV(3)    }, // 81.6 MHz -> 400 KHz
-	{ RST_DEV_V_SET, CLK_ENB_V_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, CLK_V_I2C4, 0, CLK_SRC_DIV(10.5) }, // 20.4 MHz -> 100 KHz
-	{ RST_DEV_H_SET, CLK_ENB_H_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, CLK_H_I2C5, 0, CLK_SRC_DIV(3)    }, // 81.6 MHz -> 400 KHz
-	{ RST_DEV_X_SET, CLK_ENB_X_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, CLK_X_I2C6, 0, CLK_SRC_DIV(10.5) }  // 20.4 MHz -> 100 KHz
+	{ RST_DEV_L_SET, CLK_ENB_L_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, CLK_L_I2C1, 6, CLK_I2C_SRC_DIV(4) }, //  4.8 MHz -> 100 KHz
+	{ RST_DEV_H_SET, CLK_ENB_H_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, CLK_H_I2C2, 6, CLK_I2C_SRC_DIV(1) }, // 19.2 MHz -> 400 KHz
+	{ RST_DEV_U_SET, CLK_ENB_U_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, CLK_U_I2C3, 6, CLK_I2C_SRC_DIV(1) }, // 19.2 MHz -> 400 KHz
+	{ RST_DEV_V_SET, CLK_ENB_V_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, CLK_V_I2C4, 6, CLK_I2C_SRC_DIV(4) }, //  4.8 MHz -> 100 KHz
+	{ RST_DEV_H_SET, CLK_ENB_H_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, CLK_H_I2C5, 6, CLK_I2C_SRC_DIV(1) }, // 19.2 MHz -> 400 KHz
+	{ RST_DEV_X_SET, CLK_ENB_X_SET, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, CLK_X_I2C6, 6, CLK_I2C_SRC_DIV(4) }  //  4.8 MHz -> 100 KHz
 };
 
 static clk_rst_t _clock_se = {
@@ -733,7 +733,7 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 clock)
 	u32 source  = SDMMC_CLOCK_SRC_PLLP_OUT0;
 
 	if (id > SDMMC_4)
-		return 0;
+		return 1;
 
 	// Get IO clock divisor.
 	switch (clock)
@@ -813,7 +813,7 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 clock)
 	const clk_rst_mgd_t *clk = &_clock_sdmmc[id];
 	CLOCK(clk->source) = (source << 29u) | divisor;
 
-	return 1;
+	return 0;
 }
 
 void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 clock)

bdk/soc/clock.h

@@ -199,7 +199,8 @@
 #define UTMIPLL_LOCK         BIT(31)
 
 /*! Clock source */
-#define CLK_SRC_DIV(d) ((d) ? ((u32)(((d) - 1) * 2)) : 0)
+#define CLK_SRC_DIV(d)     ((d) ? ((u32)(((d) - 1) * 2)) : 0)
+#define CLK_I2C_SRC_DIV(d) ((d) ? ((u32)(((d) - 1))) : 0)
 
 /*! PTO_CLK_CNT */
 #define PTO_REF_CLK_WIN_CFG_MASK 0xF

bdk/soc/hw_init.c

@@ -438,9 +438,9 @@ void hw_init()
 	if (!tegra_t210)
 	{
 		// This is not actually needed since it's done by bootrom. The read locks are extra.
-		PMC(APBDEV_PMC_TZRAM_PWR_CNTRL)      &= ~PMC_TZRAM_PWR_CNTRL_SD;
-		PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
-		PMC(APBDEV_PMC_TZRAM_SEC_DISABLE)     = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
+		PMC(APBDEV_PMC_TZRAM_PWR_CNTRL_B01)      &= ~PMC_TZRAM_PWR_CNTRL_SD;
+		PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE_B01) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
+		PMC(APBDEV_PMC_TZRAM_SEC_DISABLE_B01)     = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
 	}
 
 	// Set arbiter.

bdk/soc/i2c.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2022 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -49,6 +49,9 @@
 #define I2C_TX_FIFO           (0x50 / 4)
 #define I2C_RX_FIFO           (0x54 / 4)
 
+#define I2C_PACKET_TRANSFER_STATUS (0x58 / 4)
+#define  PKT_TRANSFER_COMPLETE BIT(24)
+
 #define I2C_FIFO_CONTROL      (0x5C / 4)
 #define  RX_FIFO_FLUSH        BIT(0)
 #define  TX_FIFO_FLUSH        BIT(1)
@@ -96,10 +99,10 @@ static void _i2c_load_cfg_wait(vu32 *base)
 	}
 }
 
-static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, const u8 *buf, u32 size)
+static int _i2c_send_normal(u32 i2c_idx, u32 dev_addr, const u8 *buf, u32 size)
 {
 	if (size > 8)
-		return 0;
+		return 1;
 
 	u32 tmp = 0;
 
@@ -129,25 +132,25 @@ static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, const u8 *buf, u32 size)
 	_i2c_load_cfg_wait(base);
 
 	// Initiate transaction on normal mode.
-	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
+	base[I2C_CNFG] = (base[I2C_CNFG] & ~NORMAL_MODE_GO) | NORMAL_MODE_GO;
 
-	u32 timeout = get_tmr_us() + 200000; // Actual for max 8 bytes at 100KHz is 0.74ms.
+	u32 timeout = get_tmr_ms() + 100; // Actual for max 8 bytes at 100KHz is 0.74ms.
 	while (base[I2C_STATUS] & I2C_STATUS_BUSY)
 	{
-		if (get_tmr_us() > timeout)
-			return 0;
+		if (get_tmr_ms() > timeout)
+			return 1;
 	}
 
 	if (base[I2C_STATUS] & I2C_STATUS_NOACK)
-		return 0;
+		return 1;
 
-	return 1;
+	return 0;
 }
 
-static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
+static int _i2c_recv_normal(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 {
 	if (size > 8)
-		return 0;
+		return 1;
 
 	vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
 
@@ -161,17 +164,17 @@ static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 	_i2c_load_cfg_wait(base);
 
 	// Initiate transaction on normal mode.
-	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
+	base[I2C_CNFG] = (base[I2C_CNFG] & ~NORMAL_MODE_GO) | NORMAL_MODE_GO;
 
-	u32 timeout = get_tmr_us() + 200000; // Actual for max 8 bytes at 100KHz is 0.74ms.
+	u32 timeout = get_tmr_ms() + 100; // Actual for max 8 bytes at 100KHz is 0.74ms.
 	while (base[I2C_STATUS] & I2C_STATUS_BUSY)
 	{
-		if (get_tmr_us() > timeout)
-			return 0;
+		if (get_tmr_ms() > timeout)
+			return 1;
 	}
 
 	if (base[I2C_STATUS] & I2C_STATUS_NOACK)
-		return 0;
+		return 1;
 
 	u32 tmp = base[I2C_CMD_DATA1]; // Get LS value.
 	if (size > 4)
@@ -183,23 +186,18 @@ static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 	else
 		memcpy(buf, &tmp, size);
 
-	return 1;
+	return 0;
 }
 
-static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
+static int _i2c_send_packet(u32 i2c_idx, const u8 *buf, u32 size, u32 dev_addr)
 {
 	if (size > 32)
-		return 0;
+		return 1;
 
 	int res = 0;
 
 	vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
 
-	// Enable interrupts.
-	base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
-		ARB_LOST | TX_FIFO_OVER | RX_FIFO_UNDER | TX_FIFO_DATA_REQ;
-	base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
-
 	// Set device address and send mode.
 	base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_WRITE;
 
@@ -213,31 +211,28 @@ static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 	_i2c_load_cfg_wait(base);
 
 	// Initiate transaction on packet mode.
-	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | PACKET_MODE_GO;
-
-	u32 hdr[3];
-	hdr[0] = I2C_PACKET_PROT_I2C;
-	hdr[1] = size - 1;
-	hdr[2] = I2C_HEADER_IE_ENABLE | I2C_HEADER_CONT_XFER | (dev_addr << 1);
+	base[I2C_CNFG] = (base[I2C_CNFG] & ~NORMAL_MODE_GO) | PACKET_MODE_GO;
 
 	// Send header with request.
-	base[I2C_TX_FIFO] = hdr[0];
-	base[I2C_TX_FIFO] = hdr[1];
-	base[I2C_TX_FIFO] = hdr[2];
+	base[I2C_TX_FIFO] = I2C_PACKET_PROT_I2C;
+	base[I2C_TX_FIFO] = size - 1;
+	base[I2C_TX_FIFO] = I2C_HEADER_IE_ENABLE | I2C_HEADER_CONT_XFER | (dev_addr << 1);
 
-	u32 timeout = get_tmr_ms() + 400;
-	while (size)
+	// Send data.
+	u32 rem = size;
+	while (rem)
 	{
-		if (base[I2C_FIFO_STATUS] & TX_FIFO_EMPTY_CNT)
-		{
-			u32 tmp = 0;
-			u32 snd_size = MIN(size, 4);
-			memcpy(&tmp, buf, snd_size);
-			base[I2C_TX_FIFO] = tmp;
-			buf += snd_size;
-			size -= snd_size;
-		}
+		u32 len = MIN(rem, sizeof(u32));
+		u32 word = 0;
+		memcpy(&word, buf, len);
+		base[I2C_TX_FIFO] = word;
+		buf += len;
+		rem -= len;
+	}
 
+	u32 timeout = get_tmr_ms() + 200;
+	while (((base[I2C_PACKET_TRANSFER_STATUS] >> 4) & 0xFFF) != (size - 1))
+	{
 		if (get_tmr_ms() > timeout)
 		{
 			res = 1;
@@ -245,33 +240,27 @@ static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 		}
 	}
 
-	if (base[I2C_STATUS] & I2C_STATUS_NOACK || base[I2C_INT_STATUS] & NO_ACK)
+	// Check if no reply.
+	if (base[I2C_STATUS] & I2C_STATUS_NOACK)
 		res = 1;
 
-	// Disable packet mode.
+	// Wait for STOP and disable packet mode.
 	usleep(20);
-	base[I2C_CNFG] &= 0xFFFFF9FF;
-
-	// Disable interrupts.
-	base[I2C_INT_EN] = 0;
+	base[I2C_CNFG] &= ~(PACKET_MODE_GO | NORMAL_MODE_GO);
 
 	return res;
 }
 
-static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
+int i2c_xfer_packet(u32 i2c_idx, u32 dev_addr, const u8 *tx_buf, u32 tx_size, u8 *rx_buf, u32 rx_size)
 {
-	if (size > 32)
-		return 0;
+	// Max 32 bytes TX/RX fifo.
+	if (tx_size > 20 || rx_size > 32) // Header included.
+		return 1;
 
 	int res = 0;
 
 	vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]);
 
-	// Enable interrupts.
-	base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK |
-		ARB_LOST | TX_FIFO_OVER | RX_FIFO_UNDER | RX_FIFO_DATA_REQ;
-	base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
-
 	// Set device address and recv mode.
 	base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
 
@@ -285,44 +274,51 @@ static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
 	_i2c_load_cfg_wait(base);
 
 	// Initiate transaction on packet mode.
-	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | PACKET_MODE_GO;
+	base[I2C_CNFG] = (base[I2C_CNFG] & ~NORMAL_MODE_GO) | PACKET_MODE_GO;
 
-	// Send reg request.
-	u32 hdr[3];
-	hdr[0] = I2C_PACKET_PROT_I2C;
-	hdr[1] = 1 - 1;
-	hdr[2] = I2C_HEADER_REP_START | (dev_addr << 1);
+	// Send header with send request.
+	base[I2C_TX_FIFO] = I2C_PACKET_PROT_I2C;
+	base[I2C_TX_FIFO] = tx_size - 1;
+	base[I2C_TX_FIFO] = I2C_HEADER_REP_START | (dev_addr << 1);
 
-	// Send header with reg request.
-	base[I2C_TX_FIFO] = hdr[0];
-	base[I2C_TX_FIFO] = hdr[1];
-	base[I2C_TX_FIFO] = hdr[2];
-	base[I2C_TX_FIFO] = reg;
+	// Send data.
+	u32 tx_rem = tx_size;
+	while (tx_rem)
+	{
+		u32 len = MIN(tx_rem, sizeof(u32));
+		u32 word = 0;
+		memcpy(&word, tx_buf, len);
+		base[I2C_TX_FIFO] = word;
+		tx_buf += len;
+		tx_rem -= len;
+	}
 
-	u32 timeout = get_tmr_ms() + 400;
-	while (!(base[I2C_FIFO_STATUS] & TX_FIFO_EMPTY_CNT))
+	u32 timeout = get_tmr_ms() + 200;
+	while (((base[I2C_PACKET_TRANSFER_STATUS] >> 4) & 0xFFF) != (tx_size - 1))
+	{
 		if (get_tmr_ms() > timeout)
-			break;
+		{
+			res = 1;
+			goto out;
+		}
+	}
 
-	// Send read request.
-	hdr[1] = size - 1;
-	hdr[2] = I2C_HEADER_READ | (dev_addr << 1);
+	// Send header with receive request
+	base[I2C_TX_FIFO] = I2C_PACKET_PROT_I2C;
+	base[I2C_TX_FIFO] = rx_size - 1;
+	base[I2C_TX_FIFO] = I2C_HEADER_READ | (dev_addr << 1);
 
-	// Send header with read request.
-	base[I2C_TX_FIFO] = hdr[0];
-	base[I2C_TX_FIFO] = hdr[1];
-	base[I2C_TX_FIFO] = hdr[2];
-
-	timeout = get_tmr_ms() + 400;
-	while (size)
+	// Receive data.
+	timeout = get_tmr_ms() + 200;
+	while (rx_size)
 	{
 		if (base[I2C_FIFO_STATUS] & RX_FIFO_FULL_CNT)
 		{
-			u32 rcv_size = MIN(size, 4);
-			u32 tmp = base[I2C_RX_FIFO];
-			memcpy(buf, &tmp, rcv_size);
-			buf += rcv_size;
-			size -= rcv_size;
+			u32 len = MIN(rx_size, sizeof(u32));
+			u32 word = base[I2C_RX_FIFO];
+			memcpy(rx_buf, &word, len);
+			rx_buf  += len;
+			rx_size -= len;
 		}
 
 		if (get_tmr_ms() > timeout)
@@ -332,15 +328,14 @@ static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
 		}
 	}
 
-	if (base[I2C_STATUS] & I2C_STATUS_NOACK || base[I2C_INT_STATUS] & NO_ACK)
+out:
+	// Check if no reply.
+	if (base[I2C_STATUS] & I2C_STATUS_NOACK)
 		res = 1;
 
-	// Disable packet mode.
+	// Wait for STOP and disable packet mode.
 	usleep(20);
-	base[I2C_CNFG] &= 0xFFFFF9FF;
-
-	// Disable interrupts.
-	base[I2C_INT_EN] = 0;
+	base[I2C_CNFG] &= ~(PACKET_MODE_GO | NORMAL_MODE_GO);
 
 	return res;
 }
@@ -366,42 +361,33 @@ void i2c_init(u32 i2c_idx)
 	base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
 }
 
-int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr)
+int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, const u8 *buf, u32 size)
 {
-	return _i2c_recv_single(i2c_idx, buf, size, dev_addr);
-}
-
-int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
-{
-	if (size > 32)
-		return 0;
-
-	return _i2c_send_pkt(i2c_idx, buf, size, dev_addr);
+	return _i2c_send_packet(i2c_idx, buf, size, dev_addr);
 }
 
 int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg)
 {
-	return _i2c_recv_pkt(i2c_idx, buf, size, dev_addr, reg);
+	return i2c_xfer_packet(i2c_idx, dev_addr, (u8 *)&reg, 1, buf, size);
 }
 
 int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, const u8 *buf, u32 size)
 {
-	u8 tmp[8];
-
 	if (size > 7)
-		return 0;
+		return 1;
 
+	u8 tmp[8];
 	tmp[0] = reg;
 	memcpy(tmp + 1, buf, size);
 
-	return _i2c_send_single(i2c_idx, dev_addr, tmp, size + 1);
+	return _i2c_send_normal(i2c_idx, dev_addr, tmp, size + 1);
 }
 
 int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg)
 {
-	int res = _i2c_send_single(i2c_idx, dev_addr, (u8 *)&reg, 1);
-	if (res)
-		res = _i2c_recv_single(i2c_idx, buf, size, dev_addr);
+	int res = _i2c_send_normal(i2c_idx, dev_addr, (u8 *)&reg, 1);
+	if (!res)
+		res = _i2c_recv_normal(i2c_idx, buf, size, dev_addr);
 	return res;
 }
 

bdk/soc/i2c.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020 CTCaer
+ * Copyright (c) 2020-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -28,8 +28,8 @@
 #define I2C_6 5
 
 void i2c_init(u32 i2c_idx);
-int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr);
-int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size);
+int i2c_xfer_packet(u32 i2c_idx, u32 dev_addr, const u8 *tx_buf, u32 tx_size, u8 *rx_buf, u32 rx_size);
+int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, const u8 *buf, u32 size);
 int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg);
 int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, const u8 *buf, u32 size);
 int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg);

bdk/soc/kfuse.c

@@ -25,25 +25,25 @@ int kfuse_wait_ready()
 		;
 
 	if (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_CRCPASS))
-		return 0;
+		return 1;
 
-	return 1;
+	return 0;
 }
 
 int kfuse_read(u32 *buf)
 {
-	int res = 0;
+	int res = 1;
 
 	clock_enable_kfuse();
 
-	if (!kfuse_wait_ready())
+	if (kfuse_wait_ready())
 		goto out;
 
 	KFUSE(KFUSE_KEYADDR) = KFUSE_KEYADDR_AUTOINC;
 	for (int i = 0; i < KFUSE_NUM_WORDS; i++)
 		buf[i] = KFUSE(KFUSE_KEYS);
 
-	res = 1;
+	res = 0;
 
 out:
 	clock_disable_kfuse();

bdk/soc/pinmux.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2024 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -15,6 +15,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <soc/i2c.h>
 #include <soc/pinmux.h>
 #include <soc/t210.h>
 
@@ -30,6 +31,13 @@ void pinmux_config_i2c(u32 idx)
 {
 	PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(idx)) = PINMUX_INPUT_ENABLE;
 	PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(idx)) = PINMUX_INPUT_ENABLE;
+
+	// Detach I2C4 pins from I2C3 function.
+	if (idx == I2C_3 || idx == I2C_4)
+	{
+		PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(I2C_4)) |= 1;
+		PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(I2C_4)) |= 1;
+	}
 }
 
 void pinmux_config_i2s(u32 idx)

bdk/soc/pmc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 CTCaer
+ * Copyright (c) 2020-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -75,10 +75,10 @@ void pmc_scratch_lock(pmc_sec_lock_t lock_mask)
 		PMC(APBDEV_PMC_SEC_DISABLE)  |= 0xFF000;    // RW lock: 4-7
 
 	if (lock_mask & PMC_SEC_LOCK_SE2_SRK_B01)
-		PMC(APBDEV_PMC_SEC_DISABLE9)  |= 0x3FC;     // RW lock: 120-123 (T210B01). LP0 also sets global bits (b0-1).
+		PMC(APBDEV_PMC_SEC_DISABLE9_B01)  |= 0x3FC; // RW lock: 120-123 (T210B01). LP0 also sets global bits (b0-1).
 
 	if (lock_mask & PMC_SEC_LOCK_MISC_B01)
-		PMC(APBDEV_PMC_SEC_DISABLE10) = 0xFFFFFFFF; // RW lock: 135-150. Happens on T210B01 LP0 always.
+		PMC(APBDEV_PMC_SEC_DISABLE10_B01) = 0xFFFFFFFF; // RW lock: 135-150. Happens on T210B01 LP0 always.
 
 	if (lock_mask & PMC_SEC_LOCK_CARVEOUTS_L4T)
 		PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x5555;     // W: 8-15 LP0 and Carveouts. Superseded by LP0 lock.
@@ -87,15 +87,15 @@ void pmc_scratch_lock(pmc_sec_lock_t lock_mask)
 	// They could also use the NS write disable registers instead.
 	if (lock_mask & PMC_SEC_LOCK_LP0_PARAMS_B01)
 	{
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE0) |= 0xCBCFE0;   // W lock: 5-11, 14-17, 19, 22-23.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1) |= 0x583FF;    // W lock: 24-33, 39-40, 42.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE2) |= 0x1BE;      // W lock: 44-48, 50-51.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE3)  = 0xFFFFFFFF; // W lock: 56-87.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE4) |= 0xFFFFFFF;  // W lock: 88-115.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE5) |= 0xFFFFFFF8; // W lock: 123-151.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE6)  = 0xFFFFFFFF; // W lock: 152-183.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE7) |= 0xFC00FFFF; // W lock: 184-199, 210-215.
-		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE8) |= 0xF;        // W lock: 216-219.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE0_B01) |= 0xCBCFE0;   // W lock: 5-11, 14-17, 19, 22-23.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1_B01) |= 0x583FF;    // W lock: 24-33, 39-40, 42.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE2_B01) |= 0x1BE;      // W lock: 44-48, 50-51.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE3_B01)  = 0xFFFFFFFF; // W lock: 56-87.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE4_B01) |= 0xFFFFFFF;  // W lock: 88-115.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE5_B01) |= 0xFFFFFFF8; // W lock: 123-151.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE6_B01)  = 0xFFFFFFFF; // W lock: 152-183.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE7_B01) |= 0xFC00FFFF; // W lock: 184-199, 210-215.
+		PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE8_B01) |= 0xF;        // W lock: 216-219.
 	}
 }
 
@@ -115,28 +115,26 @@ int pmc_domain_pwrgate_set(pmc_power_rail_t part, u32 enable)
 
 	// Check if the power domain has the state we want.
 	if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
-		return 1;
+		return 0;
 
-	u32 i = 5001;
+	int retries = 5000;
 	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & PMC_PWRGATE_TOGGLE_START)
 	{
 		usleep(1);
-		i--;
-		if (i < 1)
-			return 0;
+		if (--retries < 1)
+			return 1;
 	}
 
 	// Toggle power gating.
 	PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | PMC_PWRGATE_TOGGLE_START;
 
-	i = 5001;
-	while (i > 0)
+	retries = 5000;
+	while ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) != desired_state)
 	{
-		if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
-			break;
 		usleep(1);
-		i--;
+		if (--retries < 1)
+			return 1;
 	}
 
-	return 1;
+	return 0;
 }

bdk/soc/pmc.h

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 st4rk
- * Copyright (c) 2018-2024 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -20,185 +20,7 @@
 #define _PMC_H_
 
 #include <utils/types.h>
-
-/*! PMC registers. */
-#define APBDEV_PMC_CNTRL             0x0
-#define  PMC_CNTRL_RTC_CLK_DIS             BIT(1)
-#define  PMC_CNTRL_RTC_RST                 BIT(2)
-#define  PMC_CNTRL_MAIN_RST                BIT(4)
-#define  PMC_CNTRL_LATCHWAKE_EN            BIT(5)
-#define  PMC_CNTRL_BLINK_EN                BIT(7)
-#define  PMC_CNTRL_PWRREQ_OE               BIT(9)
-#define  PMC_CNTRL_SYSCLK_OE               BIT(11)
-#define  PMC_CNTRL_PWRGATE_DIS             BIT(12)
-#define  PMC_CNTRL_SIDE_EFFECT_LP0         BIT(14)
-#define  PMC_CNTRL_CPUPWRREQ_OE            BIT(16)
-#define  PMC_CNTRL_FUSE_OVERRIDE           BIT(18)
-#define  PMC_CNTRL_SHUTDOWN_OE             BIT(22)
-#define APBDEV_PMC_SEC_DISABLE       0x4
-#define APBDEV_PMC_PWRGATE_TOGGLE    0x30
-#define  PMC_PWRGATE_TOGGLE_START          BIT(8)
-#define APBDEV_PMC_PWRGATE_STATUS    0x38
-#define APBDEV_PMC_NO_IOPOWER        0x44
-#define  PMC_NO_IOPOWER_MEM                BIT(7)
-#define  PMC_NO_IOPOWER_SDMMC1             BIT(12)
-#define  PMC_NO_IOPOWER_SDMMC4             BIT(14)
-#define  PMC_NO_IOPOWER_MEM_COMP           BIT(16)
-#define  PMC_NO_IOPOWER_AUDIO_HV           BIT(18)
-#define  PMC_NO_IOPOWER_GPIO               BIT(21)
-#define APBDEV_PMC_SCRATCH0          0x50
-#define  PMC_SCRATCH0_MODE_WARMBOOT        BIT(0)
-#define  PMC_SCRATCH0_MODE_RCM             BIT(1)
-#define  PMC_SCRATCH0_MODE_PAYLOAD         BIT(29)
-#define  PMC_SCRATCH0_MODE_BOOTLOADER      BIT(30)
-#define  PMC_SCRATCH0_MODE_RECOVERY        BIT(31)
-#define  PMC_SCRATCH0_MODE_CUSTOM_ALL      (PMC_SCRATCH0_MODE_RECOVERY   | \
-											PMC_SCRATCH0_MODE_BOOTLOADER | \
-											PMC_SCRATCH0_MODE_PAYLOAD)
-#define APBDEV_PMC_BLINK_TIMER       0x40
-#define  PMC_BLINK_ON(n)                   ((n & 0x7FFF))
-#define  PMC_BLINK_FORCE                   BIT(15)
-#define  PMC_BLINK_OFF(n)                  ((u32)(n & 0xFFFF) << 16)
-#define APBDEV_PMC_SCRATCH1          0x54
-#define APBDEV_PMC_SCRATCH20         0xA0 // ODM data/config scratch.
-#define APBDEV_PMC_SECURE_SCRATCH4   0xC0
-#define APBDEV_PMC_SECURE_SCRATCH5   0xC4
-#define APBDEV_PMC_PWR_DET_VAL       0xE4
-#define  PMC_PWR_DET_33V_SDMMC1            BIT(12)
-#define  PMC_PWR_DET_33V_AUDIO_HV          BIT(18)
-#define  PMC_PWR_DET_33V_GPIO              BIT(21)
-#define APBDEV_PMC_DDR_PWR           0xE8
-#define APBDEV_PMC_USB_AO            0xF0
-#define APBDEV_PMC_CRYPTO_OP         0xF4
-#define  PMC_CRYPTO_OP_SE_ENABLE           0
-#define  PMC_CRYPTO_OP_SE_DISABLE          1
-#define APBDEV_PMC_PLLP_WB0_OVERRIDE 0xF8
-#define  PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE_ENABLE BIT(11)
-#define  PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
-#define APBDEV_PMC_SCRATCH33         0x120
-#define APBDEV_PMC_SCRATCH37         0x130
-#define  PMC_SCRATCH37_KERNEL_PANIC_MAGIC  0x4E415054 // "TPAN"
-#define APBDEV_PMC_SCRATCH39         0x138
-#define APBDEV_PMC_SCRATCH40         0x13C
-#define APBDEV_PMC_OSC_EDPD_OVER     0x1A4
-#define  PMC_OSC_EDPD_OVER_OSC_CTRL_OVER   BIT(22)
-#define APBDEV_PMC_CLK_OUT_CNTRL     0x1A8
-#define  PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN   BIT(2)
-#define  PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN   BIT(10)
-#define  PMC_CLK_OUT_CNTRL_CLK3_FORCE_EN   BIT(18)
-#define  PMC_CLK_OUT_CNTRL_CLK1_SRC_SEL(src) (((src) & 3) << 6)
-#define  PMC_CLK_OUT_CNTRL_CLK2_SRC_SEL(src) (((src) & 3) << 14)
-#define  PMC_CLK_OUT_CNTRL_CLK3_SRC_SEL(src) (((src) & 3) << 22)
-#define   OSC_DIV1                         0
-#define   OSC_DIV2                         1
-#define   OSC_DIV4                         2
-#define   OSC_CAR                          3
-#define APBDEV_PMC_RST_STATUS        0x1B4
-#define  PMC_RST_STATUS_MASK               7
-#define  PMC_RST_STATUS_POR                0
-#define  PMC_RST_STATUS_WATCHDOG           1
-#define  PMC_RST_STATUS_SENSOR             2
-#define  PMC_RST_STATUS_SW_MAIN            3
-#define  PMC_RST_STATUS_LP0                4
-#define  PMC_RST_STATUS_AOTAG              5
-#define APBDEV_PMC_IO_DPD_REQ        0x1B8
-#define  PMC_IO_DPD_REQ_DPD_IDLE           (0 << 30u)
-#define  PMC_IO_DPD_REQ_DPD_OFF            (1 << 30u)
-#define  PMC_IO_DPD_REQ_DPD_ON             (2 << 30u)
-#define APBDEV_PMC_IO_DPD2_REQ       0x1C0
-#define APBDEV_PMC_VDDP_SEL          0x1CC
-#define APBDEV_PMC_DDR_CFG           0x1D0
-#define APBDEV_PMC_SECURE_SCRATCH6   0x224
-#define APBDEV_PMC_SECURE_SCRATCH7   0x228
-#define APBDEV_PMC_SCRATCH45         0x234
-#define APBDEV_PMC_SCRATCH46         0x238
-#define APBDEV_PMC_SCRATCH49         0x244
-#define APBDEV_PMC_SCRATCH52         0x250
-#define APBDEV_PMC_SCRATCH53         0x254
-#define APBDEV_PMC_SCRATCH54         0x258
-#define APBDEV_PMC_SCRATCH55         0x25C
-#define APBDEV_PMC_TSC_MULT          0x2B4
-#define APBDEV_PMC_STICKY_BITS       0x2C0
-#define  PMC_STICKY_BITS_HDA_LPBK_DIS      BIT(0)
-#define APBDEV_PMC_SEC_DISABLE2      0x2C4
-#define APBDEV_PMC_WEAK_BIAS         0x2C8
-#define APBDEV_PMC_REG_SHORT         0x2CC
-#define APBDEV_PMC_SEC_DISABLE3      0x2D8
-#define APBDEV_PMC_SECURE_SCRATCH21  0x334
-#define  PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT BIT(4)
-#define APBDEV_PMC_SECURE_SCRATCH22  0x338 // AArch32 reset address.
-#define APBDEV_PMC_SECURE_SCRATCH32  0x360
-#define APBDEV_PMC_SECURE_SCRATCH34  0x368 // AArch64 reset address.
-#define APBDEV_PMC_SECURE_SCRATCH35  0x36C // AArch64 reset hi-address.
-#define APBDEV_PMC_SECURE_SCRATCH49  0x3A4
-#define APBDEV_PMC_CNTRL2            0x440
-#define  PMC_CNTRL2_WAKE_INT_EN            BIT(0)
-#define  PMC_CNTRL2_WAKE_DET_EN            BIT(9)
-#define  PMC_CNTRL2_SYSCLK_ORRIDE          BIT(10)
-#define  PMC_CNTRL2_HOLD_CKE_LOW_EN        BIT(12)
-#define  PMC_CNTRL2_ALLOW_PULSE_WAKE       BIT(14)
-#define APBDEV_PMC_FUSE_CONTROL      0x450
-#define  PMC_FUSE_CONTROL_PS18_LATCH_SET   BIT(8)
-#define  PMC_FUSE_CONTROL_PS18_LATCH_CLR   BIT(9)
-#define APBDEV_PMC_IO_DPD3_REQ       0x45C
-#define APBDEV_PMC_IO_DPD4_REQ       0x464
-#define APBDEV_PMC_UTMIP_PAD_CFG1    0x4C4
-#define APBDEV_PMC_UTMIP_PAD_CFG3    0x4CC
-#define APBDEV_PMC_DDR_CNTRL         0x4E4
-#define APBDEV_PMC_SEC_DISABLE4      0x5B0
-#define APBDEV_PMC_SEC_DISABLE5      0x5B4
-#define APBDEV_PMC_SEC_DISABLE6      0x5B8
-#define APBDEV_PMC_SEC_DISABLE7      0x5BC
-#define APBDEV_PMC_SEC_DISABLE8      0x5C0
-#define APBDEV_PMC_SEC_DISABLE9      0x5C4
-#define APBDEV_PMC_SEC_DISABLE10     0x5C8
-#define APBDEV_PMC_SCRATCH188        0x810
-#define APBDEV_PMC_SCRATCH190        0x818
-#define APBDEV_PMC_SCRATCH200        0x840
-#define  PMC_NX_PANIC_SAFE_MODE            0x20
-#define  PMC_NX_PANIC_BYPASS_FUSES         0x21
-#define APBDEV_PMC_SCRATCH201        0x844
-#define APBDEV_PMC_SCRATCH250        0x908
-#define APBDEV_PMC_SECURE_SCRATCH108 0xB08
-#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
-#define APBDEV_PMC_SECURE_SCRATCH110 0xB10
-#define APBDEV_PMC_SECURE_SCRATCH112 0xB18
-#define APBDEV_PMC_SECURE_SCRATCH113 0xB1C
-#define APBDEV_PMC_SECURE_SCRATCH114 0xB20
-#define APBDEV_PMC_SECURE_SCRATCH119 0xB34
-
-// Only in T210B01.
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE0 0xA48
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE1 0xA4C
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE2 0xA50
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE3 0xA54
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE4 0xA58
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE5 0xA5C
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE6 0xA60
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE7 0xA64
-#define APBDEV_PMC_SCRATCH_WRITE_DISABLE8 0xA68
-#define APBDEV_PMC_LED_BREATHING_CTRL         0xB48
-#define  PMC_LED_BREATHING_CTRL_ENABLE              BIT(0)
-#define  PMC_LED_BREATHING_CTRL_COUNTER1_EN         BIT(1)
-#define APBDEV_PMC_LED_BREATHING_SLOPE_STEPS  0xB4C
-#define APBDEV_PMC_LED_BREATHING_ON_COUNTER   0xB50
-#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER1 0xB54
-#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER0 0xB58
-#define  PMC_LED_BREATHING_COUNTER_HZ               32768
-#define APBDEV_PMC_LED_BREATHING_STATUS       0xB5C
-#define  PMC_LED_BREATHING_FSM_STATUS_MASK          0x7
-#define  PMC_LED_BREATHING_FSM_STS_IDLE             0
-#define  PMC_LED_BREATHING_FSM_STS_UP_RAMP          1
-#define  PMC_LED_BREATHING_FSM_STS_PLATEAU          2
-#define  PMC_LED_BREATHING_FSM_STS_DOWN_RAMP        3
-#define  PMC_LED_BREATHING_FSM_STS_SHORT_LOW_PERIOD 4
-#define  PMC_LED_BREATHING_FSM_STS_LONG_LOW_PERIOD  5
-#define APBDEV_PMC_TZRAM_PWR_CNTRL            0xBE8
-#define  PMC_TZRAM_PWR_CNTRL_SD                     BIT(0)
-#define APBDEV_PMC_TZRAM_SEC_DISABLE          0xBEC
-#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE      0xBF0
-#define  PMC_TZRAM_DISABLE_REG_WRITE                BIT(0)
-#define  PMC_TZRAM_DISABLE_REG_READ                 BIT(1)
+#include <soc/pmc_t210.h>
 
 typedef enum _pmc_sec_lock_t
 {

bdk/soc/pmc_lp0_t210.h

@@ -1,564 +0,0 @@
-/*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-#ifndef _TEGRA210_PMC_H_
-#define _TEGRA210_PMC_H_
-
-#include <utils/types.h>
-
-struct tegra_pmc_regs
-{
-	u32 cntrl;
-	u32 sec_disable;
-	u32 pmc_swrst;
-	u32 wake_mask;
-	u32 wake_lvl;
-	u32 wake_status;
-	u32 sw_wake_status;
-	u32 dpd_pads_oride;
-	u32 dpd_sample;
-	u32 dpd_enable;
-	u32 pwrgate_timer_off;
-	u32 clamp_status;
-	u32 pwrgate_toggle;
-	u32 remove_clamping_cmd;
-	u32 pwrgate_status;
-	u32 pwrgood_timer;
-	u32 blink_timer;
-	u32 no_iopower;
-	u32 pwr_det;
-	u32 pwr_det_latch;
-	u32 scratch0;
-	u32 scratch1;
-	u32 scratch2;
-	u32 scratch3;
-	u32 scratch4;
-	u32 scratch5;
-	u32 scratch6;
-	u32 scratch7;
-	u32 scratch8;
-	u32 scratch9;
-	u32 scratch10;
-	u32 scratch11;
-	u32 scratch12;
-	u32 scratch13;
-	u32 scratch14;
-	u32 scratch15;
-	u32 scratch16;
-	u32 scratch17;
-	u32 scratch18;
-	u32 scratch19;
-	u32 odmdata;
-	u32 scratch21;
-	u32 scratch22;
-	u32 scratch23;
-	u32 secure_scratch0;
-	u32 secure_scratch1;
-	u32 secure_scratch2;
-	u32 secure_scratch3;
-	u32 secure_scratch4;
-	u32 secure_scratch5;
-	u32 cpupwrgood_timer;
-	u32 cpupwroff_timer;
-	u32 pg_mask;
-	u32 pg_mask_1;
-	u32 auto_wake_lvl;
-	u32 auto_wake_lvl_mask;
-	u32 wake_delay;
-	u32 pwr_det_val;
-	u32 ddr_pwr;
-	u32 usb_debounce_del;
-	u32 usb_a0;
-	u32 crypto_op;
-	u32 pllp_wb0_override;
-	u32 scratch24;
-	u32 scratch25;
-	u32 scratch26;
-	u32 scratch27;
-	u32 scratch28;
-	u32 scratch29;
-	u32 scratch30;
-	u32 scratch31;
-	u32 scratch32;
-	u32 scratch33;
-	u32 scratch34;
-	u32 scratch35;
-	u32 scratch36;
-	u32 scratch37;
-	u32 scratch38;
-	u32 scratch39;
-	u32 scratch40;
-	u32 scratch41;
-	u32 scratch42;
-	u32 bondout_mirror[3];
-	u32 sys_33v_en;
-	u32 bondout_mirror_access;
-	u32 gate;
-	u32 wake2_mask;
-	u32 wake2_lvl;
-	u32 wake2_status;
-	u32 sw_wake2_status;
-	u32 auto_wake2_lvl_mask;
-	u32 pg_mask_2;
-	u32 pg_mask_ce1;
-	u32 pg_mask_ce2;
-	u32 pg_mask_ce3;
-	u32 pwrgate_timer_ce[7];
-	u32 pcx_edpd_cntrl;
-	u32 osc_edpd_over;
-	u32 clk_out_cntrl;
-	u32 sata_pwrgt;
-	u32 sensor_ctrl;
-	u32 rst_status;
-	u32 io_dpd_req;
-	u32 io_dpd_status;
-	u32 io_dpd2_req;
-	u32 io_dpd2_status;
-	u32 sel_dpd_tim;
-	u32 vddp_sel;
-	u32 ddr_cfg;
-	u32 e_no_vttgen;
-	u8 _rsv0[4];
-	u32 pllm_wb0_override_freq;
-	u32 test_pwrgate;
-	u32 pwrgate_timer_mult;
-	u32 dis_sel_dpd;
-	u32 utmip_uhsic_triggers;
-	u32 utmip_uhsic_saved_state;
-	u32 utmip_pad_cfg;
-	u32 utmip_term_pad_cfg;
-	u32 utmip_uhsic_sleep_cfg;
-	u32 utmip_uhsic_sleepwalk_cfg;
-	u32 utmip_sleepwalk_p[3];
-	u32 uhsic_sleepwalk_p0;
-	u32 utmip_uhsic_status;
-	u32 utmip_uhsic_fake;
-	u32 bondout_mirror3[5 - 3];
-	u32 secure_scratch6;
-	u32 secure_scratch7;
-	u32 scratch43;
-	u32 scratch44;
-	u32 scratch45;
-	u32 scratch46;
-	u32 scratch47;
-	u32 scratch48;
-	u32 scratch49;
-	u32 scratch50;
-	u32 scratch51;
-	u32 scratch52;
-	u32 scratch53;
-	u32 scratch54;
-	u32 scratch55;
-	u32 scratch0_eco;
-	u32 por_dpd_ctrl;
-	u32 scratch2_eco;
-	u32 utmip_uhsic_line_wakeup;
-	u32 utmip_bias_master_cntrl;
-	u32 utmip_master_config;
-	u32 td_pwrgate_inter_part_timer;
-	u32 utmip_uhsic2_triggers;
-	u32 utmip_uhsic2_saved_state;
-	u32 utmip_uhsic2_sleep_cfg;
-	u32 utmip_uhsic2_sleepwalk_cfg;
-	u32 uhsic2_sleepwalk_p1;
-	u32 utmip_uhsic2_status;
-	u32 utmip_uhsic2_fake;
-	u32 utmip_uhsic2_line_wakeup;
-	u32 utmip_master2_config;
-	u32 utmip_uhsic_rpd_cfg;
-	u32 pg_mask_ce0;
-	u32 pg_mask3[5 - 3];
-	u32 pllm_wb0_override2;
-	u32 tsc_mult;
-	u32 cpu_vsense_override;
-	u32 glb_amap_cfg;
-	u32 sticky_bits;
-	u32 sec_disable2;
-	u32 weak_bias;
-	u32 reg_short;
-	u32 pg_mask_andor;
-	u8 _rsv1[0x2c];
-	u32 secure_scratch8;	/* offset 0x300 */
-	u32 secure_scratch9;
-	u32 secure_scratch10;
-	u32 secure_scratch11;
-	u32 secure_scratch12;
-	u32 secure_scratch13;
-	u32 secure_scratch14;
-	u32 secure_scratch15;
-	u32 secure_scratch16;
-	u32 secure_scratch17;
-	u32 secure_scratch18;
-	u32 secure_scratch19;
-	u32 secure_scratch20;
-	u32 secure_scratch21;
-	u32 secure_scratch22;
-	u32 secure_scratch23;
-	u32 secure_scratch24;
-	u32 secure_scratch25;
-	u32 secure_scratch26;
-	u32 secure_scratch27;
-	u32 secure_scratch28;
-	u32 secure_scratch29;
-	u32 secure_scratch30;
-	u32 secure_scratch31;
-	u32 secure_scratch32;
-	u32 secure_scratch33;
-	u32 secure_scratch34;
-	u32 secure_scratch35;
-	u32 secure_scratch36;
-	u32 secure_scratch37;
-	u32 secure_scratch38;
-	u32 secure_scratch39;
-	u32 secure_scratch40;
-	u32 secure_scratch41;
-	u32 secure_scratch42;
-	u32 secure_scratch43;
-	u32 secure_scratch44;
-	u32 secure_scratch45;
-	u32 secure_scratch46;
-	u32 secure_scratch47;
-	u32 secure_scratch48;
-	u32 secure_scratch49;
-	u32 secure_scratch50;
-	u32 secure_scratch51;
-	u32 secure_scratch52;
-	u32 secure_scratch53;
-	u32 secure_scratch54;
-	u32 secure_scratch55;
-	u32 secure_scratch56;
-	u32 secure_scratch57;
-	u32 secure_scratch58;
-	u32 secure_scratch59;
-	u32 secure_scratch60;
-	u32 secure_scratch61;
-	u32 secure_scratch62;
-	u32 secure_scratch63;
-	u32 secure_scratch64;
-	u32 secure_scratch65;
-	u32 secure_scratch66;
-	u32 secure_scratch67;
-	u32 secure_scratch68;
-	u32 secure_scratch69;
-	u32 secure_scratch70;
-	u32 secure_scratch71;
-	u32 secure_scratch72;
-	u32 secure_scratch73;
-	u32 secure_scratch74;
-	u32 secure_scratch75;
-	u32 secure_scratch76;
-	u32 secure_scratch77;
-	u32 secure_scratch78;
-	u32 secure_scratch79;
-	u32 _rsv0x420[8];
-	u32 cntrl2;			/* 0x440 */
-	u32 _rsv0x444[2];
-	u32 event_counter;	/* 0x44C */
-	u32 fuse_control;
-	u32 scratch1_eco;
-	u32 _rsv0x458[1];
-	u32 io_dpd3_req;	/* 0x45C */
-	u32 io_dpd3_status;
-	u32 io_dpd4_req;
-	u32 io_dpd4_status;
-	u32 _rsv0x46C[30];
-	u32 ddr_cntrl;		/* 0x4E4 */
-	u32 _rsv0x4E8[70];
-	u32 scratch56;		/* 0x600 */
-	u32 scratch57;
-	u32 scratch58;
-	u32 scratch59;
-	u32 scratch60;
-	u32 scratch61;
-	u32 scratch62;
-	u32 scratch63;
-	u32 scratch64;
-	u32 scratch65;
-	u32 scratch66;
-	u32 scratch67;
-	u32 scratch68;
-	u32 scratch69;
-	u32 scratch70;
-	u32 scratch71;
-	u32 scratch72;
-	u32 scratch73;
-	u32 scratch74;
-	u32 scratch75;
-	u32 scratch76;
-	u32 scratch77;
-	u32 scratch78;
-	u32 scratch79;
-	u32 scratch80;
-	u32 scratch81;
-	u32 scratch82;
-	u32 scratch83;
-	u32 scratch84;
-	u32 scratch85;
-	u32 scratch86;
-	u32 scratch87;
-	u32 scratch88;
-	u32 scratch89;
-	u32 scratch90;
-	u32 scratch91;
-	u32 scratch92;
-	u32 scratch93;
-	u32 scratch94;
-	u32 scratch95;
-	u32 scratch96;
-	u32 scratch97;
-	u32 scratch98;
-	u32 scratch99;
-	u32 scratch100;
-	u32 scratch101;
-	u32 scratch102;
-	u32 scratch103;
-	u32 scratch104;
-	u32 scratch105;
-	u32 scratch106;
-	u32 scratch107;
-	u32 scratch108;
-	u32 scratch109;
-	u32 scratch110;
-	u32 scratch111;
-	u32 scratch112;
-	u32 scratch113;
-	u32 scratch114;
-	u32 scratch115;
-	u32 scratch116;
-	u32 scratch117;
-	u32 scratch118;
-	u32 scratch119;
-	u32 scratch120;		/* 0x700 */
-	u32 scratch121;
-	u32 scratch122;
-	u32 scratch123;
-	u32 scratch124;
-	u32 scratch125;
-	u32 scratch126;
-	u32 scratch127;
-	u32 scratch128;
-	u32 scratch129;
-	u32 scratch130;
-	u32 scratch131;
-	u32 scratch132;
-	u32 scratch133;
-	u32 scratch134;
-	u32 scratch135;
-	u32 scratch136;
-	u32 scratch137;
-	u32 scratch138;
-	u32 scratch139;
-	u32 scratch140;
-	u32 scratch141;
-	u32 scratch142;
-	u32 scratch143;
-	u32 scratch144;
-	u32 scratch145;
-	u32 scratch146;
-	u32 scratch147;
-	u32 scratch148;
-	u32 scratch149;
-	u32 scratch150;
-	u32 scratch151;
-	u32 scratch152;
-	u32 scratch153;
-	u32 scratch154;
-	u32 scratch155;
-	u32 scratch156;
-	u32 scratch157;
-	u32 scratch158;
-	u32 scratch159;
-	u32 scratch160;
-	u32 scratch161;
-	u32 scratch162;
-	u32 scratch163;
-	u32 scratch164;
-	u32 scratch165;
-	u32 scratch166;
-	u32 scratch167;
-	u32 scratch168;
-	u32 scratch169;
-	u32 scratch170;
-	u32 scratch171;
-	u32 scratch172;
-	u32 scratch173;
-	u32 scratch174;
-	u32 scratch175;
-	u32 scratch176;
-	u32 scratch177;
-	u32 scratch178;
-	u32 scratch179;
-	u32 scratch180;
-	u32 scratch181;
-	u32 scratch182;
-	u32 scratch183;
-	u32 scratch184;
-	u32 scratch185;
-	u32 scratch186;
-	u32 scratch187;
-	u32 scratch188;
-	u32 scratch189;
-	u32 scratch190;
-	u32 scratch191;
-	u32 scratch192;
-	u32 scratch193;
-	u32 scratch194;
-	u32 scratch195;
-	u32 scratch196;
-	u32 scratch197;
-	u32 scratch198;
-	u32 scratch199;
-	u32 scratch200;
-	u32 scratch201;
-	u32 scratch202;
-	u32 scratch203;
-	u32 scratch204;
-	u32 scratch205;
-	u32 scratch206;
-	u32 scratch207;
-	u32 scratch208;
-	u32 scratch209;
-	u32 scratch210;
-	u32 scratch211;
-	u32 scratch212;
-	u32 scratch213;
-	u32 scratch214;
-	u32 scratch215;
-	u32 scratch216;
-	u32 scratch217;
-	u32 scratch218;
-	u32 scratch219;
-	u32 scratch220;
-	u32 scratch221;
-	u32 scratch222;
-	u32 scratch223;
-	u32 scratch224;
-	u32 scratch225;
-	u32 scratch226;
-	u32 scratch227;
-	u32 scratch228;
-	u32 scratch229;
-	u32 scratch230;
-	u32 scratch231;
-	u32 scratch232;
-	u32 scratch233;
-	u32 scratch234;
-	u32 scratch235;
-	u32 scratch236;
-	u32 scratch237;
-	u32 scratch238;
-	u32 scratch239;
-	u32 scratch240;
-	u32 scratch241;
-	u32 scratch242;
-	u32 scratch243;
-	u32 scratch244;
-	u32 scratch245;
-	u32 scratch246;
-	u32 scratch247;
-	u32 scratch248;
-	u32 scratch249;
-	u32 scratch250;
-	u32 scratch251;
-	u32 scratch252;
-	u32 scratch253;
-	u32 scratch254;
-	u32 scratch255;
-	u32 scratch256;
-	u32 scratch257;
-	u32 scratch258;
-	u32 scratch259;
-	u32 scratch260;
-	u32 scratch261;
-	u32 scratch262;
-	u32 scratch263;
-	u32 scratch264;
-	u32 scratch265;
-	u32 scratch266;
-	u32 scratch267;
-	u32 scratch268;
-	u32 scratch269;
-	u32 scratch270;
-	u32 scratch271;
-	u32 scratch272;
-	u32 scratch273;
-	u32 scratch274;
-	u32 scratch275;
-	u32 scratch276;
-	u32 scratch277;
-	u32 scratch278;
-	u32 scratch279;
-	u32 scratch280;
-	u32 scratch281;
-	u32 scratch282;
-	u32 scratch283;
-	u32 scratch284;
-	u32 scratch285;
-	u32 scratch286;
-	u32 scratch287;
-	u32 scratch288;
-	u32 scratch289;
-	u32 scratch290;
-	u32 scratch291;
-	u32 scratch292;
-	u32 scratch293;
-	u32 scratch294;
-	u32 scratch295;
-	u32 scratch296;
-	u32 scratch297;
-	u32 scratch298;
-	u32 scratch299;			/* 0x9CC */
-	u32 _rsv0x9D0[50];
-	u32 secure_scratch80;	/* 0xa98 */
-	u32 secure_scratch81;
-	u32 secure_scratch82;
-	u32 secure_scratch83;
-	u32 secure_scratch84;
-	u32 secure_scratch85;
-	u32 secure_scratch86;
-	u32 secure_scratch87;
-	u32 secure_scratch88;
-	u32 secure_scratch89;
-	u32 secure_scratch90;
-	u32 secure_scratch91;
-	u32 secure_scratch92;
-	u32 secure_scratch93;
-	u32 secure_scratch94;
-	u32 secure_scratch95;
-	u32 secure_scratch96;
-	u32 secure_scratch97;
-	u32 secure_scratch98;
-	u32 secure_scratch99;
-	u32 secure_scratch100;
-	u32 secure_scratch101;
-	u32 secure_scratch102;
-	u32 secure_scratch103;
-	u32 secure_scratch104;
-	u32 secure_scratch105;
-	u32 secure_scratch106;
-	u32 secure_scratch107;
-	u32 secure_scratch108;
-	u32 secure_scratch109;
-	u32 secure_scratch110;
-	u32 secure_scratch111;
-	u32 secure_scratch112;
-	u32 secure_scratch113;
-	u32 secure_scratch114;
-	u32 secure_scratch115;
-	u32 secure_scratch116;
-	u32 secure_scratch117;
-	u32 secure_scratch118;
-	u32 secure_scratch119;
-};
-
-#endif	/* _TEGRA210_PMC_H_ */

bdk/soc/timer.c

@@ -22,7 +22,7 @@
 #include <soc/t210.h>
 #include <utils/types.h>
 
-#define EXCP_TYPE_ADDR 0x4003FFF8
+#define EXCP_TYPE_ADDR 0x4003FF18
 #define  EXCP_TYPE_WDT 0x544457 // "WDT".
 
 #define USE_RTC_TIMER

bdk/storage/emmc.c

@@ -79,7 +79,7 @@ int emmc_init_retry(bool power_cycle)
 	switch (emmc_mode)
 	{
 	case EMMC_INIT_FAIL: // Reset to max.
-		return 0;
+		return 1;
 	case EMMC_1BIT_HS52:
 		bus_width = SDMMC_BUS_WIDTH_1;
 		type = SDHCI_TIMING_MMC_HS52;
@@ -100,7 +100,7 @@ int emmc_init_retry(bool power_cycle)
 	return sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, bus_width, type);
 }
 
-bool emmc_initialize(bool power_cycle)
+int emmc_initialize(bool power_cycle)
 {
 	// Reset mode in case of previous failure.
 	if (emmc_mode == EMMC_INIT_FAIL)
@@ -109,12 +109,12 @@ bool emmc_initialize(bool power_cycle)
 	if (power_cycle)
 		emmc_end();
 
-	int res = !emmc_init_retry(false);
+	int res = emmc_init_retry(false);
 
 	while (true)
 	{
 		if (!res)
-			return true;
+			return 0;
 		else
 		{
 			emmc_errors[EMMC_ERROR_INIT_FAIL]++;
@@ -122,13 +122,13 @@ bool emmc_initialize(bool power_cycle)
 			if (emmc_mode == EMMC_INIT_FAIL)
 				break;
 			else
-				res = !emmc_init_retry(true);
+				res = emmc_init_retry(true);
 		}
 	}
 
 	emmc_end();
 
-	return false;
+	return 1;
 }
 
 int emmc_set_partition(u32 partition) { return sdmmc_storage_set_mmc_partition(&emmc_storage, partition); }
@@ -190,7 +190,7 @@ int emmc_part_read(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf
 {
 	// The last LBA is inclusive.
 	if (part->lba_start + sector_off > part->lba_end)
-		return 0;
+		return 1;
 
 #ifdef BDK_EMUMMC_ENABLE
 	return emummc_storage_read(part->lba_start + sector_off, num_sectors, buf);
@@ -203,7 +203,7 @@ int emmc_part_write(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *bu
 {
 	// The last LBA is inclusive.
 	if (part->lba_start + sector_off > part->lba_end)
-		return 0;
+		return 1;
 
 #ifdef BDK_EMUMMC_ENABLE
 	return emummc_storage_write(part->lba_start + sector_off, num_sectors, buf);

bdk/storage/emmc.h

@@ -62,7 +62,7 @@ void emmc_error_count_increment(u8 type);
 u16 *emmc_get_error_count();
 u32  emmc_get_mode();
 int  emmc_init_retry(bool power_cycle);
-bool emmc_initialize(bool power_cycle);
+int  emmc_initialize(bool power_cycle);
 int  emmc_set_partition(u32 partition);
 void emmc_end();
 

bdk/storage/mmc_def.h

@@ -416,8 +416,8 @@
 /*
  * BKOPS modes
  */
-#define EXT_CSD_MANUAL_BKOPS_MASK	0x01
-#define EXT_CSD_AUTO_BKOPS_MASK		0x02
+#define EXT_CSD_BKOPS_MANUAL	0x01 /* STICKY! */
+#define EXT_CSD_BKOPS_AUTO		0x02
 
 /*
  * Command Queue

bdk/storage/nx_emmc_bis.c

@@ -91,7 +91,7 @@ static int nx_emmc_bis_write_block(u32 sector, u32 count, void *buff, bool flush
 	}
 
 	// Encrypt cluster.
-	if (!se_aes_crypt_xts_sec_nx(ks_tweak, ks_crypt, ENCRYPT, cluster, tweak, true, sector_in_cluster, bis_cache->dma_buff, buff, count * EMMC_BLOCKSIZE))
+	if (se_aes_crypt_xts_sec_nx(ks_tweak, ks_crypt, ENCRYPT, cluster, tweak, true, sector_in_cluster, bis_cache->dma_buff, buff, count * EMMC_BLOCKSIZE))
 		return 1; // Encryption error.
 
 	// If not reading from cache, do a regular read and decrypt.
@@ -99,7 +99,7 @@ static int nx_emmc_bis_write_block(u32 sector, u32 count, void *buff, bool flush
 		res = emmc_part_write(system_part, sector, count, bis_cache->dma_buff);
 	else
 		res = sdmmc_storage_write(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff);
-	if (!res)
+	if (res)
 		return 1; // R/W error.
 
 	// Mark cache entry not dirty if write succeeds.
@@ -159,7 +159,7 @@ static int nx_emmc_bis_read_block_normal(u32 sector, u32 count, void *buff)
 		res = emmc_part_read(system_part, sector, count, bis_cache->dma_buff);
 	else
 		res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff);
-	if (!res)
+	if (res)
 		return 1; // R/W error.
 
 	if (prev_cluster != cluster) // Sector in different cluster than last read.
@@ -177,7 +177,7 @@ static int nx_emmc_bis_read_block_normal(u32 sector, u32 count, void *buff)
 		tweak_exp = sector_in_cluster;
 
 	// Maximum one cluster (1 XTS crypto block 16KB).
-	if (!se_aes_crypt_xts_sec_nx(ks_tweak, ks_crypt, DECRYPT, prev_cluster, tweak, regen_tweak, tweak_exp, buff, bis_cache->dma_buff, count * EMMC_BLOCKSIZE))
+	if (se_aes_crypt_xts_sec_nx(ks_tweak, ks_crypt, DECRYPT, prev_cluster, tweak, regen_tweak, tweak_exp, buff, bis_cache->dma_buff, count * EMMC_BLOCKSIZE))
 		return 1; // R/W error.
 
 	prev_sector = sector + count - 1;
@@ -216,11 +216,11 @@ static int nx_emmc_bis_read_block_cached(u32 sector, u32 count, void *buff)
 		res = emmc_part_read(system_part, cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff);
 	else
 		res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff);
-	if (!res)
+	if (res)
 		return 1; // R/W error.
 
 	// Decrypt cluster.
-	if (!se_aes_crypt_xts_sec_nx(ks_tweak, ks_crypt, DECRYPT, cluster, cache_tweak, true, 0, bis_cache->dma_buff, bis_cache->dma_buff, BIS_CLUSTER_SIZE))
+	if (se_aes_crypt_xts_sec_nx(ks_tweak, ks_crypt, DECRYPT, cluster, cache_tweak, true, 0, bis_cache->dma_buff, bis_cache->dma_buff, BIS_CLUSTER_SIZE))
 		return 1; // Decryption error.
 
 	// Copy to cluster cache.
@@ -258,14 +258,14 @@ int nx_emmc_bis_read(u32 sector, u32 count, void *buff)
 		u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access.
 
 		if (nx_emmc_bis_read_block(curr_sct, sct_cnt, buf))
-			return 0;
+			return 1;
 
 		count    -= sct_cnt;
 		curr_sct += sct_cnt;
 		buf      += sct_cnt * EMMC_BLOCKSIZE;
 	}
 
-	return 1;
+	return 0;
 }
 
 int nx_emmc_bis_write(u32 sector, u32 count, void *buff)
@@ -282,14 +282,14 @@ int nx_emmc_bis_write(u32 sector, u32 count, void *buff)
 		u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access.
 
 		if (nx_emmc_bis_write_block(curr_sct, sct_cnt, buf, false))
-			return 0;
+			return 1;
 
 		count    -= sct_cnt;
 		curr_sct += sct_cnt;
 		buf      += sct_cnt * EMMC_BLOCKSIZE;
 	}
 
-	return 1;
+	return 0;
 }
 
 void nx_emmc_bis_init(emmc_part_t *part, bool enable_cache, u32 emummc_offset)

bdk/storage/sd.c

@@ -103,7 +103,7 @@ int sd_init_retry(bool power_cycle)
 	switch (sd_mode)
 	{
 	case SD_INIT_FAIL: // Reset to max.
-		return 0;
+		return 1;
 
 	case SD_1BIT_HS25:
 		bus_width = SDMMC_BUS_WIDTH_1;
@@ -134,7 +134,7 @@ int sd_init_retry(bool power_cycle)
 	}
 
 	int res = sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type);
-	if (res)
+	if (!res)
 	{
 		sd_init_done    = true;
 		insertion_event = true;
@@ -145,17 +145,17 @@ int sd_init_retry(bool power_cycle)
 	return res;
 }
 
-bool sd_initialize(bool power_cycle)
+int sd_initialize(bool power_cycle)
 {
 	if (power_cycle)
 		sdmmc_storage_end(&sd_storage);
 
-	int res = !sd_init_retry(false);
+	int res = sd_init_retry(false);
 
 	while (true)
 	{
 		if (!res)
-			return true;
+			return 0;
 		else if (!sdmmc_get_sd_inserted()) // SD Card is not inserted.
 		{
 			sd_mode = SD_DEFAULT_SPEED;
@@ -168,24 +168,24 @@ bool sd_initialize(bool power_cycle)
 			if (sd_mode == SD_INIT_FAIL)
 				break;
 			else
-				res = !sd_init_retry(true);
+				res = sd_init_retry(true);
 		}
 	}
 
 	sdmmc_storage_end(&sd_storage);
 
-	return false;
+	return 1;
 }
 
-bool sd_mount()
+int sd_mount()
 {
 	if (sd_init_done && sd_mounted)
-		return true;
+		return 0;
 
 	int res = 0;
 
 	if (!sd_init_done)
-		res = !sd_initialize(false);
+		res = sd_initialize(false);
 
 	if (res)
 	{
@@ -203,7 +203,7 @@ bool sd_mount()
 		if (res == FR_OK)
 		{
 			sd_mounted = true;
-			return true;
+			return 0;
 		}
 		else
 		{
@@ -212,7 +212,7 @@ bool sd_mount()
 		}
 	}
 
-	return false;
+	return 1;
 }
 
 static void _sd_deinit(bool deinit)

bdk/storage/sd.h

@@ -55,8 +55,8 @@ bool sd_get_card_initialized();
 bool sd_get_card_mounted();
 u32  sd_get_mode();
 int  sd_init_retry(bool power_cycle);
-bool sd_initialize(bool power_cycle);
-bool sd_mount();
+int  sd_initialize(bool power_cycle);
+int  sd_mount();
 void sd_unmount();
 void sd_end();
 bool sd_is_gpt();

bdk/storage/sdmmc.h

@@ -143,9 +143,8 @@ typedef struct _mmc_csd
 
 typedef struct _mmc_ext_csd
 {
-	//u8  bkops;        /* background support bit */
-	//u8  bkops_en;     /* manual bkops enable bit */
-	//u8  bkops_status; /* 246 */
+	u8  bkops;        /* background support bit */
+	u8  bkops_en;     /* manual bkops enable bit */
 	u8  rev;
 	u8  ext_struct;   /* 194 */
 	u8  card_type;    /* 196 */
@@ -193,6 +192,7 @@ typedef struct _sd_ext_reg_t
 typedef struct _sdmmc_storage_t
 {
 	sdmmc_t *sdmmc;
+
 	int initialized;
 	int is_low_voltage;
 	int has_sector_access;
@@ -200,10 +200,11 @@ typedef struct _sdmmc_storage_t
 	u32 sec_cnt;
 	u32 partition;
 	u32 max_power;
-	u8  raw_cid[0x10];
-	u8  raw_csd[0x10];
-	u8  raw_scr[8];
-	u8  raw_ssr[0x40];
+	u8  raw_cid[0x10]                    __attribute__((aligned(SDMMC_ADMA_ADDR_ALIGN)));
+	u8  raw_csd[0x10]                    __attribute__((aligned(SDMMC_ADMA_ADDR_ALIGN)));
+	u8  raw_scr[8]                       __attribute__((aligned(SDMMC_ADMA_ADDR_ALIGN)));
+	u8  raw_ssr[SDMMC_CMD_BLOCKSIZE]     __attribute__((aligned(SDMMC_ADMA_ADDR_ALIGN)));
+	u8  raw_ext_csd[SDMMC_DAT_BLOCKSIZE] __attribute__((aligned(SDMMC_ADMA_ADDR_ALIGN)));
 	mmc_cid_t     cid;
 	mmc_csd_t     csd;
 	mmc_ext_csd_t ext_csd;
@@ -232,12 +233,12 @@ int  sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc);
 int  sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg);
 int  sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf);
 
-int  mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf);
+int  mmc_storage_get_ext_csd(sdmmc_storage_t *storage);
 
 int  sd_storage_get_ext_reg(sdmmc_storage_t *storage, u8 fno, u8 page, u16 offset, u32 len, void *buf);
 int  sd_storage_get_fmodes(sdmmc_storage_t *storage, u8 *buf, sd_func_modes_t *functions);
-int  sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf);
-int  sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf);
+int  sd_storage_get_scr(sdmmc_storage_t *storage);
+int  sd_storage_get_ssr(sdmmc_storage_t *storage);
 u32  sd_storage_get_ssr_au(sdmmc_storage_t *storage);
 
 void sd_storage_get_ext_regs(sdmmc_storage_t *storage, u8 *buf);

bdk/storage/sdmmc_driver.c

@@ -70,13 +70,13 @@ static int _sdmmc_set_io_power(sdmmc_t *sdmmc, u32 power)
 		break;
 
 	default:
-		return 0;
+		return 1;
 	}
 
 	if (power != SDMMC_POWER_OFF)
 		sdmmc->regs->pwrcon |= SDHCI_POWER_ON;
 
-	return 1;
+	return 0;
 }
 
 u32 sdmmc_get_bus_width(sdmmc_t *sdmmc)
@@ -121,8 +121,9 @@ static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
 
 	if (type == SDHCI_TIMING_MMC_HS400)
 	{
+		// Tap is saved during HS200 switch.
 		if (!sdmmc->venclkctl_set)
-			return 0;
+			return 1;
 
 		tap_val = sdmmc->venclkctl_tap;
 	}
@@ -131,7 +132,7 @@ static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
 
 	sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & ~0xFF0000) | (tap_val << 16);
 
-	return 1;
+	return 0;
 }
 
 static void _sdmmc_commit_changes(sdmmc_t *sdmmc)
@@ -236,7 +237,7 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power)
 
 static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
 {
-	int result = 1, should_disable_sd_clock = 0;
+	int res = 0, should_disable_sd_clock = 0;
 
 	if (!(sdmmc->regs->clkcon & SDHCI_CLOCK_CARD_EN))
 	{
@@ -256,7 +257,7 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
 	{
 		if (get_tmr_ms() > timeout)
 		{
-			result = 0;
+			res = 1;
 			goto out;
 		}
 	}
@@ -266,15 +267,16 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
 	{
 		if (get_tmr_ms() > timeout)
 		{
-			result = 0;
+			res = 1;
 			goto out;
 		}
 	}
 
-out:;
+out:
 	if (should_disable_sd_clock)
 		sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
-	return result;
+
+	return res;
 }
 
 static void _sdmmc_reset_cmd_data(sdmmc_t *sdmmc)
@@ -389,7 +391,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
 	if (type == SDHCI_TIMING_MMC_HS400)
 		return _sdmmc_dll_cal_execute(sdmmc);
 
-	return 1;
+	return 0;
 }
 
 static void _sdmmc_card_clock_enable(sdmmc_t *sdmmc)
@@ -455,16 +457,16 @@ static int _sdmmc_cache_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 type)
 		break;
 
 	default:
-		return 0;
+		return 1;
 	}
 
-	return 1;
+	return 0;
 }
 
 int sdmmc_get_cached_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 type)
 {
-	if (!rsp || sdmmc->expected_rsp_type != type)
-		return 0;
+	if (sdmmc->expected_rsp_type != type)
+		return 1;
 
 	switch (type)
 	{
@@ -481,10 +483,10 @@ int sdmmc_get_cached_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 type)
 		break;
 
 	default:
-		return 0;
+		return 1;
 	}
 
-	return 1;
+	return 0;
 }
 
 static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat)
@@ -496,7 +498,7 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat)
 		if (get_tmr_ms() > timeout)
 		{
 			_sdmmc_reset_cmd_data(sdmmc);
-			return 0;
+			return 1;
 		}
 
 	if (wait_dat)
@@ -506,11 +508,11 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat)
 			if (get_tmr_ms() > timeout)
 			{
 				_sdmmc_reset_cmd_data(sdmmc);
-				return 0;
+				return 1;
 			}
 	}
 
-	return 1;
+	return 0;
 }
 
 static int _sdmmc_wait_card_busy(sdmmc_t *sdmmc)
@@ -522,10 +524,10 @@ static int _sdmmc_wait_card_busy(sdmmc_t *sdmmc)
 		if (get_tmr_ms() > timeout)
 		{
 			_sdmmc_reset_cmd_data(sdmmc);
-			return 0;
+			return 1;
 		}
 
-	return 1;
+	return 0;
 }
 
 static int _sdmmc_setup_read_small_block(sdmmc_t *sdmmc)
@@ -533,7 +535,7 @@ static int _sdmmc_setup_read_small_block(sdmmc_t *sdmmc)
 	switch (sdmmc_get_bus_width(sdmmc))
 	{
 	case SDMMC_BUS_WIDTH_1:
-		return 0;
+		return 1;
 
 	case SDMMC_BUS_WIDTH_4:
 		sdmmc->regs->blksize = 64;
@@ -547,7 +549,7 @@ static int _sdmmc_setup_read_small_block(sdmmc_t *sdmmc)
 	sdmmc->regs->blkcnt = 1;
 	sdmmc->regs->trnmod = SDHCI_TRNS_READ;
 
-	return 1;
+	return 0;
 }
 
 static int _sdmmc_send_cmd(sdmmc_t *sdmmc, const sdmmc_cmd_t *cmd, bool is_data_present)
@@ -577,7 +579,7 @@ static int _sdmmc_send_cmd(sdmmc_t *sdmmc, const sdmmc_cmd_t *cmd, bool is_data_
 		break;
 
 	default:
-		return 0;
+		return 1;
 	}
 
 	if (is_data_present)
@@ -586,7 +588,7 @@ static int _sdmmc_send_cmd(sdmmc_t *sdmmc, const sdmmc_cmd_t *cmd, bool is_data_
 	sdmmc->regs->argument = cmd->arg;
 	sdmmc->regs->cmdreg   = SDHCI_CMD_IDX(cmd->cmd) | cmdflags;
 
-	return 1;
+	return 0;
 }
 
 static void _sdmmc_send_tuning_cmd(sdmmc_t *sdmmc, u32 cmd)
@@ -601,8 +603,8 @@ static void _sdmmc_send_tuning_cmd(sdmmc_t *sdmmc, u32 cmd)
 
 static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd, u32 tap)
 {
-	if (!_sdmmc_wait_cmd_data_inhibit(sdmmc, true))
-		return 0;
+	if (_sdmmc_wait_cmd_data_inhibit(sdmmc, true))
+		return 1;
 
 	_sdmmc_setup_read_small_block(sdmmc);
 
@@ -612,7 +614,7 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd, u32 tap)
 
 #ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
 	// Set tap if manual tuning.
-	if (tap != HW_TAP_TUNING)
+	if (tap != SDMMC_HW_TAP_TUNING)
 	{
 		sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
 		sdmmc->regs->venclkctl   = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (tap << 16);
@@ -632,13 +634,15 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd, u32 tap)
 	u32 timeout = get_tmr_us() + 5000;
 	while (get_tmr_us() < timeout)
 	{
+		// Check if we got valid data.
 		if (sdmmc->regs->norintsts & SDHCI_INT_DATA_AVAIL)
 		{
 			sdmmc->regs->norintsts = SDHCI_INT_DATA_AVAIL;
 			sdmmc->regs->norintstsen &= ~SDHCI_INT_DATA_AVAIL;
 			_sdmmc_commit_changes(sdmmc);
 			usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
-			return 1;
+
+			return 0;
 		}
 	}
 
@@ -648,7 +652,7 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd, u32 tap)
 	_sdmmc_commit_changes(sdmmc);
 	usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 
-	return 0;
+	return 1;
 }
 
 #ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
@@ -662,7 +666,7 @@ typedef struct _sdmmc_manual_tuning_t
 
 static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *tuning)
 {
-	u32 tap_start = INVALID_TAP;
+	u32 tap_start = SDMMC_INVALID_TAP;
 	u32 win_size  = 0;
 	u32 best_tap  = 0;
 	u32 best_size = 0;
@@ -673,14 +677,14 @@ static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *t
 		u32 stable = tuning->result[i / 32] & BIT(i % 32);
 		if (stable && !iter_end)
 		{
-			if (tap_start == INVALID_TAP)
+			if (tap_start == SDMMC_INVALID_TAP)
 				tap_start = i;
 
 			win_size++;
 		}
 		else
 		{
-			if (tap_start != INVALID_TAP)
+			if (tap_start != SDMMC_INVALID_TAP)
 			{
 				u32 tap_end = !iter_end ? (i - 1) : i;
 
@@ -691,7 +695,7 @@ static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *t
 					best_size = win_size + iter_end;
 				}
 
-				tap_start = INVALID_TAP;
+				tap_start = SDMMC_INVALID_TAP;
 				win_size  = 0;
 			}
 		}
@@ -699,8 +703,8 @@ static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *t
 
 
 	// Check if failed or window too small.
-	if (!best_tap || best_size < SAMPLING_WINDOW_SIZE_MIN)
-		return 0;
+	if (!best_tap || best_size < SDMMC_SAMPLE_WIN_SIZE_MIN)
+		return 1;
 
 	sdmmc->regs->clkcon     &= ~SDHCI_CLOCK_CARD_EN;
 	sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
@@ -711,7 +715,7 @@ static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *t
 	sdmmc->regs->ventunctl0 |=  SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
 	sdmmc->regs->clkcon     |= SDHCI_CLOCK_CARD_EN;
 
-	return 1;
+	return 0;
 }
 
 /*
@@ -758,7 +762,7 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
 	u32 num_iter, flag;
 
 	if (sdmmc->powersave_enabled)
-		return 0;
+		return 1;
 
 	switch (type)
 	{
@@ -779,7 +783,7 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
 	case SDHCI_TIMING_MMC_HS400:
 	case SDHCI_TIMING_UHS_SDR12:
 	case SDHCI_TIMING_UHS_SDR25:
-		return 1;
+		return 0;
 
 #ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
 	case SDHCI_TIMING_UHS_DDR200:
@@ -787,7 +791,7 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
 #endif
 
 	default:
-		return 0;
+		return 1;
 	}
 
 	sdmmc->regs->ventunctl1  = 0; // step_size 1.
@@ -799,16 +803,16 @@ int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
 
 	for (u32 i = 0; i < num_iter; i++)
 	{
-		_sdmmc_tuning_execute_once(sdmmc, cmd, HW_TAP_TUNING);
+		_sdmmc_tuning_execute_once(sdmmc, cmd, SDMMC_HW_TAP_TUNING);
 
 		if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING))
 			break;
 	}
 
 	if (sdmmc->regs->hostctl2 & SDHCI_CTRL_TUNED_CLK)
-		return 1;
+		return 0;
 
-	return 0;
+	return 1;
 }
 
 static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
@@ -820,7 +824,7 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
 	while (!(sdmmc->regs->clkcon & SDHCI_CLOCK_INT_STABLE))
 	{
 		if (get_tmr_ms() > timeout)
-			return 0;
+			return 1;
 	}
 
 	sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_PRESET_VAL_EN;
@@ -829,13 +833,13 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
 	sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN;
 
 	if (!(sdmmc->regs->capareg & SDHCI_CAP_64BIT))
-		return 0;
+		return 1;
 
 	sdmmc->regs->hostctl2  |= SDHCI_ADDRESSING_64BIT_EN;
 	sdmmc->regs->hostctl   &= ~SDHCI_CTRL_DMA_MASK; // Use SDMA. Host V4 enabled so adma address regs in use.
 	sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 14; // TMCLK * 2^27.
 
-	return 1;
+	return 0;
 }
 
 static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
@@ -848,7 +852,7 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
 	case SDMMC_2:
 	case SDMMC_4:
 		if (power != SDMMC_POWER_1_8)
-			return 0;
+			return 1;
 		off_pd = 5;
 		off_pu = 5;
 		break;
@@ -876,12 +880,12 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
 			}
 		}
 		else
-			return 0;
+			return 1;
 		break;
 	}
 
 	sdmmc->regs->autocalcfg = (sdmmc->regs->autocalcfg & 0xFFFF8080) | (off_pd << 8) | off_pu;
-	return 1;
+	return 0;
 }
 
 static void _sdmmc_enable_interrupts(sdmmc_t *sdmmc)
@@ -935,25 +939,25 @@ static int _sdmmc_wait_response(sdmmc_t *sdmmc)
 	u32 timeout = get_tmr_ms() + 2000;
 	while (true)
 	{
-		u32 result = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE);
-		if (result == SDMMC_MASKINT_MASKED)
+		u32 res = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE);
+		if (res == SDMMC_MASKINT_MASKED)
 			break;
-		if (result != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout)
+		if (res != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout)
 		{
 			_sdmmc_reset_cmd_data(sdmmc);
-			return 0;
+			return 1;
 		}
 	}
 
-	return 1;
+	return 0;
 }
 
 static int _sdmmc_stop_transmission_inner(sdmmc_t *sdmmc, u32 *rsp)
 {
 	sdmmc_cmd_t cmd;
 
-	if (!_sdmmc_wait_cmd_data_inhibit(sdmmc, false))
-		return 0;
+	if (_sdmmc_wait_cmd_data_inhibit(sdmmc, false))
+		return 1;
 
 	_sdmmc_enable_interrupts(sdmmc);
 
@@ -964,11 +968,11 @@ static int _sdmmc_stop_transmission_inner(sdmmc_t *sdmmc, u32 *rsp)
 
 	_sdmmc_send_cmd(sdmmc, &cmd, false);
 
-	int result = _sdmmc_wait_response(sdmmc);
+	int res = _sdmmc_wait_response(sdmmc);
 	_sdmmc_mask_interrupts(sdmmc);
 
-	if (!result)
-		return 0;
+	if (res)
+		return 1;
 
 	_sdmmc_cache_rsp(sdmmc, rsp, SDMMC_RSP_TYPE_1);
 
@@ -978,7 +982,7 @@ static int _sdmmc_stop_transmission_inner(sdmmc_t *sdmmc, u32 *rsp)
 int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp)
 {
 	if (!sdmmc->card_clock_enabled)
-		return 0;
+		return 1;
 
 	// Recalibrate periodically if needed.
 	if (sdmmc->periodic_calibration && sdmmc->powersave_enabled)
@@ -993,35 +997,35 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp)
 		usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 	}
 
-	int result = _sdmmc_stop_transmission_inner(sdmmc, rsp);
+	int res = _sdmmc_stop_transmission_inner(sdmmc, rsp);
 	usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 
 	if (should_disable_sd_clock)
 		sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
 
-	return result;
+	return res;
 }
 
-static int _sdmmc_config_sdma(sdmmc_t *sdmmc, u32 *blkcnt_out, const sdmmc_req_t *req)
+static int _sdmmc_config_sdma(sdmmc_t *sdmmc, u32 *blkcnt_out, const sdmmc_req_t *request)
 {
-	if (!req->blksize || !req->num_sectors)
-		return 0;
+	if (!request->blksize || !request->num_sectors)
+		return 1;
 
-	u32 blkcnt = req->num_sectors;
+	u32 blkcnt = request->num_sectors;
 	if (blkcnt >= SDMMC_HMAX_BLOCKNUM)
 		blkcnt = SDMMC_HMAX_BLOCKNUM;
-	u32 admaaddr = (u32)req->buf;
+	u32 admaaddr = (u32)request->buf;
 
 	// Check alignment.
 	if (admaaddr & 7)
-		return 0;
+		return 1;
 
 	sdmmc->regs->admaaddr = admaaddr;
 	sdmmc->regs->admaaddr_hi = 0;
 
 	sdmmc->dma_addr_next = ALIGN_DOWN((admaaddr + SZ_512K), SZ_512K);
 
-	sdmmc->regs->blksize = req->blksize | (7u << 12); // SDMA DMA 512KB Boundary (Detects A18 carry out).
+	sdmmc->regs->blksize = request->blksize | (7u << 12); // SDMA DMA 512KB Boundary (Detects A18 carry out).
 	sdmmc->regs->blkcnt  = blkcnt;
 
 	if (blkcnt_out)
@@ -1030,22 +1034,22 @@ static int _sdmmc_config_sdma(sdmmc_t *sdmmc, u32 *blkcnt_out, const sdmmc_req_t
 	u32 trnmode = SDHCI_TRNS_DMA | SDHCI_TRNS_RTYPE_R1;
 
 	// Set multiblock request.
-	if (req->is_multi_block)
+	if (request->is_multi_block)
 		trnmode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
 
 	// Set request direction.
-	if (!req->is_write)
+	if (!request->is_write)
 		trnmode |= SDHCI_TRNS_READ;
 
 	// Automatic send of stop transmission or set block count cmd.
-	if (req->is_auto_stop_trn)
+	if (request->is_auto_stop_trn)
 		trnmode |= SDHCI_TRNS_AUTO_CMD12;
-	//else if (req->is_auto_set_blkcnt)
+	//else if (request->is_auto_set_blkcnt)
 	//	trnmode |= SDHCI_TRNS_AUTO_CMD23;
 
 	sdmmc->regs->trnmod = trnmode;
 
-	return 1;
+	return 0;
 }
 
 static int _sdmmc_update_sdma(sdmmc_t *sdmmc)
@@ -1057,17 +1061,17 @@ static int _sdmmc_update_sdma(sdmmc_t *sdmmc)
 		u32 timeout = get_tmr_ms() + 1500;
 		do
 		{
-			u32 result = SDMMC_MASKINT_MASKED;
+			u32 res = SDMMC_MASKINT_MASKED;
 			while (true)
 			{
 				u16 intr = 0;
-				result = _sdmmc_check_mask_interrupt(sdmmc, &intr,
+				res = _sdmmc_check_mask_interrupt(sdmmc, &intr,
 					SDHCI_INT_DATA_END | SDHCI_INT_DMA_END);
-				if (result != SDMMC_MASKINT_MASKED)
+				if (res != SDMMC_MASKINT_MASKED)
 					break;
 
 				if (intr & SDHCI_INT_DATA_END)
-					return 1; // Transfer complete.
+					return 0; // Transfer complete.
 
 				if (intr & SDHCI_INT_DMA_END)
 				{
@@ -1078,39 +1082,39 @@ static int _sdmmc_update_sdma(sdmmc_t *sdmmc)
 				}
 			}
 
-			if (result != SDMMC_MASKINT_NOERROR)
+			if (res != SDMMC_MASKINT_NOERROR)
 			{
 #ifdef ERROR_EXTRA_PRINTING
 				EPRINTFARGS("SDMMC%d: int error!", sdmmc->id + 1);
 #endif
 				_sdmmc_reset_cmd_data(sdmmc);
 
-				return 0;
+				return 1;
 			}
 		} while (get_tmr_ms() < timeout);
 	} while (sdmmc->regs->blkcnt != blkcnt);
 
 	_sdmmc_reset_cmd_data(sdmmc);
 
-	return 0;
+	return 1;
 }
 
-static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out)
+static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *request, u32 *blkcnt_out)
 {
-	bool has_req_or_check_busy = req || cmd->check_busy;
-	if (!_sdmmc_wait_cmd_data_inhibit(sdmmc, has_req_or_check_busy))
-		return 0;
+	bool has_req_or_check_busy = request || cmd->check_busy;
+	if (_sdmmc_wait_cmd_data_inhibit(sdmmc, has_req_or_check_busy))
+		return 1;
 
 	u32 blkcnt = 0;
 	bool is_data_present = false;
-	if (req)
+	if (request)
 	{
-		if (!_sdmmc_config_sdma(sdmmc, &blkcnt, req))
+		if (_sdmmc_config_sdma(sdmmc, &blkcnt, request))
 		{
 #ifdef ERROR_EXTRA_PRINTING
 			EPRINTFARGS("SDMMC%d: DMA Wrong cfg!", sdmmc->id + 1);
 #endif
-			return 0;
+			return 1;
 		}
 
 		// Flush cache before starting the transfer.
@@ -1121,37 +1125,34 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
 
 	_sdmmc_enable_interrupts(sdmmc);
 
-	if (!_sdmmc_send_cmd(sdmmc, cmd, is_data_present))
+	if (_sdmmc_send_cmd(sdmmc, cmd, is_data_present))
 	{
 #ifdef ERROR_EXTRA_PRINTING
 		EPRINTFARGS("SDMMC%d: Wrong Response type %08X!", sdmmc->id + 1, cmd->rsp_type);
 #endif
-		return 0;
+		return 1;
 	}
 
-	int result = _sdmmc_wait_response(sdmmc);
+	int res = _sdmmc_wait_response(sdmmc);
 #ifdef ERROR_EXTRA_PRINTING
-	if (!result)
+	if (res)
 		EPRINTFARGS("SDMMC%d: Transfer error!", sdmmc->id + 1);
 #endif
-	DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
+	DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", res,
 		sdmmc->regs->rspreg[0], sdmmc->regs->rspreg[1], sdmmc->regs->rspreg[2], sdmmc->regs->rspreg[3]);
-	if (result)
+
+	if (!res)
 	{
 		if (cmd->rsp_type)
 		{
 			sdmmc->expected_rsp_type = cmd->rsp_type;
-			result = _sdmmc_cache_rsp(sdmmc, sdmmc->rsp, cmd->rsp_type);
-#ifdef ERROR_EXTRA_PRINTING
-			if (!result)
-				EPRINTFARGS("SDMMC%d: Unknown response type!", sdmmc->id + 1);
-#endif
+			res = _sdmmc_cache_rsp(sdmmc, sdmmc->rsp, cmd->rsp_type);
 		}
-		if (req && result)
+		if (request && !res)
 		{
-			result = _sdmmc_update_sdma(sdmmc);
+			res = _sdmmc_update_sdma(sdmmc);
 #ifdef ERROR_EXTRA_PRINTING
-			if (!result)
+			if (res)
 				EPRINTFARGS("SDMMC%d: DMA Update failed!", sdmmc->id + 1);
 #endif
 		}
@@ -1159,9 +1160,9 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
 
 	_sdmmc_mask_interrupts(sdmmc);
 
-	if (result)
+	if (!res)
 	{
-		if (req)
+		if (request)
 		{
 			// Invalidate cache after transfer.
 			bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false);
@@ -1169,22 +1170,21 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
 			if (blkcnt_out)
 				*blkcnt_out = blkcnt;
 
-			if (req->is_auto_stop_trn)
+			if (request->is_auto_stop_trn)
 				sdmmc->stop_trn_rsp = sdmmc->regs->rspreg[3];
 		}
 
 		if (has_req_or_check_busy)
 		{
-			result = _sdmmc_wait_card_busy(sdmmc);
+			res = _sdmmc_wait_card_busy(sdmmc);
 #ifdef ERROR_EXTRA_PRINTING
-			if (!result)
+			if (res)
 				EPRINTFARGS("SDMMC%d: Busy timeout!", sdmmc->id + 1);
 #endif
-			return result;
 		}
 	}
 
-	return result;
+	return res;
 }
 
 bool sdmmc_get_sd_inserted()
@@ -1251,7 +1251,7 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
 
 	// Check if SD card is inserted.
 	if (!sdmmc_get_sd_inserted())
-		return 0;
+		return 1;
 
 	// Enable deep loopback for SDMMC1 CLK pad so reads work.
 	APB_MISC(APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL) = 1;
@@ -1300,7 +1300,7 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
 		usleep(1000);
 	}
 
-	return 1;
+	return 0;
 }
 
 static void _sdmmc_config_emmc(u32 id, bool t210b01)
@@ -1342,7 +1342,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
 	const u8 *trim_values;
 
 	if (id > SDMMC_4 || id == SDMMC_3)
-		return 0;
+		return 1;
 
 	memset(sdmmc, 0, sizeof(sdmmc_t));
 
@@ -1357,8 +1357,8 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
 	switch (id)
 	{
 	case SDMMC_1:
-		if (!_sdmmc_config_sdmmc1(sdmmc->t210b01))
-			return 0;
+		if (_sdmmc_config_sdmmc1(sdmmc->t210b01))
+			return 1;
 		if (sdmmc->t210b01)
 			vref_sel = 0;
 		else
@@ -1393,8 +1393,8 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
 	sdmmc->regs->sdmemcmppadctl = (sdmmc->regs->sdmemcmppadctl & ~SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK) | vref_sel;
 
 	// Configure auto calibration values.
-	if (!_sdmmc_autocal_config_offset(sdmmc, power))
-		return 0;
+	if (_sdmmc_autocal_config_offset(sdmmc, power))
+		return 1;
 
 	_sdmmc_commit_changes(sdmmc);
 
@@ -1402,22 +1402,23 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
 	_sdmmc_autocal_execute(sdmmc, power);
 
 	// Enable internal clock and power.
-	if (_sdmmc_enable_internal_clock(sdmmc))
+	if (!_sdmmc_enable_internal_clock(sdmmc))
 	{
 		sdmmc_set_bus_width(sdmmc, bus_width);
 		_sdmmc_set_io_power(sdmmc, power);
 
-		if (sdmmc_setup_clock(sdmmc, type))
+		if (!sdmmc_setup_clock(sdmmc, type))
 		{
 			sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_DISABLE);
 			_sdmmc_card_clock_enable(sdmmc);
 			_sdmmc_commit_changes(sdmmc);
 
-			return 1;
+			return 0;
 		}
 	}
 
-	return 0;
+	// Failed to enable clock.
+	return 1;
 }
 
 void sdmmc1_disable_power()
@@ -1480,10 +1481,10 @@ void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 che
 	cmdbuf->check_busy = check_busy;
 }
 
-int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out)
+int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *request, u32 *blkcnt_out)
 {
 	if (!sdmmc->card_clock_enabled)
-		return 0;
+		return 1;
 
 	// Recalibrate periodically if needed.
 	if (sdmmc->periodic_calibration && sdmmc->powersave_enabled)
@@ -1498,19 +1499,19 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b
 		usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 	}
 
-	int result = _sdmmc_execute_cmd_inner(sdmmc, cmd, req, blkcnt_out);
+	int res = _sdmmc_execute_cmd_inner(sdmmc, cmd, request, blkcnt_out);
 	usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 
 	if (should_disable_sd_clock)
 		sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
 
-	return result;
+	return res;
 }
 
 int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
 {
 	if (sdmmc->id != SDMMC_1)
-		return 0;
+		return 1;
 
 	_sdmmc_commit_changes(sdmmc);
 
@@ -1538,8 +1539,8 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
 		_sdmmc_commit_changes(sdmmc);
 		usleep(1000);
 		if ((sdmmc->regs->prnsts & SDHCI_DATA_LVL_MASK) == SDHCI_DATA_LVL_MASK)
-			return 1;
+			return 0;
 	}
 
-	return 0;
+	return 1;
 }

bdk/storage/sdmmc_driver.h

@@ -274,9 +274,11 @@
 /*! Helper for SWITCH command argument. */
 #define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
 
-#define HW_TAP_TUNING            0x100
-#define INVALID_TAP              0x100
-#define SAMPLING_WINDOW_SIZE_MIN 8
+#define SDMMC_HW_TAP_TUNING       0x100
+#define SDMMC_INVALID_TAP         0x100
+#define SDMMC_SAMPLE_WIN_SIZE_MIN 8
+
+#define SDMMC_ADMA_ADDR_ALIGN 8
 
 /*! SDMMC controller context. */
 typedef struct _sdmmc_t
@@ -332,7 +334,7 @@ bool sdmmc_get_sd_inserted();
 int  sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type);
 void sdmmc_end(sdmmc_t *sdmmc);
 void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
-int  sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
+int  sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *request, u32 *blkcnt_out);
 int  sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
 
 #endif

bdk/usb/usb_gadget_hid.c

@@ -1,7 +1,7 @@
 /*
  * USB Gadget HID driver for Tegra X1
  *
- * Copyright (c) 2019-2025 CTCaer
+ * Copyright (c) 2019-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -315,33 +315,30 @@ typedef struct _touchpad_report_t
 
 static bool _fts_touch_read(touchpad_report_t *rpt)
 {
-	static touch_event touchpad;
+	static touch_event_t touchpad;
 
-	touch_poll(&touchpad);
+	if (touch_poll(&touchpad))
+		return false;
 
 	rpt->rpt_id = 5;
 	rpt->count = 1;
 
 	// Decide touch enable.
-	switch (touchpad.type & STMFTS_MASK_EVENT_ID)
+	if (touchpad.touch)
 	{
-	//case STMFTS_EV_MULTI_TOUCH_ENTER:
-	case STMFTS_EV_MULTI_TOUCH_MOTION:
 		rpt->x = touchpad.x;
 		rpt->y = touchpad.y;
 		//rpt->z = touchpad.z;
-		rpt->id = touchpad.fingers ? touchpad.fingers - 1 : 0;
+		rpt->id = touchpad.finger;
 		rpt->tip_switch = 1;
-		break;
-	case STMFTS_EV_MULTI_TOUCH_LEAVE:
+	}
+	else
+	{
 		rpt->x = touchpad.x;
 		rpt->y = touchpad.y;
 		//rpt->z = touchpad.z;
-		rpt->id = touchpad.fingers ? touchpad.fingers - 1 : 0;
+		rpt->id = touchpad.finger;
 		rpt->tip_switch = 0;
-		break;
-	case STMFTS_EV_NO_EVENT:
-		return false;
 	}
 
 	return true;

bdk/usb/usb_gadget_ums.c

@@ -495,7 +495,7 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt)
 		}
 
 		// Do the SDMMC read.
-		if (!sdmmc_storage_read(ums->lun.storage, ums->lun.offset + lba_offset, amount, sdmmc_buf))
+		if (sdmmc_storage_read(ums->lun.storage, ums->lun.offset + lba_offset, amount, sdmmc_buf))
 			amount = 0;
 
 		// Wait for the async USB transfer to finish.
@@ -650,7 +650,7 @@ static int _scsi_write(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt)
 				goto empty_write;
 
 			// Perform the write.
-			if (!sdmmc_storage_write(ums->lun.storage, ums->lun.offset + lba_offset,
+			if (sdmmc_storage_write(ums->lun.storage, ums->lun.offset + lba_offset,
 				amount >> UMS_DISK_LBA_SHIFT, (u8 *)bulk_ctxt->bulk_out_buf))
 				amount = 0;
 
@@ -722,7 +722,7 @@ static int _scsi_verify(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt)
 			break;
 		}
 
-		if (!sdmmc_storage_read(ums->lun.storage, ums->lun.offset + lba_offset, amount, bulk_ctxt->bulk_in_buf))
+		if (sdmmc_storage_read(ums->lun.storage, ums->lun.offset + lba_offset, amount, bulk_ctxt->bulk_in_buf))
 			amount = 0;
 
 DPRINTF("File read %X @ %X\n", amount, lba_offset);
@@ -1861,7 +1861,7 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs)
 	if (usbs->type == MMC_SD)
 	{
 		sd_end();
-		if (!sd_mount())
+		if (sd_mount())
 		{
 			ums.set_text(ums.label, "#FFDD00 Failed to init SD!#");
 			res = 1;
@@ -1874,7 +1874,7 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs)
 	}
 	else
 	{
-		if (!emmc_initialize(false))
+		if (emmc_initialize(false))
 		{
 			ums.set_text(ums.label, "#FFDD00 Failed to init eMMC!#");
 			res = 1;

bdk/usb/xusbd.c

@@ -931,7 +931,7 @@ int xusb_device_init()
 	bpmp_clk_rate_relaxed(false);
 
 	// Enable AHB redirect for access to IRAM for Event/EP ring buffers.
-	mc_enable_ahb_redirect();
+	mc_enable_ahb_redirect(1);
 
 	 // Enable XUSB device IPFS.
 	XUSB_DEV_DEV(XUSB_DEV_CONFIGURATION) |= DEV_CONFIGURATION_EN_FPCI;

bdk/utils/dirlist.h

@@ -16,6 +16,9 @@
 
 #include <utils/types.h>
 
+#ifndef _DIRLIST_H_
+#define _DIRLIST_H_
+
 #define DIR_MAX_ENTRIES 64
 
 #define DIR_SHOW_HIDDEN BIT(0)
@@ -29,3 +32,5 @@ typedef struct _dirlist_t
 } dirlist_t;
 
 dirlist_t *dirlist(const char *directory, const char *pattern, u32 flags);
+
+#endif

bdk/utils/ini.c

@@ -74,7 +74,7 @@ int ini_parse(link_t *dst, const char *ini_path, bool is_dir)
 		if (!filelist)
 		{
 			free(filename);
-			return 0;
+			return 1;
 		}
 		strcpy(filename + pathlen, "/");
 		pathlen++;
@@ -100,7 +100,7 @@ int ini_parse(link_t *dst, const char *ini_path, bool is_dir)
 			free(filelist);
 			free(filename);
 
-			return 0;
+			return 1;
 		}
 
 		lbuf = malloc(512);
@@ -170,7 +170,7 @@ int ini_parse(link_t *dst, const char *ini_path, bool is_dir)
 	free(filename);
 	free(filelist);
 
-	return 1;
+	return 0;
 }
 
 char *ini_check_special_section(ini_sec_t *cfg)

bootloader/frontend/fe_info.c

@@ -65,7 +65,7 @@ void print_mmc_info()
 
 	static const u32 SECTORS_TO_MIB_COEFF = 11;
 
-	if (!emmc_initialize(false))
+	if (emmc_initialize(false))
 	{
 		EPRINTF("Failed to init eMMC.");
 		goto out;
@@ -194,7 +194,7 @@ void print_sdcard_info()
 	gfx_clear_partial_grey(0x1B, 0, 1256);
 	gfx_con_setpos(0, 0);
 
-	if (sd_initialize(false))
+	if (!sd_initialize(false))
 	{
 		gfx_printf("%kCard IDentification:%k\n", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT);
 		gfx_printf(

bootloader/frontend/fe_tools.c

@@ -110,7 +110,7 @@ void menu_autorcm()
 		return;
 	}
 
-	if (!emmc_initialize(false))
+	if (emmc_initialize(false))
 	{
 		EPRINTF("Failed to init eMMC.");
 		btn_wait();

bootloader/hos/hos.c

@@ -72,6 +72,7 @@ static const u8 master_kekseed_t210_tsec_v4[HOS_MKEY_VER_MAX - HOS_MKEY_VER_810
 	{ 0xD7, 0x63, 0x74, 0x46, 0x4E, 0xBA, 0x78, 0x0A, 0x7C, 0x9D, 0xB3, 0xE8, 0x7A, 0x3D, 0x71, 0xE3 }, // 19.0.0.
 	{ 0xA1, 0x7D, 0x34, 0xDB, 0x2D, 0x9D, 0xDA, 0xE5, 0xF8, 0x15, 0x63, 0x4C, 0x8F, 0xE7, 0x6C, 0xD8 }, // 20.0.0.
 	{ 0x66, 0xC8, 0xCB, 0x3D, 0xEC, 0xF4, 0x59, 0x73, 0x54, 0x88, 0xE1, 0x2E, 0xE6, 0x3D, 0x68, 0x46 }, // 21.0.0.
+	{ 0x15, 0xAC, 0x96, 0x34, 0xF5, 0x32, 0x56, 0x68, 0xFE, 0x5B, 0x9D, 0xD7, 0xED, 0x19, 0xB7, 0x8E }, // 22.0.0.
 };
 
 //!TODO: Update on mkey changes.
@@ -92,6 +93,7 @@ static const u8 master_kekseed_t210b01[HOS_MKEY_VER_MAX - HOS_MKEY_VER_600 + 1][
 	{ 0x31, 0xBE, 0x25, 0xFB, 0xDB, 0xB4, 0xEE, 0x49, 0x5C, 0x77, 0x05, 0xC2, 0x36, 0x9F, 0x34, 0x80 }, // 19.0.0.
 	{ 0x1A, 0x31, 0x62, 0x87, 0xA8, 0x09, 0xCA, 0xF8, 0x69, 0x15, 0x45, 0xC2, 0x6B, 0xAA, 0x5A, 0x8A }, // 20.0.0.
 	{ 0xEB, 0xF3, 0x5B, 0x2D, 0x4A, 0x2D, 0xCE, 0x45, 0x3A, 0x6F, 0x61, 0x38, 0x0B, 0x00, 0x3B, 0x46 }, // 21.0.0.
+	{ 0x82, 0xE2, 0x0A, 0x59, 0x67, 0xDF, 0xBF, 0x51, 0x47, 0x62, 0x11, 0xF2, 0x41, 0xD3, 0xEE, 0x13 }, // 22.0.0.
 };
 
 static const u8 console_keyseed[SE_KEY_128_SIZE] =
@@ -131,23 +133,23 @@ static void _se_lock(bool lock_se)
 	SB(SB_CSR) = SB_CSR_PIROM_DISABLE;
 }
 
-static bool _hos_eks_rw_try(u8 *buf, bool write)
+static int _hos_eks_rw_try(u8 *buf, bool write)
 {
 	for (u32 i = 0; i < 3; i++)
 	{
 		if (!write)
 		{
-			if (sdmmc_storage_read(&sd_storage, 0, 1, buf))
-				return true;
+			if (!sdmmc_storage_read(&sd_storage, 0, 1, buf))
+				return 0;
 		}
 		else
 		{
-			if (sdmmc_storage_write(&sd_storage, 0, 1, buf))
-				return true;
+			if (!sdmmc_storage_write(&sd_storage, 0, 1, buf))
+				return 0;
 		}
 	}
 
-	return false;
+	return 1;
 }
 
 static void _hos_eks_get()
@@ -161,7 +163,7 @@ static void _hos_eks_get()
 	{
 		// Read EKS blob.
 		u8 *mbr = malloc(SD_BLOCKSIZE);
-		if (!_hos_eks_rw_try(mbr, false))
+		if (_hos_eks_rw_try(mbr, false))
 			goto out;
 
 		// Decrypt EKS blob.
@@ -199,7 +201,7 @@ static void _hos_eks_save()
 	{
 		// Read EKS blob.
 		u8 *mbr = malloc(SD_BLOCKSIZE);
-		if (!_hos_eks_rw_try(mbr, false))
+		if (_hos_eks_rw_try(mbr, false))
 		{
 			if (new_eks)
 			{
@@ -253,7 +255,7 @@ static void _hos_eks_clear(u32 mkey)
 		{
 			// Read EKS blob.
 			u8 *mbr = malloc(SD_BLOCKSIZE);
-			if (!_hos_eks_rw_try(mbr, false))
+			if (_hos_eks_rw_try(mbr, false))
 				goto out;
 
 			// Disable current Master key version.
@@ -291,7 +293,7 @@ static int _hos_keygen(pkg1_eks_t *eks, u32 mkey, tsec_ctxt_t *tsec_ctxt, bool s
 	tsec_keys_t tsec_keys;
 
 	if (mkey > HOS_MKEY_VER_MAX)
-		return 0;
+		return 1;
 
 	// Do Mariko keygen.
 	if (h_cfg.t210b01)
@@ -306,7 +308,7 @@ static int _hos_keygen(pkg1_eks_t *eks, u32 mkey, tsec_ctxt_t *tsec_ctxt, bool s
 		// Derive latest pkg2 key.
 		se_aes_unwrap_key(8, 7, package2_keyseed);
 
-		return 1;
+		return 0;
 	}
 
 	// Do Erista keygen.
@@ -317,7 +319,7 @@ static int _hos_keygen(pkg1_eks_t *eks, u32 mkey, tsec_ctxt_t *tsec_ctxt, bool s
 		if (fuse_set_sbk())
 			sbk_is_set = true;
 		else
-			return 1; // Continue with current SE keys.
+			return 0; // Continue with current SE keys.
 	}
 
 	// Use HOS EKS if it exists.
@@ -354,7 +356,7 @@ static int _hos_keygen(pkg1_eks_t *eks, u32 mkey, tsec_ctxt_t *tsec_ctxt, bool s
 		if (!tsec_ctxt->fw)
 		{
 			_hos_crit_error("Failed to load thk.bin");
-			return 0;
+			return 1;
 		}
 
 		tsec_ctxt->size = 0x1F00;
@@ -378,7 +380,7 @@ static int _hos_keygen(pkg1_eks_t *eks, u32 mkey, tsec_ctxt_t *tsec_ctxt, bool s
 		if (retries > 15)
 		{
 			_hos_crit_error("Failed to get TSEC keys.");
-			return 0;
+			return 1;
 		}
 	}
 
@@ -483,7 +485,7 @@ static int _hos_keygen(pkg1_eks_t *eks, u32 mkey, tsec_ctxt_t *tsec_ctxt, bool s
 		se_aes_unwrap_key(11, 13, cmac_keyseed);
 		se_aes_hash_cmac(cmac, SE_KEY_128_SIZE, 11, (void *)eks->ctr, sizeof(eks->ctr) + sizeof(eks->keys));
 		if (!memcmp(eks->cmac, cmac, SE_KEY_128_SIZE))
-			return 0;
+			return 1;
 */
 
 		se_aes_crypt_ecb(13, DECRYPT, tsec_keys.tsec, cmac_keyseed, SE_KEY_128_SIZE);
@@ -537,7 +539,7 @@ static int _hos_keygen(pkg1_eks_t *eks, u32 mkey, tsec_ctxt_t *tsec_ctxt, bool s
 		se_aes_unwrap_key(8, !is_exo ? 12 : 13, package2_keyseed);
 	}
 
-	return 1;
+	return 0;
 }
 
 static int _read_emmc_pkg1(launch_ctxt_t *ctxt)
@@ -586,7 +588,7 @@ try_load:
 			goto try_load;
 		}
 
-		return 0;
+		return 1;
 	}
 	gfx_printf("Identified pkg1 and mkey %d\n\n", ctxt->pkg1_id->mkey);
 
@@ -599,7 +601,7 @@ try_load:
 							eks_size / EMMC_BLOCKSIZE, ctxt->eks);
 	}
 
-	return 1;
+	return 0;
 }
 
 static u8 *_read_emmc_pkg2(launch_ctxt_t *ctxt)
@@ -666,7 +668,7 @@ static bool _get_fs_exfat_compatible(link_t *info, u32 *hos_revision)
 		if (strcmp((char *)ki->kip1->name, "FS"))
 			continue;
 
-		if (!se_sha_hash_256_oneshot(sha_buf, ki->kip1, ki->size))
+		if (se_sha_hash_256_oneshot(sha_buf, ki->kip1, ki->size))
 			break;
 
 		pkg2_get_ids(&kip_ids, &fs_ids_cnt);
@@ -734,14 +736,14 @@ void hos_launch(ini_sec_t *cfg)
 	}
 
 	// Try to parse config if present.
-	if (!parse_boot_config(&ctxt))
+	if (hos_parse_boot_config(&ctxt))
 	{
 		_hos_crit_error("Wrong ini cfg or missing/corrupt files!");
 		goto error;
 	}
 
 	// Read package1 and the correct eks.
-	if (!_read_emmc_pkg1(&ctxt))
+	if (_read_emmc_pkg1(&ctxt))
 	{
 		// Check if stock is enabled and device can boot in OFW.
 		if (ctxt.stock && (h_cfg.t210b01 || !tools_autorcm_enabled()))
@@ -770,7 +772,7 @@ void hos_launch(ini_sec_t *cfg)
 		}
 
 		ctxt.patch_krn_proc_id = true; // Set kernel process id patching in case of no pkg3.
-		config_kip1patch(&ctxt, "emummc");
+		hos_config_kip1patch(&ctxt, "emummc");
 	}
 	else if (!emu_cfg.enabled && ctxt.emummc_forced)
 	{
@@ -801,7 +803,7 @@ void hos_launch(ini_sec_t *cfg)
 				((fuses & BIT(14)) && (ctxt.pkg1_id->fuses <= 14))    // HOS 12.0.2+ fuses burnt.
 			  )
 			))
-			config_kip1patch(&ctxt, "nogc");
+			hos_config_kip1patch(&ctxt, "nogc");
 	}
 
 	gfx_printf("Loaded config and pkg1\n%s mode\n", ctxt.stock ? "Stock" : "CFW");
@@ -821,7 +823,7 @@ void hos_launch(ini_sec_t *cfg)
 	tsec_ctxt.pkg11_off = ctxt.pkg1_id->pkg11_off;
 
 	// Generate keys.
-	if (!_hos_keygen(ctxt.eks, mkey, &tsec_ctxt, ctxt.stock, is_exo))
+	if (_hos_keygen(ctxt.eks, mkey, &tsec_ctxt, ctxt.stock, is_exo))
 		goto error;
 	gfx_puts("Generated keys\n");
 
@@ -871,7 +873,7 @@ void hos_launch(ini_sec_t *cfg)
 	}
 
 	// Configure and manage Warmboot binary.
-	if (!pkg1_warmboot_config(&ctxt, warmboot_base, ctxt.pkg1_id->fuses, mkey))
+	if (pkg1_warmboot_config(&ctxt, warmboot_base, ctxt.pkg1_id->fuses, mkey))
 	{
 		// Can only happen on T210B01.
 		_hos_crit_error("\nFailed to match warmboot with fuses!\nIf you continue, sleep wont work!");
@@ -928,7 +930,7 @@ void hos_launch(ini_sec_t *cfg)
 	}
 
 	LIST_INIT(kip1_info);
-	if (!pkg2_parse_kips(&kip1_info, pkg2_hdr, &ctxt.new_pkg2))
+	if (pkg2_parse_kips(&kip1_info, pkg2_hdr, &ctxt.new_pkg2))
 	{
 		_hos_crit_error("INI1 parsing failed!");
 		goto error;

bootloader/hos/hos.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2025 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -48,7 +48,8 @@ enum {
 	HOS_MKEY_VER_1900 = 18,
 	HOS_MKEY_VER_2000 = 19,
 	HOS_MKEY_VER_2100 = 20,
-	HOS_MKEY_VER_MAX  = HOS_MKEY_VER_2100
+	HOS_MKEY_VER_2200 = 21,
+	HOS_MKEY_VER_MAX  = HOS_MKEY_VER_2200
 };
 
 #define HOS_TSEC_VERSION 4 //! TODO: Update on TSEC Root Key changes.
@@ -62,9 +63,10 @@ enum {
 
 typedef struct _exo_ctxt_t
 {
-	u32  hos_revision;
-	bool no_user_exceptions;
-	bool user_pmu;
+	u32   hos_revision;
+	bool  no_user_exceptions;
+	bool  user_pmu;
+	bool *force_mem_mode;
 	bool *usb3_force;
 	bool *cal0_blank;
 	bool *cal0_allow_writes_sys;

bootloader/hos/hos_config.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2025 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -31,27 +31,27 @@ static int _config_warmboot(launch_ctxt_t *ctxt, const char *value)
 {
 	ctxt->warmboot = sd_file_read(value, &ctxt->warmboot_size);
 	if (!ctxt->warmboot)
-		return 0;
+		return 1;
 
-	return 1;
+	return 0;
 }
 
 static int _config_secmon(launch_ctxt_t *ctxt, const char *value)
 {
 	ctxt->secmon = sd_file_read(value, &ctxt->secmon_size);
 	if (!ctxt->secmon)
-		return 0;
+		return 1;
 
-	return 1;
+	return 0;
 }
 
 static int _config_kernel(launch_ctxt_t *ctxt, const char *value)
 {
 	ctxt->kernel = sd_file_read(value, &ctxt->kernel_size);
 	if (!ctxt->kernel)
-		return 0;
+		return 1;
 
-	return 1;
+	return 0;
 }
 
 static int _config_kip1(launch_ctxt_t *ctxt, const char *value)
@@ -88,7 +88,7 @@ static int _config_kip1(launch_ctxt_t *ctxt, const char *value)
 					free(dir);
 					free(filelist);
 
-					return 0;
+					return 1;
 				}
 				DPRINTF("Loaded kip1 from SD (size %08X)\n", size);
 				list_append(&ctxt->kip1_list, &mkip1->link);
@@ -108,20 +108,20 @@ static int _config_kip1(launch_ctxt_t *ctxt, const char *value)
 		{
 			free(mkip1);
 
-			return 0;
+			return 1;
 		}
 		DPRINTF("Loaded kip1 from SD (size %08X)\n", size);
 		list_append(&ctxt->kip1_list, &mkip1->link);
 	}
 
-	return 1;
+	return 0;
 }
 
-int config_kip1patch(launch_ctxt_t *ctxt, const char *value)
+int hos_config_kip1patch(launch_ctxt_t *ctxt, const char *value)
 {
 	int len = strlen(value);
 	if (!len)
-		return 0;
+		return 1;
 
 	if (ctxt->kip1_patches == NULL)
 	{
@@ -142,7 +142,8 @@ int config_kip1patch(launch_ctxt_t *ctxt, const char *value)
 		memcpy(&ctxt->kip1_patches[old_len], value, len);
 		ctxt->kip1_patches[old_len + len] = 0;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_svcperm(launch_ctxt_t *ctxt, const char *value)
@@ -152,7 +153,8 @@ static int _config_svcperm(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Disabled SVC verification\n");
 		ctxt->svcperm = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_debugmode(launch_ctxt_t *ctxt, const char *value)
@@ -162,7 +164,8 @@ static int _config_debugmode(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Enabled Debug mode\n");
 		ctxt->debugmode = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_stock(launch_ctxt_t *ctxt, const char *value)
@@ -172,7 +175,8 @@ static int _config_stock(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Enabled stock mode\n");
 		ctxt->stock = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_emummc_forced(launch_ctxt_t *ctxt, const char *value)
@@ -182,7 +186,8 @@ static int _config_emummc_forced(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Forced emuMMC\n");
 		ctxt->emummc_forced = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_kernel_proc_id(launch_ctxt_t *ctxt, const char *value)
@@ -192,7 +197,8 @@ static int _config_kernel_proc_id(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Enabled kernel process id send/recv patching\n");
 		ctxt->patch_krn_proc_id = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_dis_exo_user_exceptions(launch_ctxt_t *ctxt, const char *value)
@@ -202,7 +208,8 @@ static int _config_dis_exo_user_exceptions(launch_ctxt_t *ctxt, const char *valu
 		DPRINTF("Disabled exosphere user exception handlers\n");
 		ctxt->exo_ctx.no_user_exceptions = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_exo_user_pmu_access(launch_ctxt_t *ctxt, const char *value)
@@ -212,7 +219,22 @@ static int _config_exo_user_pmu_access(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Enabled user access to PMU\n");
 		ctxt->exo_ctx.user_pmu = true;
 	}
-	return 1;
+
+	return 0;
+}
+
+static int _config_exo_force_mem_mode(launch_ctxt_t *ctxt, const char *value)
+{
+	// Override key found.
+	ctxt->exo_ctx.force_mem_mode = zalloc(sizeof(bool));
+
+	if (*value == '1')
+	{
+		DPRINTF("Enabled Auto Memory Mode\n");
+		*ctxt->exo_ctx.force_mem_mode = true;
+	}
+
+	return 0;
 }
 
 static int _config_exo_usb3_force(launch_ctxt_t *ctxt, const char *value)
@@ -225,7 +247,8 @@ static int _config_exo_usb3_force(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Enabled USB 3.0\n");
 		*ctxt->exo_ctx.usb3_force = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_exo_cal0_blanking(launch_ctxt_t *ctxt, const char *value)
@@ -238,7 +261,8 @@ static int _config_exo_cal0_blanking(launch_ctxt_t *ctxt, const char *value)
 		DPRINTF("Enabled prodinfo blanking\n");
 		*ctxt->exo_ctx.cal0_blank = true;
 	}
-	return 1;
+
+	return 0;
 }
 
 static int _config_exo_cal0_writes_enable(launch_ctxt_t *ctxt, const char *value)
@@ -252,7 +276,7 @@ static int _config_exo_cal0_writes_enable(launch_ctxt_t *ctxt, const char *value
 		*ctxt->exo_ctx.cal0_allow_writes_sys = true;
 	}
 
-	return 1;
+	return 0;
 }
 
 static int _config_pkg3(launch_ctxt_t *ctxt, const char *value)
@@ -264,9 +288,9 @@ static int _config_exo_fatal_payload(launch_ctxt_t *ctxt, const char *value)
 {
 	ctxt->exofatal = sd_file_read(value, &ctxt->exofatal_size);
 	if (!ctxt->exofatal)
-		return 0;
+		return 1;
 
-	return 1;
+	return 0;
 }
 
 static int _config_ucid(launch_ctxt_t *ctxt, const char *value)
@@ -274,7 +298,7 @@ static int _config_ucid(launch_ctxt_t *ctxt, const char *value)
 	// Override uCID if set.
 	ctxt->ucid = atoi(value);
 
-	return 1;
+	return 0;
 }
 
 typedef struct _cfg_handler_t
@@ -289,7 +313,7 @@ static const cfg_handler_t _config_handlers[] = {
 	{ "secmon",           _config_secmon },
 	{ "kernel",           _config_kernel },
 	{ "kip1",             _config_kip1 },
-	{ "kip1patch",        config_kip1patch },
+	{ "kip1patch",        hos_config_kip1patch },
 	{ "fullsvcperm",      _config_svcperm },
 	{ "debugmode",        _config_debugmode },
 	{ "kernelprocid",     _config_kernel_proc_id },
@@ -302,6 +326,7 @@ static const cfg_handler_t _config_handlers[] = {
 	{ "emummcforce",      _config_emummc_forced },
 	{ "nouserexceptions", _config_dis_exo_user_exceptions },
 	{ "userpmu",          _config_exo_user_pmu_access },
+	{ "memmode",          _config_exo_force_mem_mode },
 	{ "usb3force",        _config_exo_usb3_force },
 	{ "cal0blank",        _config_exo_cal0_blanking },
 	{ "cal0writesys",     _config_exo_cal0_writes_enable },
@@ -309,10 +334,10 @@ static const cfg_handler_t _config_handlers[] = {
 	{ NULL, NULL },
 };
 
-int parse_boot_config(launch_ctxt_t *ctxt)
+int hos_parse_boot_config(launch_ctxt_t *ctxt)
 {
 	if (!ctxt->cfg)
-		return 1;
+		return 0;
 
 	// Check each config key.
 	LIST_FOREACH_ENTRY(ini_kv_t, kv, &ctxt->cfg->kvs, link)
@@ -322,12 +347,12 @@ int parse_boot_config(launch_ctxt_t *ctxt)
 			// If key matches, call its handler.
 			if (!strcmp(_config_handlers[i].key, kv->key))
 			{
-				if (!_config_handlers[i].handler(ctxt, kv->val))
+				if (_config_handlers[i].handler(ctxt, kv->val))
 				{
 					gfx_con.mute = false;
 					EPRINTFARGS("Error while loading %s:\n%s", kv->key, kv->val);
 
-					return 0;
+					return 1;
 				}
 
 				break;
@@ -335,5 +360,5 @@ int parse_boot_config(launch_ctxt_t *ctxt)
 		}
 	}
 
-	return 1;
+	return 0;
 }

bootloader/hos/hos_config.h

@@ -19,8 +19,8 @@
 
 #include "hos.h"
 
-int parse_boot_config(launch_ctxt_t *ctxt);
-int config_kip1patch(launch_ctxt_t *ctxt, const char *value);
+int hos_parse_boot_config(launch_ctxt_t *ctxt);
+int hos_config_kip1patch(launch_ctxt_t *ctxt, const char *value);
 
 #endif
 

bootloader/hos/pkg1.c

@@ -171,7 +171,8 @@ static const pkg1_id_t _pkg1_ids[] = {
 	{ "20240207", 17, 19, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 18.0.0 - 18.1.0.
 	{ "20240808", 18, 20, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 19.0.0 - 19.0.1.
 	{ "20250206", 19, 21, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 20.0.0 - 20.5.0.
-	{ "20251009", 20, 22, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 21.0.0+
+	{ "20251009", 20, 22, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 21.0.0 - 21.2.0.
+	{ "20260123", 21, 23, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 22.0.0+
 };
 
 const pkg1_id_t *pkg1_get_latest()
@@ -195,7 +196,7 @@ const pkg1_id_t *pkg1_identify(u8 *pkg1)
 	return NULL;
 }
 
-int pkg1_decrypt(const pkg1_id_t *id, u8 *pkg1)
+bool pkg1_decrypt(const pkg1_id_t *id, u8 *pkg1)
 {
 	pk11_hdr_t *hdr;
 
@@ -344,7 +345,7 @@ void pkg1_warmboot_patch(void *hos_ctxt)
 int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base, u32 fuses_fw, u8 mkey)
 {
 	launch_ctxt_t *ctxt = (launch_ctxt_t *)hos_ctxt;
-	int res = 1;
+	int res = 0;
 
 	if (h_cfg.t210b01)
 	{
@@ -374,7 +375,7 @@ int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base, u32 fuses_fw, u8 mke
 
 				// Check if high enough.
 				if (!warmboot_fw || burnt_fuses > fuses_fw)
-					res = 0;
+					res = 1;
 				else
 				{
 					ctxt->warmboot = warmboot_fw + sizeof(u32);

bootloader/hos/pkg1.h

@@ -162,7 +162,7 @@ typedef struct _nx_bit_t
 
 const pkg1_id_t *pkg1_get_latest();
 const pkg1_id_t *pkg1_identify(u8 *pkg1);
-int  pkg1_decrypt(const pkg1_id_t *id, u8 *pkg1);
+bool  pkg1_decrypt(const pkg1_id_t *id, u8 *pkg1);
 const u8 *pkg1_unpack(void *wm_dst, u32 *wb_sz, void *sm_dst, void *ldr_dst, const pkg1_id_t *id, u8 *pkg1);
 void pkg1_secmon_patch(void *hos_ctxt, u32 secmon_base, bool t210b01);
 void pkg1_warmboot_patch(void *hos_ctxt);

bootloader/hos/pkg2.c

@@ -63,101 +63,101 @@ static void parse_external_kip_patches()
 	if (ext_patches_parsed)
 		return;
 
+	ext_patches_parsed = true;
+
 	LIST_INIT(ini_kip_sections);
 	if (ini_patch_parse(&ini_kip_sections, "bootloader/patches.ini"))
+		return;
+
+	// Copy ids into a new patchset.
+	_kip_id_sets = zalloc(sizeof(kip1_id_t) * 256); // Max 256 kip ids.
+	memcpy(_kip_id_sets, _kip_ids, sizeof(_kip_ids));
+
+	// Parse patchsets and glue them together.
+	LIST_FOREACH_ENTRY(ini_kip_sec_t, ini_psec, &ini_kip_sections, link)
 	{
-		// Copy ids into a new patchset.
-		_kip_id_sets = zalloc(sizeof(kip1_id_t) * 256); // Max 256 kip ids.
-		memcpy(_kip_id_sets, _kip_ids, sizeof(_kip_ids));
-
-		// Parse patchsets and glue them together.
-		LIST_FOREACH_ENTRY(ini_kip_sec_t, ini_psec, &ini_kip_sections, link)
+		kip1_id_t *kip = NULL;
+		bool found = false;
+		for (u32 kip_idx = 0; kip_idx < _kip_id_sets_cnt + 1; kip_idx++)
 		{
-			kip1_id_t *kip = NULL;
-			bool found = false;
-			for (u32 kip_idx = 0; kip_idx < _kip_id_sets_cnt + 1; kip_idx++)
+			kip = &_kip_id_sets[kip_idx];
+
+			// Check if reached the end of predefined list.
+			if (!kip->name)
+				break;
+
+			// Check if name and hash match.
+			if (!strcmp(kip->name, ini_psec->name) && !memcmp(kip->hash, ini_psec->hash, 8))
 			{
-				kip = &_kip_id_sets[kip_idx];
-
-				// Check if reached the end of predefined list.
-				if (!kip->name)
-					break;
-
-				// Check if name and hash match.
-				if (!strcmp(kip->name, ini_psec->name) && !memcmp(kip->hash, ini_psec->hash, 8))
-				{
-					found = true;
-					break;
-				}
+				found = true;
+				break;
 			}
-
-			if (!kip)
-				continue;
-
-			// If not found, create a new empty entry.
-			if (!found)
-			{
-				kip->name = ini_psec->name;
-				memcpy(kip->hash, ini_psec->hash, 8);
-				kip->patchset = zalloc(sizeof(kip1_patchset_t));
-
-				_kip_id_sets_cnt++;
-			}
-
-			kip1_patchset_t *patchsets = (kip1_patchset_t *)zalloc(sizeof(kip1_patchset_t) * 16); // Max 16 patchsets per kip.
-
-			u32 patchset_idx;
-			for (patchset_idx = 0; kip->patchset[patchset_idx].name != NULL; patchset_idx++)
-			{
-				patchsets[patchset_idx].name    = kip->patchset[patchset_idx].name;
-				patchsets[patchset_idx].patches = kip->patchset[patchset_idx].patches;
-			}
-
-			kip->patchset = patchsets;
-			bool first_ext_patch = true;
-			u32 patch_idx = 0;
-
-			// Parse patches and glue them together to a patchset.
-			kip1_patch_t *patches = zalloc(sizeof(kip1_patch_t) * 32); // Max 32 patches per set.
-			LIST_FOREACH_ENTRY(ini_patchset_t, pt, &ini_psec->pts, link)
-			{
-				if (first_ext_patch)
-				{
-					first_ext_patch = false;
-					patchsets[patchset_idx].name    = pt->name;
-					patchsets[patchset_idx].patches = patches;
-				}
-				else if (strcmp(pt->name, patchsets[patchset_idx].name))
-				{
-					// New patchset name found, create a new set.
-					patchset_idx++;
-					patch_idx = 0;
-					patches = zalloc(sizeof(kip1_patch_t) * 32); // Max 32 patches per set.
-
-					patchsets[patchset_idx].name    = pt->name;
-					patchsets[patchset_idx].patches = patches;
-				}
-
-				if (pt->length)
-				{
-					patches[patch_idx].offset = pt->offset;
-					patches[patch_idx].length = pt->length;
-
-					patches[patch_idx].src_data = (char *)pt->src_data;
-					patches[patch_idx].dst_data = (char *)pt->dst_data;
-				}
-				else
-					patches[patch_idx].src_data = malloc(1); // Empty patches check. Keep everything else as 0.
-
-				patch_idx++;
-			}
-			patchset_idx++;
-			patchsets[patchset_idx].name = NULL;
-			patchsets[patchset_idx].patches = NULL;
 		}
-	}
 
-	ext_patches_parsed = true;
+		if (!kip)
+			continue;
+
+		// If not found, create a new empty entry.
+		if (!found)
+		{
+			kip->name = ini_psec->name;
+			memcpy(kip->hash, ini_psec->hash, 8);
+			kip->patchset = zalloc(sizeof(kip1_patchset_t));
+
+			_kip_id_sets_cnt++;
+		}
+
+		kip1_patchset_t *patchsets = (kip1_patchset_t *)zalloc(sizeof(kip1_patchset_t) * 16); // Max 16 patchsets per kip.
+
+		u32 patchset_idx;
+		for (patchset_idx = 0; kip->patchset[patchset_idx].name != NULL; patchset_idx++)
+		{
+			patchsets[patchset_idx].name    = kip->patchset[patchset_idx].name;
+			patchsets[patchset_idx].patches = kip->patchset[patchset_idx].patches;
+		}
+
+		kip->patchset = patchsets;
+		bool first_ext_patch = true;
+		u32 patch_idx = 0;
+
+		// Parse patches and glue them together to a patchset.
+		kip1_patch_t *patches = zalloc(sizeof(kip1_patch_t) * 32); // Max 32 patches per set.
+		LIST_FOREACH_ENTRY(ini_patchset_t, pt, &ini_psec->pts, link)
+		{
+			if (first_ext_patch)
+			{
+				first_ext_patch = false;
+				patchsets[patchset_idx].name    = pt->name;
+				patchsets[patchset_idx].patches = patches;
+			}
+			else if (strcmp(pt->name, patchsets[patchset_idx].name))
+			{
+				// New patchset name found, create a new set.
+				patchset_idx++;
+				patch_idx = 0;
+				patches = zalloc(sizeof(kip1_patch_t) * 32); // Max 32 patches per set.
+
+				patchsets[patchset_idx].name    = pt->name;
+				patchsets[patchset_idx].patches = patches;
+			}
+
+			if (pt->length)
+			{
+				patches[patch_idx].offset = pt->offset;
+				patches[patch_idx].length = pt->length;
+
+				patches[patch_idx].src_data = (char *)pt->src_data;
+				patches[patch_idx].dst_data = (char *)pt->dst_data;
+			}
+			else
+				patches[patch_idx].src_data = malloc(1); // Empty patches check. Keep everything else as 0.
+
+			patch_idx++;
+		}
+		patchset_idx++;
+		patchsets[patchset_idx].name = NULL;
+		patchsets[patchset_idx].patches = NULL;
+	}
 }
 
 const pkg2_kernel_id_t *pkg2_identify(const u8 *hash)
@@ -226,7 +226,7 @@ static void _pkg2_get_newkern_info(u8 *kern_data)
 	}
 }
 
-bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2)
+int pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2)
 {
 	u8 *ptr;
 	// Check for new pkg2 type.
@@ -235,7 +235,7 @@ bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2)
 		_pkg2_get_newkern_info(pkg2->data);
 
 		if (!pkg2_newkern_ini1_start)
-			return false;
+			return 1;
 
 		ptr = pkg2->data + pkg2_newkern_ini1_start;
 		*new_pkg2 = true;
@@ -257,15 +257,15 @@ bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2)
 DPRINTF(" kip1 %d:%s @ %08X (%08X)\n", i, kip1->name, (u32)kip1, ki->size);
 	}
 
-	return true;
+	return 0;
 }
 
-int pkg2_has_kip(link_t *info, u64 tid)
+bool pkg2_has_kip(link_t *info, u64 tid)
 {
 	LIST_FOREACH_ENTRY(pkg2_kip1_info_t, ki, info, link)
 		if (ki->kip1->tid == tid)
-			return 1;
-	return 0;
+			return true;
+	return false;
 }
 
 void pkg2_replace_kip(link_t *info, u64 tid, pkg2_kip1_t *kip1)
@@ -371,65 +371,63 @@ static int _decompress_kip(pkg2_kip1_info_t *ki, u32 sectsToDecomp)
 
 static int _kipm_inject(const char *kipm_path, char *target_name, pkg2_kip1_info_t *ki)
 {
-	if (!strcmp((char *)ki->kip1->name, target_name))
+	if (strcmp((char *)ki->kip1->name, target_name))
+		return 1;
+
+	u32 size = 0;
+	u8 *kipm_data = (u8 *)sd_file_read(kipm_path, &size);
+	if (!kipm_data)
+		return 1;
+
+	u32 inject_size = size - sizeof(ki->kip1->caps);
+	u8 *kip_patched_data = (u8 *)malloc(ki->size + inject_size);
+
+	// Copy headers.
+	memcpy(kip_patched_data, ki->kip1, sizeof(pkg2_kip1_t));
+
+	pkg2_kip1_t *fs_kip = ki->kip1;
+	ki->kip1 = (pkg2_kip1_t *)kip_patched_data;
+	ki->size = ki->size + inject_size;
+
+	// Patch caps.
+	memcpy(&ki->kip1->caps, kipm_data, sizeof(ki->kip1->caps));
+	// Copy our .text data.
+	memcpy(&ki->kip1->data, kipm_data + sizeof(ki->kip1->caps), inject_size);
+
+	u32 new_offset = 0;
+
+	for (u32 section_idx = 0; section_idx < KIP1_NUM_SECTIONS - 2; section_idx++)
 	{
-		u32 size = 0;
-		u8 *kipm_data = (u8 *)sd_file_read(kipm_path, &size);
-		if (!kipm_data)
-			return 1;
-
-		u32 inject_size = size - sizeof(ki->kip1->caps);
-		u8 *kip_patched_data = (u8 *)malloc(ki->size + inject_size);
-
-		// Copy headers.
-		memcpy(kip_patched_data, ki->kip1, sizeof(pkg2_kip1_t));
-
-		pkg2_kip1_t *fs_kip = ki->kip1;
-		ki->kip1 = (pkg2_kip1_t *)kip_patched_data;
-		ki->size = ki->size + inject_size;
-
-		// Patch caps.
-		memcpy(&ki->kip1->caps, kipm_data, sizeof(ki->kip1->caps));
-		// Copy our .text data.
-		memcpy(&ki->kip1->data, kipm_data + sizeof(ki->kip1->caps), inject_size);
-
-		u32 new_offset = 0;
-
-		for (u32 section_idx = 0; section_idx < KIP1_NUM_SECTIONS - 2; section_idx++)
+		if (!section_idx) // .text.
 		{
-			if (!section_idx) // .text.
-			{
-				memcpy(ki->kip1->data + inject_size, fs_kip->data, fs_kip->sections[0].size_comp);
-				ki->kip1->sections[0].size_decomp += inject_size;
-				ki->kip1->sections[0].size_comp += inject_size;
-			}
-			else // Others.
-			{
-				if (section_idx < 3)
-					memcpy(ki->kip1->data + new_offset + inject_size, fs_kip->data + new_offset, fs_kip->sections[section_idx].size_comp);
-				ki->kip1->sections[section_idx].offset += inject_size;
-			}
-			new_offset += fs_kip->sections[section_idx].size_comp;
+			memcpy(ki->kip1->data + inject_size, fs_kip->data, fs_kip->sections[0].size_comp);
+			ki->kip1->sections[0].size_decomp += inject_size;
+			ki->kip1->sections[0].size_comp += inject_size;
 		}
-
-		// Patch PMC capabilities for 1.0.0.
-		if (!emu_cfg.fs_ver)
+		else // Others.
 		{
-			for (u32 i = 0; i < 0x20; i++)
-			{
-				if (ki->kip1->caps[i] == 0xFFFFFFFF)
-				{
-					ki->kip1->caps[i] = 0x07000E7F;
-					break;
-				}
-			}
+			if (section_idx < 3)
+				memcpy(ki->kip1->data + new_offset + inject_size, fs_kip->data + new_offset, fs_kip->sections[section_idx].size_comp);
+			ki->kip1->sections[section_idx].offset += inject_size;
 		}
-
-		free(kipm_data);
-		return 0;
+		new_offset += fs_kip->sections[section_idx].size_comp;
 	}
 
-	return 1;
+	// Patch PMC capabilities for 1.0.0.
+	if (!emu_cfg.fs_ver)
+	{
+		for (u32 i = 0; i < 0x20; i++)
+		{
+			if (ki->kip1->caps[i] == 0xFFFFFFFF)
+			{
+				ki->kip1->caps[i] = 0x07000E7F;
+				break;
+			}
+		}
+	}
+
+	free(kipm_data);
+	return 0;
 }
 
 const char *pkg2_patch_kips(link_t *info, char *patch_names)
@@ -544,7 +542,7 @@ const char *pkg2_patch_kips(link_t *info, char *patch_names)
 
 			// Check if current KIP not hashed and hash it.
 			if (kip_hash[0] == 0)
-				if (!se_sha_hash_256_oneshot(kip_hash, ki->kip1, ki->size))
+				if (se_sha_hash_256_oneshot(kip_hash, ki->kip1, ki->size))
 					memset(kip_hash, 0, sizeof(kip_hash));
 
 			// Check if kip is the expected version.

bootloader/hos/pkg2.h

@@ -208,8 +208,8 @@ typedef struct _nx_bc_t {
 	u8  padding2[0xC0];
 } nx_bc_t;
 
-bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2);
-int  pkg2_has_kip(link_t *info, u64 tid);
+int  pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2);
+bool pkg2_has_kip(link_t *info, u64 tid);
 void pkg2_replace_kip(link_t *info, u64 tid, pkg2_kip1_t *kip1);
 void pkg2_add_kip(link_t *info, pkg2_kip1_t *kip1);
 void pkg2_merge_kip(link_t *info, pkg2_kip1_t *kip1);

bootloader/hos/pkg2_ini_kippatch.c

@@ -104,7 +104,7 @@ int ini_patch_parse(link_t *dst, const char *ini_path)
 
 	// Open ini.
 	if (f_open(&fp, ini_path, FA_READ) != FR_OK)
-		return 0;
+		return 1;
 
 	lbuf = malloc(512);
 
@@ -176,5 +176,5 @@ int ini_patch_parse(link_t *dst, const char *ini_path)
 
 	free(lbuf);
 
-	return 1;
+	return 0;
 }

bootloader/hos/pkg2_patches.inl

@@ -869,6 +869,30 @@ static const kip1_patchset_t _fs_patches_2100_exfat[] = {
 	{ NULL, NULL }
 };
 
+static const kip1_patch_t _fs_nogc_2200[] = {
+	{ KPS(KIP_TEXT) | 0x182F60, 8, KIP1_PATCH_SRC_NO_CHECK, KIP1_FS_NOGC_PATCH_NOINIT },
+	{ KPS(KIP_TEXT) | 0x1B013D, 1, KIP1_PATCH_SRC_NO_CHECK, KIP1_FS_NOGC_PATCH_SDMMC3 },
+	{ KPS(KIP_TEXT) | 0x1B0155, 1, KIP1_PATCH_SRC_NO_CHECK, KIP1_FS_NOGC_PATCH_SDMMC3 },
+	{ 0, 0, NULL, NULL }
+};
+
+static const kip1_patchset_t _fs_patches_2200[] = {
+	{ "nogc",     _fs_nogc_2200 },
+	{ NULL, NULL }
+};
+
+static const kip1_patch_t _fs_nogc_2200_exfat[] = {
+	{ KPS(KIP_TEXT) | 0x18E150, 8, KIP1_PATCH_SRC_NO_CHECK, KIP1_FS_NOGC_PATCH_NOINIT },
+	{ KPS(KIP_TEXT) | 0x1BB32D, 1, KIP1_PATCH_SRC_NO_CHECK, KIP1_FS_NOGC_PATCH_SDMMC3 },
+	{ KPS(KIP_TEXT) | 0x1BB345, 1, KIP1_PATCH_SRC_NO_CHECK, KIP1_FS_NOGC_PATCH_SDMMC3 },
+	{ 0, 0, NULL, NULL }
+};
+
+static const kip1_patchset_t _fs_patches_2200_exfat[] = {
+	{ "nogc",     _fs_nogc_2200_exfat },
+	{ NULL, NULL }
+};
+
 // SHA256 hashes.
 static const kip1_id_t _kip_ids[] =
 {
@@ -942,4 +966,6 @@ static const kip1_id_t _kip_ids[] =
 	{ "FS", "\x6E\x2B\xD9\xBA\xA3\xB9\x10\xF1", _fs_patches_2100_exfat }, // FS 21.0.0 exFAT
 	{ "FS", "\xAF\x1D\xBD\xC7\x82\x98\x3C\xBD", _fs_patches_2100 },       // FS 21.2.0
 	{ "FS", "\x56\x25\x17\xA1\x92\xC3\xC8\xF0", _fs_patches_2100_exfat }, // FS 21.2.0 exFAT
+	{ "FS", "\xB7\xA2\x97\x39\xB7\xED\xDE\xFC", _fs_patches_2200 },       // FS 22.0.0
+	{ "FS", "\xFB\x0B\x68\xDB\x24\x03\xD1\x19", _fs_patches_2200_exfat }, // FS 22.0.0 exFAT
 };

bootloader/hos/pkg3.c

@@ -96,7 +96,7 @@ static int _pkg3_kip1_skip(char ***pkg3_kip1_skip, u32 *pkg3_kip1_skip_num, char
 {
 	int len = strlen(value);
 	if (!len || (*pkg3_kip1_skip_num) >= PKG3_KIP_SKIP_MAX)
-		return 0;
+		return 1;
 
 	// Allocate pointer list memory.
 	if (!(*pkg3_kip1_skip))
@@ -116,11 +116,11 @@ static int _pkg3_kip1_skip(char ***pkg3_kip1_skip, u32 *pkg3_kip1_skip_num, char
 			(*pkg3_kip1_skip)[(*pkg3_kip1_skip_num)++] = c + 1;
 
 			if ((*pkg3_kip1_skip_num) >= PKG3_KIP_SKIP_MAX)
-				return 0;
+				return 1;
 		}
 	}
 
-	return 1;
+	return 0;
 }
 
 int parse_pkg3(launch_ctxt_t *ctxt, const char *path)
@@ -153,15 +153,15 @@ int parse_pkg3(launch_ctxt_t *ctxt, const char *path)
 
 #ifdef HOS_MARIKO_STOCK_SECMON
 	if (stock && emummc_disabled && (pkg1_old || h_cfg.t210b01))
-		return 1;
+		return 0;
 #else
 	if (stock && emummc_disabled && pkg1_old)
-		return 1;
+		return 0;
 #endif
 
 	// Try to open PKG3.
 	if (f_open(&fp, path, FA_READ) != FR_OK)
-		return 0;
+		return 1;
 
 	void *pkg3 = malloc(f_size(&fp));
 
@@ -268,7 +268,7 @@ int parse_pkg3(launch_ctxt_t *ctxt, const char *path)
 
 		free(pkg3_kip1_skip);
 
-		return 1;
+		return 0;
 	}
 
 	// Failed. Close and free all.
@@ -277,5 +277,5 @@ int parse_pkg3(launch_ctxt_t *ctxt, const char *path)
 	free(pkg3_kip1_skip);
 	free(pkg3);
 
-	return 0;
+	return 1;
 }

bootloader/hos/secmon_exo.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2025 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  * Copyright (c) 2019 Atmosphère-NX
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -136,6 +136,7 @@ typedef struct _atm_fatal_error_ctx
 #define  EXO_FLAG_CAL0_BLANKING   BIT(5)
 #define  EXO_FLAG_CAL0_WRITES_SYS BIT(6)
 #define  EXO_FLAG_ENABLE_USB3     BIT(7)
+#define  EXO_FLAG_BC_MEM_MODE     BIT(8)
 
 #define EXO_FW_VER(mj, mn) (((mj) << 24) | ((mn) << 16))
 
@@ -145,6 +146,7 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base)
 	u32 exo_flags = 0;
 	bool usb3_force = false;
 	bool user_debug = false;
+	bool bc_mem_mode = false;
 	bool cal0_blanking = false;
 	bool cal0_allow_writes_sys = false;
 
@@ -197,7 +199,7 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base)
 	case 12:
 		exo_fw_no = EXO_FW_VER(9, 1);
 		break;
-	case 13 ... 24: //!TODO: Update on API changes. 24: 21.0.0.
+	case 13 ... 25: //!TODO: Update on API changes. 25: 22.0.0.
 		exo_fw_no = EXO_FW_VER(exo_fw_no - 3, ctxt->exo_ctx.hos_revision);
 		break;
 	}
@@ -206,7 +208,7 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base)
 	if (!ctxt->stock)
 	{
 		LIST_INIT(ini_exo_sections);
-		if (ini_parse(&ini_exo_sections, "exosphere.ini", false))
+		if (!ini_parse(&ini_exo_sections, "exosphere.ini", false))
 		{
 			LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_exo_sections, link)
 			{
@@ -224,6 +226,8 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base)
 						exo_cfg->uart_invert = atoi(kv->val);
 					else if (!strcmp("log_baud_rate", kv->key))
 						exo_cfg->uart_baudrate = atoi(kv->val);
+					else if (!strcmp("enable_mem_mode", kv->key))
+						bc_mem_mode = atoi(kv->val);
 					else if (emu_cfg.enabled && !h_cfg.emummc_force_disable)
 					{
 						if (!strcmp("blank_prodinfo_emummc", kv->key))
@@ -245,7 +249,7 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base)
 		if (!ctxt->exo_ctx.usb3_force)
 		{
 			LIST_INIT(ini_sys_sections);
-			if (ini_parse(&ini_sys_sections, "atmosphere/config/system_settings.ini", false))
+			if (!ini_parse(&ini_sys_sections, "atmosphere/config/system_settings.ini", false))
 			{
 				LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sys_sections, link)
 				{
@@ -283,6 +287,11 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base)
 	if (ctxt->exo_ctx.user_pmu)
 		exo_flags |= EXO_FLAG_USER_PMU;
 
+	// Enable Boot Config Memory Mode. Check if system_settings ini value is overridden. If not, check if enabled in ini.
+	if ((ctxt->exo_ctx.force_mem_mode && *ctxt->exo_ctx.force_mem_mode)
+			|| (!ctxt->exo_ctx.force_mem_mode && bc_mem_mode))
+		exo_flags |= EXO_FLAG_BC_MEM_MODE;
+
 	// Enable USB 3.0. Check if system_settings ini value is overridden. If not, check if enabled in ini.
 	if ((ctxt->exo_ctx.usb3_force && *ctxt->exo_ctx.usb3_force)
 			|| (!ctxt->exo_ctx.usb3_force && usb3_force))

bootloader/l4t/l4t.c

@@ -19,7 +19,6 @@
 #include <string.h>
 
 #include <bdk.h>
-#include <soc/pmc_lp0_t210.h>
 
 #include "../hos/hos.h"
 #include "../hos/pkg1.h"
@@ -353,21 +352,21 @@ static int _l4t_sd_load(u32 idx)
 
 static void _l4t_sdram_lp0_save_params(bool t210b01)
 {
-	struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)PMC_BASE;
+	pmc_regs_t210_t *pmc = (pmc_regs_t210_t *)PMC_BASE;
 
 #define _REG_S(base, off) *(u32 *)((base) + (off))
 #define MC_S(off) _REG_S(MC_BASE, off)
 
 #define pack(src, src_bits, dst, dst_bits) { \
-		u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
+		u32 mask = 0xFFFFFFFF >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
 		dst &= ~(mask << (0 ? dst_bits)); \
 		dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); }
 
 #define s(param, src_bits, pmcreg, dst_bits) \
-	pack(MC_S(param), src_bits, pmc->pmcreg, dst_bits)
+	pack(MC_S(param), src_bits, pmc->pmc_ ## pmcreg, dst_bits)
 
 // 32 bits version of s macro.
-#define s32(param, pmcreg) pmc->pmcreg = MC_S(param)
+#define s32(param, pmcreg) pmc->pmc_ ## pmcreg = MC_S(param)
 
 	// Only save changed carveout registers into PMC for SC7 Exit.
 
@@ -702,7 +701,7 @@ static void _l4t_late_hw_config(bool t210b01)
 	PMC(APBDEV_PMC_SCRATCH201) = BIT(1);
 
 	// Clear PLLM override for SC7.
-	PMC(APBDEV_PMC_PLLP_WB0_OVERRIDE) &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE_ENABLE;
+	PMC(APBDEV_PMC_PLLP_WB0_OVERRIDE) &= ~PMC_PLLP_WB0_OVR_PLLM_OVR_ENABLE;
 
 	// Set spare reg to 0xE0000 and clear everything else.
 	if (t210b01 && (SYSREG(AHB_AHB_SPARE_REG) & 0xE0000000) != 0xE0000000)
@@ -806,7 +805,7 @@ static void _l4t_bpmpfw_b01_config(l4t_ctxt_t *ctxt)
 
 	// Save BPMP-FW entrypoint for TZ.
 	PMC(APBDEV_PMC_SCRATCH39) = BPMPFW_B01_ENTRYPOINT;
-	PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1) |= BIT(15);
+	PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1_B01) |= BIT(15);
 }
 
 static int _l4t_sc7_exit_config(bool t210b01)
@@ -825,7 +824,7 @@ static int _l4t_sc7_exit_config(bool t210b01)
 	{
 		// Get latest SC7-Exit if needed and setup PA id.
 		launch_ctxt_t hos_ctxt = {0};
-		if (!pkg1_warmboot_config(&hos_ctxt, 0, 0, 0))
+		if (pkg1_warmboot_config(&hos_ctxt, 0, 0, 0))
 		{
 			gfx_con.mute = false;
 			gfx_wputs("\nFailed to match warmboot with fuses!\nIf you continue, sleep wont work!");
@@ -833,7 +832,7 @@ static int _l4t_sc7_exit_config(bool t210b01)
 			gfx_puts("\nPress POWER to continue.\nPress VOL to go to the menu.\n");
 
 			if (!(btn_wait() & BTN_POWER))
-				return 0;
+				return 1;
 		}
 
 		// Copy loaded warmboot fw to address if from storage.
@@ -845,7 +844,7 @@ static int _l4t_sc7_exit_config(bool t210b01)
 		PMC(APBDEV_PMC_SEC_DISABLE8) |= BIT(30);
 	}
 
-	return 1;
+	return 0;
 }
 
 static void _l4t_bl33_cfg_set_key(char *env, const char *key, const char *val)
@@ -1022,7 +1021,7 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
 	}
 
 	// Set SC7-Exit firmware address to PMC for bootrom and do further setup.
-	if (!_l4t_sc7_exit_config(t210b01))
+	if (_l4t_sc7_exit_config(t210b01))
 		return;
 
 	// Done loading bootloaders/firmware.

bootloader/libs/fatfs/diskio.c

@@ -43,7 +43,7 @@ DRESULT disk_read (
 	UINT count		/* Number of sectors to read */
 )
 {
-	return sdmmc_storage_read(&sd_storage, sector, count, buff) ? RES_OK : RES_ERROR;
+	return sdmmc_storage_read(&sd_storage, sector, count, buff);
 }
 
 /*-----------------------------------------------------------------------*/
@@ -56,7 +56,7 @@ DRESULT disk_write (
 	UINT count			/* Number of sectors to write */
 )
 {
-	return sdmmc_storage_write(&sd_storage, sector, count, (void *)buff) ? RES_OK : RES_ERROR;
+	return sdmmc_storage_write(&sd_storage, sector, count, (void *)buff);
 }
 
 /*-----------------------------------------------------------------------*/

bootloader/main.c

@@ -228,7 +228,7 @@ static void _launch_payloads()
 	gfx_clear_grey(0x1B);
 	gfx_con_setpos(0, 0);
 
-	if (!sd_mount())
+	if (sd_mount())
 		goto failed_sd_mount;
 
 	ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 3));
@@ -310,11 +310,11 @@ static void _launch_ini_list()
 	gfx_clear_grey(0x1B);
 	gfx_con_setpos(0, 0);
 
-	if (!sd_mount())
+	if (sd_mount())
 		goto parse_failed;
 
 	// Check that ini files exist and parse them.
-	if (!ini_parse(&ini_list_sections, "bootloader/ini", true))
+	if (ini_parse(&ini_list_sections, "bootloader/ini", true))
 	{
 		EPRINTF("No .ini files in bootloader/ini!");
 		goto parse_failed;
@@ -440,7 +440,7 @@ static void _launch_config()
 	gfx_clear_grey(0x1B);
 	gfx_con_setpos(0, 0);
 
-	if (!sd_mount())
+	if (sd_mount())
 		goto parse_failed;
 
 	// Load emuMMC configuration.
@@ -752,7 +752,7 @@ static void _auto_launch()
 	emummc_load_cfg();
 
 	// Parse hekate main configuration.
-	if (!ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false))
+	if (ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false))
 		goto out; // Can't load hekate_ipl.ini.
 
 	// Load configuration.
@@ -839,7 +839,7 @@ static void _auto_launch()
 		boot_entry_id = 1;
 		bootlogoCustomEntry = NULL;
 
-		if (!ini_parse(&ini_list_sections, "bootloader/ini", true))
+		if (ini_parse(&ini_list_sections, "bootloader/ini", true))
 			goto skip_list;
 
 		LIST_FOREACH_ENTRY(ini_sec_t, ini_sec_list, &ini_list_sections, link)
@@ -1015,15 +1015,15 @@ out:
 	_nyx_load_run();
 }
 
-#define EXCP_EN_ADDR   0x4003FFFC
+#define EXCP_EN_ADDR   0x4003FF1C
 #define  EXCP_MAGIC       0x30505645 // "EVP0".
-#define EXCP_TYPE_ADDR 0x4003FFF8
+#define EXCP_TYPE_ADDR 0x4003FF18
 #define  EXCP_TYPE_RESET  0x545352   // "RST".
 #define  EXCP_TYPE_UNDEF  0x464455   // "UDF".
 #define  EXCP_TYPE_PABRT  0x54424150 // "PABT".
 #define  EXCP_TYPE_DABRT  0x54424144 // "DABT".
 #define  EXCP_TYPE_WDT    0x544457   // "WDT".
-#define EXCP_LR_ADDR   0x4003FFF4
+#define EXCP_LR_ADDR   0x4003FF14
 
 #define PSTORE_LOG_OFFSET 0x180000
 #define PSTORE_RAM_SIG    0x43474244 // "DBGC".
@@ -1426,7 +1426,7 @@ ment_t ment_top[] = {
 	MDEF_END()
 };
 
-menu_t menu_top = { ment_top, "hekate v6.5.1", 0, 0 };
+menu_t menu_top = { ment_top, "hekate v6.5.2", 0, 0 };
 
 extern void pivot_stack(u32 stack_top);
 
@@ -1466,7 +1466,8 @@ void ipl_main()
 	bpmp_clk_rate_set(h_cfg.t210b01 ? ipl_ver.rcfg.bclk_t210b01 : ipl_ver.rcfg.bclk_t210);
 
 	// Mount SD Card.
-	h_cfg.errors |= !sd_mount() ? ERR_SD_BOOT_EN : 0;
+	if (sd_mount())
+		h_cfg.errors |= ERR_SD_BOOT_EN;
 
 	// Check if watchdog was fired previously.
 	if (watchdog_fired())
@@ -1477,7 +1478,7 @@ void ipl_main()
 
 	// Save sdram lp0 config.
 	void *sdram_params = h_cfg.t210b01 ? sdram_get_params_t210b01() : sdram_get_params_patched();
-	if (!ianos_loader("bootloader/sys/libsys_lp0.bso", DRAM_LIB, sdram_params))
+	if (!ianos_static_module("bootloader/sys/libsys_lp0.bso", sdram_params))
 		h_cfg.errors |= ERR_LIBSYS_LP0;
 
 	// Train DRAM and switch to max frequency.

bootloader/storage/emummc.c

@@ -43,7 +43,7 @@ void emummc_load_cfg()
 	emu_cfg.emummc_file_based_path[0] = 0;
 
 	LIST_INIT(ini_sections);
-	if (ini_parse(&ini_sections, "emuMMC/emummc.ini", false))
+	if (!ini_parse(&ini_sections, "emuMMC/emummc.ini", false))
 	{
 		LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link)
 		{
@@ -137,13 +137,13 @@ int emummc_storage_init_mmc()
 	emu_cfg.active_part = 0;
 
 	// Always init eMMC even when in emuMMC. eMMC is needed from the emuMMC driver anyway.
-	if (!emmc_initialize(false))
+	if (emmc_initialize(false))
 		return 2;
 
 	if (!emu_cfg.enabled || h_cfg.emummc_force_disable)
 		return 0;
 
-	if (!sd_mount())
+	if (sd_mount())
 		goto out;
 
 	if (!emu_cfg.sector)
@@ -180,7 +180,7 @@ int emummc_storage_end()
 	else
 		sd_end();
 
-	return 1;
+	return 0;
 }
 
 int emummc_storage_read(u32 sector, u32 num_sectors, void *buf)
@@ -211,21 +211,19 @@ int emummc_storage_read(u32 sector, u32 num_sectors, void *buf)
 		if (f_open(&fp, emu_cfg.emummc_file_based_path, FA_READ))
 		{
 			EPRINTF("Failed to open emuMMC image.");
-			return 0;
+			return 1;
 		}
 		f_lseek(&fp, (u64)sector << 9);
 		if (f_read(&fp, buf, (u64)num_sectors << 9, NULL))
 		{
 			EPRINTF("Failed to read emuMMC image.");
 			f_close(&fp);
-			return 0;
+			return 1;
 		}
 
 		f_close(&fp);
-		return 1;
+		return 0;
 	}
-
-	return 1;
 }
 
 int emummc_storage_write(u32 sector, u32 num_sectors, void *buf)
@@ -255,17 +253,17 @@ int emummc_storage_write(u32 sector, u32 num_sectors, void *buf)
 		}
 
 		if (f_open(&fp, emu_cfg.emummc_file_based_path, FA_WRITE))
-			return 0;
+			return 1;
 
 		f_lseek(&fp, (u64)sector << 9);
 		if (f_write(&fp, buf, (u64)num_sectors << 9, NULL))
 		{
 			f_close(&fp);
-			return 0;
+			return 1;
 		}
 
 		f_close(&fp);
-		return 1;
+		return 0;
 	}
 }
 
@@ -275,7 +273,7 @@ int emummc_storage_set_mmc_partition(u32 partition)
 	emmc_set_partition(partition);
 
 	if (!emu_cfg.enabled || h_cfg.emummc_force_disable || emu_cfg.sector)
-		return 1;
+		return 0;
 	else
 	{
 		strcpy(emu_cfg.emummc_file_based_path, emu_cfg.path);
@@ -294,8 +292,6 @@ int emummc_storage_set_mmc_partition(u32 partition)
 			break;
 		}
 
-		return 1;
+		return 0;
 	}
-
-	return 1;
 }

modules/hekate_libsys_lp0/Makefile

@@ -20,7 +20,7 @@ OBJS = $(addprefix $(BUILDDIR)/,\
 
 ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork
 CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall -Wsign-compare $(CUSTOMDEFINES)
-LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc
+LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc -Wl,-z,max-page-size=256
 
 .PHONY: all
 

modules/hekate_libsys_lp0/pmc_lp0_t210.h

@@ -1,564 +0,0 @@
-/*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-#ifndef _TEGRA210_PMC_H_
-#define _TEGRA210_PMC_H_
-
-#include "types.h"
-
-struct tegra_pmc_regs
-{
-	u32 cntrl;
-	u32 sec_disable;
-	u32 pmc_swrst;
-	u32 wake_mask;
-	u32 wake_lvl;
-	u32 wake_status;
-	u32 sw_wake_status;
-	u32 dpd_pads_oride;
-	u32 dpd_sample;
-	u32 dpd_enable;
-	u32 pwrgate_timer_off;
-	u32 clamp_status;
-	u32 pwrgate_toggle;
-	u32 remove_clamping_cmd;
-	u32 pwrgate_status;
-	u32 pwrgood_timer;
-	u32 blink_timer;
-	u32 no_iopower;
-	u32 pwr_det;
-	u32 pwr_det_latch;
-	u32 scratch0;
-	u32 scratch1;
-	u32 scratch2;
-	u32 scratch3;
-	u32 scratch4;
-	u32 scratch5;
-	u32 scratch6;
-	u32 scratch7;
-	u32 scratch8;
-	u32 scratch9;
-	u32 scratch10;
-	u32 scratch11;
-	u32 scratch12;
-	u32 scratch13;
-	u32 scratch14;
-	u32 scratch15;
-	u32 scratch16;
-	u32 scratch17;
-	u32 scratch18;
-	u32 scratch19;
-	u32 odmdata;
-	u32 scratch21;
-	u32 scratch22;
-	u32 scratch23;
-	u32 secure_scratch0;
-	u32 secure_scratch1;
-	u32 secure_scratch2;
-	u32 secure_scratch3;
-	u32 secure_scratch4;
-	u32 secure_scratch5;
-	u32 cpupwrgood_timer;
-	u32 cpupwroff_timer;
-	u32 pg_mask;
-	u32 pg_mask_1;
-	u32 auto_wake_lvl;
-	u32 auto_wake_lvl_mask;
-	u32 wake_delay;
-	u32 pwr_det_val;
-	u32 ddr_pwr;
-	u32 usb_debounce_del;
-	u32 usb_a0;
-	u32 crypto_op;
-	u32 pllp_wb0_override;
-	u32 scratch24;
-	u32 scratch25;
-	u32 scratch26;
-	u32 scratch27;
-	u32 scratch28;
-	u32 scratch29;
-	u32 scratch30;
-	u32 scratch31;
-	u32 scratch32;
-	u32 scratch33;
-	u32 scratch34;
-	u32 scratch35;
-	u32 scratch36;
-	u32 scratch37;
-	u32 scratch38;
-	u32 scratch39;
-	u32 scratch40;
-	u32 scratch41;
-	u32 scratch42;
-	u32 bondout_mirror[3];
-	u32 sys_33v_en;
-	u32 bondout_mirror_access;
-	u32 gate;
-	u32 wake2_mask;
-	u32 wake2_lvl;
-	u32 wake2_status;
-	u32 sw_wake2_status;
-	u32 auto_wake2_lvl_mask;
-	u32 pg_mask_2;
-	u32 pg_mask_ce1;
-	u32 pg_mask_ce2;
-	u32 pg_mask_ce3;
-	u32 pwrgate_timer_ce[7];
-	u32 pcx_edpd_cntrl;
-	u32 osc_edpd_over;
-	u32 clk_out_cntrl;
-	u32 sata_pwrgt;
-	u32 sensor_ctrl;
-	u32 rst_status;
-	u32 io_dpd_req;
-	u32 io_dpd_status;
-	u32 io_dpd2_req;
-	u32 io_dpd2_status;
-	u32 sel_dpd_tim;
-	u32 vddp_sel;
-	u32 ddr_cfg;
-	u32 e_no_vttgen;
-	u8 _rsv0[4];
-	u32 pllm_wb0_override_freq;
-	u32 test_pwrgate;
-	u32 pwrgate_timer_mult;
-	u32 dis_sel_dpd;
-	u32 utmip_uhsic_triggers;
-	u32 utmip_uhsic_saved_state;
-	u32 utmip_pad_cfg;
-	u32 utmip_term_pad_cfg;
-	u32 utmip_uhsic_sleep_cfg;
-	u32 utmip_uhsic_sleepwalk_cfg;
-	u32 utmip_sleepwalk_p[3];
-	u32 uhsic_sleepwalk_p0;
-	u32 utmip_uhsic_status;
-	u32 utmip_uhsic_fake;
-	u32 bondout_mirror3[5 - 3];
-	u32 secure_scratch6;
-	u32 secure_scratch7;
-	u32 scratch43;
-	u32 scratch44;
-	u32 scratch45;
-	u32 scratch46;
-	u32 scratch47;
-	u32 scratch48;
-	u32 scratch49;
-	u32 scratch50;
-	u32 scratch51;
-	u32 scratch52;
-	u32 scratch53;
-	u32 scratch54;
-	u32 scratch55;
-	u32 scratch0_eco;
-	u32 por_dpd_ctrl;
-	u32 scratch2_eco;
-	u32 utmip_uhsic_line_wakeup;
-	u32 utmip_bias_master_cntrl;
-	u32 utmip_master_config;
-	u32 td_pwrgate_inter_part_timer;
-	u32 utmip_uhsic2_triggers;
-	u32 utmip_uhsic2_saved_state;
-	u32 utmip_uhsic2_sleep_cfg;
-	u32 utmip_uhsic2_sleepwalk_cfg;
-	u32 uhsic2_sleepwalk_p1;
-	u32 utmip_uhsic2_status;
-	u32 utmip_uhsic2_fake;
-	u32 utmip_uhsic2_line_wakeup;
-	u32 utmip_master2_config;
-	u32 utmip_uhsic_rpd_cfg;
-	u32 pg_mask_ce0;
-	u32 pg_mask3[5 - 3];
-	u32 pllm_wb0_override2;
-	u32 tsc_mult;
-	u32 cpu_vsense_override;
-	u32 glb_amap_cfg;
-	u32 sticky_bits;
-	u32 sec_disable2;
-	u32 weak_bias;
-	u32 reg_short;
-	u32 pg_mask_andor;
-	u8 _rsv1[0x2c];
-	u32 secure_scratch8;	/* offset 0x300 */
-	u32 secure_scratch9;
-	u32 secure_scratch10;
-	u32 secure_scratch11;
-	u32 secure_scratch12;
-	u32 secure_scratch13;
-	u32 secure_scratch14;
-	u32 secure_scratch15;
-	u32 secure_scratch16;
-	u32 secure_scratch17;
-	u32 secure_scratch18;
-	u32 secure_scratch19;
-	u32 secure_scratch20;
-	u32 secure_scratch21;
-	u32 secure_scratch22;
-	u32 secure_scratch23;
-	u32 secure_scratch24;
-	u32 secure_scratch25;
-	u32 secure_scratch26;
-	u32 secure_scratch27;
-	u32 secure_scratch28;
-	u32 secure_scratch29;
-	u32 secure_scratch30;
-	u32 secure_scratch31;
-	u32 secure_scratch32;
-	u32 secure_scratch33;
-	u32 secure_scratch34;
-	u32 secure_scratch35;
-	u32 secure_scratch36;
-	u32 secure_scratch37;
-	u32 secure_scratch38;
-	u32 secure_scratch39;
-	u32 secure_scratch40;
-	u32 secure_scratch41;
-	u32 secure_scratch42;
-	u32 secure_scratch43;
-	u32 secure_scratch44;
-	u32 secure_scratch45;
-	u32 secure_scratch46;
-	u32 secure_scratch47;
-	u32 secure_scratch48;
-	u32 secure_scratch49;
-	u32 secure_scratch50;
-	u32 secure_scratch51;
-	u32 secure_scratch52;
-	u32 secure_scratch53;
-	u32 secure_scratch54;
-	u32 secure_scratch55;
-	u32 secure_scratch56;
-	u32 secure_scratch57;
-	u32 secure_scratch58;
-	u32 secure_scratch59;
-	u32 secure_scratch60;
-	u32 secure_scratch61;
-	u32 secure_scratch62;
-	u32 secure_scratch63;
-	u32 secure_scratch64;
-	u32 secure_scratch65;
-	u32 secure_scratch66;
-	u32 secure_scratch67;
-	u32 secure_scratch68;
-	u32 secure_scratch69;
-	u32 secure_scratch70;
-	u32 secure_scratch71;
-	u32 secure_scratch72;
-	u32 secure_scratch73;
-	u32 secure_scratch74;
-	u32 secure_scratch75;
-	u32 secure_scratch76;
-	u32 secure_scratch77;
-	u32 secure_scratch78;
-	u32 secure_scratch79;
-	u32 _rsv0x420[8];
-	u32 cntrl2;			/* 0x440 */
-	u32 _rsv0x444[2];
-	u32 event_counter;	/* 0x44C */
-	u32 fuse_control;
-	u32 scratch1_eco;
-	u32 _rsv0x458[1];
-	u32 io_dpd3_req;	/* 0x45C */
-	u32 io_dpd3_status;
-	u32 io_dpd4_req;
-	u32 io_dpd4_status;
-	u32 _rsv0x46C[30];
-	u32 ddr_cntrl;		/* 0x4E4 */
-	u32 _rsv0x4E8[70];
-	u32 scratch56;		/* 0x600 */
-	u32 scratch57;
-	u32 scratch58;
-	u32 scratch59;
-	u32 scratch60;
-	u32 scratch61;
-	u32 scratch62;
-	u32 scratch63;
-	u32 scratch64;
-	u32 scratch65;
-	u32 scratch66;
-	u32 scratch67;
-	u32 scratch68;
-	u32 scratch69;
-	u32 scratch70;
-	u32 scratch71;
-	u32 scratch72;
-	u32 scratch73;
-	u32 scratch74;
-	u32 scratch75;
-	u32 scratch76;
-	u32 scratch77;
-	u32 scratch78;
-	u32 scratch79;
-	u32 scratch80;
-	u32 scratch81;
-	u32 scratch82;
-	u32 scratch83;
-	u32 scratch84;
-	u32 scratch85;
-	u32 scratch86;
-	u32 scratch87;
-	u32 scratch88;
-	u32 scratch89;
-	u32 scratch90;
-	u32 scratch91;
-	u32 scratch92;
-	u32 scratch93;
-	u32 scratch94;
-	u32 scratch95;
-	u32 scratch96;
-	u32 scratch97;
-	u32 scratch98;
-	u32 scratch99;
-	u32 scratch100;
-	u32 scratch101;
-	u32 scratch102;
-	u32 scratch103;
-	u32 scratch104;
-	u32 scratch105;
-	u32 scratch106;
-	u32 scratch107;
-	u32 scratch108;
-	u32 scratch109;
-	u32 scratch110;
-	u32 scratch111;
-	u32 scratch112;
-	u32 scratch113;
-	u32 scratch114;
-	u32 scratch115;
-	u32 scratch116;
-	u32 scratch117;
-	u32 scratch118;
-	u32 scratch119;
-	u32 scratch120;		/* 0x700 */
-	u32 scratch121;
-	u32 scratch122;
-	u32 scratch123;
-	u32 scratch124;
-	u32 scratch125;
-	u32 scratch126;
-	u32 scratch127;
-	u32 scratch128;
-	u32 scratch129;
-	u32 scratch130;
-	u32 scratch131;
-	u32 scratch132;
-	u32 scratch133;
-	u32 scratch134;
-	u32 scratch135;
-	u32 scratch136;
-	u32 scratch137;
-	u32 scratch138;
-	u32 scratch139;
-	u32 scratch140;
-	u32 scratch141;
-	u32 scratch142;
-	u32 scratch143;
-	u32 scratch144;
-	u32 scratch145;
-	u32 scratch146;
-	u32 scratch147;
-	u32 scratch148;
-	u32 scratch149;
-	u32 scratch150;
-	u32 scratch151;
-	u32 scratch152;
-	u32 scratch153;
-	u32 scratch154;
-	u32 scratch155;
-	u32 scratch156;
-	u32 scratch157;
-	u32 scratch158;
-	u32 scratch159;
-	u32 scratch160;
-	u32 scratch161;
-	u32 scratch162;
-	u32 scratch163;
-	u32 scratch164;
-	u32 scratch165;
-	u32 scratch166;
-	u32 scratch167;
-	u32 scratch168;
-	u32 scratch169;
-	u32 scratch170;
-	u32 scratch171;
-	u32 scratch172;
-	u32 scratch173;
-	u32 scratch174;
-	u32 scratch175;
-	u32 scratch176;
-	u32 scratch177;
-	u32 scratch178;
-	u32 scratch179;
-	u32 scratch180;
-	u32 scratch181;
-	u32 scratch182;
-	u32 scratch183;
-	u32 scratch184;
-	u32 scratch185;
-	u32 scratch186;
-	u32 scratch187;
-	u32 scratch188;
-	u32 scratch189;
-	u32 scratch190;
-	u32 scratch191;
-	u32 scratch192;
-	u32 scratch193;
-	u32 scratch194;
-	u32 scratch195;
-	u32 scratch196;
-	u32 scratch197;
-	u32 scratch198;
-	u32 scratch199;
-	u32 scratch200;
-	u32 scratch201;
-	u32 scratch202;
-	u32 scratch203;
-	u32 scratch204;
-	u32 scratch205;
-	u32 scratch206;
-	u32 scratch207;
-	u32 scratch208;
-	u32 scratch209;
-	u32 scratch210;
-	u32 scratch211;
-	u32 scratch212;
-	u32 scratch213;
-	u32 scratch214;
-	u32 scratch215;
-	u32 scratch216;
-	u32 scratch217;
-	u32 scratch218;
-	u32 scratch219;
-	u32 scratch220;
-	u32 scratch221;
-	u32 scratch222;
-	u32 scratch223;
-	u32 scratch224;
-	u32 scratch225;
-	u32 scratch226;
-	u32 scratch227;
-	u32 scratch228;
-	u32 scratch229;
-	u32 scratch230;
-	u32 scratch231;
-	u32 scratch232;
-	u32 scratch233;
-	u32 scratch234;
-	u32 scratch235;
-	u32 scratch236;
-	u32 scratch237;
-	u32 scratch238;
-	u32 scratch239;
-	u32 scratch240;
-	u32 scratch241;
-	u32 scratch242;
-	u32 scratch243;
-	u32 scratch244;
-	u32 scratch245;
-	u32 scratch246;
-	u32 scratch247;
-	u32 scratch248;
-	u32 scratch249;
-	u32 scratch250;
-	u32 scratch251;
-	u32 scratch252;
-	u32 scratch253;
-	u32 scratch254;
-	u32 scratch255;
-	u32 scratch256;
-	u32 scratch257;
-	u32 scratch258;
-	u32 scratch259;
-	u32 scratch260;
-	u32 scratch261;
-	u32 scratch262;
-	u32 scratch263;
-	u32 scratch264;
-	u32 scratch265;
-	u32 scratch266;
-	u32 scratch267;
-	u32 scratch268;
-	u32 scratch269;
-	u32 scratch270;
-	u32 scratch271;
-	u32 scratch272;
-	u32 scratch273;
-	u32 scratch274;
-	u32 scratch275;
-	u32 scratch276;
-	u32 scratch277;
-	u32 scratch278;
-	u32 scratch279;
-	u32 scratch280;
-	u32 scratch281;
-	u32 scratch282;
-	u32 scratch283;
-	u32 scratch284;
-	u32 scratch285;
-	u32 scratch286;
-	u32 scratch287;
-	u32 scratch288;
-	u32 scratch289;
-	u32 scratch290;
-	u32 scratch291;
-	u32 scratch292;
-	u32 scratch293;
-	u32 scratch294;
-	u32 scratch295;
-	u32 scratch296;
-	u32 scratch297;
-	u32 scratch298;
-	u32 scratch299;			/* 0x9CC */
-	u32 _rsv0x9D0[50];
-	u32 secure_scratch80;	/* 0xa98 */
-	u32 secure_scratch81;
-	u32 secure_scratch82;
-	u32 secure_scratch83;
-	u32 secure_scratch84;
-	u32 secure_scratch85;
-	u32 secure_scratch86;
-	u32 secure_scratch87;
-	u32 secure_scratch88;
-	u32 secure_scratch89;
-	u32 secure_scratch90;
-	u32 secure_scratch91;
-	u32 secure_scratch92;
-	u32 secure_scratch93;
-	u32 secure_scratch94;
-	u32 secure_scratch95;
-	u32 secure_scratch96;
-	u32 secure_scratch97;
-	u32 secure_scratch98;
-	u32 secure_scratch99;
-	u32 secure_scratch100;
-	u32 secure_scratch101;
-	u32 secure_scratch102;
-	u32 secure_scratch103;
-	u32 secure_scratch104;
-	u32 secure_scratch105;
-	u32 secure_scratch106;
-	u32 secure_scratch107;
-	u32 secure_scratch108;
-	u32 secure_scratch109;
-	u32 secure_scratch110;
-	u32 secure_scratch111;
-	u32 secure_scratch112;
-	u32 secure_scratch113;
-	u32 secure_scratch114;
-	u32 secure_scratch115;
-	u32 secure_scratch116;
-	u32 secure_scratch117;
-	u32 secure_scratch118;
-	u32 secure_scratch119;
-};
-
-#endif	/* _TEGRA210_PMC_H_ */

modules/hekate_libsys_lp0/pmc_t210.h

@@ -0,0 +1,671 @@
+/*
+ * Copyright (c) 2018-2026 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _PMC_T210_H_
+#define _PMC_T210_H_
+
+#include "types.h"
+
+typedef struct _pmc_regs_t210_t  {
+/* 0x000 */	u32 pmc_cntrl;
+/* 0x004 */	u32 pmc_sec_disable;
+/* 0x008 */	u32 pmc_pmc_swrst;
+/* 0x00c */	u32 pmc_wake_mask;
+/* 0x010 */	u32 pmc_wake_lvl;
+/* 0x014 */	u32 pmc_wake_status;
+/* 0x018 */	u32 pmc_sw_wake_status;
+/* 0x01c */	u32 pmc_dpd_pads_oride;
+/* 0x020 */	u32 pmc_dpd_sample;
+/* 0x024 */	u32 pmc_dpd_enable;
+/* 0x028 */	u32 pmc_pwrgate_timer_off;
+/* 0x02c */	u32 pmc_clamp_status;
+/* 0x030 */	u32 pmc_pwrgate_toggle;
+/* 0x034 */	u32 pmc_remove_clamping_cmd;
+/* 0x038 */	u32 pmc_pwrgate_status;
+/* 0x03c */	u32 pmc_pwrgood_timer;
+/* 0x040 */	u32 pmc_blink_timer;
+/* 0x044 */	u32 pmc_no_iopower;
+/* 0x048 */	u32 pmc_pwr_det;
+/* 0x04c */	u32 pmc_pwr_det_latch;
+/* 0x050 */	u32 pmc_scratch0;
+/* 0x054 */	u32 pmc_scratch1;
+/* 0x058 */	u32 pmc_scratch2;
+/* 0x05c */	u32 pmc_scratch3;
+/* 0x060 */	u32 pmc_scratch4;
+/* 0x064 */	u32 pmc_scratch5;
+/* 0x068 */	u32 pmc_scratch6;
+/* 0x06c */	u32 pmc_scratch7;
+/* 0x070 */	u32 pmc_scratch8;
+/* 0x074 */	u32 pmc_scratch9;
+/* 0x078 */	u32 pmc_scratch10;
+/* 0x07c */	u32 pmc_scratch11;
+/* 0x080 */	u32 pmc_scratch12;
+/* 0x084 */	u32 pmc_scratch13;
+/* 0x088 */	u32 pmc_scratch14;
+/* 0x08c */	u32 pmc_scratch15;
+/* 0x090 */	u32 pmc_scratch16;
+/* 0x094 */	u32 pmc_scratch17;
+/* 0x098 */	u32 pmc_scratch18;
+/* 0x09c */	u32 pmc_scratch19;
+/* 0x0a0 */	u32 pmc_scratch20; // ODM data/config scratch.
+/* 0x0a4 */	u32 pmc_scratch21;
+/* 0x0a8 */	u32 pmc_scratch22;
+/* 0x0ac */	u32 pmc_scratch23;
+/* 0x0b0 */	u32 pmc_secure_scratch0;
+/* 0x0b4 */	u32 pmc_secure_scratch1;
+/* 0x0b8 */	u32 pmc_secure_scratch2;
+/* 0x0bc */	u32 pmc_secure_scratch3;
+/* 0x0c0 */	u32 pmc_secure_scratch4;
+/* 0x0c4 */	u32 pmc_secure_scratch5;
+/* 0x0c8 */	u32 pmc_cpupwrgood_timer;
+/* 0x0cc */	u32 pmc_cpupwroff_timer;
+/* 0x0d0 */	u32 pmc_pg_mask;
+/* 0x0d4 */	u32 pmc_pg_mask_1;
+/* 0x0d8 */	u32 pmc_auto_wake_lvl;
+/* 0x0dc */	u32 pmc_auto_wake_lvl_mask;
+/* 0x0e0 */	u32 pmc_wake_delay;
+/* 0x0e4 */	u32 pmc_pwr_det_val;
+/* 0x0e8 */	u32 pmc_ddr_pwr;
+/* 0x0ec */	u32 pmc_usb_debounce_del;
+/* 0x0f0 */	u32 pmc_usb_ao;
+/* 0x0f4 */	u32 pmc_crypto_op;
+/* 0x0f8 */	u32 pmc_pllp_wb0_override;
+/* 0x0fc */	u32 pmc_scratch24;
+/* 0x100 */	u32 pmc_scratch25;
+/* 0x104 */	u32 pmc_scratch26;
+/* 0x108 */	u32 pmc_scratch27;
+/* 0x10c */	u32 pmc_scratch28;
+/* 0x110 */	u32 pmc_scratch29;
+/* 0x114 */	u32 pmc_scratch30;
+/* 0x118 */	u32 pmc_scratch31;
+/* 0x11c */	u32 pmc_scratch32;
+/* 0x120 */	u32 pmc_scratch33;
+/* 0x124 */	u32 pmc_scratch34;
+/* 0x128 */	u32 pmc_scratch35;
+/* 0x12c */	u32 pmc_scratch36;
+/* 0x130 */	u32 pmc_scratch37;
+/* 0x134 */	u32 pmc_scratch38;
+/* 0x138 */	u32 pmc_scratch39;
+/* 0x13c */	u32 pmc_scratch40;
+/* 0x140 */	u32 pmc_scratch41;
+/* 0x144 */	u32 pmc_scratch42;
+/* 0x148 */	u32 pmc_bondout_mirror0;
+/* 0x14c */	u32 pmc_bondout_mirror1;
+/* 0x150 */	u32 pmc_bondout_mirror2;
+/* 0x154 */	u32 pmc_sys_33v_en;
+/* 0x158 */	u32 pmc_bondout_mirror_access;
+/* 0x15c */	u32 pmc_gate;
+/* 0x160 */	u32 pmc_wake2_mask;
+/* 0x164 */	u32 pmc_wake2_lvl;
+/* 0x168 */	u32 pmc_wake2_status;
+/* 0x16c */	u32 pmc_sw_wake2_status;
+/* 0x170 */	u32 pmc_auto_wake2_lvl_mask;
+/* 0x174 */	u32 pmc_pg_mask_2;
+/* 0x178 */	u32 pmc_pg_mask_ce1;
+/* 0x17c */	u32 pmc_pg_mask_ce2;
+/* 0x180 */	u32 pmc_pg_mask_ce3;
+/* 0x184 */	u32 pmc_pwrgate_timer_ce_0;
+/* 0x188 */	u32 pmc_pwrgate_timer_ce_1;
+/* 0x18c */	u32 pmc_pwrgate_timer_ce_2;
+/* 0x190 */	u32 pmc_pwrgate_timer_ce_3;
+/* 0x194 */	u32 pmc_pwrgate_timer_ce_4;
+/* 0x198 */	u32 pmc_pwrgate_timer_ce_5;
+/* 0x19c */	u32 pmc_pwrgate_timer_ce_6;
+/* 0x1a0 */	u32 pmc_pcx_edpd_cntrl;
+/* 0x1a4 */	u32 pmc_osc_edpd_over;
+/* 0x1a8 */	u32 pmc_clk_out_cntrl;
+/* 0x1ac */	u32 pmc_sata_pwrgt;
+/* 0x1b0 */	u32 pmc_sensor_ctrl;
+/* 0x1b4 */	u32 pmc_rst_status;
+/* 0x1b8 */	u32 pmc_io_dpd_req;
+/* 0x1bc */	u32 pmc_io_dpd_status;
+/* 0x1c0 */	u32 pmc_io_dpd2_req;
+/* 0x1c4 */	u32 pmc_io_dpd2_status;
+/* 0x1c8 */	u32 pmc_sel_dpd_tim;
+/* 0x1cc */	u32 pmc_vddp_sel;
+/* 0x1d0 */	u32 pmc_ddr_cfg;
+/* 0x1d4 */	u32 pmc_e_no_vttgen;
+/* 0x1d8 */	u32 rsvd_1d8;
+/* 0x1dc */	u32 pmc_pllm_wb0_override_freq;
+/* 0x1e0 */	u32 pmc_test_pwrgate;
+/* 0x1e4 */	u32 pmc_pwrgate_timer_mult;
+/* 0x1e8 */	u32 pmc_dsi_sel_dpd;
+/* 0x1ec */	u32 pmc_utmip_uhsic_triggers;
+/* 0x1f0 */	u32 pmc_utmip_uhsic_saved_state;
+/* 0x1f4 */	u32 rsvd_1f4;
+/* 0x1f8 */	u32 pmc_utmip_term_pad_cfg;
+/* 0x1fc */	u32 pmc_utmip_uhsic_sleep_cfg;
+/* 0x200 */	u32 pmc_utmip_uhsic_sleepwalk_cfg;
+/* 0x204 */	u32 pmc_utmip_sleepwalk_p0;
+/* 0x208 */	u32 pmc_utmip_sleepwalk_p1;
+/* 0x20c */	u32 pmc_utmip_sleepwalk_p2;
+/* 0x210 */	u32 pmc_uhsic_sleepwalk_p0;
+/* 0x214 */	u32 pmc_utmip_uhsic_status;
+/* 0x218 */	u32 pmc_utmip_uhsic_fake;
+/* 0x21c */	u32 pmc_bondout_mirror3;
+/* 0x220 */	u32 pmc_bondout_mirror4;
+/* 0x224 */	u32 pmc_secure_scratch6;
+/* 0x228 */	u32 pmc_secure_scratch7;
+/* 0x22c */	u32 pmc_scratch43;
+/* 0x230 */	u32 pmc_scratch44;
+/* 0x234 */	u32 pmc_scratch45;
+/* 0x238 */	u32 pmc_scratch46;
+/* 0x23c */	u32 pmc_scratch47;
+/* 0x240 */	u32 pmc_scratch48;
+/* 0x244 */	u32 pmc_scratch49;
+/* 0x248 */	u32 pmc_scratch50;
+/* 0x24c */	u32 pmc_scratch51;
+/* 0x250 */	u32 pmc_scratch52;
+/* 0x254 */	u32 pmc_scratch53;
+/* 0x258 */	u32 pmc_scratch54;
+/* 0x25c */	u32 pmc_scratch55;
+/* 0x260 */	u32 pmc_scratch0_eco;
+/* 0x264 */	u32 pmc_por_dpd_ctrl;
+/* 0x268 */	u32 pmc_scratch2_eco;
+/* 0x26c */	u32 pmc_utmip_uhsic_line_wakeup;
+/* 0x270 */	u32 pmc_utmip_bias_master_cntrl;
+/* 0x274 */	u32 pmc_utmip_master_config;
+/* 0x278 */	u32 pmc_td_pwrgate_inter_part_timer;
+/* 0x27c */	u32 pmc_utmip_uhsic2_triggers;
+/* 0x280 */	u32 pmc_utmip_uhsic2_saved_state;
+/* 0x284 */	u32 pmc_utmip_uhsic2_sleep_cfg;
+/* 0x288 */	u32 pmc_utmip_uhsic2_sleepwalk_cfg;
+/* 0x28c */	u32 pmc_uhsic2_sleepwalk_p1;
+/* 0x290 */	u32 pmc_utmip_uhsic2_status;
+/* 0x294 */	u32 pmc_utmip_uhsic2_fake;
+/* 0x298 */	u32 pmc_utmip_uhsic2_line_wakeup;
+/* 0x29c */	u32 pmc_utmip_master2_config;
+/* 0x2a0 */	u32 pmc_utmip_uhsic_rpd_cfg;
+/* 0x2a4 */	u32 pmc_pg_mask_ce0;
+/* 0x2a8 */	u32 pmc_pg_mask_3;
+/* 0x2ac */	u32 pmc_pg_mask_4;
+/* 0x2b0 */	u32 pmc_pllm_wb0_override2;
+/* 0x2b4 */	u32 pmc_tsc_mult;
+/* 0x2b8 */	u32 pmc_cpu_vsense_override;
+/* 0x2bc */	u32 pmc_glb_amap_cfg;
+/* 0x2c0 */	u32 pmc_sticky_bits;
+/* 0x2c4 */	u32 pmc_sec_disable2;
+/* 0x2c8 */	u32 pmc_weak_bias;
+/* 0x2cc */	u32 pmc_reg_short;
+/* 0x2d0 */	u32 pmc_pg_mask_andor;
+/* 0x2d4 */	u32 pmc_gpu_rg_cntrl;
+/* 0x2d8 */	u32 pmc_sec_disable3;
+/* 0x2dc */	u32 pmc_pg_mask_5;
+/* 0x2e0 */	u32 pmc_pg_mask_6;
+/* 0x2e4 */	u32 rsvd_2e4[7];
+/* 0x300 */	u32 pmc_secure_scratch8;
+/* 0x304 */	u32 pmc_secure_scratch9;
+/* 0x308 */	u32 pmc_secure_scratch10;
+/* 0x30c */	u32 pmc_secure_scratch11;
+/* 0x310 */	u32 pmc_secure_scratch12;
+/* 0x314 */	u32 pmc_secure_scratch13;
+/* 0x318 */	u32 pmc_secure_scratch14;
+/* 0x31c */	u32 pmc_secure_scratch15;
+/* 0x320 */	u32 pmc_secure_scratch16;
+/* 0x324 */	u32 pmc_secure_scratch17;
+/* 0x328 */	u32 pmc_secure_scratch18;
+/* 0x32c */	u32 pmc_secure_scratch19;
+/* 0x330 */	u32 pmc_secure_scratch20;
+/* 0x334 */	u32 pmc_secure_scratch21;
+/* 0x338 */	u32 pmc_secure_scratch22; // AArch32 reset address.
+/* 0x33c */	u32 pmc_secure_scratch23;
+/* 0x340 */	u32 pmc_secure_scratch24;
+/* 0x344 */	u32 pmc_secure_scratch25;
+/* 0x348 */	u32 pmc_secure_scratch26;
+/* 0x34c */	u32 pmc_secure_scratch27;
+/* 0x350 */	u32 pmc_secure_scratch28;
+/* 0x354 */	u32 pmc_secure_scratch29;
+/* 0x358 */	u32 pmc_secure_scratch30;
+/* 0x35c */	u32 pmc_secure_scratch31;
+/* 0x360 */	u32 pmc_secure_scratch32;
+/* 0x364 */	u32 pmc_secure_scratch33;
+/* 0x368 */	u32 pmc_secure_scratch34; // AArch64 reset address.
+/* 0x36c */	u32 pmc_secure_scratch35; // AArch64 reset hi-address.
+/* 0x370 */	u32 pmc_secure_scratch36;
+/* 0x374 */	u32 pmc_secure_scratch37;
+/* 0x378 */	u32 pmc_secure_scratch38;
+/* 0x37c */	u32 pmc_secure_scratch39;
+/* 0x380 */	u32 pmc_secure_scratch40;
+/* 0x384 */	u32 pmc_secure_scratch41;
+/* 0x388 */	u32 pmc_secure_scratch42;
+/* 0x38c */	u32 pmc_secure_scratch43;
+/* 0x390 */	u32 pmc_secure_scratch44;
+/* 0x394 */	u32 pmc_secure_scratch45;
+/* 0x398 */	u32 pmc_secure_scratch46;
+/* 0x39c */	u32 pmc_secure_scratch47;
+/* 0x3a0 */	u32 pmc_secure_scratch48;
+/* 0x3a4 */	u32 pmc_secure_scratch49;
+/* 0x3a8 */	u32 pmc_secure_scratch50;
+/* 0x3ac */	u32 pmc_secure_scratch51;
+/* 0x3b0 */	u32 pmc_secure_scratch52;
+/* 0x3b4 */	u32 pmc_secure_scratch53;
+/* 0x3b8 */	u32 pmc_secure_scratch54;
+/* 0x3bc */	u32 pmc_secure_scratch55;
+/* 0x3c0 */	u32 pmc_secure_scratch56;
+/* 0x3c4 */	u32 pmc_secure_scratch57;
+/* 0x3c8 */	u32 pmc_secure_scratch58;
+/* 0x3cc */	u32 pmc_secure_scratch59;
+/* 0x3d0 */	u32 pmc_secure_scratch60;
+/* 0x3d4 */	u32 pmc_secure_scratch61;
+/* 0x3d8 */	u32 pmc_secure_scratch62;
+/* 0x3dc */	u32 pmc_secure_scratch63;
+/* 0x3e0 */	u32 pmc_secure_scratch64;
+/* 0x3e4 */	u32 pmc_secure_scratch65;
+/* 0x3e8 */	u32 pmc_secure_scratch66;
+/* 0x3ec */	u32 pmc_secure_scratch67;
+/* 0x3f0 */	u32 pmc_secure_scratch68;
+/* 0x3f4 */	u32 pmc_secure_scratch69;
+/* 0x3f8 */	u32 pmc_secure_scratch70;
+/* 0x3fc */	u32 pmc_secure_scratch71;
+/* 0x400 */	u32 pmc_secure_scratch72;
+/* 0x404 */	u32 pmc_secure_scratch73;
+/* 0x408 */	u32 pmc_secure_scratch74;
+/* 0x40c */	u32 pmc_secure_scratch75;
+/* 0x410 */	u32 pmc_secure_scratch76;
+/* 0x414 */	u32 pmc_secure_scratch77;
+/* 0x418 */	u32 pmc_secure_scratch78;
+/* 0x41c */	u32 pmc_secure_scratch79;
+/* 0x420 */	u32 rsvd_420[8];
+/* 0x440 */	u32 pmc_cntrl2;
+/* 0x444 */	u32 pmc_io_dpd_off_mask;
+/* 0x448 */	u32 pmc_io_dpd2_off_mask;
+/* 0x44c */	u32 pmc_event_counter;
+/* 0x450 */	u32 pmc_fuse_control;
+/* 0x454 */	u32 pmc_scratch1_eco;
+/* 0x458 */	u32 rsvd_458;
+/* 0x45c */	u32 pmc_io_dpd3_req;
+/* 0x460 */	u32 pmc_io_dpd3_status;
+/* 0x464 */	u32 pmc_io_dpd4_req;
+/* 0x468 */	u32 pmc_io_dpd4_status;
+/* 0x46c */	u32 rsvd_46c[2];
+/* 0x474 */	u32 pmc_direct_thermtrip_cfg;
+/* 0x478 */	u32 pmc_tsosc_delay;
+/* 0x47c */	u32 pmc_set_sw_clamp;
+/* 0x480 */	u32 pmc_debug_authentication;
+/* 0x484 */	u32 pmc_aotag_cfg;
+/* 0x488 */	u32 pmc_aotag_thresh1_cfg;
+/* 0x48c */	u32 pmc_aotag_thresh2_cfg;
+/* 0x490 */	u32 pmc_aotag_thresh3_cfg;
+/* 0x494 */	u32 pmc_aotag_status;
+/* 0x498 */	u32 pmc_aotag_security;
+/* 0x49c */	u32 pmc_tsensor_config0;
+/* 0x4a0 */	u32 pmc_tsensor_config1;
+/* 0x4a4 */	u32 pmc_tsensor_config2;
+/* 0x4a8 */	u32 pmc_tsensor_status0;
+/* 0x4ac */	u32 pmc_tsensor_status1;
+/* 0x4b0 */	u32 pmc_tsensor_status2;
+/* 0x4b4 */	u32 pmc_tsensor_pdiv;
+/* 0x4b8 */	u32 pmc_aotag_intr_en;
+/* 0x4bc */	u32 pmc_aotag_intr_dis;
+/* 0x4c0 */	u32 pmc_utmip_pad_cfg0;
+/* 0x4c4 */	u32 pmc_utmip_pad_cfg1;
+/* 0x4c8 */	u32 pmc_utmip_pad_cfg2;
+/* 0x4cc */	u32 pmc_utmip_pad_cfg3;
+/* 0x4d0 */	u32 pmc_utmip_uhsic_sleep_cfg1;
+/* 0x4d4 */	u32 pmc_cc4_hvc_control;
+/* 0x4d8 */	u32 pmc_wake_debounce_en;
+/* 0x4dc */	u32 pmc_ramdump_ctl_status;
+/* 0x4e0 */	u32 pmc_utmip_sleepwalk_p3;
+/* 0x4e4 */	u32 pmc_ddr_cntrl;
+/* 0x4e8 */	u32 rsvd_4e8[50];
+/* 0x5b0 */	u32 pmc_sec_disable4;
+/* 0x5b4 */	u32 pmc_sec_disable5;
+/* 0x5b8 */	u32 pmc_sec_disable6;
+/* 0x5bc */	u32 pmc_sec_disable7;
+/* 0x5c0 */	u32 pmc_sec_disable8;
+/* 0x5c4 */	u32 pmc_sec_disable9_b01;
+/* 0x5c8 */	u32 pmc_sec_disable10_b01;
+/* 0x5cc */	u32 rsvd_5cc[13];
+/* 0x600 */	u32 pmc_scratch56;
+/* 0x604 */	u32 pmc_scratch57;
+/* 0x608 */	u32 pmc_scratch58;
+/* 0x60c */	u32 pmc_scratch59;
+/* 0x610 */	u32 pmc_scratch60;
+/* 0x614 */	u32 pmc_scratch61;
+/* 0x618 */	u32 pmc_scratch62;
+/* 0x61c */	u32 pmc_scratch63;
+/* 0x620 */	u32 pmc_scratch64;
+/* 0x624 */	u32 pmc_scratch65;
+/* 0x628 */	u32 pmc_scratch66;
+/* 0x62c */	u32 pmc_scratch67;
+/* 0x630 */	u32 pmc_scratch68;
+/* 0x634 */	u32 pmc_scratch69;
+/* 0x638 */	u32 pmc_scratch70;
+/* 0x63c */	u32 pmc_scratch71;
+/* 0x640 */	u32 pmc_scratch72;
+/* 0x644 */	u32 pmc_scratch73;
+/* 0x648 */	u32 pmc_scratch74;
+/* 0x64c */	u32 pmc_scratch75;
+/* 0x650 */	u32 pmc_scratch76;
+/* 0x654 */	u32 pmc_scratch77;
+/* 0x658 */	u32 pmc_scratch78;
+/* 0x65c */	u32 pmc_scratch79;
+/* 0x660 */	u32 pmc_scratch80;
+/* 0x664 */	u32 pmc_scratch81;
+/* 0x668 */	u32 pmc_scratch82;
+/* 0x66c */	u32 pmc_scratch83;
+/* 0x670 */	u32 pmc_scratch84;
+/* 0x674 */	u32 pmc_scratch85;
+/* 0x678 */	u32 pmc_scratch86;
+/* 0x67c */	u32 pmc_scratch87;
+/* 0x680 */	u32 pmc_scratch88;
+/* 0x684 */	u32 pmc_scratch89;
+/* 0x688 */	u32 pmc_scratch90;
+/* 0x68c */	u32 pmc_scratch91;
+/* 0x690 */	u32 pmc_scratch92;
+/* 0x694 */	u32 pmc_scratch93;
+/* 0x698 */	u32 pmc_scratch94;
+/* 0x69c */	u32 pmc_scratch95;
+/* 0x6a0 */	u32 pmc_scratch96;
+/* 0x6a4 */	u32 pmc_scratch97;
+/* 0x6a8 */	u32 pmc_scratch98;
+/* 0x6ac */	u32 pmc_scratch99;
+/* 0x6b0 */	u32 pmc_scratch100;
+/* 0x6b4 */	u32 pmc_scratch101;
+/* 0x6b8 */	u32 pmc_scratch102;
+/* 0x6bc */	u32 pmc_scratch103;
+/* 0x6c0 */	u32 pmc_scratch104;
+/* 0x6c4 */	u32 pmc_scratch105;
+/* 0x6c8 */	u32 pmc_scratch106;
+/* 0x6cc */	u32 pmc_scratch107;
+/* 0x6d0 */	u32 pmc_scratch108;
+/* 0x6d4 */	u32 pmc_scratch109;
+/* 0x6d8 */	u32 pmc_scratch110;
+/* 0x6dc */	u32 pmc_scratch111;
+/* 0x6e0 */	u32 pmc_scratch112;
+/* 0x6e4 */	u32 pmc_scratch113;
+/* 0x6e8 */	u32 pmc_scratch114;
+/* 0x6ec */	u32 pmc_scratch115;
+/* 0x6f0 */	u32 pmc_scratch116;
+/* 0x6f4 */	u32 pmc_scratch117;
+/* 0x6f8 */	u32 pmc_scratch118;
+/* 0x6fc */	u32 pmc_scratch119;
+/* 0x700 */	u32 pmc_scratch120;
+/* 0x704 */	u32 pmc_scratch121;
+/* 0x708 */	u32 pmc_scratch122;
+/* 0x70c */	u32 pmc_scratch123;
+/* 0x710 */	u32 pmc_scratch124;
+/* 0x714 */	u32 pmc_scratch125;
+/* 0x718 */	u32 pmc_scratch126;
+/* 0x71c */	u32 pmc_scratch127;
+/* 0x720 */	u32 pmc_scratch128;
+/* 0x724 */	u32 pmc_scratch129;
+/* 0x728 */	u32 pmc_scratch130;
+/* 0x72c */	u32 pmc_scratch131;
+/* 0x730 */	u32 pmc_scratch132;
+/* 0x734 */	u32 pmc_scratch133;
+/* 0x738 */	u32 pmc_scratch134;
+/* 0x73c */	u32 pmc_scratch135;
+/* 0x740 */	u32 pmc_scratch136;
+/* 0x744 */	u32 pmc_scratch137;
+/* 0x748 */	u32 pmc_scratch138;
+/* 0x74c */	u32 pmc_scratch139;
+/* 0x750 */	u32 pmc_scratch140;
+/* 0x754 */	u32 pmc_scratch141;
+/* 0x758 */	u32 pmc_scratch142;
+/* 0x75c */	u32 pmc_scratch143;
+/* 0x760 */	u32 pmc_scratch144;
+/* 0x764 */	u32 pmc_scratch145;
+/* 0x768 */	u32 pmc_scratch146;
+/* 0x76c */	u32 pmc_scratch147;
+/* 0x770 */	u32 pmc_scratch148;
+/* 0x774 */	u32 pmc_scratch149;
+/* 0x778 */	u32 pmc_scratch150;
+/* 0x77c */	u32 pmc_scratch151;
+/* 0x780 */	u32 pmc_scratch152;
+/* 0x784 */	u32 pmc_scratch153;
+/* 0x788 */	u32 pmc_scratch154;
+/* 0x78c */	u32 pmc_scratch155;
+/* 0x790 */	u32 pmc_scratch156;
+/* 0x794 */	u32 pmc_scratch157;
+/* 0x798 */	u32 pmc_scratch158;
+/* 0x79c */	u32 pmc_scratch159;
+/* 0x7a0 */	u32 pmc_scratch160;
+/* 0x7a4 */	u32 pmc_scratch161;
+/* 0x7a8 */	u32 pmc_scratch162;
+/* 0x7ac */	u32 pmc_scratch163;
+/* 0x7b0 */	u32 pmc_scratch164;
+/* 0x7b4 */	u32 pmc_scratch165;
+/* 0x7b8 */	u32 pmc_scratch166;
+/* 0x7bc */	u32 pmc_scratch167;
+/* 0x7c0 */	u32 pmc_scratch168;
+/* 0x7c4 */	u32 pmc_scratch169;
+/* 0x7c8 */	u32 pmc_scratch170;
+/* 0x7cc */	u32 pmc_scratch171;
+/* 0x7d0 */	u32 pmc_scratch172;
+/* 0x7d4 */	u32 pmc_scratch173;
+/* 0x7d8 */	u32 pmc_scratch174;
+/* 0x7dc */	u32 pmc_scratch175;
+/* 0x7e0 */	u32 pmc_scratch176;
+/* 0x7e4 */	u32 pmc_scratch177;
+/* 0x7e8 */	u32 pmc_scratch178;
+/* 0x7ec */	u32 pmc_scratch179;
+/* 0x7f0 */	u32 pmc_scratch180;
+/* 0x7f4 */	u32 pmc_scratch181;
+/* 0x7f8 */	u32 pmc_scratch182;
+/* 0x7fc */	u32 pmc_scratch183;
+/* 0x800 */	u32 pmc_scratch184;
+/* 0x804 */	u32 pmc_scratch185;
+/* 0x808 */	u32 pmc_scratch186;
+/* 0x80c */	u32 pmc_scratch187;
+/* 0x810 */	u32 pmc_scratch188;
+/* 0x814 */	u32 pmc_scratch189;
+/* 0x818 */	u32 pmc_scratch190;
+/* 0x81c */	u32 pmc_scratch191;
+/* 0x820 */	u32 pmc_scratch192;
+/* 0x824 */	u32 pmc_scratch193;
+/* 0x828 */	u32 pmc_scratch194;
+/* 0x82c */	u32 pmc_scratch195;
+/* 0x830 */	u32 pmc_scratch196;
+/* 0x834 */	u32 pmc_scratch197;
+/* 0x838 */	u32 pmc_scratch198;
+/* 0x83c */	u32 pmc_scratch199;
+/* 0x840 */	u32 pmc_scratch200;
+/* 0x844 */	u32 pmc_scratch201;
+/* 0x848 */	u32 pmc_scratch202;
+/* 0x84c */	u32 pmc_scratch203;
+/* 0x850 */	u32 pmc_scratch204;
+/* 0x854 */	u32 pmc_scratch205;
+/* 0x858 */	u32 pmc_scratch206;
+/* 0x85c */	u32 pmc_scratch207;
+/* 0x860 */	u32 pmc_scratch208;
+/* 0x864 */	u32 pmc_scratch209;
+/* 0x868 */	u32 pmc_scratch210;
+/* 0x86c */	u32 pmc_scratch211;
+/* 0x870 */	u32 pmc_scratch212;
+/* 0x874 */	u32 pmc_scratch213;
+/* 0x878 */	u32 pmc_scratch214;
+/* 0x87c */	u32 pmc_scratch215;
+/* 0x880 */	u32 pmc_scratch216;
+/* 0x884 */	u32 pmc_scratch217;
+/* 0x888 */	u32 pmc_scratch218;
+/* 0x88c */	u32 pmc_scratch219;
+/* 0x890 */	u32 pmc_scratch220;
+/* 0x894 */	u32 pmc_scratch221;
+/* 0x898 */	u32 pmc_scratch222;
+/* 0x89c */	u32 pmc_scratch223;
+/* 0x8a0 */	u32 pmc_scratch224;
+/* 0x8a4 */	u32 pmc_scratch225;
+/* 0x8a8 */	u32 pmc_scratch226;
+/* 0x8ac */	u32 pmc_scratch227;
+/* 0x8b0 */	u32 pmc_scratch228;
+/* 0x8b4 */	u32 pmc_scratch229;
+/* 0x8b8 */	u32 pmc_scratch230;
+/* 0x8bc */	u32 pmc_scratch231;
+/* 0x8c0 */	u32 pmc_scratch232;
+/* 0x8c4 */	u32 pmc_scratch233;
+/* 0x8c8 */	u32 pmc_scratch234;
+/* 0x8cc */	u32 pmc_scratch235;
+/* 0x8d0 */	u32 pmc_scratch236;
+/* 0x8d4 */	u32 pmc_scratch237;
+/* 0x8d8 */	u32 pmc_scratch238;
+/* 0x8dc */	u32 pmc_scratch239;
+/* 0x8e0 */	u32 pmc_scratch240;
+/* 0x8e4 */	u32 pmc_scratch241;
+/* 0x8e8 */	u32 pmc_scratch242;
+/* 0x8ec */	u32 pmc_scratch243;
+/* 0x8f0 */	u32 pmc_scratch244;
+/* 0x8f4 */	u32 pmc_scratch245;
+/* 0x8f8 */	u32 pmc_scratch246;
+/* 0x8fc */	u32 pmc_scratch247;
+/* 0x900 */	u32 pmc_scratch248;
+/* 0x904 */	u32 pmc_scratch249;
+/* 0x908 */	u32 pmc_scratch250;
+/* 0x90c */	u32 pmc_scratch251;
+/* 0x910 */	u32 pmc_scratch252;
+/* 0x914 */	u32 pmc_scratch253;
+/* 0x918 */	u32 pmc_scratch254;
+/* 0x91c */	u32 pmc_scratch255;
+/* 0x920 */	u32 pmc_scratch256;
+/* 0x924 */	u32 pmc_scratch257;
+/* 0x928 */	u32 pmc_scratch258;
+/* 0x92c */	u32 pmc_scratch259;
+/* 0x930 */	u32 pmc_scratch260;
+/* 0x934 */	u32 pmc_scratch261;
+/* 0x938 */	u32 pmc_scratch262;
+/* 0x93c */	u32 pmc_scratch263;
+/* 0x940 */	u32 pmc_scratch264;
+/* 0x944 */	u32 pmc_scratch265;
+/* 0x948 */	u32 pmc_scratch266;
+/* 0x94c */	u32 pmc_scratch267;
+/* 0x950 */	u32 pmc_scratch268;
+/* 0x954 */	u32 pmc_scratch269;
+/* 0x958 */	u32 pmc_scratch270;
+/* 0x95c */	u32 pmc_scratch271;
+/* 0x960 */	u32 pmc_scratch272;
+/* 0x964 */	u32 pmc_scratch273;
+/* 0x968 */	u32 pmc_scratch274;
+/* 0x96c */	u32 pmc_scratch275;
+/* 0x970 */	u32 pmc_scratch276;
+/* 0x974 */	u32 pmc_scratch277;
+/* 0x978 */	u32 pmc_scratch278;
+/* 0x97c */	u32 pmc_scratch279;
+/* 0x980 */	u32 pmc_scratch280;
+/* 0x984 */	u32 pmc_scratch281;
+/* 0x988 */	u32 pmc_scratch282;
+/* 0x98c */	u32 pmc_scratch283;
+/* 0x990 */	u32 pmc_scratch284;
+/* 0x994 */	u32 pmc_scratch285;
+/* 0x998 */	u32 pmc_scratch286;
+/* 0x99c */	u32 pmc_scratch287;
+/* 0x9a0 */	u32 pmc_scratch288;
+/* 0x9a4 */	u32 pmc_scratch289;
+/* 0x9a8 */	u32 pmc_scratch290;
+/* 0x9ac */	u32 pmc_scratch291;
+/* 0x9b0 */	u32 pmc_scratch292;
+/* 0x9b4 */	u32 pmc_scratch293;
+/* 0x9b8 */	u32 pmc_scratch294;
+/* 0x9bc */	u32 pmc_scratch295;
+/* 0x9c0 */	u32 pmc_scratch296;
+/* 0x9c4 */	u32 pmc_scratch297;
+/* 0x9c8 */	u32 pmc_scratch298;
+/* 0x9cc */	u32 pmc_scratch299;
+/* 0x9d0 */	u32 rsvd_9d0[30];
+/* 0xa48 */	u32 pmc_scratch_write_disable0_b01;
+/* 0xa4c */	u32 pmc_scratch_write_disable1_b01;
+/* 0xa50 */	u32 pmc_scratch_write_disable2_b01;
+/* 0xa54 */	u32 pmc_scratch_write_disable3_b01;
+/* 0xa58 */	u32 pmc_scratch_write_disable4_b01;
+/* 0xa5c */	u32 pmc_scratch_write_disable5_b01;
+/* 0xa60 */	u32 pmc_scratch_write_disable6_b01;
+/* 0xa64 */	u32 pmc_scratch_write_disable7_b01;
+/* 0xa68 */	u32 pmc_scratch_write_disable8_b01;
+/* 0xa6c */	u32 pmc_scratch_write_disable9_b01;
+/* 0xa70 */	u32 pmc_scratch_write_disable10_b01;
+/* 0xa74 */	u32 pmc_scratch_write_lock_disable_sticky_b01;
+/* 0xa78 */	u32 rsvd_a78[8];
+/* 0xa98 */	u32 pmc_secure_scratch80;
+/* 0xa9c */	u32 pmc_secure_scratch81;
+/* 0xaa0 */	u32 pmc_secure_scratch82;
+/* 0xaa4 */	u32 pmc_secure_scratch83;
+/* 0xaa8 */	u32 pmc_secure_scratch84;
+/* 0xaac */	u32 pmc_secure_scratch85;
+/* 0xab0 */	u32 pmc_secure_scratch86;
+/* 0xab4 */	u32 pmc_secure_scratch87;
+/* 0xab8 */	u32 pmc_secure_scratch88;
+/* 0xabc */	u32 pmc_secure_scratch89;
+/* 0xac0 */	u32 pmc_secure_scratch90;
+/* 0xac4 */	u32 pmc_secure_scratch91;
+/* 0xac8 */	u32 pmc_secure_scratch92;
+/* 0xacc */	u32 pmc_secure_scratch93;
+/* 0xad0 */	u32 pmc_secure_scratch94;
+/* 0xad4 */	u32 pmc_secure_scratch95;
+/* 0xad8 */	u32 pmc_secure_scratch96;
+/* 0xadc */	u32 pmc_secure_scratch97;
+/* 0xae0 */	u32 pmc_secure_scratch98;
+/* 0xae4 */	u32 pmc_secure_scratch99;
+/* 0xae8 */	u32 pmc_secure_scratch100;
+/* 0xaec */	u32 pmc_secure_scratch101;
+/* 0xaf0 */	u32 pmc_secure_scratch102;
+/* 0xaf4 */	u32 pmc_secure_scratch103;
+/* 0xaf8 */	u32 pmc_secure_scratch104;
+/* 0xafc */	u32 pmc_secure_scratch105;
+/* 0xb00 */	u32 pmc_secure_scratch106;
+/* 0xb04 */	u32 pmc_secure_scratch107;
+/* 0xb08 */	u32 pmc_secure_scratch108;
+/* 0xb0c */	u32 pmc_secure_scratch109;
+/* 0xb10 */	u32 pmc_secure_scratch110;
+/* 0xb14 */	u32 pmc_secure_scratch111;
+/* 0xb18 */	u32 pmc_secure_scratch112;
+/* 0xb1c */	u32 pmc_secure_scratch113;
+/* 0xb20 */	u32 pmc_secure_scratch114;
+/* 0xb24 */	u32 pmc_secure_scratch115;
+/* 0xb28 */	u32 pmc_secure_scratch116;
+/* 0xb2c */	u32 pmc_secure_scratch117;
+/* 0xb30 */	u32 pmc_secure_scratch118;
+/* 0xb34 */	u32 pmc_secure_scratch119;
+/* 0xb38 */	u32 pmc_secure_scratch120_b01;
+/* 0xb3c */	u32 pmc_secure_scratch121_b01;
+/* 0xb40 */	u32 pmc_secure_scratch122_b01;
+/* 0xb44 */	u32 pmc_secure_scratch123_b01;
+/* 0xb48 */	u32 pmc_led_breathing_ctrl_b01;
+/* 0xb4c */	u32 pmc_led_breathing_counter0_b01; // Slope Steps.
+/* 0xb50 */	u32 pmc_led_breathing_counter1_b01; // ON counter.
+/* 0xb54 */	u32 pmc_led_breathing_counter2_b01; // OFF counter1.
+/* 0xb58 */	u32 pmc_led_breathing_counter3_b01; // OFF counter0.
+/* 0xb5c */	u32 pmc_led_breathing_status_b01;
+/* 0xb60 */	u32 rsvd_b60[2];
+/* 0xb68 */	u32 pmc_secure_scratch124_b01;
+/* 0xb6c */	u32 pmc_secure_scratch125_b01;
+/* 0xb70 */	u32 pmc_secure_scratch126_b01;
+/* 0xb74 */	u32 pmc_secure_scratch127_b01;
+/* 0xb78 */	u32 pmc_secure_scratch128_b01;
+/* 0xb7c */	u32 pmc_secure_scratch129_b01;
+/* 0xb80 */	u32 pmc_secure_scratch130_b01;
+/* 0xb84 */	u32 pmc_secure_scratch131_b01;
+/* 0xb88 */	u32 pmc_secure_scratch132_b01;
+/* 0xb8c */	u32 pmc_secure_scratch133_b01;
+/* 0xb90 */	u32 pmc_secure_scratch134_b01;
+/* 0xb94 */	u32 pmc_secure_scratch135_b01;
+/* 0xb98 */	u32 pmc_secure_scratch136_b01;
+/* 0xb9c */	u32 pmc_secure_scratch137_b01;
+/* 0xba0 */	u32 pmc_secure_scratch138_b01;
+/* 0xba4 */	u32 pmc_secure_scratch139_b01;
+/* 0xba8 */	u32 rsvd_ba8[2];
+/* 0xbb0 */	u32 pmc_sec_disable_ns_b01;
+/* 0xbb4 */	u32 pmc_sec_disable2_ns_b01;
+/* 0xbb8 */	u32 pmc_sec_disable3_ns_b01;
+/* 0xbbc */	u32 pmc_sec_disable4_ns_b01;
+/* 0xbc0 */	u32 pmc_sec_disable5_ns_b01;
+/* 0xbc4 */	u32 pmc_sec_disable6_ns_b01;
+/* 0xbc8 */	u32 pmc_sec_disable7_ns_b01;
+/* 0xbcc */	u32 pmc_sec_disable8_ns_b01;
+/* 0xbd0 */	u32 pmc_sec_disable9_ns_b01;
+/* 0xbd4 */	u32 pmc_sec_disable10_ns_b01;
+/* 0xbd8 */	u32 rsvd_bd8[4];
+/* 0xbe8 */	u32 pmc_tzram_pwr_cntrl_b01;
+/* 0xbec */	u32 pmc_tzram_sec_disable_b01;
+/* 0xbf0 */	u32 pmc_tzram_non_sec_disable_b01;
+} pmc_regs_t210_t;
+
+#endif	/* _PMC_T210_H_ */

modules/hekate_libsys_lp0/sdram_lp0_param_t210.h

@@ -57,7 +57,7 @@ enum
 /**
  * Defines the SDRAM parameter structure
  */
-struct sdram_params_t210
+typedef struct _sdram_params_t210_t
 {
 
 	/* Specifies the type of memory device */
@@ -959,6 +959,6 @@ struct sdram_params_t210
 	u32 McMtsCarveoutRegCtrl;
 
 	/* End */
-};
+} sdram_params_t210_t;
 
 #endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */

modules/hekate_libsys_lp0/sdram_lp0_param_t210b01.h

@@ -16,7 +16,7 @@
 
 #include "types.h"
 
-struct sdram_params_t210b01
+typedef struct _sdram_params_t210b01_t
 {
 	/* Specifies the type of memory device */
 	u32 memory_type;
@@ -986,6 +986,6 @@ struct sdram_params_t210b01
 
 	/* Just a place holder for special usage when there is no BCT for certain registers */
 	u32 bct_na;
-};
+} sdram_params_t210b01_t;
 
 #endif

modules/hekate_libsys_minerva/Makefile

@@ -20,7 +20,7 @@ OBJS = $(addprefix $(BUILDDIR)/,\
 
 ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork
 CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall -Wsign-compare $(CUSTOMDEFINES)
-LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc
+LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc -Wl,-z,max-page-size=256
 
 .PHONY: all
 

modules/hekate_libsys_minerva/sys_sdrammtc.c

@@ -25,7 +25,7 @@
 #include "types.h"
 #include <module.h>
 
-#define DVFS_T21X_CC_VERSION "Minerva Training Cell v0.1_T21X"
+#define DVFS_T21X_CC_VERSION "Minerva Training Cell v0.2_T21X"
 #define DVFS_T210_CC_VERSION "Minerva Training Cell v1.6_T210"
 
 #define EPRINTF(...)
@@ -3758,7 +3758,7 @@ static int _minerva_set_ir_boost(mtc_config_t *mtc_cfg)
 		MC(MC_EMEM_ARB_TIMING_FAW)   = 4;
 		MC(MC_EMEM_ARB_TIMING_RFCPB) = 0xE;
 		MC(MC_EMEM_ARB_DA_COVERS)    = 0x30203;
-		MC(MC_EMEM_ARB_MISC0)        = 0x73C30507;
+		MC(MC_EMEM_ARB_MISC0)        = 0x71E30507;
 
 		// Program base timings.
 		EMC(EMC_RP)      = 8;
@@ -4012,7 +4012,7 @@ error:
 	return;
 }
 
-void minerva_entry(mtc_config_t *mtc_cfg, bdkParams_t bp)
+void minerva_entry(mtc_config_t *mtc_cfg, bdk_params_t *bp)
 {
 	EPRINTF("-- Minerva Training Cell --");
 

modules/simple_sample/Makefile

@@ -27,7 +27,7 @@ CUSTOMDEFINES := -DGFX_INC=$(GFX_INC)
 
 ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork
 CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall -Wsign-compare $(CUSTOMDEFINES)
-LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc
+LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc -Wl,-z,max-page-size=256
 
 .PHONY: clean all
 

modules/simple_sample/module_sample.c

@@ -6,13 +6,13 @@
 #include <module.h>
 #include <gfx_utils.h>
 
-void mod_entry(void *moduleConfig, bdkParams_t bp)
+void mod_entry(void *moduleConfig, bdk_params_t *bp)
 {
-	memcpy(&gfx_con, bp->gfxCon, sizeof(gfx_con_t));
-	memcpy(&gfx_ctxt, bp->gfxCtx, sizeof(gfx_ctxt_t));
+	memcpy(&gfx_con, bp->gfx_con, sizeof(gfx_con_t));
+	memcpy(&gfx_ctxt, bp->gfx_ctx, sizeof(gfx_ctxt_t));
 
 	gfx_puts("Hello World!");
 
-	memcpy(bp->gfxCon, &gfx_con, sizeof(gfx_con_t));
-	memcpy(bp->gfxCtx, &gfx_ctxt, sizeof(gfx_ctxt_t));
+	memcpy(bp->gfx_con, &gfx_con, sizeof(gfx_con_t));
+	memcpy(bp->gfx_ctx, &gfx_ctxt, sizeof(gfx_ctxt_t));
 }

nyx/Makefile

@@ -73,7 +73,7 @@ CUSTOMDEFINES := -DNYX_LOAD_ADDR=$(NYX_LOAD_ADDR) -DNYX_MAGIC=$(NYX_MAGIC)
 CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_VER_RL=$(NYXVERSION_REL)
 
 # BDK defines.
-CUSTOMDEFINES += -DBDK_MC_ENABLE_AHB_REDIRECT -DBDK_MINERVA_CFG_FROM_RAM -DBDK_HW_EXTRA_DEINIT -DBDK_SDMMC_EXTRA_PRINT
+CUSTOMDEFINES += -DBDK_MINERVA_CFG_FROM_RAM -DBDK_HW_EXTRA_DEINIT -DBDK_SDMMC_EXTRA_PRINT
 CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC)
 
 #CUSTOMDEFINES += -DDEBUG

nyx/nyx_gui/config.c

@@ -65,12 +65,12 @@ int create_config_entry()
 {
 	char lbuf[64];
 	FIL fp;
-	bool mainIniFound = false;
+	bool ini_found = false;
 
 	LIST_INIT(ini_sections);
 
-	if (ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false))
-		mainIniFound = true;
+	if (!ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false))
+		ini_found = true;
 	else
 	{
 		u8 res = f_open(&fp, "bootloader/hekate_ipl.ini", FA_READ);
@@ -137,7 +137,7 @@ int create_config_entry()
 
 	f_puts("\n", &fp);
 
-	if (mainIniFound)
+	if (ini_found)
 	{
 		// Re-construct existing entries.
 		LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link)
@@ -188,7 +188,7 @@ int create_nyx_config_entry(bool force_unmount)
 {
 	bool sd_mounted = sd_get_card_mounted();
 
-	if (!sd_mount())
+	if (sd_mount())
 		return 1;
 
 	char lbuf[64];

nyx/nyx_gui/config.h

@@ -45,7 +45,7 @@ typedef struct _hekate_config
 
 typedef struct _nyx_config
 {
-	u32 theme_bg;
+	u32 theme_bg; // COLOR_BG_BASE_MIN - COLOR_BG_BASE_MAX.
 	u32 theme_color;
 	u32 entries_5_col;
 	u32 timeoffset;

nyx/nyx_gui/frontend/fe_emmc_tools.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 Rajko Stojadinovic
- * Copyright (c) 2018-2025 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -122,7 +122,7 @@ static lv_obj_t *create_mbox_text(const char *text, bool button_ok)
 
 	lv_mbox_set_text(mbox, text);
 	if (button_ok)
-		lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action);
+		lv_mbox_add_btns(mbox, mbox_btn_map, nyx_mbox_action);
 
 	lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0);
 	lv_obj_set_top(mbox, true);
@@ -211,7 +211,7 @@ static int _emmc_sd_copy_verify(emmc_tool_gui_t *gui, sdmmc_storage_t *storage,
 			// Full provides all that, plus protection from extremely rare I/O corruption.
 			if ((n_cfg.verification >= 2) || !(sparseShouldVerify % 4))
 			{
-				if (!sdmmc_storage_read(storage, lba_curr, num, bufEm))
+				if (sdmmc_storage_read(storage, lba_curr, num, bufEm))
 				{
 					s_printf(gui->txt_buf,
 						"\n#FF0000 Failed to read %d blocks (@LBA %08X),#\n"
@@ -380,7 +380,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
-			return 0;
+			return 1;
 		}
 		sd_sector_off = sector_start + (0x2000 * active_part);
 		if (active_part == 2)
@@ -424,7 +424,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
-			return 0;
+			return 1;
 		}
 	}
 	// Check if we are continuing a previous raw eMMC or USER partition backup in progress.
@@ -447,7 +447,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
-			return 0;
+			return 1;
 		}
 
 		// Increase maxSplitParts to accommodate previously backed up parts.
@@ -485,7 +485,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 		if (!(btn_wait() & BTN_POWER))
 		{
 			lv_obj_del(warn_mbox_bg);
-			return 0;
+			return 1;
 		}
 		lv_obj_del(warn_mbox_bg);
 	}
@@ -502,7 +502,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 		lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 		manual_system_maintenance(true);
 
-		return 0;
+		return 1;
 	}
 
 	u8 *buf = (u8 *)MIXD_BUF_ALIGNED;
@@ -553,7 +553,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 					strcpy(gui->txt_buf, "\n#FFDD00 Please try again...#\n");
 					lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 					manual_system_maintenance(true);
-					return 0;
+					return 1;
 				case VERIF_STATUS_ABORT:
 					verification = 0;
 					break;
@@ -580,7 +580,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 					lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 					manual_system_maintenance(true);
 
-					return 0;
+					return 1;
 				}
 
 				// More parts to backup that do not currently fit the sd card free space or fatal error.
@@ -596,7 +596,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 
 					partial_sd_full_unmount = true;
 
-					return 1;
+					return 0;
 				}
 			}
 
@@ -615,7 +615,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 
-				return 0;
+				return 1;
 			}
 
 			bytesWritten = 0;
@@ -629,9 +629,9 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 
 		int res_read;
 		if (!gui->raw_emummc)
-			res_read = !sdmmc_storage_read(storage, lba_curr, num, buf);
+			res_read = sdmmc_storage_read(storage, lba_curr, num, buf);
 		else
-			res_read = !sdmmc_storage_read(&sd_storage, lba_curr + sd_sector_off, num, buf);
+			res_read = sdmmc_storage_read(&sd_storage, lba_curr + sd_sector_off, num, buf);
 
 		while (res_read)
 		{
@@ -663,7 +663,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 				free(clmt);
 				f_unlink(outFilename);
 
-				return 0;
+				return 1;
 			}
 			else
 			{
@@ -671,8 +671,13 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 			}
+
+			if (!gui->raw_emummc)
+				res_read = sdmmc_storage_read(storage, lba_curr, num, buf);
+			else
+				res_read = sdmmc_storage_read(&sd_storage, lba_curr + sd_sector_off, num, buf);
+			manual_system_maintenance(false);
 		}
-		manual_system_maintenance(false);
 
 		res = f_write_fast(&fp, buf, EMMC_BLOCKSIZE * num);
 
@@ -686,7 +691,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 			free(clmt);
 			f_unlink(outFilename);
 
-			return 0;
+			return 1;
 		}
 
 		manual_system_maintenance(false);
@@ -725,7 +730,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 			free(clmt);
 			f_unlink(outFilename);
 
-			return 0;
+			return 1;
 		}
 	}
 	lv_bar_set_value(gui->bar, 100);
@@ -745,7 +750,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
-			return 0;
+			return 1;
 		}
 		lv_bar_set_value(gui->bar, 100);
 		lv_label_set_text(gui->label_pct, " "SYMBOL_DOT" 100%");
@@ -764,12 +769,12 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part,
 		partial_sd_full_unmount = true;
 	}
 
-	return 1;
+	return 0;
 }
 
 void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui)
 {
-	int res = 0;
+	int res = 1;
 	u32 timer = 0;
 
 	char *txt_buf = (char *)malloc(SZ_16K);
@@ -781,7 +786,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui)
 	lv_label_set_text(gui->label_info, "Checking for available free space...");
 	manual_system_maintenance(true);
 
-	if (!sd_mount())
+	if (sd_mount())
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init SD!#");
 		goto out;
@@ -790,7 +795,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui)
 	// Get SD Card free space for Partial Backup.
 	f_getfree("", &sd_fs.free_clst, NULL);
 
-	if (!emmc_initialize(false))
+	if (emmc_initialize(false))
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#");
 		goto out;
@@ -844,7 +849,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui)
 
 			res = _dump_emmc_part(gui, sdPath, i, &emmc_storage, &bootPart);
 
-			if (!res)
+			if (res)
 				strcpy(txt_buf, "#FFDD00 Failed!#\n");
 			else
 				strcpy(txt_buf, "Done!\n");
@@ -884,7 +889,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui)
 				emmcsn_path_impl(sdPath, "/partitions", part->name, &emmc_storage);
 				res = _dump_emmc_part(gui, sdPath, 0, &emmc_storage, part);
 				// If a part failed, don't continue.
-				if (!res)
+				if (res)
 				{
 					strcpy(txt_buf, "#FFDD00 Failed!#\n");
 					lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf);
@@ -927,7 +932,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui)
 
 				res = _dump_emmc_part(gui, sdPath, 2, &emmc_storage, &rawPart);
 
-				if (!res)
+				if (res)
 					strcpy(txt_buf, "#FFDD00 Failed!#\n");
 				else
 					strcpy(txt_buf, "Done!\n");
@@ -941,9 +946,9 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui)
 	timer = get_tmr_s() - timer;
 	emmc_end();
 
-	if (res && n_cfg.verification && !gui->raw_emummc)
+	if (!res && n_cfg.verification && !gui->raw_emummc)
 		s_printf(txt_buf, "Time taken: %dm %ds.\n#96FF00 Finished and verified!#", timer / 60, timer % 60);
-	else if (res)
+	else if (!res)
 		s_printf(txt_buf, "Time taken: %dm %ds.\nFinished!", timer / 60, timer % 60);
 	else
 		s_printf(txt_buf, "Time taken: %dm %ds.", timer / 60, timer % 60);
@@ -1027,13 +1032,13 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 
-				return 0;
+				return 1;
 			}
 			else if (f_stat(outFilename, &fno))
 			{
 				if (!gui->raw_emummc)
 				{
-					s_printf(gui->txt_buf, "\n#FFDD00 Error (%d) file not found#\n#FFDD00 %s.#\n\n", res, outFilename);
+					s_printf(gui->txt_buf, "\n#FFDD00 Error file not found#\n#FFDD00 %s.#\n\n", outFilename);
 					lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 					manual_system_maintenance(true);
 
@@ -1056,7 +1061,7 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa
 					lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 					manual_system_maintenance(true);
 
-					return 0;
+					return 1;
 				}
 			}
 			else
@@ -1069,7 +1074,7 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa
 					lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 					manual_system_maintenance(true);
 
-					return 0;
+					return 1;
 				}
 
 				check_4MB_aligned = false;
@@ -1097,7 +1102,7 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 
-				return 0;
+				return 1;
 			}
 			lv_obj_del(warn_mbox_bg);
 
@@ -1143,7 +1148,7 @@ multipart_not_allowed:
 			manual_system_maintenance(true);
 		}
 
-		return -1;
+		return 2;
 	}
 	else if (!use_multipart && (((u32)((u64)f_size(&fp) >> (u64)9)) != totalSectors)) // Check total restore size vs emmc size.
 	{
@@ -1155,7 +1160,7 @@ multipart_not_allowed:
 
 			f_close(&fp);
 
-			return 0;
+			return 1;
 		}
 		else if (!gui->raw_emummc)
 		{
@@ -1174,7 +1179,7 @@ multipart_not_allowed:
 
 				f_close(&fp);
 
-				return 0;
+				return 1;
 			}
 			lv_obj_del(warn_mbox_bg);
 		}
@@ -1216,7 +1221,7 @@ multipart_not_allowed:
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
-			return 0;
+			return 1;
 		}
 		sd_sector_off = sector_start + (0x2000 * active_part);
 	}
@@ -1246,7 +1251,7 @@ multipart_not_allowed:
 					strcpy(gui->txt_buf, "\n#FFDD00 Please try again...#\n");
 					lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 					manual_system_maintenance(true);
-					return 0;
+					return 1;
 				case VERIF_STATUS_ABORT:
 					verification = 0;
 					break;
@@ -1275,7 +1280,7 @@ multipart_not_allowed:
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 
-				return 0;
+				return 1;
 			}
 			fileSize = (u64)f_size(&fp);
 			bytesWritten = 0;
@@ -1299,12 +1304,12 @@ multipart_not_allowed:
 
 			f_close(&fp);
 			free(clmt);
-			return 0;
+			return 1;
 		}
 		if (!gui->raw_emummc)
-			res = !sdmmc_storage_write(storage, lba_curr, num, buf);
+			res = sdmmc_storage_write(storage, lba_curr, num, buf);
 		else
-			res = !sdmmc_storage_write(&sd_storage, lba_curr + sd_sector_off, num, buf);
+			res = sdmmc_storage_write(&sd_storage, lba_curr + sd_sector_off, num, buf);
 
 		manual_system_maintenance(false);
 
@@ -1328,7 +1333,7 @@ multipart_not_allowed:
 
 				f_close(&fp);
 				free(clmt);
-				return 0;
+				return 1;
 			}
 			else
 			{
@@ -1337,9 +1342,9 @@ multipart_not_allowed:
 				manual_system_maintenance(true);
 			}
 			if (!gui->raw_emummc)
-				res = !sdmmc_storage_write(storage, lba_curr, num, buf);
+				res = sdmmc_storage_write(storage, lba_curr, num, buf);
 			else
-				res = !sdmmc_storage_write(&sd_storage, lba_curr + sd_sector_off, num, buf);
+				res = sdmmc_storage_write(&sd_storage, lba_curr + sd_sector_off, num, buf);
 			manual_system_maintenance(false);
 		}
 		pct = (u64)((u64)(lba_curr - part->lba_start) * 100u) / (u64)(lba_end - part->lba_start);
@@ -1373,7 +1378,7 @@ multipart_not_allowed:
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
-			return 0;
+			return 1;
 		}
 		lv_bar_set_value(gui->bar, 100);
 		lv_label_set_text(gui->label_pct, " "SYMBOL_DOT" 100%");
@@ -1397,7 +1402,7 @@ multipart_not_allowed:
 		save_emummc_cfg(part_idx, sector_start, sdPath);
 	}
 
-	return 1;
+	return 0;
 }
 
 void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui)
@@ -1457,13 +1462,13 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui)
 	lv_obj_del(warn_mbox_bg);
 	manual_system_maintenance(true);
 
-	if (!sd_mount())
+	if (sd_mount())
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init SD!#");
 		goto out;
 	}
 
-	if (!emmc_initialize(false))
+	if (emmc_initialize(false))
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#");
 		goto out;
@@ -1512,15 +1517,14 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui)
 				emmcsn_path_impl(sdPath, "/restore/emummc", bootPart.name, &emmc_storage);
 			res = _restore_emmc_part(gui, sdPath, i, &emmc_storage, &bootPart, false);
 
-			if (!res)
+			if (res == 1)
 				strcpy(txt_buf, "#FFDD00 Failed!#\n");
-			else if (res > 0)
+			else if (!res)
 				strcpy(txt_buf, "Done!\n");
 
-			if (res >= 0)
+			if (res <= 1)
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf);
-			else
-				res = 0;
+
 			manual_system_maintenance(true);
 		}
 	}
@@ -1548,15 +1552,14 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui)
 			emmcsn_path_impl(sdPath, "/restore/partitions", part->name, &emmc_storage);
 			res = _restore_emmc_part(gui, sdPath, 0, &emmc_storage, part, false);
 
-			if (!res)
+			if (res == 1)
 				strcpy(txt_buf, "#FFDD00 Failed!#\n");
-			else if (res > 0)
+			else if (!res)
 				strcpy(txt_buf, "Done!\n");
 
-			if (res >= 0)
+			if (res <= 1)
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf);
-			else
-				res = 0;
+
 			manual_system_maintenance(true);
 		}
 		emmc_gpt_free(&gpt);
@@ -1587,15 +1590,14 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui)
 				emmcsn_path_impl(sdPath, "/restore/emummc", rawPart.name, &emmc_storage);
 			res = _restore_emmc_part(gui, sdPath, 2, &emmc_storage, &rawPart, true);
 
-			if (!res)
+			if (res == 1)
 				strcpy(txt_buf, "#FFDD00 Failed!#\n");
-			else if (res > 0)
+			else if (!res)
 				strcpy(txt_buf, "Done!\n");
 
-			if (res >= 0)
+			if (res <= 1)
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf);
-			else
-				res = 0;
+
 			manual_system_maintenance(true);
 		}
 	}
@@ -1603,9 +1605,9 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui)
 	timer = get_tmr_s() - timer;
 	emmc_end();
 
-	if (res && n_cfg.verification && !gui->raw_emummc)
+	if (!res && n_cfg.verification && !gui->raw_emummc)
 		s_printf(txt_buf, "Time taken: %dm %ds.\n#96FF00 Finished and verified!#", timer / 60, timer % 60);
-	else if (res)
+	else if (!res)
 		s_printf(txt_buf, "Time taken: %dm %ds.\nFinished!", timer / 60, timer % 60);
 	else
 		s_printf(txt_buf, "Time taken: %dm %ds.", timer / 60, timer % 60);

nyx/nyx_gui/frontend/fe_emummc_tools.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018 naehrwert
  * Copyright (c) 2018 Rajko Stojadinovic
- * Copyright (c) 2018-2025 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -33,15 +33,13 @@
 #define OUT_FILENAME_SZ      128
 #define NUM_SECTORS_PER_ITER 8192 // 4MB Cache.
 
-extern volatile boot_cfg_t *b_cfg;
-
 void load_emummc_cfg(emummc_cfg_t *emu_info)
 {
 	memset(emu_info, 0, sizeof(emummc_cfg_t));
 
 	// Parse emuMMC configuration.
 	LIST_INIT(ini_sections);
-	if (!ini_parse(&ini_sections, "emuMMC/emummc.ini", false))
+	if (ini_parse(&ini_sections, "emuMMC/emummc.ini", false))
 		return;
 
 	LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link)
@@ -172,7 +170,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto
 		lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 		manual_system_maintenance(true);
 
-		return 0;
+		return 1;
 	}
 
 	// Check if filesystem is FAT32 or the free space is smaller and dump in parts.
@@ -198,7 +196,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto
 		lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 		manual_system_maintenance(true);
 
-		return 0;
+		return 1;
 	}
 
 	u8 *buf = (u8 *)MIXD_BUF_ALIGNED;
@@ -244,7 +242,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 
-				return 0;
+				return 1;
 			}
 
 			bytesWritten = 0;
@@ -266,13 +264,13 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto
 
 			msleep(1000);
 
-			return 0;
+			return 1;
 		}
 
 		retryCount = 0;
 		num = MIN(totalSectors, NUM_SECTORS_PER_ITER);
 
-		while (!sdmmc_storage_read(storage, lba_curr, num, buf))
+		while (sdmmc_storage_read(storage, lba_curr, num, buf))
 		{
 			s_printf(gui->txt_buf,
 				"\n#FFDD00 Error reading %d blocks @ LBA %08X,#\n"
@@ -292,7 +290,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto
 				free(clmt);
 				f_unlink(outFilename);
 
-				return 0;
+				return 1;
 			}
 			else
 			{
@@ -318,7 +316,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto
 			free(clmt);
 			f_unlink(outFilename);
 
-			return 0;
+			return 1;
 		}
 		pct = (u64)((u64)(lba_curr - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start);
 		if (pct != prevPct)
@@ -352,12 +350,12 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto
 	f_close(&fp);
 	free(clmt);
 
-	return 1;
+	return 0;
 }
 
 void dump_emummc_file(emmc_tool_gui_t *gui)
 {
-	int res = 0;
+	int res = 1;
 	int base_len = 0;
 	u32 timer = 0;
 
@@ -370,7 +368,7 @@ void dump_emummc_file(emmc_tool_gui_t *gui)
 
 	manual_system_maintenance(true);
 
-	if (!sd_mount())
+	if (sd_mount())
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init SD!#");
 		goto out;
@@ -382,7 +380,7 @@ void dump_emummc_file(emmc_tool_gui_t *gui)
 	// Get SD Card free space for file based emuMMC.
 	f_getfree("", &sd_fs.free_clst, NULL);
 
-	if (!emmc_initialize(false))
+	if (emmc_initialize(false))
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#");
 		goto out;
@@ -434,7 +432,7 @@ void dump_emummc_file(emmc_tool_gui_t *gui)
 		strcat(sdPath, bootPart.name);
 		res = _dump_emummc_file_part(gui, sdPath, &emmc_storage, &bootPart);
 
-		if (!res)
+		if (res)
 		{
 			s_printf(txt_buf, "#FFDD00 Failed!#\n");
 			goto out_failed;
@@ -469,7 +467,7 @@ void dump_emummc_file(emmc_tool_gui_t *gui)
 
 	res = _dump_emummc_file_part(gui, sdPath, &emmc_storage, &rawPart);
 
-	if (!res)
+	if (res)
 		s_printf(txt_buf, "#FFDD00 Failed!#\n");
 	else
 		s_printf(txt_buf, "Done!\n");
@@ -481,7 +479,7 @@ out_failed:
 	timer = get_tmr_s() - timer;
 	emmc_end();
 
-	if (res)
+	if (!res)
 	{
 		s_printf(txt_buf, "Time taken: %dm %ds.\nFinished!", timer / 60, timer % 60);
 		gui->base_path[strlen(gui->base_path) - 5] = '\0';
@@ -545,7 +543,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
-			return 0;
+			return 1;
 		}
 
 		user_offset = user_part->lba_start;
@@ -559,20 +557,20 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 		// Check for cancellation combo.
 		if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN))
 		{
-			s_printf(gui->txt_buf, "\n#FFDD00 The emuMMC was cancelled!#\n");
+			s_printf(gui->txt_buf, "\n#FFDD00 emuMMC creation was cancelled!#\n");
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			manual_system_maintenance(true);
 
 			msleep(1000);
 
-			return 0;
+			return 1;
 		}
 
 		retryCount = 0;
 		num = MIN(totalSectors, NUM_SECTORS_PER_ITER);
 
 		// Read data from eMMC.
-		while (!sdmmc_storage_read(&emmc_storage, lba_curr, num, buf))
+		while (sdmmc_storage_read(&emmc_storage, lba_curr, num, buf))
 		{
 			s_printf(gui->txt_buf,
 				"\n#FFDD00 Error reading %d blocks @LBA %08X,#\n"
@@ -588,7 +586,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 
-				return 0;
+				return 1;
 			}
 			else
 			{
@@ -602,7 +600,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 
 		// Write data to SD card.
 		retryCount = 0;
-		while (!sdmmc_storage_write(&sd_storage, sd_sector_off + lba_curr, num, buf))
+		while (sdmmc_storage_write(&sd_storage, sd_sector_off + lba_curr, num, buf))
 		{
 			s_printf(gui->txt_buf,
 				"\n#FFDD00 Error writing %d blocks @LBA %08X,#\n"
@@ -618,7 +616,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 				lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 				manual_system_maintenance(true);
 
-				return 0;
+				return 1;
 			}
 			else
 			{
@@ -690,7 +688,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 			s_printf(gui->txt_buf, "#FF0000 Failed (%d)!#\nPlease try again...\n", mkfs_error);
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 
-			return 0;
+			return 1;
 		}
 		lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, "Done!\n");
 
@@ -722,7 +720,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 			lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf);
 			free(gpt);
 
-			return 0;
+			return 1;
 		}
 
 		// Set new emuMMC size and USER size.
@@ -763,16 +761,17 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part
 		free(gpt);
 	}
 
-	return 1;
+	return 0;
 }
 
 int emummc_raw_derive_bis_keys()
 {
-	// Generate BIS keys.
-	hos_bis_keygen();
-
 	u8 *cal0_buff = malloc(SZ_64K);
 
+	// Generate BIS keys.
+	if (hos_bis_keygen())
+		goto error;
+
 	// Read and decrypt CAL0 for validation of working BIS keys.
 	emmc_set_partition(EMMC_GPP);
 	LIST_INIT(gpt);
@@ -788,6 +787,7 @@ int emummc_raw_derive_bis_keys()
 	// Check keys validity.
 	if (memcmp(&cal0->magic, "CAL0", 4))
 	{
+error:
 		// Clear EKS keys.
 		hos_eks_clear(HOS_MKEY_VER_MAX);
 
@@ -809,7 +809,7 @@ int emummc_raw_derive_bis_keys()
 		lv_obj_set_width(lb_desc, LV_HOR_RES / 9 * 4);
 
 		lv_label_set_text(lb_desc, "#FFDD00 BIS keys validation failed!#\n");
-		lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action);
+		lv_mbox_add_btns(mbox, mbox_btn_map, nyx_mbox_action);
 
 		lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0);
 		lv_obj_set_top(mbox, true);
@@ -825,7 +825,7 @@ int emummc_raw_derive_bis_keys()
 
 void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 resized_count)
 {
-	int res = 0;
+	int res = 1;
 	u32 timer = 0;
 
 	char *txt_buf = (char *)malloc(SZ_16K);
@@ -837,13 +837,13 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r
 
 	manual_system_maintenance(true);
 
-	if (!sd_mount())
+	if (sd_mount())
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init SD!#");
 		goto out;
 	}
 
-	if (!emmc_initialize(false))
+	if (emmc_initialize(false))
 	{
 		lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#");
 		goto out;
@@ -896,7 +896,7 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r
 		strcat(sdPath, bootPart.name);
 		res = _dump_emummc_raw_part(gui, i, part_idx, sector_start, &bootPart, 0);
 
-		if (!res)
+		if (res)
 		{
 			s_printf(txt_buf, "#FFDD00 Failed!#\n");
 			goto out_failed;
@@ -930,7 +930,7 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r
 
 		res = _dump_emummc_raw_part(gui, 2, part_idx, sector_start, &rawPart, resized_count);
 
-		if (!res)
+		if (res)
 			s_printf(txt_buf, "#FFDD00 Failed!#\n");
 		else
 			s_printf(txt_buf, "Done!\n");
@@ -943,7 +943,7 @@ out_failed:
 	timer = get_tmr_s() - timer;
 	emmc_end();
 
-	if (res)
+	if (!res)
 	{
 		s_printf(txt_buf, "Time taken: %dm %ds.\nFinished!", timer / 60, timer % 60);
 		strcpy(sdPath, gui->base_path);