bdk: mc: add offset to arc aperture
And increase it back to 4KB for TSEC only, since the firmware actually checks for it.
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@@ -107,13 +107,13 @@ void mc_config_carveout_hos()
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}
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// SDMMC, TSEC, XUSB and probably more need it to access < DRAM_START.
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void mc_enable_ahb_redirect()
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void mc_enable_ahb_redirect(u32 offset)
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{
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// Bypass ARC clock gating.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19);
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//MC(MC_IRAM_REG_CTRL) &= ~BIT(0);
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MC(MC_IRAM_BOM) = IRAM_BASE;
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MC(MC_IRAM_TOM) = DRAM_START - 1; // Default is only IRAM: 0x4003F000.
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MC(MC_IRAM_TOM) = DRAM_START - offset; // Default is only IRAM: 0x4003F000.
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}
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void mc_disable_ahb_redirect()
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@@ -150,5 +150,5 @@ void mc_enable()
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usleep(5);
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// Enable redirection by default.
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mc_enable_ahb_redirect();
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mc_enable_ahb_redirect(1);
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}
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@@ -22,7 +22,7 @@
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void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock);
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void mc_config_carveout_hos();
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void mc_enable_ahb_redirect();
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void mc_enable_ahb_redirect(u32 offset);
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void mc_disable_ahb_redirect();
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bool mc_client_has_access(void *address);
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void mc_enable();
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@@ -97,7 +97,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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pmc_domain_pwrgate_set(POWER_RAIL_CE3, DISABLE);
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// Enable AHB aperture and set it to full mmio.
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mc_enable_ahb_redirect();
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mc_enable_ahb_redirect(0);
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}
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// Configure Falcon.
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@@ -308,7 +308,7 @@ out:
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bpmp_clk_rate_relaxed(false);
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// Re-enable AHB aperture.
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mc_enable_ahb_redirect();
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mc_enable_ahb_redirect(1);
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return res;
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}
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@@ -931,7 +931,7 @@ int xusb_device_init()
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bpmp_clk_rate_relaxed(false);
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// Enable AHB redirect for access to IRAM for Event/EP ring buffers.
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mc_enable_ahb_redirect();
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mc_enable_ahb_redirect(1);
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// Enable XUSB device IPFS.
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XUSB_DEV_DEV(XUSB_DEV_CONFIGURATION) |= DEV_CONFIGURATION_EN_FPCI;
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