bdk: mc: add offset to arc aperture

And increase it back to 4KB for TSEC only, since the firmware actually checks for it.
This commit is contained in:
CTCaer
2026-03-20 13:34:55 +02:00
parent e26b941f90
commit 9494767295
4 changed files with 7 additions and 7 deletions

View File

@@ -107,13 +107,13 @@ void mc_config_carveout_hos()
}
// SDMMC, TSEC, XUSB and probably more need it to access < DRAM_START.
void mc_enable_ahb_redirect()
void mc_enable_ahb_redirect(u32 offset)
{
// Bypass ARC clock gating.
CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19);
//MC(MC_IRAM_REG_CTRL) &= ~BIT(0);
MC(MC_IRAM_BOM) = IRAM_BASE;
MC(MC_IRAM_TOM) = DRAM_START - 1; // Default is only IRAM: 0x4003F000.
MC(MC_IRAM_TOM) = DRAM_START - offset; // Default is only IRAM: 0x4003F000.
}
void mc_disable_ahb_redirect()
@@ -150,5 +150,5 @@ void mc_enable()
usleep(5);
// Enable redirection by default.
mc_enable_ahb_redirect();
mc_enable_ahb_redirect(1);
}

View File

@@ -22,7 +22,7 @@
void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock);
void mc_config_carveout_hos();
void mc_enable_ahb_redirect();
void mc_enable_ahb_redirect(u32 offset);
void mc_disable_ahb_redirect();
bool mc_client_has_access(void *address);
void mc_enable();

View File

@@ -97,7 +97,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
pmc_domain_pwrgate_set(POWER_RAIL_CE3, DISABLE);
// Enable AHB aperture and set it to full mmio.
mc_enable_ahb_redirect();
mc_enable_ahb_redirect(0);
}
// Configure Falcon.
@@ -308,7 +308,7 @@ out:
bpmp_clk_rate_relaxed(false);
// Re-enable AHB aperture.
mc_enable_ahb_redirect();
mc_enable_ahb_redirect(1);
return res;
}

View File

@@ -931,7 +931,7 @@ int xusb_device_init()
bpmp_clk_rate_relaxed(false);
// Enable AHB redirect for access to IRAM for Event/EP ring buffers.
mc_enable_ahb_redirect();
mc_enable_ahb_redirect(1);
// Enable XUSB device IPFS.
XUSB_DEV_DEV(XUSB_DEV_CONFIGURATION) |= DEV_CONFIGURATION_EN_FPCI;