OmniNX/hekate
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e937689ca36222548dba6777b13d6bdebb43b0ac
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633 Commits

Author SHA1 Message Date
CTCaer
9494767295 bdk: mc: add offset to arc aperture 
And increase it back to 4KB for TSEC only, since the firmware actually checks for it.
 2026-03-20 13:34:55 +02:00
CTCaer
1ad2233db5 bdk: sdmmc: parse bkops info 2026-03-19 15:15:40 +02:00
CTCaer
8ae7404529 bdk: memory map: define max use from sdram params 2026-03-18 22:35:01 +02:00
CTCaer
ef1ce85735 bdk: sdmmc: rename bkops define 
And remove dead code.
 2026-03-18 22:35:01 +02:00
CTCaer
c6c89ce0b1 bdk: smmu: reset heap on disable 
And rename domain init/deinit
 2026-03-18 22:35:01 +02:00
CTCaer
5328c21df6 bdk: sdram: add missing T210 1GB density timings 2026-03-18 22:35:01 +02:00
CTCaer
a052929c5a bdk: lvgl: add creme accent support 2026-03-18 22:35:01 +02:00
CTCaer
e3334b9a85 bdk: lvgl: correct slider knob signal coordinates 
It should always point to the middle of the knob and not be variable with offset.
 2026-03-18 22:35:01 +02:00
CTCaer
f2c2a77bc4 touch: increase max allowed touched area 2026-03-18 22:35:01 +02:00
CTCaer
fc370d0608 bdk: mc: reduce ahb aperture by 4KB 
The state machine automatically uses TOM + 4KB as real top address.
This can cause issues with HW that accesses that low RAM range,
since once the request enters ARC can't be redirected to MC and can hang.
 2026-02-25 13:49:33 +02:00
CTCaer
392cda96d9 bdk: mc: always enable ahb redirection 2026-02-25 13:32:18 +02:00
CTCaer
1b8aa8a97b bdk: touch: add clone support 
From LCD on OLED sku.
 2026-02-22 08:51:54 +02:00
CTCaer
25fda88e46 bdk: sdmmc: homogenize return values 
The actual target of this refactoring.
 2026-02-22 08:32:34 +02:00
CTCaer
719c109d4e bdk: ini: homogenize return values 2026-02-22 03:23:28 +02:00
CTCaer
4f9a173087 bdk: pmc: homogenize return values 2026-02-22 03:17:48 +02:00
CTCaer
6c642abb7b bdk: kfuse: homogenize return values 2026-02-22 03:15:41 +02:00
CTCaer
5471449860 bdk: clock: homogenize return values 2026-02-22 03:13:50 +02:00
CTCaer
0b7415f6d4 bdk: tsec: homogenize return values 2026-02-22 03:10:18 +02:00
CTCaer
d328d56268 bdk: se: homogenize return values 2026-02-22 03:08:34 +02:00
CTCaer
ab799e4ee7 bdk: power: homogenize return values 2026-02-22 02:57:38 +02:00
CTCaer
1f2855b17d bdk: dram: homogenize return values 2026-02-22 02:53:55 +02:00
CTCaer
9b2026ac6e bdk: touch: homogenize return values 2026-02-22 02:50:45 +02:00
CTCaer
cb81aaecdb bdk: i2c: homogenize return values 2026-02-22 02:42:53 +02:00
CTCaer
722a4a24c8 bdk: vic: expose idle wait 2026-02-22 02:27:08 +02:00
CTCaer
2824dff8f0 bdk: touch: check event count for wait event 
And increase checks during autotune execution.
 2026-02-21 09:15:15 +02:00
CTCaer
3e141fba20 bdk: touch: simplify input reporting 
Additionally, touch polling now returns 1 for no event result.
 2026-02-20 02:50:18 +02:00
CTCaer
c067c113e6 bdk: touch: switch to custom chip info cmd 
And also check if chip id is correct on init.
 2026-02-20 02:39:54 +02:00
CTCaer
98c14fd3c1 bdk: touch: use packet i2c for all transfers 
The repeating byte doesn't exist in i2c packet mode.
Additionally, adjust split transfers to one.
 2026-02-20 02:36:38 +02:00
CTCaer
f6bf40b903 bdk: touch: refactor 
And also use packet mode for big tx/rx combo i2c trasnfers.
 2026-02-20 00:43:58 +02:00
CTCaer
0815ae9c58 bdk: i2c: optimize packet mode functions 
- Allow xfer packet to send up to 20 bytes before receiving
- Remove interrupt use since it's only polling
- Check proper status for TX finish.
 2026-02-20 00:32:36 +02:00
CTCaer
304cb0c571 bdk: i2c: refactor 2026-02-20 00:00:33 +02:00
CTCaer
143b5db993 bdk: clk: add missing macro 2026-02-17 21:43:39 +02:00
CTCaer
0a55598ab6 bdk: touch: refactor/improve 
- Remove useless poll wait
- Use more defines
- Deduplicate code
- Add more checks
- Add switch sense mode
 2026-02-15 02:32:38 +02:00
CTCaer
38e73d6492 bdk: clk: reduce i2c freq input to save power 2026-02-14 23:59:39 +02:00
CTCaer
38210a08d1 bdk: vic: add hw version that this driver aims for 
Also TRM lies about best cache width, like always.
The higher the faster. The lower the simpler alignment.
A balanced one is used by default.
 2026-02-12 22:04:56 +02:00
CTCaer
ca8717d4a7 bdk: bm92t: do not parse non fixed pdos 2026-02-12 21:56:39 +02:00
CTCaer
e6984a149b bdk: sdmmc: remove dependency to ram for init 2026-02-12 21:53:59 +02:00
CTCaer
9171fa70c9 bdk: mem: rename sdmmc dma buffer 2026-02-12 21:38:56 +02:00
CTCaer
d14a1fb7d6 bdk: move exception type base away from IRQ stack 
Allow a more heavy stack usage by IRQ handlers.
 2026-02-12 21:32:43 +02:00
CTCaer
380bbe77a5 bdk: lvgl: complete black theme 
This has the side-effect to make any theme color component from 0x0B to 0xC7 work.
 2026-02-07 00:04:44 +02:00
CTCaer
b297e58bc8 bdk: add missing header guards 2026-01-29 09:07:22 +02:00
CTCaer
2014a72774 bdk: ianos: restructure for future expansion 2026-01-29 08:58:19 +02:00
CTCaer
55330b1bf5 bdk: pmc: refactor register defines and structs 2026-01-29 08:33:01 +02:00
CTCaer
0da69efd07 bdk: pinmux: always detach I2C4 pins from I2C3 pm 
Generally I2C3 communication can work via I2C3 or I2C4 pins.
Defaults are fine as long as one of the pin groups are floating or grounded or
both share I2C traces.

In NX boards I2C4 SDA is used for GC and connected to 1V8.
So if a GC is slotted, I2C3 works, if not, no communication is possible.

This config was done previously inside I2C3 consumer driver (touchscreen).
Now it's moved inside pinmux_config_i2c.
 2026-01-21 23:49:59 +02:00
CTCaer
74972a68df bdk: joycon: make init stricter but relax timings 
Additionally, if both Joy-Con are found, try to send rumble simultaneously.
 2026-01-20 20:03:38 +02:00
CTCaer
3134af6e92 bdk: display: reduce display off waiting time 
And align oled panel inside vblank.
Assumes display deinit happens before the rest of deinit.
 2026-01-20 06:13:02 +02:00
CTCaer
5936d9bad4 bdk: se: add T210 SHA256 silicon errata WAR 
Apparently, some T210 silicon have an undocumented errata where the MSG_LEFT2/3
registers are not ignored as they should.
When they have random data in POR they cause a hang as long as the message and
SHA calculation speed. So always clear them.
Additionally, clear MSG_LENGTH2/3 registers too even though they do not matter.
 2026-01-15 19:09:34 +02:00
CTCaer
68281d3051 bdk: se: adjust T210 silicon errata coherency WAR 
Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).
 2026-01-15 19:02:36 +02:00
CTCaer
e3267d1db7 bdk: se: correct result for < block size aes 2026-01-15 17:40:52 +02:00
CTCaer
8ab6f04243 bdk: hwinit: remove coreboot support 
Everything external is finally updated and beyond parity with old things that needed it.
 2026-01-12 03:57:39 +02:00