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8d6bb5f4273820aefe23a4791eb75545100ad69c
Commit Graph

550 Commits

Author SHA1 Message Date
CTCaer
8d6bb5f427 bdk: clock: update some defines 2025-12-17 04:33:40 +02:00
CTCaer
4797b42e76 bdk: sdmmc: add defines for max block number 2025-12-17 04:30:12 +02:00
CTCaer
7cbefa3061 bdk: add reserved cfg to ipl meta and nyx storage 2025-11-27 12:17:33 +02:00
CTCaer
5176ce4394 bdk: sdmmc: correct drive ohms comment 2025-11-27 12:14:43 +02:00
CTCaer
a6d4e5adaa bdk: clock: add i2c to the errata affected list 2025-11-27 12:12:13 +02:00
CTCaer
4a24956f3a bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2025-11-27 12:04:12 +02:00
CTCaer
727d37c991 bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2025-11-27 11:25:08 +02:00
CTCaer
1fc92cfa33 bdk: nyx: rename disp_id to panel_id 2025-11-27 11:21:06 +02:00
CTCaer
62163f3255 bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2025-11-27 11:20:19 +02:00
CTCaer
fc71e405d2 bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2025-11-27 11:13:54 +02:00
CTCaer
e7783f0bd7 bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2025-11-26 16:53:19 +02:00
CTCaer
e50ad58d61 bdk: clock: add sdmmc1 to the errata affected list 2025-11-26 16:47:29 +02:00
CTCaer
0a63fa19a3 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2025-11-26 16:46:11 +02:00
CTCaer
19285745b5 bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2025-11-26 14:48:47 +02:00
CTCaer
9c028cd94a bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2025-11-26 14:37:14 +02:00
CTCaer
a2ea3fb08e bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2025-11-26 14:33:56 +02:00
CTCaer
813346f796 bdk: bpmp: add binX clock defines 2025-11-11 13:52:00 +02:00
CTCaer
260e28e628 bdk: fuse: add sense function 2025-11-11 13:28:44 +02:00
CTCaer
602945d918 bdk: fuse: add extra info on regs 2025-11-11 13:27:36 +02:00
CTCaer
7e01438ed3 bdk: fuse: correct masking on array read cmd 2025-11-11 13:27:13 +02:00
CTCaer
2c66b17f42 bdk: t210: add mc channel macros 2025-11-11 13:24:06 +02:00
CTCaer
e2f043a58a bdk: emc/mc: don't use [io]_rsvd naming for unused regs 2025-11-11 13:23:07 +02:00
CTCaer
0737f27ba0 bdk: lvgl: make sure task has a task to call 2025-11-11 13:17:34 +02:00
CTCaer
ded26332c6 bdk: ini: switch back to ASCII ordering 
For combining multiple inis.
 2025-08-27 15:22:54 +03:00
CTCaer
9309b53054 bdk: dirlist: use flags instead of arguments 
A new flag was also added that forces an ASCII ordering instead of Alphabetical one.
 2025-08-27 15:18:41 +03:00
CTCaer
9368a780cd bdk: minerva: allow sdmmc la to be skipped on L4T 2025-08-27 15:16:42 +03:00
CTCaer
20fa8382e6 bdk: hwinit: refactor MBIST WAR & add description 
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
 2025-08-27 15:13:56 +03:00
CTCaer
3cde8b7d58 bdk: hwinit: fix RAM_SVOP_PDP try no 2 
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
 2025-08-27 15:10:47 +03:00
CTCaer
bdf556fd36 bdk: storage: small mmc refactoring 
- Correct some Response Type names
- And use _def for mmc defines similarly to sd_def
 2025-08-27 15:08:11 +03:00
CTCaer
fee7571135 bdk: mc: carveouts are not set by cfg so fix them 
For HOS <= 3.0.2 the carveouts are set by bootloader and sdram config actually does not set them.
So add which need different value from reset and also make sure that data is flushed for WPR config.
 2025-08-27 15:02:27 +03:00
CTCaer
459fe8c19c bdk: make use of new MC/EMC defines 2025-08-27 14:57:12 +03:00
CTCaer
a1e4549c29 bdk: rework MC/EMC register defines from scratch 
And add register structs also.
 2025-08-27 14:52:36 +03:00
CTCaer
f354f0e5bd bdk: add some t210 and fuses defines 
PGUP tag register can be used to identify which cpu we are running on.
 2025-08-27 14:48:35 +03:00
CTCaer
ea3a60f516 bdk: clock: simplify logic 
Simplify logic for clock enable and sdmmc clock management
 2025-08-27 14:44:41 +03:00
CTCaer
b4b3133570 bdk: clock: remove non existent module ids 
And add comments to special handling ones
 2025-08-27 14:41:27 +03:00
CTCaer
c63ccd0cdc bdk: pmc: rename pmc_enable_partition 2025-08-27 14:39:44 +03:00
CTCaer
8be2c5506e bdk: clock: wait for PLLD to lock when set 2025-08-08 15:58:32 +03:00
CTCaer
f083dcd280 bdk: add tegra BCT/BIT headers for T210/T210B01 2025-08-08 15:12:30 +03:00
CTCaer
28594c8777 bdk: rtc: add auto dst support and fix an off-by-one 2025-08-08 14:47:47 +03:00
CTCaer
a1a6111819 bdk: lvgl: set long press to 5s 2025-06-22 13:39:37 +03:00
CTCaer
01c414a180 bdk: fatfs: optimize format and fix PrFILE2 SAFE 
The FAT tables are now always aligned 1MB which can increase the FAT traversing
speed. Additionally, always aligning the FAT tables to minimum 16KB fixes a case
where PrFILE2 SAFE could be disabled because of unaligned FAT.
 2025-06-22 13:38:56 +03:00
CTCaer
9fe953bee1 bdk: use f_unmount instead of null f_mount 2025-06-22 13:34:42 +03:00
CTCaer
05cc9b6985 bdk: refactor several comments and defines 2025-06-22 13:32:32 +03:00
CTCaer
d9fda9411b bdk: update memory map to increase ramdisk size 
From 1040 to 1280MB.
 2025-06-22 13:27:25 +03:00
CTCaer
40b05ea5ea bdk: usb: revamp hid logic 
- Add support for GET REPORT. Allows OS to get a single input report.
- Add support for SET_IDLE. Allows OS to control when to send input reports

The SET IDLE and the underlying logic change fixes several things:
- The old issue of congestion in some systems.
- The new bug that would not allow setup packets to be received because mode
 was set to only send when there are changes.
- Now this starts properly as the old code but allows to be changed by OS on
 demand, while continuing servicing setup packets.
 2025-06-22 13:24:47 +03:00
CTCaer
e1ea05d53a bdk: usb: small refactor 2025-06-22 13:16:10 +03:00
CTCaer
88c0d13f0b bdk: usb: remove unused endpoint from hid 2025-06-22 13:10:47 +03:00
CTCaer
a1e8ddb2a7 bdk: max17050: add version check 2025-06-22 13:00:50 +03:00
CTCaer
39de4464ee bdk: bq24193: add version check 2025-06-22 13:00:27 +03:00
CTCaer
835dba384b bdk: bm92t: add version check 2025-06-22 13:00:01 +03:00