- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
19285745b5