OmniNX/hekate
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

bdk: emc/mc: don't use [io]_rsvd naming for unused regs

Browse Source
This commit is contained in:
CTCaer
2025-11-11 13:23:07 +02:00
parent 0737f27ba0
commit e2f043a58a
2 changed files with 152 additions and 152 deletions
Download Patch File Download Diff File Expand all files Collapse all files

142
bdk/mem/emc_t210.h
View File

@@ -758,7 +758,7 @@ typedef struct _emc_regs_t210_t {
/* 0x008 */ u32 emc_dbg;
/* 0x00c */ u32 emc_cfg;
/* 0x010 */ u32 emc_adr_cfg;
/* 0x014 */ u32 emc_rsvd_14[3];
/* 0x014 */ u32 rsvd_014[3];
/* 0x020 */ u32 emc_refctrl;
/* 0x024 */ u32 emc_pin;
/* 0x028 */ u32 emc_timing_control;
@@ -841,7 +841,7 @@ typedef struct _emc_regs_t210_t {
/* 0x15c */ u32 emc_tpd;
/* 0x160 */ u32 emc_stat_control;
/* 0x164 */ u32 emc_stat_status;
/* 0x168 */ u32 emc_rsvd_168[13];
/* 0x168 */ u32 rsvd_168[13];
/* 0x19c */ u32 emc_stat_dram_clock_limit_lo;
/* 0x1a0 */ u32 emc_stat_dram_clock_limit_hi;
/* 0x1a4 */ u32 emc_stat_dram_clocks_lo;
@@ -927,10 +927,10 @@ typedef struct _emc_regs_t210_t {
/* 0x2e4 */ u32 emc_zcal_wait_cnt;
/* 0x2e8 */ u32 emc_zcal_mrw_cmd;
/* 0x2ec */ u32 emc_zq_cal;
/* 0x2f0 */ u32 emc_rsvd_2f0;
/* 0x2f0 */ u32 rsvd_2f0;
/* 0x2f4 */ u32 emc_xm2comppadctrl3;
/* 0x2f8 */ u32 emc_auto_cal_vref_sel_0;
/* 0x2fc */ u32 emc_rsvd_2fc;
/* 0x2fc */ u32 rsvd_2fc;
/* 0x300 */ u32 emc_auto_cal_vref_sel_1;
/* 0x304 */ u32 emc_pmacro_pmu_ctrl_b01;
/* 0x308 */ u32 emc_pmacro_xm2comp_pmu_ctrl_b01;
@@ -939,12 +939,12 @@ typedef struct _emc_regs_t210_t {
/* 0x314 */ u32 emc_fdpd_ctrl_cmd;
/* 0x318 */ u32 emc_pmacro_cmd_brick_ctrl_fdpd;
/* 0x31c */ u32 emc_pmacro_data_brick_ctrl_fdpd;
/* 0x320 */ u32 emc_rsvd_320;
/* 0x320 */ u32 rsvd_320;
/* 0x324 */ u32 emc_scratch0;
/* 0x328 */ u32 emc_rsvd_328[2];
/* 0x328 */ u32 rsvd_328[2];
/* 0x330 */ u32 emc_pmacro_brick_ctrl_rfu1;
/* 0x334 */ u32 emc_pmacro_brick_ctrl_rfu2;
/* 0x338 */ u32 emc_rsvd_338[18];
/* 0x338 */ u32 rsvd_338[18];
/* 0x380 */ u32 emc_cmd_mapping_cmd0_0;
/* 0x384 */ u32 emc_cmd_mapping_cmd0_1;
/* 0x388 */ u32 emc_cmd_mapping_cmd0_2;
@@ -982,28 +982,28 @@ typedef struct _emc_regs_t210_t {
/* 0x408 */ u32 emc_swizzle_rank0_byte1;
/* 0x40c */ u32 emc_swizzle_rank0_byte2;
/* 0x410 */ u32 emc_swizzle_rank0_byte3;
/* 0x414 */ u32 emc_rsvd_414;
/* 0x414 */ u32 rsvd_414;
/* 0x418 */ u32 emc_swizzle_rank1_byte0;
/* 0x41c */ u32 emc_swizzle_rank1_byte1;
/* 0x420 */ u32 emc_swizzle_rank1_byte2;
/* 0x424 */ u32 emc_swizzle_rank1_byte3;
/* 0x428 */ u32 emc_issue_qrst;
/* 0x42c */ u32 emc_auto_cal_config9_b01;
/* 0x430 */ u32 emc_rsvd_430[4];
/* 0x430 */ u32 rsvd_430[4];
/* 0x440 */ u32 emc_pmc_scratch1;
/* 0x444 */ u32 emc_pmc_scratch2;
/* 0x448 */ u32 emc_pmc_scratch3;
/* 0x44c */ u32 emc_pmacro_ddllcal_en_b01;
/* 0x450 */ u32 emc_rsvd_450[2];
/* 0x450 */ u32 rsvd_450[2];
/* 0x458 */ u32 emc_auto_cal_config2;
/* 0x45c */ u32 emc_auto_cal_config3;
/* 0x460 */ u32 emc_tr_dvfs;
/* 0x464 */ u32 emc_auto_cal_channel;
/* 0x468 */ u32 emc_ibdly;
/* 0x46c */ u32 emc_obdly;
/* 0x470 */ u32 emc_rsvd_470[4];
/* 0x470 */ u32 rsvd_470[4];
/* 0x480 */ u32 emc_txdsrvttgen;
/* 0x484 */ u32 emc_rsvd_484[2];
/* 0x484 */ u32 rsvd_484[2];
/* 0x48c */ u32 emc_we_duration;
/* 0x490 */ u32 emc_ws_duration;
/* 0x494 */ u32 emc_wev;
@@ -1019,13 +1019,13 @@ typedef struct _emc_regs_t210_t {
/* 0x4bc */ u32 emc_mrw12;
/* 0x4c0 */ u32 emc_mrw13;
/* 0x4c4 */ u32 emc_mrw14;
/* 0x4c8 */ u32 emc_rsvd_4c8[2];
/* 0x4c8 */ u32 rsvd_4c8[2];
/* 0x4d0 */ u32 emc_mrw15;
/* 0x4d4 */ u32 emc_cfg_sync;
/* 0x4d8 */ u32 emc_fdpd_ctrl_cmd_no_ramp;
/* 0x4dc */ u32 emc_rsvd_4dc;
/* 0x4dc */ u32 rsvd_4dc;
/* 0x4e0 */ u32 emc_wdv_chk;
/* 0x4e4 */ u32 emc_rsvd_4e4[28];
/* 0x4e4 */ u32 rsvd_4e4[28];
/* 0x554 */ u32 emc_cfg_pipe_2;
/* 0x558 */ u32 emc_cfg_pipe_clk;
/* 0x55c */ u32 emc_cfg_pipe_1;
@@ -1033,7 +1033,7 @@ typedef struct _emc_regs_t210_t {
/* 0x564 */ u32 emc_qpop;
/* 0x568 */ u32 emc_quse_width;
/* 0x56c */ u32 emc_puterm_width;
/* 0x570 */ u32 emc_rsvd_570;
/* 0x570 */ u32 rsvd_570;
/* 0x574 */ u32 emc_auto_cal_config7;
/* 0x578 */ u32 emc_xm2comppadctrl2;
/* 0x57c */ u32 emc_comp_pad_sw_ctrl;
@@ -1074,91 +1074,91 @@ typedef struct _emc_regs_t210_t {
/* 0x5f0 */ u32 emc_config_sample_delay;
/* 0x5f4 */ u32 emc_cfg_update;
/* 0x5f8 */ u32 emc_pmacro_dll_cfg_2_b01;
/* 0x5fc */ u32 emc_rsvd_5fc;
/* 0x5fc */ u32 rsvd_5fc;
/* 0x600 */ u32 emc_pmacro_quse_ddll_rank0_0;
/* 0x604 */ u32 emc_pmacro_quse_ddll_rank0_1;
/* 0x608 */ u32 emc_pmacro_quse_ddll_rank0_2;
/* 0x60c */ u32 emc_pmacro_quse_ddll_rank0_3;
/* 0x610 */ u32 emc_pmacro_quse_ddll_rank0_4;
/* 0x614 */ u32 emc_pmacro_quse_ddll_rank0_5;
/* 0x618 */ u32 emc_rsvd_618[2];
/* 0x618 */ u32 rsvd_618[2];
/* 0x620 */ u32 emc_pmacro_quse_ddll_rank1_0;
/* 0x624 */ u32 emc_pmacro_quse_ddll_rank1_1;
/* 0x628 */ u32 emc_pmacro_quse_ddll_rank1_2;
/* 0x62c */ u32 emc_pmacro_quse_ddll_rank1_3;
/* 0x630 */ u32 emc_pmacro_quse_ddll_rank1_4;
/* 0x634 */ u32 emc_pmacro_quse_ddll_rank1_5;
/* 0x638 */ u32 emc_rsvd_638[2];
/* 0x638 */ u32 rsvd_638[2];
/* 0x640 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
/* 0x644 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
/* 0x648 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
/* 0x64c */ u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
/* 0x650 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
/* 0x654 */ u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
/* 0x658 */ u32 emc_rsvd_658[2];
/* 0x658 */ u32 rsvd_658[2];
/* 0x660 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
/* 0x664 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
/* 0x668 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
/* 0x66c */ u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
/* 0x670 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
/* 0x674 */ u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
/* 0x678 */ u32 emc_rsvd_678[2];
/* 0x678 */ u32 rsvd_678[2];
/* 0x680 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
/* 0x684 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
/* 0x688 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
/* 0x68c */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
/* 0x690 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
/* 0x694 */ u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
/* 0x698 */ u32 emc_rsvd_698[2];
/* 0x698 */ u32 rsvd_698[2];
/* 0x6a0 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
/* 0x6a4 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
/* 0x6a8 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
/* 0x6ac */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
/* 0x6b0 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
/* 0x6b4 */ u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
/* 0x6b8 */ u32 emc_rsvd_6b8[2];
/* 0x6b8 */ u32 rsvd_6b8[2];
/* 0x6c0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
/* 0x6c4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
/* 0x6c8 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
/* 0x6cc */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
/* 0x6d0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_4;
/* 0x6d4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank0_5;
/* 0x6d8 */ u32 emc_rsvd_6d8[2];
/* 0x6d8 */ u32 rsvd_6d8[2];
/* 0x6e0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
/* 0x6e4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
/* 0x6e8 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
/* 0x6ec */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
/* 0x6f0 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_4;
/* 0x6f4 */ u32 emc_pmacro_ib_ddll_long_dqs_rank1_5;
/* 0x6f8 */ u32 emc_rsvd_6f8[2];
/* 0x6f8 */ u32 rsvd_6f8[2];
/* 0x700 */ u32 emc_pmacro_autocal_cfg_0;
/* 0x704 */ u32 emc_pmacro_autocal_cfg_1;
/* 0x708 */ u32 emc_pmacro_autocal_cfg_2;
/* 0x70c */ u32 emc_rsvd_70c[5];
/* 0x70c */ u32 rsvd_70c[5];
/* 0x720 */ u32 emc_pmacro_tx_pwrd_0;
/* 0x724 */ u32 emc_pmacro_tx_pwrd_1;
/* 0x728 */ u32 emc_pmacro_tx_pwrd_2;
/* 0x72c */ u32 emc_pmacro_tx_pwrd_3;
/* 0x730 */ u32 emc_pmacro_tx_pwrd_4;
/* 0x734 */ u32 emc_pmacro_tx_pwrd_5;
/* 0x738 */ u32 emc_rsvd_738[2];
/* 0x738 */ u32 rsvd_738[2];
/* 0x740 */ u32 emc_pmacro_tx_sel_clk_src_0;
/* 0x744 */ u32 emc_pmacro_tx_sel_clk_src_1;
/* 0x748 */ u32 emc_pmacro_tx_sel_clk_src_2;
/* 0x74c */ u32 emc_pmacro_tx_sel_clk_src_3;
/* 0x750 */ u32 emc_pmacro_tx_sel_clk_src_4;
/* 0x754 */ u32 emc_pmacro_tx_sel_clk_src_5;
/* 0x758 */ u32 emc_rsvd_758[2];
/* 0x758 */ u32 rsvd_758[2];
/* 0x760 */ u32 emc_pmacro_ddll_bypass;
/* 0x764 */ u32 emc_rsvd_764[3];
/* 0x764 */ u32 rsvd_764[3];
/* 0x770 */ u32 emc_pmacro_ddll_pwrd_0;
/* 0x774 */ u32 emc_pmacro_ddll_pwrd_1;
/* 0x778 */ u32 emc_pmacro_ddll_pwrd_2;
/* 0x77c */ u32 emc_rsvd_77c;
/* 0x77c */ u32 rsvd_77c;
/* 0x780 */ u32 emc_pmacro_cmd_ctrl_0;
/* 0x784 */ u32 emc_pmacro_cmd_ctrl_1;
/* 0x788 */ u32 emc_pmacro_cmd_ctrl_2;
/* 0x78c */ u32 emc_rsvd_78c[29];
/* 0x78c */ u32 rsvd_78c[29];
/* 0x800 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
/* 0x804 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
/* 0x808 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
@@ -1207,7 +1207,7 @@ typedef struct _emc_regs_t210_t {
/* 0x8b4 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
/* 0x8b8 */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
/* 0x8bc */ u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
/* 0x8c0 */ u32 emc_rsvd_8c0[16];
/* 0x8c0 */ u32 rsvd_8c0[16];
/* 0x900 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
/* 0x904 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
/* 0x908 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
@@ -1256,122 +1256,122 @@ typedef struct _emc_regs_t210_t {
/* 0x9b4 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
/* 0x9b8 */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
/* 0x9bc */ u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
/* 0x9c0 */ u32 emc_rsvd_9c0[16];
/* 0x9c0 */ u32 rsvd_9c0[16];
/* 0xa00 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
/* 0xa04 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
/* 0xa08 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
/* 0xa0c */ u32 emc_rsvd_a0c;
/* 0xa0c */ u32 rsvd_a0c;
/* 0xa10 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
/* 0xa14 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
/* 0xa18 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
/* 0xa1c */ u32 emc_rsvd_a1c;
/* 0xa1c */ u32 rsvd_a1c;
/* 0xa20 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
/* 0xa24 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
/* 0xa28 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
/* 0xa2c */ u32 emc_rsvd_a2c;
/* 0xa2c */ u32 rsvd_a2c;
/* 0xa30 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
/* 0xa34 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
/* 0xa38 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
/* 0xa3c */ u32 emc_rsvd_a3c;
/* 0xa3c */ u32 rsvd_a3c;
/* 0xa40 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
/* 0xa44 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
/* 0xa48 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
/* 0xa4c */ u32 emc_rsvd_a4c;
/* 0xa4c */ u32 rsvd_a4c;
/* 0xa50 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
/* 0xa54 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
/* 0xa58 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
/* 0xa5c */ u32 emc_rsvd_a5c;
/* 0xa5c */ u32 rsvd_a5c;
/* 0xa60 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
/* 0xa64 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
/* 0xa68 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
/* 0xa6c */ u32 emc_rsvd_a6c;
/* 0xa6c */ u32 rsvd_a6c;
/* 0xa70 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
/* 0xa74 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
/* 0xa78 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
/* 0xa7c */ u32 emc_rsvd_a7c;
/* 0xa7c */ u32 rsvd_a7c;
/* 0xa80 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd0_0;
/* 0xa84 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd0_1;
/* 0xa88 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd0_2;
/* 0xa8c */ u32 emc_rsvd_a8c;
/* 0xa8c */ u32 rsvd_a8c;
/* 0xa90 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd1_0;
/* 0xa94 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd1_1;
/* 0xa98 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd1_2;
/* 0xa9c */ u32 emc_rsvd_a9c;
/* 0xa9c */ u32 rsvd_a9c;
/* 0xaa0 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd2_0;
/* 0xaa4 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd2_1;
/* 0xaa8 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd2_2;
/* 0xaac */ u32 emc_rsvd_aac;
/* 0xaac */ u32 rsvd_aac;
/* 0xab0 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd3_0;
/* 0xab4 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd3_1;
/* 0xab8 */ u32 emc_pmacro_ib_ddll_short_dq_rank0_cmd3_2;
/* 0xabc */ u32 emc_rsvd_abc[17];
/* 0xabc */ u32 rsvd_abc[17];
/* 0xb00 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
/* 0xb04 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
/* 0xb08 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
/* 0xb0c */ u32 emc_rsvd_b0c;
/* 0xb0c */ u32 rsvd_b0c;
/* 0xb10 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
/* 0xb14 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
/* 0xb18 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
/* 0xb1c */ u32 emc_rsvd_b1c;
/* 0xb1c */ u32 rsvd_b1c;
/* 0xb20 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
/* 0xb24 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
/* 0xb28 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
/* 0xb2c */ u32 emc_rsvd_b2c;
/* 0xb2c */ u32 rsvd_b2c;
/* 0xb30 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
/* 0xb34 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
/* 0xb38 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
/* 0xb3c */ u32 emc_rsvd_b3c;
/* 0xb3c */ u32 rsvd_b3c;
/* 0xb40 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
/* 0xb44 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
/* 0xb48 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
/* 0xb4c */ u32 emc_rsvd_b4c;
/* 0xb4c */ u32 rsvd_b4c;
/* 0xb50 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
/* 0xb54 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
/* 0xb58 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
/* 0xb5c */ u32 emc_rsvd_b5c;
/* 0xb5c */ u32 rsvd_b5c;
/* 0xb60 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
/* 0xb64 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
/* 0xb68 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
/* 0xb6c */ u32 emc_rsvd_b6c;
/* 0xb6c */ u32 rsvd_b6c;
/* 0xb70 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
/* 0xb74 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
/* 0xb78 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
/* 0xb7c */ u32 emc_rsvd_b7c;
/* 0xb7c */ u32 rsvd_b7c;
/* 0xb80 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd0_0;
/* 0xb84 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd0_1;
/* 0xb88 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd0_2;
/* 0xb8c */ u32 emc_rsvd_b8c;
/* 0xb8c */ u32 rsvd_b8c;
/* 0xb90 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd1_0;
/* 0xb94 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd1_1;
/* 0xb98 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd1_2;
/* 0xb9c */ u32 emc_rsvd_b9c;
/* 0xb9c */ u32 rsvd_b9c;
/* 0xba0 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd2_0;
/* 0xba4 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd2_1;
/* 0xba8 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd2_2;
/* 0xbac */ u32 emc_rsvd_bac;
/* 0xbac */ u32 rsvd_bac;
/* 0xbb0 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd3_0;
/* 0xbb4 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd3_1;
/* 0xbb8 */ u32 emc_pmacro_ib_ddll_short_dq_rank1_cmd3_2;
/* 0xbbc */ u32 emc_rsvd_bbc[9];
/* 0xbbc */ u32 rsvd_bbc[9];
/* 0xbe0 */ u32 emc_pmacro_ib_vref_dq_0;
/* 0xbe4 */ u32 emc_pmacro_ib_vref_dq_1;
/* 0xbe8 */ u32 emc_pmacro_ib_vref_dq_2;
/* 0xbec */ u32 emc_rsvd_bec;
/* 0xbec */ u32 rsvd_bec;
/* 0xbf0 */ u32 emc_pmacro_ib_vref_dqs_0;
/* 0xbf4 */ u32 emc_pmacro_ib_vref_dqs_1;
/* 0xbf8 */ u32 emc_pmacro_ib_vref_dqs_2;
/* 0xbfc */ u32 emc_rsvd_bfc;
/* 0xbfc */ u32 rsvd_bfc;
/* 0xc00 */ u32 emc_pmacro_ddll_long_cmd_0;
/* 0xc04 */ u32 emc_pmacro_ddll_long_cmd_1;
/* 0xc08 */ u32 emc_pmacro_ddll_long_cmd_2;
/* 0xc0c */ u32 emc_pmacro_ddll_long_cmd_3;
/* 0xc10 */ u32 emc_pmacro_ddll_long_cmd_4;
/* 0xc14 */ u32 emc_pmacro_ddll_long_cmd_5;
/* 0xc18 */ u32 emc_rsvd_c18[2];
/* 0xc18 */ u32 rsvd_c18[2];
/* 0xc20 */ u32 emc_pmacro_ddll_short_cmd_0;
/* 0xc24 */ u32 emc_pmacro_ddll_short_cmd_1;
/* 0xc28 */ u32 emc_pmacro_ddll_short_cmd_2;
/* 0xc2c */ u32 emc_rsvd_c2c;
/* 0xc2c */ u32 rsvd_c2c;
/* 0xc30 */ u32 emc_pmacro_cfg_pm_global_0;
/* 0xc34 */ u32 emc_pmacro_vttgen_ctrl_0;
/* 0xc38 */ u32 emc_pmacro_vttgen_ctrl_1;
@@ -1391,7 +1391,7 @@ typedef struct _emc_regs_t210_t {
/* 0xc70 */ u32 emc_pmacro_dq_tx_drv;
/* 0xc74 */ u32 emc_pmacro_ca_tx_drv;
/* 0xc78 */ u32 emc_pmacro_autocal_cfg_common;
/* 0xc7c */ u32 emc_rsvd_c7c;
/* 0xc7c */ u32 rsvd_c7c;
/* 0xc80 */ u32 emc_pmacro_brick_mapping_0;
/* 0xc84 */ u32 emc_pmacro_brick_mapping_1;
/* 0xc88 */ u32 emc_pmacro_brick_mapping_2;
@@ -1414,11 +1414,11 @@ typedef struct _emc_regs_t210_t {
/* 0xccc */ u32 emc_stat_dram_io_sr_cke_eq0_clks_lo;
/* 0xcd0 */ u32 emc_stat_dram_io_sr_cke_eq0_clks_hi;
/* 0xcd4 */ u32 emc_stat_dram_io_dsr;
/* 0xcd8 */ u32 emc_rsvd_cd8[2];
/* 0xcd8 */ u32 rsvd_cd8[2];
/* 0xce0 */ u32 emc_pmacro_ddllcal_cal_t210;
/* 0xce4 */ u32 emc_pmacro_ddll_offset;
/* 0xce8 */ u32 emc_pmacro_ddll_periodic_offset;
/* 0xcec */ u32 emc_rsvd_cec;
/* 0xcec */ u32 rsvd_cec;
/* 0xcf0 */ u32 emc_pmacro_vttgen_ctrl_2;
/* 0xcf4 */ u32 emc_pmacro_ib_rxrt;
/* 0xcf8 */ u32 emc_pmacro_training_ctrl_0;
@@ -1429,44 +1429,44 @@ typedef struct _emc_regs_t210_t {
/* 0xd0c */ u32 emc_pmacro_ddllcal_cal_3_b01;
/* 0xd10 */ u32 emc_pmacro_ddllcal_cal_4_b01;
/* 0xd14 */ u32 emc_pmacro_ddllcal_cal_5_b01;
/* 0xd18 */ u32 emc_rsvd_d18[2];
/* 0xd18 */ u32 rsvd_d18[2];
/* 0xd20 */ u32 emc_pmacro_dig_dll_status_0_b01;
/* 0xd24 */ u32 emc_pmacro_dig_dll_status_1_b01;
/* 0xd28 */ u32 emc_pmacro_dig_dll_status_2_b01;
/* 0xd2c */ u32 emc_pmacro_dig_dll_status_3_b01;
/* 0xd30 */ u32 emc_pmacro_dig_dll_status_4_b01;
/* 0xd34 */ u32 emc_pmacro_dig_dll_status_5_b01;
/* 0xd38 */ u32 emc_rsvd_d38[2];
/* 0xd38 */ u32 rsvd_d38[2];
/* 0xd40 */ u32 emc_pmacro_perbit_fgcg_ctrl_0_b01;
/* 0xd44 */ u32 emc_pmacro_perbit_fgcg_ctrl_1_b01;
/* 0xd48 */ u32 emc_pmacro_perbit_fgcg_ctrl_2_b01;
/* 0xd4c */ u32 emc_pmacro_perbit_fgcg_ctrl_3_b01;
/* 0xd50 */ u32 emc_pmacro_perbit_fgcg_ctrl_4_b01;
/* 0xd54 */ u32 emc_pmacro_perbit_fgcg_ctrl_5_b01;
/* 0xd58 */ u32 emc_rsvd_d58[2];
/* 0xd58 */ u32 rsvd_d58[2];
/* 0xd60 */ u32 emc_pmacro_perbit_rfu_ctrl_0_b01;
/* 0xd64 */ u32 emc_pmacro_perbit_rfu_ctrl_1_b01;
/* 0xd68 */ u32 emc_pmacro_perbit_rfu_ctrl_2_b01;
/* 0xd6c */ u32 emc_pmacro_perbit_rfu_ctrl_3_b01;
/* 0xd70 */ u32 emc_pmacro_perbit_rfu_ctrl_4_b01;
/* 0xd74 */ u32 emc_pmacro_perbit_rfu_ctrl_5_b01;
/* 0xd78 */ u32 emc_rsvd_d78[2];
/* 0xd78 */ u32 rsvd_d78[2];
/* 0xd80 */ u32 emc_pmacro_perbit_rfu1_ctrl_0_b01;
/* 0xd84 */ u32 emc_pmacro_perbit_rfu1_ctrl_1_b01;
/* 0xd88 */ u32 emc_pmacro_perbit_rfu1_ctrl_2_b01;
/* 0xd8c */ u32 emc_pmacro_perbit_rfu1_ctrl_3_b01;
/* 0xd90 */ u32 emc_pmacro_perbit_rfu1_ctrl_4_b01;
/* 0xd94 */ u32 emc_pmacro_perbit_rfu1_ctrl_5_b01;
/* 0xd98 */ u32 emc_rsvd_d98[2];
/* 0xd98 */ u32 rsvd_d98[2];
/* 0xda0 */ u32 emc_pmacro_pmu_out_eoff1_0_b01;
/* 0xda4 */ u32 emc_pmacro_pmu_out_eoff1_1_b01;
/* 0xda8 */ u32 emc_pmacro_pmu_out_eoff1_2_b01;
/* 0xdac */ u32 emc_pmacro_pmu_out_eoff1_3_b01;
/* 0xdb0 */ u32 emc_pmacro_pmu_out_eoff1_4_b01;
/* 0xdb4 */ u32 emc_pmacro_pmu_out_eoff1_5_b01;
/* 0xdb8 */ u32 emc_rsvd_db8[2];
/* 0xdb8 */ u32 rsvd_db8[2];
/* 0xdc0 */ u32 emc_pmacro_comp_pmu_out_b01;
/* 0xdc4 */ u32 emc_rsvd_dc4[15];
/* 0xdc4 */ u32 rsvd_dc4[15];
/* 0xe00 */ u32 emc_training_cmd;
/* 0xe04 */ u32 emc_training_ctrl;
/* 0xe08 */ u32 emc_training_status;

162
bdk/mem/mc_t210.h
View File

@@ -113,10 +113,10 @@
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1AC
#define MC_STAT_EMC_FILTER_SET1_ASID 0x1B0
#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1B8
#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1BC
#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT_MSBS 0x1BC
#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1C0
#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1C8
#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1CC
#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT_MSBS 0x1CC
#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1D0
#define MC_SMMU_STATS_TLB_HIT_MISS_SOURCE 0x1EC
#define MC_SMMU_STATS_TLB_HIT_COUNT 0x1F0
@@ -751,7 +751,7 @@ typedef struct _mc_regs_t210_t {
/* 0x018 */ u32 mc_smmu_ptc_config;
/* 0x01c */ u32 mc_smmu_ptb_asid;
/* 0x020 */ u32 mc_smmu_ptb_data;
/* 0x024 */ u32 mc_rsvd_24[3];
/* 0x024 */ u32 rsvd_024[3];
/* 0x030 */ u32 mc_smmu_tlb_flush;
/* 0x034 */ u32 mc_smmu_ptc_flush;
/* 0x038 */ u32 mc_smmu_asid_security;
@@ -770,9 +770,9 @@ typedef struct _mc_regs_t210_t {
/* 0x06c */ u32 mc_emem_adr_cfg_bank_mask_2;
/* 0x070 */ u32 mc_security_cfg0;
/* 0x074 */ u32 mc_security_cfg1;
/* 0x078 */ u32 mc_rsvd_78;
/* 0x078 */ u32 rsvd_078;
/* 0x07c */ u32 mc_security_rsv;
/* 0x080 */ u32 mc_rsvd_80[4];
/* 0x080 */ u32 rsvd_080[4];
/* 0x090 */ u32 mc_emem_arb_cfg;
/* 0x094 */ u32 mc_emem_arb_outstanding_req;
/* 0x098 */ u32 mc_emem_arb_timing_rcd;
@@ -788,7 +788,7 @@ typedef struct _mc_regs_t210_t {
/* 0x0c0 */ u32 mc_emem_arb_timing_r2w;
/* 0x0c4 */ u32 mc_emem_arb_timing_w2r;
/* 0x0c8 */ u32 mc_emem_arb_misc2;
/* 0x0cc */ u32 mc_rsvd_cc;
/* 0x0cc */ u32 rsvd_0cc;
/* 0x0d0 */ u32 mc_emem_arb_da_turns;
/* 0x0d4 */ u32 mc_emem_arb_da_covers;
/* 0x0d8 */ u32 mc_emem_arb_misc0;
@@ -797,7 +797,7 @@ typedef struct _mc_regs_t210_t {
/* 0x0e4 */ u32 mc_emem_arb_ring3_throttle;
/* 0x0e8 */ u32 mc_emem_arb_override;
/* 0x0ec */ u32 mc_emem_arb_rsv;
/* 0x0f0 */ u32 mc_rsvd_f0;
/* 0x0f0 */ u32 rsvd_0f0;
/* 0x0f4 */ u32 mc_clken_override;
/* 0x0f8 */ u32 mc_timing_control_dbg;
/* 0x0fc */ u32 mc_timing_control;
@@ -810,7 +810,7 @@ typedef struct _mc_regs_t210_t {
/* 0x118 */ u32 mc_stat_emc_filter_set0_adr_limit_lo;
/* 0x11c */ u32 mc_stat_emc_filter_set0_adr_limit_hi;
/* 0x120 */ u32 mc_stat_emc_filter_set0_slack_limit;
/* 0x124 */ u32 mc_rsvd_124;
/* 0x124 */ u32 rsvd_124;
/* 0x128 */ u32 mc_stat_emc_filter_set0_client_0;
/* 0x12c */ u32 mc_stat_emc_filter_set0_client_1;
/* 0x130 */ u32 mc_stat_emc_filter_set0_client_2;
@@ -822,11 +822,11 @@ typedef struct _mc_regs_t210_t {
/* 0x148 */ u32 mc_stat_emc_set0_histo_count;
/* 0x14c */ u32 mc_stat_emc_set0_histo_count_msbs;
/* 0x150 */ u32 mc_stat_emc_set0_minimum_slack_observed;
/* 0x154 */ u32 mc_rsvd_154;
/* 0x154 */ u32 rsvd_154;
/* 0x158 */ u32 mc_stat_emc_filter_set1_adr_limit_lo;
/* 0x15c */ u32 mc_stat_emc_filter_set1_adr_limit_hi;
/* 0x160 */ u32 mc_stat_emc_filter_set1_slack_limit;
/* 0x164 */ u32 mc_rsvd_164;
/* 0x164 */ u32 rsvd_164;
/* 0x168 */ u32 mc_stat_emc_filter_set1_client_0;
/* 0x16c */ u32 mc_stat_emc_filter_set1_client_1;
/* 0x170 */ u32 mc_stat_emc_filter_set1_client_2;
@@ -838,23 +838,23 @@ typedef struct _mc_regs_t210_t {
/* 0x188 */ u32 mc_stat_emc_set1_histo_count;
/* 0x18c */ u32 mc_stat_emc_set1_histo_count_msbs;
/* 0x190 */ u32 mc_stat_emc_set1_minimum_slack_observed;
/* 0x194 */ u32 mc_rsvd_194;
/* 0x194 */ u32 rsvd_194;
/* 0x198 */ u32 mc_stat_emc_filter_set0_virtual_adr_limit_lo;
/* 0x19c */ u32 mc_stat_emc_filter_set0_virtual_adr_limit_hi;
/* 0x1a0 */ u32 mc_stat_emc_filter_set0_asid;
/* 0x1a4 */ u32 mc_rsvd_1a4;
/* 0x1a4 */ u32 rsvd_1a4;
/* 0x1a8 */ u32 mc_stat_emc_filter_set1_virtual_adr_limit_lo;
/* 0x1ac */ u32 mc_stat_emc_filter_set1_virtual_adr_limit_hi;
/* 0x1b0 */ u32 mc_stat_emc_filter_set1_asid;
/* 0x1b4 */ u32 mc_rsvd_1b4;
/* 0x1b4 */ u32 rsvd_1b4;
/* 0x1b8 */ u32 mc_stat_emc_set0_idle_cycle_count;
/* 0x1bc */ u32 mc_stat_emc_set0_idle_cycl_count_msbs;
/* 0x1bc */ u32 mc_stat_emc_set0_idle_cycle_count_msbs;
/* 0x1c0 */ u32 mc_stat_emc_set0_idle_cycle_partition_select;
/* 0x1c4 */ u32 mc_rsvd_1c4;
/* 0x1c4 */ u32 rsvd_1c4;
/* 0x1c8 */ u32 mc_stat_emc_set1_idle_cycle_count;
/* 0x1cc */ u32 mc_stat_emc_set1_idle_cycl_count_msbs;
/* 0x1cc */ u32 mc_stat_emc_set1_idle_cycle_count_msbs;
/* 0x1d0 */ u32 mc_stat_emc_set1_idle_cycle_partition_select;
/* 0x1d4 */ u32 mc_rsvd_1d4[6];
/* 0x1d4 */ u32 rsvd_1d4[6];
/* 0x1ec */ u32 mc_smmu_stats_tlb_hit_miss_source;
/* 0x1f0 */ u32 mc_smmu_stats_tlb_hit_count;
/* 0x1f4 */ u32 mc_smmu_stats_tlb_miss_count;
@@ -878,16 +878,16 @@ typedef struct _mc_regs_t210_t {
/* 0x23c */ u32 mc_smmu_avpc_asid;
/* 0x240 */ u32 mc_smmu_dc_asid;
/* 0x244 */ u32 mc_smmu_dcb_asid;
/* 0x248 */ u32 mc_rsvd_248[2];
/* 0x248 */ u32 rsvd_248[2];
/* 0x250 */ u32 mc_smmu_hc_asid;
/* 0x254 */ u32 mc_smmu_hda_asid;
/* 0x258 */ u32 mc_smmu_isp2_asid;
/* 0x25c */ u32 mc_rsvd_25c[2];
/* 0x25c */ u32 rsvd_25c[2];
/* 0x264 */ u32 mc_smmu_nvenc_asid;
/* 0x268 */ u32 mc_rsvd_268[2];
/* 0x268 */ u32 rsvd_268[2];
/* 0x270 */ u32 mc_smmu_ppcs_asid;
/* 0x274 */ u32 mc_smmu_sata_asid;
/* 0x278 */ u32 mc_rsvd_278[2];
/* 0x278 */ u32 rsvd_278[2];
/* 0x280 */ u32 mc_smmu_vi_asid;
/* 0x284 */ u32 mc_smmu_vic_asid;
/* 0x288 */ u32 mc_smmu_xusb_host_asid;
@@ -895,18 +895,18 @@ typedef struct _mc_regs_t210_t {
/* 0x290 */ u32 mc_smmu_a9avp_asid;
/* 0x294 */ u32 mc_smmu_tsec_asid;
/* 0x298 */ u32 mc_smmu_ppcs1_asid;
/* 0x29c */ u32 mc_rsvd_29c;
/* 0x29c */ u32 rsvd_29c;
/* 0x2a0 */ u32 mc_ahb_extra_snap_levels;
/* 0x2a4 */ u32 mc_apb_extra_snap_levels;
/* 0x2a8 */ u32 mc_avp_extra_snap_levels;
/* 0x2ac */ u32 mc_dis_extra_snap_levels;
/* 0x2b0 */ u32 mc_rsvd_2b0[2];
/* 0x2b0 */ u32 rsvd_2b0[2];
/* 0x2b8 */ u32 mc_pcx_extra_snap_levels;
/* 0x2bc */ u32 mc_ftop_extra_snap_levels;
/* 0x2c0 */ u32 mc_sax_extra_snap_levels;
/* 0x2c4 */ u32 mc_rsvd_2c4[5];
/* 0x2c4 */ u32 rsvd_2c4[5];
/* 0x2d8 */ u32 mc_ve_extra_snap_levels;
/* 0x2dc */ u32 mc_rsvd_2dc;
/* 0x2dc */ u32 rsvd_2dc;
/* 0x2e0 */ u32 mc_latency_allowance_afi_0;
/* 0x2e4 */ u32 mc_latency_allowance_avpc_0;
/* 0x2e8 */ u32 mc_latency_allowance_dc_0;
@@ -915,43 +915,43 @@ typedef struct _mc_regs_t210_t {
/* 0x2f4 */ u32 mc_latency_allowance_dcb_0;
/* 0x2f8 */ u32 mc_latency_allowance_dcb_1;
/* 0x2fc */ u32 mc_latency_allowance_dcb_2;
/* 0x300 */ u32 mc_rsvd_300[4];
/* 0x300 */ u32 rsvd_300[4];
/* 0x310 */ u32 mc_latency_allowance_hc_0;
/* 0x314 */ u32 mc_latency_allowance_hc_1;
/* 0x318 */ u32 mc_latency_allowance_hda_0;
/* 0x31c */ u32 mc_rsvd_31c;
/* 0x31c */ u32 rsvd_31c;
/* 0x320 */ u32 mc_latency_allowance_mpcore_0;
/* 0x324 */ u32 mc_rsvd_324;
/* 0x324 */ u32 rsvd_324;
/* 0x328 */ u32 mc_latency_allowance_nvenc_0;
/* 0x32c */ u32 mc_rsvd_32c[6];
/* 0x32c */ u32 rsvd_32c[6];
/* 0x344 */ u32 mc_latency_allowance_ppcs_0;
/* 0x348 */ u32 mc_latency_allowance_ppcs_1;
/* 0x34c */ u32 mc_latency_allowance_ptc_0;
/* 0x350 */ u32 mc_latency_allowance_sata_0;
/* 0x354 */ u32 mc_rsvd_354[7];
/* 0x354 */ u32 rsvd_354[7];
/* 0x370 */ u32 mc_latency_allowance_isp2_0;
/* 0x374 */ u32 mc_latency_allowance_isp2_1;
/* 0x378 */ u32 mc_rsvd_378;
/* 0x378 */ u32 rsvd_378;
/* 0x37c */ u32 mc_latency_allowance_xusb_0;
/* 0x380 */ u32 mc_latency_allowance_xusb_1;
/* 0x384 */ u32 mc_latency_allowance_isp2b_0;
/* 0x388 */ u32 mc_latency_allowance_isp2b_1;
/* 0x38c */ u32 mc_rsvd_38c;
/* 0x38c */ u32 rsvd_38c;
/* 0x390 */ u32 mc_latency_allowance_tsec_0;
/* 0x394 */ u32 mc_latency_allowance_vic_0;
/* 0x398 */ u32 mc_latency_allowance_vi2_0;
/* 0x39c */ u32 mc_rsvd_39c;
/* 0x39c */ u32 rsvd_39c;
/* 0x3a0 */ u32 mc_latency_allowance_axiap_0;
/* 0x3a4 */ u32 mc_latency_allowance_a9avp_0;
/* 0x3a8 */ u32 mc_rsvd_3a8;
/* 0x3a8 */ u32 rsvd_3a8;
/* 0x3ac */ u32 mc_latency_allowance_gpu_0;
/* 0x3b0 */ u32 mc_rsvd_3b0[2];
/* 0x3b0 */ u32 rsvd_3b0[2];
/* 0x3b8 */ u32 mc_latency_allowance_sdmmca_0;
/* 0x3bc */ u32 mc_latency_allowance_sdmmcaa_0;
/* 0x3c0 */ u32 mc_latency_allowance_sdmmc_0;
/* 0x3c4 */ u32 mc_latency_allowance_sdmmcab_0;
/* 0x3c8 */ u32 mc_latency_allowance_dc_3;
/* 0x3cc */ u32 mc_rsvd_3cc[3];
/* 0x3cc */ u32 rsvd_3cc[3];
/* 0x3d8 */ u32 mc_latency_allowance_nvdec_0;
/* 0x3dc */ u32 mc_latency_allowance_ape_0;
/* 0x3e0 */ u32 mc_latency_allowance_se_0;
@@ -959,9 +959,9 @@ typedef struct _mc_regs_t210_t {
/* 0x3e8 */ u32 mc_latency_allowance_gpu2_0;
/* 0x3ec */ u32 mc_latency_allowance_etr_0;
/* 0x3f0 */ u32 mc_latency_allowance_tsecb_0;
/* 0x3f4 */ u32 mc_rsvd_3f4[2];
/* 0x3f4 */ u32 rsvd_3f4[2];
/* 0x3fc */ u32 mc_reserved_rsv;
/* 0x400 */ u32 mc_rsvd_400;
/* 0x400 */ u32 rsvd_400;
/* 0x404 */ u32 mc_usbx_extra_snap_levels;
/* 0x408 */ u32 mc_disb_extra_snap_levels;
/* 0x40c */ u32 mc_mse_extra_snap_levels;
@@ -986,7 +986,7 @@ typedef struct _mc_regs_t210_t {
/* 0x458 */ u32 mc_smmu_smmu_ptsa_rate;
/* 0x45c */ u32 mc_smmu_smmu_ptsa_min;
/* 0x460 */ u32 mc_smmu_smmu_ptsa_max;
/* 0x464 */ u32 mc_rsvd_464[6];
/* 0x464 */ u32 rsvd_464[6];
/* 0x47c */ u32 mc_ring1_ptsa_rate;
/* 0x480 */ u32 mc_ring1_ptsa_min;
/* 0x484 */ u32 mc_ring1_ptsa_max;
@@ -1020,7 +1020,7 @@ typedef struct _mc_regs_t210_t {
/* 0x4f4 */ u32 mc_avp_ptsa_rate;
/* 0x4f8 */ u32 mc_avp_ptsa_min;
/* 0x4fc */ u32 mc_avp_ptsa_max;
/* 0x500 */ u32 mc_rsvd_500[3];
/* 0x500 */ u32 rsvd_500[3];
/* 0x50c */ u32 mc_ftop_ptsa_rate;
/* 0x510 */ u32 mc_ftop_ptsa_min;
/* 0x514 */ u32 mc_ftop_ptsa_max;
@@ -1042,14 +1042,14 @@ typedef struct _mc_regs_t210_t {
/* 0x554 */ u32 mc_vicpc_ptsa_rate;
/* 0x558 */ u32 mc_vicpc_ptsa_min;
/* 0x55c */ u32 mc_vicpc_ptsa_max;
/* 0x560 */ u32 mc_rsvd_560[9];
/* 0x560 */ u32 rsvd_560[9];
/* 0x584 */ u32 mc_jpg_ptsa_rate;
/* 0x588 */ u32 mc_jpg_ptsa_min;
/* 0x58c */ u32 mc_jpg_ptsa_max;
/* 0x590 */ u32 mc_video_protect_vpr_override1;
/* 0x594 */ u32 mc_rsvd_594[27];
/* 0x594 */ u32 rsvd_594[27];
/* 0x600 */ u32 mc_smmu_tlb_set_selection_mask_0;
/* 0x604 */ u32 mc_rsvd_604[3];
/* 0x604 */ u32 rsvd_604[3];
/* 0x610 */ u32 mc_gk2_ptsa_rate;
/* 0x614 */ u32 mc_gk2_ptsa_min;
/* 0x618 */ u32 mc_gk2_ptsa_max;
@@ -1062,7 +1062,7 @@ typedef struct _mc_regs_t210_t {
/* 0x634 */ u32 mc_dfd_ptsa_rate;
/* 0x638 */ u32 mc_dfd_ptsa_min;
/* 0x63c */ u32 mc_dfd_ptsa_max;
/* 0x640 */ u32 mc_rsvd_640[2];
/* 0x640 */ u32 rsvd_640[2];
/* 0x648 */ u32 mc_video_protect_bom;
/* 0x64c */ u32 mc_video_protect_size_mb;
/* 0x650 */ u32 mc_video_protect_reg_ctrl;
@@ -1080,27 +1080,27 @@ typedef struct _mc_regs_t210_t {
/* 0x680 */ u32 mc_err_sec_adr;
/* 0x684 */ u32 mc_pc_idle_clock_gate_config;
/* 0x688 */ u32 mc_stutter_control;
/* 0x68c */ u32 mc_rsvd_68c;
/* 0x68c */ u32 rsvd_68c;
/* 0x690 */ u32 mc_scaled_latency_allowance_display0a;
/* 0x694 */ u32 mc_scaled_latency_allowance_display0ab;
/* 0x698 */ u32 mc_scaled_latency_allowance_display0b;
/* 0x69c */ u32 mc_scaled_latency_allowance_display0bb;
/* 0x6a0 */ u32 mc_scaled_latency_allowance_display0c;
/* 0x6a4 */ u32 mc_scaled_latency_allowance_display0cb;
/* 0x6a8 */ u32 mc_rsvd_6a8[2];
/* 0x6a8 */ u32 rsvd_6a8[2];
/* 0x6b0 */ u32 mc_emem_arb_niso_throttle;
/* 0x6b4 */ u32 mc_emem_arb_outstanding_req_niso;
/* 0x6b8 */ u32 mc_emem_arb_niso_throttle_mask;
/* 0x6bc */ u32 mc_emem_arb_ring0_throttle_mask;
/* 0x6c0 */ u32 mc_emem_arb_timing_rfcpb;
/* 0x6c4 */ u32 mc_emem_arb_timing_ccdmw;
/* 0x6c8 */ u32 mc_rsvd_6c8[10];
/* 0x6c8 */ u32 rsvd_6c8[10];
/* 0x6f0 */ u32 mc_emem_arb_refpb_hp_ctrl;
/* 0x6f4 */ u32 mc_emem_arb_refpb_bank_ctrl;
/* 0x6f8 */ u32 mc_rsvd_6f8[67];
/* 0x6f8 */ u32 rsvd_6f8[67];
/* 0x804 */ u32 mc_smmu_isp21_asid_b01;
/* 0x808 */ u32 mc_smmu_isp2b1_asid_b01;
/* 0x80c */ u32 mc_rsvd_80c[32];
/* 0x80c */ u32 rsvd_80c[32];
/* 0x88c */ u32 mc_min_length_afi_0;
/* 0x890 */ u32 mc_min_length_avpc_0;
/* 0x894 */ u32 mc_min_length_dc_0;
@@ -1109,52 +1109,52 @@ typedef struct _mc_regs_t210_t {
/* 0x8a0 */ u32 mc_min_length_dcb_0;
/* 0x8a4 */ u32 mc_min_length_dcb_1;
/* 0x8a8 */ u32 mc_min_length_dcb_2;
/* 0x8ac */ u32 mc_rsvd_8ac[4];
/* 0x8ac */ u32 rsvd_8ac[4];
/* 0x8bc */ u32 mc_min_length_hc_0;
/* 0x8c0 */ u32 mc_min_length_hc_1;
/* 0x8c4 */ u32 mc_min_length_hda_0;
/* 0x8c8 */ u32 mc_rsvd_8c8;
/* 0x8c8 */ u32 rsvd_8c8;
/* 0x8cc */ u32 mc_min_length_mpcore_0;
/* 0x8d0 */ u32 mc_rsvd_8d0;
/* 0x8d0 */ u32 rsvd_8d0;
/* 0x8d4 */ u32 mc_min_length_nvenc_0;
/* 0x8d8 */ u32 mc_rsvd_8d8[6];
/* 0x8d8 */ u32 rsvd_8d8[6];
/* 0x8f0 */ u32 mc_min_length_ppcs_0;
/* 0x8f4 */ u32 mc_min_length_ppcs_1;
/* 0x8f8 */ u32 mc_min_length_ptc_0;
/* 0x8fc */ u32 mc_min_length_sata_0;
/* 0x900 */ u32 mc_rsvd_900[7];
/* 0x900 */ u32 rsvd_900[7];
/* 0x91c */ u32 mc_min_length_isp2_0;
/* 0x920 */ u32 mc_min_length_isp2_1;
/* 0x924 */ u32 mc_rsvd_924;
/* 0x924 */ u32 rsvd_924;
/* 0x928 */ u32 mc_min_length_xusb_0;
/* 0x92c */ u32 mc_min_length_xusb_1;
/* 0x930 */ u32 mc_min_length_isp2b_0;
/* 0x934 */ u32 mc_min_length_isp2b_1;
/* 0x938 */ u32 mc_rsvd_938;
/* 0x938 */ u32 rsvd_938;
/* 0x93c */ u32 mc_min_length_tsec_0;
/* 0x940 */ u32 mc_min_length_vic_0;
/* 0x944 */ u32 mc_min_length_vi2_0;
/* 0x948 */ u32 mc_untranslated_region_check_b01;
/* 0x94c */ u32 mc_min_length_axiap_0;
/* 0x950 */ u32 mc_min_length_a9avp_0;
/* 0x954 */ u32 mc_rsvd_954;
/* 0x954 */ u32 rsvd_954;
/* 0x958 */ u32 mc_reserved_rsv_1;
/* 0x95c */ u32 mc_dvfs_pipe_select;
/* 0x960 */ u32 mc_ptsa_grant_decrement;
/* 0x964 */ u32 mc_iram_reg_ctrl;
/* 0x968 */ u32 mc_emem_arb_override_1;
/* 0x96c */ u32 mc_rsvd_96c;
/* 0x96c */ u32 rsvd_96c;
/* 0x970 */ u32 mc_client_hotreset_ctrl_1;
/* 0x974 */ u32 mc_client_hotreset_status_1;
/* 0x978 */ u32 mc_video_protect_bom_adr_hi;
/* 0x97c */ u32 mc_rsvd_97c;
/* 0x97c */ u32 rsvd_97c;
/* 0x980 */ u32 mc_iram_adr_hi;
/* 0x984 */ u32 mc_video_protect_gpu_override_0;
/* 0x988 */ u32 mc_video_protect_gpu_override_1;
/* 0x98c */ u32 mc_rsvd_98c;
/* 0x98c */ u32 rsvd_98c;
/* 0x990 */ u32 mc_emem_arb_stats_0;
/* 0x994 */ u32 mc_emem_arb_stats_1;
/* 0x998 */ u32 mc_rsvd_998[2];
/* 0x998 */ u32 rsvd_998[2];
/* 0x9a0 */ u32 mc_mts_carveout_bom;
/* 0x9a4 */ u32 mc_mts_carveout_size_mb;
/* 0x9a8 */ u32 mc_mts_carveout_adr_hi;
@@ -1163,10 +1163,10 @@ typedef struct _mc_regs_t210_t {
/* 0x9b4 */ u32 mc_err_mts_adr;
/* 0x9b8 */ u32 mc_smmu_ptc_flush_1;
/* 0x9bc */ u32 mc_security_cfg3;
/* 0x9c0 */ u32 mc_rsvd_9c0[4];
/* 0x9c0 */ u32 rsvd_9c0[4];
/* 0x9d0 */ u32 mc_err_apb_asid_update_status;
/* 0x9d4 */ u32 mc_sec_carveout_adr_hi;
/* 0x9d8 */ u32 mc_rsvd_9d8;
/* 0x9d8 */ u32 rsvd_9d8;
/* 0x9dc */ u32 mc_da_config0;
/* 0x9e0 */ u32 mc_smmu_asid_security_2;
/* 0x9e4 */ u32 mc_smmu_asid_security_3;
@@ -1174,11 +1174,11 @@ typedef struct _mc_regs_t210_t {
/* 0x9ec */ u32 mc_smmu_asid_security_5;
/* 0x9f0 */ u32 mc_smmu_asid_security_6;
/* 0x9f4 */ u32 mc_smmu_asid_security_7;
/* 0x9f8 */ u32 mc_rsvd_9f8[2];
/* 0x9f8 */ u32 rsvd_9f8[2];
/* 0xa00 */ u32 mc_gk_extra_snap_levels;
/* 0xa04 */ u32 mc_sd_extra_snap_levels;
/* 0xa08 */ u32 mc_isp_extra_snap_levels;
/* 0xa0c */ u32 mc_rsvd_a0c;
/* 0xa0c */ u32 rsvd_a0c;
/* 0xa10 */ u32 mc_aud_extra_snap_levels;
/* 0xa14 */ u32 mc_host_extra_snap_levels;
/* 0xa18 */ u32 mc_usbd_extra_snap_levels;
@@ -1187,15 +1187,15 @@ typedef struct _mc_regs_t210_t {
/* 0xa24 */ u32 mc_stat_emc_filter_set1_adr_limit_upper;
/* 0xa28 */ u32 mc_stat_emc_filter_set0_virtual_adr_limit_upper;
/* 0xa2c */ u32 mc_stat_emc_filter_set1_virtual_adr_limit_upper;
/* 0xa30 */ u32 mc_rsvd_a30[3];
/* 0xa30 */ u32 rsvd_a30[3];
/* 0xa3c */ u32 mc_jpg_extra_snap_levels;
/* 0xa40 */ u32 mc_gk2_extra_snap_levels;
/* 0xa44 */ u32 mc_sdm_extra_snap_levels;
/* 0xa48 */ u32 mc_hdapc_extra_snap_levels;
/* 0xa4c */ u32 mc_dfd_extra_snap_levels;
/* 0xa50 */ u32 mc_rsvd_a50[14];
/* 0xa50 */ u32 rsvd_a50[14];
/* 0xa88 */ u32 mc_smmu_dc1_asid;
/* 0xa8c */ u32 mc_rsvd_a8c[2];
/* 0xa8c */ u32 rsvd_a8c[2];
/* 0xa94 */ u32 mc_smmu_sdmmc1a_asid;
/* 0xa98 */ u32 mc_smmu_sdmmc2a_asid;
/* 0xa9c */ u32 mc_smmu_sdmmc3a_asid;
@@ -1216,15 +1216,15 @@ typedef struct _mc_regs_t210_t {
/* 0xad8 */ u32 mc_smmu_tsec1_asid;
/* 0xadc */ u32 mc_smmu_tsecb1_asid;
/* 0xae0 */ u32 mc_smmu_nvdec1_asid;
/* 0xae4 */ u32 mc_rsvd_ae4[8];
/* 0xae4 */ u32 rsvd_ae4[8];
/* 0xb04 */ u32 mc_min_length_gpu_0;
/* 0xb08 */ u32 mc_rsvd_b08[2];
/* 0xb08 */ u32 rsvd_b08[2];
/* 0xb10 */ u32 mc_min_length_sdmmca_0;
/* 0xb14 */ u32 mc_min_length_sdmmcaa_0;
/* 0xb18 */ u32 mc_min_length_sdmmc_0;
/* 0xb1c */ u32 mc_min_length_sdmmcab_0;
/* 0xb20 */ u32 mc_min_length_dc_3;
/* 0xb24 */ u32 mc_rsvd_b24[3];
/* 0xb24 */ u32 rsvd_b24[3];
/* 0xb30 */ u32 mc_min_length_nvdec_0;
/* 0xb34 */ u32 mc_min_length_ape_0;
/* 0xb38 */ u32 mc_min_length_se_0;
@@ -1232,22 +1232,22 @@ typedef struct _mc_regs_t210_t {
/* 0xb40 */ u32 mc_min_length_gpu2_0;
/* 0xb44 */ u32 mc_min_length_etr_0;
/* 0xb48 */ u32 mc_min_length_tsecb_0;
/* 0xb4c */ u32 mc_rsvd_b4c[13];
/* 0xb4c */ u32 rsvd_b4c[13];
/* 0xb80 */ u32 mc_emem_arb_niso_throttle_mask_1;
/* 0xb84 */ u32 mc_emem_arb_hysteresis_4;
/* 0xb88 */ u32 mc_stat_emc_filter_set0_client_4;
/* 0xb8c */ u32 mc_stat_emc_filter_set1_client_4;
/* 0xb90 */ u32 mc_rsvd_b90;
/* 0xb90 */ u32 rsvd_b90;
/* 0xb94 */ u32 mc_emem_arb_isochronous_4;
/* 0xb98 */ u32 mc_smmu_translation_enable_4;
/* 0xb9c */ u32 mc_smmu_client_config4;
/* 0xba0 */ u32 mc_rsvd_ba0[4];
/* 0xba0 */ u32 rsvd_ba0[4];
/* 0xbb0 */ u32 mc_emem_arb_dhysteresis_0;
/* 0xbb4 */ u32 mc_emem_arb_dhysteresis_1;
/* 0xbb8 */ u32 mc_emem_arb_dhysteresis_2;
/* 0xbbc */ u32 mc_emem_arb_dhysteresis_3;
/* 0xbc0 */ u32 mc_emem_arb_dhysteresis_4;
/* 0xbc4 */ u32 mc_rsvd_bc4[2];
/* 0xbc4 */ u32 rsvd_bc4[2];
/* 0xbcc */ u32 mc_emem_arb_dhyst_ctrl;
/* 0xbd0 */ u32 mc_emem_arb_dhyst_timeout_util_0;
/* 0xbd4 */ u32 mc_emem_arb_dhyst_timeout_util_1;
@@ -1257,7 +1257,7 @@ typedef struct _mc_regs_t210_t {
/* 0xbe4 */ u32 mc_emem_arb_dhyst_timeout_util_5;
/* 0xbe8 */ u32 mc_emem_arb_dhyst_timeout_util_6;
/* 0xbec */ u32 mc_emem_arb_dhyst_timeout_util_7;
/* 0xbf0 */ u32 mc_rsvd_bf0[4];
/* 0xbf0 */ u32 rsvd_bf0[4];
/* 0xc00 */ u32 mc_err_generalized_carveout_status;
/* 0xc04 */ u32 mc_err_generalized_carveout_adr;
/* 0xc08 */ u32 mc_security_carveout1_cfg0;
@@ -1274,7 +1274,7 @@ typedef struct _mc_regs_t210_t {
/* 0xc34 */ u32 mc_security_carveout1_client_force_internal_access2;
/* 0xc38 */ u32 mc_security_carveout1_client_force_internal_access3;
/* 0xc3c */ u32 mc_security_carveout1_client_force_internal_access4;
/* 0xc40 */ u32 mc_rsvd_c40[6];
/* 0xc40 */ u32 rsvd_c40[6];
/* 0xc58 */ u32 mc_security_carveout2_cfg0;
/* 0xc5c */ u32 mc_security_carveout2_bom;
/* 0xc60 */ u32 mc_security_carveout2_bom_hi;
@@ -1289,7 +1289,7 @@ typedef struct _mc_regs_t210_t {
/* 0xc84 */ u32 mc_security_carveout2_client_force_internal_access2;
/* 0xc88 */ u32 mc_security_carveout2_client_force_internal_access3;
/* 0xc8c */ u32 mc_security_carveout2_client_force_internal_access4;
/* 0xc90 */ u32 mc_rsvd_c90[6];
/* 0xc90 */ u32 rsvd_c90[6];
/* 0xca8 */ u32 mc_security_carveout3_cfg0;
/* 0xcac */ u32 mc_security_carveout3_bom;
/* 0xcb0 */ u32 mc_security_carveout3_bom_hi;
@@ -1304,7 +1304,7 @@ typedef struct _mc_regs_t210_t {
/* 0xcd4 */ u32 mc_security_carveout3_client_force_internal_access2;
/* 0xcd8 */ u32 mc_security_carveout3_client_force_internal_access3;
/* 0xcdc */ u32 mc_security_carveout3_client_force_internal_access4;
/* 0xce0 */ u32 mc_rsvd_ce0[6];
/* 0xce0 */ u32 rsvd_ce0[6];
/* 0xcf8 */ u32 mc_security_carveout4_cfg0;
/* 0xcfc */ u32 mc_security_carveout4_bom;
/* 0xd00 */ u32 mc_security_carveout4_bom_hi;
@@ -1319,7 +1319,7 @@ typedef struct _mc_regs_t210_t {
/* 0xd24 */ u32 mc_security_carveout4_client_force_internal_access2;
/* 0xd28 */ u32 mc_security_carveout4_client_force_internal_access3;
/* 0xd2c */ u32 mc_security_carveout4_client_force_internal_access4;
/* 0xd30 */ u32 mc_rsvd_d30[6];
/* 0xd30 */ u32 rsvd_d30[6];
/* 0xd48 */ u32 mc_security_carveout5_cfg0;
/* 0xd4c */ u32 mc_security_carveout5_bom;
/* 0xd50 */ u32 mc_security_carveout5_bom_hi;
@@ -1334,7 +1334,7 @@ typedef struct _mc_regs_t210_t {
/* 0xd74 */ u32 mc_security_carveout5_client_force_internal_access2;
/* 0xd78 */ u32 mc_security_carveout5_client_force_internal_access3;
/* 0xd7c */ u32 mc_security_carveout5_client_force_internal_access4;
/* 0xd80 */ u32 mc_rsvd_d80[20];
/* 0xd80 */ u32 rsvd_d80[20];
/* 0xdd0 */ u32 mc_pcfifo_client_config0;
/* 0xdd4 */ u32 mc_pcfifo_client_config1;
/* 0xdd8 */ u32 mc_pcfifo_client_config2;