155 lines
5.6 KiB
C
155 lines
5.6 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2025 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <memory_map.h>
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#include <mem/mc.h>
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#include <soc/bpmp.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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#include <soc/clock.h>
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#define HOS_WPR1_BASE 0x80020000
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void mc_config_carveout_hos()
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{
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// Enable ACR GSR3 and flush data to ram.
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*(u32 *)(HOS_WPR1_BASE + SZ_256K - sizeof(u32)) = ACR_GSC3_ENABLE_MAGIC;
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false);
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// Set VPR CYA TRUSTED DEFAULT.
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MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = VPR_OVR0_CYA_TRUST_DEFAULT;
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MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
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// Disable VPR carveout.
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MC(MC_VIDEO_PROTECT_BOM) = 0;
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MC(MC_VIDEO_PROTECT_SIZE_MB) = 0;
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MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_LOCKED;
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// Disable TZDRAM carveout.
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MC(MC_SEC_CARVEOUT_BOM) = 0;
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MC(MC_SEC_CARVEOUT_SIZE_MB) = 0;
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MC(MC_SEC_CARVEOUT_REG_CTRL) = BIT(0);
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// Disable CPU FW carveout.
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MC(MC_MTS_CARVEOUT_BOM) = 0;
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MC(MC_MTS_CARVEOUT_SIZE_MB) = 0;
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MC(MC_MTS_CARVEOUT_REG_CTRL) = BIT(0);
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// Disable GEN1 carveout.
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MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_LOCKED |
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SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
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SEC_CARVEOUT_CFG_APERTURE_ID(0) |
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SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;
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// Enable GEN2 carveout as WPR1.
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MC(MC_SECURITY_CARVEOUT2_BOM) = HOS_WPR1_BASE;
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MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = SZ_256K / SZ_128K;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU | SEC_CARVEOUT_CA2_W_GPU | SEC_CARVEOUT_CA2_R_TSEC;
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MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2;
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MC(MC_SECURITY_CARVEOUT2_CFG0) = SEC_CARVEOUT_CFG_LOCKED |
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SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
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SEC_CARVEOUT_CFG_RD_NS |
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SEC_CARVEOUT_CFG_RD_SEC |
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SEC_CARVEOUT_CFG_RD_FALCON_LS |
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SEC_CARVEOUT_CFG_RD_FALCON_HS |
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SEC_CARVEOUT_CFG_WR_FALCON_LS |
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SEC_CARVEOUT_CFG_WR_FALCON_HS |
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SEC_CARVEOUT_CFG_APERTURE_ID(2) |
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SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU |
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SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;
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// Prepare GEN3 carveout as WPR2.
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MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU | SEC_CARVEOUT_CA2_W_GPU;
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MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2;
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MC(MC_SECURITY_CARVEOUT3_CFG0) = SEC_CARVEOUT_CFG_LOCKED |
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SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
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SEC_CARVEOUT_CFG_RD_NS |
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SEC_CARVEOUT_CFG_RD_SEC |
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SEC_CARVEOUT_CFG_RD_FALCON_LS |
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SEC_CARVEOUT_CFG_RD_FALCON_HS |
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SEC_CARVEOUT_CFG_WR_FALCON_LS |
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SEC_CARVEOUT_CFG_WR_FALCON_HS |
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SEC_CARVEOUT_CFG_APERTURE_ID(3) |
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SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU |
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SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;
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// Disable GEN4 carveout.
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MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE |
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SEC_CARVEOUT_CFG_LOCKED |
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SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
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SEC_CARVEOUT_CFG_RD_NS |
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SEC_CARVEOUT_CFG_WR_NS;
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// Disable GEN5 carveout.
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MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
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MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE |
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SEC_CARVEOUT_CFG_LOCKED |
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SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
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SEC_CARVEOUT_CFG_RD_NS |
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SEC_CARVEOUT_CFG_WR_NS;
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}
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// SDMMC, TSEC, XUSB and probably more need it to access < DRAM_START.
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void mc_enable_ahb_redirect(u32 offset)
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{
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// Bypass ARC clock gating.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19);
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//MC(MC_IRAM_REG_CTRL) &= ~BIT(0);
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MC(MC_IRAM_BOM) = IRAM_BASE;
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MC(MC_IRAM_TOM) = DRAM_START - offset; // Default is only IRAM: 0x4003F000.
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}
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void mc_disable_ahb_redirect()
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{
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MC(MC_IRAM_BOM) = 0xFFFFF000;
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MC(MC_IRAM_TOM) = 0;
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// Disable IRAM_CFG_WRITE_ACCESS (sticky).
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//MC(MC_IRAM_REG_CTRL) |= BIT(0);
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// Set ARC clock gating to automatic.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= ~BIT(19);
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}
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bool mc_client_has_access(void *address)
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{
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// Check if address is in DRAM or if arbitration for IRAM is enabled.
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if ((u32)address >= DRAM_START)
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return true; // Access by default.
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else if ((u32)address >= IRAM_BASE && MC(MC_IRAM_BOM) == IRAM_BASE)
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return true; // Access by AHB arbitration.
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// No access to address space.
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return false;
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}
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void mc_enable()
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{
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// Reset EMC source to PLLP.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29u);
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// Enable and clear reset for memory clocks.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
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usleep(5);
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// Enable redirection by default.
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mc_enable_ahb_redirect(1);
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}
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