Files
hekate/bdk/sec/se.c
CTCaer 68281d3051 bdk: se: adjust T210 silicon errata coherency WAR
Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).
2026-01-15 19:02:36 +02:00

21 KiB