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Author SHA1 Message Date
CTCaer
ae7c5fdfdb bdk: heap: add more safe guards 
- Use magic for used regions
- Deduplicate calloc
Enable a print/abort in _heap_free() for debugging.
 2025-12-25 12:33:41 +02:00
CTCaer
a7ad3d4984 bdk: display: improve and deduplicate more 
- Add delay after a DSI soft reset
- Remove more duplicated configs
- Improve code to save code size
- Improve comments
- Do not allow display_backlight to be used with OLED
 2025-12-25 11:36:06 +02:00
CTCaer
67140d026c bdk: util: use volatile base for reg_write_array 2025-12-18 11:50:00 +02:00
CTCaer
998053f8db bdk: display: use a scratch reg for backlight 
Spare registers normally have hidden hw config usage, so avoid them just in case.
 2025-12-18 11:48:53 +02:00
CTCaer
b5a6c8eb64 bdk: display: simplify macros 
Expand register index in parent macro and remove _DI/_DSIREG macros.
 2025-12-18 11:17:43 +02:00
CTCaer
8faa1a6690 bdk: display: use spare reg to store dcs bl duty 
And also remove backlight pwm restoring from coreboot hw deinit path.
 2025-12-18 09:54:26 +02:00
CTCaer
ba95bb7494 bdk: fatfs: improve fat read/write 
- Convert access from min cluster size to block size
  Also allow read/writes to less than cluster size
- In case of intercluster access throw an error
- Do not error on zero size

On reads buffer still needs to be block (instead of cluster) aligned.
On writes, buffer still needs to be readable out of bounds.
 2025-12-17 07:11:51 +02:00
CTCaer
b90935ac16 nyx: info: update 20nm wafer bounds 2025-12-17 06:54:57 +02:00
CTCaer
c78b94b0ac nyx: info: unlocked T210B01 fuses dumping support 2025-12-17 06:51:04 +02:00
CTCaer
20a50988c5 bdk: fuse: return array size with fuse_read_array 2025-12-17 06:41:52 +02:00
CTCaer
ac60695b24 nyx: parted: remove invisible btns in eMMC mode 2025-12-17 06:34:42 +02:00
CTCaer
468544ce1e nyx: add a small stall in lvgl loop 
EMC CC should not run in less than 20us.
 2025-12-17 06:33:05 +02:00
CTCaer
73d96b7ca8 hos/l4t: deduplicate sc7exit-b01 load 
And remove obsolete MWS (L4T one deprecated it 3 years ago).
 2025-12-17 06:28:36 +02:00
CTCaer
4af4692710 hos: reflect minerva changes 2025-12-17 06:07:58 +02:00
CTCaer
4229a43818 lp0 cfg: use a more appropriate entry name 2025-12-17 06:00:02 +02:00
CTCaer
b6ec6a8f6e minerva: update tov1.6_T210/v0.1_T21X 
T21X v0.1:
- Add IRB/no table support
T210 v1.6/Common:
- Add a proper table for 8GB T210 config instead of editing a 4GB one
- Increase timeout to 2ms
- Generally improve checks and guard against unknown SoCs/SKUs
- Remove the long ago obsolete OVERCLOCK_FREQ/OVERCLOCK_VOLTAGE ifdefs
 2025-12-17 05:58:09 +02:00
CTCaer
0db758592a bdk: minerva: add IRB support 
Aka no table support.
 2025-12-17 05:24:16 +02:00
CTCaer
8b4d5507f6 hekate: gfx: correct a very very very old typo 2025-12-17 04:48:37 +02:00
CTCaer
c584242873 hekate: exo: simplify fatal screen to save space 
And remove an obsolete message.
 2025-12-17 04:45:20 +02:00
CTCaer
3f75917c8b hekate: remove precise free clusters calc in TUI 2025-12-17 04:37:36 +02:00
CTCaer
8d6bb5f427 bdk: clock: update some defines 2025-12-17 04:33:40 +02:00
CTCaer
4797b42e76 bdk: sdmmc: add defines for max block number 2025-12-17 04:30:12 +02:00
CTCaer
6207a783d7 Bump hekate to v6.4.2 and Nyx to v1.8.2 2025-12-02 12:59:51 +02:00
CTCaer
768824df33 nyx: options: add month/date checks for roller 
Now the roller will return back automatically if day can't be set for selected month.
Additionally, fix the check when saving.
 2025-12-01 14:19:03 +02:00
CTCaer
03a9c2d75c nyx: info: add wafer graph with die x/y placement 2025-12-01 14:16:26 +02:00
CTCaer
84bf634e33 nyx: info: streamline hw info from fuses 
- Compact and group relevant values together
- Use actual value name instead of register name where possible
- Fix LOT code masking
- Fully parse and show LOT code (it's the same marking on die)
- Correct X coordinate parsing (9bit 2s complement)
- Add product code
 2025-12-01 14:15:18 +02:00
CTCaer
86871bea7d hekate: write rsvd cfg to update.bin if different 2025-12-01 13:53:34 +02:00
CTCaer
98960a72d8 nyx: do init always with lowest clock boost 2025-11-27 12:38:52 +02:00
CTCaer
6cf7c645df nyx: fix bt pairing dumping 2025-11-27 12:37:36 +02:00
CTCaer
5775b3c47e nyx: info: add forced 8GB ram info 2025-11-27 12:36:20 +02:00
CTCaer
7c212358ed hekate: show errors before parsing R2C 2025-11-27 12:30:51 +02:00
CTCaer
e5566c0a46 hekate: add force 8GB ram config mode 2025-11-27 12:29:16 +02:00
CTCaer
dcf8e76441 loader/hekate/nyx: utilize the new rsvd cfg 2025-11-27 12:28:19 +02:00
CTCaer
7cbefa3061 bdk: add reserved cfg to ipl meta and nyx storage 2025-11-27 12:17:33 +02:00
CTCaer
5176ce4394 bdk: sdmmc: correct drive ohms comment 2025-11-27 12:14:43 +02:00
CTCaer
a6d4e5adaa bdk: clock: add i2c to the errata affected list 2025-11-27 12:12:13 +02:00
CTCaer
4a24956f3a bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2025-11-27 12:04:12 +02:00
CTCaer
364465399e hekate/nyx: use minerva storage and panel id 2025-11-27 11:28:26 +02:00
CTCaer
727d37c991 bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2025-11-27 11:25:08 +02:00
CTCaer
1fc92cfa33 bdk: nyx: rename disp_id to panel_id 2025-11-27 11:21:06 +02:00
CTCaer
62163f3255 bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2025-11-27 11:20:19 +02:00
CTCaer
fc71e405d2 bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2025-11-27 11:13:54 +02:00
CTCaer
e7783f0bd7 bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2025-11-26 16:53:19 +02:00
CTCaer
e50ad58d61 bdk: clock: add sdmmc1 to the errata affected list 2025-11-26 16:47:29 +02:00
CTCaer
0a63fa19a3 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2025-11-26 16:46:11 +02:00
CTCaer
19285745b5 bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2025-11-26 14:48:47 +02:00
CTCaer
9c028cd94a bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2025-11-26 14:37:14 +02:00
CTCaer
a2ea3fb08e bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2025-11-26 14:33:56 +02:00
CTCaer
50ac32fd40 Bump hekate to v6.4.1 and Nyx to v1.8.1 2025-11-16 22:11:31 +02:00
CTCaer
43dec3021f nyx: info: add hos version for 22 fuses burnt 2025-11-16 21:54:03 +02:00