OmniNX/hekate
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316650dda667d1d5a00db9cfe5142d3bd854fef1
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575 Commits

Author SHA1 Message Date
CTCaer
316650dda6 bdk: display: add OLED status pin 
Code is commented out for now until it gets used.
Status is set when RST is enabled.
 2026-01-06 23:10:42 +02:00
CTCaer
afa9715cf4 bdk: se: support multiple/partial blocks for RNG 2026-01-06 23:02:33 +02:00
CTCaer
1696dd8ebf bdk: se: use proper naming for ctx keys 2026-01-06 23:00:46 +02:00
CTCaer
c9208593af bdk: se: refactor and optimize SHA256 
- Simplify config and fix partial hashing
- Add partial function calls
- All partial state is handled internally
- All functions now use the classic naming convention.
 2026-01-06 22:59:20 +02:00
CTCaer
607b19067a bdk: se: use classic naming convention for XTS 2026-01-06 22:52:21 +02:00
CTCaer
b7f1641bce bdk: se: add AES OFB encryption/decryption support 2026-01-06 22:49:57 +02:00
CTCaer
2fa1a6a4af bdk: se: remove dst/src size argument requirement 
All operations expect the destination buffer to fit the selected size.
And for simplicity STATE_WAIT is not supported.

Additionally, remove single block ECB and just use the normal function.
 2026-01-06 22:47:54 +02:00
CTCaer
3463623126 bdk: se: optimize and update aes cmac hashing 
`se_aes_cmac_128` was also renamed to `se_aes_hash_cmac`.
By following the convention of 128bit functions not having size in their name.
 2026-01-06 22:32:26 +02:00
CTCaer
b4ca6cae21 bdk: se: handle original and updated IV in one go 
IV set now requires a size where the second block is updated IV
IV clear now clears both.
 2026-01-06 22:28:18 +02:00
CTCaer
d442390e9b bdk: se: support partial blocks for all aes modes 2026-01-06 22:23:25 +02:00
CTCaer
ca307e78c8 bdk: se: do a trivial refactor pass 2026-01-06 22:18:45 +02:00
CTCaer
13c91d2848 bdk: heap: use ultra fast defragmentation 
The defragmentation runs on every free and it only merges subsequent nodes.
So there's no point of looping all nodes.
So, just check if previous and next nodes are mergeable.
This makes free performant and achieves the same exact functionality.
 2026-01-05 12:33:31 +02:00
CTCaer
800bec2ec2 bdk: max17050: simplify calculations 
And make current readings a tiny bit (±0.16%) more accurate.
 2025-12-31 03:44:44 +02:00
CTCaer
067c12655b bdk: max17050: remove unused cached batt voltage 2025-12-27 06:06:56 +02:00
CTCaer
c03757e73d bdk: joycon: improve charger config 
Utilize charger config set command which allows for supplement mode.
Additionally, remove ping config when SIO and parse buttons/sticks on subcmd reports.
 2025-12-27 06:06:17 +02:00
CTCaer
0cab56293d bdk: ccplex: do not disable mselect on cpu pwrgate 2025-12-25 12:51:37 +02:00
CTCaer
ae7c5fdfdb bdk: heap: add more safe guards 
- Use magic for used regions
- Deduplicate calloc
Enable a print/abort in _heap_free() for debugging.
 2025-12-25 12:33:41 +02:00
CTCaer
a7ad3d4984 bdk: display: improve and deduplicate more 
- Add delay after a DSI soft reset
- Remove more duplicated configs
- Improve code to save code size
- Improve comments
- Do not allow display_backlight to be used with OLED
 2025-12-25 11:36:06 +02:00
CTCaer
67140d026c bdk: util: use volatile base for reg_write_array 2025-12-18 11:50:00 +02:00
CTCaer
998053f8db bdk: display: use a scratch reg for backlight 
Spare registers normally have hidden hw config usage, so avoid them just in case.
 2025-12-18 11:48:53 +02:00
CTCaer
b5a6c8eb64 bdk: display: simplify macros 
Expand register index in parent macro and remove _DI/_DSIREG macros.
 2025-12-18 11:17:43 +02:00
CTCaer
8faa1a6690 bdk: display: use spare reg to store dcs bl duty 
And also remove backlight pwm restoring from coreboot hw deinit path.
 2025-12-18 09:54:26 +02:00
CTCaer
ba95bb7494 bdk: fatfs: improve fat read/write 
- Convert access from min cluster size to block size
  Also allow read/writes to less than cluster size
- In case of intercluster access throw an error
- Do not error on zero size

On reads buffer still needs to be block (instead of cluster) aligned.
On writes, buffer still needs to be readable out of bounds.
 2025-12-17 07:11:51 +02:00
CTCaer
20a50988c5 bdk: fuse: return array size with fuse_read_array 2025-12-17 06:41:52 +02:00
CTCaer
0db758592a bdk: minerva: add IRB support 
Aka no table support.
 2025-12-17 05:24:16 +02:00
CTCaer
8d6bb5f427 bdk: clock: update some defines 2025-12-17 04:33:40 +02:00
CTCaer
4797b42e76 bdk: sdmmc: add defines for max block number 2025-12-17 04:30:12 +02:00
CTCaer
7cbefa3061 bdk: add reserved cfg to ipl meta and nyx storage 2025-11-27 12:17:33 +02:00
CTCaer
5176ce4394 bdk: sdmmc: correct drive ohms comment 2025-11-27 12:14:43 +02:00
CTCaer
a6d4e5adaa bdk: clock: add i2c to the errata affected list 2025-11-27 12:12:13 +02:00
CTCaer
4a24956f3a bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2025-11-27 12:04:12 +02:00
CTCaer
727d37c991 bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2025-11-27 11:25:08 +02:00
CTCaer
1fc92cfa33 bdk: nyx: rename disp_id to panel_id 2025-11-27 11:21:06 +02:00
CTCaer
62163f3255 bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2025-11-27 11:20:19 +02:00
CTCaer
fc71e405d2 bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2025-11-27 11:13:54 +02:00
CTCaer
e7783f0bd7 bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2025-11-26 16:53:19 +02:00
CTCaer
e50ad58d61 bdk: clock: add sdmmc1 to the errata affected list 2025-11-26 16:47:29 +02:00
CTCaer
0a63fa19a3 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2025-11-26 16:46:11 +02:00
CTCaer
19285745b5 bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2025-11-26 14:48:47 +02:00
CTCaer
9c028cd94a bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2025-11-26 14:37:14 +02:00
CTCaer
a2ea3fb08e bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2025-11-26 14:33:56 +02:00
CTCaer
813346f796 bdk: bpmp: add binX clock defines 2025-11-11 13:52:00 +02:00
CTCaer
260e28e628 bdk: fuse: add sense function 2025-11-11 13:28:44 +02:00
CTCaer
602945d918 bdk: fuse: add extra info on regs 2025-11-11 13:27:36 +02:00
CTCaer
7e01438ed3 bdk: fuse: correct masking on array read cmd 2025-11-11 13:27:13 +02:00
CTCaer
2c66b17f42 bdk: t210: add mc channel macros 2025-11-11 13:24:06 +02:00
CTCaer
e2f043a58a bdk: emc/mc: don't use [io]_rsvd naming for unused regs 2025-11-11 13:23:07 +02:00
CTCaer
0737f27ba0 bdk: lvgl: make sure task has a task to call 2025-11-11 13:17:34 +02:00
CTCaer
ded26332c6 bdk: ini: switch back to ASCII ordering 
For combining multiple inis.
 2025-08-27 15:22:54 +03:00
CTCaer
9309b53054 bdk: dirlist: use flags instead of arguments 
A new flag was also added that forces an ASCII ordering instead of Alphabetical one.
 2025-08-27 15:18:41 +03:00