sdmmc: refactor and simplify various functions
This commit is contained in:
CTCaer
@@ -49,7 +49,7 @@
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#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
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#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
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#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
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#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
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#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
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/* class 3 */
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#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
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@@ -104,12 +104,12 @@
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/*
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* MMC_SWITCH argument format:
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*
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* [31:26] Always 0
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* [25:24] Access Mode
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* [23:16] Location of target Byte in EXT_CSD
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* [15:08] Value Byte
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* [07:03] Always 0
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* [02:00] Command Set
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* [31:26] Always 0
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* [25:24] Access Mode
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* [23:16] Location of target Byte in EXT_CSD
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* [15:08] Value Byte
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* [07:03] Always 0
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* [02:00] Command Set
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*/
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/*
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@@ -127,79 +127,81 @@
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* c : clear by read
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*/
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#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
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#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
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#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
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#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
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#define R1_ERASE_PARAM (1 << 27) /* ex, c */
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#define R1_WP_VIOLATION (1 << 26) /* erx, c */
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#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
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#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
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#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
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#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
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#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
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#define R1_CC_ERROR (1 << 20) /* erx, c */
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#define R1_ERROR (1 << 19) /* erx, c */
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#define R1_UNDERRUN (1 << 18) /* ex, c */
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#define R1_OVERRUN (1 << 17) /* ex, c */
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#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
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#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
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#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
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#define R1_ERASE_RESET (1 << 13) /* sr, c */
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#define R1_STATUS(x) ((x) & 0xFFFFE000)
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#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
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#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
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#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
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#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
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#define R1_APP_CMD (1 << 5) /* sr, c */
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#define R1_SKIP_STATE_CHECK (1 << 4) /* Custom state to skip expected state check */
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#define R1_AKE_SEQ_ERROR (1 << 3)
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#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
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#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
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#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
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#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
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#define R1_ERASE_PARAM (1 << 27) /* ex, c */
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#define R1_WP_VIOLATION (1 << 26) /* erx, c */
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#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
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#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
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#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
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#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
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#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
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#define R1_CC_ERROR (1 << 20) /* erx, c */
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#define R1_ERROR (1 << 19) /* erx, c */
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#define R1_UNDERRUN (1 << 18) /* ex, c */
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#define R1_OVERRUN (1 << 17) /* ex, c */
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#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
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#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
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#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
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#define R1_ERASE_RESET (1 << 13) /* sr, c */
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#define R1_STATUS(x) ((x) & 0xFFFFE000)
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#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
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#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
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#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
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#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
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#define R1_APP_CMD (1 << 5) /* sr, c */
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#define R1_SKIP_STATE_CHECK (1 << 4) /* Custom state to skip expected state check */
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#define R1_AKE_SEQ_ERROR (1 << 3)
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/* R1_CURRENT_STATE 12:9 */
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#define R1_STATE(x) ((x) << 9)
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#define R1_STATE_IDLE 0
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#define R1_STATE_READY 1
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#define R1_STATE_IDENT 2
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#define R1_STATE_STBY 3
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#define R1_STATE_TRAN 4
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#define R1_STATE_DATA 5
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#define R1_STATE_RCV 6
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#define R1_STATE_PRG 7
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#define R1_STATE_DIS 8
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#define R1_STATE(x) ((x) << 9)
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#define R1_STATE_IDLE 0
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#define R1_STATE_READY 1
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#define R1_STATE_IDENT 2
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#define R1_STATE_STBY 3
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#define R1_STATE_TRAN 4
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#define R1_STATE_DATA 5
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#define R1_STATE_RCV 6
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#define R1_STATE_PRG 7
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#define R1_STATE_DIS 8
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/*
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* OCR bits are mostly in host.h
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*/
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#define MMC_CARD_VDD_18 (1 << 7) /* Card VDD voltage 1.8 */
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#define MMC_CARD_VDD_27_34 (0x7F << 15) /* Card VDD voltage 2.7 ~ 3.4 */
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#define MMC_CARD_CCS (1 << 30) /* Card Capacity status bit */
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#define MMC_CARD_BUSY (1 << 31) /* Card Power up status bit */
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#define MMC_OCR_VCCQ_18 (1 << 7) /* Card VDD voltage 1.8 */
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#define MMC_OCR_VCCQ_20_26 (0x7F << 8) /* Card VDD voltage 2.0 ~ 2.6 */
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#define MMC_OCR_VCCQ_27_34 (0x7F << 15) /* Card VDD voltage 2.7 ~ 3.4 */
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#define MMC_OCR_HCS (2 << 29) /* Host Capacity status bit */
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#define MMC_OCR_CCS MMC_OCR_HCS /* Card Capacity status bit */
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#define MMC_OCR_BUSY (1 << 31) /* Card Power up status bit */
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/*
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* Card Command Classes (CCC)
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*/
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#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
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#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
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/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
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/* (and for SPI, CMD58,59) */
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#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
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#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
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/* (CMD11) */
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#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
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#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
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/* (CMD16,17,18) */
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#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
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#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
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/* (CMD20) */
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#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
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#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
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/* (CMD16,24,25,26,27) */
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#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
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#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
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/* (CMD32,33,34,35,36,37,38,39) */
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#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
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#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
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/* (CMD28,29,30) */
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#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
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#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
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/* (CMD16,CMD42) */
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#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
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#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
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/* (CMD55,56,57,ACMD*) */
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#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
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#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
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/* (CMD5,39,40,52,53) */
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#define CCC_SWITCH (1<<10) /* (10) High speed switch */
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#define CCC_SWITCH (1<<10) /* (10) High speed switch */
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/* (CMD6,34,35,36,37,50) */
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/* (11) Reserved */
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/* (CMD?) */
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@@ -208,228 +210,224 @@
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* CSD field definitions
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*/
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#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
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#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
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#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
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#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
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#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
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#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
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#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
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#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
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#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
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#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
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#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
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#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
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#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
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#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
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#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
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#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
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#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
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#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
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#define EXT_CSD_FLUSH_CACHE 32 /* W */
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#define EXT_CSD_CACHE_CTRL 33 /* R/W */
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#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
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#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
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#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
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#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
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#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
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#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
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#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
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#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
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#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
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#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* RO, 3 bytes */
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#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
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#define EXT_CSD_HPI_MGMT 161 /* R/W */
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#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
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#define EXT_CSD_BKOPS_EN 163 /* R/W */
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#define EXT_CSD_BKOPS_START 164 /* W */
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#define EXT_CSD_SANITIZE_START 165 /* W */
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#define EXT_CSD_WR_REL_PARAM 166 /* RO */
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#define EXT_CSD_RPMB_MULT 168 /* RO */
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#define EXT_CSD_FW_CONFIG 169 /* R/W */
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#define EXT_CSD_BOOT_WP 173 /* R/W */
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#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
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#define EXT_CSD_PART_CONFIG 179 /* R/W */
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#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_POWER_CLASS 187 /* R/W */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_STRUCTURE 194 /* RO */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
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#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
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#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
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#define EXT_CSD_PWR_CL_52_195 200 /* RO */
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#define EXT_CSD_PWR_CL_26_195 201 /* RO */
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#define EXT_CSD_PWR_CL_52_360 202 /* RO */
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#define EXT_CSD_PWR_CL_26_360 203 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
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#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
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#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
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#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
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#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
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#define EXT_CSD_BOOT_MULT 226 /* RO */
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#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
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#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
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#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
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#define EXT_CSD_TRIM_MULT 232 /* RO */
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#define EXT_CSD_PWR_CL_200_195 236 /* RO */
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#define EXT_CSD_PWR_CL_200_360 237 /* RO */
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#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
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#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
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#define EXT_CSD_BKOPS_STATUS 246 /* RO */
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#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
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#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
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#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
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#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
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#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
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#define EXT_CSD_DEVICE_VERSION 262 /* RO, 2 bytes */
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#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
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#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
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#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
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#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
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#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
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#define EXT_CSD_SUPPORTED_MODE 493 /* RO */
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#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
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#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
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#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
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#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
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#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
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#define EXT_CSD_HPI_FEATURES 503 /* RO */
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#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
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#define EXT_CSD_FLUSH_CACHE 32 /* W */
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#define EXT_CSD_CACHE_CTRL 33 /* R/W */
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#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
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#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
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#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
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#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
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#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
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#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
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#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
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#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
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#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
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#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* RO, 3 bytes */
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#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
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#define EXT_CSD_HPI_MGMT 161 /* R/W */
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#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
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#define EXT_CSD_BKOPS_EN 163 /* R/W */
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#define EXT_CSD_BKOPS_START 164 /* W */
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#define EXT_CSD_SANITIZE_START 165 /* W */
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#define EXT_CSD_WR_REL_PARAM 166 /* RO */
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#define EXT_CSD_RPMB_MULT 168 /* RO */
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#define EXT_CSD_FW_CONFIG 169 /* R/W */
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#define EXT_CSD_BOOT_WP 173 /* R/W */
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#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
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#define EXT_CSD_PART_CONFIG 179 /* R/W */
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#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_POWER_CLASS 187 /* R/W */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_STRUCTURE 194 /* RO */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
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#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
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#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
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#define EXT_CSD_PWR_CL_52_195 200 /* RO */
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#define EXT_CSD_PWR_CL_26_195 201 /* RO */
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#define EXT_CSD_PWR_CL_52_360 202 /* RO */
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#define EXT_CSD_PWR_CL_26_360 203 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
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#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
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#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
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#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
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#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
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#define EXT_CSD_BOOT_MULT 226 /* RO */
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#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
|
||||
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
|
||||
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
|
||||
#define EXT_CSD_TRIM_MULT 232 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
|
||||
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
|
||||
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
|
||||
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
|
||||
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
|
||||
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
|
||||
#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
|
||||
#define EXT_CSD_DEVICE_VERSION 262 /* RO, 2 bytes */
|
||||
#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
|
||||
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
|
||||
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
|
||||
#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
|
||||
#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
|
||||
#define EXT_CSD_SUPPORTED_MODE 493 /* RO */
|
||||
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
|
||||
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
|
||||
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
|
||||
#define EXT_CSD_HPI_FEATURES 503 /* RO */
|
||||
|
||||
/*
|
||||
* EXT_CSD field definitions
|
||||
*/
|
||||
|
||||
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
|
||||
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
|
||||
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
|
||||
|
||||
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
|
||||
|
||||
#define EXT_CSD_PART_SETTING_COMPLETED (0x1)
|
||||
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
|
||||
#define EXT_CSD_PART_SETTING_COMPLETED (0x1)
|
||||
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
|
||||
|
||||
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
|
||||
#define EXT_CSD_CMD_SET_SECURE (1<<1)
|
||||
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
|
||||
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
|
||||
#define EXT_CSD_CMD_SET_SECURE (1<<1)
|
||||
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
|
||||
|
||||
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
|
||||
EXT_CSD_CARD_TYPE_HS_52)
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | EXT_CSD_CARD_TYPE_HS_52)
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.8V or 3V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
|
||||
| EXT_CSD_CARD_TYPE_DDR_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V | EXT_CSD_CARD_TYPE_DDR_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
|
||||
/* SDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS200_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS400_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
|
||||
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | EXT_CSD_CARD_TYPE_HS200_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | EXT_CSD_CARD_TYPE_HS400_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
|
||||
|
||||
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
|
||||
#define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */
|
||||
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
|
||||
#define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */
|
||||
|
||||
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
|
||||
#define EXT_CSD_TIMING_HS 1 /* High speed */
|
||||
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
|
||||
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
|
||||
#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
|
||||
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
|
||||
#define EXT_CSD_TIMING_HS 1 /* High speed */
|
||||
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
|
||||
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
|
||||
#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
|
||||
|
||||
#define EXT_CSD_SEC_ER_EN (1<<0)
|
||||
#define EXT_CSD_SEC_BD_BLK_EN (1<<2)
|
||||
#define EXT_CSD_SEC_GB_CL_EN (1<<4)
|
||||
#define EXT_CSD_SEC_SANITIZE (1<<6) /* v4.5 only */
|
||||
#define EXT_CSD_SEC_ER_EN (1<<0)
|
||||
#define EXT_CSD_SEC_BD_BLK_EN (1<<2)
|
||||
#define EXT_CSD_SEC_GB_CL_EN (1<<4)
|
||||
#define EXT_CSD_SEC_SANITIZE (1<<6) /* v4.5 only */
|
||||
|
||||
#define EXT_CSD_RST_N_EN_MASK 0x3
|
||||
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
|
||||
#define EXT_CSD_RST_N_EN_MASK 0x3
|
||||
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
|
||||
|
||||
#define EXT_CSD_NO_POWER_NOTIFICATION 0
|
||||
#define EXT_CSD_POWER_ON 1
|
||||
#define EXT_CSD_POWER_OFF_SHORT 2
|
||||
#define EXT_CSD_POWER_OFF_LONG 3
|
||||
#define EXT_CSD_NO_POWER_NOTIFICATION 0
|
||||
#define EXT_CSD_POWER_ON 1
|
||||
#define EXT_CSD_POWER_OFF_SHORT 2
|
||||
#define EXT_CSD_POWER_OFF_LONG 3
|
||||
|
||||
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
|
||||
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
|
||||
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
|
||||
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
|
||||
|
||||
#define EXT_CSD_PACKED_EVENT_EN (1<<3)
|
||||
#define EXT_CSD_PACKED_EVENT_EN (1<<3)
|
||||
|
||||
/*
|
||||
* EXCEPTION_EVENT_STATUS field
|
||||
*/
|
||||
#define EXT_CSD_URGENT_BKOPS (1<<0)
|
||||
#define EXT_CSD_DYNCAP_NEEDED (1<<1)
|
||||
#define EXT_CSD_SYSPOOL_EXHAUSTED (1<<2)
|
||||
#define EXT_CSD_PACKED_FAILURE (1<<3)
|
||||
#define EXT_CSD_URGENT_BKOPS (1<<0)
|
||||
#define EXT_CSD_DYNCAP_NEEDED (1<<1)
|
||||
#define EXT_CSD_SYSPOOL_EXHAUSTED (1<<2)
|
||||
#define EXT_CSD_PACKED_FAILURE (1<<3)
|
||||
|
||||
#define EXT_CSD_PACKED_GENERIC_ERROR (1<<0)
|
||||
#define EXT_CSD_PACKED_INDEXED_ERROR (1<<1)
|
||||
#define EXT_CSD_PACKED_GENERIC_ERROR (1<<0)
|
||||
#define EXT_CSD_PACKED_INDEXED_ERROR (1<<1)
|
||||
|
||||
/*
|
||||
* BKOPS status level
|
||||
*/
|
||||
#define EXT_CSD_BKOPS_OK 0x0
|
||||
#define EXT_CSD_BKOPS_NON_CRITICAL 0x1
|
||||
#define EXT_CSD_BKOPS_PERF_IMPACTED 0x2
|
||||
#define EXT_CSD_BKOPS_CRITICAL 0x3
|
||||
#define EXT_CSD_BKOPS_OK 0x0
|
||||
#define EXT_CSD_BKOPS_NON_CRITICAL 0x1
|
||||
#define EXT_CSD_BKOPS_PERF_IMPACTED 0x2
|
||||
#define EXT_CSD_BKOPS_CRITICAL 0x3
|
||||
|
||||
/*
|
||||
* BKOPS modes
|
||||
*/
|
||||
#define EXT_CSD_BKOPS_MANUAL 0x01 /* STICKY! */
|
||||
#define EXT_CSD_BKOPS_AUTO 0x02
|
||||
#define EXT_CSD_BKOPS_MANUAL 0x01 /* STICKY! */
|
||||
#define EXT_CSD_BKOPS_AUTO 0x02
|
||||
|
||||
/*
|
||||
* Command Queue
|
||||
*/
|
||||
#define EXT_CSD_CMDQ_MODE_ENABLED (1<<0)
|
||||
#define EXT_CSD_CMDQ_DEPTH_MASK 0x1F
|
||||
#define EXT_CSD_CMDQ_SUPPORTED (1<<0)
|
||||
#define EXT_CSD_CMDQ_MODE_ENABLED (1<<0)
|
||||
#define EXT_CSD_CMDQ_DEPTH_MASK 0x1F
|
||||
#define EXT_CSD_CMDQ_SUPPORTED (1<<0)
|
||||
|
||||
/*
|
||||
* MMC_SWITCH access modes
|
||||
*/
|
||||
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
|
||||
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
|
||||
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
|
||||
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
|
||||
|
||||
/*
|
||||
* Erase/trim/discard
|
||||
*/
|
||||
#define MMC_ERASE_ARG 0x00000000
|
||||
#define MMC_SECURE_ERASE_ARG 0x80000000
|
||||
#define MMC_TRIM_ARG 0x00000001
|
||||
#define MMC_DISCARD_ARG 0x00000003
|
||||
#define MMC_SECURE_TRIM1_ARG 0x80000001
|
||||
#define MMC_SECURE_TRIM2_ARG 0x80008000
|
||||
#define MMC_SECURE_ARGS 0x80000000
|
||||
#define MMC_TRIM_ARGS 0x00008001
|
||||
#define MMC_ERASE_ARG 0x00000000
|
||||
#define MMC_SECURE_ERASE_ARG 0x80000000
|
||||
#define MMC_TRIM_ARG 0x00000001
|
||||
#define MMC_DISCARD_ARG 0x00000003
|
||||
#define MMC_SECURE_TRIM1_ARG 0x80000001
|
||||
#define MMC_SECURE_TRIM2_ARG 0x80008000
|
||||
#define MMC_SECURE_ARGS 0x80000000
|
||||
#define MMC_TRIM_ARGS 0x00008001
|
||||
|
||||
/*
|
||||
* Vendor definitions and structs
|
||||
*/
|
||||
#define MMC_SANDISK_HEALTH_REPORT 0x96C9D71C
|
||||
#define MMC_SANDISK_HEALTH_REPORT 0x96C9D71C
|
||||
|
||||
#endif /* MMC_H */
|
||||
|
||||
@@ -79,7 +79,17 @@ static int _sdmmc_storage_check_card_status(u32 res)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _sdmmc_storage_execute_cmd_type1_ex(sdmmc_storage_t *storage, u32 *resp, u32 cmd, u32 arg, u32 check_busy, u32 expected_state, u32 mask)
|
||||
static int _sdmmc_storage_check_cached_card_status(sdmmc_t *sdmmc)
|
||||
{
|
||||
u32 resp;
|
||||
sdmmc_get_cached_rsp(sdmmc, &resp, SDMMC_RSP_TYPE_1);
|
||||
if (_sdmmc_storage_check_card_status(resp))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _sdmmc_storage_execute_cmd_ex_masked(sdmmc_storage_t *storage, u32 *resp, u32 cmd, u32 arg, u32 check_busy, u32 expected_state, u32 mask)
|
||||
{
|
||||
sdmmc_cmd_t cmdbuf;
|
||||
sdmmc_init_cmd(&cmdbuf, cmd, arg, SDMMC_RSP_TYPE_1, check_busy);
|
||||
@@ -97,10 +107,10 @@ static int _sdmmc_storage_execute_cmd_type1_ex(sdmmc_storage_t *storage, u32 *re
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int _sdmmc_storage_execute_cmd_type1(sdmmc_storage_t *storage, u32 cmd, u32 arg, u32 check_busy, u32 expected_state)
|
||||
static int _sdmmc_storage_execute_cmd_ex_state(sdmmc_storage_t *storage, u32 cmd, u32 arg, u32 check_busy, u32 expected_state)
|
||||
{
|
||||
u32 tmp;
|
||||
return _sdmmc_storage_execute_cmd_type1_ex(storage, &tmp, cmd, arg, check_busy, expected_state, 0);
|
||||
return _sdmmc_storage_execute_cmd_ex_masked(storage, &tmp, cmd, arg, check_busy, expected_state, 0);
|
||||
}
|
||||
|
||||
static int _sdmmc_storage_go_idle_state(sdmmc_storage_t *storage)
|
||||
@@ -125,7 +135,7 @@ static int _sdmmc_storage_get_cid(sdmmc_storage_t *storage)
|
||||
|
||||
static int _sdmmc_storage_select_card(sdmmc_storage_t *storage)
|
||||
{
|
||||
return _sdmmc_storage_execute_cmd_type1(storage, MMC_SELECT_CARD, storage->rca << 16, 1, R1_SKIP_STATE_CHECK);
|
||||
return _sdmmc_storage_execute_cmd_ex_state(storage, MMC_SELECT_CARD, storage->rca << 16, 1, R1_SKIP_STATE_CHECK);
|
||||
}
|
||||
|
||||
static int _sdmmc_storage_get_csd(sdmmc_storage_t *storage)
|
||||
@@ -142,12 +152,12 @@ static int _sdmmc_storage_get_csd(sdmmc_storage_t *storage)
|
||||
|
||||
static int _sdmmc_storage_set_blocklen(sdmmc_storage_t *storage, u32 blocklen)
|
||||
{
|
||||
return _sdmmc_storage_execute_cmd_type1(storage, MMC_SET_BLOCKLEN, blocklen, 0, R1_STATE_TRAN);
|
||||
return _sdmmc_storage_execute_cmd_ex_state(storage, MMC_SET_BLOCKLEN, blocklen, 0, R1_STATE_TRAN);
|
||||
}
|
||||
|
||||
static int _sdmmc_storage_get_status(sdmmc_storage_t *storage, u32 *resp, u32 mask)
|
||||
{
|
||||
return _sdmmc_storage_execute_cmd_type1_ex(storage, resp, MMC_SEND_STATUS, storage->rca << 16, 0, R1_STATE_TRAN, mask);
|
||||
return _sdmmc_storage_execute_cmd_ex_masked(storage, resp, MMC_SEND_STATUS, storage->rca << 16, 0, R1_STATE_TRAN, mask);
|
||||
}
|
||||
|
||||
static int _sdmmc_storage_check_status(sdmmc_storage_t *storage)
|
||||
@@ -160,7 +170,7 @@ int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg)
|
||||
{
|
||||
sdmmc_cmd_t cmdbuf;
|
||||
sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_CMD_62, arg, SDMMC_RSP_TYPE_1, 1);
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, 0, 0))
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, NULL, NULL))
|
||||
return 1;
|
||||
|
||||
u32 resp;
|
||||
@@ -202,8 +212,7 @@ int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf)
|
||||
reqbuf.is_multi_block = 0;
|
||||
reqbuf.is_auto_stop_trn = 0;
|
||||
|
||||
u32 blkcnt_out;
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, &blkcnt_out))
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL))
|
||||
{
|
||||
sdmmc_stop_transmission(storage->sdmmc, &tmp);
|
||||
_sdmmc_storage_get_status(storage, &tmp, 0);
|
||||
@@ -241,11 +250,7 @@ static int _sdmmc_storage_readwrite_ex(sdmmc_storage_t *storage, u32 *blkcnt_out
|
||||
return 1;
|
||||
}
|
||||
|
||||
sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1);
|
||||
if (_sdmmc_storage_check_card_status(tmp))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
return _sdmmc_storage_check_cached_card_status(storage->sdmmc);
|
||||
}
|
||||
|
||||
int sdmmc_storage_end(sdmmc_storage_t *storage)
|
||||
@@ -401,7 +406,7 @@ int sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, v
|
||||
* MMC specific functions.
|
||||
*/
|
||||
|
||||
static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u32 power)
|
||||
static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *rocr, u32 power)
|
||||
{
|
||||
sdmmc_cmd_t cmdbuf;
|
||||
|
||||
@@ -409,11 +414,11 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u
|
||||
switch (power)
|
||||
{
|
||||
case SDMMC_POWER_1_8:
|
||||
arg = MMC_CARD_CCS | MMC_CARD_VDD_18;
|
||||
arg = MMC_OCR_HCS | MMC_OCR_VCCQ_18;
|
||||
break;
|
||||
|
||||
case SDMMC_POWER_3_3:
|
||||
arg = MMC_CARD_CCS | MMC_CARD_VDD_27_34;
|
||||
arg = MMC_OCR_HCS | MMC_OCR_VCCQ_27_34;
|
||||
break;
|
||||
|
||||
default:
|
||||
@@ -424,7 +429,7 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, NULL, NULL))
|
||||
return 1;
|
||||
|
||||
return sdmmc_get_cached_rsp(storage->sdmmc, pout, SDMMC_RSP_TYPE_3);
|
||||
return sdmmc_get_cached_rsp(storage->sdmmc, rocr, SDMMC_RSP_TYPE_3);
|
||||
}
|
||||
|
||||
static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
|
||||
@@ -433,15 +438,15 @@ static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
|
||||
|
||||
while (true)
|
||||
{
|
||||
u32 cond = 0;
|
||||
if (_mmc_storage_get_op_cond_inner(storage, &cond, power))
|
||||
u32 rocr = 0;
|
||||
if (_mmc_storage_get_op_cond_inner(storage, &rocr, power))
|
||||
break;
|
||||
|
||||
// Check if power up is done.
|
||||
if (cond & MMC_CARD_BUSY)
|
||||
if (rocr & MMC_OCR_BUSY)
|
||||
{
|
||||
// Check if card is high capacity.
|
||||
if (cond & MMC_CARD_CCS)
|
||||
if (rocr & MMC_OCR_CCS)
|
||||
storage->has_sector_access = 1;
|
||||
|
||||
return 0;
|
||||
@@ -457,7 +462,7 @@ static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
|
||||
|
||||
static int _mmc_storage_set_relative_addr(sdmmc_storage_t *storage)
|
||||
{
|
||||
return _sdmmc_storage_execute_cmd_type1(storage, MMC_SET_RELATIVE_ADDR, storage->rca << 16, 0, R1_SKIP_STATE_CHECK);
|
||||
return _sdmmc_storage_execute_cmd_ex_state(storage, MMC_SET_RELATIVE_ADDR, storage->rca << 16, 0, R1_SKIP_STATE_CHECK);
|
||||
}
|
||||
|
||||
static void _mmc_storage_parse_cid(sdmmc_storage_t *storage)
|
||||
@@ -562,44 +567,14 @@ int mmc_storage_get_ext_csd(sdmmc_storage_t *storage)
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL))
|
||||
return 1;
|
||||
|
||||
u32 tmp = 0;
|
||||
sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1);
|
||||
_mmc_storage_parse_ext_csd(storage);
|
||||
|
||||
return _sdmmc_storage_check_card_status(tmp);
|
||||
}
|
||||
|
||||
int sd_storage_get_ext_reg(sdmmc_storage_t *storage, u8 fno, u8 page, u16 address, u32 len, void *buf)
|
||||
{
|
||||
if (!(storage->scr.cmds & BIT(2)))
|
||||
return 1;
|
||||
|
||||
sdmmc_cmd_t cmdbuf;
|
||||
|
||||
u32 arg = fno << 27 | page << 18 | address << 9 | (len - 1);
|
||||
|
||||
sdmmc_init_cmd(&cmdbuf, SD_READ_EXTR_SINGLE, arg, SDMMC_RSP_TYPE_1, 0);
|
||||
|
||||
sdmmc_req_t reqbuf;
|
||||
reqbuf.buf = buf;
|
||||
reqbuf.blksize = SDMMC_DAT_BLOCKSIZE;
|
||||
reqbuf.num_sectors = 1;
|
||||
reqbuf.is_write = 0;
|
||||
reqbuf.is_multi_block = 0;
|
||||
reqbuf.is_auto_stop_trn = 0;
|
||||
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL))
|
||||
return 1;
|
||||
|
||||
u32 tmp = 0;
|
||||
sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1);
|
||||
|
||||
return _sdmmc_storage_check_card_status(tmp);
|
||||
return _sdmmc_storage_check_cached_card_status(storage->sdmmc);
|
||||
}
|
||||
|
||||
static int _mmc_storage_switch(sdmmc_storage_t *storage, u32 arg)
|
||||
{
|
||||
return _sdmmc_storage_execute_cmd_type1(storage, MMC_SWITCH, arg, 1, R1_SKIP_STATE_CHECK);
|
||||
return _sdmmc_storage_execute_cmd_ex_state(storage, MMC_SWITCH, arg, 1, R1_SKIP_STATE_CHECK);
|
||||
}
|
||||
|
||||
static int _mmc_storage_switch_buswidth(sdmmc_storage_t *storage, u32 bus_width)
|
||||
@@ -828,18 +803,18 @@ int sdmmc_storage_set_mmc_partition(sdmmc_storage_t *storage, u32 partition)
|
||||
static int _sd_storage_execute_app_cmd(sdmmc_storage_t *storage, u32 expected_state, u32 mask, sdmmc_cmd_t *cmdbuf, sdmmc_req_t *req, u32 *blkcnt_out)
|
||||
{
|
||||
u32 tmp;
|
||||
if (_sdmmc_storage_execute_cmd_type1_ex(storage, &tmp, MMC_APP_CMD, storage->rca << 16, 0, expected_state, mask))
|
||||
if (_sdmmc_storage_execute_cmd_ex_masked(storage, &tmp, MMC_APP_CMD, storage->rca << 16, 0, expected_state, mask))
|
||||
return 1;
|
||||
|
||||
return sdmmc_execute_cmd(storage->sdmmc, cmdbuf, req, blkcnt_out);
|
||||
}
|
||||
|
||||
static int _sd_storage_execute_app_cmd_type1(sdmmc_storage_t *storage, u32 *resp, u32 cmd, u32 arg, u32 check_busy, u32 expected_state)
|
||||
static int _sd_storage_execute_app_cmd_tran(sdmmc_storage_t *storage, u32 cmd, u32 arg)
|
||||
{
|
||||
if (_sdmmc_storage_execute_cmd_type1(storage, MMC_APP_CMD, storage->rca << 16, 0, R1_STATE_TRAN))
|
||||
if (_sdmmc_storage_execute_cmd_ex_state(storage, MMC_APP_CMD, storage->rca << 16, 0, R1_STATE_TRAN))
|
||||
return 1;
|
||||
|
||||
return _sdmmc_storage_execute_cmd_type1_ex(storage, resp, cmd, arg, check_busy, expected_state, 0);
|
||||
return _sdmmc_storage_execute_cmd_ex_state(storage, cmd, arg, 0, R1_STATE_TRAN);
|
||||
}
|
||||
|
||||
#ifdef SDMMC_DEBUG_PRINT_SD_REGS
|
||||
@@ -952,11 +927,6 @@ void _sd_storage_debug_print_ssr(const u8 *raw_ssr)
|
||||
gfx_printf("DISCARD_SUPPORT: %X\n", unstuff_bits(raw_ssr1, 313, 1));
|
||||
gfx_printf("FULE_SUPPORT: %X\n", unstuff_bits(raw_ssr1, 312, 1));
|
||||
|
||||
gfx_printf("--RSVD-- %02X %X %02X %02X %04X\n",
|
||||
unstuff_bits(raw_ssr0, 496, 6), unstuff_bits(raw_ssr0, 424, 4),
|
||||
unstuff_bits(raw_ssr1, 378, 6), unstuff_bits(raw_ssr1, 340, 6),
|
||||
unstuff_bits(raw_ssr1, 314, 14));
|
||||
|
||||
gfx_printf("VENDOR_1: %06X %08X\n",
|
||||
unstuff_bits(raw_ssr1, 288, 24), unstuff_bits(raw_ssr1, 256, 32));
|
||||
|
||||
@@ -966,9 +936,39 @@ void _sd_storage_debug_print_ssr(const u8 *raw_ssr)
|
||||
gfx_printf("VENDOR_3: %08X %08X %08X %08X\n",
|
||||
unstuff_bits(raw_ssr3, 96 - 0, 32), unstuff_bits(raw_ssr3, 64, 32),
|
||||
unstuff_bits(raw_ssr3, 32 - 0, 32), unstuff_bits(raw_ssr3, 0, 32));
|
||||
|
||||
gfx_printf("--RSVD-- %02X %X %02X %02X %04X\n",
|
||||
unstuff_bits(raw_ssr0, 496, 6), unstuff_bits(raw_ssr0, 424, 4),
|
||||
unstuff_bits(raw_ssr1, 378, 6), unstuff_bits(raw_ssr1, 340, 6),
|
||||
unstuff_bits(raw_ssr1, 314, 14));
|
||||
}
|
||||
#endif
|
||||
|
||||
int sd_storage_get_ext_reg(sdmmc_storage_t *storage, u8 fno, u8 page, u16 address, u32 len, void *buf)
|
||||
{
|
||||
if (!(storage->scr.cmds & BIT(2)))
|
||||
return 1;
|
||||
|
||||
sdmmc_cmd_t cmdbuf;
|
||||
|
||||
u32 arg = fno << 27 | page << 18 | address << 9 | (len - 1);
|
||||
|
||||
sdmmc_init_cmd(&cmdbuf, SD_READ_EXTR_SINGLE, arg, SDMMC_RSP_TYPE_1, 0);
|
||||
|
||||
sdmmc_req_t reqbuf;
|
||||
reqbuf.buf = buf;
|
||||
reqbuf.blksize = SDMMC_DAT_BLOCKSIZE;
|
||||
reqbuf.num_sectors = 1;
|
||||
reqbuf.is_write = 0;
|
||||
reqbuf.is_multi_block = 0;
|
||||
reqbuf.is_auto_stop_trn = 0;
|
||||
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL))
|
||||
return 1;
|
||||
|
||||
return _sdmmc_storage_check_cached_card_status(storage->sdmmc);
|
||||
}
|
||||
|
||||
static int _sd_storage_send_if_cond(sdmmc_storage_t *storage, bool *is_sd_v1)
|
||||
{
|
||||
sdmmc_cmd_t cmdbuf;
|
||||
@@ -1059,7 +1059,7 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, bool is_sd_v1, int
|
||||
if (rocr & SD_OCR_S18A && lv_support)
|
||||
{
|
||||
// Switch to 1.8V signaling.
|
||||
if (!_sdmmc_storage_execute_cmd_type1(storage, SD_VOLTAGE_SWITCH, 0, 0, R1_STATE_READY))
|
||||
if (!_sdmmc_storage_execute_cmd_ex_state(storage, SD_VOLTAGE_SWITCH, 0, 0, R1_STATE_READY))
|
||||
{
|
||||
if (sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_UHS_SDR12))
|
||||
return 1;
|
||||
@@ -1200,8 +1200,6 @@ int sd_storage_get_scr(sdmmc_storage_t *storage)
|
||||
if (_sd_storage_execute_app_cmd(storage, R1_STATE_TRAN, 0, &cmdbuf, &reqbuf, NULL))
|
||||
return 1;
|
||||
|
||||
u32 tmp = 0;
|
||||
sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1);
|
||||
//Prepare buffer for unstuff_bits
|
||||
for (u32 i = 0; i < 8; i += 4)
|
||||
{
|
||||
@@ -1212,7 +1210,7 @@ int sd_storage_get_scr(sdmmc_storage_t *storage)
|
||||
}
|
||||
_sd_storage_parse_scr(storage);
|
||||
|
||||
return _sdmmc_storage_check_card_status(tmp);
|
||||
return _sdmmc_storage_check_cached_card_status(storage->sdmmc);
|
||||
}
|
||||
|
||||
static int _sd_storage_switch_get_all(sdmmc_storage_t *storage, void *buf)
|
||||
@@ -1231,9 +1229,7 @@ static int _sd_storage_switch_get_all(sdmmc_storage_t *storage, void *buf)
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL))
|
||||
return 1;
|
||||
|
||||
u32 tmp = 0;
|
||||
sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1);
|
||||
return _sdmmc_storage_check_card_status(tmp);
|
||||
return _sdmmc_storage_check_cached_card_status(storage->sdmmc);
|
||||
}
|
||||
|
||||
static int _sd_storage_switch(sdmmc_storage_t *storage, void *buf, int mode, int group, u32 arg)
|
||||
@@ -1255,9 +1251,7 @@ static int _sd_storage_switch(sdmmc_storage_t *storage, void *buf, int mode, int
|
||||
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL))
|
||||
return 1;
|
||||
|
||||
u32 tmp = 0;
|
||||
sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1);
|
||||
return _sdmmc_storage_check_card_status(tmp);
|
||||
return _sdmmc_storage_check_cached_card_status(storage->sdmmc);
|
||||
}
|
||||
|
||||
static void _sd_storage_set_power_limit(sdmmc_storage_t *storage, u16 power_limit, u8 *buf)
|
||||
@@ -1773,9 +1767,6 @@ int sd_storage_get_ssr(sdmmc_storage_t *storage)
|
||||
if (_sd_storage_execute_app_cmd(storage, R1_STATE_TRAN, 0, &cmdbuf, &reqbuf, NULL))
|
||||
return 1;
|
||||
|
||||
u32 tmp = 0;
|
||||
sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1);
|
||||
|
||||
// Convert buffer to LE.
|
||||
for (u32 i = 0; i < SDMMC_CMD_BLOCKSIZE; i += 4)
|
||||
{
|
||||
@@ -1787,7 +1778,7 @@ int sd_storage_get_ssr(sdmmc_storage_t *storage)
|
||||
|
||||
_sd_storage_parse_ssr(storage);
|
||||
|
||||
return _sdmmc_storage_check_card_status(tmp);
|
||||
return _sdmmc_storage_check_cached_card_status(storage->sdmmc);
|
||||
}
|
||||
|
||||
static void _sd_storage_parse_cid(sdmmc_storage_t *storage)
|
||||
@@ -1845,7 +1836,7 @@ static void _sd_storage_parse_csd(sdmmc_storage_t *storage)
|
||||
storage->sec_cnt = storage->csd.capacity;
|
||||
}
|
||||
|
||||
static bool _sdmmc_storage_get_bus_uhs_support(u32 bus_width, u32 type)
|
||||
static bool _sd_storage_get_bus_uhs_support(u32 bus_width, u32 type)
|
||||
{
|
||||
switch (type)
|
||||
{
|
||||
@@ -1873,9 +1864,8 @@ void sdmmc_storage_init_wait_sd()
|
||||
|
||||
int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type)
|
||||
{
|
||||
u32 tmp = 0;
|
||||
bool is_sd_v1 = false;
|
||||
bool lv_support = _sdmmc_storage_get_bus_uhs_support(bus_width, type);
|
||||
bool lv_support = _sd_storage_get_bus_uhs_support(bus_width, type);
|
||||
|
||||
DPRINTF("[SD]-[init: bus: %d, type: %d]\n", bus_width, type);
|
||||
|
||||
@@ -1934,7 +1924,7 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_widt
|
||||
DPRINTF("[SD] set blocklen to SD_BLOCKSIZE\n");
|
||||
|
||||
// Disconnect Card Detect resistor from DAT3.
|
||||
if (_sd_storage_execute_app_cmd_type1(storage, &tmp, SD_APP_SET_CLR_CARD_DETECT, 0, 0, R1_STATE_TRAN))
|
||||
if (_sd_storage_execute_app_cmd_tran(storage, SD_APP_SET_CLR_CARD_DETECT, 0))
|
||||
return 1;
|
||||
DPRINTF("[SD] cleared card detect\n");
|
||||
|
||||
@@ -1945,7 +1935,7 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_widt
|
||||
// If card supports a wider bus and if it's not SD Version 1.0 switch bus width.
|
||||
if (bus_width == SDMMC_BUS_WIDTH_4 && (storage->scr.bus_widths & BIT(SD_BUS_WIDTH_4)) && storage->scr.sda_vsn)
|
||||
{
|
||||
if (_sd_storage_execute_app_cmd_type1(storage, &tmp, SD_APP_SET_BUS_WIDTH, SD_BUS_WIDTH_4, 0, R1_STATE_TRAN))
|
||||
if (_sd_storage_execute_app_cmd_tran(storage, SD_APP_SET_BUS_WIDTH, SD_BUS_WIDTH_4))
|
||||
return 1;
|
||||
|
||||
sdmmc_set_bus_width(storage->sdmmc, SDMMC_BUS_WIDTH_4);
|
||||
@@ -2018,10 +2008,9 @@ int _gc_storage_custom_cmd(sdmmc_storage_t *storage, void *buf)
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (sdmmc_get_cached_rsp(storage->sdmmc, &resp, SDMMC_RSP_TYPE_1))
|
||||
return 1;
|
||||
if (_sdmmc_storage_check_card_status(resp))
|
||||
if (_sdmmc_storage_check_cached_card_status(storage->sdmmc))
|
||||
return 1;
|
||||
|
||||
return _sdmmc_storage_check_status(storage);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user