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sdmmc: modernize SD/eMMC cmds

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Add up to SDA 8.0.0 and eMMC 5.1 and correct some
This commit is contained in:
CTCaer
2026-06-13 21:26:51 +03:00
parent 229e7223cf
commit 5d6d86b86a
4 changed files with 68 additions and 62 deletions
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47
bdk/storage/mmc_def.h
View File

@@ -2,7 +2,7 @@
* Header for MultiMediaCard (MMC)
*
* Copyright 2002 Hewlett-Packard Company
* Copyright 2018-2021 CTCaer
* Copyright 2018-2026 CTCaer
*
* Use consistent with the GNU GPL is permitted,
* provided that this copyright notice is
@@ -44,14 +44,11 @@
#define MMC_BUS_TEST_R 14 /* adtc R1 */
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
#define MMC_BUS_TEST_W 19 /* adtc R1 */
#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
/* class 2 */
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
/* class 3 */
@@ -63,11 +60,13 @@
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
#define MMC_PROGRAM_CID 26 /* adtc R1 */
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
#define MMC_SET_TIME 49 /* adtc R1 */
/* class 6 */
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
#define MMC_SEND_WR_PROTECT_TYPE 31 /* adtc [31:0] wpdata addr R1 */
/* class 5 */
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
@@ -85,18 +84,23 @@
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
#define MMC_VENDOR_60_CMD 60 /* Vendor Defined */
#define MMC_VENDOR_61_CMD 61 /* Vendor Defined */
#define MMC_VENDOR_62_CMD 62 /* Vendor Defined */
#define MMC_VENDOR_63_CMD 63 /* Vendor Defined */
/* class 10 */
#define MMC_PROTOCOL_RD 53 /* adtc R1 */
#define MMC_PROTOCOL_WR 54 /* adtc R1 */
/* class 11 */
#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
#define MMC_QUEUED_TASK_PARAMS 44 /* ac [20:16] task id R1 */
#define MMC_QUEUED_TASK_ADDR 45 /* ac [31:0] data addr R1 */
#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
/* class 12 */
#define MMC_VENDOR_CMD_60 60 /* Vendor Defined */
#define MMC_VENDOR_CMD_61 61 /* Vendor Defined */
#define MMC_VENDOR_CMD_62 62 /* Vendor Defined */
#define MMC_VENDOR_CMD_63 63 /* Vendor Defined */
/*
* MMC_SWITCH argument format:
*
@@ -163,29 +167,6 @@
#define R1_STATE_PRG 7
#define R1_STATE_DIS 8
/*
* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
* R1 is the low order byte; R2 is the next highest byte, when present.
*/
#define R1_SPI_IDLE (1 << 0)
#define R1_SPI_ERASE_RESET (1 << 1)
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
#define R1_SPI_COM_CRC (1 << 3)
#define R1_SPI_ERASE_SEQ (1 << 4)
#define R1_SPI_ADDRESS (1 << 5)
#define R1_SPI_PARAMETER (1 << 6)
/* R1 bit 7 is always zero */
#define R2_SPI_CARD_LOCKED (1 << 8)
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
#define R2_SPI_ERROR (1 << 10)
#define R2_SPI_CC_ERROR (1 << 11)
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
#define R2_SPI_WP_VIOLATION (1 << 13)
#define R2_SPI_ERASE_PARAM (1 << 14)
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
/*
* OCR bits are mostly in host.h
*/

65
bdk/storage/sd_def.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2005-2007 Pierre Ossman, All Rights Reserved.
* Copyright (c) 2018-2025 CTCaer
* Copyright (c) 2018-2026 CTCaer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -11,43 +11,68 @@
#ifndef SD_DEF_H
#define SD_DEF_H
/* SD commands type argument response */
/* SD commands type argument response */
/* class 0 */
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
#define SD_VOLTAGE_SWITCH 11 /* ac R1 */
/* Class 1 */
#define SD_Q_MANAGEMENT 43 /* ac R1b */
#define SD_Q_TASK_INFO_A 44 /* ac R1 */
#define SD_Q_TASK_INFO_B 45 /* ac R1 */
#define SD_Q_RD_TASK 46 /* adtc R1 */
#define SD_Q_WR_TASK 47 /* adtc R1 */
/* Class 2 */
#define SD_ADDR_EXT 22 /* ac [5:0] R1 */
/* class 10 */
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
#define SD_SEND_TUNING_BLOCK 19 /* ac R1b */
#define SD_SPEED_CLASS_CONTROL 20 /* ac [31:0] R1 */
#define SD_ADDRESS_EXTENSION 22 /* ac [5:0] UC ext addr R1 */
/* class 5 */
#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
/* Class 9 */
#define SD_IO_SEND_OP_COND 5 /* bcr [31:0] OCR R4 */
#define SD_IO_RW_DIRECT 52 /* ac R5 */
#define SD_IO_RW_EXTENDED 53 /* adtc R5 */
/* class 10 */
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
#define SD_CMD_SYSTEM_34 34 /* cmd system defined */
#define SD_CMD_SYSTEM_35 35 /* cmd system defined */
#define SD_CMD_SYSTEM_36 36 /* cmd system defined */
#define SD_CMD_SYSTEM_37 37 /* cmd system defined */
#define SD_CMD_SYSTEM_50 50 /* cmd system defined */
#define SD_CMD_SYSTEM_57 57 /* cmd system defined */
/* class 11 */
#define SD_READ_EXTR_SINGLE 48 /* adtc [31:0] R1 */
#define SD_WRITE_EXTR_SINGLE 49 /* adtc [31:0] R1 */
#define SD_READ_EXTR_MULTI 58 /* adtc [31:0] R1 */
#define SD_WRITE_EXTR_MULTI 59 /* adtc [31:0] R1 */
#define SD_VENDOR_CMD_60 60 /* vendor defined */
#define SD_VENDOR_CMD_61 61 /* vendor defined */
#define SD_VENDOR_CMD_62 62 /* vendor defined */
#define SD_VENDOR_CMD_63 63 /* vendor defined */
/* Application commands */
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define SD_APP_SD_STATUS 13 /* adtc R1 */
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SD_APP_SEND_NUM_WR_BLOCKS 22 /* adtc R1 */
#define SD_APP_SET_WR_BLK_ERASE_COUNT 23 /* ac R1 */
#define SD_APP_SD_SEND_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SD_APP_SET_CLR_CARD_DETECT 42 /* adtc R1 */
#define SD_APP_SEND_SCR 51 /* adtc R1 */
/* Application secure commands */
#define SD_APP_SECURE_READ_MULTI_BLOCK 18 /* adtc R1 */
#define SD_APP_SECURE_WRITE_MULTI_BLOCK 25 /* adtc R1 */
#define SD_APP_SECURE_WRITE_MKB 26 /* adtc R1 */
#define SD_APP_SECURE_ERASE 38 /* adtc R1b */
#define SD_APP_GET_MKB 43 /* adtc [31:0] See below R1 */
#define SD_APP_GET_MID 44 /* adtc R1 */
#define SD_APP_SET_CER_RN1 45 /* adtc R1 */
#define SD_APP_GET_CER_RN2 46 /* adtc R1 */
#define SD_APP_SET_CER_RES2 47 /* adtc R1 */
#define SD_APP_GET_CER_RES1 48 /* adtc R1 */
#define SD_APP_CHANGE_SECURE_AREA 49 /* adtc R1b */
/* Application sd secure commands */
#define SD_APP_SECURE_READ_MULTI_BLOCK 18 /* adtc R1 */
#define SD_APP_SECURE_WRITE_MULTI_BLOCK 25 /* adtc R1 */
#define SD_APP_SECURE_WRITE_MKB 26 /* adtc R1 */
#define SD_APP_SECURE_ERASE 38 /* adtc R1b */
#define SD_APP_GET_MKB 43 /* adtc [31:0] See below R1 */
#define SD_APP_GET_MID 44 /* adtc R1 */
#define SD_APP_SET_CER_RN1 45 /* adtc R1 */
#define SD_APP_GET_CER_RN2 46 /* adtc R1 */
#define SD_APP_SET_CER_RES2 47 /* adtc R1 */
#define SD_APP_GET_CER_RES1 48 /* adtc R1 */
#define SD_APP_CHANGE_SECURE_AREA 49 /* adtc R1b */
/* ICR bit definitions */
#define SD_ICR_PATTERN 0xAA /* Check pattern */

12
bdk/storage/sdmmc.c
View File

@@ -159,7 +159,7 @@ static int _sdmmc_storage_check_status(sdmmc_storage_t *storage)
int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg)
{
sdmmc_cmd_t cmdbuf;
sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_62_CMD, arg, SDMMC_RSP_TYPE_1, 1);
sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_CMD_62, arg, SDMMC_RSP_TYPE_1, 1);
if (sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, 0, 0))
return 1;
@@ -193,7 +193,7 @@ int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf)
sdmmc_cmd_t cmdbuf;
sdmmc_req_t reqbuf;
sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_63_CMD, 0, SDMMC_RSP_TYPE_1, 0); // similar to CMD17 with arg 0x0.
sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_CMD_63, 0, SDMMC_RSP_TYPE_1, 0); // similar to CMD17 with arg 0x0.
reqbuf.buf = buf;
reqbuf.num_sectors = 1;
@@ -1011,7 +1011,7 @@ static int _sd_storage_send_op_cond(sdmmc_storage_t *storage, u32 *rocr, u32 ocr
{
sdmmc_cmd_t cmdbuf;
sdmmc_init_cmd(&cmdbuf, SD_APP_OP_COND, ocr, SDMMC_RSP_TYPE_3, 0);
sdmmc_init_cmd(&cmdbuf, SD_APP_SD_SEND_OP_COND, ocr, SDMMC_RSP_TYPE_3, 0);
if (_sd_storage_execute_app_cmd(storage, R1_SKIP_STATE_CHECK, is_sd_v1 ? R1_ILLEGAL_COMMAND : 0, &cmdbuf, NULL, NULL))
return 1;
@@ -1059,7 +1059,7 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, bool is_sd_v1, int
if (rocr & SD_OCR_S18A && lv_support)
{
// Switch to 1.8V signaling.
if (!_sdmmc_storage_execute_cmd_type1(storage, SD_SWITCH_VOLTAGE, 0, 0, R1_STATE_READY))
if (!_sdmmc_storage_execute_cmd_type1(storage, SD_VOLTAGE_SWITCH, 0, 0, R1_STATE_READY))
{
if (sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_UHS_SDR12))
return 1;
@@ -1557,7 +1557,7 @@ static int _sd_storage_set_uhs_bus_speed(sdmmc_storage_t *storage, u32 type)
return 1;
DPRINTF("[SD] after setup clock\n");
if (sdmmc_tuning_execute(storage->sdmmc, type, MMC_SEND_TUNING_BLOCK))
if (sdmmc_tuning_execute(storage->sdmmc, type, SD_SEND_TUNING_BLOCK))
return 1;
DPRINTF("[SD] after tuning\n");
@@ -2002,7 +2002,7 @@ int _gc_storage_custom_cmd(sdmmc_storage_t *storage, void *buf)
{
u32 resp;
sdmmc_cmd_t cmdbuf;
sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_60_CMD, 0, SDMMC_RSP_TYPE_1, 1);
sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_CMD_60, 0, SDMMC_RSP_TYPE_1, 1);
sdmmc_req_t reqbuf;
reqbuf.buf = buf;

6
bdk/storage/sdmmc_driver.c
View File

@@ -908,7 +908,7 @@ static u32 _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
u16 norintsts = sdmmc->regs->norintsts;
u16 errintsts = sdmmc->regs->errintsts;
DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);
DPRINTF("norintsts %04X, errintsts %04X\n", norintsts, errintsts);
if (pout)
*pout = norintsts;
@@ -917,7 +917,7 @@ static u32 _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
if (norintsts & SDHCI_INT_ERROR)
{
#ifdef ERROR_EXTRA_PRINTING
EPRINTFARGS("SDMMC%d: intsts %08X, errintsts %08X", sdmmc->id + 1, norintsts, errintsts);
EPRINTFARGS("SDMMC%d: intsts %04X, errintsts %04X", sdmmc->id + 1, norintsts, errintsts);
#endif
sdmmc->error_sts = errintsts;
sdmmc->regs->errintsts = errintsts;
@@ -1128,7 +1128,7 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
if (_sdmmc_send_cmd(sdmmc, cmd, is_data_present))
{
#ifdef ERROR_EXTRA_PRINTING
EPRINTFARGS("SDMMC%d: Wrong Response type %08X!", sdmmc->id + 1, cmd->rsp_type);
EPRINTFARGS("SDMMC%d: Wrong Response type %d!", sdmmc->id + 1, cmd->rsp_type);
#endif
return 1;
}