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hoc-sys: revert to an ancient version that works on mariko units

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This commit is contained in:
souldbminersmwc
2025-12-02 20:01:33 -05:00
parent 5fb7a3031a
commit feaa0fd93d
82 changed files with 528 additions and 41080 deletions
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34
Source/sys-clk/sysmodule/src/board.cpp
View File

@@ -31,10 +31,6 @@
#define HOSSVC_HAS_CLKRST (hosversionAtLeast(8,0,0))
#define HOSSVC_HAS_TC (hosversionAtLeast(5,0,0))
#define NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD 0x80044715
Result nvCheck = 1;
u32 fd = 0;
static SysClkSocType g_socType = SysClkSocType_Erista;
@@ -121,11 +117,6 @@ void Board::Initialize()
rc = tmp451Initialize();
ASSERT_RESULT_OK(rc, "tmp451Initialize");
// u32 fd = 0;
// if (R_SUCCEEDED(nvInitialize())) nvCheck = nvOpen(&fd, "/dev/nvhost-ctrl-gpu");
FetchHardwareInfos();
}
@@ -150,7 +141,6 @@ void Board::Exit()
max17050Exit();
tmp451Exit();
nvExit();
}
SysClkProfile Board::GetProfile()
@@ -473,23 +463,16 @@ std::int32_t Board::GetPowerMw(SysClkPowerSensor sensor)
return 0;
}
std::uint32_t Board::GetPartLoad(SysClkPartLoad loadSource)
std::uint32_t Board::GetRamLoad(SysClkRamLoad loadSource)
{
// u32 temp, GPU_Load_u = 0;
switch(loadSource)
{
case SysClkPartLoad_EMC:
case SysClkRamLoad_All:
return t210EmcLoadAll();
case SysClkPartLoad_EMCCpu:
case SysClkRamLoad_Cpu:
return t210EmcLoadCpu();
// case HocClkPartLoad_GPU:
// #define gpu_samples_average 10
// // nvIoctl(fd, NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD, &temp);
// GPU_Load_u = ((GPU_Load_u * (gpu_samples_average-1)) + temp) / gpu_samples_average;
// return GPU_Load_u / 10;
default:
ASSERT_ENUM_VALID(SysClkPartLoad, loadSource);
ASSERT_ENUM_VALID(SysClkRamLoad, loadSource);
}
return 0;
@@ -513,10 +496,15 @@ void Board::FetchHardwareInfos()
switch(sku)
{
case 2 ... 5:
case 2:
case 3:
case 5:
g_socType = SysClkSocType_Mariko;
break;
case 4:
g_socType = SysClkSocType_MarikoLite;
break;
default:
g_socType = SysClkSocType_Erista;
}
}
}

2
Source/sys-clk/sysmodule/src/board.h
View File

@@ -51,7 +51,7 @@ class Board
static void GetFreqList(SysClkModule module, std::uint32_t* outList, std::uint32_t maxCount, std::uint32_t* outCount);
static std::uint32_t GetTemperatureMilli(SysClkThermalSensor sensor);
static std::int32_t GetPowerMw(SysClkPowerSensor sensor);
static std::uint32_t GetPartLoad(SysClkPartLoad load);
static std::uint32_t GetRamLoad(SysClkRamLoad load);
static SysClkSocType GetSocType();
protected:

152
Source/sys-clk/sysmodule/src/clock_manager.cpp
View File

@@ -24,7 +24,6 @@
* --------------------------------------------------------------------------
*/
#include "notification.h"
#include "clock_manager.h"
#include <cstring>
@@ -36,10 +35,6 @@
#define HOSPPC_HAS_BOOST (hosversionAtLeast(7,0,0))
bool HAS_TDP_BEEN_FIRED = false;
bool HAS_EBL_BEEN_FIRED = false;
bool HAS_TT_BEEN_FIRED = false;
ClockManager *ClockManager::instance = NULL;
ClockManager *ClockManager::GetInstance()
@@ -233,92 +228,41 @@ void ClockManager::RefreshFreqTableRow(SysClkModule module)
void ClockManager::Tick()
{
std::uint32_t mode = 0;
AppletOperationMode opMode = appletGetOperationMode();
Result rc = apmExtGetCurrentPerformanceConfiguration(&mode);
ASSERT_RESULT_OK(rc, "apmExtGetCurrentPerformanceConfiguration");
if(this->config->GetConfigValue(HocClkConfigValue_EMCDVFS)) {
#define DEFAULT_FREQ_MHZ 1600
#define DEFAULT_FREQ_MHZ_M 1862
int ram_mhz = Board::GetHz((SysClkModule)SysClkModule_MEM) / 1000000;
if (Board::GetSocType() == SysClkSocType_Mariko) {
if(ram_mhz > DEFAULT_FREQ_MHZ_M)
set_sd1_voltage(this->config->GetConfigValue(HocClkConfigValue_EMCVdd2VoltageUV));
else
set_sd1_voltage(this->config->GetConfigValue(HocClkConfigValue_EMCVdd2VoltageUVStockMariko));
} else {
if(ram_mhz > DEFAULT_FREQ_MHZ)
set_sd1_voltage(this->config->GetConfigValue(HocClkConfigValue_EMCVdd2VoltageUV));
else
set_sd1_voltage(this->config->GetConfigValue(HocClkConfigValue_EMCVdd2VoltageUVStockErista));
}
}
if(this->config->GetConfigValue(HocClkConfigValue_HandheldTDP) && opMode == AppletOperationMode_Handheld) {
if(Board::GetSocType() == SysClkSocType_MarikoLite) {
if(Board::GetPowerMw(SysClkPowerSensor_Avg) < -(int)this->config->GetConfigValue(HocClkConfigValue_LiteTDPLimit)) {
if(!HAS_TDP_BEEN_FIRED)
writeNotification("Horizon OC\nTDP has been activated");
HAS_TDP_BEEN_FIRED = true;
ResetToStockClocks();
return;
} else {
HAS_TDP_BEEN_FIRED = false;
}
} else {
if(Board::GetPowerMw(SysClkPowerSensor_Avg) < -(int)this->config->GetConfigValue(HocClkConfigValue_HandheldTDPLimit)) {
if(!HAS_TDP_BEEN_FIRED)
writeNotification("Horizon OC\nTDP has been activated");
HAS_TDP_BEEN_FIRED = true;
ResetToStockClocks();
return;
} else {
HAS_TDP_BEEN_FIRED = false;
}
}
} else if(opMode == AppletOperationMode_Console && this->config->GetConfigValue(HocClkConfigValue_EnforceBoardLimit)) {
if(Board::GetPowerMw(SysClkPowerSensor_Avg) < 0) {
if(!HAS_EBL_BEEN_FIRED)
writeNotification("Horizon OC\nBoard Limit has been exeeded");
HAS_EBL_BEEN_FIRED = true;
ResetToStockClocks();
return;
} else {
HAS_EBL_BEEN_FIRED = false;
}
}
if(this->config->GetConfigValue(HocClkConfigValue_ThermalThrottle)) {
if(tmp451TempSoc() / 1000 > (int)this->config->GetConfigValue(HocClkConfigValue_ThermalThrottleThreshold)) {
if(!HAS_TT_BEEN_FIRED)
writeNotification("Horizon OC\nThermal Throttle has started");
HAS_TT_BEEN_FIRED = true;
ResetToStockClocks();
return;
} else {
HAS_TT_BEEN_FIRED = false;
}
}
std::scoped_lock lock{this->contextMutex};
if (this->RefreshContext() || this->config->Refresh())
{
std::uint32_t targetHz = 0;
std::uint32_t maxHz = 0;
std::uint32_t nearestHz = 0;
std::uint32_t mode = 0;
AppletOperationMode opMode = appletGetOperationMode();
Result rc = apmExtGetCurrentPerformanceConfiguration(&mode);
ASSERT_RESULT_OK(rc, "apmExtGetCurrentPerformanceConfiguration");
if(this->config->GetConfigValue(HocClkConfigValue_HandheldTDP) && opMode == AppletOperationMode_Handheld) {
if(Board::GetSocType() == SysClkSocType_MarikoLite) {
if(Board::GetPowerMw(SysClkPowerSensor_Now) < -(int)this->config->GetConfigValue(HocClkConfigValue_LiteTDPLimit)) {
ResetToStockClocks();
return;
}
} else {
if(Board::GetPowerMw(SysClkPowerSensor_Now) < -(int)this->config->GetConfigValue(HocClkConfigValue_HandheldTDPLimit)) {
ResetToStockClocks();
return;
}
}
}
if(apmExtIsBoostMode(mode) && !this->config->GetConfigValue(HocClkConfigValue_OverwriteBoostMode)) {
ResetToStockClocks();
return;
}
if(((tmp451TempSoc() / 1000) > (int)this->config->GetConfigValue(HocClkConfigValue_ThermalThrottleThreshold)) && this->config->GetConfigValue(HocClkConfigValue_ThermalThrottle)) {
ResetToStockClocks();
return;
}
if(this->config->GetConfigValue(HocClkConfigValue_HandheldGovernor) && opMode == AppletOperationMode_Handheld) {
}
@@ -482,9 +426,9 @@ bool ClockManager::RefreshContext()
}
// ram load do not and should not force a refresh, hasChanged untouched
for (unsigned int loadSource = 0; loadSource < SysClkPartLoad_EnumMax; loadSource++)
for (unsigned int loadSource = 0; loadSource < SysClkRamLoad_EnumMax; loadSource++)
{
this->context->partLoad[loadSource] = Board::GetPartLoad((SysClkPartLoad)loadSource);
this->context->ramLoad[loadSource] = Board::GetRamLoad((SysClkRamLoad)loadSource);
}
if (this->ConfigIntervalTimeout(SysClkConfigValue_CsvWriteIntervalMs, ns, &this->lastCsvWriteNs))
@@ -498,50 +442,4 @@ bool ClockManager::RefreshContext()
void ClockManager::SetRNXRTMode(ReverseNXMode mode)
{
this->rnxSync->SetRTMode(mode);
}
void ClockManager::set_sd1_voltage(uint32_t voltage_uv)
{
// SD1 parameters
const u32 uv_step = 12500;
const u32 uv_min = 600000;
const u32 uv_max = 1237500;
const u8 volt_addr = 0x17; // MAX77620_REG_SD1
const u8 volt_mask = 0x7F; // MAX77620_SD1_VOLT_MASK
if (voltage_uv < uv_min || voltage_uv > uv_max)
return;
u32 mult = (voltage_uv + uv_step - 1 - uv_min) / uv_step;
mult = mult & volt_mask;
I2cSession session;
Result res = i2cOpenSession(&session, I2cDevice_Max77620Pmic);
if (R_FAILED(res)) {
return;
}
u8 current_val = 0;
res = i2csessionSendAuto(&session, &volt_addr, 1, I2cTransactionOption_Start);
if (R_FAILED(res)) {
writeNotification("I2C write failed. This may be a hardware issue");
i2csessionClose(&session);
return;
}
res = i2csessionReceiveAuto(&session, &current_val, 1, I2cTransactionOption_Stop);
if (R_FAILED(res)) {
writeNotification("I2C write failed. This may be a hardware issue");
i2csessionClose(&session);
return;
}
// Mask in the new voltage bits, preserving other bits
u8 new_val = (current_val & ~volt_mask) | mult;
// Write back register with START and STOP conditions
u8 write_buf[2] = {volt_addr, new_val};
res = i2csessionSendAuto(&session, write_buf, sizeof(write_buf), I2cTransactionOption_All);
i2csessionClose(&session);
}

1
Source/sys-clk/sysmodule/src/clock_manager.h
View File

@@ -70,7 +70,6 @@ class ClockManager
bool ConfigIntervalTimeout(SysClkConfigValue intervalMsConfigValue, std::uint64_t ns, std::uint64_t* lastLogNs);
void RefreshFreqTableRow(SysClkModule module);
bool RefreshContext();
void set_sd1_voltage(uint32_t voltage_uv);
static ClockManager *instance;

114
Source/sys-clk/sysmodule/src/config.cpp
View File

@@ -15,8 +15,7 @@
*
*/
/*
* --------------------------------------------------------------------------
/* --------------------------------------------------------------------------
* "THE BEER-WARE LICENSE" (Revision 42):
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
* wrote this file. As long as you retain this notice you can do whatever you
@@ -25,6 +24,7 @@
* --------------------------------------------------------------------------
*/
#include "config.h"
#include <sys/types.h>
#include <sys/stat.h>
@@ -197,24 +197,17 @@ bool Config::SetProfiles(std::uint64_t tid, SysClkTitleProfileList* profiles, bo
std::scoped_lock lock{this->configMutex};
uint8_t numProfiles = 0;
// String pointer array passed to ini
char* iniKeys[SysClkProfile_EnumMax * SysClkModule_EnumMax + 1];
char* iniValues[SysClkProfile_EnumMax * SysClkModule_EnumMax + 1];
// Char arrays to build strings
char keysStr[SysClkProfile_EnumMax * SysClkModule_EnumMax * 0x40];
char valuesStr[SysClkProfile_EnumMax * SysClkModule_EnumMax * 0x10];
char section[17] = {0};
// Iteration pointers
char** ik = &iniKeys[0];
char** iv = &iniValues[0];
char* sk = &keysStr[0];
char* sv = &valuesStr[0];
std::uint32_t* mhz = &profiles->mhz[0];
snprintf(section, sizeof(section), "%016lX", tid);
// Use dynamic allocation
std::vector<std::string> keys;
std::vector<std::string> values;
keys.reserve(SysClkProfile_EnumMax * SysClkModule_EnumMax);
values.reserve(SysClkProfile_EnumMax * SysClkModule_EnumMax);
std::uint32_t* mhz = &profiles->mhz[0];
for(unsigned int profile = 0; profile < SysClkProfile_EnumMax; profile++)
{
for(unsigned int module = 0; module < SysClkModule_EnumMax; module++)
@@ -223,34 +216,38 @@ bool Config::SetProfiles(std::uint64_t tid, SysClkTitleProfileList* profiles, bo
{
numProfiles++;
// Put key and value as string
snprintf(sk, 0x40, "%s_%s", Board::GetProfileName((SysClkProfile)profile, false), Board::GetModuleName((SysClkModule)module, false));
snprintf(sv, 0x10, "%d", *mhz);
// Build key and value strings
std::string key = std::string(Board::GetProfileName((SysClkProfile)profile, false)) +
"_" +
Board::GetModuleName((SysClkModule)module, false);
std::string value = std::to_string(*mhz);
// Add them to the ini key/value str arrays
*ik = sk;
*iv = sv;
ik++;
iv++;
// We used those chars, get to the next ones
sk += 0x40;
sv += 0x10;
keys.push_back(key);
values.push_back(value);
}
mhz++;
}
}
*ik = NULL;
*iv = NULL;
// Build pointer arrays
std::vector<const char*> keyPointers;
std::vector<const char*> valuePointers;
keyPointers.reserve(keys.size() + 1);
valuePointers.reserve(values.size() + 1);
if(!ini_putsection(section, (const char**)iniKeys, (const char**)iniValues, this->path.c_str()))
for(size_t i = 0; i < keys.size(); i++) {
keyPointers.push_back(keys[i].c_str());
valuePointers.push_back(values[i].c_str());
}
keyPointers.push_back(NULL);
valuePointers.push_back(NULL);
if(!ini_putsection(section, keyPointers.data(), valuePointers.data(), this->path.c_str()))
{
return false;
}
// Only actually apply changes in memory after a succesful save
// Only actually apply changes in memory after a successful save
if(immediate)
{
mhz = &profiles->mhz[0];
@@ -431,46 +428,43 @@ bool Config::SetConfigValues(SysClkConfigValueList* configValues, bool immediate
{
std::scoped_lock lock{this->configMutex};
// String pointer array passed to ini
const char* iniKeys[SysClkConfigValue_EnumMax + 1];
char* iniValues[SysClkConfigValue_EnumMax + 1];
// char arrays to build strings
char valuesStr[SysClkConfigValue_EnumMax * 0x20];
// Iteration pointers
char* sv = &valuesStr[0];
const char** ik = &iniKeys[0];
char** iv = &iniValues[0];
// Use dynamic allocation instead of fixed stack buffers
std::vector<const char*> iniKeys;
std::vector<std::string> iniValues;
iniKeys.reserve(SysClkConfigValue_EnumMax + 1);
iniValues.reserve(SysClkConfigValue_EnumMax);
for(unsigned int kval = 0; kval < SysClkConfigValue_EnumMax; kval++)
{
if(!sysclkValidConfigValue((SysClkConfigValue)kval, configValues->values[kval]) || configValues->values[kval] == sysclkDefaultConfigValue((SysClkConfigValue)kval))
if(!sysclkValidConfigValue((SysClkConfigValue)kval, configValues->values[kval]) ||
configValues->values[kval] == sysclkDefaultConfigValue((SysClkConfigValue)kval))
{
continue;
}
// Put key and value as string
// And add them to the ini key/value str arrays
snprintf(sv, 0x20, "%ld", configValues->values[kval]);
*ik = sysclkFormatConfigValue((SysClkConfigValue)kval, false);
*iv = sv;
// We used those chars, get to the next ones
sv += 0x20;
ik++;
iv++;
// Store as string in vector (automatically managed memory)
iniValues.push_back(std::to_string(configValues->values[kval]));
iniKeys.push_back(sysclkFormatConfigValue((SysClkConfigValue)kval, false));
}
*ik = NULL;
*iv = NULL;
// Null terminate
iniKeys.push_back(NULL);
if(!ini_putsection(CONFIG_VAL_SECTION, (const char**)iniKeys, (const char**)iniValues, this->path.c_str()))
// Build pointer array for ini function
std::vector<const char*> valuePointers;
valuePointers.reserve(iniValues.size() + 1);
for(const auto& val : iniValues) {
valuePointers.push_back(val.c_str());
}
valuePointers.push_back(NULL);
if(!ini_putsection(CONFIG_VAL_SECTION, iniKeys.data(), valuePointers.data(), this->path.c_str()))
{
return false;
}
// Only actually apply changes in memory after a succesful save
// Only actually apply changes in memory after a successful save
if(immediate)
{
for(unsigned int kval = 0; kval < SysClkConfigValue_EnumMax; kval++)

0
Source/sys-clk/sysmodule/src/emc.cpp Normal file
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0
Source/sys-clk/sysmodule/src/emc.h Normal file
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91
Source/sys-clk/sysmodule/src/emc_patcher.cpp
View File

@@ -1,91 +0,0 @@
#include "emc_patcher.h"
#include "file_utils.h"
#include "board.h"
#define MC_BASE 0x70019000
#define EMC_BASE 0x7001B000
#define MC_EMC_BASE_SIZE 0x1000
#define EMC_TIMING_CONTROL_0 0x28
#define EMC_RAS_0 0x34
#define EMC_RAS_BIT_END 5
#define HOSSVC_HAS_MM (hosversionAtLeast(10,0,0))
EMCpatcher* EMCpatcher::instance = nullptr;
EMCpatcher* EMCpatcher::GetInstance()
{
return instance;
}
void EMCpatcher::Initialize()
{
if (!instance)
{
instance = new EMCpatcher();
FileUtils::LogLine("[emc] Initialized EMCpatcher");
}
}
Config *EMCpatcher::GetConfig()
{
return this->config;
}
void EMCpatcher::Exit()
{
if (instance)
{
FileUtils::LogLine("[emc] Exiting EMCpatcher");
delete instance;
instance = nullptr;
}
}
EMCpatcher::EMCpatcher()
{
this->config = Config::CreateDefault();
}
EMCpatcher::~EMCpatcher()
{
delete this->config;
}
void EMCpatcher::Run()
{
std::scoped_lock lock{this->patcherMutex};
this->config->Refresh();
this->ApplyEMCPatch();
}
void EMCpatcher::ApplyEMCPatch()
{
// if(HOSSVC_HAS_MM) { // only for 10.0.0+, older versions need rewrites
// u64 mc_virt_addr = 0;
// u64 mc_out_size = 0;
// u64 emc_virt_addr = 0;
// u64 emc_out_size = 0;
// Result rc;
// // rc = svcQueryMemoryMapping(&mc_virt_addr, &mc_out_size, MC_BASE, MC_EMC_BASE_SIZE); // map mc
// // ASSERT_RESULT_OK(rc, "svcQueryMemoryMapping");
// // rc = svcQueryMemoryMapping(&emc_virt_addr, &emc_out_size, EMC_BASE, MC_EMC_BASE_SIZE); // map emc
// // ASSERT_RESULT_OK(rc, "svcQueryMemoryMapping");
// write_reg64(EMC_BASE, EMC_RAS_0, 1);
// write_reg64(EMC_BASE, EMC_TIMING_CONTROL_0, 0x1); // apply shadow regs
// // svcUnmapMemory((void *)mc_virt_addr, (void *)MC_BASE, MC_EMC_BASE_SIZE); // clean up
// // svcUnmapMemory((void *)emc_virt_addr, (void *)EMC_BASE, MC_EMC_BASE_SIZE);
// }
}

73
Source/sys-clk/sysmodule/src/emc_patcher.h
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@@ -1,73 +0,0 @@
#pragma once
#include <mutex>
#include <cstdint>
#include "config.h"
#include <array>
#include "errors.h"
// Read a 32-bit register via libnx SVC
static inline uint32_t read_reg64(uint64_t phys_addr, uint32_t offset) {
uint32_t value = 0;
Result rc = svcReadWriteRegister(&value, phys_addr + offset, 0, false);
if (R_FAILED(rc)) {
// Handle failure if needed
return 0;
}
return value;
}
// Write a 32-bit register via libnx SVC
static inline void write_reg64(uint64_t phys_addr, uint32_t offset, uint32_t value) {
Result rc = svcReadWriteRegister(NULL, phys_addr + offset, value, true);
if (R_FAILED(rc)) {
// Handle failure if needed
}
}
// Bitfield helper remains the same
static inline uint32_t set_bits(uint32_t reg_value, uint8_t start_bit, uint8_t end_bit, uint32_t value)
{
if (end_bit < start_bit || end_bit > 31)
return reg_value;
uint32_t mask = ((1u << (end_bit - start_bit + 1)) - 1u) << start_bit;
reg_value = (reg_value & ~mask) | ((value << start_bit) & mask);
return reg_value;
}
/* Primary timings. */
const std::array<double, 8> tRCD_values = {18, 17, 16, 15, 14, 13, 12, 11};
const std::array<double, 8> tRP_values = {18, 17, 16, 15, 14, 13, 12, 11};
const std::array<double, 10> tRAS_values = {42, 36, 34, 32, 30, 28, 26, 24, 22, 20};
/* Secondary timings. */
const std::array<double, 8> tRRD_values = {10.0, 7.5, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0};
const std::array<double, 6> tRFC_values = {140, 120, 100, 80, 60, 40};
const std::array<u32, 10> tRTW_values = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; /* Is this even correct? */
const std::array<double, 10> tWTR_values = {10, 9, 8, 7, 6, 5, 4, 3, 2, 1};
const std::array<u32, 7> tREFpb_values = {488, 732, 488 * 2, 488 * 3, 488 * 4, 488 * 6, 488 * 8}; /* TODO: Figure out if it's actually 8 and if this is even right. */
struct SOC_THERM_THERMCTL_LEVEL0_GROUP_CPU_0 {
};
class EMCpatcher
{
private:
static EMCpatcher* instance;
Config* config;
std::mutex patcherMutex;
public:
static EMCpatcher* GetInstance();
static void Initialize();
Config *GetConfig();
static void Exit();
EMCpatcher();
~EMCpatcher();
void Run();
void ApplyEMCPatch();
};

14
Source/sys-clk/sysmodule/src/ipc_service.cpp
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@@ -31,8 +31,6 @@
#include "file_utils.h"
#include "errors.h"
#include "clock_manager.h"
#include "emc_patcher.h"
IpcService::IpcService(ClockManager* clockMgr)
{
std::int32_t priority;
@@ -191,9 +189,6 @@ Result IpcService::ServiceHandlerFunc(void* arg, const IpcServerRequest* r, u8*
return ipcSrv->SetReverseNXRTMode(mode);
}
break;
case HocClkIpcCmd_UpdateEMCRegs: // Trigger, not data
return ipcSrv->PatchEmcRegs();
break;
}
return SYSCLK_ERROR(Generic);
@@ -230,7 +225,6 @@ Result IpcService::Exit()
return 0;
}
Result IpcService::GetProfileCount(std::uint64_t* tid, std::uint8_t* out_count)
{
Config* config = this->clockMgr->GetConfig();
@@ -269,7 +263,7 @@ Result IpcService::SetProfiles(SysClkIpc_SetProfiles_Args* args)
if(!config->SetProfiles(args->tid, &profiles, true))
{
return SYSCLK_ERROR(ConfigSaveFailed); // 0x584
return SYSCLK_ERROR(ConfigSaveFailed);
}
return 0;
@@ -351,9 +345,3 @@ Result IpcService::SetReverseNXRTMode(ReverseNXMode mode) {
ClockManager::GetInstance()->SetRNXRTMode(mode);
return 0;
}
Result IpcService::PatchEmcRegs() {
EMCpatcher::GetInstance()->Run();
return 0;
}

2
Source/sys-clk/sysmodule/src/ipc_service.h
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@@ -54,8 +54,6 @@ class IpcService
Result SetConfigValues(SysClkConfigValueList* configValues);
Result GetFreqList(SysClkIpc_GetFreqList_Args* args, std::uint32_t* out_list, std::size_t size, std::uint32_t* out_count);
Result SetReverseNXRTMode(ReverseNXMode mode);
Result PatchEmcRegs();
bool running;
Thread thread;

30
Source/sys-clk/sysmodule/src/main.cpp
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@@ -38,9 +38,7 @@
#include "clock_manager.h"
#include "ipc_service.h"
#include "fancontrol.h"
#include "emc_patcher.h"
#define INNER_HEAP_SIZE 0x50000
#define INNER_HEAP_SIZE 0x30000
extern "C"
{
@@ -68,22 +66,12 @@ extern "C"
void __appInit(void)
{
Result rc;
if (R_FAILED(smInitialize()))
{
fatalThrow(MAKERESULT(Module_Libnx, LibnxError_InitFail_SM));
}
rc = fanInitialize();
if (R_FAILED(rc))
diagAbortWithResult(MAKERESULT(Module_Libnx, LibnxError_ShouldNotHappen));
rc = i2cInitialize();
if (R_FAILED(rc))
diagAbortWithResult(MAKERESULT(Module_Libnx, LibnxError_ShouldNotHappen));
rc = setsysInitialize();
Result rc = setsysInitialize();
if (R_SUCCEEDED(rc))
{
SetSysFirmwareVersion fw;
@@ -92,7 +80,14 @@ extern "C"
hosversionSet(MAKEHOSVERSION(fw.major, fw.minor, fw.micro));
setsysExit();
}
rc = fanInitialize();
if (R_FAILED(rc))
diagAbortWithResult(MAKERESULT(Module_Libnx, LibnxError_ShouldNotHappen));
rc = i2cInitialize();
if (R_FAILED(rc))
diagAbortWithResult(MAKERESULT(Module_Libnx, LibnxError_ShouldNotHappen));
}
void __appExit(void)
@@ -101,8 +96,7 @@ extern "C"
fanExit();
i2cExit();
fsExit();
fsdevUnmountAll();
smExit();
fsdevUnmountAll();
}
}
@@ -125,7 +119,7 @@ int main(int argc, char** argv)
ClockManager* clockMgr = new ClockManager();
IpcService* ipcSrv = new IpcService(clockMgr);
FileUtils::LogLine("Starting Horizon OC Sysmodule");
FileUtils::LogLine("Ready");
clockMgr->SetRunning(true);
clockMgr->GetConfig()->SetEnabled(true);

691
Source/sys-clk/sysmodule/src/maxXXXXX.h
View File

@@ -1,691 +0,0 @@
/*
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/*
* Defining registers address and its bit definitions of MAX77620 and MAX20024
*
* Copyright (c) 2019-2020 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <switch.h>
#ifndef MAX77XXX_H
#define MAX77XXX_H
#define MAX17050_BOARD_CGAIN 2 /* Actual: 1.99993 */
#define MAX17050_BOARD_SNS_RESISTOR_UOHM 5000 /* 0.005 Ohm */
#define MAX17050_STATUS_BattAbsent BIT(3)
/* Consider RepCap which is less then 10 units below FullCAP full */
#define MAX17050_FULL_THRESHOLD 10
#define MAX17050_CHARACTERIZATION_DATA_SIZE 48
#define MAXIM17050_I2C_ADDR 0x36
enum MAX17050_reg {
MAX17050_STATUS = 0x00,
MAX17050_VALRT_Th = 0x01,
MAX17050_TALRT_Th = 0x02,
MAX17050_SALRT_Th = 0x03,
MAX17050_AtRate = 0x04,
MAX17050_RepCap = 0x05,
MAX17050_RepSOC = 0x06,
MAX17050_Age = 0x07,
MAX17050_TEMP = 0x08,
MAX17050_VCELL = 0x09,
MAX17050_Current = 0x0A,
MAX17050_AvgCurrent = 0x0B,
MAX17050_SOC = 0x0D,
MAX17050_AvSOC = 0x0E,
MAX17050_RemCap = 0x0F,
MAX17050_FullCAP = 0x10,
MAX17050_TTE = 0x11,
MAX17050_QRTbl00 = 0x12,
MAX17050_FullSOCThr = 0x13,
MAX17050_RSLOW = 0x14,
MAX17050_AvgTA = 0x16,
MAX17050_Cycles = 0x17,
MAX17050_DesignCap = 0x18,
MAX17050_AvgVCELL = 0x19,
MAX17050_MinMaxTemp = 0x1A,
MAX17050_MinMaxVolt = 0x1B,
MAX17050_MinMaxCurr = 0x1C,
MAX17050_CONFIG = 0x1D,
MAX17050_ICHGTerm = 0x1E,
MAX17050_AvCap = 0x1F,
MAX17050_ManName = 0x20,
MAX17050_DevName = 0x21,
MAX17050_QRTbl10 = 0x22,
MAX17050_FullCAPNom = 0x23,
MAX17050_TempNom = 0x24,
MAX17050_TempLim = 0x25,
MAX17050_TempHot = 0x26,
MAX17050_AIN = 0x27,
MAX17050_LearnCFG = 0x28,
MAX17050_FilterCFG = 0x29,
MAX17050_RelaxCFG = 0x2A,
MAX17050_MiscCFG = 0x2B,
MAX17050_TGAIN = 0x2C,
MAX17050_TOFF = 0x2D,
MAX17050_CGAIN = 0x2E,
MAX17050_COFF = 0x2F,
MAX17050_QRTbl20 = 0x32,
MAX17050_SOC_empty = 0x33,
MAX17050_T_empty = 0x34,
MAX17050_FullCAP0 = 0x35,
MAX17050_LAvg_empty = 0x36,
MAX17050_FCTC = 0x37,
MAX17050_RCOMP0 = 0x38,
MAX17050_TempCo = 0x39,
MAX17050_V_empty = 0x3A,
MAX17050_K_empty0 = 0x3B,
MAX17050_TaskPeriod = 0x3C,
MAX17050_FSTAT = 0x3D,
MAX17050_TIMER = 0x3E,
MAX17050_SHDNTIMER = 0x3F,
MAX17050_QRTbl30 = 0x42,
MAX17050_dQacc = 0x45,
MAX17050_dPacc = 0x46,
MAX17050_VFSOC0 = 0x48,
Max17050_QH0 = 0x4C,
MAX17050_QH = 0x4D,
MAX17050_QL = 0x4E,
MAX17050_MinVolt = 0x50, // Custom ID. Not to be sent to i2c.
MAX17050_MaxVolt = 0x51, // Custom ID. Not to be sent to i2c.
MAX17050_VFSOC0Enable = 0x60,
MAX17050_MODELEnable1 = 0x62,
MAX17050_MODELEnable2 = 0x63,
MAX17050_MODELChrTbl = 0x80,
MAX17050_OCV = 0xEE,
MAX17050_OCVInternal = 0xFB,
MAX17050_VFSOC = 0xFF,
};
#define MAX77620_I2C_ADDR 0x3C
/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
#define MAX77620_REG_CNFGGLBL1 0x00
#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
#define MAX77620_CNFGGLBL1_LBDAC_MASK 0x0E
#define MAX77620_CNFGGLBL1_LBDAC_2700 (0 << 1)
#define MAX77620_CNFGGLBL1_LBDAC_2800 (1 << 1)
#define MAX77620_CNFGGLBL1_LBDAC_2900 (2 << 1)
#define MAX77620_CNFGGLBL1_LBDAC_3000 (3 << 1)
#define MAX77620_CNFGGLBL1_LBDAC_3100 (4 << 1)
#define MAX77620_CNFGGLBL1_LBDAC_3200 (5 << 1)
#define MAX77620_CNFGGLBL1_LBDAC_3300 (6 << 1)
#define MAX77620_CNFGGLBL1_LBDAC_3400 (7 << 1)
#define MAX77620_CNFGGLBL1_LBHYST_100 (0 << 4)
#define MAX77620_CNFGGLBL1_LBHYST_200 (1 << 4)
#define MAX77620_CNFGGLBL1_LBHYST_300 (2 << 4)
#define MAX77620_CNFGGLBL1_LBHYST_400 (3 << 4)
#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
#define MAX77620_REG_CNFGGLBL2 0x01
#define MAX77620_TWD_MASK 0x3
#define MAX77620_TWD_2s 0x0
#define MAX77620_TWD_16s 0x1
#define MAX77620_TWD_64s 0x2
#define MAX77620_TWD_128s 0x3
#define MAX77620_WDTEN BIT(2)
#define MAX77620_WDTSLPC BIT(3)
#define MAX77620_WDTOFFC BIT(4)
#define MAX77620_GLBL_LPM BIT(5)
#define MAX77620_I2CTWD_MASK 0xC0
#define MAX77620_I2CTWD_DISABLED 0x00
#define MAX77620_I2CTWD_1_33ms 0x40
#define MAX77620_I2CTWD_35_7ms 0x80
#define MAX77620_I2CTWD_41_7ms 0xC0
#define MAX77620_REG_CNFGGLBL3 0x02
#define MAX77620_WDTC_MASK 0x3
#define MAX77620_REG_CNFG1_32K 0x03
#define MAX77620_CNFG1_PWR_MD_32K_MASK 0x3
#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
#define MAX77620_CNFG1_32KLOAD_MASK 0x30
#define MAX77620_CNFG1_32K_OK BIT(7)
#define MAX77620_REG_CNFGBBC 0x04
#define MAX77620_CNFGBBC_ENABLE BIT(0)
#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
#define MAX77620_CNFGBBC_RESISTOR_100 (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
#define MAX77620_CNFGBBC_RESISTOR_1K (1 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
#define MAX77620_CNFGBBC_RESISTOR_3K (2 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
#define MAX77620_CNFGBBC_RESISTOR_6K (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
#define MAX77620_REG_IRQTOP 0x05
#define MAX77620_REG_IRQTOPM 0x0D
#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
#define MAX77620_REG_INTLBT 0x06
#define MAX77620_REG_INTENLBT 0x0E
#define MAX77620_IRQ_GLBLM_MASK BIT(0)
#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
#define MAX77620_IRQ_LBM_MASK BIT(3)
#define MAX77620_REG_IRQSD 0x07
#define MAX77620_REG_IRQMASKSD 0x0F
#define MAX77620_IRQSD_PFI_SD3 BIT(4)
#define MAX77620_IRQSD_PFI_SD2 BIT(5)
#define MAX77620_IRQSD_PFI_SD1 BIT(6)
#define MAX77620_IRQSD_PFI_SD0 BIT(7)
#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 // LDO number that irq occurred.
#define MAX77620_REG_IRQ_MSK_L0_7 0x10
#define MAX77620_REG_IRQ_LVL2_L8 \
0x09 // LDO number that irq occurred. Only bit0: LDO8 is valid.
#define MAX77620_REG_IRQ_MSK_L8 0x11
#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A // Edge detection interrupt.
#define MAX77620_REG_ONOFFIRQ 0x0B
#define MAX77620_REG_ONOFFIRQM 0x12
#define MAX77620_ONOFFIRQ_MRWRN BIT(0)
#define MAX77620_ONOFFIRQ_EN0_1SEC BIT(1)
#define MAX77620_ONOFFIRQ_EN0_F BIT(2)
#define MAX77620_ONOFFIRQ_EN0_R BIT(3)
#define MAX77620_ONOFFIRQ_LID_F BIT(4)
#define MAX77620_ONOFFIRQ_LID_R BIT(5)
#define MAX77620_ONOFFIRQ_ACOK_F BIT(6)
#define MAX77620_ONOFFIRQ_ACOK_R BIT(7)
#define MAX77620_REG_NVERC 0x0C // Shutdown reason (non-volatile).
#define MAX77620_NVERC_SHDN BIT(0)
#define MAX77620_NVERC_WTCHDG BIT(1)
#define MAX77620_NVERC_HDRST BIT(2)
#define MAX77620_NVERC_TOVLD BIT(3)
#define MAX77620_NVERC_MBLSD BIT(4)
#define MAX77620_NVERC_MBO BIT(5)
#define MAX77620_NVERC_MBU BIT(6)
#define MAX77620_NVERC_RSTIN BIT(7)
#define MAX77620_REG_STATLBT 0x13
#define MAX77620_REG_STATSD 0x14
#define MAX77620_REG_ONOFFSTAT 0x15
#define MAX77620_ONOFFSTAT_LID BIT(0)
#define MAX77620_ONOFFSTAT_ACOK BIT(1)
#define MAX77620_ONOFFSTAT_EN0 BIT(2)
/* SD and LDO Registers */
#define MAX77620_REG_SD0 0x16
#define MAX77620_REG_SD1 0x17
#define MAX77620_REG_SD2 0x18
#define MAX77620_REG_SD3 0x19
#define MAX77620_REG_SD4 0x1A
#define MAX77620_REG_DVSSD0 0x1B
#define MAX77620_REG_DVSSD1 0x1C
#define MAX77620_SDX_VOLT_MASK 0xFF
#define MAX77620_SD0_VOLT_MASK 0x7F // Max is 0x40.
#define MAX77620_SD1_VOLT_MASK 0x7F // Max is 0x4C.
#define MAX77620_LDO_VOLT_MASK 0x3F
#define MAX77620_REG_SD0_CFG 0x1D
#define MAX77620_REG_SD1_CFG 0x1E
#define MAX77620_REG_SD2_CFG 0x1F
#define MAX77620_REG_SD3_CFG 0x20
#define MAX77620_REG_SD4_CFG 0x21
#define MAX77620_SD_SR_MASK 0xC0
#define MAX77620_SD_SR_SHIFT 6
#define MAX77620_SD_POWER_MODE_MASK 0x30
#define MAX77620_SD_POWER_MODE_SHIFT 4
#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
#define MAX77620_SD_CFG1_ADE_DISABLE 0
#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
#define MAX77620_SD_FPWM_MASK 0x04
#define MAX77620_SD_FPWM_SHIFT 2
#define MAX77620_SD_FSRADE_MASK 0x01
#define MAX77620_SD_FSRADE_SHIFT 0
#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
#define MAX77620_SD_CFG1_MPOK_MASK BIT(1)
#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
#define MAX77620_REG_SD_CFG2 0x22
#define MAX77620_SD_CNF2_RSVD BIT(0)
#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
#define MAX77620_REG_LDO0_CFG 0x23
#define MAX77620_REG_LDO0_CFG2 0x24
#define MAX77620_REG_LDO1_CFG 0x25
#define MAX77620_REG_LDO1_CFG2 0x26
#define MAX77620_REG_LDO2_CFG 0x27
#define MAX77620_REG_LDO2_CFG2 0x28
#define MAX77620_REG_LDO3_CFG 0x29
#define MAX77620_REG_LDO3_CFG2 0x2A
#define MAX77620_REG_LDO4_CFG 0x2B
#define MAX77620_REG_LDO4_CFG2 0x2C
#define MAX77620_REG_LDO5_CFG 0x2D
#define MAX77620_REG_LDO5_CFG2 0x2E
#define MAX77620_REG_LDO6_CFG 0x2F
#define MAX77620_REG_LDO6_CFG2 0x30
#define MAX77620_REG_LDO7_CFG 0x31
#define MAX77620_REG_LDO7_CFG2 0x32
#define MAX77620_REG_LDO8_CFG 0x33
#define MAX77620_REG_LDO8_CFG2 0x34
/*! LDO CFG */
#define MAX77620_LDO_POWER_MODE_SHIFT 6
#define MAX77620_LDO_POWER_MODE_MASK (3 << MAX77620_LDO_POWER_MODE_SHIFT)
#define MAX77620_POWER_MODE_NORMAL 3
#define MAX77620_POWER_MODE_LPM 2
#define MAX77620_POWER_MODE_GLPM 1
#define MAX77620_POWER_MODE_DISABLE 0
/*! LDO CFG2 */
#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
#define MAX77620_LDO_CFG2_SS_FAST (0 << 0)
#define MAX77620_LDO_CFG2_SS_SLOW (1 << 0)
#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1)
#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
#define MAX77620_LDO_CFG2_MPOK_MASK BIT(2)
#define MAX77620_LDO_CFG2_POK_MASK BIT(3)
#define MAX77620_LDO_CFG2_COMP_SHIFT 4
#define MAX77620_LDO_CFG2_COMP_MASK (3 << MAX77620_LDO_COMP_SHIFT)
#define MAX77620_LDO_CFG2_COMP_SLOW 3
#define MAX77620_LDO_CFG2_COMP_MID_SLOW 2
#define MAX77620_LDO_CFG2_COMP_MID_FAST 1
#define MAX77620_LDO_CFG2_COMP_FAST 0
#define MAX77620_LDO_CFG2_ALPM_EN_MASK BIT(6)
#define MAX77620_LDO_CFG2_OVCLMP_MASK BIT(7)
#define MAX77620_REG_LDO_CFG3 0x35
#define MAX77620_LDO_BIAS_EN BIT(0)
#define MAX77620_TRACK4_SHIFT 5
#define MAX77620_TRACK4_MASK (1 << MAX77620_TRACK4_SHIFT)
#define MAX77620_REG_GPIO0 0x36
#define MAX77620_REG_GPIO1 0x37
#define MAX77620_REG_GPIO2 0x38
#define MAX77620_REG_GPIO3 0x39
#define MAX77620_REG_GPIO4 0x3A
#define MAX77620_REG_GPIO5 0x3B
#define MAX77620_REG_GPIO6 0x3C
#define MAX77620_REG_GPIO7 0x3D
#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0)
#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0)
#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN (0 << 0)
#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1)
#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1)
#define MAX77620_CNFG_GPIO_DIR_OUTPUT (0 << 1)
#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2)
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3)
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3)
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW (0 << 3)
#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4)
#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5)
#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
#define MAX77620_GPIO_OUTPUT_DISABLE 0
#define MAX77620_GPIO_OUTPUT_ENABLE 1
#define MAX77620_REG_PUE_GPIO 0x3E // Gpio Pullup resistor enable.
#define MAX77620_REG_PDE_GPIO 0x3F // Gpio Pulldown resistor enable.
#define MAX77620_REG_AME_GPIO \
0x40 // Gpio pinmuxing. Clear bits are Standard GPIO.
#define MAX77620_REG_ONOFFCNFG1 0x41
#define MAX20024_ONOFFCNFG1_CLRSE 0x18
#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
#define MAX77620_ONOFFCNFG1_RSVD BIT(6)
#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
#define MAX77620_REG_ONOFFCNFG2 0x42
#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
#define MAX77620_ONOFFCNFG2_WK_ALARM2 BIT(1)
#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
#define MAX77620_ONOFFCNFG2_WK_MBATT \
BIT(3) // MBATT event generates a wakeup signal. use it in android/l4t?
#define MAX77620_ONOFFCNFG2_WK_ACOK BIT(4)
#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
/* FPS Registers */
#define MAX77620_REG_FPS_CFG0 0x43 // FPS0.
#define MAX77620_REG_FPS_CFG1 0x44 // FPS1.
#define MAX77620_REG_FPS_CFG2 0x45 // FPS2.
#define MAX77620_FPS_ENFPS_SW_MASK 0x01
#define MAX77620_FPS_ENFPS_SW 0x01
#define MAX77620_FPS_EN_SRC_SHIFT 1
#define MAX77620_FPS_EN_SRC_MASK 0x06
#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
#define MAX77620_REG_FPS_LDO0 0x46
#define MAX77620_REG_FPS_LDO1 0x47
#define MAX77620_REG_FPS_LDO2 0x48
#define MAX77620_REG_FPS_LDO3 0x49
#define MAX77620_REG_FPS_LDO4 0x4A
#define MAX77620_REG_FPS_LDO5 0x4B
#define MAX77620_REG_FPS_LDO6 0x4C
#define MAX77620_REG_FPS_LDO7 0x4D
#define MAX77620_REG_FPS_LDO8 0x4E
#define MAX77620_REG_FPS_SD0 0x4F
#define MAX77620_REG_FPS_SD1 0x50
#define MAX77620_REG_FPS_SD2 0x51
#define MAX77620_REG_FPS_SD3 0x52
#define MAX77620_REG_FPS_SD4 0x53
#define MAX77620_REG_FPS_GPIO1 0x54
#define MAX77620_REG_FPS_GPIO2 0x55
#define MAX77620_REG_FPS_GPIO3 0x56
#define MAX77620_REG_FPS_RSO 0x57
#define MAX77620_FPS_PD_PERIOD_SHIFT 0
#define MAX77620_FPS_PD_PERIOD_MASK 0x07
#define MAX77620_FPS_PU_PERIOD_SHIFT 3
#define MAX77620_FPS_PU_PERIOD_MASK 0x38
#define MAX77620_FPS_SRC_SHIFT 6
#define MAX77620_FPS_SRC_MASK 0xC0
#define MAX77620_FPS_COUNT 3
#define MAX77620_FPS_PERIOD_MIN_US 40
#define MAX77620_FPS_PERIOD_MAX_US 2560
#define MAX77620_REG_CID0 0x58
#define MAX77620_REG_CID1 0x59
#define MAX77620_REG_CID2 0x5A
#define MAX77620_REG_CID3 0x5B
#define MAX77620_REG_CID4 0x5C // OTP version.
#define MAX77620_REG_CID5 0x5D // ES version.
#define MAX77620_CID_DIDO_MASK 0xF
#define MAX77620_CID_DIDO_SHIFT 0
#define MAX77620_CID_DIDM_MASK 0xF0
#define MAX77620_CID_DIDM_SHIFT 4
/* Device Identification Metal */
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
/* Device Indentification OTP */
#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
#define MAX77620_REG_DVSSD4 0x5E
#define MAX20024_REG_MAX_ADD 0x70
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
/* Interrupts */
enum {
MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
MAX77620_IRQ_TOP_SD, /* SD power fail */
MAX77620_IRQ_TOP_LDO, /* LDO power fail */
MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
MAX77620_IRQ_TOP_RTC, /* RTC */
MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
};
/* GPIOs */
enum {
MAX77620_GPIO0,
MAX77620_GPIO1,
MAX77620_GPIO2,
MAX77620_GPIO3,
MAX77620_GPIO4,
MAX77620_GPIO5,
MAX77620_GPIO6,
MAX77620_GPIO7,
MAX77620_GPIO_NR,
};
/* FPS Source */
enum max77620_fps_src {
MAX77620_FPS_SRC_0,
MAX77620_FPS_SRC_1,
MAX77620_FPS_SRC_2,
MAX77620_FPS_SRC_NONE,
MAX77620_FPS_SRC_DEF,
};
#define MAX77812_PHASE31_CPU_I2C_ADDR \
0x31 // High power GPU. 2 Outputs: 3-phase M1 + 1-phase M4.
#define MAX77812_PHASE211_CPU_I2C_ADDR \
0x33 // Low power GPU. 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
#define MAX77812_REG_RSET 0x00
#define MAX77812_REG_INT_SRC 0x01
#define MAX77812_REG_INT_SRC_M 0x02
#define MAX77812_REG_TOPSYS_INT 0x03
#define MAX77812_REG_TOPSYS_INT_M 0x04
#define MAX77812_REG_TOPSYS_STAT 0x05
#define MAX77812_REG_EN_CTRL 0x06
#define MAX77812_EN_CTRL_ENABLE 1
#define MAX77812_EN_CTRL_EN_M1_SHIFT 0
#define MAX77812_EN_CTRL_EN_M1_MASK (1 << MAX77812_EN_CTRL_EN_M1_SHIFT)
#define MAX77812_EN_CTRL_EN_M2_SHIFT 2
#define MAX77812_EN_CTRL_EN_M2_MASK (1 << MAX77812_EN_CTRL_EN_M2_SHIFT)
#define MAX77812_EN_CTRL_EN_M3_SHIFT 4
#define MAX77812_EN_CTRL_EN_M3_MASK (1 << MAX77812_EN_CTRL_EN_M3_SHIFT)
#define MAX77812_EN_CTRL_EN_M4_SHIFT 6
#define MAX77812_EN_CTRL_EN_M4_MASK (1 << MAX77812_EN_CTRL_EN_M4_SHIFT)
#define MAX77812_REG_STUP_DLY2 0x07
#define MAX77812_REG_STUP_DLY3 0x08
#define MAX77812_REG_STUP_DLY4 0x09
#define MAX77812_REG_SHDN_DLY1 0x0A
#define MAX77812_REG_SHDN_DLY2 0x0B
#define MAX77812_REG_SHDN_DLY3 0x0C
#define MAX77812_REG_SHDN_DLY4 0x0D
#define MAX77812_REG_WDTRSTB_DEB 0x0E
#define MAX77812_REG_GPI_FUNC 0x0F
#define MAX77812_REG_GPI_DEB1 0x10
#define MAX77812_REG_GPI_DEB2 0x11
#define MAX77812_REG_GPI_PD_CTRL 0x12
#define MAX77812_REG_PROT_CFG 0x13
#define MAX77812_REG_VERSION 0x14
#define MAX77812_REG_I2C_CFG 0x15
#define MAX77812_REG_BUCK_INT 0x20
#define MAX77812_REG_BUCK_INT_M 0x21
#define MAX77812_REG_BUCK_STAT 0x22
#define MAX77812_REG_M1_VOUT 0x23 // GPU.
#define MAX77812_REG_M2_VOUT 0x24
#define MAX77812_REG_M3_VOUT 0x25 // DRAM on PHASE211.
#define MAX77812_REG_M4_VOUT 0x26 // CPU.
#define MAX77812_REG_M1_VOUT_D 0x27
#define MAX77812_REG_M2_VOUT_D 0x28
#define MAX77812_REG_M3_VOUT_D 0x29
#define MAX77812_REG_M4_VOUT_D 0x2A
#define MAX77812_REG_M1_VOUT_S 0x2B
#define MAX77812_REG_M2_VOUT_S 0x2C
#define MAX77812_REG_M3_VOUT_S 0x2D
#define MAX77812_REG_M4_VOUT_S 0x2E
#define MAX77812_REG_M1_CFG 0x2F // HOS: M1_ILIM - 7.2A/4.8A.
#define MAX77812_REG_M2_CFG 0x30 // HOS: M2_ILIM - 7.2A/4.8A.
#define MAX77812_REG_M3_CFG 0x31 // HOS: M3_ILIM - 7.2A/4.8A.
#define MAX77812_REG_M4_CFG 0x32 // HOS: M4_ILIM - 7.2A/4.8A.
#define MAX77812_REG_GLB_CFG1 0x33 // HOS: B_SD_SR/B_SS_SR - 5mV/us.
#define MAX77812_REG_GLB_CFG2 0x34 // HOS: B_RD_SR/B_RU_SR - 5mV/us
#define MAX77812_REG_GLB_CFG3 0x35
/*! Protected area and settings only for MAX77812_ES2_VERSION */
#define MAX77812_REG_GLB_CFG4 0x36 // QS: 0xBB.
#define MAX77812_REG_GLB_CFG5 0x37 // QS: 0x39. ES2: Set to 0x3E.
#define MAX77812_REG_GLB_CFG6 0x38 // QS: 0x88. ES2: Set to 0x90.
#define MAX77812_REG_GLB_CFG7 0x39 // QS: 0x04.
#define MAX77812_REG_GLB_CFG8 0x3A // QS: 0x3A. ES2: Set to 0x3A.
#define MAX77812_REG_PROT_ACCESS 0xFD // 0x00: Lock, 0x5A: Unlock.
#define MAX77812_REG_UNKNOWN 0xFE
#define MAX77812_REG_EN_CTRL_MASK(n) BIT(n)
#define MAX77812_START_SLEW_RATE_MASK 0x07
#define MAX77812_SHDN_SLEW_RATE_MASK 0x70
#define MAX77812_RAMPUP_SLEW_RATE_MASK 0x07
#define MAX77812_RAMPDOWN_SLEW_RATE_MASK 0x70
#define MAX77812_SLEW_RATE_SHIFT 4
#define MAX77812_OP_ACTIVE_DISCHARGE_MASK BIT(7)
#define MAX77812_PEAK_CURRENT_LMT_MASK 0x70
#define MAX77812_SWITCH_FREQ_MASK 0x0C
#define MAX77812_FORCED_PWM_MASK BIT(1)
#define MAX77812_SLEW_RATE_CNTRL_MASK BIT(0)
#define MAX77812_START_SHD_DELAY_MASK 0x1F
#define MAX77812_VERSION_MASK 0x07
#define MAX77812_ES2_VERSION 0x04
#define MAX77812_QS_VERSION 0x05
#define MAX77812_BUCK_VOLT_MASK 0xFF
#define BQ24193_I2C_ADDR 0x6B
// REG 0 masks.
#define BQ24193_INCONFIG_INLIMIT_MASK (7 << 0)
#define BQ24193_INCONFIG_VINDPM_MASK 0x78
#define BQ24193_INCONFIG_HIZ_EN_MASK (1 << 7)
// REG 1 masks.
#define BQ24193_PORCONFIG_BOOST_MASK (1 << 0)
#define BQ24193_PORCONFIG_SYSMIN_MASK (7 << 1) // 3000uV HOS default.
#define BQ24193_PORCONFIG_CHGCONFIG_MASK (3 << 4)
#define BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN (1 << 4)
#define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1 << 6)
#define BQ24193_PORCONFIG_RESET_MASK (1 << 7)
// REG 2 masks.
#define BQ24193_CHRGCURR_20PCT_MASK (1 << 0)
#define BQ24193_CHRGCURR_ICHG_MASK 0xFC
// REG 3 masks.
#define BQ24193_PRECHRG_ITERM 0x0F
#define BQ24193_PRECHRG_IPRECHG 0xF0
// REG 4 masks.
#define BQ24193_CHRGVOLT_VTHRES (1 << 0)
#define BQ24193_CHRGVOLT_BATTLOW (1 << 1)
#define BQ24193_CHRGVOLT_VREG 0xFC
// REG 5 masks.
#define BQ24193_CHRGTERM_ISET_MASK (1 << 0)
#define BQ24193_CHRGTERM_CHGTIMER_MASK (3 << 1)
#define BQ24193_CHRGTERM_ENTIMER_MASK (1 << 3)
#define BQ24193_CHRGTERM_WATCHDOG_MASK (3 << 4)
#define BQ24193_CHRGTERM_TERM_ST_MASK (1 << 6)
#define BQ24193_CHRGTERM_TERM_EN_MASK (1 << 7)
// REG 6 masks.
#define BQ24193_IRTHERMAL_THERM_MASK (3 << 0)
#define BQ24193_IRTHERMAL_VCLAMP_MASK (7 << 2)
#define BQ24193_IRTHERMAL_BATTCOMP_MASK (7 << 5)
// REG 7 masks.
#define BQ24193_MISC_INT_MASK (3 << 0)
#define BQ24193_MISC_VSET_MASK (1 << 4)
#define BQ24193_MISC_BATFET_DI_MASK (1 << 5)
#define BQ24193_MISC_TMR2X_EN_MASK (1 << 6)
#define BQ24193_MISC_DPDM_EN_MASK (1 << 7)
// REG 8 masks.
#define BQ24193_STATUS_VSYS_MASK (1 << 0)
#define BQ24193_STATUS_THERM_MASK (1 << 1)
#define BQ24193_STATUS_PG_MASK (1 << 2)
#define BQ24193_STATUS_DPM_MASK (1 << 3)
#define BQ24193_STATUS_CHRG_MASK (3 << 4)
#define BQ24193_STATUS_VBUS_MASK (3 << 6)
// REG 9 masks.
#define BQ24193_FAULT_THERM_MASK (7 << 0)
#define BQ24193_FAULT_BATT_OVP_MASK (1 << 3)
#define BQ24193_FAULT_CHARGE_MASK (3 << 4)
#define BQ24193_FAULT_BOOST_MASK (1 << 6)
#define BQ24193_FAULT_WATCHDOG_MASK (1 << 7)
// REG A masks.
#define BQ24193_VENDORPART_DEV_MASK (3 << 0)
#define BQ24193_VENDORPART_PN_MASK (7 << 3)
enum BQ24193_reg {
BQ24193_InputSource = 0x00,
BQ24193_PORConfig = 0x01,
BQ24193_ChrgCurr = 0x02,
BQ24193_PreChrgTerm = 0x03,
BQ24193_ChrgVolt = 0x04,
BQ24193_ChrgTermTimer = 0x05,
BQ24193_IRCompThermal = 0x06,
BQ24193_Misc = 0x07,
BQ24193_Status = 0x08,
BQ24193_FaultReg = 0x09,
BQ24193_VendorPart = 0x0A,
};
enum BQ24193_reg_prop {
BQ24193_InputVoltageLimit, // REG 0.
BQ24193_InputCurrentLimit, // REG 0.
BQ24193_SystemMinimumVoltage, // REG 1.
BQ24193_FastChargeCurrentLimit, // REG 2.
BQ24193_ChargeVoltageLimit, // REG 4.
BQ24193_RechargeThreshold, // REG 4.
BQ24193_ThermalRegulation, // REG 6.
BQ24193_ChargeStatus, // REG 8.
BQ24193_TempStatus, // REG 9.
BQ24193_DevID, // REG A.
BQ24193_ProductNumber, // REG A.
};
#endif /* MAX77XXX_H */

31
Source/sys-clk/sysmodule/src/notification.h
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@@ -1,31 +0,0 @@
#pragma once
#include <string>
#include <ctime>
#include <cstdio>
static void writeNotification(const std::string& message) {
const char* flagPath = "sdmc:/config/ultrahand/flags/NOTIFICATIONS.flag";
// Check if flag file exists
FILE* flagFile = fopen(flagPath, "r");
if (!flagFile) {
// Flag file does not exist, do nothing
return;
}
fclose(flagFile);
// Generate filename with timestamp
std::string filename = "Horzon OC -" + std::to_string(std::time(nullptr)) + ".notify";
std::string fullPath = "sdmc:/config/ultrahand/notifications/" + filename;
// Write JSON manually
FILE* file = fopen(fullPath.c_str(), "w");
if (file) {
fprintf(file, "{\n");
fprintf(file, " \"text\": \"%s\",\n", message.c_str());
fprintf(file, " \"fontSize\": 28\n");
fprintf(file, "}\n");
fclose(file);
}
}

131
Source/sys-clk/sysmodule/src/soctherm.h
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@@ -1,131 +0,0 @@
/* * HOS soctherm driver by Souldbminer & Dominatorul * Licensed under the LGPLv3 */
#ifndef _SOCTHERM_H_
#define _SOCTHERM_H_
#include <switch.h>
#define SOCTHERM_BASE 0x700E2000ULL
#define SENSOR_TEMP1 0x1c8
#define SENSOR_TEMP2 0x1cc
#define SOC_THERM_THERMCTL_LEVEL0_GROUP_CPU_0 0x0
#define SOC_THERM_THERMCTL_LEVEL0_GROUP_GPU_0 0x4
#define SOC_THERM_THERMCTL_LEVEL0_GROUP_MEM_0 0x8
#define SOC_THERM_THERMCTL_LEVEL0_GROUP_TSENSE_0 0xC
#define SENSOR_CPU0_CONFIG0 0xC0
#define SENSOR_CPU1_CONFIG0 0xE0
#define SENSOR_CPU2_CONFIG0 0x100
#define SENSOR_CPU3_CONFIG0 0x120
#define SENSOR_GPU_CONFIG0 0x180
#define SENSOR_PLLX_CONFIG0 0x1A0
#define SENSOR_CPU0_CONFIG1 0xC4
#define SENSOR_CPU1_CONFIG1 0xE4
#define SENSOR_CPU2_CONFIG1 0x104
#define SENSOR_CPU3_CONFIG1 0x124
#define SENSOR_GPU_CONFIG1 0x184
#define SENSOR_PLLX_CONFIG1 0x1A4
#define SENSOR_CPU0_STATUS 0xC8
#define SENSOR_GPU_STATUS 0x188
#define SENSOR_PLLX_STATUS 0x1A8
#define SENSOR_CONFIG0_STOP_MASK (1U << 0)
#define SENSOR_CONFIG0_TALL_SHIFT 8
#define SENSOR_CONFIG0_TALL_MASK (0xFFFFF << 8)
#define SENSOR_CONFIG1_TEMP_ENABLE_MASK (1U << 31)
#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
#define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3F << 24)
#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
#define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3F << 15)
#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
#define SENSOR_CONFIG1_TSAMPLE_MASK 0x3FF
#define SENSOR_STATUS_VALID_MASK (1U << 31)
#define TSENSOR_TALL_DEFAULT 16300
#define TSENSOR_TIDDQ_EN_DEFAULT 1
#define TSENSOR_TEN_COUNT_DEFAULT 1
#define TSENSOR_TSAMPLE_DEFAULT 120
#define SENSOR_TEMP1_CPU_TEMP_MASK (0xFFFF << 16)
#define SENSOR_TEMP1_GPU_TEMP_MASK 0xFFFF
#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xFFFF
#define READBACK_VALUE_MASK 0xFF00
#define READBACK_VALUE_SHIFT 8
#define READBACK_ADD_HALF (1 << 7)
#define READBACK_NEGATE (1 << 0)
#define REG_GET_MASK(r, m) (((r) & (m)) >> (__builtin_ffs(m) - 1))
// Timing constants (in microseconds)
#define SENSOR_STABILIZATION_DELAY_US 2000 // 2ms for sensor to stabilize
#define SENSOR_READ_DELAY_US 100 // 100us between config operations
// Makes my life easier
#define BITMASK(bits) (0UL | (bits))
#define BIT(n) (1UL << (n))
#define WRITE_REG_BIT(addr, bit, val) do { \
u32 _tmp; \
svcReadWriteRegister(&_tmp, (addr), 0, false); \
if (val) \
_tmp |= (1U << (bit)); /* set bit */ \
else \
_tmp &= ~(1U << (bit)); /* clear bit */ \
svcReadWriteRegister(&_tmp, (addr), 0, true); \
} while (0)
typedef enum {
SENSOR_CPU = 0,
SENSOR_GPU = 1,
SENSOR_PLLX = 2,
} SocthermSensor;
void socthermInit(void) {
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU0_CONFIG0, 0, 0); // start cpu0
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU0_CONFIG1, 31, 1); // start cpu0
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU1_CONFIG0, 0, 0); // start cpu1
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU1_CONFIG1, 31, 1); // start cpu1
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU2_CONFIG0, 0, 0); // start cpu2
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU2_CONFIG1, 31, 1); // start cpu2
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU3_CONFIG0, 0, 0); // start cpu3
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU3_CONFIG1, 31, 1); // start cpu3
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_GPU_CONFIG0, 0, 0); // start gpu
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_GPU_CONFIG1, 31, 1); // start gpu
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_PLLX_CONFIG0, 0, 0); // start pllx
WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_PLLX_CONFIG1, 31, 1); // start pllx
}
int socthermRead(SocthermSensor sensor) {
switch(sensor) {
case SENSOR_CPU: {
u32 temp_reg;
svcReadWriteRegister(&temp_reg, SOCTHERM_BASE + SENSOR_TEMP1, 0, false);
return REG_GET_MASK(temp_reg, SENSOR_TEMP1_CPU_TEMP_MASK);
}
case SENSOR_GPU: {
u32 temp_reg;
svcReadWriteRegister(&temp_reg, SOCTHERM_BASE + SENSOR_TEMP1, 0, false);
return REG_GET_MASK(temp_reg, SENSOR_TEMP1_GPU_TEMP_MASK);
}
case SENSOR_PLLX: {
u32 temp_reg;
svcReadWriteRegister(&temp_reg, SOCTHERM_BASE + SENSOR_TEMP2, 0, false);
return REG_GET_MASK(temp_reg, SENSOR_TEMP2_PLLX_TEMP_MASK);
}
default:
return -1; // Invalid sensor
}
}
#endif // _SOCTHERM_H_