Replaced 2600 with correct dump and added a few 1331 timings
This commit is contained in:
Lightos1
528
timings/Mariko/AA/1331/emc/1600_emc.txt
Normal file
528
timings/Mariko/AA/1331/emc/1600_emc.txt
Normal file
@@ -0,0 +1,528 @@
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Dumping EMC registers from BASE=0x7001B000
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-----------------------------------
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EMC_INTSTATUS_0 = 0x00000030
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EMC_INTMASK_0 = 0x00000000
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EMC_DBG_0 = 0x01000C00
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EMC_CFG_0 = 0xF3200000
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EMC_ADR_CFG_0 = 0x00000000
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EMC_REFCTRL_0 = 0x80000002
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EMC_PIN_0 = 0x00003101
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EMC_TIMING_CONTROL_0 = 0x00000001
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EMC_RC_0 = 0x00000060
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EMC_RFC_0 = 0x000001C0
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EMC_RAS_0 = 0x00000044
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EMC_RP_0 = 0x0000001D
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EMC_R2W_0 = 0x00000027
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EMC_W2R_0 = 0x0000001D
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EMC_R2P_0 = 0x0000000A
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EMC_W2P_0 = 0x00000025
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EMC_RD_RCD_0 = 0x0000001D
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EMC_WR_RCD_0 = 0x0000001D
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EMC_RRD_0 = 0x00000010
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EMC_REXT_0 = 0x00000017
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EMC_WDV_0 = 0x0000000C
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EMC_QUSE_0 = 0x00000020
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EMC_QRST_0 = 0x00060008
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EMC_QSAFE_0 = 0x0000002F
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EMC_RDV_0 = 0x00000035
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EMC_REFRESH_0 = 0x00001820
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EMC_BURST_REFRESH_NUM_0 = 0x00000000
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EMC_PDEX2WR_0 = 0x00000010
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EMC_PDEX2RD_0 = 0x00000010
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EMC_PCHG2PDEN_0 = 0x00000003
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EMC_ACT2PDEN_0 = 0x00000017
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EMC_AR2PDEN_0 = 0x00000003
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EMC_RW2PDEN_0 = 0x00000030
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EMC_TXSR_0 = 0x000001CC
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EMC_TCKE_0 = 0x0000000D
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EMC_TFAW_0 = 0x00000040
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EMC_TRPAB_0 = 0x00000022
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EMC_TCLKSTABLE_0 = 0x00000004
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EMC_TCLKSTOP_0 = 0x00000014
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EMC_TREFBW_0 = 0x00001860
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EMC_TPPD_0 = 0x00000004
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EMC_ODT_WRITE_0 = 0x00000000
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EMC_PDEX2MRR_0 = 0x0000002E
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EMC_WEXT_0 = 0x00000016
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EMC_RFC_SLR_0 = 0x00000000
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EMC_MRS_WAIT_CNT2_0 = 0x01900017
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EMC_MRS_WAIT_CNT_0 = 0x0640002B
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EMC_MRS_0 = 0x00000000
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EMC_EMRS_0 = 0x00000000
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EMC_REF_0 = 0x80000000
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EMC_PRE_0 = 0x00000000
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EMC_NOP_0 = 0x00000000
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EMC_SELF_REF_0 = 0x00000000
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EMC_DPD_0 = 0x00000000
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EMC_MRW_0 = 0x00170040
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EMC_MRR_0 = 0x8012C1DD
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EMC_CMDQ_0 = 0x10004408
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EMC_MC2EMCQ_0 = 0x06000404
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EMC_FBIO_SPARE_0 = 0x00000012
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EMC_FBIO_CFG5_0 = 0x9160A00D
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EMC_FBIO_CFG6_0 = 0x00001010
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EMC_PDEX2CKE_0 = 0x00000002
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EMC_CKE2PDEN_0 = 0x0000000E
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EMC_CFG_RSV_0 = 0xFF00FF00
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EMC_ACPD_CONTROL_0 = 0x00000000
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EMC_MPC_0 = 0x0000004B
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EMC_EMRS2_0 = 0x00000000
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EMC_EMRS3_0 = 0x00000000
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EMC_MRW2_0 = 0x88020024
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EMC_MRW3_0 = 0x8C0D00D0
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EMC_MRW4_0 = 0xC0000000
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EMC_CLKEN_OVERRIDE_0 = 0x00000000
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EMC_R2R_0 = 0x00000000
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EMC_W2W_0 = 0x00000000
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EMC_EINPUT_0 = 0x00000010
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EMC_EINPUT_DURATION_0 = 0x0000001C
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EMC_PUTERM_EXTRA_0 = 0x00000001
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EMC_TCKESR_0 = 0x00000018
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EMC_TPD_0 = 0x0000000C
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EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
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EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
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EMC_AUTO_CAL_STATUS_0 = 0x1D190000
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EMC_REQ_CTRL_0 = 0x00000000
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EMC_EMC_STATUS_0 = 0x0B430035
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EMC_CFG_2_0 = 0x00110835
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EMC_CFG_DIG_DLL_0 = 0x002C03A9
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EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
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EMC_DIG_DLL_STATUS_0 = 0x00000004
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EMC_CFG_DIG_DLL_1_0 = 0x000F3701
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EMC_RDV_MASK_0 = 0x00000037
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EMC_WDV_MASK_0 = 0x0000000C
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EMC_RDV_EARLY_MASK_0 = 0x00000035
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EMC_RDV_EARLY_0 = 0x00000033
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EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
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EMC_ZCAL_INTERVAL_0 = 0x00064000
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EMC_ZCAL_WAIT_CNT_0 = 0x00310640
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EMC_ZCAL_MRW_CMD_0 = 0x8051004F
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EMC_ZQ_CAL_0 = 0x80000002
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EMC_XM2COMPPADCTRL3_0 = 0x00901000
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EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
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EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
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EMC_XM2COMPPADCTRL_0 = 0x00000030
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EMC_FDPD_CTRL_DQ_0 = 0x8020221F
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EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
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EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
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EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
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EMC_SCRATCH0_0 = 0x00000000
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EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
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EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
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EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
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EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
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EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
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EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
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EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
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EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
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EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
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EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
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EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
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EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
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EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
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EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
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EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
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EMC_TR_TIMING_0_0 = 0x01186190
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EMC_TR_CTRL_0_0 = 0x00000020
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EMC_TR_CTRL_1_0 = 0x00000000
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EMC_SWITCH_BACK_CTRL_0 = 0x00000001
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EMC_TR_RDV_0 = 0x00000035
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EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
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EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
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EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
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EMC_AUTO_CAL_ = 0x3F1F080B
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EMC_SEL_DPD_CTRL_0 = 0x0004000C
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EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000608
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EMC_DYN_SELF_REF_CONTROL_0 = 0x8000308C
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EMC_TXSRDLL_0 = 0x000001CC
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EMC_CCFIFO_ADDR_0 = 0x80000000
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EMC_CCFIFO_DATA_0 = 0x00000000
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EMC_CCFIFO_STATUS_0 = 0x00000000
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EMC_TR_QPOP_0 = 0x00000027
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EMC_TR_RDV_MASK_0 = 0x00000037
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EMC_TR_QSAFE_0 = 0x0000002F
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EMC_TR_QRST_0 = 0x00060008
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EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
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EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
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EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
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EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
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EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
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EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
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EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
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EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
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EMC_ISSUE_QRST_0 = 0x00000000
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EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
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EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
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EMC_PMC_SCRATCH3_0 = 0x4036D71F
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EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
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EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
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EMC_TR_DVFS_0 = 0x00000000
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EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
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EMC_IBDLY_0 = 0x10000018
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EMC_OBDLY_0 = 0x10000000
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EMC_TXDSRVTTGEN_0 = 0x00000000
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EMC_WE_DURATION_0 = 0x0000000E
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EMC_WS_DURATION_0 = 0x00000008
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EMC_WEV_0 = 0x00000008
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EMC_WSV_0 = 0x0000000A
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EMC_CFG_3_0 = 0x00000040
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EMC_MRW5_0 = 0x00000000
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EMC_MRW6_0 = 0x8803F1F1
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EMC_MRW7_0 = 0xC803F1F1
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EMC_MRW8_0 = 0x880B0606
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EMC_MRW9_0 = 0x8C0E5D5D
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EMC_MRW10_0 = 0x880C5D5D
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EMC_MRW11_0 = 0xC80C5D5D
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EMC_MRW12_0 = 0x880E0C0A
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EMC_MRW13_0 = 0xC80E0000
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EMC_MRW14_0 = 0x88161414
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EMC_MRW15_0 = 0xC8161414
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EMC_CFG_SYNC_0 = 0x00000001
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EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
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EMC_WDV_CHK_0 = 0x00000006
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EMC_CFG_PIPE_2_0 = 0x00000000
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EMC_CFG_PIPE_CLK_0 = 0x00000000
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EMC_CFG_PIPE_1_0 = 0x0FFF0000
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EMC_CFG_PIPE_0 = 0x0FFF0000
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EMC_QPOP_0 = 0x00000027
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EMC_QUSE_WIDTH_0 = 0x00000008
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EMC_PUTERM_WIDTH_0 = 0x80000000
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EMC_BGBIAS_CTL0_0 = 0x00000000
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EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
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EMC_XM2COMPPADCTRL2_0 = 0x16001000
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EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
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EMC_REFCTRL2_0 = 0x00000000
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EMC_FBIO_CFG7_0 = 0x00003BFF
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EMC_DATA_BRLSHFT_0_0 = 0x00000249
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EMC_DATA_BRLSHFT_1_0 = 0x00000000
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EMC_RFCPB_0 = 0x000000E0
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EMC_DQS_BRLSHFT_0_0 = 0x00000000
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EMC_DQS_BRLSHFT_1_0 = 0x00000000
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EMC_CMD_BRLSHFT_0_0 = 0x00000000
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EMC_CMD_BRLSHFT_1_0 = 0x00000000
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EMC_CMD_BRLSHFT_2_0 = 0x00000012
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EMC_CMD_BRLSHFT_3_0 = 0x00000012
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EMC_QUSE_BRLSHFT_0_0 = 0x00000000
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EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
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EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
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EMC_QUSE_BRLSHFT_1_0 = 0x00000000
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EMC_QUSE_BRLSHFT_2_0 = 0x00000000
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EMC_CCDMW_0 = 0x00000020
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EMC_QUSE_BRLSHFT_3_0 = 0x00000000
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EMC_FBIO_CFG8_0 = 0x0CF30000
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EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
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EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
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EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
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EMC_PROTOBIST_MISC_0 = 0x00000000
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EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
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EMC_PROTOBIST_WDATA_UPPER_0 = 0x80200002
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EMC_PROTOBIST_RDATA_0 = 0x00000000
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EMC_DLL_CFG_0_0 = 0x1F136120
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EMC_DLL_CFG_1_0 = 0x00012014
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EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
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EMC_CFG_UPDATE_0 = 0x70000301
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EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000E0006
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000B
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020007
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00230024
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00200022
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
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EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
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EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
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EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
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EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
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EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
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EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
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EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
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EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
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EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
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EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
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EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
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EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
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EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
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EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
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EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
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EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
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EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x2E2F2F2F
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EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2B292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2B2D2C2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2A2E282A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x32313233
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x2F313228
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x252C2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A2A2624
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2B2F2D2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2C2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x36363735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353233
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2E2E2A2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2A2D29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03040505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050605
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05030104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05030402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24232428
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262524
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x070B070B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
288
timings/Mariko/AA/1331/mc/1600_mc.txt
Normal file
288
timings/Mariko/AA/1331/mc/1600_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01011200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFEBB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x78685AE1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000C
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000006
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x00000009
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x04050000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000C080C
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726C2419
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00023090
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000000
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x000000D0
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000318
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x00000018
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000010
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00001203
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000080
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080016
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
@@ -1,87 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
emc_cfg = 0xF3200000
|
||||
emc_rc = 0x0000009C
|
||||
emc_rfc = 0x000002D8
|
||||
emc_ras = 0x0000006E
|
||||
emc_rp = 0x0000002F
|
||||
emc_r2w = 0x00000031
|
||||
emc_w2r = 0x0000002B
|
||||
emc_r2p = 0x0000000E
|
||||
emc_w2p = 0x00000033
|
||||
emc_rd_rcd = 0x0000002F
|
||||
emc_wr_rcd = 0x0000002F
|
||||
emc_rrd = 0x00000014
|
||||
emc_rext = 0x0000001B
|
||||
emc_qsafe = 0x0000003C
|
||||
emc_refresh = 0x0000275C
|
||||
emc_burst_refresh_num = 0x00000000
|
||||
emc_pdex2wr = 0x0000001B
|
||||
emc_pdex2rd = 0x0000001B
|
||||
emc_pchg2pden = 0x00000005
|
||||
emc_act2pden = 0x00000025
|
||||
emc_ar2pden = 0x00000005
|
||||
emc_rw2pden = 0x00000040
|
||||
emc_txsr = 0x000002EC
|
||||
emc_tcke = 0x00000016
|
||||
emc_tfaw = 0x0000004E
|
||||
emc_trpab = 0x00000037
|
||||
emc_tclkstable = 0x00000004
|
||||
emc_tclkstop = 0x0000001E
|
||||
emc_trefbw = 0x0000279C
|
||||
emc_tppd = 0x00000004
|
||||
emc_odt_write = 0x00000000
|
||||
emc_pdex2mrr = 0x0000004C
|
||||
emc_wext = 0x00000019
|
||||
emc_rfc_slr = 0x00000000
|
||||
emc_mrs_wait_cnt2 = 0x028A0025
|
||||
emc_mrs_wait_cnt = 0x07FF0037
|
||||
emc_mrs = 0x00000000
|
||||
emc_emrs = 0x00000000
|
||||
emc_mrw = 0x00170040
|
||||
emc_fbio_spare = 0x00000012
|
||||
emc_fbio_cfg5 = 0x9160A00D
|
||||
emc_pdex2cke = 0x00000003
|
||||
emc_cke2pden = 0x00000017
|
||||
emc_r2r = 0x00000000
|
||||
emc_einput = 0x00000010
|
||||
emc_einput_duration = 0x00000029
|
||||
emc_puterm_extra = 0x00000001
|
||||
emc_tckesr = 0x00000027
|
||||
emc_tpd = 0x00000014
|
||||
emc_cfg_2 = 0x0011083D
|
||||
emc_cfg_dig_dll = 0x002C03A9
|
||||
emc_cfg_dig_dll_period = 0x00008000
|
||||
emc_rdv_mask = 0x00000044
|
||||
emc_wdv_mask = 0x00000010
|
||||
emc_rdv_early_mask = 0x00000042
|
||||
emc_rdv_early = 0x00000040
|
||||
emc_fdpd_ctrl_dq = 0x8020221F
|
||||
emc_fdpd_ctrl_cmd = 0x0220F40F
|
||||
emc_sel_dpd_ctrl = 0x0004000C
|
||||
emc_pre_refresh_req_cnt = 0x000009D7
|
||||
emc_dyn_self_ref_control = 0x80004E41
|
||||
emc_txsrdll = 0x000002EC
|
||||
emc_ibdly = 0x10000020
|
||||
emc_obdly = 0x10000002
|
||||
emc_txdsrvttgen = 0x00000000
|
||||
emc_we_duration = 0x0000000E
|
||||
emc_ws_duration = 0x00000008
|
||||
emc_wev = 0x0000000C
|
||||
emc_cfg_3 = 0x00000040
|
||||
emc_wdv_chk = 0x00000006
|
||||
emc_cfg_pipe_2 = 0x00000000
|
||||
emc_cfg_pipe_1 = 0x0FFF0000
|
||||
emc_cfg_pipe = 0x0FFF0000
|
||||
emc_quse_width = 0x0000000B
|
||||
emc_puterm_width = 0x80000000
|
||||
emc_fbio_cfg7 = 0x00003BFF
|
||||
emc_rfcpb = 0x0000016C
|
||||
emc_ccdmw = 0x00000020
|
||||
emc_config_sample_delay = 0x00000020
|
||||
emc_wdv = 0x00000010
|
||||
emc_quse = 0x0000002A
|
||||
emc_qrst = 0x00080006
|
||||
emc_rdv = 0x00000042
|
||||
emc_wsv = 0x0000000E
|
||||
emc_qpop = 0x00000034
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009C
|
||||
EMC_RFC_0 = 0x000002D8
|
||||
EMC_RAS_0 = 0x0000006E
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00080006
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x00000042
|
||||
EMC_REFRESH_0 = 0x0000275C
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002EC
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004E
|
||||
EMC_TRPAB_0 = 0x00000037
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000279C
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x028A0025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012C0D8
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000044
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||
EMC_RDV_EARLY_0 = 0x00000040
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118628A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000042
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009D7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004E41
|
||||
EMC_TXSRDLL_0 = 0x000002EC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000034
|
||||
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000034
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000016C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x12121313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x110C0A10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10120F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0E130A0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x19171A1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x15181909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x030E0F0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0B0B0501
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0D130F12
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0E130E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0E0C0E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0F0D0E0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1E1E201D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1B1C1819
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x12130C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x100E110A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080508
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0606080B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04040806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624252A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27292826
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040514
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
|
||||
@@ -1,56 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
mc_emem_arb_cfg = 0x08000013
|
||||
mc_emem_arb_outstanding_req = 0x80040080
|
||||
mc_emem_arb_timing_rcd = 0x0000000A
|
||||
mc_emem_arb_timing_rp = 0x0000000B
|
||||
mc_emem_arb_timing_rc = 0x00000027
|
||||
mc_emem_arb_timing_ras = 0x0000001A
|
||||
mc_emem_arb_timing_faw = 0x00000013
|
||||
mc_emem_arb_timing_rrd = 0x00000004
|
||||
mc_emem_arb_timing_rap2pre = 0x00000004
|
||||
mc_emem_arb_timing_wap2pre = 0x0000000F
|
||||
mc_emem_arb_timing_r2r = 0x00000001
|
||||
mc_emem_arb_timing_w2w = 0x00000001
|
||||
mc_emem_arb_timing_r2w = 0x0000000E
|
||||
mc_emem_arb_timing_w2r = 0x0000000C
|
||||
mc_emem_arb_da_turns = 0x06070000
|
||||
mc_emem_arb_da_covers = 0x00120D13
|
||||
mc_emem_arb_misc0 = 0x72743B28
|
||||
mc_emem_arb_misc1 = 0x70000F0F
|
||||
mc_emem_arb_misc2 = 0x00000000
|
||||
mc_emem_arb_ring1_throttle = 0x001F0000
|
||||
mc_emem_arb_timing_rfcpb = 0x0000005A
|
||||
mc_emem_arb_timing_ccdmw = 0x00000008
|
||||
mc_emem_arb_dhyst_ctrl = 0x000A1020
|
||||
mc_emem_arb_dhyst_timeout_util_0 = 0x0000001A
|
||||
mc_emem_arb_dhyst_timeout_util_1 = 0x0000001A
|
||||
mc_emem_arb_dhyst_timeout_util_2 = 0x0000001A
|
||||
mc_emem_arb_dhyst_timeout_util_3 = 0x0000001A
|
||||
mc_emem_arb_dhyst_timeout_util_4 = 0x0000001A
|
||||
mc_emem_arb_dhyst_timeout_util_5 = 0x0000001A
|
||||
mc_emem_arb_dhyst_timeout_util_6 = 0x0000001A
|
||||
mc_emem_arb_dhyst_timeout_util_7 = 0x0000001A
|
||||
mc_mll_mpcorer_ptsa_rate = 0x00000115
|
||||
mc_ftop_ptsa_rate = 0x00000000
|
||||
mc_ptsa_grant_decrement = 0x000017FF
|
||||
mc_latency_allowance_avpc_0 = 0x004E0004
|
||||
mc_latency_allowance_sdmmcaa_0 = 0x004E0005
|
||||
mc_latency_allowance_sdmmca_0 = 0x004E0014
|
||||
mc_latency_allowance_isp2_0 = 0x0000002C
|
||||
mc_latency_allowance_isp2_1 = 0x004E004E
|
||||
mc_latency_allowance_vic_0 = 0x004E0012
|
||||
mc_latency_allowance_nvdec_0 = 0x004E0095
|
||||
mc_latency_allowance_tsec_0 = 0x004E0041
|
||||
mc_latency_allowance_ppcs_1 = 0x004E0080
|
||||
mc_latency_allowance_xusb_0 = 0x004E003D
|
||||
mc_latency_allowance_ppcs_0 = 0x00340049
|
||||
mc_latency_allowance_gpu2_0 = 0x004E0010
|
||||
mc_latency_allowance_hc_1 = 0x0000004E
|
||||
mc_latency_allowance_sdmmc_0 = 0x004E0090
|
||||
mc_latency_allowance_mpcore_0 = 0x004E0004
|
||||
mc_latency_allowance_vi2_0 = 0x0000004E
|
||||
mc_latency_allowance_hc_0 = 0x0008000E
|
||||
mc_latency_allowance_gpu_0 = 0x004E0010
|
||||
mc_latency_allowance_sdmmcab_0 = 0x004E0005
|
||||
mc_latency_allowance_nvenc_0 = 0x004E0018
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFB7B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0xFFBBBDF1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743B28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000000
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004E004E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004E0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
|
||||
@@ -8,45 +8,45 @@ EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000060
|
||||
EMC_RFC_0 = 0x000001C0
|
||||
EMC_RAS_0 = 0x00000044
|
||||
EMC_RP_0 = 0x0000001D
|
||||
EMC_R2W_0 = 0x00000029
|
||||
EMC_W2R_0 = 0x00000021
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000001D
|
||||
EMC_WR_RCD_0 = 0x0000001D
|
||||
EMC_RRD_0 = 0x00000010
|
||||
EMC_REXT_0 = 0x00000017
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x0006000C
|
||||
EMC_QSAFE_0 = 0x00000033
|
||||
EMC_RDV_0 = 0x00000039
|
||||
EMC_REFRESH_0 = 0x00001820
|
||||
EMC_RC_0 = 0x0000009C
|
||||
EMC_RFC_0 = 0x000002D8
|
||||
EMC_RAS_0 = 0x0000006E
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002D
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x0008000A
|
||||
EMC_QSAFE_0 = 0x00000040
|
||||
EMC_RDV_0 = 0x00000046
|
||||
EMC_REFRESH_0 = 0x0000275C
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000010
|
||||
EMC_PDEX2RD_0 = 0x00000010
|
||||
EMC_PCHG2PDEN_0 = 0x00000003
|
||||
EMC_ACT2PDEN_0 = 0x00000017
|
||||
EMC_AR2PDEN_0 = 0x00000003
|
||||
EMC_RW2PDEN_0 = 0x00000038
|
||||
EMC_TXSR_0 = 0x000001CC
|
||||
EMC_TCKE_0 = 0x0000000D
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x00000022
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002EC
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004E
|
||||
EMC_TRPAB_0 = 0x00000037
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x00000014
|
||||
EMC_TREFBW_0 = 0x00001860
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000279C
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000002E
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x01900017
|
||||
EMC_MRS_WAIT_CNT_0 = 0x0640002F
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x028A0025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
@@ -55,47 +55,47 @@ EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012C6E3
|
||||
EMC_MRR_0 = 0x8012BCD5
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x0000000E
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00C0
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000018
|
||||
EMC_TPD_0 = 0x0000000C
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x00110835
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003B
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000039
|
||||
EMC_RDV_EARLY_0 = 0x00000037
|
||||
EMC_RDV_MASK_0 = 0x00000048
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000046
|
||||
EMC_RDV_EARLY_0 = 0x00000044
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x00310640
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
@@ -122,26 +122,26 @@ EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186190
|
||||
EMC_TR_TIMING_0_0 = 0x0118628A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000039
|
||||
EMC_TR_RDV_0 = 0x00000046
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070B
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000608
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000308C
|
||||
EMC_TXSRDLL_0 = 0x000001CC
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009D7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004E41
|
||||
EMC_TXSRDLL_0 = 0x000002EC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002B
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003B
|
||||
EMC_TR_QSAFE_0 = 0x00000033
|
||||
EMC_TR_QRST_0 = 0x0006000C
|
||||
EMC_TR_QPOP_0 = 0x00000038
|
||||
EMC_TR_RDV_MASK_0 = 0x00000048
|
||||
EMC_TR_QSAFE_0 = 0x00000040
|
||||
EMC_TR_QRST_0 = 0x0008000A
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
@@ -157,14 +157,14 @@ EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
@@ -173,7 +173,7 @@ EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E09
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
@@ -184,8 +184,8 @@ EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x00000008
|
||||
EMC_QPOP_0 = 0x00000038
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
@@ -193,15 +193,15 @@ EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_RFCPB_0 = 0x0000016C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
@@ -214,8 +214,8 @@ EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80200002
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
@@ -237,30 +237,30 @@ EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x001F0022
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
@@ -291,37 +291,37 @@ EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x2E2F2F2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2A292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x12121313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x100D0A10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2C2E2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10120F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0E130A0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323333
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x30323328
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x18171A1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x15181A09
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A2A2623
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x040E100D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0B0B0601
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2C2F2D2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0D121012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0E120E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2C2B2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2C2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0E0C0E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0E0D0F0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x36363635
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353233
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1E1E201D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1B1C181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2F2E2A2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2D29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x12130C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x100E110B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
@@ -387,29 +387,29 @@ EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03040506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0607090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020203
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05040200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
@@ -459,17 +459,17 @@ EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23242425
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26252324
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27242429
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29292627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
@@ -477,10 +477,10 @@ EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
@@ -489,9 +489,9 @@ EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
@@ -522,7 +522,7 @@ EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040514
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E09
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_ERR_ADR_0 = 0x11211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD1B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7B210471
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC7B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x786771F1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
@@ -18,23 +18,23 @@ MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000C
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000006
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80040080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000D080C
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726C2419
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743B28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
@@ -77,22 +77,22 @@ MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C181000
|
||||
MC_ERR_VPR_ADR_0 = 0x0C5D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063090
|
||||
MC_ERR_SEC_ADR_0 = 0x08130850
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02110800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
@@ -153,7 +153,7 @@ MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
@@ -176,7 +176,7 @@ MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000230
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
@@ -199,14 +199,14 @@ MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000010
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
@@ -238,26 +238,26 @@ MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004E004E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004E0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
@@ -266,23 +266,23 @@ MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080016
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
|
||||
Reference in New Issue
Block a user