131 lines
4.5 KiB
C
131 lines
4.5 KiB
C
/* * HOS soctherm driver by Souldbminer & Dominatorul * Licensed under the LGPLv3 */
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#ifndef _SOCTHERM_H_
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#define _SOCTHERM_H_
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#include <switch.h>
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#define SOCTHERM_BASE 0x700E2000ULL
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#define SENSOR_TEMP1 0x1c8
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#define SENSOR_TEMP2 0x1cc
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#define SOC_THERM_THERMCTL_LEVEL0_GROUP_CPU_0 0x0
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#define SOC_THERM_THERMCTL_LEVEL0_GROUP_GPU_0 0x4
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#define SOC_THERM_THERMCTL_LEVEL0_GROUP_MEM_0 0x8
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#define SOC_THERM_THERMCTL_LEVEL0_GROUP_TSENSE_0 0xC
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#define SENSOR_CPU0_CONFIG0 0xC0
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#define SENSOR_CPU1_CONFIG0 0xE0
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#define SENSOR_CPU2_CONFIG0 0x100
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#define SENSOR_CPU3_CONFIG0 0x120
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#define SENSOR_GPU_CONFIG0 0x180
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#define SENSOR_PLLX_CONFIG0 0x1A0
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#define SENSOR_CPU0_CONFIG1 0xC4
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#define SENSOR_CPU1_CONFIG1 0xE4
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#define SENSOR_CPU2_CONFIG1 0x104
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#define SENSOR_CPU3_CONFIG1 0x124
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#define SENSOR_GPU_CONFIG1 0x184
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#define SENSOR_PLLX_CONFIG1 0x1A4
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#define SENSOR_CPU0_STATUS 0xC8
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#define SENSOR_GPU_STATUS 0x188
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#define SENSOR_PLLX_STATUS 0x1A8
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#define SENSOR_CONFIG0_STOP_MASK (1U << 0)
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#define SENSOR_CONFIG0_TALL_SHIFT 8
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#define SENSOR_CONFIG0_TALL_MASK (0xFFFFF << 8)
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#define SENSOR_CONFIG1_TEMP_ENABLE_MASK (1U << 31)
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#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
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#define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3F << 24)
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#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
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#define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3F << 15)
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#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
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#define SENSOR_CONFIG1_TSAMPLE_MASK 0x3FF
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#define SENSOR_STATUS_VALID_MASK (1U << 31)
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#define TSENSOR_TALL_DEFAULT 16300
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#define TSENSOR_TIDDQ_EN_DEFAULT 1
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#define TSENSOR_TEN_COUNT_DEFAULT 1
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#define TSENSOR_TSAMPLE_DEFAULT 120
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#define SENSOR_TEMP1_CPU_TEMP_MASK (0xFFFF << 16)
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#define SENSOR_TEMP1_GPU_TEMP_MASK 0xFFFF
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#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xFFFF
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#define READBACK_VALUE_MASK 0xFF00
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#define READBACK_VALUE_SHIFT 8
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#define READBACK_ADD_HALF (1 << 7)
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#define READBACK_NEGATE (1 << 0)
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#define REG_GET_MASK(r, m) (((r) & (m)) >> (__builtin_ffs(m) - 1))
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// Timing constants (in microseconds)
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#define SENSOR_STABILIZATION_DELAY_US 2000 // 2ms for sensor to stabilize
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#define SENSOR_READ_DELAY_US 100 // 100us between config operations
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// Makes my life easier
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#define BITMASK(bits) (0UL | (bits))
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#define BIT(n) (1UL << (n))
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#define WRITE_REG_BIT(addr, bit, val) do { \
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u32 _tmp; \
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svcReadWriteRegister(&_tmp, (addr), 0, false); \
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if (val) \
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_tmp |= (1U << (bit)); /* set bit */ \
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else \
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_tmp &= ~(1U << (bit)); /* clear bit */ \
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svcReadWriteRegister(&_tmp, (addr), 0, true); \
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} while (0)
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typedef enum {
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SENSOR_CPU = 0,
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SENSOR_GPU = 1,
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SENSOR_PLLX = 2,
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} SocthermSensor;
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void socthermInit(void) {
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU0_CONFIG0, 0, 0); // start cpu0
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU0_CONFIG1, 31, 1); // start cpu0
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU1_CONFIG0, 0, 0); // start cpu1
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU1_CONFIG1, 31, 1); // start cpu1
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU2_CONFIG0, 0, 0); // start cpu2
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU2_CONFIG1, 31, 1); // start cpu2
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU3_CONFIG0, 0, 0); // start cpu3
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_CPU3_CONFIG1, 31, 1); // start cpu3
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_GPU_CONFIG0, 0, 0); // start gpu
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_GPU_CONFIG1, 31, 1); // start gpu
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_PLLX_CONFIG0, 0, 0); // start pllx
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WRITE_REG_BIT(SOCTHERM_BASE + SENSOR_PLLX_CONFIG1, 31, 1); // start pllx
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}
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int socthermRead(SocthermSensor sensor) {
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switch(sensor) {
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case SENSOR_CPU: {
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u32 temp_reg;
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svcReadWriteRegister(&temp_reg, SOCTHERM_BASE + SENSOR_TEMP1, 0, false);
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return REG_GET_MASK(temp_reg, SENSOR_TEMP1_CPU_TEMP_MASK);
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}
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case SENSOR_GPU: {
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u32 temp_reg;
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svcReadWriteRegister(&temp_reg, SOCTHERM_BASE + SENSOR_TEMP1, 0, false);
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return REG_GET_MASK(temp_reg, SENSOR_TEMP1_GPU_TEMP_MASK);
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}
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case SENSOR_PLLX: {
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u32 temp_reg;
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svcReadWriteRegister(&temp_reg, SOCTHERM_BASE + SENSOR_TEMP2, 0, false);
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return REG_GET_MASK(temp_reg, SENSOR_TEMP2_PLLX_TEMP_MASK);
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}
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default:
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return -1; // Invalid sensor
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}
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}
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#endif // _SOCTHERM_H_
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