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homebrew to query clkrst registers, requires rebuilding nx-hbloader to allow access; emc pllm(b) divm accepts 1/2/4 only

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This commit is contained in:
KazushiM
2022-02-09 15:27:57 +08:00
parent c701de9ca5
commit 94ac52e80b
8 changed files with 130 additions and 10 deletions
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2
Source/Atmosphere/stratosphere/loader/source/oc/Makefile
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@@ -3,7 +3,7 @@ export CC := g++-11
all: test
test:
$(CC) ldr_oc_suite.cpp test.cpp -o ./test -O2 -std=c++20 -DOC_TEST
$(CC) ldr_oc_suite.cpp test.cpp -o ./test -O2 -std=c++20
clean:
rm ./test

2
Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_customize.inc
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@@ -29,7 +29,7 @@ static const volatile CustomizeTable C = {
/* Mariko EMC:
* - RAM Clock in kHz:
* Values should be > 1600000, and divided evenly by 9600 or 12800.
* Values should be > 1600000, and divided evenly by 9600.
* [WARNING]
* RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
* - Graphical glitches

8
Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.cpp
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@@ -16,7 +16,7 @@
//#define EXPERIMENTAL
#ifdef OC_TEST
#ifndef ATMOSPHERE_IS_STRATOSPHERE
#include "ldr_oc_suite_test.hpp"
#else
#include <stratosphere.hpp>
@@ -170,7 +170,7 @@ namespace ams::ldr::oc {
} pllmb_div;
constexpr pllmb_div div[] = {
{3, 4}, {2, 3}, {1, 2}, {1, 3}, {1, 4}, {0, 1}
{3, 4}, {1, 2}, {1, 4}, {0, 1}
};
constexpr u32 pll_osc_in = 38400;
@@ -1124,7 +1124,7 @@ namespace ams::ldr::oc {
void Patch(uintptr_t mapped_nso, size_t nso_size) {
SafetyCheck();
#ifdef OC_TEST
#ifndef ATMOSPHERE_IS_STRATOSPHERE
void* buf = malloc(nso_size);
uintptr_t mapped_exe = reinterpret_cast<uintptr_t>(buf);
std::memcpy(buf, reinterpret_cast<void *>(mapped_nso), nso_size);
@@ -1144,7 +1144,7 @@ namespace ams::ldr::oc {
namespace ptm {
void Patch(uintptr_t mapped_nso, size_t nso_size) {
#ifndef OC_TEST
#ifdef ATMOSPHERE_IS_STRATOSPHERE
bool isMariko = (spl::GetSocType() == spl::SocType_Mariko);
if (!isMariko)
return;

2
Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.hpp
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@@ -48,7 +48,7 @@ namespace ams::ldr::oc {
inline Result ResultFailure() { return -1; }
#ifndef OC_TEST
#ifdef ATMOSPHERE_IS_STRATOSPHERE
#define LOGGING(fmt, ...) ((void)0)
#endif

2
Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite_test.hpp
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@@ -1,4 +1,4 @@
#ifdef OC_TEST
#ifndef ATMOSPHERE_IS_STRATOSPHERE
#include <iostream>
#include <cstdint>
#include <cstring>

2
Source/Atmosphere/stratosphere/loader/source/oc/test.cpp
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@@ -13,7 +13,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifdef OC_TEST
#ifndef ATMOSPHERE_IS_STRATOSPHERE
#include <cstdio>
#include <cstring>
#include <cstdlib>

120
Source/clkrst_query.cpp Normal file
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@@ -0,0 +1,120 @@
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include <inttypes.h>
#include <switch.h>
/* Recompile nx-hbloader with following added in config.json "kernel_capabilities"
{
"type": "map",
"value": {
"address": "0x60006000",
"size": "0x1000",
"is_ro": false,
"is_io": true
}
}
*/
void waitForKeyA(PadState pad) {
while (appletMainLoop()) {
padUpdate(&pad);
u64 kDown = padGetButtonsDown(&pad);
if (kDown & HidNpadButton_A)
break;
consoleUpdate(NULL);
}
}
int main() {
consoleInit(NULL);
PadState pad;
padConfigureInput(1, HidNpadStyleSet_NpadStandard);
padInitializeDefault(&pad);
// Get clkrst MMIO virtual address
#define CLK_RST_IO_BASE 0x60006000
#define CLK_RST_IO_SIZE 0x1000
u64 virtaddr_base = 0;
u64 virtaddr_size = 0;
Result rc = svcQueryIoMapping(&virtaddr_base, &virtaddr_size, CLK_RST_IO_BASE, CLK_RST_IO_SIZE);
if (R_FAILED(rc)) {
printf("[ERROR] svcQueryIoMapping: 0x%X\n", rc);
consoleUpdate(NULL);
waitForKeyA(pad);
consoleExit(NULL);
return -1;
}
printf("virtaddr_base: 0x%lX\nvirtaddr_size: 0x%lX\n", virtaddr_base, virtaddr_size);
#define READ_REG(OFFSET) (*reinterpret_cast<volatile u32 *>(OFFSET))
#define GET_BITS(VAL, HIGH, LOW) ((VAL & ((1UL << (HIGH + 1UL)) - 1UL)) >> LOW)
#define GET_BIT(VAL, BIT) GET_BITS(VAL, BIT, BIT)
{
#define CLKRST_PLLX_BASE 0xE0
u32 pllx_base = READ_REG(virtaddr_base + CLKRST_PLLX_BASE);
printf("\n"\
"PLLX_BASE: 0x%X\n"\
"PLLX_ENABLE: %lu\n"\
"PLLX_REF_DIS: %lu\n"\
"PLLX_LOCK: %lu\n"\
"PLLX_DIVP: %lu\n"\
"PLLX_DIVN: %lu\n"\
"PLLX_DIVM: %lu",
pllx_base,
GET_BIT(pllx_base, 30),
GET_BIT(pllx_base, 29),
GET_BIT(pllx_base, 27),
GET_BITS(pllx_base, 24, 20),
GET_BITS(pllx_base, 15, 8),
GET_BITS(pllx_base, 7, 0));
}
{
#define CLKRST_PLLX_MISC 0xE4
u32 pllx_misc = READ_REG(virtaddr_base + CLKRST_PLLX_MISC);
printf("\n"\
"PLLX_MISC: 0x%X\n"\
"PLLX_FO_G_DISABLE: %lu\n"\
"PLLX_PTS: %lu\n"\
"PLLX_LOCK_ENABLE: %lu",
pllx_misc,
GET_BIT(pllx_misc, 28),
GET_BITS(pllx_misc, 23, 22),
GET_BIT(pllx_misc, 18));
}
{
#define CLKRST_PLLMB_SS_CFG 0x780
u32 pllmb_ss_cfg = READ_REG(virtaddr_base + CLKRST_PLLMB_SS_CFG);
printf("\n"\
"PLLMB_SS_CFG: 0x%X\n"\
"PLLMB_EN_SDM: %lu\n"\
"PLLMB_EN_SSC: %lu",
pllmb_ss_cfg,
GET_BIT(pllmb_ss_cfg, 31),
GET_BIT(pllmb_ss_cfg, 30));
}
{
#define CLKRST_PLLMB_SS_CTRL1 0x784
u32 pllmb_ss_ctrl1 = READ_REG(virtaddr_base + CLKRST_PLLMB_SS_CTRL1);
printf("\n"\
"PLLMB_SS_CTRL1: 0x%X\n"\
"PLLMB_SDM_SSC_MAX: %lu\n"\
"PLLMB_SDM_SSC_MIN: %lu",
pllmb_ss_ctrl1,
GET_BITS(pllmb_ss_ctrl1, 31, 16),
GET_BITS(pllmb_ss_ctrl1, 15, 0));
}
consoleUpdate(NULL);
waitForKeyA(pad);
consoleExit(NULL);
return 0;
}

2
ldr_config.py
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@@ -23,7 +23,7 @@ cust_conf = {
"marikoGpuMaxClock": 1305600,
# Mariko EMC:
# - RAM Clock in kHz:
# Values should be > 1600000, and divided evenly by 9600 or 12800.
# Values should be > 1600000, and divided evenly by 9600.
# [WARNING]
# RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
# - Graphical glitches