Compare commits
3 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
|
165c926135 | ||
|
|
d43bc68d0b | ||
|
|
c5edb031fa |
2
Makefile
2
Makefile
@@ -65,7 +65,6 @@ dist-no-debug: all
|
||||
mkdir -p atmosphere-$(AMSVER)/atmosphere/flags
|
||||
touch atmosphere-$(AMSVER)/atmosphere/flags/clean_stratosphere_for_0.19.0.flag
|
||||
cp fusee/fusee-primary/fusee-primary.bin atmosphere-$(AMSVER)/atmosphere/reboot_payload.bin
|
||||
cp fusee/fusee-mtc/fusee-mtc.bin atmosphere-$(AMSVER)/atmosphere/fusee-mtc.bin
|
||||
cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
|
||||
cp config_templates/BCT.ini atmosphere-$(AMSVER)/atmosphere/config_templates/BCT.ini
|
||||
cp config_templates/override_config.ini atmosphere-$(AMSVER)/atmosphere/config_templates/override_config.ini
|
||||
@@ -119,7 +118,6 @@ dist: dist-no-debug
|
||||
rm -rf atmosphere-$(AMSVER)-debug
|
||||
mkdir atmosphere-$(AMSVER)-debug
|
||||
cp fusee/fusee-primary/fusee-primary.elf atmosphere-$(AMSVER)-debug/fusee-primary.elf
|
||||
cp fusee/fusee-mtc/fusee-mtc.elf atmosphere-$(AMSVER)-debug/fusee-mtc.elf
|
||||
cp fusee/fusee-secondary/fusee-secondary-experimental.elf atmosphere-$(AMSVER)-debug/fusee-secondary.elf
|
||||
cp exosphere/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/exosphere-loader-stub.elf
|
||||
cp exosphere/program/program.elf atmosphere-$(AMSVER)-debug/exosphere-program.elf
|
||||
|
||||
@@ -1,4 +1,9 @@
|
||||
# Changelog
|
||||
## 0.20.1
|
||||
+ An issue was fixed that caused severely degraded performance after wake-from-sleep on Mariko hardware.
|
||||
+ This was due to Mariko MTC resulting in a frequency of 1599.999MHz instead of 1600MHz.
|
||||
+ Due to this off-by-one, Nintendo's EMC management code failed to initialize/take over, and after wake from sleep RAM would be in a strange state.
|
||||
+ General system stability improvements to enhance the user's experience.
|
||||
## 0.20.0
|
||||
+ DRAM training (MTC) was implemented for Mariko hardware, increasing RAM speed from 204MHz to 1600MHz.
|
||||
+ This significantly optimizes Mariko boot speed, cutting boot time roughly in half.
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
SUBFOLDERS := fusee-primary fusee-mtc fusee-secondary
|
||||
SUBFOLDERS := fusee-primary fusee-secondary
|
||||
|
||||
TOPTARGETS := all clean
|
||||
|
||||
|
||||
@@ -1,167 +0,0 @@
|
||||
#---------------------------------------------------------------------------------
|
||||
.SUFFIXES:
|
||||
#---------------------------------------------------------------------------------
|
||||
|
||||
ifeq ($(strip $(DEVKITARM)),)
|
||||
$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
|
||||
endif
|
||||
|
||||
TOPDIR ?= $(CURDIR)
|
||||
|
||||
AMS := $(TOPDIR)/../../
|
||||
include $(DEVKITARM)/base_rules
|
||||
|
||||
AMSBRANCH := $(shell git symbolic-ref --short HEAD)
|
||||
AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
|
||||
|
||||
ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
|
||||
AMSREV := $(AMSREV)-dirty
|
||||
endif
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# TARGET is the name of the output
|
||||
# BUILD is the directory where object files & intermediate files will be placed
|
||||
# SOURCES is a list of directories containing source code
|
||||
# DATA is a list of directories containing data files
|
||||
# INCLUDES is a list of directories containing header files
|
||||
#---------------------------------------------------------------------------------
|
||||
TARGET := $(notdir $(CURDIR))
|
||||
BUILD := build
|
||||
SOURCES := src ../../fusee/common ../../fusee/common/display
|
||||
DATA := data
|
||||
INCLUDES := include ../../libraries/libvapours/include
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# options for code generation
|
||||
#---------------------------------------------------------------------------------
|
||||
ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
|
||||
DEFINES := -D__BPMP__ -DFUSEE_MTC_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
|
||||
|
||||
CFLAGS := \
|
||||
-g \
|
||||
-gdwarf-4 \
|
||||
-O2 \
|
||||
-fomit-frame-pointer \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-std=gnu11 \
|
||||
-Werror \
|
||||
-Wall \
|
||||
-Wno-array-bounds \
|
||||
-Wno-stringop-overflow \
|
||||
-Wno-stringop-overread \
|
||||
-fstrict-volatile-bitfields \
|
||||
$(ARCH) $(DEFINES)
|
||||
|
||||
CFLAGS += $(INCLUDE)
|
||||
|
||||
CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
|
||||
|
||||
ASFLAGS := -g -gdwarf-4 $(ARCH)
|
||||
LDFLAGS = -specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map)
|
||||
|
||||
LIBS :=
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# list of directories containing libraries, this must be the top level containing
|
||||
# include and lib
|
||||
#---------------------------------------------------------------------------------
|
||||
LIBDIRS :=
|
||||
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# no real need to edit anything past this point unless you need to add additional
|
||||
# rules for different file extensions
|
||||
#---------------------------------------------------------------------------------
|
||||
ifneq ($(BUILD),$(notdir $(CURDIR)))
|
||||
#---------------------------------------------------------------------------------
|
||||
|
||||
export OUTPUT := $(CURDIR)/$(TARGET)
|
||||
export TOPDIR := $(CURDIR)
|
||||
|
||||
export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
|
||||
$(foreach dir,$(DATA),$(CURDIR)/$(dir))
|
||||
|
||||
export DEPSDIR := $(CURDIR)/$(BUILD)
|
||||
|
||||
CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
|
||||
CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
|
||||
SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
|
||||
BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*)))
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# use CXX for linking C++ projects, CC for standard C
|
||||
#---------------------------------------------------------------------------------
|
||||
ifeq ($(strip $(CPPFILES)),)
|
||||
#---------------------------------------------------------------------------------
|
||||
export LD := $(CC)
|
||||
#---------------------------------------------------------------------------------
|
||||
else
|
||||
#---------------------------------------------------------------------------------
|
||||
export LD := $(CXX)
|
||||
#---------------------------------------------------------------------------------
|
||||
endif
|
||||
#---------------------------------------------------------------------------------
|
||||
|
||||
export OFILES_BIN := $(addsuffix .o,$(BINFILES))
|
||||
export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
|
||||
export OFILES := $(OFILES_BIN) $(OFILES_SRC)
|
||||
export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES)))
|
||||
|
||||
export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
|
||||
$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
|
||||
-I$(CURDIR)/$(BUILD)
|
||||
|
||||
export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib)
|
||||
|
||||
.PHONY: $(BUILD) clean all
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
all: $(BUILD)
|
||||
|
||||
$(BUILD):
|
||||
@[ -d $@ ] || mkdir -p $@
|
||||
@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
clean:
|
||||
@echo clean ...
|
||||
@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
else
|
||||
.PHONY: all
|
||||
|
||||
DEPENDS := $(OFILES:.o=.d)
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# main targets
|
||||
#---------------------------------------------------------------------------------
|
||||
all : $(OUTPUT).bin
|
||||
|
||||
$(OUTPUT).bin : $(OUTPUT).elf
|
||||
$(OBJCOPY) -S -O binary $< $@
|
||||
@echo built ... $(notdir $@)
|
||||
|
||||
$(OUTPUT).elf : $(OFILES)
|
||||
|
||||
%.elf: $(OFILES)
|
||||
@echo linking $(notdir $@)
|
||||
@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
|
||||
@$(NM) -CSn $@ > $(notdir $*.lst)
|
||||
|
||||
$(OFILES_SRC) : $(HFILES_BIN)
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# you need a rule like this for each extension you use as binary data
|
||||
#---------------------------------------------------------------------------------
|
||||
%.bin.o %_bin.h: %.bin
|
||||
#---------------------------------------------------------------------------------
|
||||
@echo $(notdir $<)
|
||||
@$(bin2o)
|
||||
|
||||
-include $(DEPENDS)
|
||||
|
||||
#---------------------------------------------------------------------------------------
|
||||
endif
|
||||
#---------------------------------------------------------------------------------------
|
||||
@@ -1,170 +0,0 @@
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
|
||||
PHDRS
|
||||
{
|
||||
crt0 PT_LOAD;
|
||||
main PT_LOAD;
|
||||
}
|
||||
|
||||
/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */
|
||||
MEMORY
|
||||
{
|
||||
NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
|
||||
main : ORIGIN = 0xF0000000, LENGTH = 0x10000000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
PROVIDE(__start__ = 0xF0000000);
|
||||
PROVIDE(__stack_bottom__ = 0x90010000);
|
||||
PROVIDE(__stack_top__ = 0x90020000);
|
||||
PROVIDE(__heap_start__ = 0x90020000);
|
||||
PROVIDE(__heap_end__ = 0xA0020000);
|
||||
|
||||
. = __start__;
|
||||
|
||||
.crt0 :
|
||||
{
|
||||
KEEP( *(.text.start) )
|
||||
KEEP( *(.init) )
|
||||
. = ALIGN(32);
|
||||
} >main :crt0
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
/* .text */
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.stub)
|
||||
*(.gnu.warning)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* .fini */
|
||||
KEEP( *(.fini) )
|
||||
. = ALIGN(8);
|
||||
} >main :main
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.roda)
|
||||
*(.rodata.*)
|
||||
*all.rodata*(*)
|
||||
*(.gnu.linkonce.r*)
|
||||
SORT(CONSTRUCTORS)
|
||||
. = ALIGN(8);
|
||||
} >main
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
} >main
|
||||
|
||||
.init_array ALIGN(4) :
|
||||
{
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
} >main
|
||||
|
||||
.fini_array ALIGN(4) :
|
||||
{
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
} >main
|
||||
|
||||
.ctors ALIGN(4) :
|
||||
{
|
||||
KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
|
||||
} >main
|
||||
|
||||
.dtors ALIGN(4) :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
|
||||
} >main
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main
|
||||
ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = ABSOLUTE(.);} >main
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(32);
|
||||
} >main
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
PROVIDE (__bss_start__ = ABSOLUTE(.));
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b*)
|
||||
*(COMMON)
|
||||
. = ALIGN(32);
|
||||
PROVIDE (__bss_end__ = ABSOLUTE(.));
|
||||
} >main :NONE
|
||||
__end__ = ABSOLUTE(.) ;
|
||||
|
||||
|
||||
/* ==================
|
||||
==== Metadata ====
|
||||
================== */
|
||||
|
||||
/* Discard sections that difficult post-processing */
|
||||
/DISCARD/ : { *(.group .comment .note) }
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
}
|
||||
@@ -1,7 +0,0 @@
|
||||
%rename link old_link
|
||||
|
||||
*link:
|
||||
%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections
|
||||
|
||||
*startfile:
|
||||
crti%O%s crtbegin%O%s
|
||||
@@ -1,142 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "car.h"
|
||||
#include "timers.h"
|
||||
#include "utils.h"
|
||||
|
||||
static inline uint32_t get_clk_source_reg(CarDevice dev) {
|
||||
switch (dev) {
|
||||
case CARDEVICE_UARTA: return 0x178;
|
||||
case CARDEVICE_UARTB: return 0x17C;
|
||||
case CARDEVICE_UARTC: return 0x1A0;
|
||||
case CARDEVICE_I2C1: return 0x124;
|
||||
case CARDEVICE_I2C5: return 0x128;
|
||||
case CARDEVICE_TZRAM: return 0;
|
||||
case CARDEVICE_SE: return 0x42C;
|
||||
case CARDEVICE_HOST1X: return 0x180;
|
||||
case CARDEVICE_TSEC: return 0x1F4;
|
||||
case CARDEVICE_SOR_SAFE: return 0;
|
||||
case CARDEVICE_SOR0: return 0;
|
||||
case CARDEVICE_SOR1: return 0x410;
|
||||
case CARDEVICE_KFUSE: return 0;
|
||||
case CARDEVICE_CL_DVFS: return 0;
|
||||
case CARDEVICE_CORESIGHT: return 0x1D4;
|
||||
case CARDEVICE_MSELECT: return 0x3B4;
|
||||
case CARDEVICE_ACTMON: return 0x3E8;
|
||||
case CARDEVICE_BPMP: return 0;
|
||||
default: generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint32_t get_clk_source_val(CarDevice dev) {
|
||||
switch (dev) {
|
||||
case CARDEVICE_UARTA: return 0;
|
||||
case CARDEVICE_UARTB: return 0;
|
||||
case CARDEVICE_UARTC: return 0;
|
||||
case CARDEVICE_I2C1: return 6;
|
||||
case CARDEVICE_I2C5: return 6;
|
||||
case CARDEVICE_TZRAM: return 0;
|
||||
case CARDEVICE_SE: return 0;
|
||||
case CARDEVICE_HOST1X: return 4;
|
||||
case CARDEVICE_TSEC: return 0;
|
||||
case CARDEVICE_SOR_SAFE: return 0;
|
||||
case CARDEVICE_SOR0: return 0;
|
||||
case CARDEVICE_SOR1: return 0;
|
||||
case CARDEVICE_KFUSE: return 0;
|
||||
case CARDEVICE_CL_DVFS: return 0;
|
||||
case CARDEVICE_CORESIGHT: return 0;
|
||||
case CARDEVICE_MSELECT: return 0;
|
||||
case CARDEVICE_ACTMON: return 6;
|
||||
case CARDEVICE_BPMP: return 0;
|
||||
default: generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint32_t get_clk_source_div(CarDevice dev) {
|
||||
switch (dev) {
|
||||
case CARDEVICE_UARTA: return 0;
|
||||
case CARDEVICE_UARTB: return 0;
|
||||
case CARDEVICE_UARTC: return 0;
|
||||
case CARDEVICE_I2C1: return 0;
|
||||
case CARDEVICE_I2C5: return 0;
|
||||
case CARDEVICE_TZRAM: return 0;
|
||||
case CARDEVICE_SE: return 0;
|
||||
case CARDEVICE_HOST1X: return 3;
|
||||
case CARDEVICE_TSEC: return 2;
|
||||
case CARDEVICE_SOR_SAFE: return 0;
|
||||
case CARDEVICE_SOR0: return 0;
|
||||
case CARDEVICE_SOR1: return 2;
|
||||
case CARDEVICE_KFUSE: return 0;
|
||||
case CARDEVICE_CL_DVFS: return 0;
|
||||
case CARDEVICE_CORESIGHT: return 4;
|
||||
case CARDEVICE_MSELECT: return 6;
|
||||
case CARDEVICE_ACTMON: return 0;
|
||||
case CARDEVICE_BPMP: return 0;
|
||||
default: generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
|
||||
static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4};
|
||||
|
||||
void clk_enable(CarDevice dev) {
|
||||
uint32_t clk_source_reg;
|
||||
if ((clk_source_reg = get_clk_source_reg(dev))) {
|
||||
MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev);
|
||||
}
|
||||
MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
|
||||
}
|
||||
|
||||
void clk_disable(CarDevice dev) {
|
||||
MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
|
||||
}
|
||||
|
||||
void rst_enable(CarDevice dev) {
|
||||
MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
|
||||
}
|
||||
|
||||
void rst_disable(CarDevice dev) {
|
||||
MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
|
||||
}
|
||||
|
||||
void clkrst_enable(CarDevice dev) {
|
||||
clk_enable(dev);
|
||||
rst_disable(dev);
|
||||
}
|
||||
|
||||
void clkrst_disable(CarDevice dev) {
|
||||
rst_enable(dev);
|
||||
clk_disable(dev);
|
||||
}
|
||||
|
||||
void clkrst_reboot(CarDevice dev) {
|
||||
clkrst_disable(dev);
|
||||
if (dev == CARDEVICE_KFUSE) {
|
||||
/* Workaround for KFUSE clock. */
|
||||
clk_enable(dev);
|
||||
udelay(100);
|
||||
rst_disable(dev);
|
||||
udelay(200);
|
||||
} else {
|
||||
clkrst_enable(dev);
|
||||
}
|
||||
}
|
||||
|
||||
void clkrst_enable_fuse_regs(bool enable) {
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28));
|
||||
}
|
||||
@@ -1,519 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_CAR_H
|
||||
#define FUSEE_CAR_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define CAR_BASE 0x60006000
|
||||
#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n)
|
||||
|
||||
#define CLK_L_SDMMC1 (1 << 14)
|
||||
#define CLK_L_SDMMC2 (1 << 9)
|
||||
#define CLK_U_SDMMC3 (1 << 5)
|
||||
#define CLK_L_SDMMC4 (1 << 15)
|
||||
|
||||
#define CLK_SOURCE_MASK (0b111 << 29)
|
||||
#define CLK_SOURCE_FIRST (0b000 << 29)
|
||||
#define CLK_DIVIDER_MASK (0xff << 0)
|
||||
#define CLK_DIVIDER_UNITY (0x00 << 0)
|
||||
|
||||
#define NUM_CAR_BANKS 7
|
||||
|
||||
/* Clock and reset devices. */
|
||||
typedef enum {
|
||||
CARDEVICE_BPMP = ((0 << 5) | 0x1),
|
||||
CARDEVICE_UARTA = ((0 << 5) | 0x6),
|
||||
CARDEVICE_UARTB = ((0 << 5) | 0x7),
|
||||
CARDEVICE_I2C1 = ((0 << 5) | 0xC),
|
||||
CARDEVICE_USBD = ((0 << 5) | 0x16),
|
||||
CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
|
||||
CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
|
||||
CARDEVICE_APBDMA = ((1 << 5) | 0x2),
|
||||
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
|
||||
CARDEVICE_I2C5 = ((1 << 5) | 0xF),
|
||||
CARDEVICE_UARTC = ((1 << 5) | 0x17),
|
||||
CARDEVICE_USB2 = ((1 << 5) | 0x1A),
|
||||
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
|
||||
CARDEVICE_TSEC = ((2 << 5) | 0x13),
|
||||
CARDEVICE_MSELECT = ((3 << 5) | 0x8),
|
||||
CARDEVICE_ACTMON = ((3 << 5) | 0x17),
|
||||
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
|
||||
CARDEVICE_SE = ((3 << 5) | 0x1F),
|
||||
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
|
||||
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
|
||||
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
|
||||
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
|
||||
} CarDevice;
|
||||
|
||||
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
|
||||
typedef struct {
|
||||
uint32_t rst_src; /* _RST_SOURCE_0, 0x00 */
|
||||
|
||||
/* _RST_DEVICES_L/H/U_0 0x4-0xc */
|
||||
uint32_t rst_dev_l;
|
||||
uint32_t rst_dev_h;
|
||||
uint32_t rst_dev_u;
|
||||
|
||||
/* _CLK_OUT_ENB_L/H/U_0 0x10-0x18 */
|
||||
uint32_t clk_out_enb_l;
|
||||
uint32_t clk_out_enb_h;
|
||||
uint32_t clk_out_enb_u;
|
||||
|
||||
uint32_t _0x1C;
|
||||
uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
|
||||
uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0, 0x24 */
|
||||
uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
|
||||
uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0, 0x2c */
|
||||
uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
|
||||
uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
|
||||
uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0, 0x38 */
|
||||
uint32_t _0x3C;
|
||||
uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0, 0x40 */
|
||||
uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
|
||||
uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
|
||||
uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4c */
|
||||
uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */
|
||||
uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */
|
||||
uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
|
||||
uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0, 0x5c */
|
||||
uint32_t _0x60[2];
|
||||
uint32_t plle_ss_cntl; /* _PLLE_SS_CNTL_0, 0x68 */
|
||||
uint32_t plle_misc1; /* _PLLE_MISC1_0, 0x6c */
|
||||
uint32_t _0x70[4];
|
||||
|
||||
/* PLLC 0x80-0x8c */
|
||||
uint32_t pllc_base;
|
||||
uint32_t pllc_out;
|
||||
uint32_t pllc_misc0;
|
||||
uint32_t pllc_misc1;
|
||||
|
||||
/* PLLM 0x90-0x9c */
|
||||
uint32_t pllm_base;
|
||||
uint32_t pllm_out;
|
||||
uint32_t pllm_misc1;
|
||||
uint32_t pllm_misc2;
|
||||
|
||||
/* PLLP 0xa0-0xac */
|
||||
uint32_t pllp_base;
|
||||
uint32_t pllp_outa;
|
||||
uint32_t pllp_outb;
|
||||
uint32_t pllp_misc;
|
||||
|
||||
/* PLLA 0xb0-0xbc */
|
||||
uint32_t plla_base;
|
||||
uint32_t plla_out;
|
||||
uint32_t plla_misc0;
|
||||
uint32_t plla_misc1;
|
||||
|
||||
/* PLLU 0xc0-0xcc */
|
||||
uint32_t pllu_base;
|
||||
uint32_t pllu_out;
|
||||
uint32_t pllu_misc1;
|
||||
uint32_t pllu_misc2;
|
||||
|
||||
/* PLLD 0xd0-0xdc */
|
||||
uint32_t plld_base;
|
||||
uint32_t plld_out;
|
||||
uint32_t plld_misc1;
|
||||
uint32_t plld_misc2;
|
||||
|
||||
/* PLLX 0xe0-0xe4 */
|
||||
uint32_t pllx_base;
|
||||
uint32_t pllx_misc;
|
||||
|
||||
/* PLLE 0xe8-0xf4 */
|
||||
uint32_t plle_base;
|
||||
uint32_t plle_misc;
|
||||
uint32_t plle_ss_cntl1;
|
||||
uint32_t plle_ss_cntl2;
|
||||
|
||||
uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */
|
||||
uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */
|
||||
|
||||
uint32_t clk_source_i2s2; /* _CLK_SOURCE_I2S2_0, 0x100 */
|
||||
uint32_t clk_source_i2s3; /* _CLK_SOURCE_I2S3_0, 0x104 */
|
||||
uint32_t clk_source_spdif_out; /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */
|
||||
uint32_t clk_source_spdif_in; /* _CLK_SOURCE_SPDIF_IN_0, 0x10c */
|
||||
uint32_t clk_source_pwm; /* _CLK_SOURCE_PWM_0, 0x110 */
|
||||
uint32_t _0x114;
|
||||
uint32_t clk_source_spi2; /* _CLK_SOURCE_SPI2_0, 0x118 */
|
||||
uint32_t clk_source_spi3; /* _CLK_SOURCE_SPI3_0, 0x11c */
|
||||
uint32_t _0x120;
|
||||
uint32_t clk_source_i2c1; /* _CLK_SOURCE_I2C1_0, 0x124 */
|
||||
uint32_t clk_source_i2c5; /* _CLK_SOURCE_I2C5_0, 0x128 */
|
||||
uint32_t _0x12c[2];
|
||||
uint32_t clk_source_spi1; /* _CLK_SOURCE_SPI1_0, 0x134 */
|
||||
uint32_t clk_source_disp1; /* _CLK_SOURCE_DISP1_0, 0x138 */
|
||||
uint32_t clk_source_disp2; /* _CLK_SOURCE_DISP2_0, 0x13c */
|
||||
uint32_t _0x140;
|
||||
uint32_t clk_source_isp; /* _CLK_SOURCE_ISP_0, 0x144 */
|
||||
uint32_t clk_source_vi; /* _CLK_SOURCE_VI_0, 0x148 */
|
||||
uint32_t _0x14c;
|
||||
uint32_t clk_source_sdmmc1; /* _CLK_SOURCE_SDMMC1_0, 0x150 */
|
||||
uint32_t clk_source_sdmmc2; /* _CLK_SOURCE_SDMMC2_0, 0x154 */
|
||||
uint32_t _0x158[3];
|
||||
uint32_t clk_source_sdmmc4; /* _CLK_SOURCE_SDMMC4_0, 0x164 */
|
||||
uint32_t _0x168[4];
|
||||
uint32_t clk_source_uarta; /* _CLK_SOURCE_UARTA_0, 0x178 */
|
||||
uint32_t clk_source_uartb; /* _CLK_SOURCE_UARTB_0, 0x17c */
|
||||
uint32_t clk_source_host1x; /* _CLK_SOURCE_HOST1X_0, 0x180 */
|
||||
uint32_t _0x184[5];
|
||||
uint32_t clk_source_i2c2; /* _CLK_SOURCE_I2C2_0, 0x198 */
|
||||
uint32_t clk_source_emc; /* _CLK_SOURCE_EMC_0, 0x19c */
|
||||
uint32_t clk_source_uartc; /* _CLK_SOURCE_UARTC_0, 0x1a0 */
|
||||
uint32_t _0x1a4;
|
||||
uint32_t clk_source_vi_sensor; /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */
|
||||
uint32_t _0x1ac[2];
|
||||
uint32_t clk_source_spi4; /* _CLK_SOURCE_SPI4_0, 0x1b4 */
|
||||
uint32_t clk_source_i2c3; /* _CLK_SOURCE_I2C3_0, 0x1b8 */
|
||||
uint32_t clk_source_sdmmc3; /* _CLK_SOURCE_SDMMC3_0, 0x1bc */
|
||||
uint32_t clk_source_uartd; /* _CLK_SOURCE_UARTD_0, 0x1c0 */
|
||||
uint32_t _0x1c4[2];
|
||||
uint32_t clk_source_owr; /* _CLK_SOURCE_OWR_0, 0x1cc */
|
||||
uint32_t _0x1d0;
|
||||
uint32_t clk_source_csite; /* _CLK_SOURCE_CSITE_0, 0x1d4 */
|
||||
uint32_t clk_source_i2s1; /* _CLK_SOURCE_I2S1_0, 0x1d8 */
|
||||
uint32_t clk_source_dtv; /* _CLK_SOURCE_DTV_0, 0x1dc */
|
||||
uint32_t _0x1e0[5];
|
||||
uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */
|
||||
uint32_t _0x1f8;
|
||||
|
||||
uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */
|
||||
uint32_t _0x200[32];
|
||||
|
||||
uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
|
||||
uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
|
||||
uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
|
||||
|
||||
uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
|
||||
uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
|
||||
uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
|
||||
|
||||
uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
|
||||
uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
|
||||
uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
|
||||
|
||||
uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
|
||||
uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
|
||||
uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
|
||||
|
||||
uint32_t _0x2b0[17];
|
||||
uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */
|
||||
uint32_t _0x2f8[2];
|
||||
|
||||
/* _RST_DEV_L/H/U_SET_0 0x300-0x314 */
|
||||
uint32_t rst_dev_l_set;
|
||||
uint32_t rst_dev_l_clr;
|
||||
uint32_t rst_dev_h_set;
|
||||
uint32_t rst_dev_h_clr;
|
||||
uint32_t rst_dev_u_set;
|
||||
uint32_t rst_dev_u_clr;
|
||||
|
||||
uint32_t _0x318[2];
|
||||
|
||||
/* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */
|
||||
uint32_t clk_enb_l_set;
|
||||
uint32_t clk_enb_l_clr;
|
||||
uint32_t clk_enb_h_set;
|
||||
uint32_t clk_enb_h_clr;
|
||||
uint32_t clk_enb_u_set;
|
||||
uint32_t clk_enb_u_clr;
|
||||
|
||||
uint32_t _0x338;
|
||||
uint32_t ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */
|
||||
uint32_t rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
|
||||
uint32_t rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
|
||||
|
||||
/* Additional (T30) registers */
|
||||
uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
|
||||
uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
|
||||
|
||||
uint32_t _0x350[2];
|
||||
uint32_t rst_dev_v; /* _RST_DEVICES_V_0, 0x358 */
|
||||
uint32_t rst_dev_w; /* _RST_DEVICES_W_0, 0x35c */
|
||||
uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V_0, 0x360 */
|
||||
uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_W_0, 0x364 */
|
||||
uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
|
||||
uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36c */
|
||||
uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
|
||||
uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
|
||||
uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
|
||||
uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37c */
|
||||
uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
|
||||
uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
|
||||
uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
|
||||
uint32_t _0x38c[5];
|
||||
uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */
|
||||
uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */
|
||||
uint32_t _0x3a8[2];
|
||||
|
||||
uint32_t _0x3b0;
|
||||
uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */
|
||||
uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */
|
||||
uint32_t clk_source_i2s4; /* _CLK_SOURCE_I2S4_0, 0x3bc */
|
||||
uint32_t clk_source_i2s5; /* _CLK_SOURCE_I2S5_0, 0x3c0 */
|
||||
uint32_t clk_source_i2c4; /* _CLK_SOURCE_I2C4_0, 0x3c4 */
|
||||
uint32_t _0x3c8[2];
|
||||
uint32_t clk_source_ahub; /* _CLK_SOURCE_AHUB_0, 0x3d0 */
|
||||
uint32_t _0x3d4[4];
|
||||
uint32_t clk_source_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X_0, 0x3e4 */
|
||||
uint32_t clk_source_actmon; /* _CLK_SOURCE_ACTMON_0, 0x3e8 */
|
||||
uint32_t clk_source_extperiph1; /* _CLK_SOURCE_EXTPERIPH1_0, 0x3ec */
|
||||
uint32_t clk_source_extperiph2; /* _CLK_SOURCE_EXTPERIPH2_0, 0x3f0 */
|
||||
uint32_t clk_source_extperiph3; /* _CLK_SOURCE_EXTPERIPH3_0, 0x3f4 */
|
||||
uint32_t _0x3f8;
|
||||
uint32_t clk_source_i2c_slow; /* _CLK_SOURCE_I2C_SLOW_0, 0x3fc */
|
||||
uint32_t clk_source_sys; /* _CLK_SOURCE_SYS_0, 0x400 */
|
||||
uint32_t clk_source_ispb; /* _CLK_SOURCE_ISPB_0, 0x404 */
|
||||
uint32_t _0x408[2];
|
||||
uint32_t clk_source_sor1; /* _CLK_SOURCE_SOR1_0, 0x410 */
|
||||
uint32_t clk_source_sor0; /* _CLK_SOURCE_SOR0_0, 0x414 */
|
||||
uint32_t _0x418[2];
|
||||
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
|
||||
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
|
||||
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
|
||||
uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
|
||||
|
||||
/* _RST_DEV_V/W_SET_0 0x430-0x43c */
|
||||
uint32_t rst_dev_v_set;
|
||||
uint32_t rst_dev_v_clr;
|
||||
uint32_t rst_dev_w_set;
|
||||
uint32_t rst_dev_w_clr;
|
||||
|
||||
/* _CLK_ENB_V/W_CLR_0 0x440-0x44c */
|
||||
uint32_t clk_enb_v_set;
|
||||
uint32_t clk_enb_v_clr;
|
||||
uint32_t clk_enb_w_set;
|
||||
uint32_t clk_enb_w_clr;
|
||||
|
||||
/* Additional (T114+) registers */
|
||||
uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
|
||||
uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
|
||||
uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
|
||||
uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45c */
|
||||
uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
|
||||
uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
|
||||
uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
|
||||
uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46c */
|
||||
uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
|
||||
uint32_t _0x474;
|
||||
uint32_t intstatus; /* _INTSTATUS_0, 0x478 */
|
||||
uint32_t intmask; /* _INTMASK_0, 0x47c */
|
||||
uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
|
||||
uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
|
||||
uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
|
||||
|
||||
uint32_t plle_aux; /* _PLLE_AUX_0, 0x48c */
|
||||
uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
|
||||
uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
|
||||
uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
|
||||
|
||||
uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49c */
|
||||
uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4a0 */
|
||||
uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4a4 */
|
||||
uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4a8 */
|
||||
uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4ac */
|
||||
uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4b0 */
|
||||
uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */
|
||||
|
||||
uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4b8 */
|
||||
uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4bc */
|
||||
uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4c0 */
|
||||
uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4c4 */
|
||||
uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4c8 */
|
||||
uint32_t pllrefe_out; /* _PLLREFE_OUT_0, 0x4cc */
|
||||
uint32_t cpu_finetrim_byp; /* _CPU_FINETRIM_BYP_0, 0x4d0 */
|
||||
uint32_t cpu_finetrim_select; /* _CPU_FINETRIM_SELECT_0, 0x4d4 */
|
||||
uint32_t cpu_finetrim_dr; /* _CPU_FINETRIM_DR_0, 0x4d8 */
|
||||
uint32_t cpu_finetrim_df; /* _CPU_FINETRIM_DF_0, 0x4dc */
|
||||
uint32_t cpu_finetrim_f; /* _CPU_FINETRIM_F_0, 0x4e0 */
|
||||
uint32_t cpu_finetrim_r; /* _CPU_FINETRIM_R_0, 0x4e4 */
|
||||
uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4e8 */
|
||||
uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4ec */
|
||||
uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4f0 */
|
||||
uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4f4 */
|
||||
uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4f8 */
|
||||
uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4fc */
|
||||
uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
|
||||
uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
|
||||
uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
|
||||
uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50c */
|
||||
uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
|
||||
uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
|
||||
uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
|
||||
uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51c */
|
||||
uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
|
||||
uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */
|
||||
uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
|
||||
uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */
|
||||
uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
|
||||
uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
|
||||
uint32_t _0x538;
|
||||
uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53c */
|
||||
uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
|
||||
uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
|
||||
uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
|
||||
uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54c */
|
||||
uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
|
||||
uint32_t lvl2_clk_gate_ovre; /* _LVL2_CLK_GATE_OVRE, 0x554 */
|
||||
uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
|
||||
uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */
|
||||
uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
|
||||
uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
|
||||
|
||||
uint32_t _0x568[2];
|
||||
uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */
|
||||
uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */
|
||||
uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */
|
||||
uint32_t _0x57c[5];
|
||||
|
||||
uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/
|
||||
uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */
|
||||
uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
|
||||
uint32_t plldp_ss_ctrl1; /* _PLLDP_SS_CTRL1_0, 0x59c */
|
||||
uint32_t plldp_ss_ctrl2; /* _PLLDP_SS_CTRL2_0, 0x5a0 */
|
||||
uint32_t pllc4_base; /* _PLLC4_BASE_0, 0x5a4 */
|
||||
uint32_t pllc4_misc; /* _PLLC4_MISC_0, 0x5a8 */
|
||||
uint32_t _0x5ac[6];
|
||||
uint32_t clk_spare0; /* _CLK_SPARE0_0, 0x5c4 */
|
||||
uint32_t clk_spare1; /* _CLK_SPARE1_0, 0x5c8 */
|
||||
uint32_t gpu_isob_ctrl; /* _GPU_ISOB_CTRL_0, 0x5cc */
|
||||
uint32_t pllc_misc2; /* _PLLC_MISC_2_0, 0x5d0 */
|
||||
uint32_t pllc_misc3; /* _PLLC_MISC_3_0, 0x5d4 */
|
||||
uint32_t plla_misc2; /* _PLLA_MISC2_0, 0x5d8 */
|
||||
uint32_t _0x5dc[2];
|
||||
uint32_t pllc4_out; /* _PLLC4_OUT_0, 0x5e4 */
|
||||
uint32_t pllmb_base; /* _PLLMB_BASE_0, 0x5e8 */
|
||||
uint32_t pllmb_misc1; /* _PLLMB_MISC1_0, 0x5ec */
|
||||
uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */
|
||||
uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */
|
||||
uint32_t _0x5f8[2];
|
||||
|
||||
uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */
|
||||
uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */
|
||||
uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */
|
||||
uint32_t clk_source_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV_0, 0x60c */
|
||||
uint32_t clk_source_xusb_ss; /* _CLK_SOURCE_XUSB_SS_0, 0x610 */
|
||||
uint32_t clk_source_cilab; /* _CLK_SOURCE_CILAB_0, 0x614 */
|
||||
uint32_t clk_source_cilcd; /* _CLK_SOURCE_CILCD_0, 0x618 */
|
||||
uint32_t clk_source_cilef; /* _CLK_SOURCE_CILEF_0, 0x61c */
|
||||
uint32_t clk_source_dsia_lp; /* _CLK_SOURCE_DSIA_LP_0, 0x620 */
|
||||
uint32_t clk_source_dsib_lp; /* _CLK_SOURCE_DSIB_LP_0, 0x624 */
|
||||
uint32_t clk_source_entropy; /* _CLK_SOURCE_ENTROPY_0, 0x628 */
|
||||
uint32_t clk_source_dvfs_ref; /* _CLK_SOURCE_DVFS_REF_0, 0x62c */
|
||||
uint32_t clk_source_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC_0, 0x630 */
|
||||
uint32_t _0x634[3];
|
||||
uint32_t clk_source_emc_latency; /* _CLK_SOURCE_EMC_LATENCY_0, 0x640 */
|
||||
uint32_t clk_source_soc_therm; /* _CLK_SOURCE_SOC_THERM_0, 0x644 */
|
||||
uint32_t _0x648;
|
||||
uint32_t clk_source_dmic1; /* _CLK_SOURCE_DMIC1_0, 0x64c */
|
||||
uint32_t clk_source_dmic2; /* _CLK_SOURCE_DMIC2_0, 0x650 */
|
||||
uint32_t _0x654;
|
||||
uint32_t clk_source_vi_sensor2; /* _CLK_SOURCE_VI_SENSOR2_0, 0x658 */
|
||||
uint32_t clk_source_i2c6; /* _CLK_SOURCE_I2C6_0, 0x65c */
|
||||
uint32_t clk_source_mipibif; /* _CLK_SOURCE_MIPIBIF_0, 0x660 */
|
||||
uint32_t clk_source_emc_dll; /* _CLK_SOURCE_EMC_DLL_0, 0x664 */
|
||||
uint32_t _0x668;
|
||||
uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */
|
||||
uint32_t _0x670[2];
|
||||
uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */
|
||||
|
||||
uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */
|
||||
uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */
|
||||
uint32_t _0x684[2];
|
||||
uint32_t emc_div_clk_shaper_ctrl; /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */
|
||||
uint32_t emc_pllc_shaper_ctrl; /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */
|
||||
|
||||
uint32_t clk_source_sdmmc_legacy_tm; /* _CLK_SOURCE_SDMMC_LEGACY_TM_0, 0x694 */
|
||||
uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */
|
||||
uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */
|
||||
uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */
|
||||
|
||||
uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */
|
||||
uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */
|
||||
uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */
|
||||
uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */
|
||||
uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */
|
||||
uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
|
||||
|
||||
uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */
|
||||
uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */
|
||||
uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */
|
||||
uint32_t clk_source_vi_i2c; /* _CLK_SOURCE_VI_I2C_0, 0x6c8 */
|
||||
uint32_t clk_source_usb2_hsic_trk; /* _CLK_SOURCE_USB2_HSIC_TRK_0, 0x6cc */
|
||||
uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */
|
||||
uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */
|
||||
uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */
|
||||
|
||||
uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */
|
||||
uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */
|
||||
uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
|
||||
|
||||
uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
|
||||
uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
|
||||
uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
|
||||
uint32_t nvdec_super_clk_divider; /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */
|
||||
uint32_t isp_super_clk_divider; /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */
|
||||
uint32_t ispb_super_clk_divider; /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */
|
||||
uint32_t nvjpg_super_clk_divider; /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */
|
||||
uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
|
||||
uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
|
||||
uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
|
||||
|
||||
uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */
|
||||
uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */
|
||||
uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */
|
||||
uint32_t clk_ccplex_cc4_ret_clk_enb; /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */
|
||||
uint32_t actmon_cpu_clk; /* _ACTMON_CPU_CLK_0, 0x720 */
|
||||
uint32_t clk_source_emc_safe; /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */
|
||||
uint32_t sdmmc2_pllc4_out0_shaper_ctrl; /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */
|
||||
uint32_t sdmmc2_pllc4_out1_shaper_ctrl; /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */
|
||||
uint32_t sdmmc2_pllc4_out2_shaper_ctrl; /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */
|
||||
uint32_t sdmmc2_div_clk_shaper_ctrl; /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */
|
||||
uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
|
||||
uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
|
||||
uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
|
||||
uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
|
||||
|
||||
uint32_t _0x748[(0x774-0x748) / sizeof(uint32_t)]; // TODO
|
||||
|
||||
uint32_t pllm_ss_cfg; /* _PLLM_SS_CFG_0, 0x744 */
|
||||
uint32_t pllm_ss_ctrl1; /* _PLLM_SS_CTRL1_0, 0x778 */
|
||||
uint32_t pllm_ss_ctrl2; /* _PLLM_SS_CTRL2_0, 0x77C */
|
||||
uint32_t pllmb_ss_cfg; /* _PLLMB_SS_CFG_0, 0x780 */
|
||||
uint32_t pllmb_ss_ctrl1; /* _PLLMB_SS_CTRL1_0, 0x784 */
|
||||
uint32_t pllmb_ss_ctrl2; /* _PLLMB_SS_CTRL2_0, 0x788 */
|
||||
} tegra_car_t;
|
||||
|
||||
static inline volatile tegra_car_t *car_get_regs(void) {
|
||||
return (volatile tegra_car_t *)CAR_BASE;
|
||||
}
|
||||
|
||||
void clk_enable(CarDevice dev);
|
||||
void clk_disable(CarDevice dev);
|
||||
void rst_enable(CarDevice dev);
|
||||
void rst_disable(CarDevice dev);
|
||||
|
||||
void clkrst_enable(CarDevice dev);
|
||||
void clkrst_disable(CarDevice dev);
|
||||
void clkrst_reboot(CarDevice dev);
|
||||
|
||||
void clkrst_enable_fuse_regs(bool enable);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,346 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <vapours/ams_version.h>
|
||||
|
||||
#include "car.h"
|
||||
#include "fuse.h"
|
||||
#include "pmc.h"
|
||||
#include "timers.h"
|
||||
|
||||
/* Initialize the fuse driver */
|
||||
void fuse_init(void) {
|
||||
/* Make all fuse registers visible, disable the private key and disable programming. */
|
||||
clkrst_enable_fuse_regs(true);
|
||||
fuse_disable_private_key();
|
||||
fuse_disable_programming();
|
||||
}
|
||||
|
||||
/* Disable access to the private key and set the TZ sticky bit. */
|
||||
void fuse_disable_private_key(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
|
||||
}
|
||||
|
||||
/* Disable all fuse programming. */
|
||||
void fuse_disable_programming(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse->FUSE_DISABLEREGPROGRAM = 1;
|
||||
}
|
||||
|
||||
/* Enable power to the fuse hardware array. */
|
||||
void fuse_enable_power(void) {
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
pmc->fuse_control &= ~(0x200); /* Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
|
||||
mdelay(1);
|
||||
pmc->fuse_control |= 0x100; /* Set PMC_FUSE_CTRL_PS18_LATCH_SET. */
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
/* Disable power to the fuse hardware array. */
|
||||
void fuse_disable_power(void) {
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
pmc->fuse_control &= ~(0x100); /* Clear PMC_FUSE_CTRL_PS18_LATCH_SET. */
|
||||
mdelay(1);
|
||||
pmc->fuse_control |= 0x200; /* Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
/* Wait for the fuse driver to go idle. */
|
||||
static void fuse_wait_idle(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
uint32_t ctrl_val = 0;
|
||||
|
||||
/* Wait for STATE_IDLE */
|
||||
while ((ctrl_val & (0xF0000)) != 0x40000) {
|
||||
ctrl_val = fuse->FUSE_FUSECTRL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read a fuse from the hardware array. */
|
||||
uint32_t fuse_hw_read(uint32_t addr) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
|
||||
/* Wait for idle state. */
|
||||
fuse_wait_idle();
|
||||
|
||||
/* Program the target address. */
|
||||
fuse->FUSE_FUSEADDR = addr;
|
||||
|
||||
/* Enable read operation in control register. */
|
||||
uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
|
||||
ctrl_val &= ~0x3;
|
||||
ctrl_val |= 0x1; /* Set READ command. */
|
||||
fuse->FUSE_FUSECTRL = ctrl_val;
|
||||
|
||||
/* Wait for idle state. */
|
||||
fuse_wait_idle();
|
||||
|
||||
return fuse->FUSE_FUSERDATA;
|
||||
}
|
||||
|
||||
/* Write a fuse in the hardware array. */
|
||||
void fuse_hw_write(uint32_t value, uint32_t addr) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
|
||||
/* Wait for idle state. */
|
||||
fuse_wait_idle();
|
||||
|
||||
/* Program the target address and value. */
|
||||
fuse->FUSE_FUSEADDR = addr;
|
||||
fuse->FUSE_FUSEWDATA = value;
|
||||
|
||||
/* Enable write operation in control register. */
|
||||
uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
|
||||
ctrl_val &= ~0x3;
|
||||
ctrl_val |= 0x2; /* Set WRITE command. */
|
||||
fuse->FUSE_FUSECTRL = ctrl_val;
|
||||
|
||||
/* Wait for idle state. */
|
||||
fuse_wait_idle();
|
||||
}
|
||||
|
||||
/* Sense the fuse hardware array into the fuse cache. */
|
||||
void fuse_hw_sense(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
|
||||
/* Wait for idle state. */
|
||||
fuse_wait_idle();
|
||||
|
||||
/* Enable sense operation in control register */
|
||||
uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
|
||||
ctrl_val &= ~0x3;
|
||||
ctrl_val |= 0x3; /* Set SENSE_CTRL command */
|
||||
fuse->FUSE_FUSECTRL = ctrl_val;
|
||||
|
||||
/* Wait for idle state. */
|
||||
fuse_wait_idle();
|
||||
}
|
||||
|
||||
/* Read the SKU info register. */
|
||||
uint32_t fuse_get_sku_info(void) {
|
||||
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
|
||||
return fuse_chip->FUSE_SKU_INFO;
|
||||
}
|
||||
|
||||
/* Read the bootrom patch version. */
|
||||
uint32_t fuse_get_bootrom_patch_version(void) {
|
||||
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
|
||||
return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
|
||||
}
|
||||
|
||||
/* Read a spare bit register. */
|
||||
uint32_t fuse_get_spare_bit(uint32_t index) {
|
||||
uint32_t soc_type = fuse_get_soc_type();
|
||||
if (soc_type == 0) {
|
||||
if (index < 32) {
|
||||
volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs();
|
||||
return fuse_chip->FUSE_SPARE_BIT[index];
|
||||
}
|
||||
} else if (soc_type == 1) {
|
||||
if (index < 30) {
|
||||
volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
|
||||
return fuse_chip->FUSE_SPARE_BIT[index];
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Read a reserved ODM register. */
|
||||
uint32_t fuse_get_reserved_odm(uint32_t index) {
|
||||
if (index < 8) {
|
||||
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
|
||||
return fuse_chip->FUSE_RESERVED_ODM0[index];
|
||||
} else {
|
||||
uint32_t soc_type = fuse_get_soc_type();
|
||||
if (soc_type == 1) {
|
||||
volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
|
||||
if (index < 22) {
|
||||
return fuse_chip->FUSE_RESERVED_ODM8[index - 8];
|
||||
} else if (index < 25) {
|
||||
return fuse_chip->FUSE_RESERVED_ODM22[index - 22];
|
||||
} else if (index < 26) {
|
||||
return fuse_chip->FUSE_RESERVED_ODM25;
|
||||
} else if (index < 29) {
|
||||
return fuse_chip->FUSE_RESERVED_ODM26[index - 26];
|
||||
} else if (index < 30) {
|
||||
return fuse_chip->FUSE_RESERVED_ODM29;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get the DramId. */
|
||||
uint32_t fuse_get_dram_id(void) {
|
||||
return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
|
||||
}
|
||||
|
||||
/* Derive the DeviceId. */
|
||||
uint64_t fuse_get_device_id(void) {
|
||||
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
|
||||
|
||||
uint64_t device_id = 0;
|
||||
uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
|
||||
uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
|
||||
uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
|
||||
uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0;
|
||||
uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
|
||||
|
||||
uint64_t derived_lot_code = 0;
|
||||
for (unsigned int i = 0; i < 5; i++) {
|
||||
derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
|
||||
}
|
||||
derived_lot_code &= 0x03FFFFFF;
|
||||
|
||||
device_id |= y_coord << 0;
|
||||
device_id |= x_coord << 9;
|
||||
device_id |= wafer_id << 18;
|
||||
device_id |= derived_lot_code << 24;
|
||||
device_id |= fab_code << 50;
|
||||
|
||||
return device_id;
|
||||
}
|
||||
|
||||
/* Derive the HardwareType with firmware specific checks. */
|
||||
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) {
|
||||
uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
|
||||
uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
|
||||
|
||||
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) {
|
||||
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
|
||||
uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1);
|
||||
|
||||
switch (hardware_type) {
|
||||
case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3;
|
||||
case 0x01: return 0; /* HardwareType_Icosa */
|
||||
case 0x02: return 1; /* HardwareType_Copper */
|
||||
default: return 3; /* HardwareType_Undefined */
|
||||
}
|
||||
} else {
|
||||
hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
|
||||
|
||||
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
|
||||
switch (hardware_type) {
|
||||
case 0x01: return 0; /* HardwareType_Icosa */
|
||||
case 0x02: return 1; /* HardwareType_Copper */
|
||||
case 0x04: return 3; /* HardwareType_Iowa */
|
||||
default: return 4; /* HardwareType_Undefined */
|
||||
}
|
||||
} else {
|
||||
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) {
|
||||
switch (hardware_type) {
|
||||
case 0x01: return 0; /* HardwareType_Icosa */
|
||||
case 0x02: return 4; /* HardwareType_Calcio */
|
||||
case 0x04: return 3; /* HardwareType_Iowa */
|
||||
case 0x08: return 2; /* HardwareType_Hoag */
|
||||
default: return 0xF; /* HardwareType_Undefined */
|
||||
}
|
||||
} else {
|
||||
switch (hardware_type) {
|
||||
case 0x01: return 0; /* HardwareType_Icosa */
|
||||
case 0x02: return 4; /* HardwareType_Calcio */
|
||||
case 0x04: return 3; /* HardwareType_Iowa */
|
||||
case 0x08: return 2; /* HardwareType_Hoag */
|
||||
case 0x10: return 5; /* HardwareType_Five */
|
||||
default: return 0xF; /* HardwareType_Undefined */
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Derive the HardwareType. */
|
||||
uint32_t fuse_get_hardware_type(void) {
|
||||
return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT);
|
||||
}
|
||||
|
||||
/* Derive the HardwareState. */
|
||||
uint32_t fuse_get_hardware_state(void) {
|
||||
uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
|
||||
uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
|
||||
|
||||
switch (hardware_state) {
|
||||
case 0x03: return 0; /* HardwareState_Development */
|
||||
case 0x04: return 1; /* HardwareState_Production */
|
||||
default: return 2; /* HardwareState_Undefined */
|
||||
}
|
||||
}
|
||||
|
||||
/* Derive the 16-byte HardwareInfo and copy to output buffer. */
|
||||
void fuse_get_hardware_info(void *dst) {
|
||||
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
|
||||
uint32_t hw_info[0x4];
|
||||
|
||||
uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
|
||||
uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
|
||||
uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
|
||||
uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
|
||||
uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0;
|
||||
uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF;
|
||||
uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
|
||||
uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF;
|
||||
|
||||
/* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
|
||||
hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved));
|
||||
hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
|
||||
hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
|
||||
hw_info[3] = (uint32_t)(vendor_code);
|
||||
|
||||
memcpy(dst, hw_info, 0x10);
|
||||
}
|
||||
|
||||
/* Check if have a new ODM fuse format. */
|
||||
bool fuse_is_new_format(void) {
|
||||
return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2));
|
||||
}
|
||||
|
||||
/* Get the DeviceUniqueKeyGeneration. */
|
||||
uint32_t fuse_get_device_unique_key_generation(void) {
|
||||
if (fuse_is_new_format()) {
|
||||
return (fuse_get_reserved_odm(2) & 0x1F);
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get the SocType from the HardwareType. */
|
||||
uint32_t fuse_get_soc_type(void) {
|
||||
switch (fuse_get_hardware_type()) {
|
||||
case 0:
|
||||
case 1:
|
||||
return 0; /* SocType_Erista */
|
||||
case 3:
|
||||
case 2:
|
||||
case 4:
|
||||
case 5:
|
||||
return 1; /* SocType_Mariko */
|
||||
default:
|
||||
return 0xF; /* SocType_Undefined */
|
||||
}
|
||||
}
|
||||
|
||||
/* Get the Regulator type. */
|
||||
uint32_t fuse_get_regulator(void) {
|
||||
if (fuse_get_soc_type() == 1) {
|
||||
return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */
|
||||
} else {
|
||||
return 0; /* Regulator_Erista_Max77621 */
|
||||
}
|
||||
}
|
||||
@@ -1,484 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_FUSE_H
|
||||
#define FUSEE_FUSE_H
|
||||
|
||||
#define FUSE_BASE 0x7000F800
|
||||
#define FUSE_CHIP_BASE (FUSE_BASE + 0x98)
|
||||
#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
|
||||
#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
|
||||
|
||||
typedef struct {
|
||||
uint32_t FUSE_FUSECTRL;
|
||||
uint32_t FUSE_FUSEADDR;
|
||||
uint32_t FUSE_FUSERDATA;
|
||||
uint32_t FUSE_FUSEWDATA;
|
||||
uint32_t FUSE_FUSETIME_RD1;
|
||||
uint32_t FUSE_FUSETIME_RD2;
|
||||
uint32_t FUSE_FUSETIME_PGM1;
|
||||
uint32_t FUSE_FUSETIME_PGM2;
|
||||
uint32_t FUSE_PRIV2INTFC_START;
|
||||
uint32_t FUSE_FUSEBYPASS;
|
||||
uint32_t FUSE_PRIVATEKEYDISABLE;
|
||||
uint32_t FUSE_DISABLEREGPROGRAM;
|
||||
uint32_t FUSE_WRITE_ACCESS_SW;
|
||||
uint32_t FUSE_PWR_GOOD_SW;
|
||||
uint32_t _0x38;
|
||||
uint32_t FUSE_PRIV2RESHIFT;
|
||||
uint32_t _0x40[0x3];
|
||||
uint32_t FUSE_FUSETIME_RD3;
|
||||
uint32_t _0x50[0xC];
|
||||
uint32_t FUSE_PRIVATE_KEY0_NONZERO;
|
||||
uint32_t FUSE_PRIVATE_KEY1_NONZERO;
|
||||
uint32_t FUSE_PRIVATE_KEY2_NONZERO;
|
||||
uint32_t FUSE_PRIVATE_KEY3_NONZERO;
|
||||
uint32_t FUSE_PRIVATE_KEY4_NONZERO;
|
||||
uint32_t _0x94;
|
||||
} tegra_fuse_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t _0x98[0x1A];
|
||||
uint32_t FUSE_PRODUCTION_MODE;
|
||||
uint32_t FUSE_JTAG_SECUREID_VALID;
|
||||
uint32_t FUSE_ODM_LOCK;
|
||||
uint32_t FUSE_OPT_OPENGL_EN;
|
||||
uint32_t FUSE_SKU_INFO;
|
||||
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
|
||||
uint32_t FUSE_CPU_IDDQ_CALIB;
|
||||
uint32_t _0x11C[0x3];
|
||||
uint32_t FUSE_OPT_FT_REV;
|
||||
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
|
||||
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
|
||||
uint32_t FUSE_SOC_IDDQ_CALIB;
|
||||
uint32_t _0x144;
|
||||
uint32_t FUSE_FA;
|
||||
uint32_t FUSE_RESERVED_PRODUCTION;
|
||||
uint32_t FUSE_HDMI_LANE0_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE1_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE2_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE3_CALIB;
|
||||
uint32_t FUSE_ENCRYPTION_RATE;
|
||||
uint32_t FUSE_PUBLIC_KEY[0x8];
|
||||
uint32_t FUSE_TSENSOR1_CALIB;
|
||||
uint32_t FUSE_TSENSOR2_CALIB;
|
||||
uint32_t _0x18C;
|
||||
uint32_t FUSE_OPT_CP_REV;
|
||||
uint32_t FUSE_OPT_PFG;
|
||||
uint32_t FUSE_TSENSOR0_CALIB;
|
||||
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
|
||||
uint32_t FUSE_SECURITY_MODE;
|
||||
uint32_t FUSE_PRIVATE_KEY[0x5];
|
||||
uint32_t FUSE_ARM_JTAG_DIS;
|
||||
uint32_t FUSE_BOOT_DEVICE_INFO;
|
||||
uint32_t FUSE_RESERVED_SW;
|
||||
uint32_t FUSE_OPT_VP9_DISABLE;
|
||||
uint32_t FUSE_RESERVED_ODM0[0x8];
|
||||
uint32_t FUSE_OBS_DIS;
|
||||
uint32_t _0x1EC;
|
||||
uint32_t FUSE_USB_CALIB;
|
||||
uint32_t FUSE_SKU_DIRECT_CONFIG;
|
||||
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
|
||||
uint32_t FUSE_PACKAGE_INFO;
|
||||
uint32_t FUSE_OPT_VENDOR_CODE;
|
||||
uint32_t FUSE_OPT_FAB_CODE;
|
||||
uint32_t FUSE_OPT_LOT_CODE_0;
|
||||
uint32_t FUSE_OPT_LOT_CODE_1;
|
||||
uint32_t FUSE_OPT_WAFER_ID;
|
||||
uint32_t FUSE_OPT_X_COORDINATE;
|
||||
uint32_t FUSE_OPT_Y_COORDINATE;
|
||||
uint32_t FUSE_OPT_SEC_DEBUG_EN;
|
||||
uint32_t FUSE_OPT_OPS_RESERVED;
|
||||
uint32_t _0x224;
|
||||
uint32_t FUSE_GPU_IDDQ_CALIB;
|
||||
uint32_t FUSE_TSENSOR3_CALIB;
|
||||
uint32_t FUSE_CLOCK_BOUNDOUT0;
|
||||
uint32_t FUSE_CLOCK_BOUNDOUT1;
|
||||
uint32_t _0x238[0x3];
|
||||
uint32_t FUSE_OPT_SAMPLE_TYPE;
|
||||
uint32_t FUSE_OPT_SUBREVISION;
|
||||
uint32_t FUSE_OPT_SW_RESERVED_0;
|
||||
uint32_t FUSE_OPT_SW_RESERVED_1;
|
||||
uint32_t FUSE_TSENSOR4_CALIB;
|
||||
uint32_t FUSE_TSENSOR5_CALIB;
|
||||
uint32_t FUSE_TSENSOR6_CALIB;
|
||||
uint32_t FUSE_TSENSOR7_CALIB;
|
||||
uint32_t FUSE_OPT_PRIV_SEC_EN;
|
||||
uint32_t _0x268[0x5];
|
||||
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
|
||||
uint32_t FUSE_TSENSOR_COMMON;
|
||||
uint32_t FUSE_OPT_CP_BIN;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE;
|
||||
uint32_t FUSE_OPT_FT_BIN;
|
||||
uint32_t FUSE_OPT_DONE_MAP;
|
||||
uint32_t _0x294;
|
||||
uint32_t FUSE_APB2JTAG_DISABLE;
|
||||
uint32_t FUSE_ODM_INFO;
|
||||
uint32_t _0x2A0[0x2];
|
||||
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
|
||||
uint32_t _0x2AC[0x5];
|
||||
uint32_t FUSE_WOA_SKU_FLAG;
|
||||
uint32_t FUSE_ECO_RESERVE_1;
|
||||
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
|
||||
uint32_t FUSE_PRODUCTION_MONTH;
|
||||
uint32_t FUSE_RAM_REPAIR_INDICATOR;
|
||||
uint32_t FUSE_TSENSOR9_CALIB;
|
||||
uint32_t _0x2D8;
|
||||
uint32_t FUSE_VMIN_CALIBRATION;
|
||||
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
|
||||
uint32_t FUSE_DEBUG_AUTHENTICATION;
|
||||
uint32_t FUSE_SECURE_PROVISION_INDEX;
|
||||
uint32_t FUSE_SECURE_PROVISION_INFO;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
|
||||
uint32_t FUSE_SPARE_ENDIS;
|
||||
uint32_t FUSE_ECO_RESERVE_0;
|
||||
uint32_t _0x2FC[0x2];
|
||||
uint32_t FUSE_RESERVED_CALIB0;
|
||||
uint32_t FUSE_RESERVED_CALIB1;
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
|
||||
uint32_t FUSE_TSENSOR10_CALIB;
|
||||
uint32_t FUSE_TSENSOR10_CALIB_AUX;
|
||||
uint32_t _0x324[0x5];
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
|
||||
uint32_t FUSE_USB_CALIB_EXT;
|
||||
uint32_t FUSE_RESERVED_FIELD;
|
||||
uint32_t _0x358[0x9];
|
||||
uint32_t FUSE_SPARE_REALIGNMENT_REG;
|
||||
uint32_t FUSE_SPARE_BIT[0x20];
|
||||
} tegra_fuse_chip_common_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t _0x98[0x1A];
|
||||
uint32_t FUSE_PRODUCTION_MODE;
|
||||
uint32_t FUSE_JTAG_SECUREID_VALID;
|
||||
uint32_t FUSE_ODM_LOCK;
|
||||
uint32_t FUSE_OPT_OPENGL_EN;
|
||||
uint32_t FUSE_SKU_INFO;
|
||||
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
|
||||
uint32_t FUSE_CPU_IDDQ_CALIB;
|
||||
uint32_t _0x11C[0x3];
|
||||
uint32_t FUSE_OPT_FT_REV;
|
||||
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
|
||||
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
|
||||
uint32_t FUSE_SOC_IDDQ_CALIB;
|
||||
uint32_t _0x144;
|
||||
uint32_t FUSE_FA;
|
||||
uint32_t FUSE_RESERVED_PRODUCTION;
|
||||
uint32_t FUSE_HDMI_LANE0_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE1_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE2_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE3_CALIB;
|
||||
uint32_t FUSE_ENCRYPTION_RATE;
|
||||
uint32_t FUSE_PUBLIC_KEY[0x8];
|
||||
uint32_t FUSE_TSENSOR1_CALIB;
|
||||
uint32_t FUSE_TSENSOR2_CALIB;
|
||||
uint32_t _0x18C;
|
||||
uint32_t FUSE_OPT_CP_REV;
|
||||
uint32_t FUSE_OPT_PFG;
|
||||
uint32_t FUSE_TSENSOR0_CALIB;
|
||||
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
|
||||
uint32_t FUSE_SECURITY_MODE;
|
||||
uint32_t FUSE_PRIVATE_KEY[0x5];
|
||||
uint32_t FUSE_ARM_JTAG_DIS;
|
||||
uint32_t FUSE_BOOT_DEVICE_INFO;
|
||||
uint32_t FUSE_RESERVED_SW;
|
||||
uint32_t FUSE_OPT_VP9_DISABLE;
|
||||
uint32_t FUSE_RESERVED_ODM0[0x8];
|
||||
uint32_t FUSE_OBS_DIS;
|
||||
uint32_t _0x1EC;
|
||||
uint32_t FUSE_USB_CALIB;
|
||||
uint32_t FUSE_SKU_DIRECT_CONFIG;
|
||||
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
|
||||
uint32_t FUSE_PACKAGE_INFO;
|
||||
uint32_t FUSE_OPT_VENDOR_CODE;
|
||||
uint32_t FUSE_OPT_FAB_CODE;
|
||||
uint32_t FUSE_OPT_LOT_CODE_0;
|
||||
uint32_t FUSE_OPT_LOT_CODE_1;
|
||||
uint32_t FUSE_OPT_WAFER_ID;
|
||||
uint32_t FUSE_OPT_X_COORDINATE;
|
||||
uint32_t FUSE_OPT_Y_COORDINATE;
|
||||
uint32_t FUSE_OPT_SEC_DEBUG_EN;
|
||||
uint32_t FUSE_OPT_OPS_RESERVED;
|
||||
uint32_t FUSE_SATA_CALIB; /* Erista only. */
|
||||
uint32_t FUSE_GPU_IDDQ_CALIB;
|
||||
uint32_t FUSE_TSENSOR3_CALIB;
|
||||
uint32_t FUSE_CLOCK_BOUNDOUT0;
|
||||
uint32_t FUSE_CLOCK_BOUNDOUT1;
|
||||
uint32_t _0x238[0x3];
|
||||
uint32_t FUSE_OPT_SAMPLE_TYPE;
|
||||
uint32_t FUSE_OPT_SUBREVISION;
|
||||
uint32_t FUSE_OPT_SW_RESERVED_0;
|
||||
uint32_t FUSE_OPT_SW_RESERVED_1;
|
||||
uint32_t FUSE_TSENSOR4_CALIB;
|
||||
uint32_t FUSE_TSENSOR5_CALIB;
|
||||
uint32_t FUSE_TSENSOR6_CALIB;
|
||||
uint32_t FUSE_TSENSOR7_CALIB;
|
||||
uint32_t FUSE_OPT_PRIV_SEC_EN;
|
||||
uint32_t FUSE_PKC_DISABLE; /* Erista only. */
|
||||
uint32_t _0x26C[0x4];
|
||||
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
|
||||
uint32_t FUSE_TSENSOR_COMMON;
|
||||
uint32_t FUSE_OPT_CP_BIN;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE;
|
||||
uint32_t FUSE_OPT_FT_BIN;
|
||||
uint32_t FUSE_OPT_DONE_MAP;
|
||||
uint32_t _0x294;
|
||||
uint32_t FUSE_APB2JTAG_DISABLE;
|
||||
uint32_t FUSE_ODM_INFO;
|
||||
uint32_t _0x2A0[0x2];
|
||||
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
|
||||
uint32_t _0x2AC[0x5];
|
||||
uint32_t FUSE_WOA_SKU_FLAG;
|
||||
uint32_t FUSE_ECO_RESERVE_1;
|
||||
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
|
||||
uint32_t FUSE_PRODUCTION_MONTH;
|
||||
uint32_t FUSE_RAM_REPAIR_INDICATOR;
|
||||
uint32_t FUSE_TSENSOR9_CALIB;
|
||||
uint32_t _0x2D8;
|
||||
uint32_t FUSE_VMIN_CALIBRATION;
|
||||
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
|
||||
uint32_t FUSE_DEBUG_AUTHENTICATION;
|
||||
uint32_t FUSE_SECURE_PROVISION_INDEX;
|
||||
uint32_t FUSE_SECURE_PROVISION_INFO;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
|
||||
uint32_t FUSE_SPARE_ENDIS;
|
||||
uint32_t FUSE_ECO_RESERVE_0;
|
||||
uint32_t _0x2FC[0x2];
|
||||
uint32_t FUSE_RESERVED_CALIB0;
|
||||
uint32_t FUSE_RESERVED_CALIB1;
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
|
||||
uint32_t FUSE_TSENSOR10_CALIB;
|
||||
uint32_t FUSE_TSENSOR10_CALIB_AUX;
|
||||
uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */
|
||||
uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */
|
||||
uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */
|
||||
uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */
|
||||
uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
|
||||
uint32_t FUSE_USB_CALIB_EXT;
|
||||
uint32_t FUSE_RESERVED_FIELD;
|
||||
uint32_t _0x358[0x9];
|
||||
uint32_t FUSE_SPARE_REALIGNMENT_REG;
|
||||
uint32_t FUSE_SPARE_BIT[0x20];
|
||||
} tegra_fuse_chip_erista_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */
|
||||
uint32_t FUSE_KEK[0x4]; /* Mariko only. */
|
||||
uint32_t FUSE_BEK[0x4]; /* Mariko only. */
|
||||
uint32_t _0xF0; /* Mariko only. */
|
||||
uint32_t _0xF4; /* Mariko only. */
|
||||
uint32_t _0xF8; /* Mariko only. */
|
||||
uint32_t _0xFC; /* Mariko only. */
|
||||
uint32_t FUSE_PRODUCTION_MODE;
|
||||
uint32_t FUSE_JTAG_SECUREID_VALID;
|
||||
uint32_t FUSE_ODM_LOCK;
|
||||
uint32_t FUSE_OPT_OPENGL_EN;
|
||||
uint32_t FUSE_SKU_INFO;
|
||||
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
|
||||
uint32_t FUSE_CPU_IDDQ_CALIB;
|
||||
uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */
|
||||
uint32_t FUSE_OPT_FT_REV;
|
||||
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
|
||||
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
|
||||
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
|
||||
uint32_t FUSE_SOC_IDDQ_CALIB;
|
||||
uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */
|
||||
uint32_t FUSE_FA;
|
||||
uint32_t FUSE_RESERVED_PRODUCTION;
|
||||
uint32_t FUSE_HDMI_LANE0_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE1_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE2_CALIB;
|
||||
uint32_t FUSE_HDMI_LANE3_CALIB;
|
||||
uint32_t FUSE_ENCRYPTION_RATE;
|
||||
uint32_t FUSE_PUBLIC_KEY[0x8];
|
||||
uint32_t FUSE_TSENSOR1_CALIB;
|
||||
uint32_t FUSE_TSENSOR2_CALIB;
|
||||
uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */
|
||||
uint32_t FUSE_OPT_CP_REV;
|
||||
uint32_t FUSE_OPT_PFG;
|
||||
uint32_t FUSE_TSENSOR0_CALIB;
|
||||
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
|
||||
uint32_t FUSE_SECURITY_MODE;
|
||||
uint32_t FUSE_PRIVATE_KEY[0x5];
|
||||
uint32_t FUSE_ARM_JTAG_DIS;
|
||||
uint32_t FUSE_BOOT_DEVICE_INFO;
|
||||
uint32_t FUSE_RESERVED_SW;
|
||||
uint32_t FUSE_OPT_VP9_DISABLE;
|
||||
uint32_t FUSE_RESERVED_ODM0[0x8];
|
||||
uint32_t FUSE_OBS_DIS;
|
||||
uint32_t _0x1EC; /* Mariko only. */
|
||||
uint32_t FUSE_USB_CALIB;
|
||||
uint32_t FUSE_SKU_DIRECT_CONFIG;
|
||||
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
|
||||
uint32_t FUSE_PACKAGE_INFO;
|
||||
uint32_t FUSE_OPT_VENDOR_CODE;
|
||||
uint32_t FUSE_OPT_FAB_CODE;
|
||||
uint32_t FUSE_OPT_LOT_CODE_0;
|
||||
uint32_t FUSE_OPT_LOT_CODE_1;
|
||||
uint32_t FUSE_OPT_WAFER_ID;
|
||||
uint32_t FUSE_OPT_X_COORDINATE;
|
||||
uint32_t FUSE_OPT_Y_COORDINATE;
|
||||
uint32_t FUSE_OPT_SEC_DEBUG_EN;
|
||||
uint32_t FUSE_OPT_OPS_RESERVED;
|
||||
uint32_t _0x224; /* Mariko only. */
|
||||
uint32_t FUSE_GPU_IDDQ_CALIB;
|
||||
uint32_t FUSE_TSENSOR3_CALIB;
|
||||
uint32_t FUSE_CLOCK_BOUNDOUT0;
|
||||
uint32_t FUSE_CLOCK_BOUNDOUT1;
|
||||
uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */
|
||||
uint32_t FUSE_OPT_SAMPLE_TYPE;
|
||||
uint32_t FUSE_OPT_SUBREVISION;
|
||||
uint32_t FUSE_OPT_SW_RESERVED_0;
|
||||
uint32_t FUSE_OPT_SW_RESERVED_1;
|
||||
uint32_t FUSE_TSENSOR4_CALIB;
|
||||
uint32_t FUSE_TSENSOR5_CALIB;
|
||||
uint32_t FUSE_TSENSOR6_CALIB;
|
||||
uint32_t FUSE_TSENSOR7_CALIB;
|
||||
uint32_t FUSE_OPT_PRIV_SEC_EN;
|
||||
uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */
|
||||
uint32_t _0x26C; /* Mariko only. */
|
||||
uint32_t _0x270; /* Mariko only. */
|
||||
uint32_t _0x274; /* Mariko only. */
|
||||
uint32_t _0x278; /* Mariko only. */
|
||||
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
|
||||
uint32_t FUSE_TSENSOR_COMMON;
|
||||
uint32_t FUSE_OPT_CP_BIN;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE;
|
||||
uint32_t FUSE_OPT_FT_BIN;
|
||||
uint32_t FUSE_OPT_DONE_MAP;
|
||||
uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */
|
||||
uint32_t FUSE_APB2JTAG_DISABLE;
|
||||
uint32_t FUSE_ODM_INFO;
|
||||
uint32_t _0x2A0[0x2];
|
||||
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
|
||||
uint32_t _0x2AC;
|
||||
uint32_t _0x2B0; /* Mariko only. */
|
||||
uint32_t _0x2B4; /* Mariko only. */
|
||||
uint32_t _0x2B8; /* Mariko only. */
|
||||
uint32_t _0x2BC; /* Mariko only. */
|
||||
uint32_t FUSE_WOA_SKU_FLAG;
|
||||
uint32_t FUSE_ECO_RESERVE_1;
|
||||
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
|
||||
uint32_t FUSE_PRODUCTION_MONTH;
|
||||
uint32_t FUSE_RAM_REPAIR_INDICATOR;
|
||||
uint32_t FUSE_TSENSOR9_CALIB;
|
||||
uint32_t _0x2D8;
|
||||
uint32_t FUSE_VMIN_CALIBRATION;
|
||||
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
|
||||
uint32_t FUSE_DEBUG_AUTHENTICATION;
|
||||
uint32_t FUSE_SECURE_PROVISION_INDEX;
|
||||
uint32_t FUSE_SECURE_PROVISION_INFO;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
|
||||
uint32_t FUSE_SPARE_ENDIS;
|
||||
uint32_t FUSE_ECO_RESERVE_0;
|
||||
uint32_t _0x2FC[0x2];
|
||||
uint32_t FUSE_RESERVED_CALIB0;
|
||||
uint32_t FUSE_RESERVED_CALIB1;
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
|
||||
uint32_t FUSE_TSENSOR10_CALIB;
|
||||
uint32_t FUSE_TSENSOR10_CALIB_AUX;
|
||||
uint32_t _0x324; /* Mariko only. */
|
||||
uint32_t _0x328; /* Mariko only. */
|
||||
uint32_t _0x32C; /* Mariko only. */
|
||||
uint32_t _0x330; /* Mariko only. */
|
||||
uint32_t _0x334; /* Mariko only. */
|
||||
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
|
||||
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
|
||||
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
|
||||
uint32_t FUSE_USB_CALIB_EXT;
|
||||
uint32_t FUSE_RESERVED_FIELD;
|
||||
uint32_t _0x358[0x9];
|
||||
uint32_t FUSE_SPARE_REALIGNMENT_REG;
|
||||
uint32_t FUSE_SPARE_BIT[0x1E];
|
||||
} tegra_fuse_chip_mariko_t;
|
||||
|
||||
static inline volatile tegra_fuse_t *fuse_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_fuse_t *)FUSE_BASE;
|
||||
}
|
||||
|
||||
static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE;
|
||||
}
|
||||
|
||||
static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE;
|
||||
}
|
||||
|
||||
static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE;
|
||||
}
|
||||
|
||||
void fuse_init(void);
|
||||
void fuse_disable_programming(void);
|
||||
void fuse_disable_private_key(void);
|
||||
void fuse_enable_power(void);
|
||||
void fuse_disable_power(void);
|
||||
|
||||
uint32_t fuse_get_sku_info(void);
|
||||
uint32_t fuse_get_spare_bit(uint32_t index);
|
||||
uint32_t fuse_get_reserved_odm(uint32_t index);
|
||||
uint32_t fuse_get_bootrom_patch_version(void);
|
||||
uint64_t fuse_get_device_id(void);
|
||||
uint32_t fuse_get_dram_id(void);
|
||||
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
|
||||
uint32_t fuse_get_hardware_type(void);
|
||||
uint32_t fuse_get_retail_type(void);
|
||||
void fuse_get_hardware_info(void *dst);
|
||||
bool fuse_is_new_format(void);
|
||||
uint32_t fuse_get_device_unique_key_generation(void);
|
||||
uint32_t fuse_get_soc_type(void);
|
||||
uint32_t fuse_get_regulator(void);
|
||||
|
||||
uint32_t fuse_hw_read(uint32_t addr);
|
||||
void fuse_hw_write(uint32_t value, uint32_t addr);
|
||||
void fuse_hw_sense(void);
|
||||
|
||||
#endif
|
||||
@@ -1,86 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
#include <malloc.h>
|
||||
#include <sys/iosupport.h>
|
||||
#include "stage2.h"
|
||||
#include "utils.h"
|
||||
|
||||
void __libc_init_array(void);
|
||||
void __libc_fini_array(void);
|
||||
|
||||
extern uint8_t __bss_start__[], __bss_end__[];
|
||||
extern uint8_t __heap_start__[], __heap_end__[];
|
||||
|
||||
extern char *fake_heap_start;
|
||||
extern char *fake_heap_end;
|
||||
|
||||
int __program_argc;
|
||||
void **__program_argv;
|
||||
|
||||
void __program_exit(int rc);
|
||||
static void __program_parse_argc_argv(int argc, char *argdata);
|
||||
static void __program_cleanup_argv(void);
|
||||
|
||||
static void __program_init_heap(void) {
|
||||
fake_heap_start = (char*)__heap_start__;
|
||||
fake_heap_end = (char*)__heap_end__;
|
||||
}
|
||||
|
||||
static void __program_init_newlib_hooks(void) {
|
||||
__syscalls.exit = __program_exit; /* For exit, etc. */
|
||||
}
|
||||
|
||||
void __program_init(int argc, char *argdata) {
|
||||
/* Zero-fill the .bss section */
|
||||
memset(__bss_start__, 0, __bss_end__ - __bss_start__);
|
||||
|
||||
__program_init_heap();
|
||||
__program_init_newlib_hooks();
|
||||
__program_parse_argc_argv(argc, argdata);
|
||||
__libc_init_array();
|
||||
}
|
||||
|
||||
void __program_exit(int rc) {
|
||||
__libc_fini_array();
|
||||
__program_cleanup_argv();
|
||||
}
|
||||
|
||||
static void __program_parse_argc_argv(int argc, char *argdata) {
|
||||
__program_argc = argc;
|
||||
|
||||
__program_argv = malloc(argc * sizeof(void **));
|
||||
if (__program_argv == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
__program_argv[0] = malloc(sizeof(stage2_mtc_args_t));
|
||||
if (__program_argv[0] == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
memcpy(__program_argv[0], argdata, sizeof(stage2_mtc_args_t));
|
||||
}
|
||||
|
||||
static void __program_cleanup_argv(void) {
|
||||
for (int i = 0; i < __program_argc; i++) {
|
||||
free(__program_argv[i]);
|
||||
__program_argv[i] = NULL;
|
||||
}
|
||||
free(__program_argv);
|
||||
}
|
||||
@@ -1,57 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include "mtc.h"
|
||||
#include "stage2.h"
|
||||
#include "../../../fusee/common/display/video_fb.h"
|
||||
|
||||
static void *g_framebuffer;
|
||||
static __attribute__((__aligned__(0x200))) stage2_mtc_args_t g_mtc_args_store;
|
||||
static stage2_mtc_args_t *g_mtc_args;
|
||||
|
||||
/* Allow for main(int argc, void **argv) signature. */
|
||||
#pragma GCC diagnostic ignored "-Wmain"
|
||||
|
||||
int main(int argc, void **argv) {
|
||||
ScreenLogLevel log_level = SCREEN_LOG_LEVEL_NONE;
|
||||
|
||||
/* Check argc. */
|
||||
if (argc != MTC_ARGC) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Extract arguments from argv. */
|
||||
g_mtc_args = &g_mtc_args_store;
|
||||
memcpy(g_mtc_args, (stage2_mtc_args_t *)argv[MTC_ARGV_ARGUMENT_STRUCT], sizeof(*g_mtc_args));
|
||||
log_level = g_mtc_args->log_level;
|
||||
|
||||
/* Override the global logging level. */
|
||||
log_set_log_level(log_level);
|
||||
|
||||
if (log_level != SCREEN_LOG_LEVEL_NONE) {
|
||||
/* Set framebuffer address. */
|
||||
g_framebuffer = (void *)0xC0000000;
|
||||
|
||||
/* Zero-fill the framebuffer and register it as printk provider. */
|
||||
video_init(g_framebuffer);
|
||||
}
|
||||
|
||||
/* Train DRAM. */
|
||||
train_dram();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,167 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "mc.h"
|
||||
#include "car.h"
|
||||
#include "timers.h"
|
||||
|
||||
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock)
|
||||
{
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom;
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
|
||||
|
||||
if (lock)
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1;
|
||||
}
|
||||
|
||||
void mc_config_carveout()
|
||||
{
|
||||
*(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
|
||||
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
|
||||
|
||||
mc_config_tsec_carveout(0, 0, true);
|
||||
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
|
||||
}
|
||||
|
||||
void mc_config_carveout_finalize()
|
||||
{
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
|
||||
}
|
||||
|
||||
void mc_enable_ahb_redirect()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000);
|
||||
|
||||
MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000;
|
||||
MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000;
|
||||
}
|
||||
|
||||
void mc_disable_ahb_redirect()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
|
||||
MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000;
|
||||
MAKE_MC_REG(MC_IRAM_TOM) = 0;
|
||||
|
||||
car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF;
|
||||
}
|
||||
|
||||
void mc_enable()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
|
||||
/* Set EMC clock source. */
|
||||
car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000);
|
||||
|
||||
/* Enable MIPI CAL clock. */
|
||||
car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000);
|
||||
|
||||
/* Enable MC clock. */
|
||||
car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1);
|
||||
|
||||
/* Enable EMC DLL clock. */
|
||||
car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000);
|
||||
|
||||
/* Clear EMC and MC reset. */
|
||||
car->rst_dev_h_set = 0x2000001;
|
||||
udelay(5);
|
||||
|
||||
mc_disable_ahb_redirect();
|
||||
}
|
||||
@@ -1,606 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_MC_H_
|
||||
#define FUSEE_MC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define MC_BASE 0x70019000
|
||||
#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
|
||||
|
||||
#define MC_INTSTATUS 0x0
|
||||
#define MC_INTMASK 0x4
|
||||
#define MC_ERR_STATUS 0x8
|
||||
#define MC_ERR_ADR 0xc
|
||||
#define MC_SMMU_CONFIG 0x10
|
||||
#define MC_SMMU_TLB_CONFIG 0x14
|
||||
#define MC_SMMU_PTC_CONFIG 0x18
|
||||
#define MC_SMMU_PTB_ASID 0x1c
|
||||
#define MC_SMMU_PTB_DATA 0x20
|
||||
#define MC_SMMU_TLB_FLUSH 0x30
|
||||
#define MC_SMMU_PTC_FLUSH 0x34
|
||||
#define MC_SMMU_ASID_SECURITY 0x38
|
||||
#define MC_SMMU_ASID_SECURITY_1 0x3c
|
||||
#define MC_SMMU_ASID_SECURITY_2 0x9e0
|
||||
#define MC_SMMU_ASID_SECURITY_3 0x9e4
|
||||
#define MC_SMMU_ASID_SECURITY_4 0x9e8
|
||||
#define MC_SMMU_ASID_SECURITY_5 0x9ec
|
||||
#define MC_SMMU_ASID_SECURITY_6 0x9f0
|
||||
#define MC_SMMU_ASID_SECURITY_7 0x9f4
|
||||
#define MC_SMMU_AFI_ASID 0x238
|
||||
#define MC_SMMU_AVPC_ASID 0x23c
|
||||
#define MC_SMMU_TSEC_ASID 0x294
|
||||
#define MC_SMMU_PPCS1_ASID 0x298
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
|
||||
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
|
||||
#define MC_EMEM_CFG 0x50
|
||||
#define MC_EMEM_ADR_CFG 0x54
|
||||
#define MC_EMEM_ADR_CFG_DEV0 0x58
|
||||
#define MC_EMEM_ADR_CFG_DEV1 0x5c
|
||||
#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c
|
||||
#define MC_SECURITY_CFG0 0x70
|
||||
#define MC_SECURITY_CFG1 0x74
|
||||
#define MC_SECURITY_CFG3 0x9bc
|
||||
#define MC_SECURITY_RSV 0x7c
|
||||
#define MC_EMEM_ARB_CFG 0x90
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
|
||||
#define MC_EMEM_ARB_TIMING_RCD 0x98
|
||||
#define MC_EMEM_ARB_TIMING_RP 0x9c
|
||||
#define MC_EMEM_ARB_TIMING_RC 0xa0
|
||||
#define MC_EMEM_ARB_TIMING_RAS 0xa4
|
||||
#define MC_EMEM_ARB_TIMING_FAW 0xa8
|
||||
#define MC_EMEM_ARB_TIMING_RRD 0xac
|
||||
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
|
||||
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
|
||||
#define MC_EMEM_ARB_TIMING_R2R 0xb8
|
||||
#define MC_EMEM_ARB_TIMING_W2W 0xbc
|
||||
#define MC_EMEM_ARB_TIMING_R2W 0xc0
|
||||
#define MC_EMEM_ARB_TIMING_W2R 0xc4
|
||||
#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0
|
||||
#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4
|
||||
#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0
|
||||
#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4
|
||||
#define MC_EMEM_ARB_DA_TURNS 0xd0
|
||||
#define MC_EMEM_ARB_DA_COVERS 0xd4
|
||||
#define MC_EMEM_ARB_MISC0 0xd8
|
||||
#define MC_EMEM_ARB_MISC1 0xdc
|
||||
#define MC_EMEM_ARB_MISC2 0xc8
|
||||
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
|
||||
#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
|
||||
#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0
|
||||
#define MC_EMEM_ARB_OVERRIDE 0xe8
|
||||
#define MC_EMEM_ARB_RSV 0xec
|
||||
#define MC_CLKEN_OVERRIDE 0xf4
|
||||
#define MC_TIMING_CONTROL_DBG 0xf8
|
||||
#define MC_TIMING_CONTROL 0xfc
|
||||
#define MC_STAT_CONTROL 0x100
|
||||
#define MC_STAT_STATUS 0x104
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT 0x108
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c
|
||||
#define MC_STAT_EMC_CLOCKS 0x110
|
||||
#define MC_STAT_EMC_CLOCKS_MSBS 0x114
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24
|
||||
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198
|
||||
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8
|
||||
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c
|
||||
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac
|
||||
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28
|
||||
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c
|
||||
#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0
|
||||
#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0
|
||||
#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120
|
||||
#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c
|
||||
#define MC_STAT_EMC_SET0_COUNT 0x138
|
||||
#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c
|
||||
#define MC_STAT_EMC_SET1_COUNT 0x178
|
||||
#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c
|
||||
#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140
|
||||
#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144
|
||||
#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180
|
||||
#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184
|
||||
#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148
|
||||
#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c
|
||||
#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188
|
||||
#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c
|
||||
#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150
|
||||
#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190
|
||||
#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8
|
||||
#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc
|
||||
#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8
|
||||
#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc
|
||||
#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0
|
||||
#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0
|
||||
#define MC_CLIENT_HOTRESET_CTRL 0x200
|
||||
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
|
||||
#define MC_CLIENT_HOTRESET_STATUS 0x204
|
||||
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94
|
||||
#define MC_EMEM_ARB_HYSTERESIS_0 0x218
|
||||
#define MC_EMEM_ARB_HYSTERESIS_1 0x21c
|
||||
#define MC_EMEM_ARB_HYSTERESIS_2 0x220
|
||||
#define MC_EMEM_ARB_HYSTERESIS_3 0x224
|
||||
#define MC_EMEM_ARB_HYSTERESIS_4 0xb84
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0
|
||||
#define MC_EMEM_ARB_DHYST_CTRL 0xbcc
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec
|
||||
#define MC_RESERVED_RSV 0x3fc
|
||||
#define MC_DISB_EXTRA_SNAP_LEVELS 0x408
|
||||
#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4
|
||||
#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0
|
||||
#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18
|
||||
#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08
|
||||
#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10
|
||||
#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c
|
||||
#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40
|
||||
#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414
|
||||
#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc
|
||||
#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c
|
||||
#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14
|
||||
#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0
|
||||
#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac
|
||||
#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c
|
||||
#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48
|
||||
#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8
|
||||
#define MC_USBX_EXTRA_SNAP_LEVELS 0x404
|
||||
#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8
|
||||
#define MC_SD_EXTRA_SNAP_LEVELS 0xa04
|
||||
#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c
|
||||
#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8
|
||||
#define MC_GK_EXTRA_SNAP_LEVELS 0xa00
|
||||
#define MC_VE2_EXTRA_SNAP_LEVELS 0x410
|
||||
#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44
|
||||
#define MC_VIDEO_PROTECT_BOM 0x648
|
||||
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
|
||||
#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978
|
||||
#define MC_VIDEO_PROTECT_REG_CTRL 0x650
|
||||
#define MC_ERR_VPR_STATUS 0x654
|
||||
#define MC_ERR_VPR_ADR 0x658
|
||||
#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
|
||||
#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590
|
||||
#define MC_IRAM_BOM 0x65c
|
||||
#define MC_IRAM_TOM 0x660
|
||||
#define MC_IRAM_ADR_HI 0x980
|
||||
#define MC_IRAM_REG_CTRL 0x964
|
||||
#define MC_EMEM_CFG_ACCESS_CTRL 0x664
|
||||
#define MC_TZ_SECURITY_CTRL 0x668
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4
|
||||
#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc
|
||||
#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8
|
||||
#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80
|
||||
#define MC_SEC_CARVEOUT_BOM 0x670
|
||||
#define MC_SEC_CARVEOUT_SIZE_MB 0x674
|
||||
#define MC_SEC_CARVEOUT_ADR_HI 0x9d4
|
||||
#define MC_SEC_CARVEOUT_REG_CTRL 0x678
|
||||
#define MC_ERR_SEC_STATUS 0x67c
|
||||
#define MC_ERR_SEC_ADR 0x680
|
||||
#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684
|
||||
#define MC_STUTTER_CONTROL 0x688
|
||||
#define MC_RESERVED_RSV_1 0x958
|
||||
#define MC_DVFS_PIPE_SELECT 0x95c
|
||||
#define MC_AHB_PTSA_MIN 0x4e0
|
||||
#define MC_AUD_PTSA_MIN 0x54c
|
||||
#define MC_MLL_MPCORER_PTSA_RATE 0x44c
|
||||
#define MC_RING2_PTSA_RATE 0x440
|
||||
#define MC_USBD_PTSA_RATE 0x530
|
||||
#define MC_USBX_PTSA_MIN 0x528
|
||||
#define MC_USBD_PTSA_MIN 0x534
|
||||
#define MC_APB_PTSA_MAX 0x4f0
|
||||
#define MC_JPG_PTSA_RATE 0x584
|
||||
#define MC_DIS_PTSA_MIN 0x420
|
||||
#define MC_AVP_PTSA_MAX 0x4fc
|
||||
#define MC_AVP_PTSA_RATE 0x4f4
|
||||
#define MC_RING1_PTSA_MIN 0x480
|
||||
#define MC_DIS_PTSA_MAX 0x424
|
||||
#define MC_SD_PTSA_MAX 0x4d8
|
||||
#define MC_MSE_PTSA_RATE 0x4c4
|
||||
#define MC_VICPC_PTSA_MIN 0x558
|
||||
#define MC_PCX_PTSA_MAX 0x4b4
|
||||
#define MC_ISP_PTSA_RATE 0x4a0
|
||||
#define MC_A9AVPPC_PTSA_MIN 0x48c
|
||||
#define MC_RING2_PTSA_MAX 0x448
|
||||
#define MC_AUD_PTSA_RATE 0x548
|
||||
#define MC_HOST_PTSA_MIN 0x51c
|
||||
#define MC_MLL_MPCORER_PTSA_MAX 0x454
|
||||
#define MC_SD_PTSA_MIN 0x4d4
|
||||
#define MC_RING1_PTSA_RATE 0x47c
|
||||
#define MC_JPG_PTSA_MIN 0x588
|
||||
#define MC_HDAPC_PTSA_MIN 0x62c
|
||||
#define MC_AVP_PTSA_MIN 0x4f8
|
||||
#define MC_JPG_PTSA_MAX 0x58c
|
||||
#define MC_VE_PTSA_MAX 0x43c
|
||||
#define MC_DFD_PTSA_MAX 0x63c
|
||||
#define MC_VICPC_PTSA_RATE 0x554
|
||||
#define MC_GK_PTSA_MAX 0x544
|
||||
#define MC_VICPC_PTSA_MAX 0x55c
|
||||
#define MC_SDM_PTSA_MAX 0x624
|
||||
#define MC_SAX_PTSA_RATE 0x4b8
|
||||
#define MC_PCX_PTSA_MIN 0x4b0
|
||||
#define MC_APB_PTSA_MIN 0x4ec
|
||||
#define MC_GK2_PTSA_MIN 0x614
|
||||
#define MC_PCX_PTSA_RATE 0x4ac
|
||||
#define MC_RING1_PTSA_MAX 0x484
|
||||
#define MC_HDAPC_PTSA_RATE 0x628
|
||||
#define MC_MLL_MPCORER_PTSA_MIN 0x450
|
||||
#define MC_GK2_PTSA_MAX 0x618
|
||||
#define MC_AUD_PTSA_MAX 0x550
|
||||
#define MC_GK2_PTSA_RATE 0x610
|
||||
#define MC_ISP_PTSA_MAX 0x4a8
|
||||
#define MC_DISB_PTSA_RATE 0x428
|
||||
#define MC_VE2_PTSA_MAX 0x49c
|
||||
#define MC_DFD_PTSA_MIN 0x638
|
||||
#define MC_FTOP_PTSA_RATE 0x50c
|
||||
#define MC_A9AVPPC_PTSA_RATE 0x488
|
||||
#define MC_VE2_PTSA_MIN 0x498
|
||||
#define MC_USBX_PTSA_MAX 0x52c
|
||||
#define MC_DIS_PTSA_RATE 0x41c
|
||||
#define MC_USBD_PTSA_MAX 0x538
|
||||
#define MC_A9AVPPC_PTSA_MAX 0x490
|
||||
#define MC_USBX_PTSA_RATE 0x524
|
||||
#define MC_FTOP_PTSA_MAX 0x514
|
||||
#define MC_HDAPC_PTSA_MAX 0x630
|
||||
#define MC_SD_PTSA_RATE 0x4d0
|
||||
#define MC_DFD_PTSA_RATE 0x634
|
||||
#define MC_FTOP_PTSA_MIN 0x510
|
||||
#define MC_SDM_PTSA_RATE 0x61c
|
||||
#define MC_AHB_PTSA_RATE 0x4dc
|
||||
#define MC_SMMU_SMMU_PTSA_MAX 0x460
|
||||
#define MC_RING2_PTSA_MIN 0x444
|
||||
#define MC_SDM_PTSA_MIN 0x620
|
||||
#define MC_APB_PTSA_RATE 0x4e8
|
||||
#define MC_MSE_PTSA_MIN 0x4c8
|
||||
#define MC_HOST_PTSA_RATE 0x518
|
||||
#define MC_VE_PTSA_RATE 0x434
|
||||
#define MC_AHB_PTSA_MAX 0x4e4
|
||||
#define MC_SAX_PTSA_MIN 0x4bc
|
||||
#define MC_SMMU_SMMU_PTSA_MIN 0x45c
|
||||
#define MC_ISP_PTSA_MIN 0x4a4
|
||||
#define MC_HOST_PTSA_MAX 0x520
|
||||
#define MC_SAX_PTSA_MAX 0x4c0
|
||||
#define MC_VE_PTSA_MIN 0x438
|
||||
#define MC_GK_PTSA_MIN 0x540
|
||||
#define MC_MSE_PTSA_MAX 0x4cc
|
||||
#define MC_DISB_PTSA_MAX 0x430
|
||||
#define MC_DISB_PTSA_MIN 0x42c
|
||||
#define MC_SMMU_SMMU_PTSA_RATE 0x458
|
||||
#define MC_VE2_PTSA_RATE 0x494
|
||||
#define MC_GK_PTSA_RATE 0x53c
|
||||
#define MC_PTSA_GRANT_DECREMENT 0x960
|
||||
#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
|
||||
#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
|
||||
#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
|
||||
#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
|
||||
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
|
||||
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
|
||||
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
|
||||
#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
|
||||
#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0
|
||||
#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698
|
||||
#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
|
||||
#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0
|
||||
#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4
|
||||
#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
|
||||
#define MC_LATENCY_ALLOWANCE_HC_1 0x314
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
|
||||
#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4
|
||||
#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
|
||||
#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec
|
||||
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
|
||||
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4
|
||||
#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690
|
||||
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
|
||||
#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8
|
||||
#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
|
||||
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
|
||||
#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
|
||||
#define MC_MIN_LENGTH_APE_0 0xb34
|
||||
#define MC_MIN_LENGTH_DCB_2 0x8a8
|
||||
#define MC_MIN_LENGTH_A9AVP_0 0x950
|
||||
#define MC_MIN_LENGTH_TSEC_0 0x93c
|
||||
#define MC_MIN_LENGTH_DC_1 0x898
|
||||
#define MC_MIN_LENGTH_AXIAP_0 0x94c
|
||||
#define MC_MIN_LENGTH_ISP2B_0 0x930
|
||||
#define MC_MIN_LENGTH_VI2_0 0x944
|
||||
#define MC_MIN_LENGTH_DCB_0 0x8a0
|
||||
#define MC_MIN_LENGTH_DCB_1 0x8a4
|
||||
#define MC_MIN_LENGTH_PPCS_1 0x8f4
|
||||
#define MC_MIN_LENGTH_NVJPG_0 0xb3c
|
||||
#define MC_MIN_LENGTH_HDA_0 0x8c4
|
||||
#define MC_MIN_LENGTH_NVENC_0 0x8d4
|
||||
#define MC_MIN_LENGTH_SDMMC_0 0xb18
|
||||
#define MC_MIN_LENGTH_ISP2B_1 0x934
|
||||
#define MC_MIN_LENGTH_HC_1 0x8c0
|
||||
#define MC_MIN_LENGTH_DC_3 0xb20
|
||||
#define MC_MIN_LENGTH_AVPC_0 0x890
|
||||
#define MC_MIN_LENGTH_VIC_0 0x940
|
||||
#define MC_MIN_LENGTH_ISP2_0 0x91c
|
||||
#define MC_MIN_LENGTH_HC_0 0x8bc
|
||||
#define MC_MIN_LENGTH_SE_0 0xb38
|
||||
#define MC_MIN_LENGTH_NVDEC_0 0xb30
|
||||
#define MC_MIN_LENGTH_SATA_0 0x8fc
|
||||
#define MC_MIN_LENGTH_DC_0 0x894
|
||||
#define MC_MIN_LENGTH_XUSB_1 0x92c
|
||||
#define MC_MIN_LENGTH_DC_2 0x89c
|
||||
#define MC_MIN_LENGTH_SDMMCAA_0 0xb14
|
||||
#define MC_MIN_LENGTH_GPU_0 0xb04
|
||||
#define MC_MIN_LENGTH_ETR_0 0xb44
|
||||
#define MC_MIN_LENGTH_AFI_0 0x88c
|
||||
#define MC_MIN_LENGTH_PPCS_0 0x8f0
|
||||
#define MC_MIN_LENGTH_ISP2_1 0x920
|
||||
#define MC_MIN_LENGTH_XUSB_0 0x928
|
||||
#define MC_MIN_LENGTH_MPCORE_0 0x8cc
|
||||
#define MC_MIN_LENGTH_TSECB_0 0xb48
|
||||
#define MC_MIN_LENGTH_SDMMCA_0 0xb10
|
||||
#define MC_MIN_LENGTH_GPU2_0 0xb40
|
||||
#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c
|
||||
#define MC_MIN_LENGTH_PTC_0 0x8f8
|
||||
#define MC_EMEM_ARB_OVERRIDE_1 0x968
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988
|
||||
#define MC_EMEM_ARB_STATS_0 0x990
|
||||
#define MC_EMEM_ARB_STATS_1 0x994
|
||||
#define MC_MTS_CARVEOUT_BOM 0x9a0
|
||||
#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4
|
||||
#define MC_MTS_CARVEOUT_ADR_HI 0x9a8
|
||||
#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac
|
||||
#define MC_ERR_MTS_STATUS 0x9b0
|
||||
#define MC_ERR_MTS_ADR 0x9b4
|
||||
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
|
||||
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74
|
||||
#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10
|
||||
#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c
|
||||
#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4
|
||||
#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
|
||||
#define MC_SECURITY_CARVEOUT1_CFG0 0xc08
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68
|
||||
#define MC_SECURITY_CARVEOUT3_BOM 0xcac
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60
|
||||
#define MC_SECURITY_CARVEOUT3_CFG0 0xca8
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88
|
||||
#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64
|
||||
#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50
|
||||
#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14
|
||||
#define MC_SECURITY_CARVEOUT1_BOM 0xc0c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c
|
||||
#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8
|
||||
#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60
|
||||
#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80
|
||||
#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc
|
||||
#define MC_SECURITY_CARVEOUT4_BOM 0xcfc
|
||||
#define MC_SECURITY_CARVEOUT5_CFG0 0xd48
|
||||
#define MC_SECURITY_CARVEOUT2_BOM 0xc5c
|
||||
#define MC_SECURITY_CARVEOUT5_BOM 0xd4c
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0
|
||||
#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
|
||||
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
||||
#define MC_DA_CONFIG0 0x9dc
|
||||
#define MC_UNTRANSLATED_REGION_CHECK 0x948
|
||||
|
||||
/* Memory Controller clients */
|
||||
#define CLIENT_ACCESS_NUM_CLIENTS 32
|
||||
typedef enum {
|
||||
/* _ACCESS0 */
|
||||
CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
|
||||
/* _ACCESS1 */
|
||||
CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
|
||||
/* _ACCESS2 */
|
||||
CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
|
||||
/* _ACCESS3 */
|
||||
CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
|
||||
/* _ACCESS4 */
|
||||
CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
|
||||
} McClient;
|
||||
|
||||
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
|
||||
void mc_config_carveout();
|
||||
void mc_config_carveout_finalize();
|
||||
void mc_enable_ahb_redirect();
|
||||
void mc_disable_ahb_redirect();
|
||||
void mc_enable();
|
||||
|
||||
#endif
|
||||
@@ -1,713 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_PMC_H
|
||||
#define FUSEE_PMC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define PMC_BASE 0x7000E400
|
||||
#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n)
|
||||
|
||||
#define PMC_CONTROL_SDMMC1 (1 << 12)
|
||||
#define PMC_CONTROL_SDMMC3 (1 << 13)
|
||||
#define PMC_CONTROL_SDMMC4 (1 << 14)
|
||||
|
||||
#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00)
|
||||
#define APBDEV_PM_0 MAKE_PMC_REG(0x14)
|
||||
#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24)
|
||||
#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30)
|
||||
#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38)
|
||||
#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44)
|
||||
#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50)
|
||||
#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54)
|
||||
#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0)
|
||||
#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4)
|
||||
#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8)
|
||||
#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4)
|
||||
#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168)
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4)
|
||||
#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4)
|
||||
#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8)
|
||||
#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0)
|
||||
#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC)
|
||||
#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244)
|
||||
#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4)
|
||||
#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC)
|
||||
#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4)
|
||||
#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440)
|
||||
#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464)
|
||||
#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4)
|
||||
#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC)
|
||||
#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4)
|
||||
#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C)
|
||||
#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810)
|
||||
#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818)
|
||||
#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840)
|
||||
|
||||
#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234)
|
||||
#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238)
|
||||
#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120)
|
||||
#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C)
|
||||
|
||||
/* Power Management Controller (APBDEV_PMC_) regs */
|
||||
typedef struct {
|
||||
uint32_t cntrl; /* _CNTRL_0, 0x00 */
|
||||
uint32_t sec_disable; /* _SEC_DISABLE_0, 0x04 */
|
||||
uint32_t pmc_swrst; /* _PMC_SWRST_0, 0x08 */
|
||||
uint32_t wake_mask; /* _WAKE_MASK_0, 0x0c */
|
||||
uint32_t wake_lvl; /* _WAKE_LVL_0, 0x10 */
|
||||
uint32_t wake_status; /* _WAKE_STATUS_0, 0x14 */
|
||||
uint32_t sw_wake_status; /* _SW_WAKE_STATUS_0, 0x18 */
|
||||
uint32_t dpd_pads_oride; /* _DPD_PADS_ORIDE_0, 0x1c */
|
||||
uint32_t dpd_sample; /* _DPD_SAMPLE_0, 0x20 */
|
||||
uint32_t dpd_enable; /* _DPD_ENABLE_0, 0x24 */
|
||||
uint32_t pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, 0x28 */
|
||||
uint32_t clamp_status; /* _CLAMP_STATUS_0, 0x2c */
|
||||
uint32_t pwrgate_toggle; /* _PWRGATE_TOGGLE_0, 0x30 */
|
||||
uint32_t remove_clamping; /* _REMOVE_CLAMPING_0, 0x34 */
|
||||
uint32_t pwrgate_status; /* _PWRGATE_STATUS_0, 0x38 */
|
||||
uint32_t pwrgood_timer; /* _PWRGOOD_TIMER_0, 0x3c */
|
||||
uint32_t blink_timer; /* _BLINK_TIMER_0, 0x40 */
|
||||
uint32_t no_iopower; /* _NO_IOPOWER_0, 0x44 */
|
||||
uint32_t pwr_det; /* _PWR_DET_0, 0x48 */
|
||||
uint32_t pwr_det_latch; /* _PWR_DET_LATCH_0, 0x4c */
|
||||
uint32_t scratch0; /* _SCRATCH0_0, 0x50 */
|
||||
uint32_t scratch1; /* _SCRATCH1_0, 0x54 */
|
||||
uint32_t scratch2; /* _SCRATCH2_0, 0x58 */
|
||||
uint32_t scratch3; /* _SCRATCH3_0, 0x5c */
|
||||
uint32_t scratch4; /* _SCRATCH4_0, 0x60 */
|
||||
uint32_t scratch5; /* _SCRATCH5_0, 0x64 */
|
||||
uint32_t scratch6; /* _SCRATCH6_0, 0x68 */
|
||||
uint32_t scratch7; /* _SCRATCH7_0, 0x6c */
|
||||
uint32_t scratch8; /* _SCRATCH8_0, 0x70 */
|
||||
uint32_t scratch9; /* _SCRATCH9_0, 0x74 */
|
||||
uint32_t scratch10; /* _SCRATCH10_0, 0x78 */
|
||||
uint32_t scratch11; /* _SCRATCH11_0, 0x7c */
|
||||
uint32_t scratch12; /* _SCRATCH12_0, 0x80 */
|
||||
uint32_t scratch13; /* _SCRATCH13_0, 0x84 */
|
||||
uint32_t scratch14; /* _SCRATCH14_0, 0x88 */
|
||||
uint32_t scratch15; /* _SCRATCH15_0, 0x8c */
|
||||
uint32_t scratch16; /* _SCRATCH16_0, 0x90 */
|
||||
uint32_t scratch17; /* _SCRATCH17_0, 0x94 */
|
||||
uint32_t scratch18; /* _SCRATCH18_0, 0x98 */
|
||||
uint32_t scratch19; /* _SCRATCH19_0, 0x9c */
|
||||
uint32_t scratch20; /* _SCRATCH20_0, 0xa0 */
|
||||
uint32_t scratch21; /* _SCRATCH21_0, 0xa4 */
|
||||
uint32_t scratch22; /* _SCRATCH22_0, 0xa8 */
|
||||
uint32_t scratch23; /* _SCRATCH23_0, 0xac */
|
||||
uint32_t secure_scratch0; /* _SECURE_SCRATCH0_0, 0xb0 */
|
||||
uint32_t secure_scratch1; /* _SECURE_SCRATCH1_0, 0xb4 */
|
||||
uint32_t secure_scratch2; /* _SECURE_SCRATCH2_0, 0xb8 */
|
||||
uint32_t secure_scratch3; /* _SECURE_SCRATCH3_0, 0xbc */
|
||||
uint32_t secure_scratch4; /* _SECURE_SCRATCH4_0, 0xc0 */
|
||||
uint32_t secure_scratch5; /* _SECURE_SCRATCH5_0, 0xc4 */
|
||||
uint32_t cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, 0xc8 */
|
||||
uint32_t cpupwroff_timer; /* _CPUPWROFF_TIMER_0, 0xcc */
|
||||
uint32_t pg_mask; /* _PG_MASK_0, 0xd0 */
|
||||
uint32_t pg_mask_1; /* _PG_MASK_1_0, 0xd4 */
|
||||
uint32_t auto_wake_lvl; /* _AUTO_WAKE_LVL_0, 0xd8 */
|
||||
uint32_t auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, 0xdc */
|
||||
uint32_t wake_delay; /* _WAKE_DELAY_0, 0xe0 */
|
||||
uint32_t pwr_det_val; /* _PWR_DET_VAL_0, 0xe4 */
|
||||
uint32_t ddr_pwr; /* _DDR_PWR_0, 0xe8 */
|
||||
uint32_t usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, 0xec */
|
||||
uint32_t usb_ao; /* _USB_AO_0, 0xf0 */
|
||||
uint32_t crypto_op; /* _CRYPTO_OP_0, 0xf4 */
|
||||
uint32_t pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, 0xf8 */
|
||||
uint32_t scratch24; /* _SCRATCH24_0, 0xfc */
|
||||
uint32_t scratch25; /* _SCRATCH25_0, 0x100 */
|
||||
uint32_t scratch26; /* _SCRATCH26_0, 0x104 */
|
||||
uint32_t scratch27; /* _SCRATCH27_0, 0x108 */
|
||||
uint32_t scratch28; /* _SCRATCH28_0, 0x10c */
|
||||
uint32_t scratch29; /* _SCRATCH29_0, 0x110 */
|
||||
uint32_t scratch30; /* _SCRATCH30_0, 0x114 */
|
||||
uint32_t scratch31; /* _SCRATCH31_0, 0x118 */
|
||||
uint32_t scratch32; /* _SCRATCH32_0, 0x11c */
|
||||
uint32_t scratch33; /* _SCRATCH33_0, 0x120 */
|
||||
uint32_t scratch34; /* _SCRATCH34_0, 0x124 */
|
||||
uint32_t scratch35; /* _SCRATCH35_0, 0x128 */
|
||||
uint32_t scratch36; /* _SCRATCH36_0, 0x12c */
|
||||
uint32_t scratch37; /* _SCRATCH37_0, 0x130 */
|
||||
uint32_t scratch38; /* _SCRATCH38_0, 0x134 */
|
||||
uint32_t scratch39; /* _SCRATCH39_0, 0x138 */
|
||||
uint32_t scratch40; /* _SCRATCH40_0, 0x13c */
|
||||
uint32_t scratch41; /* _SCRATCH41_0, 0x140 */
|
||||
uint32_t scratch42; /* _SCRATCH42_0, 0x144 */
|
||||
uint32_t bondout_mirror0; /* _BONDOUT_MIRROR0_0, 0x148 */
|
||||
uint32_t bondout_mirror1; /* _BONDOUT_MIRROR1_0, 0x14c */
|
||||
uint32_t bondout_mirror2; /* _BONDOUT_MIRROR2_0, 0x150 */
|
||||
uint32_t sys_33v_en; /* _SYS_33V_EN_0, 0x154 */
|
||||
uint32_t bondout_mirror_access; /* _BONDOUT_MIRROR_ACCESS_0, 0x158 */
|
||||
uint32_t gate; /* _GATE_0, 0x15c */
|
||||
uint32_t wake2_mask; /* _WAKE2_MASK_0, 0x160 */
|
||||
uint32_t wake2_lvl; /* _WAKE2_LVL_0, 0x164 */
|
||||
uint32_t wake2_status; /* _WAKE2_STATUS_0, 0x168 */
|
||||
uint32_t sw_wake2_status; /* _SW_WAKE2_STATUS_0, 0x16c */
|
||||
uint32_t auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, 0x170 */
|
||||
uint32_t pg_mask_2; /* _PG_MASK_2_0, 0x174 */
|
||||
uint32_t pg_mask_ce1; /* _PG_MASK_CE1_0, 0x178 */
|
||||
uint32_t pg_mask_ce2; /* _PG_MASK_CE2_0, 0x17c */
|
||||
uint32_t pg_mask_ce3; /* _PG_MASK_CE3_0, 0x180 */
|
||||
uint32_t pwrgate_timer_ce_0; /* _PWRGATE_TIMER_CE_0_0, 0x184 */
|
||||
uint32_t pwrgate_timer_ce_1; /* _PWRGATE_TIMER_CE_1_0, 0x188 */
|
||||
uint32_t pwrgate_timer_ce_2; /* _PWRGATE_TIMER_CE_2_0, 0x18c */
|
||||
uint32_t pwrgate_timer_ce_3; /* _PWRGATE_TIMER_CE_3_0, 0x190 */
|
||||
uint32_t pwrgate_timer_ce_4; /* _PWRGATE_TIMER_CE_4_0, 0x194 */
|
||||
uint32_t pwrgate_timer_ce_5; /* _PWRGATE_TIMER_CE_5_0, 0x198 */
|
||||
uint32_t pwrgate_timer_ce_6; /* _PWRGATE_TIMER_CE_6_0, 0x19c */
|
||||
uint32_t pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, 0x1a0 */
|
||||
uint32_t osc_edpd_over; /* _OSC_EDPD_OVER_0, 0x1a4 */
|
||||
uint32_t clk_out_cntrl; /* _CLK_OUT_CNTRL_0, 0x1a8 */
|
||||
uint32_t sata_pwrgt; /* _SATA_PWRGT_0, 0x1ac */
|
||||
uint32_t sensor_ctrl; /* _SENSOR_CTRL_0, 0x1b0 */
|
||||
uint32_t rst_status; /* _RST_STATUS_0, 0x1b4 */
|
||||
uint32_t io_dpd_req; /* _IO_DPD_REQ_0, 0x1b8 */
|
||||
uint32_t io_dpd_status; /* _IO_DPD_STATUS_0, 0x1bc */
|
||||
uint32_t io_dpd2_req; /* _IO_DPD2_REQ_0, 0x1c0 */
|
||||
uint32_t io_dpd2_status; /* _IO_DPD2_STATUS_0, 0x1c4 */
|
||||
uint32_t sel_dpd_tim; /* _SEL_DPD_TIM_0, 0x1c8 */
|
||||
uint32_t vddp_sel; /* _VDDP_SEL_0, 0x1cc */
|
||||
uint32_t ddr_cfg; /* _DDR_CFG_0, 0x1d0 */
|
||||
uint32_t _0x1d4[2];
|
||||
uint32_t pllm_wb0_override_freq; /* _PLLM_WB0_OVERRIDE_FREQ_0, 0x1dc */
|
||||
uint32_t _0x1e0;
|
||||
uint32_t pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, 0x1e4 */
|
||||
uint32_t dsi_sel_dpd; /* _DSI_SEL_DPD_0, 0x1e8 */
|
||||
uint32_t utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, 0x1ec */
|
||||
uint32_t utmip_uhsic_saved_state; /* _UTMIP_UHSIC_SAVED_STATE_0, 0x1f0 */
|
||||
uint32_t _0x1f4;
|
||||
uint32_t utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, 0x1f8 */
|
||||
uint32_t utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, 0x1fc */
|
||||
uint32_t utmip_uhsic_sleepwalk_cfg; /* _UTMIP_UHSIC_SLEEPWALK_CFG_0, 0x200 */
|
||||
uint32_t utmip_sleepwalk_p0; /* _UTMIP_SLEEPWALK_P0_0, 0x204 */
|
||||
uint32_t utmip_sleepwalk_p1; /* _UTMIP_SLEEPWALK_P1_0, 0x208 */
|
||||
uint32_t utmip_sleepwalk_p2; /* _UTMIP_SLEEPWALK_P2_0, 0x20c */
|
||||
uint32_t uhsic_sleepwalk_p0; /* _UHSIC_SLEEPWALK_P0_0, 0x210 */
|
||||
uint32_t utmip_uhsic_status; /* _UTMIP_UHSIC_STATUS_0, 0x214 */
|
||||
uint32_t utmip_uhsic_fake; /* _UTMIP_UHSIC_FAKE_0, 0x218 */
|
||||
uint32_t bondout_mirror3; /* _BONDOUT_MIRROR3_0, 0x21c */
|
||||
uint32_t bondout_mirror4; /* _BONDOUT_MIRROR4_0, 0x220 */
|
||||
uint32_t secure_scratch6; /* _SECURE_SCRATCH6_0, 0x224 */
|
||||
uint32_t secure_scratch7; /* _SECURE_SCRATCH7_0, 0x228 */
|
||||
uint32_t scratch43; /* _SCRATCH43_0, 0x22c */
|
||||
uint32_t scratch44; /* _SCRATCH44_0, 0x230 */
|
||||
uint32_t scratch45; /* _SCRATCH45_0, 0x234 */
|
||||
uint32_t scratch46; /* _SCRATCH46_0, 0x238 */
|
||||
uint32_t scratch47; /* _SCRATCH47_0, 0x23c */
|
||||
uint32_t scratch48; /* _SCRATCH48_0, 0x240 */
|
||||
uint32_t scratch49; /* _SCRATCH49_0, 0x244 */
|
||||
uint32_t scratch50; /* _SCRATCH50_0, 0x248 */
|
||||
uint32_t scratch51; /* _SCRATCH51_0, 0x24c */
|
||||
uint32_t scratch52; /* _SCRATCH52_0, 0x250 */
|
||||
uint32_t scratch53; /* _SCRATCH53_0, 0x254 */
|
||||
uint32_t scratch54; /* _SCRATCH54_0, 0x258 */
|
||||
uint32_t scratch55; /* _SCRATCH55_0, 0x25c */
|
||||
uint32_t scratch0_eco; /* _SCRATCH0_ECO_0, 0x260 */
|
||||
uint32_t por_dpd_ctrl; /* _POR_DPD_CTRL_0, 0x264 */
|
||||
uint32_t scratch2_eco; /* _SCRATCH2_ECO_0, 0x268 */
|
||||
uint32_t utmip_uhsic_line_wakeup; /* _UTMIP_UHSIC_LINE_WAKEUP_0, 0x26c */
|
||||
uint32_t utmip_bias_master_cntrl; /* _UTMIP_BIAS_MASTER_CNTRL_0, 0x270 */
|
||||
uint32_t utmip_master_config; /* _UTMIP_MASTER_CONFIG_0, 0x274 */
|
||||
uint32_t td_pwrgate_inter_part_timer; /* _TD_PWRGATE_INTER_PART_TIMER_0, 0x278 */
|
||||
uint32_t utmip_uhsic2_triggers; /* _UTMIP_UHSIC2_TRIGGERS_0, 0x27c */
|
||||
uint32_t utmip_uhsic2_saved_state; /* _UTMIP_UHSIC2_SAVED_STATE_0, 0x280 */
|
||||
uint32_t utmip_uhsic2_sleep_cfg; /* _UTMIP_UHSIC2_SLEEP_CFG_0, 0x284 */
|
||||
uint32_t utmip_uhsic2_sleepwalk_cfg; /* _UTMIP_UHSIC2_SLEEPWALK_CFG_0, 0x288 */
|
||||
uint32_t uhsic2_sleepwalk_p1; /* _UHSIC2_SLEEPWALK_P1_0, 0x28c */
|
||||
uint32_t utmip_uhsic2_status; /* _UTMIP_UHSIC2_STATUS_0, 0x290 */
|
||||
uint32_t utmip_uhsic2_fake; /* _UTMIP_UHSIC2_FAKE_0, 0x294 */
|
||||
uint32_t utmip_uhsic2_line_wakeup; /* _UTMIP_UHSIC2_LINE_WAKEUP_0, 0x298 */
|
||||
uint32_t utmip_master2_config; /* _UTMIP_MASTER2_CONFIG_0, 0x29c */
|
||||
uint32_t utmip_uhsic_rpd_cfg; /* _UTMIP_UHSIC_RPD_CFG_0, 0x2a0 */
|
||||
uint32_t pg_mask_ce0; /* _PG_MASK_CE0_0, 0x2a4 */
|
||||
uint32_t pg_mask_3; /* _PG_MASK_3_0, 0x2a8 */
|
||||
uint32_t pg_mask_4; /* _PG_MASK_4_0, 0x2ac */
|
||||
uint32_t pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2_0, 0x2b0 */
|
||||
uint32_t tsc_mult; /* _TSC_MULT_0, 0x2b4 */
|
||||
uint32_t cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, 0x2b8 */
|
||||
uint32_t glb_amap_cfg; /* _GLB_AMAP_CFG_0, 0x2bc */
|
||||
uint32_t sticky_bits; /* _STICKY_BITS_0, 0x2c0 */
|
||||
uint32_t sec_disable2; /* _SEC_DISABLE2_0, 0x2c4 */
|
||||
uint32_t weak_bias; /* _WEAK_BIAS_0, 0x2c8 */
|
||||
uint32_t reg_short; /* _REG_SHORT_0, 0x2cc */
|
||||
uint32_t pg_mask_andor; /* _PG_MASK_ANDOR_0, 0x2d0 */
|
||||
uint32_t gpu_rg_cntrl; /* _GPU_RG_CNTRL_0, 0x2d4 */
|
||||
uint32_t sec_disable3; /* _SEC_DISABLE3_0, 0x2d8 */
|
||||
uint32_t pg_mask_5; /* _PG_MASK_5_0, 0x2dc */
|
||||
uint32_t pg_mask_6; /* _PG_MASK_6_0, 0x2e0 */
|
||||
uint32_t _0x2e4[7];
|
||||
uint32_t secure_scratch8; /* _SECURE_SCRATCH8_0, 0x300 */
|
||||
uint32_t secure_scratch9; /* _SECURE_SCRATCH9_0, 0x304 */
|
||||
uint32_t secure_scratch10; /* _SECURE_SCRATCH10_0, 0x308 */
|
||||
uint32_t secure_scratch11; /* _SECURE_SCRATCH11_0, 0x30c */
|
||||
uint32_t secure_scratch12; /* _SECURE_SCRATCH12_0, 0x310 */
|
||||
uint32_t secure_scratch13; /* _SECURE_SCRATCH13_0, 0x314 */
|
||||
uint32_t secure_scratch14; /* _SECURE_SCRATCH14_0, 0x318 */
|
||||
uint32_t secure_scratch15; /* _SECURE_SCRATCH15_0, 0x31c */
|
||||
uint32_t secure_scratch16; /* _SECURE_SCRATCH16_0, 0x320 */
|
||||
uint32_t secure_scratch17; /* _SECURE_SCRATCH17_0, 0x324 */
|
||||
uint32_t secure_scratch18; /* _SECURE_SCRATCH18_0, 0x328 */
|
||||
uint32_t secure_scratch19; /* _SECURE_SCRATCH19_0, 0x32c */
|
||||
uint32_t secure_scratch20; /* _SECURE_SCRATCH20_0, 0x330 */
|
||||
uint32_t secure_scratch21; /* _SECURE_SCRATCH21_0, 0x334 */
|
||||
uint32_t secure_scratch22; /* _SECURE_SCRATCH22_0, 0x338 */
|
||||
uint32_t secure_scratch23; /* _SECURE_SCRATCH23_0, 0x33c */
|
||||
uint32_t secure_scratch24; /* _SECURE_SCRATCH24_0, 0x340 */
|
||||
uint32_t secure_scratch25; /* _SECURE_SCRATCH25_0, 0x344 */
|
||||
uint32_t secure_scratch26; /* _SECURE_SCRATCH26_0, 0x348 */
|
||||
uint32_t secure_scratch27; /* _SECURE_SCRATCH27_0, 0x34c */
|
||||
uint32_t secure_scratch28; /* _SECURE_SCRATCH28_0, 0x350 */
|
||||
uint32_t secure_scratch29; /* _SECURE_SCRATCH29_0, 0x354 */
|
||||
uint32_t secure_scratch30; /* _SECURE_SCRATCH30_0, 0x358 */
|
||||
uint32_t secure_scratch31; /* _SECURE_SCRATCH31_0, 0x35c */
|
||||
uint32_t secure_scratch32; /* _SECURE_SCRATCH32_0, 0x360 */
|
||||
uint32_t secure_scratch33; /* _SECURE_SCRATCH33_0, 0x364 */
|
||||
uint32_t secure_scratch34; /* _SECURE_SCRATCH34_0, 0x368 */
|
||||
uint32_t secure_scratch35; /* _SECURE_SCRATCH35_0, 0x36c */
|
||||
uint32_t secure_scratch36; /* _SECURE_SCRATCH36_0, 0x370 */
|
||||
uint32_t secure_scratch37; /* _SECURE_SCRATCH37_0, 0x374 */
|
||||
uint32_t secure_scratch38; /* _SECURE_SCRATCH38_0, 0x378 */
|
||||
uint32_t secure_scratch39; /* _SECURE_SCRATCH39_0, 0x37c */
|
||||
uint32_t secure_scratch40; /* _SECURE_SCRATCH40_0, 0x380 */
|
||||
uint32_t secure_scratch41; /* _SECURE_SCRATCH41_0, 0x384 */
|
||||
uint32_t secure_scratch42; /* _SECURE_SCRATCH42_0, 0x388 */
|
||||
uint32_t secure_scratch43; /* _SECURE_SCRATCH43_0, 0x38c */
|
||||
uint32_t secure_scratch44; /* _SECURE_SCRATCH44_0, 0x390 */
|
||||
uint32_t secure_scratch45; /* _SECURE_SCRATCH45_0, 0x394 */
|
||||
uint32_t secure_scratch46; /* _SECURE_SCRATCH46_0, 0x398 */
|
||||
uint32_t secure_scratch47; /* _SECURE_SCRATCH47_0, 0x39c */
|
||||
uint32_t secure_scratch48; /* _SECURE_SCRATCH48_0, 0x3a0 */
|
||||
uint32_t secure_scratch49; /* _SECURE_SCRATCH49_0, 0x3a4 */
|
||||
uint32_t secure_scratch50; /* _SECURE_SCRATCH50_0, 0x3a8 */
|
||||
uint32_t secure_scratch51; /* _SECURE_SCRATCH51_0, 0x3ac */
|
||||
uint32_t secure_scratch52; /* _SECURE_SCRATCH52_0, 0x3b0 */
|
||||
uint32_t secure_scratch53; /* _SECURE_SCRATCH53_0, 0x3b4 */
|
||||
uint32_t secure_scratch54; /* _SECURE_SCRATCH54_0, 0x3b8 */
|
||||
uint32_t secure_scratch55; /* _SECURE_SCRATCH55_0, 0x3bc */
|
||||
uint32_t secure_scratch56; /* _SECURE_SCRATCH56_0, 0x3c0 */
|
||||
uint32_t secure_scratch57; /* _SECURE_SCRATCH57_0, 0x3c4 */
|
||||
uint32_t secure_scratch58; /* _SECURE_SCRATCH58_0, 0x3c8 */
|
||||
uint32_t secure_scratch59; /* _SECURE_SCRATCH59_0, 0x3cc */
|
||||
uint32_t secure_scratch60; /* _SECURE_SCRATCH60_0, 0x3d0 */
|
||||
uint32_t secure_scratch61; /* _SECURE_SCRATCH61_0, 0x3d4 */
|
||||
uint32_t secure_scratch62; /* _SECURE_SCRATCH62_0, 0x3d8 */
|
||||
uint32_t secure_scratch63; /* _SECURE_SCRATCH63_0, 0x3dc */
|
||||
uint32_t secure_scratch64; /* _SECURE_SCRATCH64_0, 0x3e0 */
|
||||
uint32_t secure_scratch65; /* _SECURE_SCRATCH65_0, 0x3e4 */
|
||||
uint32_t secure_scratch66; /* _SECURE_SCRATCH66_0, 0x3e8 */
|
||||
uint32_t secure_scratch67; /* _SECURE_SCRATCH67_0, 0x3ec */
|
||||
uint32_t secure_scratch68; /* _SECURE_SCRATCH68_0, 0x3f0 */
|
||||
uint32_t secure_scratch69; /* _SECURE_SCRATCH69_0, 0x3f4 */
|
||||
uint32_t secure_scratch70; /* _SECURE_SCRATCH70_0, 0x3f8 */
|
||||
uint32_t secure_scratch71; /* _SECURE_SCRATCH71_0, 0x3fc */
|
||||
uint32_t secure_scratch72; /* _SECURE_SCRATCH72_0, 0x400 */
|
||||
uint32_t secure_scratch73; /* _SECURE_SCRATCH73_0, 0x404 */
|
||||
uint32_t secure_scratch74; /* _SECURE_SCRATCH74_0, 0x408 */
|
||||
uint32_t secure_scratch75; /* _SECURE_SCRATCH75_0, 0x40c */
|
||||
uint32_t secure_scratch76; /* _SECURE_SCRATCH76_0, 0x410 */
|
||||
uint32_t secure_scratch77; /* _SECURE_SCRATCH77_0, 0x414 */
|
||||
uint32_t secure_scratch78; /* _SECURE_SCRATCH78_0, 0x418 */
|
||||
uint32_t secure_scratch79; /* _SECURE_SCRATCH79_0, 0x41c */
|
||||
uint32_t _0x420[8];
|
||||
uint32_t cntrl2; /* _CNTRL2_0, 0x440 */
|
||||
uint32_t io_dpd_off_mask; /* _IO_DPD_OFF_MASK_0, 0x444 */
|
||||
uint32_t io_dpd2_off_mask; /* _IO_DPD2_OFF_MASK_0, 0x448 */
|
||||
uint32_t event_counter; /* _EVENT_COUNTER_0, 0x44c */
|
||||
uint32_t fuse_control; /* _FUSE_CONTROL_0, 0x450 */
|
||||
uint32_t scratch1_eco; /* _SCRATCH1_ECO_0, 0x454 */
|
||||
uint32_t _0x458;
|
||||
uint32_t io_dpd3_req; /* _IO_DPD3_REQ_0, 0x45c */
|
||||
uint32_t io_dpd3_status; /* _IO_DPD3_STATUS_0, 0x460 */
|
||||
uint32_t io_dpd4_req; /* _IO_DPD4_REQ_0, 0x464 */
|
||||
uint32_t io_dpd4_status; /* _IO_DPD4_STATUS_0, 0x468 */
|
||||
uint32_t _0x46c[2];
|
||||
uint32_t direct_thermtrip_cfg; /* _DIRECT_THERMTRIP_CFG_0, 0x474 */
|
||||
uint32_t tsosc_delay; /* _TSOSC_DELAY_0, 0x478 */
|
||||
uint32_t set_sw_clamp; /* _SET_SW_CLAMP_0, 0x47c */
|
||||
uint32_t debug_authentication; /* _DEBUG_AUTHENTICATION_0, 0x480 */
|
||||
uint32_t aotag_cfg; /* _AOTAG_CFG_0, 0x484 */
|
||||
uint32_t aotag_thresh1_cfg; /* _AOTAG_THRESH1_CFG_0, 0x488 */
|
||||
uint32_t aotag_thresh2_cfg; /* _AOTAG_THRESH2_CFG_0, 0x48c */
|
||||
uint32_t aotag_thresh3_cfg; /* _AOTAG_THRESH3_CFG_0, 0x490 */
|
||||
uint32_t aotag_status; /* _AOTAG_STATUS_0, 0x494 */
|
||||
uint32_t aotag_security; /* _AOTAG_SECURITY_0, 0x498 */
|
||||
uint32_t tsensor_config0; /* _TSENSOR_CONFIG0_0, 0x49c */
|
||||
uint32_t tsensor_config1; /* _TSENSOR_CONFIG1_0, 0x4a0 */
|
||||
uint32_t tsensor_config2; /* _TSENSOR_CONFIG2_0, 0x4a4 */
|
||||
uint32_t tsensor_status0; /* _TSENSOR_STATUS0_0, 0x4a8 */
|
||||
uint32_t tsensor_status1; /* _TSENSOR_STATUS1_0, 0x4ac */
|
||||
uint32_t tsensor_status2; /* _TSENSOR_STATUS2_0, 0x4b0 */
|
||||
uint32_t tsensor_pdiv; /* _TSENSOR_PDIV_0, 0x4b4 */
|
||||
uint32_t aotag_intr_en; /* _AOTAG_INTR_EN_0, 0x4b8 */
|
||||
uint32_t aotag_intr_dis; /* _AOTAG_INTR_DIS_0, 0x4bc */
|
||||
uint32_t utmip_pad_cfg0; /* _UTMIP_PAD_CFG0_0, 0x4c0 */
|
||||
uint32_t utmip_pad_cfg1; /* _UTMIP_PAD_CFG1_0, 0x4c4 */
|
||||
uint32_t utmip_pad_cfg2; /* _UTMIP_PAD_CFG2_0, 0x4c8 */
|
||||
uint32_t utmip_pad_cfg3; /* _UTMIP_PAD_CFG3_0, 0x4cc */
|
||||
uint32_t utmip_uhsic_sleep_cfg1; /* _UTMIP_UHSIC_SLEEP_CFG1_0, 0x4d0 */
|
||||
uint32_t cc4_hvc_control; /* _CC4_HVC_CONTROL_0, 0x4d4 */
|
||||
uint32_t wake_debounce_en; /* _WAKE_DEBOUNCE_EN_0, 0x4d8 */
|
||||
uint32_t ramdump_ctl_status; /* _RAMDUMP_CTL_STATUS_0, 0x4dc */
|
||||
uint32_t utmip_sleepwalk_p3; /* _UTMIP_SLEEPWALK_P3_0, 0x4e0 */
|
||||
uint32_t ddr_cntrl; /* _DDR_CNTRL_0, 0x4e4 */
|
||||
uint32_t _0x4e8[50];
|
||||
uint32_t sec_disable4; /* _SEC_DISABLE4_0, 0x5b0 */
|
||||
uint32_t sec_disable5; /* _SEC_DISABLE5_0, 0x5b4 */
|
||||
uint32_t sec_disable6; /* _SEC_DISABLE6_0, 0x5b8 */
|
||||
uint32_t sec_disable7; /* _SEC_DISABLE7_0, 0x5bc */
|
||||
uint32_t sec_disable8; /* _SEC_DISABLE8_0, 0x5c0 */
|
||||
uint32_t sec_disable9; /* _SEC_DISABLE9_0, 0x5c4 */
|
||||
uint32_t sec_disable10; /* _SEC_DISABLE10_0, 0x5c8 */
|
||||
uint32_t _0x5cc[13];
|
||||
uint32_t scratch56; /* _SCRATCH56_0, 0x600 */
|
||||
uint32_t scratch57; /* _SCRATCH57_0, 0x604 */
|
||||
uint32_t scratch58; /* _SCRATCH58_0, 0x608 */
|
||||
uint32_t scratch59; /* _SCRATCH59_0, 0x60c */
|
||||
uint32_t scratch60; /* _SCRATCH60_0, 0x610 */
|
||||
uint32_t scratch61; /* _SCRATCH61_0, 0x614 */
|
||||
uint32_t scratch62; /* _SCRATCH62_0, 0x618 */
|
||||
uint32_t scratch63; /* _SCRATCH63_0, 0x61c */
|
||||
uint32_t scratch64; /* _SCRATCH64_0, 0x620 */
|
||||
uint32_t scratch65; /* _SCRATCH65_0, 0x624 */
|
||||
uint32_t scratch66; /* _SCRATCH66_0, 0x628 */
|
||||
uint32_t scratch67; /* _SCRATCH67_0, 0x62c */
|
||||
uint32_t scratch68; /* _SCRATCH68_0, 0x630 */
|
||||
uint32_t scratch69; /* _SCRATCH69_0, 0x634 */
|
||||
uint32_t scratch70; /* _SCRATCH70_0, 0x638 */
|
||||
uint32_t scratch71; /* _SCRATCH71_0, 0x63c */
|
||||
uint32_t scratch72; /* _SCRATCH72_0, 0x640 */
|
||||
uint32_t scratch73; /* _SCRATCH73_0, 0x644 */
|
||||
uint32_t scratch74; /* _SCRATCH74_0, 0x648 */
|
||||
uint32_t scratch75; /* _SCRATCH75_0, 0x64c */
|
||||
uint32_t scratch76; /* _SCRATCH76_0, 0x650 */
|
||||
uint32_t scratch77; /* _SCRATCH77_0, 0x654 */
|
||||
uint32_t scratch78; /* _SCRATCH78_0, 0x658 */
|
||||
uint32_t scratch79; /* _SCRATCH79_0, 0x65c */
|
||||
uint32_t scratch80; /* _SCRATCH80_0, 0x660 */
|
||||
uint32_t scratch81; /* _SCRATCH81_0, 0x664 */
|
||||
uint32_t scratch82; /* _SCRATCH82_0, 0x668 */
|
||||
uint32_t scratch83; /* _SCRATCH83_0, 0x66c */
|
||||
uint32_t scratch84; /* _SCRATCH84_0, 0x670 */
|
||||
uint32_t scratch85; /* _SCRATCH85_0, 0x674 */
|
||||
uint32_t scratch86; /* _SCRATCH86_0, 0x678 */
|
||||
uint32_t scratch87; /* _SCRATCH87_0, 0x67c */
|
||||
uint32_t scratch88; /* _SCRATCH88_0, 0x680 */
|
||||
uint32_t scratch89; /* _SCRATCH89_0, 0x684 */
|
||||
uint32_t scratch90; /* _SCRATCH90_0, 0x688 */
|
||||
uint32_t scratch91; /* _SCRATCH91_0, 0x68c */
|
||||
uint32_t scratch92; /* _SCRATCH92_0, 0x690 */
|
||||
uint32_t scratch93; /* _SCRATCH93_0, 0x694 */
|
||||
uint32_t scratch94; /* _SCRATCH94_0, 0x698 */
|
||||
uint32_t scratch95; /* _SCRATCH95_0, 0x69c */
|
||||
uint32_t scratch96; /* _SCRATCH96_0, 0x6a0 */
|
||||
uint32_t scratch97; /* _SCRATCH97_0, 0x6a4 */
|
||||
uint32_t scratch98; /* _SCRATCH98_0, 0x6a8 */
|
||||
uint32_t scratch99; /* _SCRATCH99_0, 0x6ac */
|
||||
uint32_t scratch100; /* _SCRATCH100_0, 0x6b0 */
|
||||
uint32_t scratch101; /* _SCRATCH101_0, 0x6b4 */
|
||||
uint32_t scratch102; /* _SCRATCH102_0, 0x6b8 */
|
||||
uint32_t scratch103; /* _SCRATCH103_0, 0x6bc */
|
||||
uint32_t scratch104; /* _SCRATCH104_0, 0x6c0 */
|
||||
uint32_t scratch105; /* _SCRATCH105_0, 0x6c4 */
|
||||
uint32_t scratch106; /* _SCRATCH106_0, 0x6c8 */
|
||||
uint32_t scratch107; /* _SCRATCH107_0, 0x6cc */
|
||||
uint32_t scratch108; /* _SCRATCH108_0, 0x6d0 */
|
||||
uint32_t scratch109; /* _SCRATCH109_0, 0x6d4 */
|
||||
uint32_t scratch110; /* _SCRATCH110_0, 0x6d8 */
|
||||
uint32_t scratch111; /* _SCRATCH111_0, 0x6dc */
|
||||
uint32_t scratch112; /* _SCRATCH112_0, 0x6e0 */
|
||||
uint32_t scratch113; /* _SCRATCH113_0, 0x6e4 */
|
||||
uint32_t scratch114; /* _SCRATCH114_0, 0x6e8 */
|
||||
uint32_t scratch115; /* _SCRATCH115_0, 0x6ec */
|
||||
uint32_t scratch116; /* _SCRATCH116_0, 0x6f0 */
|
||||
uint32_t scratch117; /* _SCRATCH117_0, 0x6f4 */
|
||||
uint32_t scratch118; /* _SCRATCH118_0, 0x6f8 */
|
||||
uint32_t scratch119; /* _SCRATCH119_0, 0x6fc */
|
||||
uint32_t scratch120; /* _SCRATCH120_0, 0x700 */
|
||||
uint32_t scratch121; /* _SCRATCH121_0, 0x704 */
|
||||
uint32_t scratch122; /* _SCRATCH122_0, 0x708 */
|
||||
uint32_t scratch123; /* _SCRATCH123_0, 0x70c */
|
||||
uint32_t scratch124; /* _SCRATCH124_0, 0x710 */
|
||||
uint32_t scratch125; /* _SCRATCH125_0, 0x714 */
|
||||
uint32_t scratch126; /* _SCRATCH126_0, 0x718 */
|
||||
uint32_t scratch127; /* _SCRATCH127_0, 0x71c */
|
||||
uint32_t scratch128; /* _SCRATCH128_0, 0x720 */
|
||||
uint32_t scratch129; /* _SCRATCH129_0, 0x724 */
|
||||
uint32_t scratch130; /* _SCRATCH130_0, 0x728 */
|
||||
uint32_t scratch131; /* _SCRATCH131_0, 0x72c */
|
||||
uint32_t scratch132; /* _SCRATCH132_0, 0x730 */
|
||||
uint32_t scratch133; /* _SCRATCH133_0, 0x734 */
|
||||
uint32_t scratch134; /* _SCRATCH134_0, 0x738 */
|
||||
uint32_t scratch135; /* _SCRATCH135_0, 0x73c */
|
||||
uint32_t scratch136; /* _SCRATCH136_0, 0x740 */
|
||||
uint32_t scratch137; /* _SCRATCH137_0, 0x744 */
|
||||
uint32_t scratch138; /* _SCRATCH138_0, 0x748 */
|
||||
uint32_t scratch139; /* _SCRATCH139_0, 0x74c */
|
||||
uint32_t scratch140; /* _SCRATCH140_0, 0x750 */
|
||||
uint32_t scratch141; /* _SCRATCH141_0, 0x754 */
|
||||
uint32_t scratch142; /* _SCRATCH142_0, 0x758 */
|
||||
uint32_t scratch143; /* _SCRATCH143_0, 0x75c */
|
||||
uint32_t scratch144; /* _SCRATCH144_0, 0x760 */
|
||||
uint32_t scratch145; /* _SCRATCH145_0, 0x764 */
|
||||
uint32_t scratch146; /* _SCRATCH146_0, 0x768 */
|
||||
uint32_t scratch147; /* _SCRATCH147_0, 0x76c */
|
||||
uint32_t scratch148; /* _SCRATCH148_0, 0x770 */
|
||||
uint32_t scratch149; /* _SCRATCH149_0, 0x774 */
|
||||
uint32_t scratch150; /* _SCRATCH150_0, 0x778 */
|
||||
uint32_t scratch151; /* _SCRATCH151_0, 0x77c */
|
||||
uint32_t scratch152; /* _SCRATCH152_0, 0x780 */
|
||||
uint32_t scratch153; /* _SCRATCH153_0, 0x784 */
|
||||
uint32_t scratch154; /* _SCRATCH154_0, 0x788 */
|
||||
uint32_t scratch155; /* _SCRATCH155_0, 0x78c */
|
||||
uint32_t scratch156; /* _SCRATCH156_0, 0x790 */
|
||||
uint32_t scratch157; /* _SCRATCH157_0, 0x794 */
|
||||
uint32_t scratch158; /* _SCRATCH158_0, 0x798 */
|
||||
uint32_t scratch159; /* _SCRATCH159_0, 0x79c */
|
||||
uint32_t scratch160; /* _SCRATCH160_0, 0x7a0 */
|
||||
uint32_t scratch161; /* _SCRATCH161_0, 0x7a4 */
|
||||
uint32_t scratch162; /* _SCRATCH162_0, 0x7a8 */
|
||||
uint32_t scratch163; /* _SCRATCH163_0, 0x7ac */
|
||||
uint32_t scratch164; /* _SCRATCH164_0, 0x7b0 */
|
||||
uint32_t scratch165; /* _SCRATCH165_0, 0x7b4 */
|
||||
uint32_t scratch166; /* _SCRATCH166_0, 0x7b8 */
|
||||
uint32_t scratch167; /* _SCRATCH167_0, 0x7bc */
|
||||
uint32_t scratch168; /* _SCRATCH168_0, 0x7c0 */
|
||||
uint32_t scratch169; /* _SCRATCH169_0, 0x7c4 */
|
||||
uint32_t scratch170; /* _SCRATCH170_0, 0x7c8 */
|
||||
uint32_t scratch171; /* _SCRATCH171_0, 0x7cc */
|
||||
uint32_t scratch172; /* _SCRATCH172_0, 0x7d0 */
|
||||
uint32_t scratch173; /* _SCRATCH173_0, 0x7d4 */
|
||||
uint32_t scratch174; /* _SCRATCH174_0, 0x7d8 */
|
||||
uint32_t scratch175; /* _SCRATCH175_0, 0x7dc */
|
||||
uint32_t scratch176; /* _SCRATCH176_0, 0x7e0 */
|
||||
uint32_t scratch177; /* _SCRATCH177_0, 0x7e4 */
|
||||
uint32_t scratch178; /* _SCRATCH178_0, 0x7e8 */
|
||||
uint32_t scratch179; /* _SCRATCH179_0, 0x7ec */
|
||||
uint32_t scratch180; /* _SCRATCH180_0, 0x7f0 */
|
||||
uint32_t scratch181; /* _SCRATCH181_0, 0x7f4 */
|
||||
uint32_t scratch182; /* _SCRATCH182_0, 0x7f8 */
|
||||
uint32_t scratch183; /* _SCRATCH183_0, 0x7fc */
|
||||
uint32_t scratch184; /* _SCRATCH184_0, 0x800 */
|
||||
uint32_t scratch185; /* _SCRATCH185_0, 0x804 */
|
||||
uint32_t scratch186; /* _SCRATCH186_0, 0x808 */
|
||||
uint32_t scratch187; /* _SCRATCH187_0, 0x80c */
|
||||
uint32_t scratch188; /* _SCRATCH188_0, 0x810 */
|
||||
uint32_t scratch189; /* _SCRATCH189_0, 0x814 */
|
||||
uint32_t scratch190; /* _SCRATCH190_0, 0x818 */
|
||||
uint32_t scratch191; /* _SCRATCH191_0, 0x81c */
|
||||
uint32_t scratch192; /* _SCRATCH192_0, 0x820 */
|
||||
uint32_t scratch193; /* _SCRATCH193_0, 0x824 */
|
||||
uint32_t scratch194; /* _SCRATCH194_0, 0x828 */
|
||||
uint32_t scratch195; /* _SCRATCH195_0, 0x82c */
|
||||
uint32_t scratch196; /* _SCRATCH196_0, 0x830 */
|
||||
uint32_t scratch197; /* _SCRATCH197_0, 0x834 */
|
||||
uint32_t scratch198; /* _SCRATCH198_0, 0x838 */
|
||||
uint32_t scratch199; /* _SCRATCH199_0, 0x83c */
|
||||
uint32_t scratch200; /* _SCRATCH200_0, 0x840 */
|
||||
uint32_t scratch201; /* _SCRATCH201_0, 0x844 */
|
||||
uint32_t scratch202; /* _SCRATCH202_0, 0x848 */
|
||||
uint32_t scratch203; /* _SCRATCH203_0, 0x84c */
|
||||
uint32_t scratch204; /* _SCRATCH204_0, 0x850 */
|
||||
uint32_t scratch205; /* _SCRATCH205_0, 0x854 */
|
||||
uint32_t scratch206; /* _SCRATCH206_0, 0x858 */
|
||||
uint32_t scratch207; /* _SCRATCH207_0, 0x85c */
|
||||
uint32_t scratch208; /* _SCRATCH208_0, 0x860 */
|
||||
uint32_t scratch209; /* _SCRATCH209_0, 0x864 */
|
||||
uint32_t scratch210; /* _SCRATCH210_0, 0x868 */
|
||||
uint32_t scratch211; /* _SCRATCH211_0, 0x86c */
|
||||
uint32_t scratch212; /* _SCRATCH212_0, 0x870 */
|
||||
uint32_t scratch213; /* _SCRATCH213_0, 0x874 */
|
||||
uint32_t scratch214; /* _SCRATCH214_0, 0x878 */
|
||||
uint32_t scratch215; /* _SCRATCH215_0, 0x87c */
|
||||
uint32_t scratch216; /* _SCRATCH216_0, 0x880 */
|
||||
uint32_t scratch217; /* _SCRATCH217_0, 0x884 */
|
||||
uint32_t scratch218; /* _SCRATCH218_0, 0x888 */
|
||||
uint32_t scratch219; /* _SCRATCH219_0, 0x88c */
|
||||
uint32_t scratch220; /* _SCRATCH220_0, 0x890 */
|
||||
uint32_t scratch221; /* _SCRATCH221_0, 0x894 */
|
||||
uint32_t scratch222; /* _SCRATCH222_0, 0x898 */
|
||||
uint32_t scratch223; /* _SCRATCH223_0, 0x89c */
|
||||
uint32_t scratch224; /* _SCRATCH224_0, 0x8a0 */
|
||||
uint32_t scratch225; /* _SCRATCH225_0, 0x8a4 */
|
||||
uint32_t scratch226; /* _SCRATCH226_0, 0x8a8 */
|
||||
uint32_t scratch227; /* _SCRATCH227_0, 0x8ac */
|
||||
uint32_t scratch228; /* _SCRATCH228_0, 0x8b0 */
|
||||
uint32_t scratch229; /* _SCRATCH229_0, 0x8b4 */
|
||||
uint32_t scratch230; /* _SCRATCH230_0, 0x8b8 */
|
||||
uint32_t scratch231; /* _SCRATCH231_0, 0x8bc */
|
||||
uint32_t scratch232; /* _SCRATCH232_0, 0x8c0 */
|
||||
uint32_t scratch233; /* _SCRATCH233_0, 0x8c4 */
|
||||
uint32_t scratch234; /* _SCRATCH234_0, 0x8c8 */
|
||||
uint32_t scratch235; /* _SCRATCH235_0, 0x8cc */
|
||||
uint32_t scratch236; /* _SCRATCH236_0, 0x8d0 */
|
||||
uint32_t scratch237; /* _SCRATCH237_0, 0x8d4 */
|
||||
uint32_t scratch238; /* _SCRATCH238_0, 0x8d8 */
|
||||
uint32_t scratch239; /* _SCRATCH239_0, 0x8dc */
|
||||
uint32_t scratch240; /* _SCRATCH240_0, 0x8e0 */
|
||||
uint32_t scratch241; /* _SCRATCH241_0, 0x8e4 */
|
||||
uint32_t scratch242; /* _SCRATCH242_0, 0x8e8 */
|
||||
uint32_t scratch243; /* _SCRATCH243_0, 0x8ec */
|
||||
uint32_t scratch244; /* _SCRATCH244_0, 0x8f0 */
|
||||
uint32_t scratch245; /* _SCRATCH245_0, 0x8f4 */
|
||||
uint32_t scratch246; /* _SCRATCH246_0, 0x8f8 */
|
||||
uint32_t scratch247; /* _SCRATCH247_0, 0x8fc */
|
||||
uint32_t scratch248; /* _SCRATCH248_0, 0x900 */
|
||||
uint32_t scratch249; /* _SCRATCH249_0, 0x904 */
|
||||
uint32_t scratch250; /* _SCRATCH250_0, 0x908 */
|
||||
uint32_t scratch251; /* _SCRATCH251_0, 0x90c */
|
||||
uint32_t scratch252; /* _SCRATCH252_0, 0x910 */
|
||||
uint32_t scratch253; /* _SCRATCH253_0, 0x914 */
|
||||
uint32_t scratch254; /* _SCRATCH254_0, 0x918 */
|
||||
uint32_t scratch255; /* _SCRATCH255_0, 0x91c */
|
||||
uint32_t scratch256; /* _SCRATCH256_0, 0x920 */
|
||||
uint32_t scratch257; /* _SCRATCH257_0, 0x924 */
|
||||
uint32_t scratch258; /* _SCRATCH258_0, 0x928 */
|
||||
uint32_t scratch259; /* _SCRATCH259_0, 0x92c */
|
||||
uint32_t scratch260; /* _SCRATCH260_0, 0x930 */
|
||||
uint32_t scratch261; /* _SCRATCH261_0, 0x934 */
|
||||
uint32_t scratch262; /* _SCRATCH262_0, 0x938 */
|
||||
uint32_t scratch263; /* _SCRATCH263_0, 0x93c */
|
||||
uint32_t scratch264; /* _SCRATCH264_0, 0x940 */
|
||||
uint32_t scratch265; /* _SCRATCH265_0, 0x944 */
|
||||
uint32_t scratch266; /* _SCRATCH266_0, 0x948 */
|
||||
uint32_t scratch267; /* _SCRATCH267_0, 0x94c */
|
||||
uint32_t scratch268; /* _SCRATCH268_0, 0x950 */
|
||||
uint32_t scratch269; /* _SCRATCH269_0, 0x954 */
|
||||
uint32_t scratch270; /* _SCRATCH270_0, 0x958 */
|
||||
uint32_t scratch271; /* _SCRATCH271_0, 0x95c */
|
||||
uint32_t scratch272; /* _SCRATCH272_0, 0x960 */
|
||||
uint32_t scratch273; /* _SCRATCH273_0, 0x964 */
|
||||
uint32_t scratch274; /* _SCRATCH274_0, 0x968 */
|
||||
uint32_t scratch275; /* _SCRATCH275_0, 0x96c */
|
||||
uint32_t scratch276; /* _SCRATCH276_0, 0x970 */
|
||||
uint32_t scratch277; /* _SCRATCH277_0, 0x974 */
|
||||
uint32_t scratch278; /* _SCRATCH278_0, 0x978 */
|
||||
uint32_t scratch279; /* _SCRATCH279_0, 0x97c */
|
||||
uint32_t scratch280; /* _SCRATCH280_0, 0x980 */
|
||||
uint32_t scratch281; /* _SCRATCH281_0, 0x984 */
|
||||
uint32_t scratch282; /* _SCRATCH282_0, 0x988 */
|
||||
uint32_t scratch283; /* _SCRATCH283_0, 0x98c */
|
||||
uint32_t scratch284; /* _SCRATCH284_0, 0x990 */
|
||||
uint32_t scratch285; /* _SCRATCH285_0, 0x994 */
|
||||
uint32_t scratch286; /* _SCRATCH286_0, 0x998 */
|
||||
uint32_t scratch287; /* _SCRATCH287_0, 0x99c */
|
||||
uint32_t scratch288; /* _SCRATCH288_0, 0x9a0 */
|
||||
uint32_t scratch289; /* _SCRATCH289_0, 0x9a4 */
|
||||
uint32_t scratch290; /* _SCRATCH290_0, 0x9a8 */
|
||||
uint32_t scratch291; /* _SCRATCH291_0, 0x9ac */
|
||||
uint32_t scratch292; /* _SCRATCH292_0, 0x9b0 */
|
||||
uint32_t scratch293; /* _SCRATCH293_0, 0x9b4 */
|
||||
uint32_t scratch294; /* _SCRATCH294_0, 0x9b8 */
|
||||
uint32_t scratch295; /* _SCRATCH295_0, 0x9bc */
|
||||
uint32_t scratch296; /* _SCRATCH296_0, 0x9c0 */
|
||||
uint32_t scratch297; /* _SCRATCH297_0, 0x9c4 */
|
||||
uint32_t scratch298; /* _SCRATCH298_0, 0x9c8 */
|
||||
uint32_t scratch299; /* _SCRATCH299_0, 0x9cc */
|
||||
uint32_t _0x9d0[50];
|
||||
uint32_t secure_scratch80; /* _SECURE_SCRATCH80_0, 0xa98 */
|
||||
uint32_t secure_scratch81; /* _SECURE_SCRATCH81_0, 0xa9c */
|
||||
uint32_t secure_scratch82; /* _SECURE_SCRATCH82_0, 0xaa0 */
|
||||
uint32_t secure_scratch83; /* _SECURE_SCRATCH83_0, 0xaa4 */
|
||||
uint32_t secure_scratch84; /* _SECURE_SCRATCH84_0, 0xaa8 */
|
||||
uint32_t secure_scratch85; /* _SECURE_SCRATCH85_0, 0xaac */
|
||||
uint32_t secure_scratch86; /* _SECURE_SCRATCH86_0, 0xab0 */
|
||||
uint32_t secure_scratch87; /* _SECURE_SCRATCH87_0, 0xab4 */
|
||||
uint32_t secure_scratch88; /* _SECURE_SCRATCH88_0, 0xab8 */
|
||||
uint32_t secure_scratch89; /* _SECURE_SCRATCH89_0, 0xabc */
|
||||
uint32_t secure_scratch90; /* _SECURE_SCRATCH90_0, 0xac0 */
|
||||
uint32_t secure_scratch91; /* _SECURE_SCRATCH91_0, 0xac4 */
|
||||
uint32_t secure_scratch92; /* _SECURE_SCRATCH92_0, 0xac8 */
|
||||
uint32_t secure_scratch93; /* _SECURE_SCRATCH93_0, 0xacc */
|
||||
uint32_t secure_scratch94; /* _SECURE_SCRATCH94_0, 0xad0 */
|
||||
uint32_t secure_scratch95; /* _SECURE_SCRATCH95_0, 0xad4 */
|
||||
uint32_t secure_scratch96; /* _SECURE_SCRATCH96_0, 0xad8 */
|
||||
uint32_t secure_scratch97; /* _SECURE_SCRATCH97_0, 0xadc */
|
||||
uint32_t secure_scratch98; /* _SECURE_SCRATCH98_0, 0xae0 */
|
||||
uint32_t secure_scratch99; /* _SECURE_SCRATCH99_0, 0xae4 */
|
||||
uint32_t secure_scratch100; /* _SECURE_SCRATCH100_0, 0xae8 */
|
||||
uint32_t secure_scratch101; /* _SECURE_SCRATCH101_0, 0xaec */
|
||||
uint32_t secure_scratch102; /* _SECURE_SCRATCH102_0, 0xaf0 */
|
||||
uint32_t secure_scratch103; /* _SECURE_SCRATCH103_0, 0xaf4 */
|
||||
uint32_t secure_scratch104; /* _SECURE_SCRATCH104_0, 0xaf8 */
|
||||
uint32_t secure_scratch105; /* _SECURE_SCRATCH105_0, 0xafc */
|
||||
uint32_t secure_scratch106; /* _SECURE_SCRATCH106_0, 0xb00 */
|
||||
uint32_t secure_scratch107; /* _SECURE_SCRATCH107_0, 0xb04 */
|
||||
uint32_t secure_scratch108; /* _SECURE_SCRATCH108_0, 0xb08 */
|
||||
uint32_t secure_scratch109; /* _SECURE_SCRATCH109_0, 0xb0c */
|
||||
uint32_t secure_scratch110; /* _SECURE_SCRATCH110_0, 0xb10 */
|
||||
uint32_t secure_scratch111; /* _SECURE_SCRATCH111_0, 0xb14 */
|
||||
uint32_t secure_scratch112; /* _SECURE_SCRATCH112_0, 0xb18 */
|
||||
uint32_t secure_scratch113; /* _SECURE_SCRATCH113_0, 0xb1c */
|
||||
uint32_t secure_scratch114; /* _SECURE_SCRATCH114_0, 0xb20 */
|
||||
uint32_t secure_scratch115; /* _SECURE_SCRATCH115_0, 0xb24 */
|
||||
uint32_t secure_scratch116; /* _SECURE_SCRATCH116_0, 0xb28 */
|
||||
uint32_t secure_scratch117; /* _SECURE_SCRATCH117_0, 0xb2c */
|
||||
uint32_t secure_scratch118; /* _SECURE_SCRATCH118_0, 0xb30 */
|
||||
uint32_t secure_scratch119; /* _SECURE_SCRATCH119_0, 0xb34 */
|
||||
uint32_t secure_scratch120; /* _SECURE_SCRATCH120_0, 0xb38 */
|
||||
uint32_t secure_scratch121; /* _SECURE_SCRATCH121_0, 0xb3c */
|
||||
uint32_t secure_scratch122; /* _SECURE_SCRATCH122_0, 0xb40 */
|
||||
uint32_t secure_scratch123; /* _SECURE_SCRATCH123_0, 0xb44 */
|
||||
uint32_t led_breathing_ctrl; /* _LED_BREATHING_CTRL_0, 0xb48 */
|
||||
uint32_t led_breathing_counter0; /* _LED_BREATHING_COUNTER0_0, 0xb4c */
|
||||
uint32_t led_breathing_counter1; /* _LED_BREATHING_COUNTER1_0, 0xb50 */
|
||||
uint32_t led_breathing_counter2; /* _LED_BREATHING_COUNTER2_0, 0xb54 */
|
||||
uint32_t led_breathing_counter3; /* _LED_BREATHING_COUNTER3_0, 0xb58 */
|
||||
uint32_t led_breathing_status; /* _LED_BREATHING_STATUS_0, 0xb5c */
|
||||
uint32_t _0xb60[2];
|
||||
uint32_t secure_scratch124; /* _SECURE_SCRATCH124_0, 0xb68 */
|
||||
uint32_t secure_scratch125; /* _SECURE_SCRATCH125_0, 0xb6c */
|
||||
uint32_t secure_scratch126; /* _SECURE_SCRATCH126_0, 0xb70 */
|
||||
uint32_t secure_scratch127; /* _SECURE_SCRATCH127_0, 0xb74 */
|
||||
uint32_t secure_scratch128; /* _SECURE_SCRATCH128_0, 0xb78 */
|
||||
uint32_t secure_scratch129; /* _SECURE_SCRATCH129_0, 0xb7c */
|
||||
uint32_t secure_scratch130; /* _SECURE_SCRATCH130_0, 0xb80 */
|
||||
uint32_t secure_scratch131; /* _SECURE_SCRATCH131_0, 0xb84 */
|
||||
uint32_t secure_scratch132; /* _SECURE_SCRATCH132_0, 0xb88 */
|
||||
uint32_t secure_scratch133; /* _SECURE_SCRATCH133_0, 0xb8c */
|
||||
uint32_t secure_scratch134; /* _SECURE_SCRATCH134_0, 0xb90 */
|
||||
uint32_t secure_scratch135; /* _SECURE_SCRATCH135_0, 0xb94 */
|
||||
uint32_t secure_scratch136; /* _SECURE_SCRATCH136_0, 0xb98 */
|
||||
uint32_t secure_scratch137; /* _SECURE_SCRATCH137_0, 0xb9c */
|
||||
uint32_t secure_scratch138; /* _SECURE_SCRATCH138_0, 0xba0 */
|
||||
uint32_t secure_scratch139; /* _SECURE_SCRATCH139_0, 0xba4 */
|
||||
uint32_t _0xba8[2];
|
||||
uint32_t sec_disable_ns; /* _SEC_DISABLE_NS_0, 0xbb0 */
|
||||
uint32_t sec_disable2_ns; /* _SEC_DISABLE2_NS_0, 0xbb4 */
|
||||
uint32_t sec_disable3_ns; /* _SEC_DISABLE3_NS_0, 0xbb8 */
|
||||
uint32_t sec_disable4_ns; /* _SEC_DISABLE4_NS_0, 0xbbc */
|
||||
uint32_t sec_disable5_ns; /* _SEC_DISABLE5_NS_0, 0xbc0 */
|
||||
uint32_t sec_disable6_ns; /* _SEC_DISABLE6_NS_0, 0xbc4 */
|
||||
uint32_t sec_disable7_ns; /* _SEC_DISABLE7_NS_0, 0xbc8 */
|
||||
uint32_t sec_disable8_ns; /* _SEC_DISABLE8_NS_0, 0xbcc */
|
||||
uint32_t sec_disable9_ns; /* _SEC_DISABLE9_NS_0, 0xbd0 */
|
||||
uint32_t sec_disable10_ns; /* _SEC_DISABLE10_NS_0, 0xbd4 */
|
||||
uint32_t _0xbd8[4];
|
||||
uint32_t tzram_pwr_cntrl; /* _TZRAM_PWR_CNTRL_0, 0xbe8 */
|
||||
uint32_t tzram_sec_disable; /* _TZRAM_SEC_DISABLE_0, 0xbec */
|
||||
uint32_t tzram_non_sec_disable; /* _TZRAM_NON_SEC_DISABLE_0, 0xbf0 */
|
||||
} tegra_pmc_t;
|
||||
|
||||
static inline volatile tegra_pmc_t *pmc_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_pmc_t *)PMC_BASE;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_STAGE2_H
|
||||
#define FUSEE_STAGE2_H
|
||||
|
||||
#include "../../../fusee/common/log.h"
|
||||
|
||||
#define MTC_ARGV_ARGUMENT_STRUCT 0
|
||||
#define MTC_ARGC 1
|
||||
|
||||
typedef struct {
|
||||
ScreenLogLevel log_level;
|
||||
} stage2_mtc_args_t;
|
||||
|
||||
#endif
|
||||
@@ -1,70 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
.macro CLEAR_GPR_REG_ITER
|
||||
mov r\@, #0
|
||||
.endm
|
||||
|
||||
.section .text.start, "ax", %progbits
|
||||
.arm
|
||||
.align 5
|
||||
.global _start
|
||||
.type _start, %function
|
||||
_start:
|
||||
/* Switch to system mode, mask all interrupts, clear all flags */
|
||||
msr cpsr_cxsf, #0xDF
|
||||
|
||||
/* Backup current stack pointer. */
|
||||
mov r12, sp
|
||||
|
||||
/* Set the stack pointer */
|
||||
ldr sp, =__stack_top__
|
||||
mov fp, #0
|
||||
|
||||
/* Save context */
|
||||
push {r12, lr}
|
||||
|
||||
/* Call init. */
|
||||
bl __program_init
|
||||
|
||||
/* Set r0 to r12 to 0 (for debugging) & call main */
|
||||
.rept 13
|
||||
CLEAR_GPR_REG_ITER
|
||||
.endr
|
||||
ldr r0, =__program_argc
|
||||
ldr r1, =__program_argv
|
||||
ldr r0, [r0]
|
||||
ldr r1, [r1]
|
||||
bl main
|
||||
|
||||
/* Save result. */
|
||||
push {r0}
|
||||
|
||||
/* Exit manually. */
|
||||
bl __program_exit
|
||||
|
||||
/* Restore result. */
|
||||
pop {r0}
|
||||
|
||||
/* Restore context */
|
||||
pop {r12}
|
||||
pop {lr}
|
||||
|
||||
/* Restore previous stack pointer. */
|
||||
mov sp, r12
|
||||
|
||||
/* Return */
|
||||
bx lr
|
||||
@@ -1,94 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_TIMERS_H
|
||||
#define FUSEE_TIMERS_H
|
||||
|
||||
#include "utils.h"
|
||||
|
||||
#define TIMERS_BASE 0x60005000
|
||||
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
||||
|
||||
#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
|
||||
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
|
||||
#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0)
|
||||
#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4)
|
||||
|
||||
#define RTC_BASE 0x7000E000
|
||||
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
|
||||
|
||||
#define RTC_SECONDS MAKE_RTC_REG(0x08)
|
||||
#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
|
||||
#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
|
||||
|
||||
typedef struct {
|
||||
uint32_t CONFIG;
|
||||
uint32_t STATUS;
|
||||
uint32_t COMMAND;
|
||||
uint32_t PATTERN;
|
||||
} watchdog_timers_t;
|
||||
|
||||
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
||||
#define WDT_REBOOT_PATTERN 0xC45A
|
||||
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n)
|
||||
|
||||
void wait(uint32_t microseconds);
|
||||
|
||||
static inline uint32_t get_time_s(void) {
|
||||
return RTC_SECONDS;
|
||||
}
|
||||
|
||||
static inline uint32_t get_time_ms(void) {
|
||||
return (RTC_MILLI_SECONDS | (RTC_SHADOW_SECONDS << 10));
|
||||
}
|
||||
|
||||
static inline uint32_t get_time_us(void) {
|
||||
return TIMERUS_CNTR_1US_0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns the time in microseconds.
|
||||
*/
|
||||
static inline uint32_t get_time(void) {
|
||||
return get_time_us();
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns the number of microseconds that have passed since a given get_time().
|
||||
*/
|
||||
static inline uint32_t get_time_since(uint32_t base) {
|
||||
return get_time_us() - base;
|
||||
}
|
||||
|
||||
/**
|
||||
* Delays for a given number of microseconds.
|
||||
*/
|
||||
static inline void udelay(uint32_t usecs) {
|
||||
uint32_t start = get_time_us();
|
||||
while (get_time_us() - start < usecs);
|
||||
}
|
||||
|
||||
/**
|
||||
* Delays for a given number of milliseconds.
|
||||
*/
|
||||
static inline void mdelay(uint32_t msecs) {
|
||||
uint32_t start = get_time_ms();
|
||||
while (get_time_ms() - start < msecs);
|
||||
}
|
||||
|
||||
__attribute__ ((noreturn)) void watchdog_reboot(void);
|
||||
|
||||
#endif
|
||||
@@ -1,49 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdarg.h>
|
||||
#include "utils.h"
|
||||
#include "../../../fusee/common/display/video_fb.h"
|
||||
#include "../../../fusee/common/log.h"
|
||||
|
||||
__attribute__ ((noreturn)) void generic_panic(void) {
|
||||
while (true) {
|
||||
/* Lock. */
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((noreturn)) void fatal_error(const char *fmt, ...) {
|
||||
/* Forcefully initialize the screen if logging is disabled. */
|
||||
if (log_get_log_level() == SCREEN_LOG_LEVEL_NONE) {
|
||||
/* Zero-fill the framebuffer and register it as printk provider. */
|
||||
video_init((void *)0xC0000000);
|
||||
|
||||
/* Override the global logging level. */
|
||||
log_set_log_level(SCREEN_LOG_LEVEL_ERROR);
|
||||
}
|
||||
|
||||
/* Display fatal error. */
|
||||
va_list args;
|
||||
print(SCREEN_LOG_LEVEL_ERROR, "Fatal error: ");
|
||||
va_start(args, fmt);
|
||||
vprint(SCREEN_LOG_LEVEL_ERROR, fmt, args);
|
||||
va_end(args);
|
||||
|
||||
while (true) {
|
||||
/* Lock. */
|
||||
}
|
||||
}
|
||||
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_UTILS_H
|
||||
#define FUSEE_UTILS_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(n) (1u << (n))
|
||||
#define BITL(n) (1ull << (n))
|
||||
#define MASK(n) (BIT(n) - 1)
|
||||
#define MASKL(n) (BITL(n) - 1)
|
||||
#define MASK2(a,b) (MASK(a) & ~MASK(b))
|
||||
#define MASK2L(a,b) (MASKL(a) & ~MASKL(b))
|
||||
|
||||
#define MAKE_REG32(a) (*(volatile uint32_t *)(a))
|
||||
|
||||
#define ALIGN(m) __attribute__((aligned(m)))
|
||||
#define PACKED __attribute__((packed))
|
||||
|
||||
#define ALINLINE __attribute__((always_inline))
|
||||
#define NOINLINE __attribute__((noinline))
|
||||
|
||||
__attribute__((noreturn)) void generic_panic(void);
|
||||
__attribute__((noreturn)) void fatal_error(const char *fmt, ...);
|
||||
|
||||
#endif
|
||||
@@ -55,42 +55,6 @@ static int stage2_ini_handler(void *user, const char *section, const char *name,
|
||||
return 1;
|
||||
}
|
||||
|
||||
static bool run_mtc(const char *mtc_path, uintptr_t mtc_address) {
|
||||
FILINFO info;
|
||||
size_t size;
|
||||
|
||||
/* Check if the MTC binary is present. */
|
||||
if (f_stat(mtc_path, &info) != FR_OK) {
|
||||
print(SCREEN_LOG_LEVEL_WARNING, "Stage2's MTC binary not found!\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
size = (size_t)info.fsize;
|
||||
|
||||
/* Try to read the MTC binary. */
|
||||
if (read_from_file((void *)mtc_address, size, mtc_path) != size) {
|
||||
print(SCREEN_LOG_LEVEL_WARNING, "Failed to read stage2's MTC binary (%s)!\n", mtc_path);
|
||||
return false;
|
||||
}
|
||||
|
||||
ScreenLogLevel mtc_log_level = log_get_log_level();
|
||||
bool mtc_res = false;
|
||||
int mtc_argc = 1;
|
||||
char mtc_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE] = {0};
|
||||
stage2_mtc_args_t *mtc_args = (stage2_mtc_args_t *)mtc_arg_data;
|
||||
|
||||
/* Setup argument data. */
|
||||
memcpy(&mtc_args->log_level, &mtc_log_level, sizeof(mtc_log_level));
|
||||
|
||||
/* Run the MTC binary. */
|
||||
mtc_res = (((int (*)(int, void *))mtc_address)(mtc_argc, mtc_arg_data) == 0);
|
||||
|
||||
/* Cleanup right away. */
|
||||
memset((void *)mtc_address, 0, size);
|
||||
|
||||
return mtc_res;
|
||||
}
|
||||
|
||||
void load_stage2(const char *bct0) {
|
||||
stage2_config_t config = {0};
|
||||
FILINFO info;
|
||||
@@ -123,11 +87,6 @@ void load_stage2(const char *bct0) {
|
||||
print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " Load Address: 0x%08x\n", config.load_address);
|
||||
print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " Entrypoint: 0x%p\n", config.entrypoint);
|
||||
|
||||
/* Run the MTC binary. */
|
||||
if (!run_mtc(config.mtc_path, config.load_address)) {
|
||||
print(SCREEN_LOG_LEVEL_WARNING, "DRAM training failed! Continuing with untrained DRAM.\n");
|
||||
}
|
||||
|
||||
if (f_stat(config.path, &info) != FR_OK) {
|
||||
fatal_error("Failed to stat stage2 (%s)!\n", config.path);
|
||||
}
|
||||
|
||||
@@ -36,7 +36,7 @@ endef
|
||||
#---------------------------------------------------------------------------------
|
||||
TARGET := $(notdir $(CURDIR))
|
||||
BUILD := build
|
||||
SOURCES := src ../../fusee/common ../../fusee/common/display ../../fusee/common/fatfs ../../fusee/common/sdmmc
|
||||
SOURCES := src ../../fusee/common ../../fusee/common/display ../../fusee/common/fatfs ../../fusee/common/sdmmc src/mtc
|
||||
DATA := data
|
||||
INCLUDES := include ../../libraries/libvapours/include
|
||||
|
||||
|
||||
@@ -490,6 +490,15 @@ typedef struct {
|
||||
uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
|
||||
uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
|
||||
uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
|
||||
|
||||
uint32_t _0x748[(0x774-0x748) / sizeof(uint32_t)]; // TODO
|
||||
|
||||
uint32_t pllm_ss_cfg; /* _PLLM_SS_CFG_0, 0x744 */
|
||||
uint32_t pllm_ss_ctrl1; /* _PLLM_SS_CTRL1_0, 0x778 */
|
||||
uint32_t pllm_ss_ctrl2; /* _PLLM_SS_CTRL2_0, 0x77C */
|
||||
uint32_t pllmb_ss_cfg; /* _PLLMB_SS_CFG_0, 0x780 */
|
||||
uint32_t pllmb_ss_ctrl1; /* _PLLMB_SS_CTRL1_0, 0x784 */
|
||||
uint32_t pllmb_ss_ctrl2; /* _PLLMB_SS_CTRL2_0, 0x788 */
|
||||
} tegra_car_t;
|
||||
|
||||
static inline volatile tegra_car_t *car_get_regs(void) {
|
||||
|
||||
@@ -19,7 +19,7 @@
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FUSEE_EMC_H_
|
||||
#define FUSEE_EMC_H_
|
||||
|
||||
@@ -393,6 +393,7 @@
|
||||
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
|
||||
#define EMC_DIG_DLL_STATUS 0x2c4
|
||||
#define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15)
|
||||
#define EMC_DIG_DLL_STATUS_DLL_LOCK_B01 (1 << 2)
|
||||
#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17)
|
||||
#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0
|
||||
#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \
|
||||
@@ -1065,6 +1066,10 @@
|
||||
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16)
|
||||
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24)
|
||||
|
||||
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF_B01 (1 << 10)
|
||||
|
||||
|
||||
|
||||
#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
|
||||
#define EMC_PMACRO_BRICK_MAPPING_0 0xc80
|
||||
#define EMC_PMACRO_BRICK_MAPPING_1 0xc84
|
||||
@@ -1126,4 +1131,8 @@
|
||||
|
||||
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
|
||||
|
||||
// B01
|
||||
#define EMC_PMACRO_DLL_CFG_0 0x5E4
|
||||
#define EMC_PMACRO_DLL_CFG_1 0x5E8
|
||||
|
||||
#endif
|
||||
|
||||
@@ -34,6 +34,9 @@
|
||||
#include "../../../fusee/common/display/video_fb.h"
|
||||
#include "../../../fusee/common/sdmmc/sdmmc.h"
|
||||
#include "../../../fusee/common/log.h"
|
||||
#include "fuse.h"
|
||||
#include "mtc/mtc.h"
|
||||
#include "mtc/mtc_b01.h"
|
||||
|
||||
extern void (*__program_exit_callback)(int rc);
|
||||
|
||||
@@ -107,6 +110,9 @@ int main(int argc, void **argv) {
|
||||
/* Initialize the boot environment. */
|
||||
setup_env();
|
||||
|
||||
/* Train dram. */
|
||||
train_dram();
|
||||
|
||||
print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, u8"Welcome to Atmosphère Fusée Stage 2!\n");
|
||||
print(SCREEN_LOG_LEVEL_DEBUG, "Stage 2 executing from: %s\n", (const char *)argv[STAGE2_ARGV_PROGRAM_PATH]);
|
||||
|
||||
@@ -134,6 +140,11 @@ int main(int argc, void **argv) {
|
||||
/* Terminate the boot environment. */
|
||||
cleanup_env();
|
||||
|
||||
/* Restore dram if mariko. */
|
||||
if (fuse_get_soc_type() == 1) {
|
||||
restore_dram_mariko();
|
||||
}
|
||||
|
||||
/* Finish boot. */
|
||||
nxboot_finish(boot_memaddr);
|
||||
} else {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -17,10 +17,10 @@
|
||||
#include "mtc.h"
|
||||
#include "mtc_b01.h"
|
||||
#include "mtc_tables_b01.h"
|
||||
#include "car.h"
|
||||
#include "fuse.h"
|
||||
#include "timers.h"
|
||||
#include "../../../fusee/common/log.h"
|
||||
#include "../car.h"
|
||||
#include "../fuse.h"
|
||||
#include "../timers.h"
|
||||
#include "../../../../fusee/common/log.h"
|
||||
|
||||
/*
|
||||
* Macros.
|
||||
@@ -98,6 +98,8 @@ static uint32_t g_program_pllm_ret = 0;
|
||||
static uint32_t g_wrote_training_pattern = 0;
|
||||
static uint32_t g_fsp_for_next_freq = 0;
|
||||
|
||||
static bool g_trained_dram = false;
|
||||
|
||||
static uint32_t g_periodic_timmer_compensation_intermediates[9 * 0x10] = {};
|
||||
|
||||
/* Register read/write helpers. */
|
||||
@@ -4176,5 +4178,16 @@ void train_dram_mariko(void) {
|
||||
//print(SCREEN_LOG_LEVEL_DEBUG, "[MTC]: Switched\n");
|
||||
|
||||
//print(SCREEN_LOG_LEVEL_DEBUG, "[MTC]: Done!\n");
|
||||
|
||||
g_trained_dram = true;
|
||||
}
|
||||
}
|
||||
|
||||
void restore_dram_mariko(void) {
|
||||
if (g_trained_dram) {
|
||||
int32_t num_timing_tables = 0;
|
||||
tegra_b01_emc_timing_t *timing_tables = get_t210_b01_emc_dvfs_timing_table(&num_timing_tables);
|
||||
|
||||
dvfs(0, timing_tables[0].rate_khz, timing_tables[num_timing_tables - 1].rate_khz, timing_tables, num_timing_tables, OP_SWITCH);
|
||||
}
|
||||
}
|
||||
@@ -686,4 +686,6 @@ _Static_assert(sizeof(tegra_b01_emc_timing_t) == 0x10CC);
|
||||
|
||||
void train_dram_mariko(void);
|
||||
|
||||
void restore_dram_mariko(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -17,7 +17,7 @@
|
||||
|
||||
#define ATMOSPHERE_RELEASE_VERSION_MAJOR 0
|
||||
#define ATMOSPHERE_RELEASE_VERSION_MINOR 20
|
||||
#define ATMOSPHERE_RELEASE_VERSION_MICRO 0
|
||||
#define ATMOSPHERE_RELEASE_VERSION_MICRO 1
|
||||
|
||||
#define ATMOSPHERE_RELEASE_VERSION ATMOSPHERE_RELEASE_VERSION_MAJOR, ATMOSPHERE_RELEASE_VERSION_MINOR, ATMOSPHERE_RELEASE_VERSION_MICRO
|
||||
|
||||
|
||||
Reference in New Issue
Block a user