ams: bump version to 0.20.1

Nintendo's Mariko tables result in trained frequency of 1599999 instead of 1600000.

PCV checks for rate == 1600000 exactly, when doing EMC init.

Thus EMC init does not succeed if we are trained to 1600000.

PCV has a fudge factor of 1000 used in SetEmcDvfsFreq, but this is not used in InitEmcDvfs.

This failure means that PCV cannot change rate back to 204MHz before sleep, and then after
wake extremely degraded performance is observed.

Restoring DRAM to 204MHz before boot causes EMC init to succeed/fixes performance degradation.

.github/ISSUE_TEMPLATE/bug_report.md

@@ -49,6 +49,8 @@ X.X.X</br>
      - [ Ex: Kosmos' distribution of Atmosphère ]
 - Do you have additional kips or sysmodules you're loading:
 - Homebrew software installed: [ * ]
+- EmuMMC or SysNAND:
+  - [ If using an EmuMMC, include whether it's partition-based or file-based. ]
 
 ### Additional context?
 

.gitignore

@@ -79,9 +79,8 @@ dkms.conf
 *.nam
 *.til
 
-# KEYS file for sept-secondary.
+# Compiled python files.
 *.pyc
-sept/sept-secondary/KEYS.py
 
 .**/
 

Makefile

@@ -32,10 +32,7 @@ mesosphere: exosphere libraries
 troposphere: stratosphere
 	$(MAKE) -C troposphere all
 
-sept: exosphere
-	$(MAKE) -C sept all
-
-fusee: exosphere mesosphere stratosphere sept
+fusee: exosphere mesosphere stratosphere
 	$(MAKE) -C $@ all
 
 libraries:
@@ -43,6 +40,7 @@ libraries:
 
 clean:
 	$(MAKE) -C fusee clean
+	$(MAKE) -C emummc clean
 	rm -rf out
 
 dist-no-debug: all
@@ -60,7 +58,6 @@ dist-no-debug: all
 	rm -rf out
 	mkdir atmosphere-$(AMSVER)
 	mkdir atmosphere-$(AMSVER)/atmosphere
-	mkdir atmosphere-$(AMSVER)/sept
 	mkdir atmosphere-$(AMSVER)/switch
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/fatal_errors
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/config_templates
@@ -68,15 +65,7 @@ dist-no-debug: all
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/flags
 	touch atmosphere-$(AMSVER)/atmosphere/flags/clean_stratosphere_for_0.19.0.flag
 	cp fusee/fusee-primary/fusee-primary.bin atmosphere-$(AMSVER)/atmosphere/reboot_payload.bin
-	cp fusee/fusee-mtc/fusee-mtc.bin atmosphere-$(AMSVER)/atmosphere/fusee-mtc.bin
 	cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
-	cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/sept/payload.bin
-	cp sept/sept-primary/sept-primary.bin atmosphere-$(AMSVER)/sept/sept-primary.bin
-	cp sept/sept-secondary/sept-secondary.bin atmosphere-$(AMSVER)/sept/sept-secondary.bin
-	cp sept/sept-secondary/sept-secondary_00.enc atmosphere-$(AMSVER)/sept/sept-secondary_00.enc
-	cp sept/sept-secondary/sept-secondary_01.enc atmosphere-$(AMSVER)/sept/sept-secondary_01.enc
-	cp sept/sept-secondary/sept-secondary_dev_00.enc atmosphere-$(AMSVER)/sept/sept-secondary_dev_00.enc
-	cp sept/sept-secondary/sept-secondary_dev_01.enc atmosphere-$(AMSVER)/sept/sept-secondary_dev_01.enc
 	cp config_templates/BCT.ini atmosphere-$(AMSVER)/atmosphere/config_templates/BCT.ini
 	cp config_templates/override_config.ini atmosphere-$(AMSVER)/atmosphere/config_templates/override_config.ini
 	cp config_templates/system_settings.ini atmosphere-$(AMSVER)/atmosphere/config_templates/system_settings.ini
@@ -108,7 +97,6 @@ dist-no-debug: all
 	cp troposphere/daybreak/daybreak.nro atmosphere-$(AMSVER)/switch/daybreak.nro
 	cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER).zip ./*; cd ../;
 	cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
-	cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/sept/payload.bin
 	cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip ./*; cd ../;
 	rm -r atmosphere-$(AMSVER)
 	mkdir out
@@ -130,11 +118,7 @@ dist: dist-no-debug
 	rm -rf atmosphere-$(AMSVER)-debug
 	mkdir atmosphere-$(AMSVER)-debug
 	cp fusee/fusee-primary/fusee-primary.elf atmosphere-$(AMSVER)-debug/fusee-primary.elf
-	cp fusee/fusee-mtc/fusee-mtc.elf atmosphere-$(AMSVER)-debug/fusee-mtc.elf
 	cp fusee/fusee-secondary/fusee-secondary-experimental.elf atmosphere-$(AMSVER)-debug/fusee-secondary.elf
-	cp sept/sept-primary/sept-primary.elf atmosphere-$(AMSVER)-debug/sept-primary.elf
-	cp sept/sept-secondary/sept-secondary.elf atmosphere-$(AMSVER)-debug/sept-secondary.elf
-	cp sept/sept-secondary/key_derivation/key_derivation.elf atmosphere-$(AMSVER)-debug/sept-secondary-key-derivation.elf
 	cp exosphere/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/exosphere-loader-stub.elf
 	cp exosphere/program/program.elf atmosphere-$(AMSVER)-debug/exosphere-program.elf
 	cp exosphere/warmboot/warmboot.elf atmosphere-$(AMSVER)-debug/exosphere-warmboot.elf

docs/building.md

@@ -9,7 +9,7 @@ Building Atmosphère is a very straightforward process that relies almost exclus
 + [PyCryptodome](https://pypi.org/project/pycryptodome) (optional)
 
 ## Instructions
-1. Follow the guide located [here](https://devkitpro.org/wiki/Getting_Started) to install and configure all the tools necessary for the build process. 
+1. Follow the guide located [here](https://devkitpro.org/wiki/Getting_Started) to install and configure all the tools necessary for the build process.
 
 2. Install the following packages via (dkp-)pacman:
     + `switch-dev`
@@ -21,12 +21,4 @@ Building Atmosphère is a very straightforward process that relies almost exclus
 3. Install the following library via python's package manager `pip`, required by [exosphere](components/exosphere.md):
     + `lz4`
 
-4. (Optional) In order to build [sept](components/sept.md) the pycryptodome PyPi package is required, which can be installed by running `pip install pycryptodome` under the installed Python environment of your choice or by installing the complete zip package to support the `make dist` recipe. This is an optional step included for advanced users who have the ability to provide the necessary encryption/signing keys themselves.
-
-5. It is, instead, possible to build [sept](components/sept.md) by providing previously encrypted/signed binaries distributed by official Atmosphère release packages. In order to do so, export the following variables in your current environment:
-    + `SEPT_00_ENC_PATH` (must point to the `sept-secondary_00.enc` file)
-    + `SEPT_01_ENC_PATH` (must point to the `sept-secondary_01.enc` file)
-    + `SEPT_DEV_00_ENC_PATH` (must point to the `sept-secondary_dev_00.enc` file)
-    + `SEPT_DEV_01_ENC_PATH` (must point to the `sept-secondary_dev_01.enc` file)
-
-6. Finally, clone the Atmosphère repository and run `make` under its root directory.
+4. Finally, clone the Atmosphère repository and run `make` under its root directory.

docs/changelog.md

@@ -1,4 +1,74 @@
 # Changelog
+## 0.20.1
++ An issue was fixed that caused severely degraded performance after wake-from-sleep on Mariko hardware.
+  + This was due to Mariko MTC resulting in a frequency of 1599.999MHz instead of 1600MHz.
+  + Due to this off-by-one, Nintendo's EMC management code failed to initialize/take over, and after wake from sleep RAM would be in a strange state.
++ General system stability improvements to enhance the user's experience.
+## 0.20.0
++ DRAM training (MTC) was implemented for Mariko hardware, increasing RAM speed from 204MHz to 1600MHz.
+  + This significantly optimizes Mariko boot speed, cutting boot time roughly in half.
+  + Typical boot time reductions (measured as "select fusee" to "home menu visible"):
+    + Normal (Iowa): ~35 seconds -> ~18 seconds.
+    + Lite (Hoag): ~65 seconds -> ~30 seconds.
+  + NOTE: Work is being started on a re-written `fusee` component, with an eye specifically towards ensuring a good boot speed.
+    + With any luck, boot will be much much faster on all units (Mariko and Erista) in an upcoming release.
++ Sept was replaced, and deleted from the repository.
+  + Erista units now use a custom TSEC firmware to manage key derivation.
+    + For more details, contact SciresM#0524 on discord.
+  + This has a number of benefits, including:
+    + This greatly simplifies key derivation logic by making it consistent on all firmwares.
+      + Fusee no longer accesses/uses keyblobs at all, so units which have accidentally destroyed/lost keyblobs can boot without them.
+    + This greatly increases stability (sept was the biggest source of boot failures).
+    + This improves boot speed (sept rebooted multiple times, performed hardware init multiple times, and was generally very slow).
+    + Atmosphère build process is now much saner.
++ A number of improvements were made to the dmnt cheat engine.
+  + Cheats which take in a memory region operand may now use types "2" or "3" to perform accesses relative to the alias/aslr regions, respectively.
+  + Support was added for an "else" opcode in the cheat engine, to make writing certain conditional logic more natural.
+  + Support was added for a cheat orchestrator homebrew (like edizon) to detach from a cheat process/set the master cheat programmatically.
++ Daybreak now provides a warning when attempting to install a firmware newer than the highest version atmosphère knows it supports.
+  + To facilitate this, exosphere now exposes the supported HOS version via an extension ConfigItem.
++ A number of minor issues were fixed, including:
+  + Several mesosphere debug SVC implementations were updated to reflect the semantics of the latest kernel.
+  + Support was fixed for deriving BIS encryption keys on certain prototype hardware.
++ General system stability improvements to enhance the user's experience.
+## 0.19.5
++ Support was added for 12.1.0.
++ LayeredFS support was added for OpenDataStorageWithProgramIndex commands.
+  + Certain games using newer (7.0.0+ APIs) which include multiple programs under a single title previously could not be modified.
+  + These are now supported as normal, and LayeredFS should have 100% compatibility again.
++ A number of minor issues were fixed, including:
+  + The Reboot to Payload NRO was updated to allow the OS to save state prior to rebooting (thanks @AuroraWright)!
+  + An issue was fixed that could cause dns.mitm to fail when games requested resolution of an empty string.
+  + An issue was fixed that caused a memory leak in the erpt system module.
+    + This would eventually cause a system crash after ~540 reports were generated without rebooting.
++ A number of minor improvements were made to improve mesosphere's accuracy.
++ General system stability improvements to enhance the user's experience.
+## 0.19.4
++ Support was added for 12.0.3.
++ A number of minor issues were fixed, including:
+  + An issue was fixed that could cause heap memory corruption when allocation was highly contended.
+  + An issue was fixed that could cause sleep to fail under certain conditions.
+  + An issue was fixed that could cause a scheduler slow path to be taken more often than necessary.
++ General system stability improvements to enhance the user's experience.
+## 0.19.3
++ Support was added for 12.0.2.
++ A number of minor issues were fixed, including:
+  + An issue was fixed in dns.mitm that caused a crash when games attempted to resolve the IP address of nullptr.
+  + An issue was fixed in erpt that would cause an abort when booting without having ever booted stock previously.
+  + An issue was fixed in (file-based) emummc that caused an error on system format/downloading certain games.
++ General system stability improvements to enhance the user's experience.
+## 0.19.2
++ Atmosphère's components were further updated to reflect latest official behaviors as of 12.0.0.
+  + Notably, `erpt` was updated to implement the new forced shutdown detection feature.
+    + When a forced-shutdown occurs, an erpt_report will be generated and saved to the SD card on the next boot.
++ Atmosphere-libs was updated to use GCC 11 (latest devkitA64/devkitARM releases).
+  + Initial inspections show mild-to-moderate optimizer improvements in several important places (kernel is 0x3000 smaller).
+  + General system stability improvements to enhance the user's experience.
++ A number of minor issues were fixed, including:
+  + A bug was fixed that caused a black screen when attempting to boot firmware versions 2.0.0-4.1.0.
+  + A bug was fixed that caused sm to abort when at the session limit, rather than returning error codes.
+  + A bug was fixed that allowed for resource exhaustion on 12.0.0, under certain circumstances.
++ Several issues were fixed, and usability and stability were improved.
 ## 0.19.1
 + An issue was fixed that caused a fatal error when using official `migration` services to transfer data between consoles.
 + An issue was fixed in `ncm` that caused an error when the OS tried to enumerate installed SD card content.

docs/components/sept.md

@@ -1,14 +0,0 @@
-# sept
-Sept is a payload that facilitates booting Atmosphère when targeting firmware version 7.0.0+.
-
-It consists of a primary and a secondary payload.
-
-## sept-primary
-sept-primary is essentially a stand-in for Nintendo's package1ldr, on 7.0.0+. To use it, the caller (normally fusée-secondary) loads the sept-primary binary to `0x4003F000`, loads the 7.0.0+ TSEC firmware to `0x40010F00`, and loads a signed, encrypted payload to `0x40016FE0`.
-
-This signed, encrypted payload is normally sept-secondary.
-
-## sept-secondary
-sept-secondary is a payload that performs 7.0.0+ key derivation, and then chainloads to `sept/payload.bin`.
-
-It is normally stored encrypted/signed. Therefore, if one wishes to build sept-secondary instead of using release builds, one must bring their own keys.

docs/features/cheats.md

@@ -19,6 +19,8 @@ This behavior ensures that cheat codes are only loaded when the user would want
 
 In cases where `dmnt` has not activated the cheat manager, but the user wants to make it do so anyway, the cheat manager's service API provides a `ForceOpenCheatProcess` command that homebrew can use. This command will cause the cheat manager to try to force itself to attach to the process.
 
+In cases where `dmnt` has activated the cheat manager, but the user wants to use an alternate debugger, the cheat manager's service API provides a `ForceCloseCheatProcess` command that homebrew can use. This command will cause the cheat manager to detach itself from the process.
+
 By default, all cheat codes listed in the loaded .txt file will be toggled on. This is configurable by the user by editing the `atmosphere!dmnt_cheats_enabled_by_default` [system setting](configurations.md).
 
 Users may use homebrew programs to toggle cheats on and off at runtime via the cheat manager's service API.
@@ -40,30 +42,30 @@ The following provides documentation of the instruction format for the virtual m
 
 Typically, instruction type is encoded in the upper nybble of the first instruction u32.
 
-### Code Type 0: Store Static Value to Memory
-Code type 0 allows writing a static value to a memory address.
+### Code Type 0x0: Store Static Value to Memory
+Code type 0x0 allows writing a static value to a memory address.
 
 #### Encoding
 `0TMR00AA AAAAAAAA VVVVVVVV (VVVVVVVV)`
 
 + T: Width of memory write (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
++ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
 + R: Register to use as an offset from memory region base.
 + A: Immediate offset to use from memory region base.
 + V: Value to write.
 
 ---
 
-### Code Type 1: Begin Conditional Block
-Code type 1 performs a comparison of the contents of memory to a static value.
+### Code Type 0x1: Begin Conditional Block
+Code type 0x1 performs a comparison of the contents of memory to a static value.
 
-If the condition is not met, all instructions until the appropriate conditional block terminator are skipped.
+If the condition is not met, all instructions until the appropriate End or Else conditional block terminator are skipped.
 
 #### Encoding
 `1TMC00AA AAAAAAAA VVVVVVVV (VVVVVVVV)`
 
 + T: Width of memory write (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
++ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
 + C: Condition to use, see below.
 + A: Immediate offset to use from memory region base.
 + V: Value to compare to.
@@ -78,16 +80,20 @@ If the condition is not met, all instructions until the appropriate conditional
 
 ---
 
-### Code Type 2: End Conditional Block
-Code type 2 marks the end of a conditional block (started by Code Type 1 or Code Type 8).
+### Code Type 0x2: End Conditional Block
+Code type 0x2 marks the end of a conditional block (started by Code Type 0x1 or Code Type 0x8).
+
+When an Else is executed, all instructions until the appropriate End conditional block terminator are skipped.
 
 #### Encoding
-`20000000`
+`2X000000`
+
++ X: End type (0 = End, 1 = Else).
 
 ---
 
-### Code Type 3: Start/End Loop
-Code type 3 allows for iterating in a loop a fixed number of times.
+### Code Type 0x3: Start/End Loop
+Code type 0x3 allows for iterating in a loop a fixed number of times.
 
 #### Start Loop Encoding
 `300R0000 VVVVVVVV`
@@ -102,8 +108,8 @@ Code type 3 allows for iterating in a loop a fixed number of times.
 
 ---
 
-### Code Type 4: Load Register with Static Value
-Code type 4 allows setting a register to a constant value.
+### Code Type 0x4: Load Register with Static Value
+Code type 0x4 allows setting a register to a constant value.
 
 #### Encoding
 `400R0000 VVVVVVVV VVVVVVVV`
@@ -113,29 +119,28 @@ Code type 4 allows setting a register to a constant value.
 
 ---
 
-### Code Type 5: Load Register with Memory Value
-Code type 5 allows loading a value from memory into a register, either using a fixed address or by dereferencing the destination register.
+### Code Type 0x5: Load Register with Memory Value
+Code type 0x5 allows loading a value from memory into a register, either using a fixed address or by dereferencing the destination register.
 
 #### Load From Fixed Address Encoding
 `5TMR00AA AAAAAAAA`
 
 + T: Width of memory read (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
++ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
 + R: Register to load value into.
 + A: Immediate offset to use from memory region base.
 
 #### Load from Register Address Encoding
-`5TMR10AA AAAAAAAA`
+`5T0R10AA AAAAAAAA`
 
 + T: Width of memory read (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
-+ R: Register to load value into.
++ R: Register to load value into. (This register is also used as the base memory address).
 + A: Immediate offset to use from register R.
 
 ---
 
-### Code Type 6: Store Static Value to Register Memory Address
-Code type 6 allows writing a fixed value to a memory address specified by a register.
+### Code Type 0x6: Store Static Value to Register Memory Address
+Code type 0x6 allows writing a fixed value to a memory address specified by a register.
 
 #### Encoding
 `6T0RIor0 VVVVVVVV VVVVVVVV`
@@ -149,10 +154,10 @@ Code type 6 allows writing a fixed value to a memory address specified by a regi
 
 ---
 
-### Code Type 7: Legacy Arithmetic
-Code type 7 allows performing arithmetic on registers.
+### Code Type 0x7: Legacy Arithmetic
+Code type 0x7 allows performing arithmetic on registers.
 
-However, it has been deprecated by Code type 9, and is only kept for backwards compatibility.
+However, it has been deprecated by Code type 0x9, and is only kept for backwards compatibility.
 
 #### Encoding
 `7T0RC000 VVVVVVVV`
@@ -171,8 +176,8 @@ However, it has been deprecated by Code type 9, and is only kept for backwards c
 
 ---
 
-### Code Type 8: Begin Keypress Conditional Block
-Code type 8 enters or skips a conditional block based on whether a key combination is pressed.
+### Code Type 0x8: Begin Keypress Conditional Block
+Code type 0x8 enters or skips a conditional block based on whether a key combination is pressed.
 
 #### Encoding
 `8kkkkkkk`
@@ -213,8 +218,8 @@ Note: This is the direct output of `hidKeysDown()`.
 
 ---
 
-### Code Type 9: Perform Arithmetic
-Code type 9 allows performing arithmetic on registers.
+### Code Type 0x9: Perform Arithmetic
+Code type 0x9 allows performing arithmetic on registers.
 
 #### Register Arithmetic Encoding
 `9TCRS0s0`
@@ -248,8 +253,8 @@ Code type 9 allows performing arithmetic on registers.
 
 ---
 
-### Code Type 10: Store Register to Memory Address
-Code type 10 allows writing a register to memory.
+### Code Type 0xA: Store Register to Memory Address
+Code type 0xA allows writing a register to memory.
 
 #### Encoding
 `ATSRIOxa (aaaaaaaa)`
@@ -272,13 +277,13 @@ Code type 10 allows writing a register to memory.
 
 ---
 
-### Code Type 11: Reserved
-Code Type 11 is currently reserved for future use.
+### Code Type 0xB: Reserved
+Code Type 0xB is currently reserved for future use.
 
 ---
 
-### Code Type 12-15: Extended-Width Instruction
-Code Types 12-15 signal to the VM to treat the upper two nybbles of the first dword as instruction type, instead of just the upper nybble.
+### Code Type 0xC-0xF: Extended-Width Instruction
+Code Types 0xC-0xF signal to the VM to treat the upper two nybbles of the first dword as instruction type, instead of just the upper nybble.
 
 This reserves an additional 64 opcodes for future use.
 

docs/main.md

@@ -12,7 +12,6 @@ Atmosphère provides six core components, mimicking to some degree the various l
 
 Additionally, Atmosphère also provides the following secondary components:
 + [emummc](components/emummc.md)
-+ [sept](components/sept.md)
 + [libraries](components/libraries.md)
 
 ## Features

emummc/.gitrepo

@@ -6,7 +6,7 @@
 [subrepo]
 	remote = https://github.com/m4xw/emuMMC
 	branch = develop
-	commit = b355ee6a8f376faa615785419c7d73a8814d9d65
-	parent = b24784f5c13a142bd0cb5d7edb82691c71f4bd00
+	commit = cbc294c390ed73bb281bc1028a8899c053427112
+	parent = 38f9a76ba028995ed3274da3a45b0254f09d1f59
 	method = rebase
 	cmdver = 0.4.1

emummc/Makefile

@@ -32,7 +32,7 @@ CFLAGS	+=	$(INCLUDE) -D__SWITCH__
 CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++17
 
 ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(DEVKITPRO)/libnx/switch.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
+LDFLAGS	=	-specs=$(EMUMMCDIR)/emummc.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
 
 ifneq ($(BUILD),$(notdir $(CURDIR)))
 

emummc/emummc.ld

@@ -0,0 +1,201 @@
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+
+PHDRS
+{
+	code   PT_LOAD FLAGS(5) /* Read | Execute */;
+	rodata PT_LOAD FLAGS(4) /* Read */;
+	data   PT_LOAD FLAGS(6) /* Read | Write */;
+	dyn    PT_DYNAMIC;
+}
+
+SECTIONS
+{
+	/* =========== CODE section =========== */
+	PROVIDE(__start__ = 0x0);
+	. = __start__;
+	__code_start = . ;
+
+	.crt0 :
+	{
+		KEEP (*(.crt0))
+		. = ALIGN(8);
+	} :code
+
+	.init :
+	{
+		KEEP( *(.init) )
+		. = ALIGN(8);
+	} :code
+
+	.plt :
+	{
+		*(.plt)
+		*(.iplt)
+		. = ALIGN(8);
+	} :code
+
+	.text :
+	{
+		*(.text.unlikely .text.*_unlikely .text.unlikely.*)
+		*(.text.exit .text.exit.*)
+		*(.text.startup .text.startup.*)
+		*(.text.hot .text.hot.*)
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		. = ALIGN(8);
+	} :code
+
+	.fini :
+	{
+		KEEP( *(.fini) )
+		. = ALIGN(8);
+	} :code
+
+	/* =========== RODATA section =========== */
+	. = ALIGN(0x1000);
+	__rodata_start = . ;
+
+	.nx-module-name : { KEEP (*(.nx-module-name)) } :rodata
+
+	.rodata :
+	{
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		. = ALIGN(8);
+	} :rodata
+
+	.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } :rodata
+	.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata
+	.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata
+	.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata
+
+	.dynamic           : { *(.dynamic) } :rodata :dyn
+	.dynsym            : { *(.dynsym) } :rodata
+	.dynstr            : { *(.dynstr) } :rodata
+	.rela.dyn          : { *(.rela.*) } :rodata
+	.interp            : { *(.interp) } :rodata
+	.hash              : { *(.hash) } :rodata
+	.gnu.hash          : { *(.gnu.hash) } :rodata
+	.gnu.version       : { *(.gnu.version) } :rodata
+	.gnu.version_d     : { *(.gnu.version_d) } :rodata
+	.gnu.version_r     : { *(.gnu.version_r) } :rodata
+	.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata
+
+	/* =========== DATA section =========== */
+	. = ALIGN(0x1000);
+	__data_start = . ;
+
+	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data
+	.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data
+	.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data
+	.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data
+
+	.tdata ALIGN(8) :
+	{
+		__tdata_lma = .;
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		. = ALIGN(8);
+		__tdata_lma_end = .;
+	} :data
+
+	.tbss ALIGN(8) :
+	{
+		*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+		. = ALIGN(8);
+	} :data
+
+	.preinit_array ALIGN(8) :
+	{
+		PROVIDE (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE (__preinit_array_end = .);
+	} :data
+
+	.init_array ALIGN(8) :
+	{
+		PROVIDE (__init_array_start = .);
+		KEEP( *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) )
+		KEEP( *(.init_array .ctors) )
+		PROVIDE (__init_array_end = .);
+	} :data
+
+	.fini_array ALIGN(8) :
+	{
+		PROVIDE (__fini_array_start = .);
+		KEEP( *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) )
+		KEEP( *(.fini_array .dtors) )
+		PROVIDE (__fini_array_end = .);
+	} :data
+
+	__got_start__ = .;
+
+	.got            : { *(.got) *(.igot) } :data
+	.got.plt        : { *(.got.plt)  *(.igot.plt) } :data
+
+	__got_end__ = .;
+
+	.data ALIGN(8) :
+	{
+		*(.data .data.* .gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+	} :data
+
+	__bss_start__ = .;
+	.bss ALIGN(8) :
+	{
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(8);
+
+		/* Reserve space for the TLS segment of the main thread */
+		__tls_start = .;
+		. += + SIZEOF(.tdata) + SIZEOF(.tbss);
+		__tls_end = .;
+	} : data
+	__bss_end__ = .;
+
+	__end__ = ABSOLUTE(.) ;
+
+	. = ALIGN(0x1000);
+	__argdata__ = ABSOLUTE(.) ;
+
+	/* ==================
+	   ==== Metadata ====
+	   ================== */
+
+	/* Discard sections that difficult post-processing */
+	/DISCARD/ : { *(.group .comment .note) }
+
+	/* Stabs debugging sections. */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0. */
+
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+}

emummc/emummc.specs

@@ -0,0 +1,8 @@
+%rename link                old_link
+
+*link:
+%(old_link) -T %:getenv(TOPDIR /emummc.ld) -pie --no-dynamic-linker --spare-dynamic-tags=0 --gc-sections -z text -z nodynamic-undefined-weak --build-id=sha1 --nx-module-name
+
+*startfile:
+crti%O%s crtbegin%O%s
+

emummc/source/FS/FS_offsets.c

@@ -53,6 +53,8 @@
 #include "offsets/1100_exfat.h"
 #include "offsets/1200.h"
 #include "offsets/1200_exfat.h"
+#include "offsets/1203.h"
+#include "offsets/1203_exfat.h"
 #include "../utils/fatal.h"
 
 #define GET_OFFSET_STRUCT_NAME(vers) g_offsets##vers
@@ -117,6 +119,8 @@ DEFINE_OFFSET_STRUCT(_1100);
 DEFINE_OFFSET_STRUCT(_1100_EXFAT);
 DEFINE_OFFSET_STRUCT(_1200);
 DEFINE_OFFSET_STRUCT(_1200_EXFAT);
+DEFINE_OFFSET_STRUCT(_1203);
+DEFINE_OFFSET_STRUCT(_1203_EXFAT);
 
 const fs_offsets_t *get_fs_offsets(enum FS_VER version) {
     switch (version) {
@@ -194,6 +198,10 @@ const fs_offsets_t *get_fs_offsets(enum FS_VER version) {
             return &(GET_OFFSET_STRUCT_NAME(_1200));
         case FS_VER_12_0_0_EXFAT:
             return &(GET_OFFSET_STRUCT_NAME(_1200_EXFAT));
+        case FS_VER_12_0_3:
+            return &(GET_OFFSET_STRUCT_NAME(_1203));
+        case FS_VER_12_0_3_EXFAT:
+            return &(GET_OFFSET_STRUCT_NAME(_1203_EXFAT));
         default:
             fatal_abort(Fatal_UnknownVersion);
     }

emummc/source/FS/FS_versions.h

@@ -77,6 +77,9 @@ enum FS_VER
     FS_VER_12_0_0,
     FS_VER_12_0_0_EXFAT,
 
+    FS_VER_12_0_3,
+    FS_VER_12_0_3_EXFAT,
+
     FS_VER_MAX,
 };
 

emummc/source/FS/offsets/1203.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 m4xw <m4x@m4xw.net>
+ * Copyright (c) 2019 Atmosphere-NX
+ * Copyright (c) 2021 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __FS_1203_H__
+#define __FS_1203_H__
+
+// Accessor vtable getters
+#define FS_OFFSET_1203_SDMMC_ACCESSOR_GC   0x1550E0
+#define FS_OFFSET_1203_SDMMC_ACCESSOR_SD   0x156EF0
+#define FS_OFFSET_1203_SDMMC_ACCESSOR_NAND 0x155610
+
+// Hooks
+#define FS_OFFSET_1203_SDMMC_WRAPPER_READ  0x150A80
+#define FS_OFFSET_1203_SDMMC_WRAPPER_WRITE 0x150B40
+#define FS_OFFSET_1203_RTLD                0x688
+#define FS_OFFSET_1203_RTLD_DESTINATION    ((uintptr_t)(INT64_C(-0x3C)))
+
+#define FS_OFFSET_1203_CLKRST_SET_MIN_V_CLK_RATE 0x14FDD0
+
+// Misc funcs
+#define FS_OFFSET_1203_LOCK_MUTEX          0x29350
+#define FS_OFFSET_1203_UNLOCK_MUTEX        0x293A0
+
+#define FS_OFFSET_1203_SDMMC_WRAPPER_CONTROLLER_OPEN  0x150960
+#define FS_OFFSET_1203_SDMMC_WRAPPER_CONTROLLER_CLOSE 0x1509F0
+
+// Misc Data
+#define FS_OFFSET_1203_SD_MUTEX            0xE3D3E8
+#define FS_OFFSET_1203_NAND_MUTEX          0xE38768
+#define FS_OFFSET_1203_ACTIVE_PARTITION    0xE387A8
+#define FS_OFFSET_1203_SDMMC_DAS_HANDLE    0xE20DB0
+
+// NOPs
+#define FS_OFFSET_1203_SD_DAS_INIT         0x27244
+
+// Nintendo Paths
+#define FS_OFFSET_1203_NINTENDO_PATHS \
+{ \
+	{.opcode_reg = 3, .adrp_offset = 0x0006E920, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 3, .adrp_offset = 0x0007AFD0, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 4, .adrp_offset = 0x00081364, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 4, .adrp_offset = 0x00092960, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 0, .adrp_offset = 0, .add_rel_offset = 0}, \
+}
+
+#endif // __FS_1203_H__

emummc/source/FS/offsets/1203_exfat.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 m4xw <m4x@m4xw.net>
+ * Copyright (c) 2019 Atmosphere-NX
+ * Copyright (c) 2021 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __FS_1203_EXFAT_H__
+#define __FS_1203_EXFAT_H__
+
+// Accessor vtable getters
+#define FS_OFFSET_1203_EXFAT_SDMMC_ACCESSOR_GC   0x1550E0
+#define FS_OFFSET_1203_EXFAT_SDMMC_ACCESSOR_SD   0x156EF0
+#define FS_OFFSET_1203_EXFAT_SDMMC_ACCESSOR_NAND 0x155610
+
+// Hooks
+#define FS_OFFSET_1203_EXFAT_SDMMC_WRAPPER_READ  0x150A80
+#define FS_OFFSET_1203_EXFAT_SDMMC_WRAPPER_WRITE 0x150B40
+#define FS_OFFSET_1203_EXFAT_RTLD                0x688
+#define FS_OFFSET_1203_EXFAT_RTLD_DESTINATION    ((uintptr_t)(INT64_C(-0x3C)))
+
+#define FS_OFFSET_1203_EXFAT_CLKRST_SET_MIN_V_CLK_RATE 0x14FDD0
+
+// Misc funcs
+#define FS_OFFSET_1203_EXFAT_LOCK_MUTEX          0x29350
+#define FS_OFFSET_1203_EXFAT_UNLOCK_MUTEX        0x293A0
+
+#define FS_OFFSET_1203_EXFAT_SDMMC_WRAPPER_CONTROLLER_OPEN  0x150960
+#define FS_OFFSET_1203_EXFAT_SDMMC_WRAPPER_CONTROLLER_CLOSE 0x1509F0
+
+// Misc Data
+#define FS_OFFSET_1203_EXFAT_SD_MUTEX            0xE4B3E8
+#define FS_OFFSET_1203_EXFAT_NAND_MUTEX          0xE46768
+#define FS_OFFSET_1203_EXFAT_ACTIVE_PARTITION    0xE467A8
+#define FS_OFFSET_1203_EXFAT_SDMMC_DAS_HANDLE    0xE2EDB0
+
+// NOPs
+#define FS_OFFSET_1203_EXFAT_SD_DAS_INIT         0x27244
+
+// Nintendo Paths
+#define FS_OFFSET_1203_EXFAT_NINTENDO_PATHS \
+{ \
+	{.opcode_reg = 3, .adrp_offset = 0x0006E920, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 3, .adrp_offset = 0x0007AFD0, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 4, .adrp_offset = 0x00081364, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 4, .adrp_offset = 0x00092960, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 0, .adrp_offset = 0, .add_rel_offset = 0}, \
+}
+
+#endif // __FS_1203_EXFAT_H__

emummc/source/emuMMC/emummc.c

@@ -292,6 +292,36 @@ static uint64_t emummc_read_write_inner(void *buf, unsigned int sector, unsigned
         {
             fp = &f_emu.fp_gpp[sector / f_emu.part_size];
             sector = sector % f_emu.part_size;
+
+            // Special handling for reads/writes which cross file-boundaries.
+            if (__builtin_expect(sector + num_sectors > f_emu.part_size, 0))
+            {
+                unsigned int remaining = num_sectors;
+                while (remaining > 0) {
+                    const unsigned int cur_sectors = MIN(remaining, f_emu.part_size - sector);
+
+                    if (f_lseek(fp, (u64)sector << 9) != FR_OK)
+                        return 0; // Out of bounds.
+
+                    if (is_write)
+                    {
+                        if (f_write_fast(fp, buf, (u64)cur_sectors << 9) != FR_OK)
+                            return 0;
+                    }
+                    else
+                    {
+                        if (f_read_fast(fp, buf, (u64)cur_sectors << 9) != FR_OK)
+                            return 0;
+                    }
+
+                    buf = (char *)buf + ((u64)cur_sectors << 9);
+                    remaining -= cur_sectors;
+                    sector = 0;
+                    ++fp;
+                }
+
+                return 1;
+            }
         }
         else
         {
@@ -306,14 +336,14 @@ static uint64_t emummc_read_write_inner(void *buf, unsigned int sector, unsigned
         break;
     }
 
-    if (f_lseek(fp, sector << 9) != FR_OK)
+    if (f_lseek(fp, (u64)sector << 9) != FR_OK)
         return 0; // Out of bounds.
 
     uint64_t res = 0;
     if (!is_write)
-        res = !f_read_fast(fp, buf, num_sectors << 9);
+        res = !f_read_fast(fp, buf, (u64)num_sectors << 9);
     else
-        res = !f_write_fast(fp, buf, num_sectors << 9);
+        res = !f_write_fast(fp, buf, (u64)num_sectors << 9);
 
     return res;
 }

exosphere/loader_stub/loader_stub.specs

@@ -1,7 +1,4 @@
 %rename link old_link
 
 *link:
-%(old_link) -T %:getenv(TOPDIR /loader_stub.ld) --gc-sections --nmagic -nostdlib -nostartfiles
-
-*startfile:
-crti%O%s crtbegin%O%s
+%(old_link) -T %:getenv(TOPDIR /loader_stub.ld) --gc-sections --nmagic

exosphere/loader_stub/source/secmon_loader_main.cpp

@@ -20,13 +20,13 @@
 
 namespace ams::secmon::loader {
 
-    NORETURN void UncompressAndExecute() {
+    NORETURN void UncompressAndExecute(const void *program, const void *boot_code) {
         /* Uncompress the program image. */
-        Uncompress(secmon::MemoryRegionPhysicalTzramFullProgramImage.GetPointer(), secmon::MemoryRegionPhysicalTzramFullProgramImage.GetSize(), program_lz4, program_lz4_size);
+        Uncompress(secmon::MemoryRegionPhysicalTzramFullProgramImage.GetPointer(), secmon::MemoryRegionPhysicalTzramFullProgramImage.GetSize(), program, program_lz4_size);
 
         /* Copy the boot image to the end of IRAM */
         u8 *relocated_boot_code = secmon::MemoryRegionPhysicalIramBootCodeImage.GetEndPointer<u8>() - boot_code_lz4_size;
-        std::memcpy(relocated_boot_code, boot_code_lz4, boot_code_lz4_size);
+        std::memcpy(relocated_boot_code, boot_code, boot_code_lz4_size);
 
         /* Uncompress the boot image. */
         Uncompress(secmon::MemoryRegionPhysicalIramBootCodeImage.GetPointer(), secmon::MemoryRegionPhysicalIramBootCodeImage.GetSize(), relocated_boot_code, boot_code_lz4_size);

exosphere/loader_stub/source/start.s

@@ -98,8 +98,8 @@ _start:
     ldr x20, =0x7C020000
     mov sp, x20
 
-    /* Call our init array functions. */
-    bl __libc_init_array
+    adr x0, program_lz4
+    adr x1, boot_code_lz4
 
     /* Uncompress the program and iram boot code images. */
-    b _ZN3ams6secmon6loader20UncompressAndExecuteEv
+    b _ZN3ams6secmon6loader20UncompressAndExecuteEPKvS3_

exosphere/mariko_fatal/mariko_fatal.specs

@@ -1,7 +1,4 @@
 %rename link old_link
 
 *link:
-%(old_link) -T %:getenv(TOPDIR /mariko_fatal.ld) --gc-sections --nmagic -nostdlib -nostartfiles
-
-*startfile:
-crti%O%s crtbegin%O%s
+%(old_link) -T %:getenv(TOPDIR /mariko_fatal.ld) --gc-sections --nmagic

exosphere/program/program.specs

@@ -1,4 +1,4 @@
 %rename link old_link
 
 *link:
-%(old_link) -T %:getenv(TOPDIR /program.ld) --gc-sections --nmagic -nostdlib -nostartfiles
+%(old_link) -T %:getenv(TOPDIR /program.ld) --gc-sections --nmagic

exosphere/program/rebootstub/rebootstub.specs

@@ -1,7 +1,4 @@
 %rename link old_link
 
 *link:
-%(old_link) -T %:getenv(TOPDIR /rebootstub.ld) --gc-sections --nmagic -nostdlib -nostartfiles
-
-*startfile:
-crti%O%s crtbegin%O%s
+%(old_link) -T %:getenv(TOPDIR /rebootstub.ld) --gc-sections --nmagic

exosphere/program/sc7fw/sc7fw.specs

@@ -1,7 +1,4 @@
 %rename link old_link
 
 *link:
-%(old_link) -T %:getenv(TOPDIR /sc7fw.ld) --gc-sections --nmagic -nostdlib -nostartfiles
-
-*startfile:
-crti%O%s crtbegin%O%s
+%(old_link) -T %:getenv(TOPDIR /sc7fw.ld) --gc-sections --nmagic

exosphere/program/source/boot/secmon_boot_key_data.s

@@ -85,10 +85,10 @@ _ZN3ams6secmon4boot15VolatileKeyDataE:
 /* We can get away with only including latest because exosphere supports newer-than-expected master key in engine. */
 /* TODO: Update on next change of keys. */
 /* Mariko Development Master Kek Source. */
-.byte 0xF9, 0x37, 0xCF, 0x9A, 0xBD, 0x86, 0xBB, 0xA9, 0x9C, 0x9E, 0x03, 0xC4, 0xFC, 0xBC, 0x3B, 0xCE
+.byte 0x75, 0x2D, 0x2E, 0xF3, 0x2F, 0x3F, 0xFE, 0x65, 0xF4, 0xA9, 0x83, 0xB4, 0xED, 0x42, 0x63, 0xBA
 
 /* Mariko Production Master Kek Source. */
-.byte 0x0E, 0x44, 0x0C, 0xED, 0xB4, 0x36, 0xC0, 0x3F, 0xAA, 0x1D, 0xAE, 0xBF, 0x62, 0xB1, 0x09, 0x82
+.byte 0xE5, 0x41, 0xAC, 0xEC, 0xD1, 0xA7, 0xD1, 0xAB, 0xED, 0x03, 0x77, 0xF1, 0x27, 0xCA, 0xF8, 0xF1
 
 /* Development Master Key Vectors. */
 .byte 0x46, 0x22, 0xB4, 0x51, 0x9A, 0x7E, 0xA7, 0x7F, 0x62, 0xA1, 0x1F, 0x8F, 0xC5, 0x3A, 0xDB, 0xFE /* Zeroes encrypted with Master Key 00. */
@@ -102,6 +102,7 @@ _ZN3ams6secmon4boot15VolatileKeyDataE:
 .byte 0xEC, 0xE1, 0x46, 0x89, 0x37, 0xFD, 0xD2, 0x15, 0x8C, 0x3F, 0x24, 0x82, 0xEF, 0x49, 0x68, 0x04 /* Master key 07 encrypted with Master key 08. */
 .byte 0x43, 0x3D, 0xC5, 0x3B, 0xEF, 0x91, 0x02, 0x21, 0x61, 0x54, 0x63, 0x8A, 0x35, 0xE7, 0xCA, 0xEE /* Master key 08 encrypted with Master key 09. */
 .byte 0x6C, 0x2E, 0xCD, 0xB3, 0x34, 0x61, 0x77, 0xF5, 0xF9, 0xB1, 0xDD, 0x61, 0x98, 0x19, 0x3E, 0xD4 /* Master key 09 encrypted with Master key 0A. */
+.byte 0x21, 0x88, 0x6B, 0x10, 0x9E, 0x83, 0xD6, 0x52, 0xAB, 0x08, 0xDB, 0x6D, 0x39, 0xFF, 0x1C, 0x9C /* Master key 0A encrypted with Master key 0B. */
 
 /* Production Master Key Vectors. */
 .byte 0x0C, 0xF0, 0x59, 0xAC, 0x85, 0xF6, 0x26, 0x65, 0xE1, 0xE9, 0x19, 0x55, 0xE6, 0xF2, 0x67, 0x3D /* Zeroes encrypted with Master Key 00. */
@@ -115,33 +116,37 @@ _ZN3ams6secmon4boot15VolatileKeyDataE:
 .byte 0xEA, 0x60, 0xB3, 0xEA, 0xCE, 0x8F, 0x24, 0x46, 0x7D, 0x33, 0x9C, 0xD1, 0xBC, 0x24, 0x98, 0x29 /* Master key 07 encrypted with Master key 08. */
 .byte 0x4D, 0xD9, 0x98, 0x42, 0x45, 0x0D, 0xB1, 0x3C, 0x52, 0x0C, 0x9A, 0x44, 0xBB, 0xAD, 0xAF, 0x80 /* Master key 08 encrypted with Master key 09. */
 .byte 0xB8, 0x96, 0x9E, 0x4A, 0x00, 0x0D, 0xD6, 0x28, 0xB3, 0xD1, 0xDB, 0x68, 0x5F, 0xFB, 0xE1, 0x2A /* Master key 09 encrypted with Master key 0A. */
+.byte 0xC1, 0x8D, 0x16, 0xBB, 0x2A, 0xE4, 0x1D, 0xD4, 0xC2, 0xC1, 0xB6, 0x40, 0x94, 0x35, 0x63, 0x98 /* Master key 0A encrypted with Master key 0B. */
 
 /* Device Master Key Source Sources. */
-.byte 0x8B, 0x4E, 0x1C, 0x22, 0x42, 0x07, 0xC8, 0x73, 0x56, 0x94, 0x08, 0x8B, 0xCC, 0x47, 0x0F, 0x5D /* 4.0.0 Device Master Key Source Source. */
-.byte 0x6C, 0xEF, 0xC6, 0x27, 0x8B, 0xEC, 0x8A, 0x91, 0x99, 0xAB, 0x24, 0xAC, 0x4F, 0x1C, 0x8F, 0x1C /* 5.0.0 Device Master Key Source Source. */
-.byte 0x70, 0x08, 0x1B, 0x97, 0x44, 0x64, 0xF8, 0x91, 0x54, 0x9D, 0xC6, 0x84, 0x8F, 0x1A, 0xB2, 0xE4 /* 6.0.0 Device Master Key Source Source. */
-.byte 0x8E, 0x09, 0x1F, 0x7A, 0xBB, 0xCA, 0x6A, 0xFB, 0xB8, 0x9B, 0xD5, 0xC1, 0x25, 0x9C, 0xA9, 0x17 /* 6.2.0 Device Master Key Source Source. */
-.byte 0x8F, 0x77, 0x5A, 0x96, 0xB0, 0x94, 0xFD, 0x8D, 0x28, 0xE4, 0x19, 0xC8, 0x16, 0x1C, 0xDB, 0x3D /* 7.0.0 Device Master Key Source Source. */
-.byte 0x67, 0x62, 0xD4, 0x8E, 0x55, 0xCF, 0xFF, 0x41, 0x31, 0x15, 0x3B, 0x24, 0x0C, 0x7C, 0x07, 0xAE /* 8.1.0 Device Master Key Source Source. */
-.byte 0x4A, 0xC3, 0x4E, 0x14, 0x8B, 0x96, 0x4A, 0xD5, 0xD4, 0x99, 0x73, 0xC4, 0x45, 0xAB, 0x8B, 0x49 /* 9.0.0 Device Master Key Source Source. */
-.byte 0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94 /* 9.1.0 Device Master Key Source Source. */
+.byte 0x8B, 0x4E, 0x1C, 0x22, 0x42, 0x07, 0xC8, 0x73, 0x56, 0x94, 0x08, 0x8B, 0xCC, 0x47, 0x0F, 0x5D /* 4.0.0  Device Master Key Source Source. */
+.byte 0x6C, 0xEF, 0xC6, 0x27, 0x8B, 0xEC, 0x8A, 0x91, 0x99, 0xAB, 0x24, 0xAC, 0x4F, 0x1C, 0x8F, 0x1C /* 5.0.0  Device Master Key Source Source. */
+.byte 0x70, 0x08, 0x1B, 0x97, 0x44, 0x64, 0xF8, 0x91, 0x54, 0x9D, 0xC6, 0x84, 0x8F, 0x1A, 0xB2, 0xE4 /* 6.0.0  Device Master Key Source Source. */
+.byte 0x8E, 0x09, 0x1F, 0x7A, 0xBB, 0xCA, 0x6A, 0xFB, 0xB8, 0x9B, 0xD5, 0xC1, 0x25, 0x9C, 0xA9, 0x17 /* 6.2.0  Device Master Key Source Source. */
+.byte 0x8F, 0x77, 0x5A, 0x96, 0xB0, 0x94, 0xFD, 0x8D, 0x28, 0xE4, 0x19, 0xC8, 0x16, 0x1C, 0xDB, 0x3D /* 7.0.0  Device Master Key Source Source. */
+.byte 0x67, 0x62, 0xD4, 0x8E, 0x55, 0xCF, 0xFF, 0x41, 0x31, 0x15, 0x3B, 0x24, 0x0C, 0x7C, 0x07, 0xAE /* 8.1.0  Device Master Key Source Source. */
+.byte 0x4A, 0xC3, 0x4E, 0x14, 0x8B, 0x96, 0x4A, 0xD5, 0xD4, 0x99, 0x73, 0xC4, 0x45, 0xAB, 0x8B, 0x49 /* 9.0.0  Device Master Key Source Source. */
+.byte 0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94 /* 9.1.0  Device Master Key Source Source. */
+.byte 0xAA, 0xFD, 0xBC, 0xBB, 0x25, 0xC3, 0xA4, 0xEF, 0xE3, 0xEE, 0x58, 0x53, 0xB7, 0xF8, 0xDD, 0xD6 /* 12.1.0 Device Master Key Source Source. */
 
 /* Development Device Master Kek Sources. */
-.byte 0xD6, 0xBD, 0x9F, 0xC6, 0x18, 0x09, 0xE1, 0x96, 0x20, 0x39, 0x60, 0xD2, 0x89, 0x83, 0x31, 0x34 /* 4.0.0 Device Master Kek Source. */
-.byte 0x59, 0x2D, 0x20, 0x69, 0x33, 0xB5, 0x17, 0xBA, 0xCF, 0xB1, 0x4E, 0xFD, 0xE4, 0xC2, 0x7B, 0xA8 /* 5.0.0 Device Master Kek Source. */
-.byte 0xF6, 0xD8, 0x59, 0x63, 0x8F, 0x47, 0xCB, 0x4A, 0xD8, 0x74, 0x05, 0x7F, 0x88, 0x92, 0x33, 0xA5 /* 6.0.0 Device Master Kek Source. */
-.byte 0x20, 0xAB, 0xF2, 0x0F, 0x05, 0xE3, 0xDE, 0x2E, 0xA1, 0xFB, 0x37, 0x5E, 0x8B, 0x22, 0x1A, 0x38 /* 6.2.0 Device Master Kek Source. */
-.byte 0x60, 0xAE, 0x56, 0x68, 0x11, 0xE2, 0x0C, 0x99, 0xDE, 0x05, 0xAE, 0x68, 0x78, 0x85, 0x04, 0xAE /* 7.0.0 Device Master Kek Source. */
-.byte 0x94, 0xD6, 0xA8, 0xC0, 0x95, 0xAF, 0xD0, 0xA6, 0x27, 0x53, 0x5E, 0xE5, 0x8E, 0x70, 0x1F, 0x87 /* 8.1.0 Device Master Kek Source. */
-.byte 0x61, 0x6A, 0x88, 0x21, 0xA3, 0x52, 0xB0, 0x19, 0x16, 0x25, 0xA4, 0xE3, 0x4C, 0x54, 0x02, 0x0F /* 9.0.0 Device Master Kek Source. */
-.byte 0x9D, 0xB1, 0xAE, 0xCB, 0xF6, 0xF6, 0xE3, 0xFE, 0xAB, 0x6F, 0xCB, 0xAF, 0x38, 0x03, 0xFC, 0x7B /* 9.1.0 Device Master Kek Source. */
+.byte 0xD6, 0xBD, 0x9F, 0xC6, 0x18, 0x09, 0xE1, 0x96, 0x20, 0x39, 0x60, 0xD2, 0x89, 0x83, 0x31, 0x34 /* 4.0.0  Device Master Kek Source. */
+.byte 0x59, 0x2D, 0x20, 0x69, 0x33, 0xB5, 0x17, 0xBA, 0xCF, 0xB1, 0x4E, 0xFD, 0xE4, 0xC2, 0x7B, 0xA8 /* 5.0.0  Device Master Kek Source. */
+.byte 0xF6, 0xD8, 0x59, 0x63, 0x8F, 0x47, 0xCB, 0x4A, 0xD8, 0x74, 0x05, 0x7F, 0x88, 0x92, 0x33, 0xA5 /* 6.0.0  Device Master Kek Source. */
+.byte 0x20, 0xAB, 0xF2, 0x0F, 0x05, 0xE3, 0xDE, 0x2E, 0xA1, 0xFB, 0x37, 0x5E, 0x8B, 0x22, 0x1A, 0x38 /* 6.2.0  Device Master Kek Source. */
+.byte 0x60, 0xAE, 0x56, 0x68, 0x11, 0xE2, 0x0C, 0x99, 0xDE, 0x05, 0xAE, 0x68, 0x78, 0x85, 0x04, 0xAE /* 7.0.0  Device Master Kek Source. */
+.byte 0x94, 0xD6, 0xA8, 0xC0, 0x95, 0xAF, 0xD0, 0xA6, 0x27, 0x53, 0x5E, 0xE5, 0x8E, 0x70, 0x1F, 0x87 /* 8.1.0  Device Master Kek Source. */
+.byte 0x61, 0x6A, 0x88, 0x21, 0xA3, 0x52, 0xB0, 0x19, 0x16, 0x25, 0xA4, 0xE3, 0x4C, 0x54, 0x02, 0x0F /* 9.0.0  Device Master Kek Source. */
+.byte 0x9D, 0xB1, 0xAE, 0xCB, 0xF6, 0xF6, 0xE3, 0xFE, 0xAB, 0x6F, 0xCB, 0xAF, 0x38, 0x03, 0xFC, 0x7B /* 9.1.0  Device Master Kek Source. */
+.byte 0xC4, 0xBB, 0xF3, 0x9F, 0xA3, 0xAA, 0x00, 0x99, 0x7C, 0x97, 0xAD, 0x91, 0x8F, 0xE8, 0x45, 0xCB /* 12.1.0 Device Master Kek Source. */
 
 /* Production Device Master Kek Sources. */
-.byte 0x88, 0x62, 0x34, 0x6E, 0xFA, 0xF7, 0xD8, 0x3F, 0xE1, 0x30, 0x39, 0x50, 0xF0, 0xB7, 0x5D, 0x5D /* 4.0.0 Device Master Kek Source. */
-.byte 0x06, 0x1E, 0x7B, 0xE9, 0x6D, 0x47, 0x8C, 0x77, 0xC5, 0xC8, 0xE7, 0x94, 0x9A, 0xA8, 0x5F, 0x2E /* 5.0.0 Device Master Kek Source. */
-.byte 0x99, 0xFA, 0x98, 0xBD, 0x15, 0x1C, 0x72, 0xFD, 0x7D, 0x9A, 0xD5, 0x41, 0x00, 0xFD, 0xB2, 0xEF /* 6.0.0 Device Master Kek Source. */
-.byte 0x81, 0x3C, 0x6C, 0xBF, 0x5D, 0x21, 0xDE, 0x77, 0x20, 0xD9, 0x6C, 0xE3, 0x22, 0x06, 0xAE, 0xBB /* 6.2.0 Device Master Kek Source. */
-.byte 0x86, 0x61, 0xB0, 0x16, 0xFA, 0x7A, 0x9A, 0xEA, 0xF6, 0xF5, 0xBE, 0x1A, 0x13, 0x5B, 0x6D, 0x9E /* 7.0.0 Device Master Kek Source. */
-.byte 0xA6, 0x81, 0x71, 0xE7, 0xB5, 0x23, 0x74, 0xB0, 0x39, 0x8C, 0xB7, 0xFF, 0xA0, 0x62, 0x9F, 0x8D /* 8.1.0 Device Master Kek Source. */
-.byte 0x03, 0xE7, 0xEB, 0x43, 0x1B, 0xCF, 0x5F, 0xB5, 0xED, 0xDC, 0x97, 0xAE, 0x21, 0x8D, 0x19, 0xED /* 9.0.0 Device Master Kek Source. */
-.byte 0xCE, 0xFE, 0x41, 0x0F, 0x46, 0x9A, 0x30, 0xD6, 0xF2, 0xE9, 0x0C, 0x6B, 0xB7, 0x15, 0x91, 0x36 /* 9.1.0 Device Master Kek Source. */
+.byte 0x88, 0x62, 0x34, 0x6E, 0xFA, 0xF7, 0xD8, 0x3F, 0xE1, 0x30, 0x39, 0x50, 0xF0, 0xB7, 0x5D, 0x5D /* 4.0.0  Device Master Kek Source. */
+.byte 0x06, 0x1E, 0x7B, 0xE9, 0x6D, 0x47, 0x8C, 0x77, 0xC5, 0xC8, 0xE7, 0x94, 0x9A, 0xA8, 0x5F, 0x2E /* 5.0.0  Device Master Kek Source. */
+.byte 0x99, 0xFA, 0x98, 0xBD, 0x15, 0x1C, 0x72, 0xFD, 0x7D, 0x9A, 0xD5, 0x41, 0x00, 0xFD, 0xB2, 0xEF /* 6.0.0  Device Master Kek Source. */
+.byte 0x81, 0x3C, 0x6C, 0xBF, 0x5D, 0x21, 0xDE, 0x77, 0x20, 0xD9, 0x6C, 0xE3, 0x22, 0x06, 0xAE, 0xBB /* 6.2.0  Device Master Kek Source. */
+.byte 0x86, 0x61, 0xB0, 0x16, 0xFA, 0x7A, 0x9A, 0xEA, 0xF6, 0xF5, 0xBE, 0x1A, 0x13, 0x5B, 0x6D, 0x9E /* 7.0.0  Device Master Kek Source. */
+.byte 0xA6, 0x81, 0x71, 0xE7, 0xB5, 0x23, 0x74, 0xB0, 0x39, 0x8C, 0xB7, 0xFF, 0xA0, 0x62, 0x9F, 0x8D /* 8.1.0  Device Master Kek Source. */
+.byte 0x03, 0xE7, 0xEB, 0x43, 0x1B, 0xCF, 0x5F, 0xB5, 0xED, 0xDC, 0x97, 0xAE, 0x21, 0x8D, 0x19, 0xED /* 9.0.0  Device Master Kek Source. */
+.byte 0xCE, 0xFE, 0x41, 0x0F, 0x46, 0x9A, 0x30, 0xD6, 0xF2, 0xE9, 0x0C, 0x6B, 0xB7, 0x15, 0x91, 0x36 /* 9.1.0  Device Master Kek Source. */
+.byte 0xC2, 0x65, 0x34, 0x6E, 0xC7, 0xC6, 0x5D, 0x97, 0x3E, 0x34, 0x5C, 0x6B, 0xB3, 0x7E, 0xC6, 0xE3 /* 12.1.0 Device Master Kek Source. */

exosphere/program/source/boot/secmon_package2.cpp

@@ -94,7 +94,7 @@ namespace ams::secmon::boot {
         }
 
         /* Check that the key generation is one that we can use. */
-        static_assert(pkg1::KeyGeneration_Count == 11);
+        static_assert(pkg1::KeyGeneration_Count == 12);
         if (key_generation >= pkg1::KeyGeneration_Count) {
             return false;
         }

exosphere/program/source/smc/secmon_smc_aes.cpp

@@ -272,7 +272,19 @@ namespace ams::secmon::smc {
 
         void GetSecureDataImpl(u8 *dst, SecureData which, bool tweak) {
             /* Compute the appropriate AES-CTR. */
-            se::ComputeAes128Ctr(dst, AesKeySize, pkg1::AesKeySlot_Device, SecureDataSource, AesKeySize, GetSecureDataCounter(which), AesKeySize);
+            {
+                /* Ensure that the SE sees consistent data. */
+                hw::FlushDataCache(dst, AesKeySize);
+                hw::DataSynchronizationBarrierInnerShareable();
+
+                /* Perform the appropriate AES operation. */
+                se::ComputeAes128Ctr(dst, AesKeySize, pkg1::AesKeySlot_Device, SecureDataSource, AesKeySize, GetSecureDataCounter(which), AesKeySize);
+                hw::DataSynchronizationBarrierInnerShareable();
+
+                /* Ensure the CPU sees consistent data. */
+                hw::FlushDataCache(dst, AesKeySize);
+                hw::DataSynchronizationBarrierInnerShareable();
+            }
 
             /* Tweak, if we should. */
             if (tweak) {

exosphere/program/source/smc/secmon_smc_info.cpp

@@ -243,7 +243,7 @@ namespace ams::secmon::smc {
                                 (static_cast<u64>(ATMOSPHERE_RELEASE_VERSION_MINOR & 0xFF) << 48) |
                                 (static_cast<u64>(ATMOSPHERE_RELEASE_VERSION_MICRO & 0xFF) << 40) |
                                 (static_cast<u64>(GetKeyGeneration())                      << 32) |
-                                (static_cast<u64>(GetTargetFirmware())                     << 00);
+                                (static_cast<u64>(GetTargetFirmware())                     <<  0);
                     break;
                 case ConfigItem::ExosphereNeedsReboot:
                     /* We are executing, so we aren't in the process of rebooting. */
@@ -290,6 +290,12 @@ namespace ams::secmon::smc {
                     /* Get whether usb 3.0 should be force-enabled. */
                     args.r[1] = GetSecmonConfiguration().IsUsb30ForceEnabled();
                     break;
+                case ConfigItem::ExosphereSupportedHosVersion:
+                    /* Get information about the supported hos version. */
+                    args.r[1] = (static_cast<u64>(ATMOSPHERE_SUPPORTED_HOS_VERSION_MAJOR & 0xFF) << 24) |
+                                (static_cast<u64>(ATMOSPHERE_SUPPORTED_HOS_VERSION_MINOR & 0xFF) << 16) |
+                                (static_cast<u64>(ATMOSPHERE_SUPPORTED_HOS_VERSION_MICRO & 0xFF) <<  8);
+                    break;
                 default:
                     return SmcResult::InvalidArgument;
             }

exosphere/program/source/smc/secmon_smc_info.hpp

@@ -40,17 +40,18 @@ namespace ams::secmon::smc {
         Package2Hash                  = 17,
 
         /* Extension config items for exosphere. */
-        ExosphereApiVersion       = 65000,
-        ExosphereNeedsReboot      = 65001,
-        ExosphereNeedsShutdown    = 65002,
-        ExosphereGitCommitHash    = 65003,
-        ExosphereHasRcmBugPatch   = 65004,
-        ExosphereBlankProdInfo    = 65005,
-        ExosphereAllowCalWrites   = 65006,
-        ExosphereEmummcType       = 65007,
-        ExospherePayloadAddress   = 65008,
-        ExosphereLogConfiguration = 65009,
-        ExosphereForceEnableUsb30 = 65010,
+        ExosphereApiVersion          = 65000,
+        ExosphereNeedsReboot         = 65001,
+        ExosphereNeedsShutdown       = 65002,
+        ExosphereGitCommitHash       = 65003,
+        ExosphereHasRcmBugPatch      = 65004,
+        ExosphereBlankProdInfo       = 65005,
+        ExosphereAllowCalWrites      = 65006,
+        ExosphereEmummcType          = 65007,
+        ExospherePayloadAddress      = 65008,
+        ExosphereLogConfiguration    = 65009,
+        ExosphereForceEnableUsb30    = 65010,
+        ExosphereSupportedHosVersion = 65011,
     };
 
     SmcResult SmcGetConfigUser(SmcArguments &args);

exosphere/sdmmc_test/sdmmc_test.specs

@@ -1,7 +1,4 @@
 %rename link old_link
 
 *link:
-%(old_link) -T %:getenv(TOPDIR /sdmmc_test.ld) --gc-sections --nmagic -nostdlib -nostartfiles
-
-*startfile:
-crti%O%s crtbegin%O%s
+%(old_link) -T %:getenv(TOPDIR /sdmmc_test.ld) --gc-sections --nmagic

exosphere/warmboot/source/warmboot_main.cpp

@@ -36,7 +36,6 @@ namespace ams::warmboot {
     void Main(const Metadata *metadata) {
         /* Ensure that we're running under vaguely sane conditions. */
         AMS_ABORT_UNLESS(metadata->magic == Metadata::Magic);
-        AMS_ABORT_UNLESS(metadata->target_firmware <= ams::TargetFirmware_Max);
 
         /* Restrict the bpmp's access to dram. */
         if (metadata->target_firmware >= TargetFirmware_4_0_0) {

exosphere/warmboot/warmboot.specs

@@ -1,7 +1,4 @@
 %rename link old_link
 
 *link:
-%(old_link) -T %:getenv(TOPDIR /warmboot.ld) --gc-sections --nmagic -nostdlib -nostartfiles
-
-*startfile:
-crti%O%s crtbegin%O%s
+%(old_link) -T %:getenv(TOPDIR /warmboot.ld) --gc-sections --nmagic

fusee/Makefile

@@ -1,4 +1,4 @@
-SUBFOLDERS := fusee-primary fusee-mtc fusee-secondary
+SUBFOLDERS := fusee-primary fusee-secondary
 
 TOPTARGETS := all clean
 

fusee/common/fatfs/diskio.c

@@ -17,8 +17,6 @@
 #include "../../../fusee/fusee-primary/fusee-primary-main/src/fs_utils.h"
 #elif defined(FUSEE_STAGE2_SRC)
 #include "../../../fusee/fusee-secondary/src/device_partition.h"
-#elif defined(SEPT_STAGE2_SRC)
-#include "../../../sept/sept-secondary/src/fs_utils.h"
 #endif
 
 #ifdef FUSEE_STAGE2_SRC

fusee/common/sdmmc/sdmmc.c

@@ -30,8 +30,6 @@
 #include "../../../fusee/fusee-primary/fusee-primary-main/src/timers.h"
 #elif defined(FUSEE_STAGE2_SRC)
 #include "../../../fusee/fusee-secondary/src/timers.h"
-#elif defined(SEPT_STAGE2_SRC)
-#include "../../../sept/sept-secondary/src/timers.h"
 #endif
 
 #define UNSTUFF_BITS(resp,start,size)                               \
@@ -102,7 +100,7 @@ static int sdmmc_device_send_r1_cmd(sdmmc_device_t *device, uint32_t opcode, uin
     if (resp_mask) {
         resp &= ~(resp_mask);
     }
-    
+
     /* We got an error state. */
     if (is_sdmmc_device_r1_error(resp)) {
         return 0;
@@ -355,7 +353,7 @@ static int sdmmc_sd_decode_scr(sdmmc_device_t *device, uint8_t *scr) {
     if (device->scr.sda_spec3) {
         device->scr.cmds = UNSTUFF_BITS(resp, 32, 2);
     }
-    
+
     /* Unknown SCR structure version. */
     if (UNSTUFF_BITS(resp, 60, 4)) {
         return 0;
@@ -465,7 +463,7 @@ static int sdmmc_sd_send_op_cond(sdmmc_device_t *device, bool is_sd_ver2, bool i
         if (is_uhs_en) {
             arg |= SD_OCR_S18R;
         }
-        
+
         cmd.opcode = SD_APP_OP_COND;
         cmd.arg = arg;
         cmd.flags = SDMMC_RSP_R3;
@@ -916,7 +914,7 @@ int sdmmc_device_sd_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth b
     if (!sdmmc_sd_decode_csd(device, csd)) {
         sdmmc_warn(sdmmc, "Got unknown CSD structure (0x%08x)!", device->csd.structure);
     }
-    
+
     /* If we never switched to 1.8V, change the bus speed mode. */
     if (!device->is_180v) {
         /* Reconfigure the internal clock. */
@@ -1155,7 +1153,7 @@ static int sdmmc_mmc_send_op_cond(sdmmc_device_t *device, SdmmcBusVoltage bus_vo
             if (resp & SD_OCR_CCS) {
                 device->is_block_sdhc = true;
             }
-            
+
             return 1;
         }
 
@@ -1439,7 +1437,7 @@ int sdmmc_device_mmc_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth
     if (!sdmmc_mmc_decode_csd(device, csd)) {
         sdmmc_warn(sdmmc, "Got unknown CSD structure (0x%08x)!", device->csd.structure);
     }
-    
+
     /* Reconfigure the internal clock. */
     if (!sdmmc_select_speed(device->sdmmc, SDMMC_SPEED_MMC_LEGACY)) {
         sdmmc_error(sdmmc, "Failed to apply the correct bus speed!");
@@ -1498,7 +1496,7 @@ int sdmmc_device_mmc_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth
     } else {
         sdmmc_info(sdmmc, "BKOPS is disabled!");
     }
-    
+
     /* Switch to high speed mode. */
     if (!sdmmc_mmc_select_timing(device, bus_speed)) {
         sdmmc_error(sdmmc, "Failed to switch to high speed mode!");

fusee/common/sdmmc/sdmmc_core.c

@@ -41,15 +41,6 @@
 #include "../../../fusee/fusee-secondary/src/gpio.h"
 #include "../../../fusee/fusee-secondary/src/pmc.h"
 #include "../../../fusee/fusee-secondary/src/max7762x.h"
-#elif defined(SEPT_STAGE2_SRC)
-#include "../../../sept/sept-secondary/src/car.h"
-#include "../../../sept/sept-secondary/src/fuse.h"
-#include "../../../sept/sept-secondary/src/pinmux.h"
-#include "../../../sept/sept-secondary/src/timers.h"
-#include "../../../sept/sept-secondary/src/apb_misc.h"
-#include "../../../sept/sept-secondary/src/gpio.h"
-#include "../../../sept/sept-secondary/src/pmc.h"
-#include "../../../sept/sept-secondary/src/max7762x.h"
 #endif
 #include "../log.h"
 

fusee/fusee-mtc/Makefile

@@ -1,163 +0,0 @@
-#---------------------------------------------------------------------------------
-.SUFFIXES:
-#---------------------------------------------------------------------------------
-
-ifeq ($(strip $(DEVKITARM)),)
-$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
-endif
-
-TOPDIR ?= $(CURDIR)
-
-AMS		:= $(TOPDIR)/../../
-include $(DEVKITARM)/base_rules
-
-AMSBRANCH := $(shell git symbolic-ref --short HEAD)
-AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
-
-ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
-    AMSREV := $(AMSREV)-dirty
-endif
-
-#---------------------------------------------------------------------------------
-# TARGET is the name of the output
-# BUILD is the directory where object files & intermediate files will be placed
-# SOURCES is a list of directories containing source code
-# DATA is a list of directories containing data files
-# INCLUDES is a list of directories containing header files
-#---------------------------------------------------------------------------------
-TARGET		:=	$(notdir $(CURDIR))
-BUILD		:=	build
-SOURCES		:=	src ../../fusee/common ../../fusee/common/display
-DATA		:=	data
-INCLUDES	:=	include ../../libraries/libvapours/include
-
-#---------------------------------------------------------------------------------
-# options for code generation
-#---------------------------------------------------------------------------------
-ARCH	:=	-march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-DEFINES :=	-D__BPMP__ -DFUSEE_MTC_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
-
-CFLAGS	:= \
-	-g \
-	-O2 \
-	-fomit-frame-pointer \
-	-ffunction-sections \
-	-fdata-sections \
-	-std=gnu11 \
-	-Werror \
-	-Wall \
-	-fstrict-volatile-bitfields \
-	$(ARCH) $(DEFINES)
-
-CFLAGS	+=	$(INCLUDE)
-
-CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
-
-ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
-
-LIBS	:=
-
-#---------------------------------------------------------------------------------
-# list of directories containing libraries, this must be the top level containing
-# include and lib
-#---------------------------------------------------------------------------------
-LIBDIRS	:=
-
-
-#---------------------------------------------------------------------------------
-# no real need to edit anything past this point unless you need to add additional
-# rules for different file extensions
-#---------------------------------------------------------------------------------
-ifneq ($(BUILD),$(notdir $(CURDIR)))
-#---------------------------------------------------------------------------------
-
-export OUTPUT	:=	$(CURDIR)/$(TARGET)
-export TOPDIR	:=	$(CURDIR)
-
-export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
-			$(foreach dir,$(DATA),$(CURDIR)/$(dir))
-
-export DEPSDIR	:=	$(CURDIR)/$(BUILD)
-
-CFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
-CPPFILES	:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
-SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
-BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*)))
-
-#---------------------------------------------------------------------------------
-# use CXX for linking C++ projects, CC for standard C
-#---------------------------------------------------------------------------------
-ifeq ($(strip $(CPPFILES)),)
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CC)
-#---------------------------------------------------------------------------------
-else
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CXX)
-#---------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------
-
-export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
-export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
-export OFILES 		:=	$(OFILES_BIN) $(OFILES_SRC)
-export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(BINFILES)))
-
-export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
-			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-			-I$(CURDIR)/$(BUILD)
-
-export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
-
-.PHONY: $(BUILD) clean all
-
-#---------------------------------------------------------------------------------
-all: $(BUILD)
-
-$(BUILD):
-	@[ -d $@ ] || mkdir -p $@
-	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
-
-#---------------------------------------------------------------------------------
-clean:
-	@echo clean ...
-	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
-
-#---------------------------------------------------------------------------------
-else
-.PHONY:	all
-
-DEPENDS	:=	$(OFILES:.o=.d)
-
-#---------------------------------------------------------------------------------
-# main targets
-#---------------------------------------------------------------------------------
-all	:	$(OUTPUT).bin
-
-$(OUTPUT).bin	:	$(OUTPUT).elf
-	$(OBJCOPY) -S -O binary $< $@
-	@echo built ... $(notdir $@)
-
-$(OUTPUT).elf	:	$(OFILES)
-
-%.elf: $(OFILES)
-	@echo linking $(notdir $@)
-	@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
-	@$(NM) -CSn $@ > $(notdir $*.lst)
-
-$(OFILES_SRC)	: $(HFILES_BIN)
-
-#---------------------------------------------------------------------------------
-# you need a rule like this for each extension you use as binary data
-#---------------------------------------------------------------------------------
-%.bin.o	%_bin.h:	%.bin
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(bin2o)
-
--include $(DEPENDS)
-
-#---------------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------------

fusee/fusee-mtc/linker.ld

@@ -1,170 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-
-PHDRS
-{
-    crt0        PT_LOAD;
-    main        PT_LOAD;
-}
-
-/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */
-MEMORY
-{
-    NULL        : ORIGIN = 0x00000000, LENGTH = 0x1000
-    main        : ORIGIN = 0xF0000000, LENGTH = 0x10000000
-}
-
-SECTIONS
-{
-    PROVIDE(__start__           = 0xF0000000);
-    PROVIDE(__stack_bottom__    = 0x90010000);
-    PROVIDE(__stack_top__       = 0x90020000);
-    PROVIDE(__heap_start__      = 0x90020000);
-    PROVIDE(__heap_end__        = 0xA0020000);
-
-    . = __start__;
-    
-    .crt0 :
-    {
-        KEEP( *(.text.start) )
-        KEEP( *(.init) )
-        . = ALIGN(32);
-    } >main :crt0
-    
-    .text :
-    {
-        . = ALIGN(32);
-        /* .text */
-        *(.text)
-        *(.text.*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.stub)
-        *(.gnu.warning)
-        *(.gnu.linkonce.t*)
-
-        /* .fini */
-        KEEP( *(.fini) )
-        . = ALIGN(8);
-    } >main :main
-
-    .rodata :
-    {
-        *(.rodata)
-        *(.roda)
-        *(.rodata.*)
-        *all.rodata*(*)
-        *(.gnu.linkonce.r*)
-        SORT(CONSTRUCTORS)
-        . = ALIGN(8);
-    } >main
-    
-    .preinit_array :
-    {
-        PROVIDE (__preinit_array_start = .);
-        KEEP (*(.preinit_array))
-        PROVIDE (__preinit_array_end = .);
-    } >main
-
-    .init_array ALIGN(4) :
-    {
-        PROVIDE (__init_array_start = .);
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        PROVIDE (__init_array_end = .);
-    } >main
-
-    .fini_array ALIGN(4) :
-    {
-        PROVIDE (__fini_array_start = .);
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        PROVIDE (__fini_array_end = .);
-    } >main
-
-    .ctors ALIGN(4) :
-    {
-        KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*(.ctors))
-        . = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-    } >main
-
-    .dtors ALIGN(4) :
-    {
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*(.dtors))
-        . = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-    } >main
-
-    .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main
-    ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*)  __exidx_end = ABSOLUTE(.);} >main
-
-    .data :
-    {
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d*)
-        CONSTRUCTORS
-        . = ALIGN(32);
-    } >main
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(32);
-        PROVIDE (__bss_start__ = ABSOLUTE(.));
-        *(.dynbss)
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b*)
-        *(COMMON)
-        . = ALIGN(32);
-        PROVIDE (__bss_end__ = ABSOLUTE(.));
-    } >main :NONE
-    __end__ = ABSOLUTE(.) ;
-
-
-    /* ==================
-       ==== Metadata ====
-       ================== */
-
-    /* Discard sections that difficult post-processing */
-    /DISCARD/ : { *(.group .comment .note) }
-
-    /* Stabs debugging sections. */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-
-    /* DWARF debug sections.
-       Symbols in the DWARF debugging sections are relative to the beginning
-       of the section so we begin them at 0. */
-
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-}

fusee/fusee-mtc/linker.specs

@@ -1,7 +0,0 @@
-%rename link                old_link
-
-*link:
-%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections
-
-*startfile:
-crti%O%s crtbegin%O%s

fusee/fusee-mtc/src/car.c

@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "car.h"
-#include "timers.h"
-#include "utils.h"
-
-static inline uint32_t get_clk_source_reg(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0x178;
-        case CARDEVICE_UARTB: return 0x17C;
-        case CARDEVICE_UARTC: return 0x1A0;
-        case CARDEVICE_I2C1: return 0x124;
-        case CARDEVICE_I2C5: return 0x128;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0x42C;
-        case CARDEVICE_HOST1X: return 0x180;
-        case CARDEVICE_TSEC: return 0x1F4;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 0x410;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 0x1D4;
-        case CARDEVICE_MSELECT: return 0x3B4;
-        case CARDEVICE_ACTMON: return 0x3E8;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-} 
-
-static inline uint32_t get_clk_source_val(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0;
-        case CARDEVICE_UARTB: return 0;
-        case CARDEVICE_UARTC: return 0;
-        case CARDEVICE_I2C1: return 6;
-        case CARDEVICE_I2C5: return 6;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0;
-        case CARDEVICE_HOST1X: return 4;
-        case CARDEVICE_TSEC: return 0;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 0;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 0;
-        case CARDEVICE_MSELECT: return 0;
-        case CARDEVICE_ACTMON: return 6;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-}
-
-static inline uint32_t get_clk_source_div(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0;
-        case CARDEVICE_UARTB: return 0;
-        case CARDEVICE_UARTC: return 0;
-        case CARDEVICE_I2C1: return 0;
-        case CARDEVICE_I2C5: return 0;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0;
-        case CARDEVICE_HOST1X: return 3;
-        case CARDEVICE_TSEC: return 2;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 2;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 4;
-        case CARDEVICE_MSELECT: return 6;
-        case CARDEVICE_ACTMON: return 0;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-}
-
-static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
-static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; 
-
-void clk_enable(CarDevice dev) {
-    uint32_t clk_source_reg;
-    if ((clk_source_reg = get_clk_source_reg(dev))) {
-        MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev);
-    }
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void clk_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void rst_enable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void rst_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void clkrst_enable(CarDevice dev) {
-    clk_enable(dev);
-    rst_disable(dev);
-}
-
-void clkrst_disable(CarDevice dev) {
-    rst_enable(dev);
-    clk_disable(dev);
-}
-
-void clkrst_reboot(CarDevice dev) {
-    clkrst_disable(dev);
-    if (dev == CARDEVICE_KFUSE) {
-        /* Workaround for KFUSE clock. */
-        clk_enable(dev);
-        udelay(100);
-        rst_disable(dev);
-        udelay(200);
-    } else {
-        clkrst_enable(dev);
-    }
-}
-
-void clkrst_enable_fuse_regs(bool enable) {
-    volatile tegra_car_t *car = car_get_regs();
-    car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28));
-}

fusee/fusee-mtc/src/car.h

@@ -1,510 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_CAR_H
-#define FUSEE_CAR_H
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#define CAR_BASE 0x60006000
-#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n)
-
-#define CLK_L_SDMMC1    (1 << 14)
-#define CLK_L_SDMMC2    (1 << 9)
-#define CLK_U_SDMMC3    (1 << 5)
-#define CLK_L_SDMMC4    (1 << 15)
-
-#define CLK_SOURCE_MASK             (0b111 << 29)
-#define CLK_SOURCE_FIRST            (0b000 << 29)
-#define CLK_DIVIDER_MASK            (0xff << 0)
-#define CLK_DIVIDER_UNITY           (0x00 << 0)
-
-#define NUM_CAR_BANKS 7
-
-/* Clock and reset devices. */
-typedef enum {
-    CARDEVICE_BPMP      = ((0 << 5) | 0x1),
-    CARDEVICE_UARTA     = ((0 << 5) | 0x6),
-    CARDEVICE_UARTB     = ((0 << 5) | 0x7),
-    CARDEVICE_I2C1      = ((0 << 5) | 0xC),
-    CARDEVICE_USBD      = ((0 << 5) | 0x16),
-    CARDEVICE_HOST1X    = ((0 << 5) | 0x1C),
-    CARDEVICE_AHBDMA    = ((1 << 5) | 0x1),
-    CARDEVICE_APBDMA    = ((1 << 5) | 0x2),
-    CARDEVICE_KFUSE     = ((1 << 5) | 0x8),
-    CARDEVICE_I2C5      = ((1 << 5) | 0xF),
-    CARDEVICE_UARTC     = ((1 << 5) | 0x17),
-    CARDEVICE_USB2      = ((1 << 5) | 0x1A),
-    CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
-    CARDEVICE_TSEC      = ((2 << 5) | 0x13),
-    CARDEVICE_MSELECT   = ((3 << 5) | 0x8),
-    CARDEVICE_ACTMON    = ((3 << 5) | 0x17),
-    CARDEVICE_TZRAM     = ((3 << 5) | 0x1E),
-    CARDEVICE_SE        = ((3 << 5) | 0x1F),
-    CARDEVICE_CL_DVFS   = ((4 << 5) | 0x1B),
-    CARDEVICE_SOR0      = ((5 << 5) | 0x16),
-    CARDEVICE_SOR1      = ((5 << 5) | 0x17),
-    CARDEVICE_SOR_SAFE  = ((6 << 5) | 0x1E),
-} CarDevice;
-
-/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-typedef struct {
-    uint32_t rst_src;           /* _RST_SOURCE_0,   0x00 */
-
-    /* _RST_DEVICES_L/H/U_0     0x4-0xc */
-    uint32_t rst_dev_l;
-    uint32_t rst_dev_h;
-    uint32_t rst_dev_u;
-
-    /* _CLK_OUT_ENB_L/H/U_0     0x10-0x18 */
-    uint32_t clk_out_enb_l;
-    uint32_t clk_out_enb_h;
-    uint32_t clk_out_enb_u;
-
-    uint32_t _0x1C;
-    uint32_t cclk_brst_pol;     /* _CCLK_BURST_POLICY_0,    0x20 */
-    uint32_t super_cclk_div;    /* _SUPER_CCLK_DIVIDER_0,   0x24 */
-    uint32_t sclk_brst_pol;     /* _SCLK_BURST_POLICY_0,    0x28 */
-    uint32_t super_sclk_div;    /* _SUPER_SCLK_DIVIDER_0,   0x2c */
-    uint32_t clk_sys_rate;      /* _CLK_SYSTEM_RATE_0,      0x30 */
-    uint32_t prog_dly_clk;      /* _PROG_DLY_CLK_0,         0x34 */
-    uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,  0x38 */
-    uint32_t _0x3C;
-    uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,  0x40 */
-    uint32_t clk_mask_arm;      /* _CLK_MASK_ARM_0,         0x44 */
-    uint32_t misc_clk_enb;      /* _MISC_CLK_ENB_0,         0x48 */
-    uint32_t clk_cpu_cmplx;     /* _CLK_CPU_CMPLX_0,        0x4c */
-    uint32_t osc_ctrl;          /* _OSC_CTRL_0,             0x50 */
-    uint32_t pll_lfsr;          /* _PLL_LFSR_0,             0x54 */
-    uint32_t osc_freq_det;      /* _OSC_FREQ_DET_0,         0x58 */
-    uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,  0x5c */
-    uint32_t _0x60[2];
-    uint32_t plle_ss_cntl;      /* _PLLE_SS_CNTL_0,         0x68 */
-    uint32_t plle_misc1;        /* _PLLE_MISC1_0,           0x6c */
-    uint32_t _0x70[4];
-
-    /* PLLC 0x80-0x8c */
-    uint32_t pllc_base;
-    uint32_t pllc_out;
-    uint32_t pllc_misc0;
-    uint32_t pllc_misc1;
-
-    /* PLLM 0x90-0x9c */
-    uint32_t pllm_base;
-    uint32_t pllm_out;
-    uint32_t pllm_misc1;
-    uint32_t pllm_misc2;
-
-    /* PLLP 0xa0-0xac */
-    uint32_t pllp_base;
-    uint32_t pllp_outa;
-    uint32_t pllp_outb;
-    uint32_t pllp_misc;
-
-    /* PLLA 0xb0-0xbc */
-    uint32_t plla_base;
-    uint32_t plla_out;
-    uint32_t plla_misc0;
-    uint32_t plla_misc1;
-
-    /* PLLU 0xc0-0xcc */
-    uint32_t pllu_base;
-    uint32_t pllu_out;
-    uint32_t pllu_misc1;
-    uint32_t pllu_misc2;
-
-    /* PLLD 0xd0-0xdc */
-    uint32_t plld_base;
-    uint32_t plld_out;
-    uint32_t plld_misc1;
-    uint32_t plld_misc2;
-
-    /* PLLX 0xe0-0xe4 */
-    uint32_t pllx_base;
-    uint32_t pllx_misc;
-
-    /* PLLE 0xe8-0xf4 */
-    uint32_t plle_base;
-    uint32_t plle_misc;
-    uint32_t plle_ss_cntl1;
-    uint32_t plle_ss_cntl2;
-
-    uint32_t lvl2_clk_gate_ovra;            /* _LVL2_CLK_GATE_OVRA_0,   0xf8 */
-    uint32_t lvl2_clk_gate_ovrb;            /* _LVL2_CLK_GATE_OVRB_0,   0xfc */
-
-    uint32_t clk_source_i2s2;               /* _CLK_SOURCE_I2S2_0,      0x100 */
-    uint32_t clk_source_i2s3;               /* _CLK_SOURCE_I2S3_0,      0x104 */
-    uint32_t clk_source_spdif_out;          /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */
-    uint32_t clk_source_spdif_in;           /* _CLK_SOURCE_SPDIF_IN_0,  0x10c */
-    uint32_t clk_source_pwm;                /* _CLK_SOURCE_PWM_0,       0x110 */
-    uint32_t _0x114;
-    uint32_t clk_source_spi2;               /* _CLK_SOURCE_SPI2_0,      0x118 */
-    uint32_t clk_source_spi3;               /* _CLK_SOURCE_SPI3_0,      0x11c */
-    uint32_t _0x120;
-    uint32_t clk_source_i2c1;               /* _CLK_SOURCE_I2C1_0,      0x124 */
-    uint32_t clk_source_i2c5;               /* _CLK_SOURCE_I2C5_0,      0x128 */
-    uint32_t _0x12c[2];
-    uint32_t clk_source_spi1;               /* _CLK_SOURCE_SPI1_0,      0x134 */
-    uint32_t clk_source_disp1;              /* _CLK_SOURCE_DISP1_0,     0x138 */
-    uint32_t clk_source_disp2;              /* _CLK_SOURCE_DISP2_0,     0x13c */
-    uint32_t _0x140;
-    uint32_t clk_source_isp;                /* _CLK_SOURCE_ISP_0,       0x144 */
-    uint32_t clk_source_vi;                 /* _CLK_SOURCE_VI_0,        0x148 */
-    uint32_t _0x14c;
-    uint32_t clk_source_sdmmc1;             /* _CLK_SOURCE_SDMMC1_0,    0x150 */
-    uint32_t clk_source_sdmmc2;             /* _CLK_SOURCE_SDMMC2_0,    0x154 */
-    uint32_t _0x158[3];
-    uint32_t clk_source_sdmmc4;             /* _CLK_SOURCE_SDMMC4_0,    0x164 */
-    uint32_t _0x168[4];
-    uint32_t clk_source_uarta;              /* _CLK_SOURCE_UARTA_0,     0x178 */
-    uint32_t clk_source_uartb;              /* _CLK_SOURCE_UARTB_0,     0x17c */
-    uint32_t clk_source_host1x;             /* _CLK_SOURCE_HOST1X_0,    0x180 */
-    uint32_t _0x184[5];
-    uint32_t clk_source_i2c2;               /* _CLK_SOURCE_I2C2_0,      0x198 */
-    uint32_t clk_source_emc;                /* _CLK_SOURCE_EMC_0,       0x19c */
-    uint32_t clk_source_uartc;              /* _CLK_SOURCE_UARTC_0,     0x1a0 */
-    uint32_t _0x1a4;
-    uint32_t clk_source_vi_sensor;          /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */
-    uint32_t _0x1ac[2];
-    uint32_t clk_source_spi4;               /* _CLK_SOURCE_SPI4_0,      0x1b4 */
-    uint32_t clk_source_i2c3;               /* _CLK_SOURCE_I2C3_0,      0x1b8 */
-    uint32_t clk_source_sdmmc3;             /* _CLK_SOURCE_SDMMC3_0,    0x1bc */
-    uint32_t clk_source_uartd;              /* _CLK_SOURCE_UARTD_0,     0x1c0 */
-    uint32_t _0x1c4[2];
-    uint32_t clk_source_owr;                /* _CLK_SOURCE_OWR_0,       0x1cc */
-    uint32_t _0x1d0;
-    uint32_t clk_source_csite;              /* _CLK_SOURCE_CSITE_0,     0x1d4 */
-    uint32_t clk_source_i2s1;               /* _CLK_SOURCE_I2S1_0,      0x1d8 */
-    uint32_t clk_source_dtv;                /* _CLK_SOURCE_DTV_0,       0x1dc */
-    uint32_t _0x1e0[5];
-    uint32_t clk_source_tsec;               /* _CLK_SOURCE_TSEC_0,      0x1f4 */
-    uint32_t _0x1f8;
-
-    uint32_t clk_spare2;                    /* _CLK_SPARE2_0,       0x1fc */
-    uint32_t _0x200[32];
-
-    uint32_t clk_out_enb_x;                 /* _CLK_OUT_ENB_X_0,    0x280 */
-    uint32_t clk_enb_x_set;                 /* _CLK_ENB_X_SET_0,    0x284 */
-    uint32_t clk_enb_x_clr;                 /* _CLK_ENB_X_CLR_0,    0x288 */
-
-    uint32_t rst_devices_x;                 /* _RST_DEVICES_X_0,    0x28c */
-    uint32_t rst_dev_x_set;                 /* _RST_DEV_X_SET_0,    0x290 */
-    uint32_t rst_dev_x_clr;                 /* _RST_DEV_X_CLR_0,    0x294 */
-
-    uint32_t clk_out_enb_y;                 /* _CLK_OUT_ENB_Y_0,    0x298 */
-    uint32_t clk_enb_y_set;                 /* _CLK_ENB_Y_SET_0,    0x29c */
-    uint32_t clk_enb_y_clr;                 /* _CLK_ENB_Y_CLR_0,    0x2a0 */
-
-    uint32_t rst_devices_y;                 /* _RST_DEVICES_Y_0,    0x2a4 */
-    uint32_t rst_dev_y_set;                 /* _RST_DEV_Y_SET_0,    0x2a8 */
-    uint32_t rst_dev_y_clr;                 /* _RST_DEV_Y_CLR_0,    0x2ac */
-
-    uint32_t _0x2b0[17];
-    uint32_t dfll_base;                     /* _DFLL_BASE_0,        0x2f4 */
-    uint32_t _0x2f8[2];
-
-    /* _RST_DEV_L/H/U_SET_0 0x300-0x314 */
-    uint32_t rst_dev_l_set;
-    uint32_t rst_dev_l_clr;
-    uint32_t rst_dev_h_set;
-    uint32_t rst_dev_h_clr;
-    uint32_t rst_dev_u_set;
-    uint32_t rst_dev_u_clr;
-
-    uint32_t _0x318[2];
-
-    /* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */
-    uint32_t clk_enb_l_set;
-    uint32_t clk_enb_l_clr;
-    uint32_t clk_enb_h_set;
-    uint32_t clk_enb_h_clr;
-    uint32_t clk_enb_u_set;
-    uint32_t clk_enb_u_clr;
-
-    uint32_t _0x338;
-    uint32_t ccplex_pg_sm_ovrd;         /* _CCPLEX_PG_SM_OVRD_0,    0x33c */
-    uint32_t rst_cpu_cmplx_set;         /* _RST_CPU_CMPLX_SET_0,    0x340 */
-    uint32_t rst_cpu_cmplx_clr;         /* _RST_CPU_CMPLX_CLR_0,    0x344 */
-
-    /* Additional (T30) registers */
-    uint32_t clk_cpu_cmplx_set;         /* _CLK_CPU_CMPLX_SET_0,    0x348 */
-    uint32_t clk_cpu_cmplx_clr;         /* _CLK_CPU_CMPLX_SET_0,    0x34c */
-
-    uint32_t _0x350[2];
-    uint32_t rst_dev_v;                 /* _RST_DEVICES_V_0,        0x358 */
-    uint32_t rst_dev_w;                 /* _RST_DEVICES_W_0,        0x35c */
-    uint32_t clk_out_enb_v;             /* _CLK_OUT_ENB_V_0,        0x360 */
-    uint32_t clk_out_enb_w;             /* _CLK_OUT_ENB_W_0,        0x364 */
-    uint32_t cclkg_brst_pol;            /* _CCLKG_BURST_POLICY_0,   0x368 */
-    uint32_t super_cclkg_div;           /* _SUPER_CCLKG_DIVIDER_0,  0x36c */
-    uint32_t cclklp_brst_pol;           /* _CCLKLP_BURST_POLICY_0,  0x370 */
-    uint32_t super_cclkp_div;           /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
-    uint32_t clk_cpug_cmplx;            /* _CLK_CPUG_CMPLX_0,       0x378 */
-    uint32_t clk_cpulp_cmplx;           /* _CLK_CPULP_CMPLX_0,      0x37c */
-    uint32_t cpu_softrst_ctrl;          /* _CPU_SOFTRST_CTRL_0,     0x380 */
-    uint32_t cpu_softrst_ctrl1;         /* _CPU_SOFTRST_CTRL1_0,    0x384 */
-    uint32_t cpu_softrst_ctrl2;         /* _CPU_SOFTRST_CTRL2_0,    0x388 */
-    uint32_t _0x38c[5];
-    uint32_t lvl2_clk_gate_ovrc;        /* _LVL2_CLK_GATE_OVRC,     0x3a0 */
-    uint32_t lvl2_clk_gate_ovrd;        /* _LVL2_CLK_GATE_OVRD,     0x3a4 */
-    uint32_t _0x3a8[2];
-
-    uint32_t _0x3b0;
-    uint32_t clk_source_mselect;        /* _CLK_SOURCE_MSELECT_0,       0x3b4 */
-    uint32_t clk_source_tsensor;        /* _CLK_SOURCE_TSENSOR_0,       0x3b8 */
-    uint32_t clk_source_i2s4;           /* _CLK_SOURCE_I2S4_0,          0x3bc */
-    uint32_t clk_source_i2s5;           /* _CLK_SOURCE_I2S5_0,          0x3c0 */
-    uint32_t clk_source_i2c4;           /* _CLK_SOURCE_I2C4_0,          0x3c4 */
-    uint32_t _0x3c8[2];
-    uint32_t clk_source_ahub;           /* _CLK_SOURCE_AHUB_0,          0x3d0 */
-    uint32_t _0x3d4[4];
-    uint32_t clk_source_hda2codec_2x;   /* _CLK_SOURCE_HDA2CODEC_2X_0,  0x3e4 */
-    uint32_t clk_source_actmon;         /* _CLK_SOURCE_ACTMON_0,        0x3e8 */
-    uint32_t clk_source_extperiph1;     /* _CLK_SOURCE_EXTPERIPH1_0,    0x3ec */
-    uint32_t clk_source_extperiph2;     /* _CLK_SOURCE_EXTPERIPH2_0,    0x3f0 */
-    uint32_t clk_source_extperiph3;     /* _CLK_SOURCE_EXTPERIPH3_0,    0x3f4 */
-    uint32_t _0x3f8;
-    uint32_t clk_source_i2c_slow;       /* _CLK_SOURCE_I2C_SLOW_0,      0x3fc */
-    uint32_t clk_source_sys;            /* _CLK_SOURCE_SYS_0,           0x400 */
-    uint32_t clk_source_ispb;           /* _CLK_SOURCE_ISPB_0,          0x404 */
-    uint32_t _0x408[2];
-    uint32_t clk_source_sor1;           /* _CLK_SOURCE_SOR1_0,          0x410 */
-    uint32_t clk_source_sor0;           /* _CLK_SOURCE_SOR0_0,          0x414 */
-    uint32_t _0x418[2];
-    uint32_t clk_source_sata_oob;       /* _CLK_SOURCE_SATA_OOB_0,      0x420 */
-    uint32_t clk_source_sata;           /* _CLK_SOURCE_SATA_0,          0x424 */
-    uint32_t clk_source_hda;            /* _CLK_SOURCE_HDA_0,           0x428 */
-    uint32_t clk_source_se;             /* _CLK_SOURCE_SE_0,            0x42c */
-
-    /* _RST_DEV_V/W_SET_0 0x430-0x43c */
-    uint32_t rst_dev_v_set;
-    uint32_t rst_dev_v_clr;
-    uint32_t rst_dev_w_set;
-    uint32_t rst_dev_w_clr;
-
-    /* _CLK_ENB_V/W_CLR_0 0x440-0x44c */
-    uint32_t clk_enb_v_set;
-    uint32_t clk_enb_v_clr;
-    uint32_t clk_enb_w_set;
-    uint32_t clk_enb_w_clr;
-
-    /* Additional (T114+) registers */
-    uint32_t rst_cpug_cmplx_set;    /* _RST_CPUG_CMPLX_SET_0,   0x450 */
-    uint32_t rst_cpug_cmplx_clr;    /* _RST_CPUG_CMPLX_CLR_0,   0x454 */
-    uint32_t rst_cpulp_cmplx_set;   /* _RST_CPULP_CMPLX_SET_0,  0x458 */
-    uint32_t rst_cpulp_cmplx_clr;   /* _RST_CPULP_CMPLX_CLR_0,  0x45c */
-    uint32_t clk_cpug_cmplx_set;    /* _CLK_CPUG_CMPLX_SET_0,   0x460 */
-    uint32_t clk_cpug_cmplx_clr;    /* _CLK_CPUG_CMPLX_CLR_0,   0x464 */
-    uint32_t clk_cpulp_cmplx_set;   /* _CLK_CPULP_CMPLX_SET_0,  0x468 */
-    uint32_t clk_cpulp_cmplx_clr;   /* _CLK_CPULP_CMPLX_CLR_0,  0x46c */
-    uint32_t cpu_cmplx_status;      /* _CPU_CMPLX_STATUS_0,     0x470 */
-    uint32_t _0x474;
-    uint32_t intstatus;             /* _INTSTATUS_0,            0x478 */
-    uint32_t intmask;               /* _INTMASK_0,              0x47c */
-    uint32_t utmip_pll_cfg0;        /* _UTMIP_PLL_CFG0_0,       0x480 */
-    uint32_t utmip_pll_cfg1;        /* _UTMIP_PLL_CFG1_0,       0x484 */
-    uint32_t utmip_pll_cfg2;        /* _UTMIP_PLL_CFG2_0,       0x488 */
-
-    uint32_t plle_aux;              /* _PLLE_AUX_0,             0x48c */
-    uint32_t sata_pll_cfg0;         /* _SATA_PLL_CFG0_0,        0x490 */
-    uint32_t sata_pll_cfg1;         /* _SATA_PLL_CFG1_0,        0x494 */
-    uint32_t pcie_pll_cfg0;         /* _PCIE_PLL_CFG0_0,        0x498 */
-
-    uint32_t prog_audio_dly_clk;    /* _PROG_AUDIO_DLY_CLK_0,   0x49c */
-    uint32_t audio_sync_clk_i2s0;   /* _AUDIO_SYNC_CLK_I2S0_0,  0x4a0 */
-    uint32_t audio_sync_clk_i2s1;   /* _AUDIO_SYNC_CLK_I2S1_0,  0x4a4 */
-    uint32_t audio_sync_clk_i2s2;   /* _AUDIO_SYNC_CLK_I2S2_0,  0x4a8 */
-    uint32_t audio_sync_clk_i2s3;   /* _AUDIO_SYNC_CLK_I2S3_0,  0x4ac */
-    uint32_t audio_sync_clk_i2s4;   /* _AUDIO_SYNC_CLK_I2S4_0,  0x4b0 */
-    uint32_t audio_sync_clk_spdif;  /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */
-
-    uint32_t plld2_base;            /* _PLLD2_BASE_0, 0x4b8 */
-    uint32_t plld2_misc;            /* _PLLD2_MISC_0, 0x4bc */
-    uint32_t utmip_pll_cfg3;        /* _UTMIP_PLL_CFG3_0, 0x4c0 */
-    uint32_t pllrefe_base;          /* _PLLREFE_BASE_0, 0x4c4 */
-    uint32_t pllrefe_misc;          /* _PLLREFE_MISC_0, 0x4c8 */
-    uint32_t pllrefe_out;           /* _PLLREFE_OUT_0, 0x4cc */
-    uint32_t cpu_finetrim_byp;      /* _CPU_FINETRIM_BYP_0, 0x4d0 */
-    uint32_t cpu_finetrim_select;   /* _CPU_FINETRIM_SELECT_0, 0x4d4 */
-    uint32_t cpu_finetrim_dr;       /* _CPU_FINETRIM_DR_0, 0x4d8 */
-    uint32_t cpu_finetrim_df;       /* _CPU_FINETRIM_DF_0, 0x4dc */
-    uint32_t cpu_finetrim_f;        /* _CPU_FINETRIM_F_0, 0x4e0 */
-    uint32_t cpu_finetrim_r;        /* _CPU_FINETRIM_R_0, 0x4e4 */
-    uint32_t pllc2_base;            /* _PLLC2_BASE_0, 0x4e8 */
-    uint32_t pllc2_misc0;           /* _PLLC2_MISC_0_0, 0x4ec */
-    uint32_t pllc2_misc1;           /* _PLLC2_MISC_1_0, 0x4f0 */
-    uint32_t pllc2_misc2;           /* _PLLC2_MISC_2_0, 0x4f4 */
-    uint32_t pllc2_misc3;           /* _PLLC2_MISC_3_0, 0x4f8 */
-    uint32_t pllc3_base;            /* _PLLC3_BASE_0, 0x4fc */
-    uint32_t pllc3_misc0;           /* _PLLC3_MISC_0_0, 0x500 */
-    uint32_t pllc3_misc1;           /* _PLLC3_MISC_1_0, 0x504 */
-    uint32_t pllc3_misc2;           /* _PLLC3_MISC_2_0, 0x508 */
-    uint32_t pllc3_misc3;           /* _PLLC3_MISC_3_0, 0x50c */
-    uint32_t pllx_misc1;            /* _PLLX_MISC_1_0, 0x510 */
-    uint32_t pllx_misc2;            /* _PLLX_MISC_2_0, 0x514 */
-    uint32_t pllx_misc3;            /* _PLLX_MISC_3_0, 0x518 */
-    uint32_t xusbio_pll_cfg0;       /* _XUSBIO_PLL_CFG0_0, 0x51c */
-    uint32_t xusbio_pll_cfg1;       /* _XUSBIO_PLL_CFG0_1, 0x520 */
-    uint32_t plle_aux1;             /* _PLLE_AUX1_0, 0x524 */
-    uint32_t pllp_reshift;          /* _PLLP_RESHIFT_0, 0x528 */
-    uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */
-    uint32_t pllu_hw_pwrdn_cfg0;    /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
-    uint32_t xusb_pll_cfg0;         /* _XUSB_PLL_CFG0_0, 0x534 */
-    uint32_t _0x538;
-    uint32_t clk_cpu_misc;          /* _CLK_CPU_MISC_0, 0x53c */
-    uint32_t clk_cpug_misc;         /* _CLK_CPUG_MISC_0, 0x540 */
-    uint32_t clk_cpulp_misc;        /* _CLK_CPULP_MISC_0, 0x544 */
-    uint32_t pllx_hw_ctrl_cfg;      /* _PLLX_HW_CTRL_CFG_0, 0x548 */
-    uint32_t pllx_sw_ramp_cfg;      /* _PLLX_SW_RAMP_CFG_0, 0x54c */
-    uint32_t pllx_hw_ctrl_status;   /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
-    uint32_t lvl2_clk_gate_ovre;    /* _LVL2_CLK_GATE_OVRE, 0x554 */
-    uint32_t super_gr3d_clk_div;    /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
-    uint32_t spare_reg0;            /* _SPARE_REG0_0, 0x55c */
-    uint32_t audio_sync_clk_dmic1;  /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
-    uint32_t audio_sync_clk_dmic2;  /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
-
-    uint32_t _0x568[2];
-    uint32_t plld2_ss_cfg;          /* _PLLD2_SS_CFG,           0x570 */
-    uint32_t plld2_ss_ctrl1;        /* _PLLD2_SS_CTRL1_0,       0x574 */
-    uint32_t plld2_ss_ctrl2;        /* _PLLD2_SS_CTRL2_0,       0x578 */
-    uint32_t _0x57c[5];
-
-    uint32_t plldp_base;            /* _PLLDP_BASE, 0x590*/
-    uint32_t plldp_misc;            /* _PLLDP_MISC, 0x594 */
-    uint32_t plldp_ss_cfg;          /* _PLLDP_SS_CFG, 0x598 */
-    uint32_t plldp_ss_ctrl1;        /* _PLLDP_SS_CTRL1_0, 0x59c */
-    uint32_t plldp_ss_ctrl2;        /* _PLLDP_SS_CTRL2_0, 0x5a0 */
-    uint32_t pllc4_base;            /* _PLLC4_BASE_0, 0x5a4 */
-    uint32_t pllc4_misc;            /* _PLLC4_MISC_0, 0x5a8 */
-    uint32_t _0x5ac[6];
-    uint32_t clk_spare0;            /* _CLK_SPARE0_0, 0x5c4 */
-    uint32_t clk_spare1;            /* _CLK_SPARE1_0, 0x5c8 */
-    uint32_t gpu_isob_ctrl;         /* _GPU_ISOB_CTRL_0, 0x5cc */
-    uint32_t pllc_misc2;            /* _PLLC_MISC_2_0, 0x5d0 */
-    uint32_t pllc_misc3;            /* _PLLC_MISC_3_0, 0x5d4 */
-    uint32_t plla_misc2;            /* _PLLA_MISC2_0, 0x5d8 */
-    uint32_t _0x5dc[2];
-    uint32_t pllc4_out;             /* _PLLC4_OUT_0, 0x5e4 */
-    uint32_t pllmb_base;            /* _PLLMB_BASE_0, 0x5e8 */
-    uint32_t pllmb_misc1;           /* _PLLMB_MISC1_0, 0x5ec */
-    uint32_t pllx_misc4;            /* _PLLX_MISC_4_0, 0x5f0 */
-    uint32_t pllx_misc5;            /* _PLLX_MISC_5_0, 0x5f4 */
-    uint32_t _0x5f8[2];
-
-    uint32_t clk_source_xusb_core_host;             /* _CLK_SOURCE_XUSB_CORE_HOST_0,    0x600 */
-    uint32_t clk_source_xusb_falcon;                /* _CLK_SOURCE_XUSB_FALCON_0,    0x604 */
-    uint32_t clk_source_xusb_fs;                    /* _CLK_SOURCE_XUSB_FS_0,    0x608 */
-    uint32_t clk_source_xusb_core_dev;              /* _CLK_SOURCE_XUSB_CORE_DEV_0,    0x60c */
-    uint32_t clk_source_xusb_ss;                    /* _CLK_SOURCE_XUSB_SS_0,    0x610 */
-    uint32_t clk_source_cilab;                      /* _CLK_SOURCE_CILAB_0,    0x614 */
-    uint32_t clk_source_cilcd;                      /* _CLK_SOURCE_CILCD_0,    0x618 */
-    uint32_t clk_source_cilef;                      /* _CLK_SOURCE_CILEF_0,    0x61c */
-    uint32_t clk_source_dsia_lp;                    /* _CLK_SOURCE_DSIA_LP_0,    0x620 */
-    uint32_t clk_source_dsib_lp;                    /* _CLK_SOURCE_DSIB_LP_0,    0x624 */
-    uint32_t clk_source_entropy;                    /* _CLK_SOURCE_ENTROPY_0,    0x628 */
-    uint32_t clk_source_dvfs_ref;                   /* _CLK_SOURCE_DVFS_REF_0,    0x62c */
-    uint32_t clk_source_dvfs_soc;                   /* _CLK_SOURCE_DVFS_SOC_0,    0x630 */
-    uint32_t _0x634[3];
-    uint32_t clk_source_emc_latency;                /* _CLK_SOURCE_EMC_LATENCY_0,    0x640 */
-    uint32_t clk_source_soc_therm;                  /* _CLK_SOURCE_SOC_THERM_0,    0x644 */
-    uint32_t _0x648;
-    uint32_t clk_source_dmic1;                      /* _CLK_SOURCE_DMIC1_0,    0x64c */
-    uint32_t clk_source_dmic2;                      /* _CLK_SOURCE_DMIC2_0,    0x650 */
-    uint32_t _0x654;
-    uint32_t clk_source_vi_sensor2;                 /* _CLK_SOURCE_VI_SENSOR2_0,    0x658 */
-    uint32_t clk_source_i2c6;                       /* _CLK_SOURCE_I2C6_0,    0x65c */
-    uint32_t clk_source_mipibif;                    /* _CLK_SOURCE_MIPIBIF_0,    0x660 */
-    uint32_t clk_source_emc_dll;                    /* _CLK_SOURCE_EMC_DLL_0,    0x664 */
-    uint32_t _0x668;
-    uint32_t clk_source_uart_fst_mipi_cal;          /* _CLK_SOURCE_UART_FST_MIPI_CAL_0,    0x66c */
-    uint32_t _0x670[2];
-    uint32_t clk_source_vic;                        /* _CLK_SOURCE_VIC_0,    0x678 */
-
-    uint32_t pllp_outc;                             /* _PLLP_OUTC_0, 0x67c */
-    uint32_t pllp_misc1;                            /* _PLLP_MISC1_0, 0x680 */
-    uint32_t _0x684[2];
-    uint32_t emc_div_clk_shaper_ctrl;               /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */
-    uint32_t emc_pllc_shaper_ctrl;                  /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */
-
-    uint32_t clk_source_sdmmc_legacy_tm;            /* _CLK_SOURCE_SDMMC_LEGACY_TM_0,    0x694 */
-    uint32_t clk_source_nvdec;                      /* _CLK_SOURCE_NVDEC_0,    0x698 */
-    uint32_t clk_source_nvjpg;                      /* _CLK_SOURCE_NVJPG_0,    0x69c */
-    uint32_t clk_source_nvenc;                      /* _CLK_SOURCE_NVENC_0,    0x6a0 */
-
-    uint32_t plla1_base;                            /* _PLLA1_BASE_0, 0x6a4 */
-    uint32_t plla1_misc0;                           /* _PLLA1_MISC_0_0, 0x6a8 */
-    uint32_t plla1_misc1;                           /* _PLLA1_MISC_1_0, 0x6ac */
-    uint32_t plla1_misc2;                           /* _PLLA1_MISC_2_0, 0x6b0 */
-    uint32_t plla1_misc3;                           /* _PLLA1_MISC_3_0, 0x6b4 */
-    uint32_t audio_sync_clk_dmic3;                  /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
-
-    uint32_t clk_source_dmic3;                      /* _CLK_SOURCE_DMIC3_0,    0x6bc */
-    uint32_t clk_source_ape;                        /* _CLK_SOURCE_APE_0,    0x6c0 */
-    uint32_t clk_source_qspi;                       /* _CLK_SOURCE_QSPI_0,    0x6c4 */
-    uint32_t clk_source_vi_i2c;                     /* _CLK_SOURCE_VI_I2C_0,    0x6c8 */
-    uint32_t clk_source_usb2_hsic_trk;              /* _CLK_SOURCE_USB2_HSIC_TRK_0,    0x6cc */
-    uint32_t clk_source_pex_sata_usb_rx_byp;        /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0,    0x6d0 */
-    uint32_t clk_source_maud;                       /* _CLK_SOURCE_MAUD_0,    0x6d4 */
-    uint32_t clk_source_tsecb;                      /* _CLK_SOURCE_TSECB_0,    0x6d8 */
-
-    uint32_t clk_cpug_misc1;                        /* _CLK_CPUG_MISC1_0, 0x6dc */
-    uint32_t aclk_burst_policy;                     /* _ACLK_BURST_POLICY_0, 0x6e0 */
-    uint32_t super_aclk_divider;                    /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
-
-    uint32_t nvenc_super_clk_divider;               /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
-    uint32_t vi_super_clk_divider;                  /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
-    uint32_t vic_super_clk_divider;                 /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
-    uint32_t nvdec_super_clk_divider;               /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */
-    uint32_t isp_super_clk_divider;                 /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */
-    uint32_t ispb_super_clk_divider;                /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */
-    uint32_t nvjpg_super_clk_divider;               /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */
-    uint32_t se_super_clk_divider;                  /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
-    uint32_t tsec_super_clk_divider;                /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
-    uint32_t tsecb_super_clk_divider;               /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
-
-    uint32_t clk_source_uartape;                    /* _CLK_SOURCE_UARTAPE_0, 0x710 */
-    uint32_t clk_cpug_misc2;                        /* _CLK_CPUG_MISC2_0, 0x714 */
-    uint32_t clk_source_dbgapb;                     /* _CLK_SOURCE_DBGAPB_0, 0x718 */
-    uint32_t clk_ccplex_cc4_ret_clk_enb;            /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */
-    uint32_t actmon_cpu_clk;                        /* _ACTMON_CPU_CLK_0, 0x720 */
-    uint32_t clk_source_emc_safe;                   /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */
-    uint32_t sdmmc2_pllc4_out0_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */
-    uint32_t sdmmc2_pllc4_out1_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */
-    uint32_t sdmmc2_pllc4_out2_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */
-    uint32_t sdmmc2_div_clk_shaper_ctrl;            /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */
-    uint32_t sdmmc4_pllc4_out0_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
-    uint32_t sdmmc4_pllc4_out1_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
-    uint32_t sdmmc4_pllc4_out2_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
-    uint32_t sdmmc4_div_clk_shaper_ctrl;            /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */    
-} tegra_car_t;
-
-static inline volatile tegra_car_t *car_get_regs(void) {
-    return (volatile tegra_car_t *)CAR_BASE;
-}
-
-void clk_enable(CarDevice dev);
-void clk_disable(CarDevice dev);
-void rst_enable(CarDevice dev);
-void rst_disable(CarDevice dev);
-
-void clkrst_enable(CarDevice dev);
-void clkrst_disable(CarDevice dev);
-void clkrst_reboot(CarDevice dev);
-
-void clkrst_enable_fuse_regs(bool enable);
-
-#endif

fusee/fusee-mtc/src/fuse.c

@@ -1,346 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-#include <vapours/ams_version.h>
-
-#include "car.h"
-#include "fuse.h"
-#include "pmc.h"
-#include "timers.h"
-
-/* Initialize the fuse driver */
-void fuse_init(void) {
-    /* Make all fuse registers visible, disable the private key and disable programming. */
-    clkrst_enable_fuse_regs(true);
-    fuse_disable_private_key();
-    fuse_disable_programming();
-}
-
-/* Disable access to the private key and set the TZ sticky bit. */
-void fuse_disable_private_key(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
-}
-
-/* Disable all fuse programming. */
-void fuse_disable_programming(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    fuse->FUSE_DISABLEREGPROGRAM = 1;
-}
-
-/* Enable power to the fuse hardware array. */
-void fuse_enable_power(void) {
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    pmc->fuse_control &= ~(0x200);      /* Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
-    mdelay(1);
-    pmc->fuse_control |= 0x100;         /* Set PMC_FUSE_CTRL_PS18_LATCH_SET. */
-    mdelay(1);
-}
-
-/* Disable power to the fuse hardware array. */
-void fuse_disable_power(void) {
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    pmc->fuse_control &= ~(0x100);      /* Clear PMC_FUSE_CTRL_PS18_LATCH_SET. */
-    mdelay(1);
-    pmc->fuse_control |= 0x200;         /* Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
-    mdelay(1);
-}
-
-/* Wait for the fuse driver to go idle. */
-static void fuse_wait_idle(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    uint32_t ctrl_val = 0;
-
-    /* Wait for STATE_IDLE */
-    while ((ctrl_val & (0xF0000)) != 0x40000) {
-        ctrl_val = fuse->FUSE_FUSECTRL;
-    }
-}
-
-/* Read a fuse from the hardware array. */
-uint32_t fuse_hw_read(uint32_t addr) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Program the target address. */
-    fuse->FUSE_FUSEADDR = addr;
-
-    /* Enable read operation in control register. */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x1;    /* Set READ command. */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    return fuse->FUSE_FUSERDATA;
-}
-
-/* Write a fuse in the hardware array. */
-void fuse_hw_write(uint32_t value, uint32_t addr) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Program the target address and value. */
-    fuse->FUSE_FUSEADDR = addr;
-    fuse->FUSE_FUSEWDATA = value;
-
-    /* Enable write operation in control register. */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x2;    /* Set WRITE command. */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-}
-
-/* Sense the fuse hardware array into the fuse cache. */
-void fuse_hw_sense(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Enable sense operation in control register */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x3;    /* Set SENSE_CTRL command */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-}
-
-/* Read the SKU info register. */
-uint32_t fuse_get_sku_info(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    return fuse_chip->FUSE_SKU_INFO;
-}
-
-/* Read the bootrom patch version. */
-uint32_t fuse_get_bootrom_patch_version(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
-}
-
-/* Read a spare bit register. */
-uint32_t fuse_get_spare_bit(uint32_t index) {
-    uint32_t soc_type = fuse_get_soc_type();
-    if (soc_type == 0) {
-        if (index < 32) {
-            volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs();
-            return fuse_chip->FUSE_SPARE_BIT[index];
-        }
-    } else if (soc_type == 1) {
-        if (index < 30) {
-            volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
-            return fuse_chip->FUSE_SPARE_BIT[index];
-        }
-    }
-    return 0;
-}
-
-/* Read a reserved ODM register. */
-uint32_t fuse_get_reserved_odm(uint32_t index) {
-    if (index < 8) {
-        volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-        return fuse_chip->FUSE_RESERVED_ODM0[index];
-    } else {
-        uint32_t soc_type = fuse_get_soc_type();
-        if (soc_type == 1) {
-            volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
-            if (index < 22) {
-                return fuse_chip->FUSE_RESERVED_ODM8[index - 8];
-            } else if (index < 25) {
-                return fuse_chip->FUSE_RESERVED_ODM22[index - 22];
-            } else if (index < 26) {
-                return fuse_chip->FUSE_RESERVED_ODM25;
-            } else if (index < 29) {
-                return fuse_chip->FUSE_RESERVED_ODM26[index - 26];
-            } else if (index < 30) {
-                return fuse_chip->FUSE_RESERVED_ODM29;
-            }
-        }
-    }
-    return 0;
-}
-
-/* Get the DramId. */
-uint32_t fuse_get_dram_id(void) {
-    return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
-}
-
-/* Derive the DeviceId. */
-uint64_t fuse_get_device_id(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-
-    uint64_t device_id = 0;
-    uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
-    uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
-    uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
-    uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0;
-    uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
-
-    uint64_t derived_lot_code = 0;
-    for (unsigned int i = 0; i < 5; i++) {
-        derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
-    }
-    derived_lot_code &= 0x03FFFFFF;
-
-    device_id |= y_coord << 0;
-    device_id |= x_coord << 9;
-    device_id |= wafer_id << 18;
-    device_id |= derived_lot_code << 24;
-    device_id |= fab_code << 50;
-
-    return device_id;
-}
-
-/* Derive the HardwareType with firmware specific checks. */
-uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) {
-    uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
-    uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
-
-    if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) {
-        volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-        uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1);
-
-        switch (hardware_type) {
-            case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3;
-            case 0x01: return 0;        /* HardwareType_Icosa */
-            case 0x02: return 1;        /* HardwareType_Copper */
-            default:   return 3;        /* HardwareType_Undefined */
-        }
-    } else {
-        hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
-
-        if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
-            switch (hardware_type) {
-                case 0x01: return 0;        /* HardwareType_Icosa */
-                case 0x02: return 1;        /* HardwareType_Copper */
-                case 0x04: return 3;        /* HardwareType_Iowa */
-                default:   return 4;        /* HardwareType_Undefined */
-            }
-        } else {
-            if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) {
-                switch (hardware_type) {
-                    case 0x01: return 0;        /* HardwareType_Icosa */
-                    case 0x02: return 4;        /* HardwareType_Calcio */
-                    case 0x04: return 3;        /* HardwareType_Iowa */
-                    case 0x08: return 2;        /* HardwareType_Hoag */
-                    default:   return 0xF;      /* HardwareType_Undefined */
-                }
-            } else {
-                switch (hardware_type) {
-                    case 0x01: return 0;        /* HardwareType_Icosa */
-                    case 0x02: return 4;        /* HardwareType_Calcio */
-                    case 0x04: return 3;        /* HardwareType_Iowa */
-                    case 0x08: return 2;        /* HardwareType_Hoag */
-                    case 0x10: return 5;        /* HardwareType_Five */
-                    default:   return 0xF;      /* HardwareType_Undefined */
-                }
-            }
-        }
-    }
-}
-
-/* Derive the HardwareType. */
-uint32_t fuse_get_hardware_type(void) {
-    return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT);
-}
-
-/* Derive the HardwareState. */
-uint32_t fuse_get_hardware_state(void) {
-    uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
-    uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
-
-    switch (hardware_state) {
-        case 0x03: return 0;        /* HardwareState_Development */
-        case 0x04: return 1;        /* HardwareState_Production */
-        default:   return 2;        /* HardwareState_Undefined */
-    }
-}
-
-/* Derive the 16-byte HardwareInfo and copy to output buffer. */
-void fuse_get_hardware_info(void *dst) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    uint32_t hw_info[0x4];
-
-    uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
-    uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
-    uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
-    uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
-    uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0;
-    uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF;
-    uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
-    uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF;
-
-    /* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
-    hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved));
-    hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
-    hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
-    hw_info[3] = (uint32_t)(vendor_code);
-
-    memcpy(dst, hw_info, 0x10);
-}
-
-/* Check if have a new ODM fuse format. */
-bool fuse_is_new_format(void) {
-    return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2));
-}
-
-/* Get the DeviceUniqueKeyGeneration. */
-uint32_t fuse_get_device_unique_key_generation(void) {
-    if (fuse_is_new_format()) {
-        return (fuse_get_reserved_odm(2) & 0x1F);
-    } else {
-        return 0;
-    }
-}
-
-/* Get the SocType from the HardwareType. */
-uint32_t fuse_get_soc_type(void) {
-    switch (fuse_get_hardware_type()) {
-        case 0:
-        case 1:
-            return 0;           /* SocType_Erista */
-        case 3:
-        case 2:
-        case 4:
-        case 5:
-            return 1;           /* SocType_Mariko */
-        default:
-            return 0xF;         /* SocType_Undefined */
-    }
-}
-
-/* Get the Regulator type. */
-uint32_t fuse_get_regulator(void) {
-    if (fuse_get_soc_type() == 1) {
-        return ((fuse_get_reserved_odm(28) & 1) + 1);   /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */
-    } else {
-        return 0;               /* Regulator_Erista_Max77621 */
-    }
-}

fusee/fusee-mtc/src/fuse.h

@@ -1,484 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_FUSE_H
-#define FUSEE_FUSE_H
-
-#define FUSE_BASE 0x7000F800
-#define FUSE_CHIP_BASE (FUSE_BASE + 0x98)
-#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
-#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
-
-typedef struct {
-    uint32_t FUSE_FUSECTRL;
-    uint32_t FUSE_FUSEADDR;
-    uint32_t FUSE_FUSERDATA;
-    uint32_t FUSE_FUSEWDATA;
-    uint32_t FUSE_FUSETIME_RD1;
-    uint32_t FUSE_FUSETIME_RD2;
-    uint32_t FUSE_FUSETIME_PGM1;
-    uint32_t FUSE_FUSETIME_PGM2;
-    uint32_t FUSE_PRIV2INTFC_START;
-    uint32_t FUSE_FUSEBYPASS;
-    uint32_t FUSE_PRIVATEKEYDISABLE;
-    uint32_t FUSE_DISABLEREGPROGRAM;
-    uint32_t FUSE_WRITE_ACCESS_SW;
-    uint32_t FUSE_PWR_GOOD_SW;
-    uint32_t _0x38;
-    uint32_t FUSE_PRIV2RESHIFT;
-    uint32_t _0x40[0x3];
-    uint32_t FUSE_FUSETIME_RD3;
-    uint32_t _0x50[0xC];
-    uint32_t FUSE_PRIVATE_KEY0_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY1_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY2_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY3_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY4_NONZERO;
-    uint32_t _0x94;
-} tegra_fuse_t;
-
-typedef struct {
-    uint32_t _0x98[0x1A];
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t _0x11C[0x3];
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t _0x144;
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t _0x18C;
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t _0x224;
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t _0x238[0x3];
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t _0x268[0x5];
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t _0x294;
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC[0x5];
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t _0x324[0x5];
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x20];
-} tegra_fuse_chip_common_t;
-
-typedef struct {
-    uint32_t _0x98[0x1A];
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t _0x11C[0x3];
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t _0x144;
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t _0x18C;
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t FUSE_SATA_CALIB;               /* Erista only. */
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t _0x238[0x3];
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t FUSE_PKC_DISABLE;              /* Erista only. */
-    uint32_t _0x26C[0x4];
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t _0x294;
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC[0x5];
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t FUSE_OPT_RAM_SVOP_DP;          /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_PDP;         /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_REG;         /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_SP;          /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_SMPDP;       /* Erista only. */
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x20];
-} tegra_fuse_chip_erista_t;
-
-typedef struct {
-    uint32_t FUSE_RESERVED_ODM8[0xE];       /* Mariko only. */
-    uint32_t FUSE_KEK[0x4];                 /* Mariko only. */
-    uint32_t FUSE_BEK[0x4];                 /* Mariko only. */
-    uint32_t _0xF0;                         /* Mariko only. */
-    uint32_t _0xF4;                         /* Mariko only. */
-    uint32_t _0xF8;                         /* Mariko only. */
-    uint32_t _0xFC;                         /* Mariko only. */
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t FUSE_RESERVED_ODM22[0x3];      /* Mariko only. */
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t FUSE_RESERVED_ODM25;           /* Mariko only. */
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t FUSE_OPT_SECURE_SCC_DIS;       /* Mariko only. */
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;                        /* Mariko only. */
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t _0x224;                        /* Mariko only. */
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t FUSE_RESERVED_ODM26[0x3];      /* Mariko only. */
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t FUSE_BOOT_SECURITY_INFO;       /* Mariko only. */
-    uint32_t _0x26C;                        /* Mariko only. */
-    uint32_t _0x270;                        /* Mariko only. */
-    uint32_t _0x274;                        /* Mariko only. */
-    uint32_t _0x278;                        /* Mariko only. */
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t FUSE_RESERVED_ODM29;           /* Mariko only. */
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC;
-    uint32_t _0x2B0;                        /* Mariko only. */
-    uint32_t _0x2B4;                        /* Mariko only. */
-    uint32_t _0x2B8;                        /* Mariko only. */
-    uint32_t _0x2BC;                        /* Mariko only. */
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t _0x324;                        /* Mariko only. */
-    uint32_t _0x328;                        /* Mariko only. */
-    uint32_t _0x32C;                        /* Mariko only. */
-    uint32_t _0x330;                        /* Mariko only. */
-    uint32_t _0x334;                        /* Mariko only. */
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x1E];
-} tegra_fuse_chip_mariko_t;
-
-static inline volatile tegra_fuse_t *fuse_get_regs(void)
-{
-    return (volatile tegra_fuse_t *)FUSE_BASE;
-}
-
-static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE;
-}
-
-static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE;
-}
-
-static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE;
-}
-
-void fuse_init(void);
-void fuse_disable_programming(void);
-void fuse_disable_private_key(void);
-void fuse_enable_power(void);
-void fuse_disable_power(void);
-
-uint32_t fuse_get_sku_info(void);
-uint32_t fuse_get_spare_bit(uint32_t index);
-uint32_t fuse_get_reserved_odm(uint32_t index);
-uint32_t fuse_get_bootrom_patch_version(void);
-uint64_t fuse_get_device_id(void);
-uint32_t fuse_get_dram_id(void);
-uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
-uint32_t fuse_get_hardware_type(void);
-uint32_t fuse_get_retail_type(void);
-void fuse_get_hardware_info(void *dst);
-bool fuse_is_new_format(void);
-uint32_t fuse_get_device_unique_key_generation(void);
-uint32_t fuse_get_soc_type(void);
-uint32_t fuse_get_regulator(void);
-
-uint32_t fuse_hw_read(uint32_t addr);
-void fuse_hw_write(uint32_t value, uint32_t addr);
-void fuse_hw_sense(void);
-
-#endif

fusee/fusee-mtc/src/init.c

@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
-#include <stddef.h>
-#include <string.h>
-#include <malloc.h>
-#include <sys/iosupport.h>
-#include "stage2.h"
-#include "utils.h"
-
-void __libc_init_array(void);
-void __libc_fini_array(void);
-
-extern uint8_t __bss_start__[], __bss_end__[];
-extern uint8_t __heap_start__[], __heap_end__[];
-
-extern char *fake_heap_start;
-extern char *fake_heap_end;
-
-int __program_argc;
-void **__program_argv;
-
-void __program_exit(int rc);
-static void __program_parse_argc_argv(int argc, char *argdata);
-static void __program_cleanup_argv(void);
-
-static void __program_init_heap(void) {
-    fake_heap_start = (char*)__heap_start__;
-    fake_heap_end   = (char*)__heap_end__;
-}
-
-static void __program_init_newlib_hooks(void) {
-    __syscalls.exit = __program_exit; /* For exit, etc. */
-}
-
-void __program_init(int argc, char *argdata) {
-    /* Zero-fill the .bss section */
-    memset(__bss_start__, 0, __bss_end__ - __bss_start__);
-    
-    __program_init_heap();
-    __program_init_newlib_hooks();
-    __program_parse_argc_argv(argc, argdata);
-    __libc_init_array();
-}
-
-void __program_exit(int rc) {
-    __libc_fini_array();
-    __program_cleanup_argv();
-}
-
-static void __program_parse_argc_argv(int argc, char *argdata) {
-    __program_argc = argc;
-
-    __program_argv = malloc(argc * sizeof(void **));
-    if (__program_argv == NULL) {
-        generic_panic();
-    }
-    
-    __program_argv[0] = malloc(sizeof(stage2_mtc_args_t));
-    if (__program_argv[0] == NULL) {
-        generic_panic();
-    }
-    memcpy(__program_argv[0], argdata, sizeof(stage2_mtc_args_t));
-}
-
-static void __program_cleanup_argv(void) {
-    for (int i = 0; i < __program_argc; i++) {
-        free(__program_argv[i]);
-        __program_argv[i] = NULL;
-    }
-    free(__program_argv);
-}

fusee/fusee-mtc/src/main.c

@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <string.h>
-#include "mtc.h"
-#include "stage2.h"
-#include "../../../fusee/common/display/video_fb.h"
-
-static void *g_framebuffer;
-static __attribute__((__aligned__(0x200))) stage2_mtc_args_t g_mtc_args_store;
-static stage2_mtc_args_t *g_mtc_args;
-
-/* Allow for main(int argc, void **argv) signature. */
-#pragma GCC diagnostic ignored "-Wmain"
-
-int main(int argc, void **argv) {
-    ScreenLogLevel log_level = SCREEN_LOG_LEVEL_NONE;
-    
-    /* Check argc. */
-    if (argc != MTC_ARGC) {
-        return 1;
-    }
-    
-    /* Extract arguments from argv. */
-    g_mtc_args = &g_mtc_args_store;
-    memcpy(g_mtc_args, (stage2_mtc_args_t *)argv[MTC_ARGV_ARGUMENT_STRUCT], sizeof(*g_mtc_args));
-    log_level = g_mtc_args->log_level;
-    
-    /* Override the global logging level. */
-    log_set_log_level(log_level);
-    
-    if (log_level != SCREEN_LOG_LEVEL_NONE) {
-        /* Set framebuffer address. */
-        g_framebuffer = (void *)0xC0000000;
-    
-        /* Zero-fill the framebuffer and register it as printk provider. */
-        video_init(g_framebuffer);
-    }
-    
-    /* Train DRAM. */
-    train_dram();
-
-    return 0;
-}

fusee/fusee-mtc/src/mc.c

@@ -1,167 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "mc.h"
-#include "car.h"
-#include "timers.h"
-
-void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock)
-{
-    MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom;
-    MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
-    
-    if (lock)
-        MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1;
-}
-
-void mc_config_carveout()
-{
-    *(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
-    
-    MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
-
-    mc_config_tsec_carveout(0, 0, true);
-
-    MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
-
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
-}
-
-void mc_config_carveout_finalize()
-{
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
-}
-
-void mc_enable_ahb_redirect()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000);
-    
-    MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000;
-    MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000;
-}
-
-void mc_disable_ahb_redirect()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    
-    MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000;
-    MAKE_MC_REG(MC_IRAM_TOM) = 0;
-    
-    car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF;
-}
-
-void mc_enable()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    
-    /* Set EMC clock source. */
-    car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000);
-    
-    /* Enable MIPI CAL clock. */
-    car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000);
-    
-    /* Enable MC clock. */
-    car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1);
-
-    /* Enable EMC DLL clock. */
-    car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000);
-    
-    /* Clear EMC and MC reset. */
-    car->rst_dev_h_set = 0x2000001; 
-    udelay(5);
-
-    mc_disable_ahb_redirect();
-}

fusee/fusee-mtc/src/mc.h

@@ -1,606 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_MC_H_
-#define FUSEE_MC_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#define MC_BASE  0x70019000
-#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
-
-#define MC_INTSTATUS                                            0x0
-#define MC_INTMASK                                              0x4
-#define MC_ERR_STATUS                                           0x8
-#define MC_ERR_ADR                                              0xc
-#define MC_SMMU_CONFIG                                          0x10
-#define MC_SMMU_TLB_CONFIG                                      0x14
-#define MC_SMMU_PTC_CONFIG                                      0x18
-#define MC_SMMU_PTB_ASID                                        0x1c
-#define MC_SMMU_PTB_DATA                                        0x20
-#define MC_SMMU_TLB_FLUSH                                       0x30
-#define MC_SMMU_PTC_FLUSH                                       0x34
-#define MC_SMMU_ASID_SECURITY                                   0x38
-#define MC_SMMU_ASID_SECURITY_1                                 0x3c
-#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
-#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
-#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
-#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
-#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
-#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
-#define MC_SMMU_AFI_ASID                                        0x238
-#define MC_SMMU_AVPC_ASID                                       0x23c
-#define MC_SMMU_TSEC_ASID                                       0x294
-#define MC_SMMU_PPCS1_ASID                                      0x298
-#define MC_SMMU_TRANSLATION_ENABLE_0                            0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1                            0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2                            0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3                            0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4                            0xb98
-#define MC_PCFIFO_CLIENT_CONFIG0                                0xdd0
-#define MC_PCFIFO_CLIENT_CONFIG1                                0xdd4
-#define MC_PCFIFO_CLIENT_CONFIG2                                0xdd8
-#define MC_PCFIFO_CLIENT_CONFIG3                                0xddc
-#define MC_PCFIFO_CLIENT_CONFIG4                                0xde0
-#define MC_EMEM_CFG                                             0x50
-#define MC_EMEM_ADR_CFG                                         0x54
-#define MC_EMEM_ADR_CFG_DEV0                                    0x58
-#define MC_EMEM_ADR_CFG_DEV1                                    0x5c
-#define MC_EMEM_ADR_CFG_CHANNEL_MASK                            0x60
-#define MC_EMEM_ADR_CFG_BANK_MASK_0                             0x64
-#define MC_EMEM_ADR_CFG_BANK_MASK_1                             0x68
-#define MC_EMEM_ADR_CFG_BANK_MASK_2                             0x6c
-#define MC_SECURITY_CFG0                                        0x70
-#define MC_SECURITY_CFG1                                        0x74
-#define MC_SECURITY_CFG3                                        0x9bc
-#define MC_SECURITY_RSV                                         0x7c
-#define MC_EMEM_ARB_CFG                                         0x90
-#define MC_EMEM_ARB_OUTSTANDING_REQ                             0x94
-#define MC_EMEM_ARB_TIMING_RCD                                  0x98
-#define MC_EMEM_ARB_TIMING_RP                                   0x9c
-#define MC_EMEM_ARB_TIMING_RC                                   0xa0
-#define MC_EMEM_ARB_TIMING_RAS                                  0xa4
-#define MC_EMEM_ARB_TIMING_FAW                                  0xa8
-#define MC_EMEM_ARB_TIMING_RRD                                  0xac
-#define MC_EMEM_ARB_TIMING_RAP2PRE                              0xb0
-#define MC_EMEM_ARB_TIMING_WAP2PRE                              0xb4
-#define MC_EMEM_ARB_TIMING_R2R                                  0xb8
-#define MC_EMEM_ARB_TIMING_W2W                                  0xbc
-#define MC_EMEM_ARB_TIMING_R2W                                  0xc0
-#define MC_EMEM_ARB_TIMING_W2R                                  0xc4
-#define MC_EMEM_ARB_TIMING_RFCPB                                0x6c0
-#define MC_EMEM_ARB_TIMING_CCDMW                                0x6c4
-#define MC_EMEM_ARB_REFPB_HP_CTRL                               0x6f0
-#define MC_EMEM_ARB_REFPB_BANK_CTRL                             0x6f4
-#define MC_EMEM_ARB_DA_TURNS                                    0xd0
-#define MC_EMEM_ARB_DA_COVERS                                   0xd4
-#define MC_EMEM_ARB_MISC0                                       0xd8
-#define MC_EMEM_ARB_MISC1                                       0xdc
-#define MC_EMEM_ARB_MISC2                                       0xc8
-#define MC_EMEM_ARB_RING1_THROTTLE                              0xe0
-#define MC_EMEM_ARB_RING3_THROTTLE                              0xe4
-#define MC_EMEM_ARB_NISO_THROTTLE                               0x6b0
-#define MC_EMEM_ARB_OVERRIDE                                    0xe8
-#define MC_EMEM_ARB_RSV                                         0xec
-#define MC_CLKEN_OVERRIDE                                       0xf4
-#define MC_TIMING_CONTROL_DBG                                   0xf8
-#define MC_TIMING_CONTROL                                       0xfc
-#define MC_STAT_CONTROL                                         0x100
-#define MC_STAT_STATUS                                          0x104
-#define MC_STAT_EMC_CLOCK_LIMIT                                 0x108
-#define MC_STAT_EMC_CLOCK_LIMIT_MSBS                            0x10c
-#define MC_STAT_EMC_CLOCKS                                      0x110
-#define MC_STAT_EMC_CLOCKS_MSBS                                 0x114
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO                    0x118
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO                    0x158
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI                    0x11c
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI                    0x15c
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER                 0xa20
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER                 0xa24
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO            0x198
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO            0x1a8
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI            0x19c
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI            0x1ac
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER         0xa28
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER         0xa2c
-#define MC_STAT_EMC_FILTER_SET0_ASID                            0x1a0
-#define MC_STAT_EMC_FILTER_SET1_ASID                            0x1b0
-#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT                     0x120
-#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT                     0x160
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_0                        0x128
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_0                        0x168
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_1                        0x12c
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_1                        0x16c
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_2                        0x130
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_2                        0x170
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_3                        0x134
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_4                        0xb88
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_3                        0x174
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_4                        0xb8c
-#define MC_STAT_EMC_SET0_COUNT                                  0x138
-#define MC_STAT_EMC_SET0_COUNT_MSBS                             0x13c
-#define MC_STAT_EMC_SET1_COUNT                                  0x178
-#define MC_STAT_EMC_SET1_COUNT_MSBS                             0x17c
-#define MC_STAT_EMC_SET0_SLACK_ACCUM                            0x140
-#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS                       0x144
-#define MC_STAT_EMC_SET1_SLACK_ACCUM                            0x180
-#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS                       0x184
-#define MC_STAT_EMC_SET0_HISTO_COUNT                            0x148
-#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS                       0x14c
-#define MC_STAT_EMC_SET1_HISTO_COUNT                            0x188
-#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS                       0x18c
-#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED                 0x150
-#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED                 0x190
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT                       0x1b8
-#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS                   0x1bc
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT                       0x1c8
-#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS                   0x1cc
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT            0x1c0
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT            0x1d0
-#define MC_CLIENT_HOTRESET_CTRL                                 0x200
-#define MC_CLIENT_HOTRESET_CTRL_1                               0x970
-#define MC_CLIENT_HOTRESET_STATUS                               0x204
-#define MC_CLIENT_HOTRESET_STATUS_1                             0x974
-#define MC_EMEM_ARB_ISOCHRONOUS_0                               0x208
-#define MC_EMEM_ARB_ISOCHRONOUS_1                               0x20c
-#define MC_EMEM_ARB_ISOCHRONOUS_2                               0x210
-#define MC_EMEM_ARB_ISOCHRONOUS_3                               0x214
-#define MC_EMEM_ARB_ISOCHRONOUS_4                               0xb94
-#define MC_EMEM_ARB_HYSTERESIS_0                                0x218
-#define MC_EMEM_ARB_HYSTERESIS_1                                0x21c
-#define MC_EMEM_ARB_HYSTERESIS_2                                0x220
-#define MC_EMEM_ARB_HYSTERESIS_3                                0x224
-#define MC_EMEM_ARB_HYSTERESIS_4                                0xb84
-#define MC_EMEM_ARB_DHYSTERESIS_0                               0xbb0
-#define MC_EMEM_ARB_DHYSTERESIS_1                               0xbb4
-#define MC_EMEM_ARB_DHYSTERESIS_2                               0xbb8
-#define MC_EMEM_ARB_DHYSTERESIS_3                               0xbbc
-#define MC_EMEM_ARB_DHYSTERESIS_4                               0xbc0
-#define MC_EMEM_ARB_DHYST_CTRL                                  0xbcc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0                        0xbd0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1                        0xbd4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2                        0xbd8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3                        0xbdc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4                        0xbe0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5                        0xbe4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6                        0xbe8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7                        0xbec
-#define MC_RESERVED_RSV                                         0x3fc
-#define MC_DISB_EXTRA_SNAP_LEVELS                               0x408
-#define MC_APB_EXTRA_SNAP_LEVELS                                0x2a4
-#define MC_AHB_EXTRA_SNAP_LEVELS                                0x2a0
-#define MC_USBD_EXTRA_SNAP_LEVELS                               0xa18
-#define MC_ISP_EXTRA_SNAP_LEVELS                                0xa08
-#define MC_AUD_EXTRA_SNAP_LEVELS                                0xa10
-#define MC_MSE_EXTRA_SNAP_LEVELS                                0x40c
-#define MC_GK2_EXTRA_SNAP_LEVELS                                0xa40
-#define MC_A9AVPPC_EXTRA_SNAP_LEVELS                            0x414
-#define MC_FTOP_EXTRA_SNAP_LEVELS                               0x2bc
-#define MC_JPG_EXTRA_SNAP_LEVELS                                0xa3c
-#define MC_HOST_EXTRA_SNAP_LEVELS                               0xa14
-#define MC_SAX_EXTRA_SNAP_LEVELS                                0x2c0
-#define MC_DIS_EXTRA_SNAP_LEVELS                                0x2ac
-#define MC_VICPC_EXTRA_SNAP_LEVELS                              0xa1c
-#define MC_HDAPC_EXTRA_SNAP_LEVELS                              0xa48
-#define MC_AVP_EXTRA_SNAP_LEVELS                                0x2a8
-#define MC_USBX_EXTRA_SNAP_LEVELS                               0x404
-#define MC_PCX_EXTRA_SNAP_LEVELS                                0x2b8
-#define MC_SD_EXTRA_SNAP_LEVELS                                 0xa04
-#define MC_DFD_EXTRA_SNAP_LEVELS                                0xa4c
-#define MC_VE_EXTRA_SNAP_LEVELS                                 0x2d8
-#define MC_GK_EXTRA_SNAP_LEVELS                                 0xa00
-#define MC_VE2_EXTRA_SNAP_LEVELS                                0x410
-#define MC_SDM_EXTRA_SNAP_LEVELS                                0xa44
-#define MC_VIDEO_PROTECT_BOM                                    0x648
-#define MC_VIDEO_PROTECT_SIZE_MB                                0x64c
-#define MC_VIDEO_PROTECT_BOM_ADR_HI                             0x978
-#define MC_VIDEO_PROTECT_REG_CTRL                               0x650
-#define MC_ERR_VPR_STATUS                                       0x654
-#define MC_ERR_VPR_ADR                                          0x658
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE                           0x418
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE1                          0x590
-#define MC_IRAM_BOM                                             0x65c
-#define MC_IRAM_TOM                                             0x660
-#define MC_IRAM_ADR_HI                                          0x980
-#define MC_IRAM_REG_CTRL                                        0x964
-#define MC_EMEM_CFG_ACCESS_CTRL                                 0x664
-#define MC_TZ_SECURITY_CTRL                                     0x668
-#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3                       0x66c
-#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO                        0x6b4
-#define MC_EMEM_ARB_RING0_THROTTLE_MASK                         0x6bc
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK                          0x6b8
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1                        0xb80
-#define MC_SEC_CARVEOUT_BOM                                     0x670
-#define MC_SEC_CARVEOUT_SIZE_MB                                 0x674
-#define MC_SEC_CARVEOUT_ADR_HI                                  0x9d4
-#define MC_SEC_CARVEOUT_REG_CTRL                                0x678
-#define MC_ERR_SEC_STATUS                                       0x67c
-#define MC_ERR_SEC_ADR                                          0x680
-#define MC_PC_IDLE_CLOCK_GATE_CONFIG                            0x684
-#define MC_STUTTER_CONTROL                                      0x688
-#define MC_RESERVED_RSV_1                                       0x958
-#define MC_DVFS_PIPE_SELECT                                     0x95c
-#define MC_AHB_PTSA_MIN                                         0x4e0
-#define MC_AUD_PTSA_MIN                                         0x54c
-#define MC_MLL_MPCORER_PTSA_RATE                                0x44c
-#define MC_RING2_PTSA_RATE                                      0x440
-#define MC_USBD_PTSA_RATE                                       0x530
-#define MC_USBX_PTSA_MIN                                        0x528
-#define MC_USBD_PTSA_MIN                                        0x534
-#define MC_APB_PTSA_MAX                                         0x4f0
-#define MC_JPG_PTSA_RATE                                        0x584
-#define MC_DIS_PTSA_MIN                                         0x420
-#define MC_AVP_PTSA_MAX                                         0x4fc
-#define MC_AVP_PTSA_RATE                                        0x4f4
-#define MC_RING1_PTSA_MIN                                       0x480
-#define MC_DIS_PTSA_MAX                                         0x424
-#define MC_SD_PTSA_MAX                                          0x4d8
-#define MC_MSE_PTSA_RATE                                        0x4c4
-#define MC_VICPC_PTSA_MIN                                       0x558
-#define MC_PCX_PTSA_MAX                                         0x4b4
-#define MC_ISP_PTSA_RATE                                        0x4a0
-#define MC_A9AVPPC_PTSA_MIN                                     0x48c
-#define MC_RING2_PTSA_MAX                                       0x448
-#define MC_AUD_PTSA_RATE                                        0x548
-#define MC_HOST_PTSA_MIN                                        0x51c
-#define MC_MLL_MPCORER_PTSA_MAX                                 0x454
-#define MC_SD_PTSA_MIN                                          0x4d4
-#define MC_RING1_PTSA_RATE                                      0x47c
-#define MC_JPG_PTSA_MIN                                         0x588
-#define MC_HDAPC_PTSA_MIN                                       0x62c
-#define MC_AVP_PTSA_MIN                                         0x4f8
-#define MC_JPG_PTSA_MAX                                         0x58c
-#define MC_VE_PTSA_MAX                                          0x43c
-#define MC_DFD_PTSA_MAX                                         0x63c
-#define MC_VICPC_PTSA_RATE                                      0x554
-#define MC_GK_PTSA_MAX                                          0x544
-#define MC_VICPC_PTSA_MAX                                       0x55c
-#define MC_SDM_PTSA_MAX                                         0x624
-#define MC_SAX_PTSA_RATE                                        0x4b8
-#define MC_PCX_PTSA_MIN                                         0x4b0
-#define MC_APB_PTSA_MIN                                         0x4ec
-#define MC_GK2_PTSA_MIN                                         0x614
-#define MC_PCX_PTSA_RATE                                        0x4ac
-#define MC_RING1_PTSA_MAX                                       0x484
-#define MC_HDAPC_PTSA_RATE                                      0x628
-#define MC_MLL_MPCORER_PTSA_MIN                                 0x450
-#define MC_GK2_PTSA_MAX                                         0x618
-#define MC_AUD_PTSA_MAX                                         0x550
-#define MC_GK2_PTSA_RATE                                        0x610
-#define MC_ISP_PTSA_MAX                                         0x4a8
-#define MC_DISB_PTSA_RATE                                       0x428
-#define MC_VE2_PTSA_MAX                                         0x49c
-#define MC_DFD_PTSA_MIN                                         0x638
-#define MC_FTOP_PTSA_RATE                                       0x50c
-#define MC_A9AVPPC_PTSA_RATE                                    0x488
-#define MC_VE2_PTSA_MIN                                         0x498
-#define MC_USBX_PTSA_MAX                                        0x52c
-#define MC_DIS_PTSA_RATE                                        0x41c
-#define MC_USBD_PTSA_MAX                                        0x538
-#define MC_A9AVPPC_PTSA_MAX                                     0x490
-#define MC_USBX_PTSA_RATE                                       0x524
-#define MC_FTOP_PTSA_MAX                                        0x514
-#define MC_HDAPC_PTSA_MAX                                       0x630
-#define MC_SD_PTSA_RATE                                         0x4d0
-#define MC_DFD_PTSA_RATE                                        0x634
-#define MC_FTOP_PTSA_MIN                                        0x510
-#define MC_SDM_PTSA_RATE                                        0x61c
-#define MC_AHB_PTSA_RATE                                        0x4dc
-#define MC_SMMU_SMMU_PTSA_MAX                                   0x460
-#define MC_RING2_PTSA_MIN                                       0x444
-#define MC_SDM_PTSA_MIN                                         0x620
-#define MC_APB_PTSA_RATE                                        0x4e8
-#define MC_MSE_PTSA_MIN                                         0x4c8
-#define MC_HOST_PTSA_RATE                                       0x518
-#define MC_VE_PTSA_RATE                                         0x434
-#define MC_AHB_PTSA_MAX                                         0x4e4
-#define MC_SAX_PTSA_MIN                                         0x4bc
-#define MC_SMMU_SMMU_PTSA_MIN                                   0x45c
-#define MC_ISP_PTSA_MIN                                         0x4a4
-#define MC_HOST_PTSA_MAX                                        0x520
-#define MC_SAX_PTSA_MAX                                         0x4c0
-#define MC_VE_PTSA_MIN                                          0x438
-#define MC_GK_PTSA_MIN                                          0x540
-#define MC_MSE_PTSA_MAX                                         0x4cc
-#define MC_DISB_PTSA_MAX                                        0x430
-#define MC_DISB_PTSA_MIN                                        0x42c
-#define MC_SMMU_SMMU_PTSA_RATE                                  0x458
-#define MC_VE2_PTSA_RATE                                        0x494
-#define MC_GK_PTSA_RATE                                         0x53c
-#define MC_PTSA_GRANT_DECREMENT                                 0x960
-#define MC_LATENCY_ALLOWANCE_AVPC_0                             0x2e4
-#define MC_LATENCY_ALLOWANCE_AXIAP_0                            0x3a0
-#define MC_LATENCY_ALLOWANCE_XUSB_1                             0x380
-#define MC_LATENCY_ALLOWANCE_ISP2B_0                            0x384
-#define MC_LATENCY_ALLOWANCE_SDMMCAA_0                          0x3bc
-#define MC_LATENCY_ALLOWANCE_SDMMCA_0                           0x3b8
-#define MC_LATENCY_ALLOWANCE_ISP2_0                             0x370
-#define MC_LATENCY_ALLOWANCE_SE_0                               0x3e0
-#define MC_LATENCY_ALLOWANCE_ISP2_1                             0x374
-#define MC_LATENCY_ALLOWANCE_DC_0                               0x2e8
-#define MC_LATENCY_ALLOWANCE_VIC_0                              0x394
-#define MC_LATENCY_ALLOWANCE_DCB_1                              0x2f8
-#define MC_LATENCY_ALLOWANCE_NVDEC_0                            0x3d8
-#define MC_LATENCY_ALLOWANCE_DCB_2                              0x2fc
-#define MC_LATENCY_ALLOWANCE_TSEC_0                             0x390
-#define MC_LATENCY_ALLOWANCE_DC_2                               0x2f0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB                  0x694
-#define MC_LATENCY_ALLOWANCE_PPCS_1                             0x348
-#define MC_LATENCY_ALLOWANCE_XUSB_0                             0x37c
-#define MC_LATENCY_ALLOWANCE_PPCS_0                             0x344
-#define MC_LATENCY_ALLOWANCE_TSECB_0                            0x3f0
-#define MC_LATENCY_ALLOWANCE_AFI_0                              0x2e0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B                   0x698
-#define MC_LATENCY_ALLOWANCE_DC_1                               0x2ec
-#define MC_LATENCY_ALLOWANCE_APE_0                              0x3dc
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C                   0x6a0
-#define MC_LATENCY_ALLOWANCE_A9AVP_0                            0x3a4
-#define MC_LATENCY_ALLOWANCE_GPU2_0                             0x3e8
-#define MC_LATENCY_ALLOWANCE_DCB_0                              0x2f4
-#define MC_LATENCY_ALLOWANCE_HC_1                               0x314
-#define MC_LATENCY_ALLOWANCE_SDMMC_0                            0x3c0
-#define MC_LATENCY_ALLOWANCE_NVJPG_0                            0x3e4
-#define MC_LATENCY_ALLOWANCE_PTC_0                              0x34c
-#define MC_LATENCY_ALLOWANCE_ETR_0                              0x3ec
-#define MC_LATENCY_ALLOWANCE_MPCORE_0                           0x320
-#define MC_LATENCY_ALLOWANCE_VI2_0                              0x398
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB                  0x69c
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB                  0x6a4
-#define MC_LATENCY_ALLOWANCE_SATA_0                             0x350
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A                   0x690
-#define MC_LATENCY_ALLOWANCE_HC_0                               0x310
-#define MC_LATENCY_ALLOWANCE_DC_3                               0x3c8
-#define MC_LATENCY_ALLOWANCE_GPU_0                              0x3ac
-#define MC_LATENCY_ALLOWANCE_SDMMCAB_0                          0x3c4
-#define MC_LATENCY_ALLOWANCE_ISP2B_1                            0x388
-#define MC_LATENCY_ALLOWANCE_NVENC_0                            0x328
-#define MC_LATENCY_ALLOWANCE_HDA_0                              0x318
-#define MC_MIN_LENGTH_APE_0                                     0xb34
-#define MC_MIN_LENGTH_DCB_2                                     0x8a8
-#define MC_MIN_LENGTH_A9AVP_0                                   0x950
-#define MC_MIN_LENGTH_TSEC_0                                    0x93c
-#define MC_MIN_LENGTH_DC_1                                      0x898
-#define MC_MIN_LENGTH_AXIAP_0                                   0x94c
-#define MC_MIN_LENGTH_ISP2B_0                                   0x930
-#define MC_MIN_LENGTH_VI2_0                                     0x944
-#define MC_MIN_LENGTH_DCB_0                                     0x8a0
-#define MC_MIN_LENGTH_DCB_1                                     0x8a4
-#define MC_MIN_LENGTH_PPCS_1                                    0x8f4
-#define MC_MIN_LENGTH_NVJPG_0                                   0xb3c
-#define MC_MIN_LENGTH_HDA_0                                     0x8c4
-#define MC_MIN_LENGTH_NVENC_0                                   0x8d4
-#define MC_MIN_LENGTH_SDMMC_0                                   0xb18
-#define MC_MIN_LENGTH_ISP2B_1                                   0x934
-#define MC_MIN_LENGTH_HC_1                                      0x8c0
-#define MC_MIN_LENGTH_DC_3                                      0xb20
-#define MC_MIN_LENGTH_AVPC_0                                    0x890
-#define MC_MIN_LENGTH_VIC_0                                     0x940
-#define MC_MIN_LENGTH_ISP2_0                                    0x91c
-#define MC_MIN_LENGTH_HC_0                                      0x8bc
-#define MC_MIN_LENGTH_SE_0                                      0xb38
-#define MC_MIN_LENGTH_NVDEC_0                                   0xb30
-#define MC_MIN_LENGTH_SATA_0                                    0x8fc
-#define MC_MIN_LENGTH_DC_0                                      0x894
-#define MC_MIN_LENGTH_XUSB_1                                    0x92c
-#define MC_MIN_LENGTH_DC_2                                      0x89c
-#define MC_MIN_LENGTH_SDMMCAA_0                                 0xb14
-#define MC_MIN_LENGTH_GPU_0                                     0xb04
-#define MC_MIN_LENGTH_ETR_0                                     0xb44
-#define MC_MIN_LENGTH_AFI_0                                     0x88c
-#define MC_MIN_LENGTH_PPCS_0                                    0x8f0
-#define MC_MIN_LENGTH_ISP2_1                                    0x920
-#define MC_MIN_LENGTH_XUSB_0                                    0x928
-#define MC_MIN_LENGTH_MPCORE_0                                  0x8cc
-#define MC_MIN_LENGTH_TSECB_0                                   0xb48
-#define MC_MIN_LENGTH_SDMMCA_0                                  0xb10
-#define MC_MIN_LENGTH_GPU2_0                                    0xb40
-#define MC_MIN_LENGTH_SDMMCAB_0                                 0xb1c
-#define MC_MIN_LENGTH_PTC_0                                     0x8f8
-#define MC_EMEM_ARB_OVERRIDE_1                                  0x968
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0                         0x984
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1                         0x988
-#define MC_EMEM_ARB_STATS_0                                     0x990
-#define MC_EMEM_ARB_STATS_1                                     0x994
-#define MC_MTS_CARVEOUT_BOM                                     0x9a0
-#define MC_MTS_CARVEOUT_SIZE_MB                                 0x9a4
-#define MC_MTS_CARVEOUT_ADR_HI                                  0x9a8
-#define MC_MTS_CARVEOUT_REG_CTRL                                0x9ac
-#define MC_ERR_MTS_STATUS                                       0x9b0
-#define MC_ERR_MTS_ADR                                          0x9b4
-#define MC_ERR_GENERALIZED_CARVEOUT_STATUS                      0xc00
-#define MC_ERR_GENERALIZED_CARVEOUT_ADR                         0xc04
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2     0xd74
-#define MC_SECURITY_CARVEOUT4_CFG0                              0xcf8
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2                    0xd10
-#define MC_SECURITY_CARVEOUT4_SIZE_128KB                        0xd04
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4                    0xc28
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1     0xc30
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4     0xc8c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0     0xd1c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1     0xd70
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0     0xc2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4     0xd7c
-#define MC_SECURITY_CARVEOUT3_SIZE_128KB                        0xcb4
-#define MC_SECURITY_CARVEOUT2_CFG0                              0xc58
-#define MC_SECURITY_CARVEOUT1_CFG0                              0xc08
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2     0xc84
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0                    0xc68
-#define MC_SECURITY_CARVEOUT3_BOM                               0xcac
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2                    0xc70
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3     0xd78
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0     0xc7c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4                    0xd18
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1                    0xcbc
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3     0xc38
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2     0xc34
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2                    0xcc0
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2                    0xd60
-#define MC_SECURITY_CARVEOUT3_CFG0                              0xca8
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0                    0xcb8
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3     0xc88
-#define MC_SECURITY_CARVEOUT2_SIZE_128KB                        0xc64
-#define MC_SECURITY_CARVEOUT5_BOM_HI                            0xd50
-#define MC_SECURITY_CARVEOUT1_SIZE_128KB                        0xc14
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3                    0xd14
-#define MC_SECURITY_CARVEOUT1_BOM                               0xc0c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4     0xd2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4                    0xd68
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4                    0xcc8
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0                    0xd58
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2     0xd24
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3                    0xcc4
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4                    0xc78
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1                    0xc1c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0                    0xc18
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3     0xd28
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1                    0xd5c
-#define MC_SECURITY_CARVEOUT3_BOM_HI                            0xcb0
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3     0xcd8
-#define MC_SECURITY_CARVEOUT2_BOM_HI                            0xc60
-#define MC_SECURITY_CARVEOUT4_BOM_HI                            0xd00
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3                    0xd64
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4     0xcdc
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1     0xc80
-#define MC_SECURITY_CARVEOUT5_SIZE_128KB                        0xd54
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1     0xd20
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2     0xcd4
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1                    0xd0c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3                    0xc74
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0     0xccc
-#define MC_SECURITY_CARVEOUT4_BOM                               0xcfc
-#define MC_SECURITY_CARVEOUT5_CFG0                              0xd48
-#define MC_SECURITY_CARVEOUT2_BOM                               0xc5c
-#define MC_SECURITY_CARVEOUT5_BOM                               0xd4c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3                    0xc24
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0     0xd6c
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1     0xcd0
-#define MC_SECURITY_CARVEOUT1_BOM_HI                            0xc10
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2                    0xc20
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4     0xc3c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1                    0xc6c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0                    0xd08
-#define MC_ERR_APB_ASID_UPDATE_STATUS                           0x9d0
-#define MC_DA_CONFIG0                                           0x9dc
-#define MC_UNTRANSLATED_REGION_CHECK                            0x948
-
-/* Memory Controller clients */
-#define CLIENT_ACCESS_NUM_CLIENTS   32
-typedef enum {
-    /* _ACCESS0 */
-    CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    
-    /* _ACCESS1 */
-    CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    
-    /* _ACCESS2 */
-    CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    
-    /* _ACCESS3 */
-    CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    
-    /* _ACCESS4 */
-    CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
-} McClient;
-
-void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
-void mc_config_carveout();
-void mc_config_carveout_finalize();
-void mc_enable_ahb_redirect();
-void mc_disable_ahb_redirect();
-void mc_enable();
-
-#endif

fusee/fusee-mtc/src/pmc.h

@@ -1,713 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_PMC_H
-#define FUSEE_PMC_H
-
-#include <stdint.h>
-
-#define PMC_BASE 0x7000E400
-#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n)
-
-#define PMC_CONTROL_SDMMC1      (1 << 12)
-#define PMC_CONTROL_SDMMC3      (1 << 13)
-#define PMC_CONTROL_SDMMC4      (1 << 14)
-
-#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00)
-#define APBDEV_PM_0 MAKE_PMC_REG(0x14)
-#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24)
-#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30)
-#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38)
-#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44)
-#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50)
-#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54)
-#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0)
-#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4)
-#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8)
-#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4)
-#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168)
-#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4)
-#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4)
-#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8)
-#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0)
-#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC)
-#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244)
-#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4)
-#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC)
-#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8)
-#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334)
-#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360)
-#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4)
-#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440)
-#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464)
-#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4)
-#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC)
-#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4)
-#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C)
-#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810)
-#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818)
-#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840)
-
-#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234)
-#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238)
-#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120)
-#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C)
-
-/* Power Management Controller (APBDEV_PMC_) regs */
-typedef struct {
-    uint32_t cntrl;                             /* _CNTRL_0,                        0x00 */
-    uint32_t sec_disable;                       /* _SEC_DISABLE_0,                  0x04 */
-    uint32_t pmc_swrst;                         /* _PMC_SWRST_0,                    0x08 */
-    uint32_t wake_mask;                         /* _WAKE_MASK_0,                    0x0c */
-    uint32_t wake_lvl;                          /* _WAKE_LVL_0,                     0x10 */
-    uint32_t wake_status;                       /* _WAKE_STATUS_0,                  0x14 */
-    uint32_t sw_wake_status;                    /* _SW_WAKE_STATUS_0,               0x18 */
-    uint32_t dpd_pads_oride;                    /* _DPD_PADS_ORIDE_0,               0x1c */
-    uint32_t dpd_sample;                        /* _DPD_SAMPLE_0,                   0x20 */
-    uint32_t dpd_enable;                        /* _DPD_ENABLE_0,                   0x24 */
-    uint32_t pwrgate_timer_off;                 /* _PWRGATE_TIMER_OFF_0,            0x28 */
-    uint32_t clamp_status;                      /* _CLAMP_STATUS_0,                 0x2c */
-    uint32_t pwrgate_toggle;                    /* _PWRGATE_TOGGLE_0,               0x30 */
-    uint32_t remove_clamping;                   /* _REMOVE_CLAMPING_0,              0x34 */
-    uint32_t pwrgate_status;                    /* _PWRGATE_STATUS_0,               0x38 */
-    uint32_t pwrgood_timer;                     /* _PWRGOOD_TIMER_0,                0x3c */
-    uint32_t blink_timer;                       /* _BLINK_TIMER_0,                  0x40 */
-    uint32_t no_iopower;                        /* _NO_IOPOWER_0,                   0x44 */
-    uint32_t pwr_det;                           /* _PWR_DET_0,                      0x48 */
-    uint32_t pwr_det_latch;                     /* _PWR_DET_LATCH_0,                0x4c */
-    uint32_t scratch0;                          /* _SCRATCH0_0,                     0x50 */
-    uint32_t scratch1;                          /* _SCRATCH1_0,                     0x54 */
-    uint32_t scratch2;                          /* _SCRATCH2_0,                     0x58 */
-    uint32_t scratch3;                          /* _SCRATCH3_0,                     0x5c */
-    uint32_t scratch4;                          /* _SCRATCH4_0,                     0x60 */
-    uint32_t scratch5;                          /* _SCRATCH5_0,                     0x64 */
-    uint32_t scratch6;                          /* _SCRATCH6_0,                     0x68 */
-    uint32_t scratch7;                          /* _SCRATCH7_0,                     0x6c */
-    uint32_t scratch8;                          /* _SCRATCH8_0,                     0x70 */
-    uint32_t scratch9;                          /* _SCRATCH9_0,                     0x74 */
-    uint32_t scratch10;                         /* _SCRATCH10_0,                    0x78 */
-    uint32_t scratch11;                         /* _SCRATCH11_0,                    0x7c */
-    uint32_t scratch12;                         /* _SCRATCH12_0,                    0x80 */
-    uint32_t scratch13;                         /* _SCRATCH13_0,                    0x84 */
-    uint32_t scratch14;                         /* _SCRATCH14_0,                    0x88 */
-    uint32_t scratch15;                         /* _SCRATCH15_0,                    0x8c */
-    uint32_t scratch16;                         /* _SCRATCH16_0,                    0x90 */
-    uint32_t scratch17;                         /* _SCRATCH17_0,                    0x94 */
-    uint32_t scratch18;                         /* _SCRATCH18_0,                    0x98 */
-    uint32_t scratch19;                         /* _SCRATCH19_0,                    0x9c */
-    uint32_t scratch20;                         /* _SCRATCH20_0,                    0xa0 */
-    uint32_t scratch21;                         /* _SCRATCH21_0,                    0xa4 */
-    uint32_t scratch22;                         /* _SCRATCH22_0,                    0xa8 */
-    uint32_t scratch23;                         /* _SCRATCH23_0,                    0xac */
-    uint32_t secure_scratch0;                   /* _SECURE_SCRATCH0_0,              0xb0 */
-    uint32_t secure_scratch1;                   /* _SECURE_SCRATCH1_0,              0xb4 */
-    uint32_t secure_scratch2;                   /* _SECURE_SCRATCH2_0,              0xb8 */
-    uint32_t secure_scratch3;                   /* _SECURE_SCRATCH3_0,              0xbc */
-    uint32_t secure_scratch4;                   /* _SECURE_SCRATCH4_0,              0xc0 */
-    uint32_t secure_scratch5;                   /* _SECURE_SCRATCH5_0,              0xc4 */
-    uint32_t cpupwrgood_timer;                  /* _CPUPWRGOOD_TIMER_0,             0xc8 */
-    uint32_t cpupwroff_timer;                   /* _CPUPWROFF_TIMER_0,              0xcc */
-    uint32_t pg_mask;                           /* _PG_MASK_0,                      0xd0 */
-    uint32_t pg_mask_1;                         /* _PG_MASK_1_0,                    0xd4 */
-    uint32_t auto_wake_lvl;                     /* _AUTO_WAKE_LVL_0,                0xd8 */
-    uint32_t auto_wake_lvl_mask;                /* _AUTO_WAKE_LVL_MASK_0,           0xdc */
-    uint32_t wake_delay;                        /* _WAKE_DELAY_0,                   0xe0 */
-    uint32_t pwr_det_val;                       /* _PWR_DET_VAL_0,                  0xe4 */
-    uint32_t ddr_pwr;                           /* _DDR_PWR_0,                      0xe8 */
-    uint32_t usb_debounce_del;                  /* _USB_DEBOUNCE_DEL_0,             0xec */
-    uint32_t usb_ao;                            /* _USB_AO_0,                       0xf0 */
-    uint32_t crypto_op;                         /* _CRYPTO_OP_0,                    0xf4 */
-    uint32_t pllp_wb0_override;                 /* _PLLP_WB0_OVERRIDE_0,            0xf8 */
-    uint32_t scratch24;                         /* _SCRATCH24_0,                    0xfc */
-    uint32_t scratch25;                         /* _SCRATCH25_0,                    0x100 */
-    uint32_t scratch26;                         /* _SCRATCH26_0,                    0x104 */
-    uint32_t scratch27;                         /* _SCRATCH27_0,                    0x108 */
-    uint32_t scratch28;                         /* _SCRATCH28_0,                    0x10c */
-    uint32_t scratch29;                         /* _SCRATCH29_0,                    0x110 */
-    uint32_t scratch30;                         /* _SCRATCH30_0,                    0x114 */
-    uint32_t scratch31;                         /* _SCRATCH31_0,                    0x118 */
-    uint32_t scratch32;                         /* _SCRATCH32_0,                    0x11c */
-    uint32_t scratch33;                         /* _SCRATCH33_0,                    0x120 */
-    uint32_t scratch34;                         /* _SCRATCH34_0,                    0x124 */
-    uint32_t scratch35;                         /* _SCRATCH35_0,                    0x128 */
-    uint32_t scratch36;                         /* _SCRATCH36_0,                    0x12c */
-    uint32_t scratch37;                         /* _SCRATCH37_0,                    0x130 */
-    uint32_t scratch38;                         /* _SCRATCH38_0,                    0x134 */
-    uint32_t scratch39;                         /* _SCRATCH39_0,                    0x138 */
-    uint32_t scratch40;                         /* _SCRATCH40_0,                    0x13c */
-    uint32_t scratch41;                         /* _SCRATCH41_0,                    0x140 */
-    uint32_t scratch42;                         /* _SCRATCH42_0,                    0x144 */
-    uint32_t bondout_mirror0;                   /* _BONDOUT_MIRROR0_0,              0x148 */
-    uint32_t bondout_mirror1;                   /* _BONDOUT_MIRROR1_0,              0x14c */
-    uint32_t bondout_mirror2;                   /* _BONDOUT_MIRROR2_0,              0x150 */
-    uint32_t sys_33v_en;                        /* _SYS_33V_EN_0,                   0x154 */
-    uint32_t bondout_mirror_access;             /* _BONDOUT_MIRROR_ACCESS_0,        0x158 */
-    uint32_t gate;                              /* _GATE_0,                         0x15c */
-    uint32_t wake2_mask;                        /* _WAKE2_MASK_0,                   0x160 */
-    uint32_t wake2_lvl;                         /* _WAKE2_LVL_0,                    0x164 */
-    uint32_t wake2_status;                      /* _WAKE2_STATUS_0,                 0x168 */
-    uint32_t sw_wake2_status;                   /* _SW_WAKE2_STATUS_0,              0x16c */
-    uint32_t auto_wake2_lvl_mask;               /* _AUTO_WAKE2_LVL_MASK_0,          0x170 */
-    uint32_t pg_mask_2;                         /* _PG_MASK_2_0,                    0x174 */
-    uint32_t pg_mask_ce1;                       /* _PG_MASK_CE1_0,                  0x178 */
-    uint32_t pg_mask_ce2;                       /* _PG_MASK_CE2_0,                  0x17c */
-    uint32_t pg_mask_ce3;                       /* _PG_MASK_CE3_0,                  0x180 */
-    uint32_t pwrgate_timer_ce_0;                /* _PWRGATE_TIMER_CE_0_0,           0x184 */
-    uint32_t pwrgate_timer_ce_1;                /* _PWRGATE_TIMER_CE_1_0,           0x188 */
-    uint32_t pwrgate_timer_ce_2;                /* _PWRGATE_TIMER_CE_2_0,           0x18c */
-    uint32_t pwrgate_timer_ce_3;                /* _PWRGATE_TIMER_CE_3_0,           0x190 */
-    uint32_t pwrgate_timer_ce_4;                /* _PWRGATE_TIMER_CE_4_0,           0x194 */
-    uint32_t pwrgate_timer_ce_5;                /* _PWRGATE_TIMER_CE_5_0,           0x198 */
-    uint32_t pwrgate_timer_ce_6;                /* _PWRGATE_TIMER_CE_6_0,           0x19c */
-    uint32_t pcx_edpd_cntrl;                    /* _PCX_EDPD_CNTRL_0,               0x1a0 */
-    uint32_t osc_edpd_over;                     /* _OSC_EDPD_OVER_0,                0x1a4 */
-    uint32_t clk_out_cntrl;                     /* _CLK_OUT_CNTRL_0,                0x1a8 */
-    uint32_t sata_pwrgt;                        /* _SATA_PWRGT_0,                   0x1ac */
-    uint32_t sensor_ctrl;                       /* _SENSOR_CTRL_0,                  0x1b0 */
-    uint32_t rst_status;                        /* _RST_STATUS_0,                   0x1b4 */
-    uint32_t io_dpd_req;                        /* _IO_DPD_REQ_0,                   0x1b8 */
-    uint32_t io_dpd_status;                     /* _IO_DPD_STATUS_0,                0x1bc */
-    uint32_t io_dpd2_req;                       /* _IO_DPD2_REQ_0,                  0x1c0 */
-    uint32_t io_dpd2_status;                    /* _IO_DPD2_STATUS_0,               0x1c4 */
-    uint32_t sel_dpd_tim;                       /* _SEL_DPD_TIM_0,                  0x1c8 */
-    uint32_t vddp_sel;                          /* _VDDP_SEL_0,                     0x1cc */
-    uint32_t ddr_cfg;                           /* _DDR_CFG_0,                      0x1d0 */
-    uint32_t _0x1d4[2];
-    uint32_t pllm_wb0_override_freq;            /* _PLLM_WB0_OVERRIDE_FREQ_0,       0x1dc */
-    uint32_t _0x1e0;
-    uint32_t pwrgate_timer_mult;                /* _PWRGATE_TIMER_MULT_0,           0x1e4 */
-    uint32_t dsi_sel_dpd;                       /* _DSI_SEL_DPD_0,                  0x1e8 */
-    uint32_t utmip_uhsic_triggers;              /* _UTMIP_UHSIC_TRIGGERS_0,         0x1ec */
-    uint32_t utmip_uhsic_saved_state;           /* _UTMIP_UHSIC_SAVED_STATE_0,      0x1f0 */
-    uint32_t _0x1f4;
-    uint32_t utmip_term_pad_cfg;                /* _UTMIP_TERM_PAD_CFG_0,           0x1f8 */
-    uint32_t utmip_uhsic_sleep_cfg;             /* _UTMIP_UHSIC_SLEEP_CFG_0,        0x1fc */
-    uint32_t utmip_uhsic_sleepwalk_cfg;         /* _UTMIP_UHSIC_SLEEPWALK_CFG_0,    0x200 */
-    uint32_t utmip_sleepwalk_p0;                /* _UTMIP_SLEEPWALK_P0_0,           0x204 */
-    uint32_t utmip_sleepwalk_p1;                /* _UTMIP_SLEEPWALK_P1_0,           0x208 */
-    uint32_t utmip_sleepwalk_p2;                /* _UTMIP_SLEEPWALK_P2_0,           0x20c */
-    uint32_t uhsic_sleepwalk_p0;                /* _UHSIC_SLEEPWALK_P0_0,           0x210 */
-    uint32_t utmip_uhsic_status;                /* _UTMIP_UHSIC_STATUS_0,           0x214 */
-    uint32_t utmip_uhsic_fake;                  /* _UTMIP_UHSIC_FAKE_0,             0x218 */
-    uint32_t bondout_mirror3;                   /* _BONDOUT_MIRROR3_0,              0x21c */
-    uint32_t bondout_mirror4;                   /* _BONDOUT_MIRROR4_0,              0x220 */
-    uint32_t secure_scratch6;                   /* _SECURE_SCRATCH6_0,              0x224 */
-    uint32_t secure_scratch7;                   /* _SECURE_SCRATCH7_0,              0x228 */
-    uint32_t scratch43;                         /* _SCRATCH43_0,                    0x22c */
-    uint32_t scratch44;                         /* _SCRATCH44_0,                    0x230 */
-    uint32_t scratch45;                         /* _SCRATCH45_0,                    0x234 */
-    uint32_t scratch46;                         /* _SCRATCH46_0,                    0x238 */
-    uint32_t scratch47;                         /* _SCRATCH47_0,                    0x23c */
-    uint32_t scratch48;                         /* _SCRATCH48_0,                    0x240 */
-    uint32_t scratch49;                         /* _SCRATCH49_0,                    0x244 */
-    uint32_t scratch50;                         /* _SCRATCH50_0,                    0x248 */
-    uint32_t scratch51;                         /* _SCRATCH51_0,                    0x24c */
-    uint32_t scratch52;                         /* _SCRATCH52_0,                    0x250 */
-    uint32_t scratch53;                         /* _SCRATCH53_0,                    0x254 */
-    uint32_t scratch54;                         /* _SCRATCH54_0,                    0x258 */
-    uint32_t scratch55;                         /* _SCRATCH55_0,                    0x25c */
-    uint32_t scratch0_eco;                      /* _SCRATCH0_ECO_0,                 0x260 */
-    uint32_t por_dpd_ctrl;                      /* _POR_DPD_CTRL_0,                 0x264 */
-    uint32_t scratch2_eco;                      /* _SCRATCH2_ECO_0,                 0x268 */
-    uint32_t utmip_uhsic_line_wakeup;           /* _UTMIP_UHSIC_LINE_WAKEUP_0,      0x26c */
-    uint32_t utmip_bias_master_cntrl;           /* _UTMIP_BIAS_MASTER_CNTRL_0,      0x270 */
-    uint32_t utmip_master_config;               /* _UTMIP_MASTER_CONFIG_0,          0x274 */
-    uint32_t td_pwrgate_inter_part_timer;       /* _TD_PWRGATE_INTER_PART_TIMER_0,  0x278 */
-    uint32_t utmip_uhsic2_triggers;             /* _UTMIP_UHSIC2_TRIGGERS_0,        0x27c */
-    uint32_t utmip_uhsic2_saved_state;          /* _UTMIP_UHSIC2_SAVED_STATE_0,     0x280 */
-    uint32_t utmip_uhsic2_sleep_cfg;            /* _UTMIP_UHSIC2_SLEEP_CFG_0,       0x284 */
-    uint32_t utmip_uhsic2_sleepwalk_cfg;        /* _UTMIP_UHSIC2_SLEEPWALK_CFG_0,   0x288 */
-    uint32_t uhsic2_sleepwalk_p1;               /* _UHSIC2_SLEEPWALK_P1_0,          0x28c */
-    uint32_t utmip_uhsic2_status;               /* _UTMIP_UHSIC2_STATUS_0,          0x290 */
-    uint32_t utmip_uhsic2_fake;                 /* _UTMIP_UHSIC2_FAKE_0,            0x294 */
-    uint32_t utmip_uhsic2_line_wakeup;          /* _UTMIP_UHSIC2_LINE_WAKEUP_0,     0x298 */
-    uint32_t utmip_master2_config;              /* _UTMIP_MASTER2_CONFIG_0,         0x29c */
-    uint32_t utmip_uhsic_rpd_cfg;               /* _UTMIP_UHSIC_RPD_CFG_0,          0x2a0 */
-    uint32_t pg_mask_ce0;                       /* _PG_MASK_CE0_0,                  0x2a4 */
-    uint32_t pg_mask_3;                         /* _PG_MASK_3_0,                    0x2a8 */
-    uint32_t pg_mask_4;                         /* _PG_MASK_4_0,                    0x2ac */
-    uint32_t pllm_wb0_override2;                /* _PLLM_WB0_OVERRIDE2_0,           0x2b0 */
-    uint32_t tsc_mult;                          /* _TSC_MULT_0,                     0x2b4 */
-    uint32_t cpu_vsense_override;               /* _CPU_VSENSE_OVERRIDE_0,          0x2b8 */
-    uint32_t glb_amap_cfg;                      /* _GLB_AMAP_CFG_0,                 0x2bc */
-    uint32_t sticky_bits;                       /* _STICKY_BITS_0,                  0x2c0 */
-    uint32_t sec_disable2;                      /* _SEC_DISABLE2_0,                 0x2c4 */
-    uint32_t weak_bias;                         /* _WEAK_BIAS_0,                    0x2c8 */
-    uint32_t reg_short;                         /* _REG_SHORT_0,                    0x2cc */
-    uint32_t pg_mask_andor;                     /* _PG_MASK_ANDOR_0,                0x2d0 */
-    uint32_t gpu_rg_cntrl;                      /* _GPU_RG_CNTRL_0,                 0x2d4 */
-    uint32_t sec_disable3;                      /* _SEC_DISABLE3_0,                 0x2d8 */
-    uint32_t pg_mask_5;                         /* _PG_MASK_5_0,                    0x2dc */
-    uint32_t pg_mask_6;                         /* _PG_MASK_6_0,                    0x2e0 */
-    uint32_t _0x2e4[7];
-    uint32_t secure_scratch8;                   /* _SECURE_SCRATCH8_0,              0x300 */
-    uint32_t secure_scratch9;                   /* _SECURE_SCRATCH9_0,              0x304 */
-    uint32_t secure_scratch10;                  /* _SECURE_SCRATCH10_0,             0x308 */
-    uint32_t secure_scratch11;                  /* _SECURE_SCRATCH11_0,             0x30c */
-    uint32_t secure_scratch12;                  /* _SECURE_SCRATCH12_0,             0x310 */
-    uint32_t secure_scratch13;                  /* _SECURE_SCRATCH13_0,             0x314 */
-    uint32_t secure_scratch14;                  /* _SECURE_SCRATCH14_0,             0x318 */
-    uint32_t secure_scratch15;                  /* _SECURE_SCRATCH15_0,             0x31c */
-    uint32_t secure_scratch16;                  /* _SECURE_SCRATCH16_0,             0x320 */
-    uint32_t secure_scratch17;                  /* _SECURE_SCRATCH17_0,             0x324 */
-    uint32_t secure_scratch18;                  /* _SECURE_SCRATCH18_0,             0x328 */
-    uint32_t secure_scratch19;                  /* _SECURE_SCRATCH19_0,             0x32c */
-    uint32_t secure_scratch20;                  /* _SECURE_SCRATCH20_0,             0x330 */
-    uint32_t secure_scratch21;                  /* _SECURE_SCRATCH21_0,             0x334 */
-    uint32_t secure_scratch22;                  /* _SECURE_SCRATCH22_0,             0x338 */
-    uint32_t secure_scratch23;                  /* _SECURE_SCRATCH23_0,             0x33c */
-    uint32_t secure_scratch24;                  /* _SECURE_SCRATCH24_0,             0x340 */
-    uint32_t secure_scratch25;                  /* _SECURE_SCRATCH25_0,             0x344 */
-    uint32_t secure_scratch26;                  /* _SECURE_SCRATCH26_0,             0x348 */
-    uint32_t secure_scratch27;                  /* _SECURE_SCRATCH27_0,             0x34c */
-    uint32_t secure_scratch28;                  /* _SECURE_SCRATCH28_0,             0x350 */
-    uint32_t secure_scratch29;                  /* _SECURE_SCRATCH29_0,             0x354 */
-    uint32_t secure_scratch30;                  /* _SECURE_SCRATCH30_0,             0x358 */
-    uint32_t secure_scratch31;                  /* _SECURE_SCRATCH31_0,             0x35c */
-    uint32_t secure_scratch32;                  /* _SECURE_SCRATCH32_0,             0x360 */
-    uint32_t secure_scratch33;                  /* _SECURE_SCRATCH33_0,             0x364 */
-    uint32_t secure_scratch34;                  /* _SECURE_SCRATCH34_0,             0x368 */
-    uint32_t secure_scratch35;                  /* _SECURE_SCRATCH35_0,             0x36c */
-    uint32_t secure_scratch36;                  /* _SECURE_SCRATCH36_0,             0x370 */
-    uint32_t secure_scratch37;                  /* _SECURE_SCRATCH37_0,             0x374 */
-    uint32_t secure_scratch38;                  /* _SECURE_SCRATCH38_0,             0x378 */
-    uint32_t secure_scratch39;                  /* _SECURE_SCRATCH39_0,             0x37c */
-    uint32_t secure_scratch40;                  /* _SECURE_SCRATCH40_0,             0x380 */
-    uint32_t secure_scratch41;                  /* _SECURE_SCRATCH41_0,             0x384 */
-    uint32_t secure_scratch42;                  /* _SECURE_SCRATCH42_0,             0x388 */
-    uint32_t secure_scratch43;                  /* _SECURE_SCRATCH43_0,             0x38c */
-    uint32_t secure_scratch44;                  /* _SECURE_SCRATCH44_0,             0x390 */
-    uint32_t secure_scratch45;                  /* _SECURE_SCRATCH45_0,             0x394 */
-    uint32_t secure_scratch46;                  /* _SECURE_SCRATCH46_0,             0x398 */
-    uint32_t secure_scratch47;                  /* _SECURE_SCRATCH47_0,             0x39c */
-    uint32_t secure_scratch48;                  /* _SECURE_SCRATCH48_0,             0x3a0 */
-    uint32_t secure_scratch49;                  /* _SECURE_SCRATCH49_0,             0x3a4 */
-    uint32_t secure_scratch50;                  /* _SECURE_SCRATCH50_0,             0x3a8 */
-    uint32_t secure_scratch51;                  /* _SECURE_SCRATCH51_0,             0x3ac */
-    uint32_t secure_scratch52;                  /* _SECURE_SCRATCH52_0,             0x3b0 */
-    uint32_t secure_scratch53;                  /* _SECURE_SCRATCH53_0,             0x3b4 */
-    uint32_t secure_scratch54;                  /* _SECURE_SCRATCH54_0,             0x3b8 */
-    uint32_t secure_scratch55;                  /* _SECURE_SCRATCH55_0,             0x3bc */
-    uint32_t secure_scratch56;                  /* _SECURE_SCRATCH56_0,             0x3c0 */
-    uint32_t secure_scratch57;                  /* _SECURE_SCRATCH57_0,             0x3c4 */
-    uint32_t secure_scratch58;                  /* _SECURE_SCRATCH58_0,             0x3c8 */
-    uint32_t secure_scratch59;                  /* _SECURE_SCRATCH59_0,             0x3cc */
-    uint32_t secure_scratch60;                  /* _SECURE_SCRATCH60_0,             0x3d0 */
-    uint32_t secure_scratch61;                  /* _SECURE_SCRATCH61_0,             0x3d4 */
-    uint32_t secure_scratch62;                  /* _SECURE_SCRATCH62_0,             0x3d8 */
-    uint32_t secure_scratch63;                  /* _SECURE_SCRATCH63_0,             0x3dc */
-    uint32_t secure_scratch64;                  /* _SECURE_SCRATCH64_0,             0x3e0 */
-    uint32_t secure_scratch65;                  /* _SECURE_SCRATCH65_0,             0x3e4 */
-    uint32_t secure_scratch66;                  /* _SECURE_SCRATCH66_0,             0x3e8 */
-    uint32_t secure_scratch67;                  /* _SECURE_SCRATCH67_0,             0x3ec */
-    uint32_t secure_scratch68;                  /* _SECURE_SCRATCH68_0,             0x3f0 */
-    uint32_t secure_scratch69;                  /* _SECURE_SCRATCH69_0,             0x3f4 */
-    uint32_t secure_scratch70;                  /* _SECURE_SCRATCH70_0,             0x3f8 */
-    uint32_t secure_scratch71;                  /* _SECURE_SCRATCH71_0,             0x3fc */
-    uint32_t secure_scratch72;                  /* _SECURE_SCRATCH72_0,             0x400 */
-    uint32_t secure_scratch73;                  /* _SECURE_SCRATCH73_0,             0x404 */
-    uint32_t secure_scratch74;                  /* _SECURE_SCRATCH74_0,             0x408 */
-    uint32_t secure_scratch75;                  /* _SECURE_SCRATCH75_0,             0x40c */
-    uint32_t secure_scratch76;                  /* _SECURE_SCRATCH76_0,             0x410 */
-    uint32_t secure_scratch77;                  /* _SECURE_SCRATCH77_0,             0x414 */
-    uint32_t secure_scratch78;                  /* _SECURE_SCRATCH78_0,             0x418 */
-    uint32_t secure_scratch79;                  /* _SECURE_SCRATCH79_0,             0x41c */
-    uint32_t _0x420[8];
-    uint32_t cntrl2;                            /* _CNTRL2_0,                       0x440 */
-    uint32_t io_dpd_off_mask;                   /* _IO_DPD_OFF_MASK_0,              0x444 */
-    uint32_t io_dpd2_off_mask;                  /* _IO_DPD2_OFF_MASK_0,             0x448 */
-    uint32_t event_counter;                     /* _EVENT_COUNTER_0,                0x44c */
-    uint32_t fuse_control;                      /* _FUSE_CONTROL_0,                 0x450 */
-    uint32_t scratch1_eco;                      /* _SCRATCH1_ECO_0,                 0x454 */
-    uint32_t _0x458;
-    uint32_t io_dpd3_req;                       /* _IO_DPD3_REQ_0,                  0x45c */
-    uint32_t io_dpd3_status;                    /* _IO_DPD3_STATUS_0,               0x460 */
-    uint32_t io_dpd4_req;                       /* _IO_DPD4_REQ_0,                  0x464 */
-    uint32_t io_dpd4_status;                    /* _IO_DPD4_STATUS_0,               0x468 */
-    uint32_t _0x46c[2];
-    uint32_t direct_thermtrip_cfg;              /* _DIRECT_THERMTRIP_CFG_0,         0x474 */
-    uint32_t tsosc_delay;                       /* _TSOSC_DELAY_0,                  0x478 */
-    uint32_t set_sw_clamp;                      /* _SET_SW_CLAMP_0,                 0x47c */
-    uint32_t debug_authentication;              /* _DEBUG_AUTHENTICATION_0,         0x480 */
-    uint32_t aotag_cfg;                         /* _AOTAG_CFG_0,                    0x484 */
-    uint32_t aotag_thresh1_cfg;                 /* _AOTAG_THRESH1_CFG_0,            0x488 */
-    uint32_t aotag_thresh2_cfg;                 /* _AOTAG_THRESH2_CFG_0,            0x48c */
-    uint32_t aotag_thresh3_cfg;                 /* _AOTAG_THRESH3_CFG_0,            0x490 */
-    uint32_t aotag_status;                      /* _AOTAG_STATUS_0,                 0x494 */
-    uint32_t aotag_security;                    /* _AOTAG_SECURITY_0,               0x498 */
-    uint32_t tsensor_config0;                   /* _TSENSOR_CONFIG0_0,              0x49c */
-    uint32_t tsensor_config1;                   /* _TSENSOR_CONFIG1_0,              0x4a0 */
-    uint32_t tsensor_config2;                   /* _TSENSOR_CONFIG2_0,              0x4a4 */
-    uint32_t tsensor_status0;                   /* _TSENSOR_STATUS0_0,              0x4a8 */
-    uint32_t tsensor_status1;                   /* _TSENSOR_STATUS1_0,              0x4ac */
-    uint32_t tsensor_status2;                   /* _TSENSOR_STATUS2_0,              0x4b0 */
-    uint32_t tsensor_pdiv;                      /* _TSENSOR_PDIV_0,                 0x4b4 */
-    uint32_t aotag_intr_en;                     /* _AOTAG_INTR_EN_0,                0x4b8 */
-    uint32_t aotag_intr_dis;                    /* _AOTAG_INTR_DIS_0,               0x4bc */
-    uint32_t utmip_pad_cfg0;                    /* _UTMIP_PAD_CFG0_0,               0x4c0 */
-    uint32_t utmip_pad_cfg1;                    /* _UTMIP_PAD_CFG1_0,               0x4c4 */
-    uint32_t utmip_pad_cfg2;                    /* _UTMIP_PAD_CFG2_0,               0x4c8 */
-    uint32_t utmip_pad_cfg3;                    /* _UTMIP_PAD_CFG3_0,               0x4cc */
-    uint32_t utmip_uhsic_sleep_cfg1;            /* _UTMIP_UHSIC_SLEEP_CFG1_0,       0x4d0 */
-    uint32_t cc4_hvc_control;                   /* _CC4_HVC_CONTROL_0,              0x4d4 */
-    uint32_t wake_debounce_en;                  /* _WAKE_DEBOUNCE_EN_0,             0x4d8 */
-    uint32_t ramdump_ctl_status;                /* _RAMDUMP_CTL_STATUS_0,           0x4dc */
-    uint32_t utmip_sleepwalk_p3;                /* _UTMIP_SLEEPWALK_P3_0,           0x4e0 */
-    uint32_t ddr_cntrl;                         /* _DDR_CNTRL_0,                    0x4e4 */
-    uint32_t _0x4e8[50];
-    uint32_t sec_disable4;                      /* _SEC_DISABLE4_0,                 0x5b0 */
-    uint32_t sec_disable5;                      /* _SEC_DISABLE5_0,                 0x5b4 */
-    uint32_t sec_disable6;                      /* _SEC_DISABLE6_0,                 0x5b8 */
-    uint32_t sec_disable7;                      /* _SEC_DISABLE7_0,                 0x5bc */
-    uint32_t sec_disable8;                      /* _SEC_DISABLE8_0,                 0x5c0 */
-    uint32_t sec_disable9;                      /* _SEC_DISABLE9_0,                 0x5c4 */
-    uint32_t sec_disable10;                     /* _SEC_DISABLE10_0,                0x5c8 */
-    uint32_t _0x5cc[13];
-    uint32_t scratch56;                         /* _SCRATCH56_0,                    0x600 */
-    uint32_t scratch57;                         /* _SCRATCH57_0,                    0x604 */
-    uint32_t scratch58;                         /* _SCRATCH58_0,                    0x608 */
-    uint32_t scratch59;                         /* _SCRATCH59_0,                    0x60c */
-    uint32_t scratch60;                         /* _SCRATCH60_0,                    0x610 */
-    uint32_t scratch61;                         /* _SCRATCH61_0,                    0x614 */
-    uint32_t scratch62;                         /* _SCRATCH62_0,                    0x618 */
-    uint32_t scratch63;                         /* _SCRATCH63_0,                    0x61c */
-    uint32_t scratch64;                         /* _SCRATCH64_0,                    0x620 */
-    uint32_t scratch65;                         /* _SCRATCH65_0,                    0x624 */
-    uint32_t scratch66;                         /* _SCRATCH66_0,                    0x628 */
-    uint32_t scratch67;                         /* _SCRATCH67_0,                    0x62c */
-    uint32_t scratch68;                         /* _SCRATCH68_0,                    0x630 */
-    uint32_t scratch69;                         /* _SCRATCH69_0,                    0x634 */
-    uint32_t scratch70;                         /* _SCRATCH70_0,                    0x638 */
-    uint32_t scratch71;                         /* _SCRATCH71_0,                    0x63c */
-    uint32_t scratch72;                         /* _SCRATCH72_0,                    0x640 */
-    uint32_t scratch73;                         /* _SCRATCH73_0,                    0x644 */
-    uint32_t scratch74;                         /* _SCRATCH74_0,                    0x648 */
-    uint32_t scratch75;                         /* _SCRATCH75_0,                    0x64c */
-    uint32_t scratch76;                         /* _SCRATCH76_0,                    0x650 */
-    uint32_t scratch77;                         /* _SCRATCH77_0,                    0x654 */
-    uint32_t scratch78;                         /* _SCRATCH78_0,                    0x658 */
-    uint32_t scratch79;                         /* _SCRATCH79_0,                    0x65c */
-    uint32_t scratch80;                         /* _SCRATCH80_0,                    0x660 */
-    uint32_t scratch81;                         /* _SCRATCH81_0,                    0x664 */
-    uint32_t scratch82;                         /* _SCRATCH82_0,                    0x668 */
-    uint32_t scratch83;                         /* _SCRATCH83_0,                    0x66c */
-    uint32_t scratch84;                         /* _SCRATCH84_0,                    0x670 */
-    uint32_t scratch85;                         /* _SCRATCH85_0,                    0x674 */
-    uint32_t scratch86;                         /* _SCRATCH86_0,                    0x678 */
-    uint32_t scratch87;                         /* _SCRATCH87_0,                    0x67c */
-    uint32_t scratch88;                         /* _SCRATCH88_0,                    0x680 */
-    uint32_t scratch89;                         /* _SCRATCH89_0,                    0x684 */
-    uint32_t scratch90;                         /* _SCRATCH90_0,                    0x688 */
-    uint32_t scratch91;                         /* _SCRATCH91_0,                    0x68c */
-    uint32_t scratch92;                         /* _SCRATCH92_0,                    0x690 */
-    uint32_t scratch93;                         /* _SCRATCH93_0,                    0x694 */
-    uint32_t scratch94;                         /* _SCRATCH94_0,                    0x698 */
-    uint32_t scratch95;                         /* _SCRATCH95_0,                    0x69c */
-    uint32_t scratch96;                         /* _SCRATCH96_0,                    0x6a0 */
-    uint32_t scratch97;                         /* _SCRATCH97_0,                    0x6a4 */
-    uint32_t scratch98;                         /* _SCRATCH98_0,                    0x6a8 */
-    uint32_t scratch99;                         /* _SCRATCH99_0,                    0x6ac */
-    uint32_t scratch100;                        /* _SCRATCH100_0,                   0x6b0 */
-    uint32_t scratch101;                        /* _SCRATCH101_0,                   0x6b4 */
-    uint32_t scratch102;                        /* _SCRATCH102_0,                   0x6b8 */
-    uint32_t scratch103;                        /* _SCRATCH103_0,                   0x6bc */
-    uint32_t scratch104;                        /* _SCRATCH104_0,                   0x6c0 */
-    uint32_t scratch105;                        /* _SCRATCH105_0,                   0x6c4 */
-    uint32_t scratch106;                        /* _SCRATCH106_0,                   0x6c8 */
-    uint32_t scratch107;                        /* _SCRATCH107_0,                   0x6cc */
-    uint32_t scratch108;                        /* _SCRATCH108_0,                   0x6d0 */
-    uint32_t scratch109;                        /* _SCRATCH109_0,                   0x6d4 */
-    uint32_t scratch110;                        /* _SCRATCH110_0,                   0x6d8 */
-    uint32_t scratch111;                        /* _SCRATCH111_0,                   0x6dc */
-    uint32_t scratch112;                        /* _SCRATCH112_0,                   0x6e0 */
-    uint32_t scratch113;                        /* _SCRATCH113_0,                   0x6e4 */
-    uint32_t scratch114;                        /* _SCRATCH114_0,                   0x6e8 */
-    uint32_t scratch115;                        /* _SCRATCH115_0,                   0x6ec */
-    uint32_t scratch116;                        /* _SCRATCH116_0,                   0x6f0 */
-    uint32_t scratch117;                        /* _SCRATCH117_0,                   0x6f4 */
-    uint32_t scratch118;                        /* _SCRATCH118_0,                   0x6f8 */
-    uint32_t scratch119;                        /* _SCRATCH119_0,                   0x6fc */
-    uint32_t scratch120;                        /* _SCRATCH120_0,                   0x700 */
-    uint32_t scratch121;                        /* _SCRATCH121_0,                   0x704 */
-    uint32_t scratch122;                        /* _SCRATCH122_0,                   0x708 */
-    uint32_t scratch123;                        /* _SCRATCH123_0,                   0x70c */
-    uint32_t scratch124;                        /* _SCRATCH124_0,                   0x710 */
-    uint32_t scratch125;                        /* _SCRATCH125_0,                   0x714 */
-    uint32_t scratch126;                        /* _SCRATCH126_0,                   0x718 */
-    uint32_t scratch127;                        /* _SCRATCH127_0,                   0x71c */
-    uint32_t scratch128;                        /* _SCRATCH128_0,                   0x720 */
-    uint32_t scratch129;                        /* _SCRATCH129_0,                   0x724 */
-    uint32_t scratch130;                        /* _SCRATCH130_0,                   0x728 */
-    uint32_t scratch131;                        /* _SCRATCH131_0,                   0x72c */
-    uint32_t scratch132;                        /* _SCRATCH132_0,                   0x730 */
-    uint32_t scratch133;                        /* _SCRATCH133_0,                   0x734 */
-    uint32_t scratch134;                        /* _SCRATCH134_0,                   0x738 */
-    uint32_t scratch135;                        /* _SCRATCH135_0,                   0x73c */
-    uint32_t scratch136;                        /* _SCRATCH136_0,                   0x740 */
-    uint32_t scratch137;                        /* _SCRATCH137_0,                   0x744 */
-    uint32_t scratch138;                        /* _SCRATCH138_0,                   0x748 */
-    uint32_t scratch139;                        /* _SCRATCH139_0,                   0x74c */
-    uint32_t scratch140;                        /* _SCRATCH140_0,                   0x750 */
-    uint32_t scratch141;                        /* _SCRATCH141_0,                   0x754 */
-    uint32_t scratch142;                        /* _SCRATCH142_0,                   0x758 */
-    uint32_t scratch143;                        /* _SCRATCH143_0,                   0x75c */
-    uint32_t scratch144;                        /* _SCRATCH144_0,                   0x760 */
-    uint32_t scratch145;                        /* _SCRATCH145_0,                   0x764 */
-    uint32_t scratch146;                        /* _SCRATCH146_0,                   0x768 */
-    uint32_t scratch147;                        /* _SCRATCH147_0,                   0x76c */
-    uint32_t scratch148;                        /* _SCRATCH148_0,                   0x770 */
-    uint32_t scratch149;                        /* _SCRATCH149_0,                   0x774 */
-    uint32_t scratch150;                        /* _SCRATCH150_0,                   0x778 */
-    uint32_t scratch151;                        /* _SCRATCH151_0,                   0x77c */
-    uint32_t scratch152;                        /* _SCRATCH152_0,                   0x780 */
-    uint32_t scratch153;                        /* _SCRATCH153_0,                   0x784 */
-    uint32_t scratch154;                        /* _SCRATCH154_0,                   0x788 */
-    uint32_t scratch155;                        /* _SCRATCH155_0,                   0x78c */
-    uint32_t scratch156;                        /* _SCRATCH156_0,                   0x790 */
-    uint32_t scratch157;                        /* _SCRATCH157_0,                   0x794 */
-    uint32_t scratch158;                        /* _SCRATCH158_0,                   0x798 */
-    uint32_t scratch159;                        /* _SCRATCH159_0,                   0x79c */
-    uint32_t scratch160;                        /* _SCRATCH160_0,                   0x7a0 */
-    uint32_t scratch161;                        /* _SCRATCH161_0,                   0x7a4 */
-    uint32_t scratch162;                        /* _SCRATCH162_0,                   0x7a8 */
-    uint32_t scratch163;                        /* _SCRATCH163_0,                   0x7ac */
-    uint32_t scratch164;                        /* _SCRATCH164_0,                   0x7b0 */
-    uint32_t scratch165;                        /* _SCRATCH165_0,                   0x7b4 */
-    uint32_t scratch166;                        /* _SCRATCH166_0,                   0x7b8 */
-    uint32_t scratch167;                        /* _SCRATCH167_0,                   0x7bc */
-    uint32_t scratch168;                        /* _SCRATCH168_0,                   0x7c0 */
-    uint32_t scratch169;                        /* _SCRATCH169_0,                   0x7c4 */
-    uint32_t scratch170;                        /* _SCRATCH170_0,                   0x7c8 */
-    uint32_t scratch171;                        /* _SCRATCH171_0,                   0x7cc */
-    uint32_t scratch172;                        /* _SCRATCH172_0,                   0x7d0 */
-    uint32_t scratch173;                        /* _SCRATCH173_0,                   0x7d4 */
-    uint32_t scratch174;                        /* _SCRATCH174_0,                   0x7d8 */
-    uint32_t scratch175;                        /* _SCRATCH175_0,                   0x7dc */
-    uint32_t scratch176;                        /* _SCRATCH176_0,                   0x7e0 */
-    uint32_t scratch177;                        /* _SCRATCH177_0,                   0x7e4 */
-    uint32_t scratch178;                        /* _SCRATCH178_0,                   0x7e8 */
-    uint32_t scratch179;                        /* _SCRATCH179_0,                   0x7ec */
-    uint32_t scratch180;                        /* _SCRATCH180_0,                   0x7f0 */
-    uint32_t scratch181;                        /* _SCRATCH181_0,                   0x7f4 */
-    uint32_t scratch182;                        /* _SCRATCH182_0,                   0x7f8 */
-    uint32_t scratch183;                        /* _SCRATCH183_0,                   0x7fc */
-    uint32_t scratch184;                        /* _SCRATCH184_0,                   0x800 */
-    uint32_t scratch185;                        /* _SCRATCH185_0,                   0x804 */
-    uint32_t scratch186;                        /* _SCRATCH186_0,                   0x808 */
-    uint32_t scratch187;                        /* _SCRATCH187_0,                   0x80c */
-    uint32_t scratch188;                        /* _SCRATCH188_0,                   0x810 */
-    uint32_t scratch189;                        /* _SCRATCH189_0,                   0x814 */
-    uint32_t scratch190;                        /* _SCRATCH190_0,                   0x818 */
-    uint32_t scratch191;                        /* _SCRATCH191_0,                   0x81c */
-    uint32_t scratch192;                        /* _SCRATCH192_0,                   0x820 */
-    uint32_t scratch193;                        /* _SCRATCH193_0,                   0x824 */
-    uint32_t scratch194;                        /* _SCRATCH194_0,                   0x828 */
-    uint32_t scratch195;                        /* _SCRATCH195_0,                   0x82c */
-    uint32_t scratch196;                        /* _SCRATCH196_0,                   0x830 */
-    uint32_t scratch197;                        /* _SCRATCH197_0,                   0x834 */
-    uint32_t scratch198;                        /* _SCRATCH198_0,                   0x838 */
-    uint32_t scratch199;                        /* _SCRATCH199_0,                   0x83c */
-    uint32_t scratch200;                        /* _SCRATCH200_0,                   0x840 */
-    uint32_t scratch201;                        /* _SCRATCH201_0,                   0x844 */
-    uint32_t scratch202;                        /* _SCRATCH202_0,                   0x848 */
-    uint32_t scratch203;                        /* _SCRATCH203_0,                   0x84c */
-    uint32_t scratch204;                        /* _SCRATCH204_0,                   0x850 */
-    uint32_t scratch205;                        /* _SCRATCH205_0,                   0x854 */
-    uint32_t scratch206;                        /* _SCRATCH206_0,                   0x858 */
-    uint32_t scratch207;                        /* _SCRATCH207_0,                   0x85c */
-    uint32_t scratch208;                        /* _SCRATCH208_0,                   0x860 */
-    uint32_t scratch209;                        /* _SCRATCH209_0,                   0x864 */
-    uint32_t scratch210;                        /* _SCRATCH210_0,                   0x868 */
-    uint32_t scratch211;                        /* _SCRATCH211_0,                   0x86c */
-    uint32_t scratch212;                        /* _SCRATCH212_0,                   0x870 */
-    uint32_t scratch213;                        /* _SCRATCH213_0,                   0x874 */
-    uint32_t scratch214;                        /* _SCRATCH214_0,                   0x878 */
-    uint32_t scratch215;                        /* _SCRATCH215_0,                   0x87c */
-    uint32_t scratch216;                        /* _SCRATCH216_0,                   0x880 */
-    uint32_t scratch217;                        /* _SCRATCH217_0,                   0x884 */
-    uint32_t scratch218;                        /* _SCRATCH218_0,                   0x888 */
-    uint32_t scratch219;                        /* _SCRATCH219_0,                   0x88c */
-    uint32_t scratch220;                        /* _SCRATCH220_0,                   0x890 */
-    uint32_t scratch221;                        /* _SCRATCH221_0,                   0x894 */
-    uint32_t scratch222;                        /* _SCRATCH222_0,                   0x898 */
-    uint32_t scratch223;                        /* _SCRATCH223_0,                   0x89c */
-    uint32_t scratch224;                        /* _SCRATCH224_0,                   0x8a0 */
-    uint32_t scratch225;                        /* _SCRATCH225_0,                   0x8a4 */
-    uint32_t scratch226;                        /* _SCRATCH226_0,                   0x8a8 */
-    uint32_t scratch227;                        /* _SCRATCH227_0,                   0x8ac */
-    uint32_t scratch228;                        /* _SCRATCH228_0,                   0x8b0 */
-    uint32_t scratch229;                        /* _SCRATCH229_0,                   0x8b4 */
-    uint32_t scratch230;                        /* _SCRATCH230_0,                   0x8b8 */
-    uint32_t scratch231;                        /* _SCRATCH231_0,                   0x8bc */
-    uint32_t scratch232;                        /* _SCRATCH232_0,                   0x8c0 */
-    uint32_t scratch233;                        /* _SCRATCH233_0,                   0x8c4 */
-    uint32_t scratch234;                        /* _SCRATCH234_0,                   0x8c8 */
-    uint32_t scratch235;                        /* _SCRATCH235_0,                   0x8cc */
-    uint32_t scratch236;                        /* _SCRATCH236_0,                   0x8d0 */
-    uint32_t scratch237;                        /* _SCRATCH237_0,                   0x8d4 */
-    uint32_t scratch238;                        /* _SCRATCH238_0,                   0x8d8 */
-    uint32_t scratch239;                        /* _SCRATCH239_0,                   0x8dc */
-    uint32_t scratch240;                        /* _SCRATCH240_0,                   0x8e0 */
-    uint32_t scratch241;                        /* _SCRATCH241_0,                   0x8e4 */
-    uint32_t scratch242;                        /* _SCRATCH242_0,                   0x8e8 */
-    uint32_t scratch243;                        /* _SCRATCH243_0,                   0x8ec */
-    uint32_t scratch244;                        /* _SCRATCH244_0,                   0x8f0 */
-    uint32_t scratch245;                        /* _SCRATCH245_0,                   0x8f4 */
-    uint32_t scratch246;                        /* _SCRATCH246_0,                   0x8f8 */
-    uint32_t scratch247;                        /* _SCRATCH247_0,                   0x8fc */
-    uint32_t scratch248;                        /* _SCRATCH248_0,                   0x900 */
-    uint32_t scratch249;                        /* _SCRATCH249_0,                   0x904 */
-    uint32_t scratch250;                        /* _SCRATCH250_0,                   0x908 */
-    uint32_t scratch251;                        /* _SCRATCH251_0,                   0x90c */
-    uint32_t scratch252;                        /* _SCRATCH252_0,                   0x910 */
-    uint32_t scratch253;                        /* _SCRATCH253_0,                   0x914 */
-    uint32_t scratch254;                        /* _SCRATCH254_0,                   0x918 */
-    uint32_t scratch255;                        /* _SCRATCH255_0,                   0x91c */
-    uint32_t scratch256;                        /* _SCRATCH256_0,                   0x920 */
-    uint32_t scratch257;                        /* _SCRATCH257_0,                   0x924 */
-    uint32_t scratch258;                        /* _SCRATCH258_0,                   0x928 */
-    uint32_t scratch259;                        /* _SCRATCH259_0,                   0x92c */
-    uint32_t scratch260;                        /* _SCRATCH260_0,                   0x930 */
-    uint32_t scratch261;                        /* _SCRATCH261_0,                   0x934 */
-    uint32_t scratch262;                        /* _SCRATCH262_0,                   0x938 */
-    uint32_t scratch263;                        /* _SCRATCH263_0,                   0x93c */
-    uint32_t scratch264;                        /* _SCRATCH264_0,                   0x940 */
-    uint32_t scratch265;                        /* _SCRATCH265_0,                   0x944 */
-    uint32_t scratch266;                        /* _SCRATCH266_0,                   0x948 */
-    uint32_t scratch267;                        /* _SCRATCH267_0,                   0x94c */
-    uint32_t scratch268;                        /* _SCRATCH268_0,                   0x950 */
-    uint32_t scratch269;                        /* _SCRATCH269_0,                   0x954 */
-    uint32_t scratch270;                        /* _SCRATCH270_0,                   0x958 */
-    uint32_t scratch271;                        /* _SCRATCH271_0,                   0x95c */
-    uint32_t scratch272;                        /* _SCRATCH272_0,                   0x960 */
-    uint32_t scratch273;                        /* _SCRATCH273_0,                   0x964 */
-    uint32_t scratch274;                        /* _SCRATCH274_0,                   0x968 */
-    uint32_t scratch275;                        /* _SCRATCH275_0,                   0x96c */
-    uint32_t scratch276;                        /* _SCRATCH276_0,                   0x970 */
-    uint32_t scratch277;                        /* _SCRATCH277_0,                   0x974 */
-    uint32_t scratch278;                        /* _SCRATCH278_0,                   0x978 */
-    uint32_t scratch279;                        /* _SCRATCH279_0,                   0x97c */
-    uint32_t scratch280;                        /* _SCRATCH280_0,                   0x980 */
-    uint32_t scratch281;                        /* _SCRATCH281_0,                   0x984 */
-    uint32_t scratch282;                        /* _SCRATCH282_0,                   0x988 */
-    uint32_t scratch283;                        /* _SCRATCH283_0,                   0x98c */
-    uint32_t scratch284;                        /* _SCRATCH284_0,                   0x990 */
-    uint32_t scratch285;                        /* _SCRATCH285_0,                   0x994 */
-    uint32_t scratch286;                        /* _SCRATCH286_0,                   0x998 */
-    uint32_t scratch287;                        /* _SCRATCH287_0,                   0x99c */
-    uint32_t scratch288;                        /* _SCRATCH288_0,                   0x9a0 */
-    uint32_t scratch289;                        /* _SCRATCH289_0,                   0x9a4 */
-    uint32_t scratch290;                        /* _SCRATCH290_0,                   0x9a8 */
-    uint32_t scratch291;                        /* _SCRATCH291_0,                   0x9ac */
-    uint32_t scratch292;                        /* _SCRATCH292_0,                   0x9b0 */
-    uint32_t scratch293;                        /* _SCRATCH293_0,                   0x9b4 */
-    uint32_t scratch294;                        /* _SCRATCH294_0,                   0x9b8 */
-    uint32_t scratch295;                        /* _SCRATCH295_0,                   0x9bc */
-    uint32_t scratch296;                        /* _SCRATCH296_0,                   0x9c0 */
-    uint32_t scratch297;                        /* _SCRATCH297_0,                   0x9c4 */
-    uint32_t scratch298;                        /* _SCRATCH298_0,                   0x9c8 */
-    uint32_t scratch299;                        /* _SCRATCH299_0,                   0x9cc */
-    uint32_t _0x9d0[50];
-    uint32_t secure_scratch80;                  /* _SECURE_SCRATCH80_0,             0xa98 */
-    uint32_t secure_scratch81;                  /* _SECURE_SCRATCH81_0,             0xa9c */
-    uint32_t secure_scratch82;                  /* _SECURE_SCRATCH82_0,             0xaa0 */
-    uint32_t secure_scratch83;                  /* _SECURE_SCRATCH83_0,             0xaa4 */
-    uint32_t secure_scratch84;                  /* _SECURE_SCRATCH84_0,             0xaa8 */
-    uint32_t secure_scratch85;                  /* _SECURE_SCRATCH85_0,             0xaac */
-    uint32_t secure_scratch86;                  /* _SECURE_SCRATCH86_0,             0xab0 */
-    uint32_t secure_scratch87;                  /* _SECURE_SCRATCH87_0,             0xab4 */
-    uint32_t secure_scratch88;                  /* _SECURE_SCRATCH88_0,             0xab8 */
-    uint32_t secure_scratch89;                  /* _SECURE_SCRATCH89_0,             0xabc */
-    uint32_t secure_scratch90;                  /* _SECURE_SCRATCH90_0,             0xac0 */
-    uint32_t secure_scratch91;                  /* _SECURE_SCRATCH91_0,             0xac4 */
-    uint32_t secure_scratch92;                  /* _SECURE_SCRATCH92_0,             0xac8 */
-    uint32_t secure_scratch93;                  /* _SECURE_SCRATCH93_0,             0xacc */
-    uint32_t secure_scratch94;                  /* _SECURE_SCRATCH94_0,             0xad0 */
-    uint32_t secure_scratch95;                  /* _SECURE_SCRATCH95_0,             0xad4 */
-    uint32_t secure_scratch96;                  /* _SECURE_SCRATCH96_0,             0xad8 */
-    uint32_t secure_scratch97;                  /* _SECURE_SCRATCH97_0,             0xadc */
-    uint32_t secure_scratch98;                  /* _SECURE_SCRATCH98_0,             0xae0 */
-    uint32_t secure_scratch99;                  /* _SECURE_SCRATCH99_0,             0xae4 */
-    uint32_t secure_scratch100;                 /* _SECURE_SCRATCH100_0,            0xae8 */
-    uint32_t secure_scratch101;                 /* _SECURE_SCRATCH101_0,            0xaec */
-    uint32_t secure_scratch102;                 /* _SECURE_SCRATCH102_0,            0xaf0 */
-    uint32_t secure_scratch103;                 /* _SECURE_SCRATCH103_0,            0xaf4 */
-    uint32_t secure_scratch104;                 /* _SECURE_SCRATCH104_0,            0xaf8 */
-    uint32_t secure_scratch105;                 /* _SECURE_SCRATCH105_0,            0xafc */
-    uint32_t secure_scratch106;                 /* _SECURE_SCRATCH106_0,            0xb00 */
-    uint32_t secure_scratch107;                 /* _SECURE_SCRATCH107_0,            0xb04 */
-    uint32_t secure_scratch108;                 /* _SECURE_SCRATCH108_0,            0xb08 */
-    uint32_t secure_scratch109;                 /* _SECURE_SCRATCH109_0,            0xb0c */
-    uint32_t secure_scratch110;                 /* _SECURE_SCRATCH110_0,            0xb10 */
-    uint32_t secure_scratch111;                 /* _SECURE_SCRATCH111_0,            0xb14 */
-    uint32_t secure_scratch112;                 /* _SECURE_SCRATCH112_0,            0xb18 */
-    uint32_t secure_scratch113;                 /* _SECURE_SCRATCH113_0,            0xb1c */
-    uint32_t secure_scratch114;                 /* _SECURE_SCRATCH114_0,            0xb20 */
-    uint32_t secure_scratch115;                 /* _SECURE_SCRATCH115_0,            0xb24 */
-    uint32_t secure_scratch116;                 /* _SECURE_SCRATCH116_0,            0xb28 */
-    uint32_t secure_scratch117;                 /* _SECURE_SCRATCH117_0,            0xb2c */
-    uint32_t secure_scratch118;                 /* _SECURE_SCRATCH118_0,            0xb30 */
-    uint32_t secure_scratch119;                 /* _SECURE_SCRATCH119_0,            0xb34 */
-    uint32_t secure_scratch120;                 /* _SECURE_SCRATCH120_0,            0xb38 */
-    uint32_t secure_scratch121;                 /* _SECURE_SCRATCH121_0,            0xb3c */
-    uint32_t secure_scratch122;                 /* _SECURE_SCRATCH122_0,            0xb40 */
-    uint32_t secure_scratch123;                 /* _SECURE_SCRATCH123_0,            0xb44 */
-    uint32_t led_breathing_ctrl;                /* _LED_BREATHING_CTRL_0,           0xb48 */
-    uint32_t led_breathing_counter0;            /* _LED_BREATHING_COUNTER0_0,       0xb4c */
-    uint32_t led_breathing_counter1;            /* _LED_BREATHING_COUNTER1_0,       0xb50 */
-    uint32_t led_breathing_counter2;            /* _LED_BREATHING_COUNTER2_0,       0xb54 */
-    uint32_t led_breathing_counter3;            /* _LED_BREATHING_COUNTER3_0,       0xb58 */
-    uint32_t led_breathing_status;              /* _LED_BREATHING_STATUS_0,         0xb5c */
-    uint32_t _0xb60[2];
-    uint32_t secure_scratch124;                 /* _SECURE_SCRATCH124_0,            0xb68 */
-    uint32_t secure_scratch125;                 /* _SECURE_SCRATCH125_0,            0xb6c */
-    uint32_t secure_scratch126;                 /* _SECURE_SCRATCH126_0,            0xb70 */
-    uint32_t secure_scratch127;                 /* _SECURE_SCRATCH127_0,            0xb74 */
-    uint32_t secure_scratch128;                 /* _SECURE_SCRATCH128_0,            0xb78 */
-    uint32_t secure_scratch129;                 /* _SECURE_SCRATCH129_0,            0xb7c */
-    uint32_t secure_scratch130;                 /* _SECURE_SCRATCH130_0,            0xb80 */
-    uint32_t secure_scratch131;                 /* _SECURE_SCRATCH131_0,            0xb84 */
-    uint32_t secure_scratch132;                 /* _SECURE_SCRATCH132_0,            0xb88 */
-    uint32_t secure_scratch133;                 /* _SECURE_SCRATCH133_0,            0xb8c */
-    uint32_t secure_scratch134;                 /* _SECURE_SCRATCH134_0,            0xb90 */
-    uint32_t secure_scratch135;                 /* _SECURE_SCRATCH135_0,            0xb94 */
-    uint32_t secure_scratch136;                 /* _SECURE_SCRATCH136_0,            0xb98 */
-    uint32_t secure_scratch137;                 /* _SECURE_SCRATCH137_0,            0xb9c */
-    uint32_t secure_scratch138;                 /* _SECURE_SCRATCH138_0,            0xba0 */
-    uint32_t secure_scratch139;                 /* _SECURE_SCRATCH139_0,            0xba4 */
-    uint32_t _0xba8[2];
-    uint32_t sec_disable_ns;                    /* _SEC_DISABLE_NS_0,               0xbb0 */
-    uint32_t sec_disable2_ns;                   /* _SEC_DISABLE2_NS_0,              0xbb4 */
-    uint32_t sec_disable3_ns;                   /* _SEC_DISABLE3_NS_0,              0xbb8 */
-    uint32_t sec_disable4_ns;                   /* _SEC_DISABLE4_NS_0,              0xbbc */
-    uint32_t sec_disable5_ns;                   /* _SEC_DISABLE5_NS_0,              0xbc0 */
-    uint32_t sec_disable6_ns;                   /* _SEC_DISABLE6_NS_0,              0xbc4 */
-    uint32_t sec_disable7_ns;                   /* _SEC_DISABLE7_NS_0,              0xbc8 */
-    uint32_t sec_disable8_ns;                   /* _SEC_DISABLE8_NS_0,              0xbcc */
-    uint32_t sec_disable9_ns;                   /* _SEC_DISABLE9_NS_0,              0xbd0 */
-    uint32_t sec_disable10_ns;                  /* _SEC_DISABLE10_NS_0,             0xbd4 */
-    uint32_t _0xbd8[4];
-    uint32_t tzram_pwr_cntrl;                   /* _TZRAM_PWR_CNTRL_0,              0xbe8 */
-    uint32_t tzram_sec_disable;                 /* _TZRAM_SEC_DISABLE_0,            0xbec */
-    uint32_t tzram_non_sec_disable;             /* _TZRAM_NON_SEC_DISABLE_0,        0xbf0 */
-} tegra_pmc_t;
-
-static inline volatile tegra_pmc_t *pmc_get_regs(void)
-{
-    return (volatile tegra_pmc_t *)PMC_BASE;
-}
-
-#endif

fusee/fusee-mtc/src/start.s

@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2018 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-.macro CLEAR_GPR_REG_ITER
-    mov r\@, #0
-.endm
-
-.section .text.start, "ax", %progbits
-.arm
-.align 5
-.global _start
-.type   _start, %function
-_start:
-    /* Switch to system mode, mask all interrupts, clear all flags */
-    msr cpsr_cxsf, #0xDF
-    
-    /* Backup current stack pointer. */
-    mov r12, sp
-    
-    /* Set the stack pointer */
-    ldr  sp, =__stack_top__
-    mov  fp, #0
-    
-    /* Save context */
-    push {r12, lr}
-    
-    /* Call init. */
-    bl  __program_init
-
-    /* Set r0 to r12 to 0 (for debugging) & call main */
-    .rept 13
-    CLEAR_GPR_REG_ITER
-    .endr
-    ldr r0, =__program_argc
-    ldr r1, =__program_argv
-    ldr r0, [r0]
-    ldr r1, [r1]
-    bl   main
-    
-    /* Save result. */
-    push {r0}
-    
-    /* Exit manually. */
-    bl  __program_exit
-    
-    /* Restore result. */
-    pop {r0}
-
-    /* Restore context */
-    pop {r12}
-    pop {lr}
-    
-    /* Restore previous stack pointer. */
-    mov sp, r12
-    
-    /* Return */
-    bx lr

fusee/fusee-mtc/src/timers.h

@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_TIMERS_H
-#define FUSEE_TIMERS_H
-
-#include "utils.h"
-
-#define TIMERS_BASE 0x60005000
-#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
-
-#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
-#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
-#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0)
-#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4)
-
-#define RTC_BASE 0x7000E000
-#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
-
-#define RTC_SECONDS MAKE_RTC_REG(0x08)
-#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
-#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
-
-typedef struct {
-    uint32_t CONFIG;
-    uint32_t STATUS;
-    uint32_t COMMAND;
-    uint32_t PATTERN;
-} watchdog_timers_t;
-
-#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
-#define WDT_REBOOT_PATTERN 0xC45A
-#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n)
-
-void wait(uint32_t microseconds);
-
-static inline uint32_t get_time_s(void) {
-    return RTC_SECONDS;
-}
-
-static inline uint32_t get_time_ms(void) {
-    return (RTC_MILLI_SECONDS | (RTC_SHADOW_SECONDS << 10));
-}
-
-static inline uint32_t get_time_us(void) {
-    return TIMERUS_CNTR_1US_0;
-}
-
-/**
- * Returns the time in microseconds.
- */
-static inline uint32_t get_time(void) {
-    return get_time_us();
-}
-
-/**
- * Returns the number of microseconds that have passed since a given get_time().
- */
-static inline uint32_t get_time_since(uint32_t base) {
-    return get_time_us() - base;
-}
-
-/**
- * Delays for a given number of microseconds.
- */
-static inline void udelay(uint32_t usecs) {
-    uint32_t start = get_time_us();
-    while (get_time_us() - start < usecs);
-}
-
-/**
- * Delays for a given number of milliseconds.
- */
-static inline void mdelay(uint32_t msecs) {
-    uint32_t start = get_time_ms();
-    while (get_time_ms() - start < msecs);
-}
-
-__attribute__ ((noreturn)) void watchdog_reboot(void);
-
-#endif

fusee/fusee-mtc/src/utils.c

@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdbool.h>
-#include <stdarg.h>
-#include "utils.h"
-#include "../../../fusee/common/display/video_fb.h"
-#include "../../../fusee/common/log.h"
-
-__attribute__ ((noreturn)) void generic_panic(void) {
-    while (true) {
-        /* Lock. */
-    }
-}
-
-__attribute__((noreturn)) void fatal_error(const char *fmt, ...) {
-    /* Forcefully initialize the screen if logging is disabled. */
-    if (log_get_log_level() == SCREEN_LOG_LEVEL_NONE) {
-        /* Zero-fill the framebuffer and register it as printk provider. */
-        video_init((void *)0xC0000000);
-        
-        /* Override the global logging level. */
-        log_set_log_level(SCREEN_LOG_LEVEL_ERROR);
-    }
-    
-    /* Display fatal error. */
-    va_list args;
-    print(SCREEN_LOG_LEVEL_ERROR, "Fatal error: ");
-    va_start(args, fmt);
-    vprint(SCREEN_LOG_LEVEL_ERROR, fmt, args);
-    va_end(args);
-    
-    while (true) {
-        /* Lock. */
-    }
-}

fusee/fusee-mtc/src/utils.h

@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_UTILS_H
-#define FUSEE_UTILS_H
-
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <string.h>
-
-#define BIT(n)      (1u   << (n))
-#define BITL(n)     (1ull << (n))
-#define MASK(n)     (BIT(n) - 1)
-#define MASKL(n)    (BITL(n) - 1)
-#define MASK2(a,b)  (MASK(a) & ~MASK(b))
-#define MASK2L(a,b) (MASKL(a) & ~MASKL(b))
-
-#define MAKE_REG32(a)   (*(volatile uint32_t *)(a))
-
-#define ALIGN(m)        __attribute__((aligned(m)))
-#define PACKED          __attribute__((packed))
-
-#define ALINLINE        __attribute__((always_inline))
-#define NOINLINE        __attribute__((noinline))
-
-__attribute__((noreturn)) void generic_panic(void);
-__attribute__((noreturn)) void fatal_error(const char *fmt, ...);
-
-#endif

fusee/fusee-primary/Makefile

@@ -46,6 +46,7 @@ DEFINES :=	-D__BPMP__ -DFUSEE_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\
 
 CFLAGS	:= \
 	-g \
+	-gdwarf-4 \
 	-O2 \
 	-fomit-frame-pointer \
 	-ffunction-sections \
@@ -53,6 +54,9 @@ CFLAGS	:= \
 	-std=gnu11 \
 	-Werror \
 	-Wall \
+	-Wno-array-bounds \
+	-Wno-stringop-overflow \
+	-Wno-stringop-overread \
 	-fstrict-volatile-bitfields \
 	$(ARCH) $(DEFINES)
 
@@ -60,8 +64,8 @@ CFLAGS	+=	$(INCLUDE)
 
 CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
 
-ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
+ASFLAGS	:=	-g -gdwarf-4 $(ARCH)
+LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map)
 
 LIBS	:=
 

fusee/fusee-primary/fusee-primary-main/Makefile

@@ -39,6 +39,7 @@ DEFINES :=	-D__BPMP__ -DFUSEE_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\
 
 CFLAGS	:= \
 	-g \
+	-gdwarf-4 \
 	-O2 \
 	-fomit-frame-pointer \
 	-ffunction-sections \
@@ -46,6 +47,9 @@ CFLAGS	:= \
 	-std=gnu11 \
 	-Werror \
 	-Wall \
+	-Wno-array-bounds \
+	-Wno-stringop-overflow \
+	-Wno-stringop-overread \
 	-fstrict-volatile-bitfields \
 	$(ARCH) $(DEFINES)
 
@@ -53,8 +57,8 @@ CFLAGS	+=	$(INCLUDE)
 
 CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
 
-ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
+ASFLAGS	:=	-g -gdwarf-4 $(ARCH)
+LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map)
 
 LIBS	:=
 

fusee/fusee-primary/fusee-primary-main/src/hwinit.c

@@ -158,7 +158,12 @@ static void config_se_brom(void) {
 
     /* Bootrom part we skipped. */
     uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]};
-    set_aes_keyslot(0xE, sbk, 0x10);
+    for (int i = 0; i < 4; ++i) {
+        if (sbk[i] != 0xFFFFFFFF) {
+            set_aes_keyslot(0xE, sbk, 0x10);
+            break;
+        }
+    }
 
     /* Lock SBK from being read. */
     se->SE_CRYPTO_KEYTABLE_ACCESS[0xE] = 0x7E;
@@ -247,7 +252,7 @@ void nx_hwinit(bool enable_log) {
     } else {
         uint8_t val = 0x40;
         i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
-        val = 0x60;
+        val = 0x58;
         i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
         val = 0x38;
         i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1);

fusee/fusee-primary/fusee-primary-main/src/stage2.c

@@ -55,42 +55,6 @@ static int stage2_ini_handler(void *user, const char *section, const char *name,
     return 1;
 }
 
-static bool run_mtc(const char *mtc_path, uintptr_t mtc_address) {
-    FILINFO info;
-    size_t size;
-
-    /* Check if the MTC binary is present. */
-    if (f_stat(mtc_path, &info) != FR_OK) {
-        print(SCREEN_LOG_LEVEL_WARNING, "Stage2's MTC binary not found!\n");
-        return false;
-    }
-
-    size = (size_t)info.fsize;
-
-    /* Try to read the MTC binary. */
-    if (read_from_file((void *)mtc_address, size, mtc_path) != size) {
-        print(SCREEN_LOG_LEVEL_WARNING, "Failed to read stage2's MTC binary (%s)!\n", mtc_path);
-        return false;
-    }
-
-    ScreenLogLevel mtc_log_level = log_get_log_level();
-    bool mtc_res = false;
-    int mtc_argc = 1;
-    char mtc_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE] = {0};
-    stage2_mtc_args_t *mtc_args = (stage2_mtc_args_t *)mtc_arg_data;
-
-    /* Setup argument data. */
-    memcpy(&mtc_args->log_level, &mtc_log_level, sizeof(mtc_log_level));
-
-    /* Run the MTC binary. */
-    mtc_res = (((int (*)(int, void *))mtc_address)(mtc_argc, mtc_arg_data) == 0);
-
-    /* Cleanup right away. */
-    memset((void *)mtc_address, 0, size);
-
-    return mtc_res;
-}
-
 void load_stage2(const char *bct0) {
     stage2_config_t config = {0};
     FILINFO info;
@@ -123,11 +87,6 @@ void load_stage2(const char *bct0) {
     print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, "    Load Address: 0x%08x\n", config.load_address);
     print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, "    Entrypoint:   0x%p\n", config.entrypoint);
 
-    /* Run the MTC binary. */
-    if (!run_mtc(config.mtc_path, config.load_address)) {
-        print(SCREEN_LOG_LEVEL_WARNING, "DRAM training failed! Continuing with untrained DRAM.\n");
-    }
-
     if (f_stat(config.path, &info) != FR_OK) {
         fatal_error("Failed to stat stage2 (%s)!\n", config.path);
     }

fusee/fusee-secondary/Makefile

@@ -36,7 +36,7 @@ endef
 #---------------------------------------------------------------------------------
 TARGET		:=	$(notdir $(CURDIR))
 BUILD		:=	build
-SOURCES		:=	src ../../fusee/common ../../fusee/common/display ../../fusee/common/fatfs ../../fusee/common/sdmmc
+SOURCES		:=	src ../../fusee/common ../../fusee/common/display ../../fusee/common/fatfs ../../fusee/common/sdmmc src/mtc
 DATA		:=	data
 INCLUDES	:=	include ../../libraries/libvapours/include
 
@@ -48,6 +48,7 @@ DEFINES :=	-D__BPMP__ -DFUSEE_STAGE2_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\
 
 CFLAGS	:= \
 	-g \
+	-gdwarf-4 \
 	-O2 \
 	-fomit-frame-pointer \
 	-ffunction-sections \
@@ -55,6 +56,9 @@ CFLAGS	:= \
 	-std=gnu11 \
 	-Werror \
 	-Wall \
+	-Wno-array-bounds \
+	-Wno-stringop-overflow \
+	-Wno-stringop-overread \
 	-fstrict-volatile-bitfields \
 	$(ARCH) $(DEFINES)
 
@@ -62,8 +66,8 @@ CFLAGS	+=	$(INCLUDE)
 
 CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
 
-ASFLAGS	:=	-g $(ARCH) $(INCLUDE) $(DEFINES)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
+ASFLAGS	:=	-g -gdwarf-4 $(ARCH) $(INCLUDE) $(DEFINES)
+LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map)
 
 LIBS	:=
 
@@ -88,8 +92,8 @@ export KIPDIRS	:= $(AMS)/stratosphere/loader $(AMS)/stratosphere/ncm $(AMS)/stra
 export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
 			$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
 			$(AMS)/exosphere $(AMS)/exosphere/warmboot $(AMS)/exosphere/program/rebootstub \
-			$(AMS)/thermosphere $(AMS)/fusee/fusee-primary $(AMS)/sept/sept-primary \
-			$(AMS)/sept/sept-secondary $(AMS)/emummc $(AMS)/mesosphere $(AMS)/mesosphere/kernel_ldr $(KIPDIRS)
+			$(AMS)/thermosphere $(AMS)/fusee/fusee-primary $(AMS)/emummc $(AMS)/mesosphere \
+			$(KIPDIRS)
 
 export DEPSDIR	:=	$(CURDIR)/$(BUILD)
 
@@ -99,9 +103,7 @@ SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
 KIPFILES 	:=	loader.kip ncm.kip pm.kip sm.kip ams_mitm.kip spl.kip boot.kip
 BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) fusee-primary.bin \
 				exosphere.bin warmboot.bin rebootstub.bin thermosphere.bin splash_screen.bin \
-				sept-primary.bin sept-secondary_00.enc sept-secondary_01.enc emummc.kip \
-				sept-secondary_dev_00.enc sept-secondary_dev_01.enc mesosphere.bin kernel_ldr.bin \
-                mariko_fatal.bin $(KIPFILES)
+			    emummc.kip mesosphere.bin mariko_fatal.bin $(KIPFILES)
 
 #---------------------------------------------------------------------------------
 # use CXX for linking C++ projects, CC for standard C
@@ -129,7 +131,7 @@ export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
 export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
 
 .PHONY: $(BUILD) clean all
-.PHONY: check_fusee_primary check_exosphere check_sept check_emummc check_thermosphere check_stratosphere check_libraries
+.PHONY: check_fusee_primary check_exosphere check_emummc check_thermosphere check_stratosphere check_libraries
 
 #---------------------------------------------------------------------------------
 all: $(BUILD)
@@ -140,9 +142,6 @@ check_fusee_primary:
 check_exosphere:
 	@$(MAKE) -C $(AMS)/exosphere all
 
-check_sept:
-	@$(MAKE) -C $(AMS)/sept all
-
 check_emummc:
 	@$(MAKE) -C $(AMS)/emummc EMUMMCDIR=$(AMS)/emummc all
 
@@ -159,7 +158,7 @@ check_libraries:
 	@$(MAKE) -C $(AMS)/libraries all
 
 
-$(BUILD): check_fusee_primary check_exosphere check_sept check_emummc check_thermosphere check_libraries check_stratosphere check_mesosphere
+$(BUILD): check_fusee_primary check_exosphere check_emummc check_thermosphere check_libraries check_stratosphere check_mesosphere
 	@[ -d $@ ] || mkdir -p $@
 	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
 
@@ -172,7 +171,6 @@ clean:
 	@$(MAKE) -C $(AMS)/libraries clean
 	@$(MAKE) -C $(AMS)/mesosphere clean
 	@$(MAKE) -C $(AMS)/stratosphere clean
-	@$(MAKE) -C $(AMS)/sept clean
 	@$(MAKE) -C $(AMS)/emummc clean
 	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
 
@@ -212,31 +210,6 @@ fusee_primary.bin.o	fusee_primary_bin.h:	fusee-primary.bin
 	@echo $(notdir $<)
 	@$(_bin2o)
 
-sept_primary.bin.o	sept_primary_bin.h:	sept-primary.bin
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(_bin2o)
-
-sept_secondary_00.enc.o	sept_secondary_00_enc.h:	sept-secondary_00.enc
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(_bin2o)
-
-sept_secondary_01.enc.o	sept_secondary_01_enc.h:	sept-secondary_01.enc
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(_bin2o)
-
-sept_secondary_dev_00.enc.o	sept_secondary_dev_00_enc.h:	sept-secondary_dev_00.enc
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(_bin2o)
-
-sept_secondary_dev_01.enc.o	sept_secondary_dev_01_enc.h:	sept-secondary_dev_01.enc
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(_bin2o)
-
 %.bin.o	%_bin.h:	%.bin
 #---------------------------------------------------------------------------------
 	@echo $(notdir $<)

fusee/fusee-secondary/linker.ld

@@ -244,12 +244,6 @@ SECTIONS
     PROVIDE(__pm_kip_size__ = pm_kip_end - pm_kip);
     PROVIDE(__rebootstub_bin_start__ = rebootstub_bin - __start__);
     PROVIDE(__rebootstub_bin_size__ = rebootstub_bin_end - rebootstub_bin);
-    PROVIDE(__sept_primary_bin_start__ = sept_primary_bin - __start__);
-    PROVIDE(__sept_primary_bin_size__ = sept_primary_bin_end - sept_primary_bin);
-    PROVIDE(__sept_secondary_00_enc_start__ = sept_secondary_00_enc - __start__);
-    PROVIDE(__sept_secondary_00_enc_size__ = sept_secondary_00_enc_end - sept_secondary_00_enc);
-    PROVIDE(__sept_secondary_01_enc_start__ = sept_secondary_01_enc - __start__);
-    PROVIDE(__sept_secondary_01_enc_size__ = sept_secondary_01_enc_end - sept_secondary_01_enc);
     PROVIDE(__sm_kip_start__ = sm_kip - __start__);
     PROVIDE(__sm_kip_size__ = sm_kip_end - sm_kip);
     PROVIDE(__spl_kip_start__ = spl_kip - __start__);
@@ -266,4 +260,6 @@ SECTIONS
     PROVIDE(__mesosphere_bin_size__ = mesosphere_bin_end - mesosphere_bin);
     PROVIDE(__mariko_fatal_bin_start__ = mariko_fatal_bin - __start__);
     PROVIDE(__mariko_fatal_bin_size__ = mariko_fatal_bin_end - mariko_fatal_bin);
+    PROVIDE(__tsec_keygen_bin_start__ = tsec_keygen_bin - __start__);
+    PROVIDE(__tsec_keygen_bin_size__ = tsec_keygen_bin_end - tsec_keygen_bin);
 }

fusee/fusee-secondary/src/car.h

@@ -13,7 +13,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #ifndef FUSEE_CAR_H
 #define FUSEE_CAR_H
 
@@ -51,7 +51,7 @@ typedef enum {
     CARDEVICE_USB2      = ((1 << 5) | 0x1A),
     CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
     CARDEVICE_TSEC      = ((2 << 5) | 0x13),
-    CARDEVICE_MSELECT   = ((3 << 5) | 0x8),
+    CARDEVICE_MSELECT   = ((3 << 5) | 0x3),
     CARDEVICE_ACTMON    = ((3 << 5) | 0x17),
     CARDEVICE_TZRAM     = ((3 << 5) | 0x1E),
     CARDEVICE_SE        = ((3 << 5) | 0x1F),
@@ -489,7 +489,16 @@ typedef struct {
     uint32_t sdmmc4_pllc4_out0_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
     uint32_t sdmmc4_pllc4_out1_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
     uint32_t sdmmc4_pllc4_out2_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
-    uint32_t sdmmc4_div_clk_shaper_ctrl;            /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */    
+    uint32_t sdmmc4_div_clk_shaper_ctrl;            /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
+
+    uint32_t _0x748[(0x774-0x748) / sizeof(uint32_t)]; // TODO
+
+    uint32_t pllm_ss_cfg;                           /* _PLLM_SS_CFG_0, 0x744 */
+    uint32_t pllm_ss_ctrl1;                         /* _PLLM_SS_CTRL1_0, 0x778 */
+    uint32_t pllm_ss_ctrl2;                         /* _PLLM_SS_CTRL2_0, 0x77C */
+    uint32_t pllmb_ss_cfg;                          /* _PLLMB_SS_CFG_0, 0x780 */
+    uint32_t pllmb_ss_ctrl1;                        /* _PLLMB_SS_CTRL1_0, 0x784 */
+    uint32_t pllmb_ss_ctrl2;                        /* _PLLMB_SS_CTRL2_0, 0x788 */
 } tegra_car_t;
 
 static inline volatile tegra_car_t *car_get_regs(void) {

fusee/fusee-secondary/src/emc.h

@@ -19,7 +19,7 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
  */
- 
+
 #ifndef FUSEE_EMC_H_
 #define FUSEE_EMC_H_
 
@@ -393,6 +393,7 @@
 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
 #define EMC_DIG_DLL_STATUS                  0x2c4
 #define EMC_DIG_DLL_STATUS_DLL_LOCK             (1 << 15)
+#define EMC_DIG_DLL_STATUS_DLL_LOCK_B01         (1 << 2)
 #define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED         (1 << 17)
 #define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT            0
 #define EMC_DIG_DLL_STATUS_DLL_OUT_MASK             \
@@ -1065,6 +1066,10 @@
 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC      (1 << 16)
 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC       (1 << 24)
 
+#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF_B01       (1 << 10)
+
+
+
 #define EMC_PMACRO_COMMON_PAD_TX_CTRL               0xc68
 #define EMC_PMACRO_BRICK_MAPPING_0              0xc80
 #define EMC_PMACRO_BRICK_MAPPING_1              0xc84
@@ -1126,4 +1131,8 @@
 
 #define EMC_PMACRO_DSR_VTTGEN_CTRL_0                    0xc6c
 
+// B01
+#define EMC_PMACRO_DLL_CFG_0 0x5E4
+#define EMC_PMACRO_DLL_CFG_1 0x5E8
+
 #endif

fusee/fusee-secondary/src/emummc_cfg.h

@@ -94,6 +94,9 @@ typedef enum {
     FS_VER_12_0_0,
     FS_VER_12_0_0_EXFAT,
 
+    FS_VER_12_0_3,
+    FS_VER_12_0_3_EXFAT,
+
     FS_VER_MAX,
 } emummc_fs_ver_t;
 

fusee/fusee-secondary/src/fuse.c

@@ -348,6 +348,7 @@ uint32_t fuse_get_regulator(void) {
 
 
 static const uint32_t fuse_version_increment_firmwares[] = {
+    ATMOSPHERE_TARGET_FIRMWARE_12_0_2,
     ATMOSPHERE_TARGET_FIRMWARE_11_0_0,
     ATMOSPHERE_TARGET_FIRMWARE_10_0_0,
     ATMOSPHERE_TARGET_FIRMWARE_9_1_0,

fusee/fusee-secondary/src/ips.c

@@ -429,6 +429,9 @@ static const uint8_t g_fs_hashes[FS_VER_MAX][0x8] = {
 
     "\xDC\x2A\x08\x49\x96\xBB\x3C\x01", /* FS_VER_12_0_0 */
     "\xD5\xA5\xBF\x36\x64\x0C\x49\xEA", /* FS_VER_12_0_0_EXFAT */
+
+    "\xC8\x67\x62\xBE\x19\xA5\x1F\xA0", /* FS_VER_12_0_3 */
+    "\xE1\xE8\xD3\xD6\xA2\xFE\x0B\x10", /* FS_VER_12_0_3_EXFAT */
 };
 
 kip1_header_t *apply_kip_ips_patches(kip1_header_t *kip, size_t kip_size, emummc_fs_ver_t *out_fs_ver) {

fusee/fusee-secondary/src/kernel_patches.c

@@ -21,12 +21,6 @@
 #include "kernel_patches.h"
 #include "ips.h"
 
-#define u8 uint8_t
-#define u32 uint32_t
-#include "kernel_ldr_bin.h"
-#undef u8
-#undef u32
-
 #define MAKE_BRANCH(a, o) 0x14000000 | ((((o) - (a)) >> 2) & 0x3FFFFFF)
 #define MAKE_NOP 0xD503201F
 

fusee/fusee-secondary/src/key_derivation.c

@@ -26,19 +26,6 @@
 
 #define AL16 ALIGN(16)
 
-static const uint8_t AL16 keyblob_seeds[MASTERKEY_REVISION_MAX][0x10] = {
-    {0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3},   /* Keyblob seed 00. */
-    {0x0C, 0x25, 0x61, 0x5D, 0x68, 0x4C, 0xEB, 0x42, 0x1C, 0x23, 0x79, 0xEA, 0x82, 0x25, 0x12, 0xAC},   /* Keyblob seed 01. */
-    {0x33, 0x76, 0x85, 0xEE, 0x88, 0x4A, 0xAE, 0x0A, 0xC2, 0x8A, 0xFD, 0x7D, 0x63, 0xC0, 0x43, 0x3B},   /* Keyblob seed 02. */
-    {0x2D, 0x1F, 0x48, 0x80, 0xED, 0xEC, 0xED, 0x3E, 0x3C, 0xF2, 0x48, 0xB5, 0x65, 0x7D, 0xF7, 0xBE},   /* Keyblob seed 03. */
-    {0xBB, 0x5A, 0x01, 0xF9, 0x88, 0xAF, 0xF5, 0xFC, 0x6C, 0xFF, 0x07, 0x9E, 0x13, 0x3C, 0x39, 0x80},   /* Keyblob seed 04. */
-    {0xD8, 0xCC, 0xE1, 0x26, 0x6A, 0x35, 0x3F, 0xCC, 0x20, 0xF3, 0x2D, 0x3B, 0x51, 0x7D, 0xE9, 0xC0}    /* Keyblob seed 05. */
-};
-
-static const uint8_t AL16 keyblob_mac_seed[0x10] = {
-    0x59, 0xC7, 0xFB, 0x6F, 0xBE, 0x9B, 0xBE, 0x87, 0x65, 0x6B, 0x15, 0xC0, 0x53, 0x73, 0x36, 0xA5
-};
-
 static const uint8_t AL16 masterkey_seed[0x10] = {
     0xD8, 0xA2, 0x41, 0x0A, 0xC6, 0xC5, 0x90, 0x01, 0xC6, 0x1D, 0x6A, 0x26, 0x7C, 0x51, 0x3F, 0x3C
 };
@@ -55,164 +42,51 @@ static const uint8_t AL16 masterkey_4x_seed[0x10] = {
     0x2D, 0xC1, 0xF4, 0x8D, 0xF3, 0x5B, 0x69, 0x33, 0x42, 0x10, 0xAC, 0x65, 0xDA, 0x90, 0x46, 0x66
 };
 
-/* TODO: Bother adding 8.1.0 here? We'll never call into here... */
-static const uint8_t AL16 new_master_kek_seeds[MASTERKEY_REVISION_700_800 - MASTERKEY_REVISION_600_610][0x10] = {
-    {0x37, 0x4B, 0x77, 0x29, 0x59, 0xB4, 0x04, 0x30, 0x81, 0xF6, 0xE5, 0x8C, 0x6D, 0x36, 0x17, 0x9A}, /* MasterKek seed 06. */
-    {0x9A, 0x3E, 0xA9, 0xAB, 0xFD, 0x56, 0x46, 0x1C, 0x9B, 0xF6, 0x48, 0x7F, 0x5C, 0xFA, 0x09, 0x5C}, /* MasterKek seed 07. */
+static const uint8_t AL16 keyblob_seed_00[0x10] = {
+    0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3
+};
+
+static const uint8_t AL16 master_kek_seed_erista[0x10] = { /* TODO: Update on next change of keys. */
+    0x84, 0x67, 0xB6, 0x7F, 0x13, 0x11, 0xAE, 0xE6, 0x58, 0x9B, 0x19, 0xAF, 0x13, 0x6C, 0x80, 0x7A /* Erista MasterKek seed 0B. */
+};
+
+static const uint8_t AL16 master_devkey_seed_erista[0x10] = {
+    0xAA, 0xFD, 0xBC, 0xBB, 0x25, 0xC3, 0xA4, 0xEF, 0xE3, 0xEE, 0x58, 0x53, 0xB7, 0xF8, 0xDD, 0xD6
 };
 
 static const uint8_t AL16 master_kek_seed_mariko[0x10] = { /* TODO: Update on next change of keys. */
-    0x0E, 0x44, 0x0C, 0xED, 0xB4, 0x36, 0xC0, 0x3F, 0xAA, 0x1D, 0xAE, 0xBF, 0x62, 0xB1, 0x09, 0x82, /* Mariko MasterKek seed 0A. */
+    0xE5, 0x41, 0xAC, 0xEC, 0xD1, 0xA7, 0xD1, 0xAB, 0xED, 0x03, 0x77, 0xF1, 0x27, 0xCA, 0xF8, 0xF1, /* Mariko MasterKek seed 0B. */
 };
 
-static nx_dec_keyblob_t AL16 g_dec_keyblobs[32];
-
-static int get_keyblob(nx_keyblob_t *dst, uint32_t revision, const nx_keyblob_t *keyblobs, uint32_t available_revision) {
-    if (revision >= 0x20) {
-        return -1;
-        /* TODO: what should we do? */
-    }
-
-    if (keyblobs != NULL) {
-        *dst = keyblobs[revision];
-    } else {
-        return -1;
-        /* TODO: what should we do? */
-    }
-
-    return 0;
-}
-
-static bool safe_memcmp(uint8_t *a, uint8_t *b, size_t sz) {
-    uint8_t different = 0;
-    for (unsigned int i = 0; i < sz; i++) {
-        different |= a[i] ^ b[i];
-    }
-    return different != 0;
-}
-
-static int decrypt_keyblob(const nx_keyblob_t *keyblobs, uint32_t revision, uint32_t available_revision) {
-    nx_keyblob_t AL16 keyblob;
-    uint8_t AL16 work_buffer[0x10];
-    unsigned int keyslot = revision == MASTERKEY_REVISION_100_230 ? 0xF : KEYSLOT_SWITCH_TEMPKEY;
-
-    if (get_keyblob(&keyblob, revision, keyblobs, available_revision) != 0) {
-        return -1;
-    }
-
-    se_aes_ecb_decrypt_block(0xD, work_buffer, 0x10, keyblob_seeds[revision], 0x10);
-    decrypt_data_into_keyslot(keyslot, 0xE, work_buffer, 0x10);
-    decrypt_data_into_keyslot(0xB, keyslot, keyblob_mac_seed, 0x10);
-
-    /* Validate keyblob. */
-    se_compute_aes_128_cmac(0xB, work_buffer, 0x10, keyblob.mac + sizeof(keyblob.mac), sizeof(keyblob) - sizeof(keyblob.mac));
-    if (safe_memcmp(keyblob.mac, work_buffer, 0x10)) {
-        return -1;
-    }
-
-    /* Decrypt keyblob. */
-    se_aes_ctr_crypt(keyslot, &g_dec_keyblobs[revision], sizeof(g_dec_keyblobs[revision]), keyblob.data, sizeof(keyblob.data), keyblob.ctr, sizeof(keyblob.ctr));
-    return 0;
-}
-
-int load_package1_key(uint32_t revision) {
-    if (revision > MASTERKEY_REVISION_600_610) {
-        return -1;
-    }
-
-    set_aes_keyslot(0xB, g_dec_keyblobs[revision].package1_key, 0x10);
-    return 0;
-}
-
 /* Derive all Switch keys. */
-int derive_nx_keydata_erista(uint32_t target_firmware, const nx_keyblob_t *keyblobs, uint32_t available_revision, const void *tsec_key, void *tsec_root_keys, unsigned int *out_keygen_type) {
+int derive_nx_keydata_erista(uint32_t target_firmware) {
     uint8_t AL16 work_buffer[0x10];
-    uint8_t AL16 zeroes[0x10] = {0};
 
-    /* Initialize keygen type. */
-    *out_keygen_type = 0;
+    /* Get whether we're using dev keys. */
+    const bool is_retail = fuse_get_hardware_state() != 0;
 
-    /* TODO: Set keyslot flags properly in preparation of derivation. */
-    set_aes_keyslot_flags(0xE, 0x15);
-    set_aes_keyslot_flags(0xD, 0x15);
+    /* Derive Keyblob Key 00. */
+    se_aes_ecb_decrypt_block(0xC, work_buffer, 0x10, keyblob_seed_00, 0x10);
+    decrypt_data_into_keyslot(0xF, 0xE, work_buffer, 0x10);
 
-    /* Set the TSEC key. */
-    set_aes_keyslot(0xD, tsec_key, 0x10);
+    /* Derive master kek. */
+    decrypt_data_into_keyslot(0xE, is_retail ? 0xD : 0xB, master_kek_seed_erista, 0x10);
 
-    /* Decrypt all keyblobs, setting keyslot 0xF correctly. */
-    for (unsigned int rev = 0; rev <= MASTERKEY_REVISION_600_610; rev++) {
-        int ret = decrypt_keyblob(keyblobs, rev, available_revision);
-        if (ret) {
-            return ret;
-        }
-    }
+    /* Derive master key, device master key. */
+    decrypt_data_into_keyslot(0xD, 0xE, masterkey_seed, 0x10);
+    decrypt_data_into_keyslot(0xE, 0xE, masterkey_4x_seed, 0x10);
 
-    /* Do 6.2.0+ keygen. */
-    if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_6_2_0) {
-        uint32_t desired_keyblob;
-
-        if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_8_1_0) {
-            /* NOTE: We load in the current key for all >= 8.1.0 firmwares to reduce sept binaries. */
-            desired_keyblob = MASTERKEY_REVISION_910_CURRENT;
-        } else if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
-            desired_keyblob = MASTERKEY_REVISION_700_800;
-        } else {
-            desired_keyblob = MASTERKEY_REVISION_620;
-        }
-
-        /* Try emulation result. */
-        for (unsigned int rev = MASTERKEY_REVISION_620; rev < MASTERKEY_REVISION_MAX; rev++) {
-            void *tsec_root_key = (void *)((uintptr_t)tsec_root_keys + 0x10 * (rev - MASTERKEY_REVISION_620));
-            if (memcmp(tsec_root_key, zeroes, 0x10) != 0) {
-                /* We got a valid key from emulation. */
-                set_aes_keyslot(0xD, tsec_root_key, 0x10);
-                se_aes_ecb_decrypt_block(0xD, work_buffer, 0x10, new_master_kek_seeds[rev - MASTERKEY_REVISION_620], 0x10);
-                memcpy(g_dec_keyblobs[rev].master_kek, work_buffer, 0x10);
-            }
-        }
-
-        if (memcmp(g_dec_keyblobs[desired_keyblob].master_kek, zeroes, 0x10) == 0) {
-            /* Try reading the keys from a file. */
-            const char *keyfile = fuse_get_hardware_state() != 0 ? "atmosphere/prod.keys" : "atmosphere/dev.keys";
-            FILE *extkey_file = fopen(keyfile, "r");
-            AL16 fusee_extkeys_t extkeys = {0};
-            if (extkey_file == NULL) {
-                fatal_error("Error: failed to read %s, needed for 6.2.0+ key derivation!", keyfile);
-            }
-            extkeys_initialize_keyset(&extkeys, extkey_file);
-            fclose(extkey_file);
-            for (unsigned int rev = MASTERKEY_REVISION_620; rev < MASTERKEY_REVISION_MAX; rev++) {
-                if (memcmp(extkeys.tsec_root_keys[rev - MASTERKEY_REVISION_620], zeroes, 0x10) != 0) {
-                    set_aes_keyslot(0xD, extkeys.tsec_root_keys[rev - MASTERKEY_REVISION_620], 0x10);
-                    se_aes_ecb_decrypt_block(0xD, work_buffer, 0x10, new_master_kek_seeds[rev - MASTERKEY_REVISION_620], 0x10);
-                    memcpy(g_dec_keyblobs[rev].master_kek, work_buffer, 0x10);
-                } else {
-                    memcpy(g_dec_keyblobs[rev].master_kek, extkeys.master_keks[rev], 0x10);
-                }
-            }
-        }
-
-        if (memcmp(g_dec_keyblobs[available_revision].master_kek, zeroes, 0x10) == 0) {
-            fatal_error("Error: failed to derive master_kek_%02x!", available_revision);
-        }
-    }
-
-    /* Clear the SBK. */
-    clear_aes_keyslot(0xE);
-
-    /* Get needed data. */
-    set_aes_keyslot(0xD, g_dec_keyblobs[available_revision].master_kek, 0x10);
-
-    /* Also set the Package1 key for the revision that is stored on the eMMC boot0 partition. */
-    if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_6_2_0) {
-        load_package1_key(available_revision);
-    }
-
-    /* Derive keys for Exosphere, lock critical keyslots. */
+    /* Derive device keys. */
     decrypt_data_into_keyslot(0xA, 0xF, devicekey_4x_seed, 0x10);
-    decrypt_data_into_keyslot(0xF, 0xF, devicekey_seed,    0x10);
-    decrypt_data_into_keyslot(0xC, 0xD, masterkey_4x_seed, 0x10);
-    decrypt_data_into_keyslot(0xD, 0xD, masterkey_seed,    0x10);
+    decrypt_data_into_keyslot(0xF, 0xF, devicekey_seed, 0x10);
+
+    /* Derive firmware specific device key. */
+    se_aes_ecb_decrypt_block(0xA, work_buffer, 0x10, master_devkey_seed_erista, 0x10);
+    decrypt_data_into_keyslot(0xC, 0xE, work_buffer, 0x10);
+
+    /* Clear keyslots 0xB/0xE. */
+    clear_aes_keyslot(0xB);
+    clear_aes_keyslot(0xE);
 
     /* Setup master key revision, derive older master keys for use. */
     return mkey_detect_revision(fuse_get_hardware_state() != 0);

fusee/fusee-secondary/src/key_derivation.h

@@ -27,29 +27,8 @@ typedef enum BisPartition {
     BisPartition_UserSystem = 2,
 } BisPartition;
 
-typedef struct {
-    union {
-        uint8_t keys[9][0x10];
-        struct {
-            uint8_t master_kek[0x10];
-            uint8_t _keys[7][0x10];
-            uint8_t package1_key[0x10];
-        };
-    };
-} nx_dec_keyblob_t;
-
-typedef struct nx_keyblob_t {
-    uint8_t mac[0x10];
-    uint8_t ctr[0x10];
-    union {
-        uint8_t data[0x90];
-        nx_dec_keyblob_t dec_blob;
-    };
-} nx_keyblob_t;
-
-int derive_nx_keydata_erista(uint32_t target_firmware, const nx_keyblob_t *keyblobs, uint32_t available_revision, const void *tsec_key, void *tsec_root_key, unsigned int *out_keygen_type);
+int derive_nx_keydata_erista(uint32_t target_firmware);
 int derive_nx_keydata_mariko(uint32_t target_firmware);
-int load_package1_key(uint32_t revision);
 void derive_bis_key(void *dst, BisPartition partition_id, uint32_t target_firmware);
 
 #endif

fusee/fusee-secondary/src/main.c

@@ -34,6 +34,9 @@
 #include "../../../fusee/common/display/video_fb.h"
 #include "../../../fusee/common/sdmmc/sdmmc.h"
 #include "../../../fusee/common/log.h"
+#include "fuse.h"
+#include "mtc/mtc.h"
+#include "mtc/mtc_b01.h"
 
 extern void (*__program_exit_callback)(int rc);
 
@@ -107,6 +110,9 @@ int main(int argc, void **argv) {
     /* Initialize the boot environment. */
     setup_env();
 
+    /* Train dram. */
+    train_dram();
+
     print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, u8"Welcome to Atmosphère Fusée Stage 2!\n");
     print(SCREEN_LOG_LEVEL_DEBUG, "Stage 2 executing from: %s\n", (const char *)argv[STAGE2_ARGV_PROGRAM_PATH]);
 
@@ -134,6 +140,11 @@ int main(int argc, void **argv) {
         /* Terminate the boot environment. */
         cleanup_env();
 
+        /* Restore dram if mariko. */
+        if (fuse_get_soc_type() == 1) {
+            restore_dram_mariko();
+        }
+
         /* Finish boot. */
         nxboot_finish(boot_memaddr);
     } else {

fusee/fusee-secondary/src/masterkey.c

@@ -44,6 +44,7 @@ static const uint8_t mkey_vectors_dev[MASTERKEY_REVISION_MAX][0x10] = {
     {0xEC, 0xE1, 0x46, 0x89, 0x37, 0xFD, 0xD2, 0x15, 0x8C, 0x3F, 0x24, 0x82, 0xEF, 0x49, 0x68, 0x04}, /* Master key 07 encrypted with Master key 08. */
     {0x43, 0x3D, 0xC5, 0x3B, 0xEF, 0x91, 0x02, 0x21, 0x61, 0x54, 0x63, 0x8A, 0x35, 0xE7, 0xCA, 0xEE}, /* Master key 08 encrypted with Master key 09. */
     {0x6C, 0x2E, 0xCD, 0xB3, 0x34, 0x61, 0x77, 0xF5, 0xF9, 0xB1, 0xDD, 0x61, 0x98, 0x19, 0x3E, 0xD4}, /* Master key 09 encrypted with Master key 0A. */
+    {0x21, 0x88, 0x6B, 0x10, 0x9E, 0x83, 0xD6, 0x52, 0xAB, 0x08, 0xDB, 0x6D, 0x39, 0xFF, 0x1C, 0x9C}, /* Master key 0A encrypted with Master key 0B. */
 };
 
 /* Retail unit keys. */
@@ -59,17 +60,19 @@ static const uint8_t mkey_vectors[MASTERKEY_REVISION_MAX][0x10] = {
     {0xEA, 0x60, 0xB3, 0xEA, 0xCE, 0x8F, 0x24, 0x46, 0x7D, 0x33, 0x9C, 0xD1, 0xBC, 0x24, 0x98, 0x29}, /* Master key 07 encrypted with Master key 08. */
     {0x4D, 0xD9, 0x98, 0x42, 0x45, 0x0D, 0xB1, 0x3C, 0x52, 0x0C, 0x9A, 0x44, 0xBB, 0xAD, 0xAF, 0x80}, /* Master key 08 encrypted with Master key 09. */
     {0xB8, 0x96, 0x9E, 0x4A, 0x00, 0x0D, 0xD6, 0x28, 0xB3, 0xD1, 0xDB, 0x68, 0x5F, 0xFB, 0xE1, 0x2A}, /* Master key 09 encrypted with Master key 0A. */
+    {0xC1, 0x8D, 0x16, 0xBB, 0x2A, 0xE4, 0x1D, 0xD4, 0xC2, 0xC1, 0xB6, 0x40, 0x94, 0x35, 0x63, 0x98}, /* Master key 0A encrypted with Master key 0B. */
 };
 
 static const uint8_t new_device_key_sources[MASTERKEY_NUM_NEW_DEVICE_KEYS][0x10] = {
-    {0x8B, 0x4E, 0x1C, 0x22, 0x42, 0x07, 0xC8, 0x73, 0x56, 0x94, 0x08, 0x8B, 0xCC, 0x47, 0x0F, 0x5D}, /* 4.x   New Device Key Source. */
-    {0x6C, 0xEF, 0xC6, 0x27, 0x8B, 0xEC, 0x8A, 0x91, 0x99, 0xAB, 0x24, 0xAC, 0x4F, 0x1C, 0x8F, 0x1C}, /* 5.x   New Device Key Source. */
-    {0x70, 0x08, 0x1B, 0x97, 0x44, 0x64, 0xF8, 0x91, 0x54, 0x9D, 0xC6, 0x84, 0x8F, 0x1A, 0xB2, 0xE4}, /* 6.x   New Device Key Source. */
-    {0x8E, 0x09, 0x1F, 0x7A, 0xBB, 0xCA, 0x6A, 0xFB, 0xB8, 0x9B, 0xD5, 0xC1, 0x25, 0x9C, 0xA9, 0x17}, /* 6.2.0 New Device Key Source. */
-    {0x8F, 0x77, 0x5A, 0x96, 0xB0, 0x94, 0xFD, 0x8D, 0x28, 0xE4, 0x19, 0xC8, 0x16, 0x1C, 0xDB, 0x3D}, /* 7.0.0 New Device Key Source. */
-    {0x67, 0x62, 0xD4, 0x8E, 0x55, 0xCF, 0xFF, 0x41, 0x31, 0x15, 0x3B, 0x24, 0x0C, 0x7C, 0x07, 0xAE}, /* 8.1.0 New Device Key Source. */
-    {0x4A, 0xC3, 0x4E, 0x14, 0x8B, 0x96, 0x4A, 0xD5, 0xD4, 0x99, 0x73, 0xC4, 0x45, 0xAB, 0x8B, 0x49}, /* 9.0.0 New Device Key Source. */
-    {0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94}, /* 9.1.0 New Device Key Source. */
+    {0x8B, 0x4E, 0x1C, 0x22, 0x42, 0x07, 0xC8, 0x73, 0x56, 0x94, 0x08, 0x8B, 0xCC, 0x47, 0x0F, 0x5D}, /* 4.x    New Device Key Source. */
+    {0x6C, 0xEF, 0xC6, 0x27, 0x8B, 0xEC, 0x8A, 0x91, 0x99, 0xAB, 0x24, 0xAC, 0x4F, 0x1C, 0x8F, 0x1C}, /* 5.x    New Device Key Source. */
+    {0x70, 0x08, 0x1B, 0x97, 0x44, 0x64, 0xF8, 0x91, 0x54, 0x9D, 0xC6, 0x84, 0x8F, 0x1A, 0xB2, 0xE4}, /* 6.x    New Device Key Source. */
+    {0x8E, 0x09, 0x1F, 0x7A, 0xBB, 0xCA, 0x6A, 0xFB, 0xB8, 0x9B, 0xD5, 0xC1, 0x25, 0x9C, 0xA9, 0x17}, /* 6.2.0  New Device Key Source. */
+    {0x8F, 0x77, 0x5A, 0x96, 0xB0, 0x94, 0xFD, 0x8D, 0x28, 0xE4, 0x19, 0xC8, 0x16, 0x1C, 0xDB, 0x3D}, /* 7.0.0  New Device Key Source. */
+    {0x67, 0x62, 0xD4, 0x8E, 0x55, 0xCF, 0xFF, 0x41, 0x31, 0x15, 0x3B, 0x24, 0x0C, 0x7C, 0x07, 0xAE}, /* 8.1.0  New Device Key Source. */
+    {0x4A, 0xC3, 0x4E, 0x14, 0x8B, 0x96, 0x4A, 0xD5, 0xD4, 0x99, 0x73, 0xC4, 0x45, 0xAB, 0x8B, 0x49}, /* 9.0.0  New Device Key Source. */
+    {0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94}, /* 9.1.0  New Device Key Source. */
+    {0xAA, 0xFD, 0xBC, 0xBB, 0x25, 0xC3, 0xA4, 0xEF, 0xE3, 0xEE, 0x58, 0x53, 0xB7, 0xF8, 0xDD, 0xD6}, /* 12.1.0 New Device Key Source. */
 };
 
 static const uint8_t new_device_keygen_sources[MASTERKEY_NUM_NEW_DEVICE_KEYS][0x10] = {
@@ -80,7 +83,8 @@ static const uint8_t new_device_keygen_sources[MASTERKEY_NUM_NEW_DEVICE_KEYS][0x
     {0x86, 0x61, 0xB0, 0x16, 0xFA, 0x7A, 0x9A, 0xEA, 0xF6, 0xF5, 0xBE, 0x1A, 0x13, 0x5B, 0x6D, 0x9E}, /* 7.0.0 New Device Keygen Source. */
     {0xA6, 0x81, 0x71, 0xE7, 0xB5, 0x23, 0x74, 0xB0, 0x39, 0x8C, 0xB7, 0xFF, 0xA0, 0x62, 0x9F, 0x8D}, /* 8.1.0 New Device Keygen Source. */
     {0x03, 0xE7, 0xEB, 0x43, 0x1B, 0xCF, 0x5F, 0xB5, 0xED, 0xDC, 0x97, 0xAE, 0x21, 0x8D, 0x19, 0xED}, /* 9.0.0 New Device Keygen Source. */
-    {0xCE, 0xFE, 0x41, 0x0F, 0x46, 0x9A, 0x30, 0xD6, 0xF2, 0xE9, 0x0C, 0x6B, 0xB7, 0x15, 0x91, 0x36}, /* 9.1.0 New Device Keygen Source to be added on next change-of-keys. */
+    {0xCE, 0xFE, 0x41, 0x0F, 0x46, 0x9A, 0x30, 0xD6, 0xF2, 0xE9, 0x0C, 0x6B, 0xB7, 0x15, 0x91, 0x36}, /* 9.1.0 New Device Keygen Source. */
+    {0xC2, 0x65, 0x34, 0x6E, 0xC7, 0xC6, 0x5D, 0x97, 0x3E, 0x34, 0x5C, 0x6B, 0xB3, 0x7E, 0xC6, 0xE3}, /* 12.1.0 New Device Keygen Source. */
 };
 
 static const uint8_t new_device_keygen_sources_dev[MASTERKEY_NUM_NEW_DEVICE_KEYS][0x10] = {
@@ -91,7 +95,8 @@ static const uint8_t new_device_keygen_sources_dev[MASTERKEY_NUM_NEW_DEVICE_KEYS
     {0x60, 0xAE, 0x56, 0x68, 0x11, 0xE2, 0x0C, 0x99, 0xDE, 0x05, 0xAE, 0x68, 0x78, 0x85, 0x04, 0xAE}, /* 7.0.0 New Device Keygen Source. */
     {0x94, 0xD6, 0xA8, 0xC0, 0x95, 0xAF, 0xD0, 0xA6, 0x27, 0x53, 0x5E, 0xE5, 0x8E, 0x70, 0x1F, 0x87}, /* 8.1.0 New Device Keygen Source. */
     {0x61, 0x6A, 0x88, 0x21, 0xA3, 0x52, 0xB0, 0x19, 0x16, 0x25, 0xA4, 0xE3, 0x4C, 0x54, 0x02, 0x0F}, /* 9.0.0 New Device Keygen Source. */
-    {0x9D, 0xB1, 0xAE, 0xCB, 0xF6, 0xF6, 0xE3, 0xFE, 0xAB, 0x6F, 0xCB, 0xAF, 0x38, 0x03, 0xFC, 0x7B}, /* 9.1.0 New Device Keygen Source to be added on next change-of-keys. */
+    {0x9D, 0xB1, 0xAE, 0xCB, 0xF6, 0xF6, 0xE3, 0xFE, 0xAB, 0x6F, 0xCB, 0xAF, 0x38, 0x03, 0xFC, 0x7B}, /* 9.1.0 New Device Keygen Source. */
+    {0xC4, 0xBB, 0xF3, 0x9F, 0xA3, 0xAA, 0x00, 0x99, 0x7C, 0x97, 0xAD, 0x91, 0x8F, 0xE8, 0x45, 0xCB}, /* 12.1.0 New Device Keygen Source. */
 };
 
 /* Determine the current SoC for Mariko specific code. */
@@ -180,8 +185,8 @@ void derive_new_device_keys(bool is_retail, unsigned int keygen_keyslot, unsigne
         if (relative_revision > mkey_get_revision()) {
             break;
         } else if (relative_revision == mkey_get_revision()) {
-            /* On 7.0.0 erista, sept will have derived this key for us already. */
-            if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0 || is_mariko) {
+            /* On Erista, this will already be derived. */
+            if (is_mariko) {
                 decrypt_data_into_keyslot(is_mariko ? KEYSLOT_SWITCH_DEVICEKEY_MARIKO : KEYSLOT_SWITCH_DEVICEKEY, KEYSLOT_SWITCH_TEMPKEY, work_buffer, 0x10);
             }
         } else {

fusee/fusee-secondary/src/masterkey.h

@@ -19,8 +19,8 @@
 
 /* This is glue code to enable master key support across versions. */
 
-/* TODO: Update to 0xC on release of new master key. */
-#define MASTERKEY_REVISION_MAX 0xB
+/* TODO: Update to 0xD on release of new master key. */
+#define MASTERKEY_REVISION_MAX 0xC
 
 #define MASTERKEY_REVISION_100_230     0x00
 #define MASTERKEY_REVISION_300         0x01
@@ -32,7 +32,8 @@
 #define MASTERKEY_REVISION_700_800     0x07
 #define MASTERKEY_REVISION_810         0x08
 #define MASTERKEY_REVISION_900         0x09
-#define MASTERKEY_REVISION_910_CURRENT 0x0A
+#define MASTERKEY_REVISION_910_1203    0x0A
+#define MASTERKEY_REVISION_C10_CURRENT 0x0B
 
 #define MASTERKEY_NUM_NEW_DEVICE_KEYS (MASTERKEY_REVISION_MAX - MASTERKEY_REVISION_400_410)
 

fusee/fusee-secondary/src/mtc/mtc_b01.h

@@ -0,0 +1,691 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018 CTCaer  <ctcaer@gmail.com>
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef FUSEE_MTC_B01_H_
+#define FUSEE_MTC_B01_H_
+
+#include "mtc.h"
+
+typedef struct {
+  uint32_t ptfv_dqsosc_movavg_c0d0u0;
+  uint32_t ptfv_dqsosc_movavg_c0d0u1;
+  uint32_t ptfv_dqsosc_movavg_c0d1u0;
+  uint32_t ptfv_dqsosc_movavg_c0d1u1;
+  uint32_t ptfv_dqsosc_movavg_c1d0u0;
+  uint32_t ptfv_dqsosc_movavg_c1d0u1;
+  uint32_t ptfv_dqsosc_movavg_c1d1u0;
+  uint32_t ptfv_dqsosc_movavg_c1d1u1;
+  uint32_t ptfv_write_samples;
+  uint32_t ptfv_dvfs_samples;
+  uint32_t ptfv_movavg_weight;
+  uint32_t ptfv_config_ctrl;
+} t210_emc_ptfv_list_table;
+
+typedef struct {
+    uint32_t emc_rc;
+    uint32_t emc_rfc;
+    uint32_t emc_rfcpb;
+    uint32_t emc_refctrl2;
+    uint32_t emc_rfc_slr;
+    uint32_t emc_ras;
+    uint32_t emc_rp;
+    uint32_t emc_r2w;
+    uint32_t emc_w2r;
+    uint32_t emc_r2p;
+    uint32_t emc_w2p;
+    uint32_t emc_r2r;
+    uint32_t emc_tppd;
+    uint32_t emc_trtm;
+    uint32_t emc_twtm;
+    uint32_t emc_tratm;
+    uint32_t emc_twatm;
+    uint32_t emc_tr2ref;
+    uint32_t emc_ccdmw;
+    uint32_t emc_rd_rcd;
+    uint32_t emc_wr_rcd;
+    uint32_t emc_rrd;
+    uint32_t emc_rext;
+    uint32_t emc_wext;
+    uint32_t emc_wdv_chk;
+    uint32_t emc_wdv;
+    uint32_t emc_wsv;
+    uint32_t emc_wev;
+    uint32_t emc_wdv_mask;
+    uint32_t emc_ws_duration;
+    uint32_t emc_we_duration;
+    uint32_t emc_quse;
+    uint32_t emc_quse_width;
+    uint32_t emc_ibdly;
+    uint32_t emc_obdly;
+    uint32_t emc_einput;
+    uint32_t emc_mrw6;
+    uint32_t emc_einput_duration;
+    uint32_t emc_puterm_extra;
+    uint32_t emc_puterm_width;
+    uint32_t emc_qrst;
+    uint32_t emc_qsafe;
+    uint32_t emc_rdv;
+    uint32_t emc_rdv_mask;
+    uint32_t emc_rdv_early;
+    uint32_t emc_rdv_early_mask;
+    uint32_t emc_refresh;
+    uint32_t emc_burst_refresh_num;
+    uint32_t emc_pre_refresh_req_cnt;
+    uint32_t emc_pdex2wr;
+    uint32_t emc_pdex2rd;
+    uint32_t emc_pchg2pden;
+    uint32_t emc_act2pden;
+    uint32_t emc_ar2pden;
+    uint32_t emc_rw2pden;
+    uint32_t emc_cke2pden;
+    uint32_t emc_pdex2cke;
+    uint32_t emc_pdex2mrr;
+    uint32_t emc_txsr;
+    uint32_t emc_txsrdll;
+    uint32_t emc_tcke;
+    uint32_t emc_tckesr;
+    uint32_t emc_tpd;
+    uint32_t emc_tfaw;
+    uint32_t emc_trpab;
+    uint32_t emc_tclkstable;
+    uint32_t emc_tclkstop;
+    uint32_t emc_mrw7;
+    uint32_t emc_trefbw;
+    uint32_t emc_odt_write;
+    uint32_t emc_fbio_cfg5;
+    uint32_t emc_fbio_cfg7;
+    uint32_t emc_cfg_dig_dll;
+    uint32_t emc_cfg_dig_dll_period;
+    uint32_t emc_pmacro_ib_rxrt;
+    uint32_t emc_cfg_pipe_1;
+    uint32_t emc_cfg_pipe_2;
+    uint32_t emc_pmacro_quse_ddll_rank0_4;
+    uint32_t emc_pmacro_quse_ddll_rank0_5;
+    uint32_t emc_pmacro_quse_ddll_rank1_4;
+    uint32_t emc_pmacro_quse_ddll_rank1_5;
+    uint32_t emc_mrw8;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
+    uint32_t emc_pmacro_ddll_long_cmd_0;
+    uint32_t emc_pmacro_ddll_long_cmd_1;
+    uint32_t emc_pmacro_ddll_long_cmd_2;
+    uint32_t emc_pmacro_ddll_long_cmd_3;
+    uint32_t emc_pmacro_ddll_long_cmd_4;
+    uint32_t emc_pmacro_ddll_short_cmd_0;
+    uint32_t emc_pmacro_ddll_short_cmd_1;
+    uint32_t emc_pmacro_ddll_short_cmd_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
+    uint32_t emc_txdsrvttgen;
+    uint32_t emc_fdpd_ctrl_dq;
+    uint32_t emc_fdpd_ctrl_cmd;
+    uint32_t emc_fbio_spare;
+    uint32_t emc_zcal_interval;
+    uint32_t emc_zcal_wait_cnt;
+    uint32_t emc_mrs_wait_cnt;
+    uint32_t emc_mrs_wait_cnt2;
+    uint32_t emc_auto_cal_channel;
+    uint32_t emc_pmacro_dll_cfg_0;
+    uint32_t emc_pmacro_dll_cfg_1;
+    uint32_t emc_pmacro_dll_cfg_2;
+    uint32_t emc_pmacro_autocal_cfg_common;
+    uint32_t emc_pmacro_zctrl;
+    uint32_t emc_cfg;
+    uint32_t emc_cfg_pipe;
+    uint32_t emc_dyn_self_ref_control;
+    uint32_t emc_qpop;
+    uint32_t emc_dqs_brlshft_0;
+    uint32_t emc_dqs_brlshft_1;
+    uint32_t emc_cmd_brlshft_2;
+    uint32_t emc_cmd_brlshft_3;
+    uint32_t emc_pmacro_pad_cfg_ctrl;
+    uint32_t emc_pmacro_data_pad_rx_ctrl;
+    uint32_t emc_pmacro_cmd_pad_rx_ctrl;
+    uint32_t emc_pmacro_data_rx_term_mode;
+    uint32_t emc_pmacro_cmd_rx_term_mode;
+    uint32_t emc_pmacro_cmd_pad_tx_ctrl;
+    uint32_t emc_pmacro_data_pad_tx_ctrl;
+    uint32_t emc_pmacro_vttgen_ctrl_0;
+    uint32_t emc_pmacro_vttgen_ctrl_1;
+    uint32_t emc_pmacro_vttgen_ctrl_2;
+    uint32_t emc_pmacro_brick_ctrl_rfu1;
+    uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
+    uint32_t emc_pmacro_brick_ctrl_rfu2;
+    uint32_t emc_pmacro_data_brick_ctrl_fdpd;
+    uint32_t emc_pmacro_bg_bias_ctrl_0;
+    uint32_t emc_cfg_3;
+    uint32_t emc_pmacro_tx_pwrd_0;
+    uint32_t emc_pmacro_tx_pwrd_1;
+    uint32_t emc_pmacro_tx_pwrd_2;
+    uint32_t emc_pmacro_tx_pwrd_3;
+    uint32_t emc_pmacro_tx_pwrd_4;
+    uint32_t emc_pmacro_tx_pwrd_5;
+    uint32_t emc_config_sample_delay;
+    uint32_t emc_pmacro_tx_sel_clk_src_0;
+    uint32_t emc_pmacro_tx_sel_clk_src_1;
+    uint32_t emc_pmacro_tx_sel_clk_src_2;
+    uint32_t emc_pmacro_tx_sel_clk_src_3;
+    uint32_t emc_pmacro_tx_sel_clk_src_4;
+    uint32_t emc_pmacro_tx_sel_clk_src_5;
+    uint32_t emc_pmacro_ddll_bypass;
+    uint32_t emc_pmacro_ddll_pwrd_0;
+    uint32_t emc_pmacro_ddll_pwrd_1;
+    uint32_t emc_pmacro_ddll_pwrd_2;
+    uint32_t emc_pmacro_cmd_ctrl_0;
+    uint32_t emc_pmacro_cmd_ctrl_1;
+    uint32_t emc_pmacro_cmd_ctrl_2;
+    uint32_t emc_pmacro_data_pi_ctrl;
+    uint32_t emc_pmacro_cmd_pi_ctrl;
+    uint32_t emc_tr_timing_0;
+    uint32_t emc_tr_dvfs;
+    uint32_t emc_tr_ctrl_1;
+    uint32_t emc_tr_rdv;
+    uint32_t emc_tr_qpop;
+    uint32_t emc_tr_rdv_mask;
+    uint32_t emc_mrw14;
+    uint32_t emc_tr_qsafe;
+    uint32_t emc_tr_qrst;
+    uint32_t emc_training_ctrl;
+    uint32_t emc_training_settle;
+    uint32_t emc_training_vref_settle;
+    uint32_t emc_training_ca_fine_ctrl;
+    uint32_t emc_training_ca_ctrl_misc;
+    uint32_t emc_training_ca_ctrl_misc1;
+    uint32_t emc_training_ca_vref_ctrl;
+    uint32_t emc_training_quse_cors_ctrl;
+    uint32_t emc_training_quse_fine_ctrl;
+    uint32_t emc_training_quse_ctrl_misc;
+    uint32_t emc_training_quse_vref_ctrl;
+    uint32_t emc_training_read_fine_ctrl;
+    uint32_t emc_training_read_ctrl_misc;
+    uint32_t emc_training_read_vref_ctrl;
+    uint32_t emc_training_write_fine_ctrl;
+    uint32_t emc_training_write_ctrl_misc;
+    uint32_t emc_training_write_vref_ctrl;
+    uint32_t emc_training_mpc;
+    uint32_t emc_mrw15;
+} t210b01_emc_burst_regs;
+
+typedef struct {
+    uint32_t emc0_mrw10;
+    uint32_t emc1_mrw10;
+    uint32_t emc0_mrw11;
+    uint32_t emc1_mrw11;
+    uint32_t emc0_mrw12;
+    uint32_t emc1_mrw12;
+    uint32_t emc0_mrw13;
+    uint32_t emc1_mrw13;
+} t210_emc_burst_reg_per_ch;
+
+typedef struct {
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
+    uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
+    uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
+    uint32_t emc_pmacro_ib_vref_dqs_0;
+    uint32_t emc_pmacro_ib_vref_dqs_1;
+    uint32_t emc_pmacro_ib_vref_dq_0;
+    uint32_t emc_pmacro_ib_vref_dq_1;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
+    uint32_t emc_pmacro_quse_ddll_rank0_0;
+    uint32_t emc_pmacro_quse_ddll_rank0_1;
+    uint32_t emc_pmacro_quse_ddll_rank0_2;
+    uint32_t emc_pmacro_quse_ddll_rank0_3;
+    uint32_t emc_pmacro_quse_ddll_rank1_0;
+    uint32_t emc_pmacro_quse_ddll_rank1_1;
+    uint32_t emc_pmacro_quse_ddll_rank1_2;
+    uint32_t emc_pmacro_quse_ddll_rank1_3;
+} t210_emc_trim_regs;
+
+typedef struct {
+    uint32_t emc_cmd_brlshft_0;
+    uint32_t emc_cmd_brlshft_1;
+    uint32_t emc0_data_brlshft_0;
+    uint32_t emc1_data_brlshft_0;
+    uint32_t emc0_data_brlshft_1;
+    uint32_t emc1_data_brlshft_1;
+    uint32_t emc_quse_brlshft_0;
+    uint32_t emc_quse_brlshft_1;
+    uint32_t emc_quse_brlshft_2;
+    uint32_t emc_quse_brlshft_3;
+} t210_emc_trim_perch_regs;
+
+typedef struct {
+    uint32_t emc0_training_opt_dqs_ib_vref_rank0;
+    uint32_t emc1_training_opt_dqs_ib_vref_rank0;
+    uint32_t emc0_training_opt_dqs_ib_vref_rank1;
+    uint32_t emc1_training_opt_dqs_ib_vref_rank1;
+} t210_emc_vref_perch_regs;
+
+typedef struct {
+    uint32_t t_rp;
+    uint32_t t_fc_lpddr4;
+    uint32_t t_rfc;
+    uint32_t t_pdex;
+    uint32_t rl;
+} t210_emc_dram_timings;
+
+typedef struct {
+    uint32_t emc0_training_rw_offset_ib_byte0;
+    uint32_t emc1_training_rw_offset_ib_byte0;
+    uint32_t emc0_training_rw_offset_ib_byte1;
+    uint32_t emc1_training_rw_offset_ib_byte1;
+    uint32_t emc0_training_rw_offset_ib_byte2;
+    uint32_t emc1_training_rw_offset_ib_byte2;
+    uint32_t emc0_training_rw_offset_ib_byte3;
+    uint32_t emc1_training_rw_offset_ib_byte3;
+    uint32_t emc0_training_rw_offset_ib_misc;
+    uint32_t emc1_training_rw_offset_ib_misc;
+    uint32_t emc0_training_rw_offset_ob_byte0;
+    uint32_t emc1_training_rw_offset_ob_byte0;
+    uint32_t emc0_training_rw_offset_ob_byte1;
+    uint32_t emc1_training_rw_offset_ob_byte1;
+    uint32_t emc0_training_rw_offset_ob_byte2;
+    uint32_t emc1_training_rw_offset_ob_byte2;
+    uint32_t emc0_training_rw_offset_ob_byte3;
+    uint32_t emc1_training_rw_offset_ob_byte3;
+    uint32_t emc0_training_rw_offset_ob_misc;
+    uint32_t emc1_training_rw_offset_ob_misc;
+} t210_emc_training_mod_regs;
+
+typedef struct {
+    uint32_t mc_emem_arb_cfg;
+    uint32_t mc_emem_arb_outstanding_req;
+    uint32_t mc_emem_arb_refpb_hp_ctrl;
+    uint32_t mc_emem_arb_refpb_bank_ctrl;
+    uint32_t mc_emem_arb_timing_rcd;
+    uint32_t mc_emem_arb_timing_rp;
+    uint32_t mc_emem_arb_timing_rc;
+    uint32_t mc_emem_arb_timing_ras;
+    uint32_t mc_emem_arb_timing_faw;
+    uint32_t mc_emem_arb_timing_rrd;
+    uint32_t mc_emem_arb_timing_rap2pre;
+    uint32_t mc_emem_arb_timing_wap2pre;
+    uint32_t mc_emem_arb_timing_r2r;
+    uint32_t mc_emem_arb_timing_w2w;
+    uint32_t mc_emem_arb_timing_r2w;
+    uint32_t mc_emem_arb_timing_ccdmw;
+    uint32_t mc_emem_arb_timing_w2r;
+    uint32_t mc_emem_arb_timing_rfcpb;
+    uint32_t mc_emem_arb_da_turns;
+    uint32_t mc_emem_arb_da_covers;
+    uint32_t mc_emem_arb_misc0;
+    uint32_t mc_emem_arb_misc1;
+    uint32_t mc_emem_arb_misc2;
+    uint32_t mc_emem_arb_ring1_throttle;
+    uint32_t mc_emem_arb_dhyst_ctrl;
+    uint32_t mc_emem_arb_dhyst_timeout_util_0;
+    uint32_t mc_emem_arb_dhyst_timeout_util_1;
+    uint32_t mc_emem_arb_dhyst_timeout_util_2;
+    uint32_t mc_emem_arb_dhyst_timeout_util_3;
+    uint32_t mc_emem_arb_dhyst_timeout_util_4;
+    uint32_t mc_emem_arb_dhyst_timeout_util_5;
+    uint32_t mc_emem_arb_dhyst_timeout_util_6;
+    uint32_t mc_emem_arb_dhyst_timeout_util_7;
+} t210_emc_burst_mc_regs;
+
+typedef struct {
+    uint32_t mc_mll_mpcorer_ptsa_rate;
+    uint32_t mc_ftop_ptsa_rate;
+    uint32_t mc_ptsa_grant_decrement;
+    uint32_t mc_latency_allowance_xusb_0;
+    uint32_t mc_latency_allowance_xusb_1;
+    uint32_t mc_latency_allowance_tsec_0;
+    uint32_t mc_latency_allowance_sdmmca_0;
+    uint32_t mc_latency_allowance_sdmmcaa_0;
+    uint32_t mc_latency_allowance_sdmmc_0;
+    uint32_t mc_latency_allowance_sdmmcab_0;
+    uint32_t mc_latency_allowance_ppcs_0;
+    uint32_t mc_latency_allowance_ppcs_1;
+    uint32_t mc_latency_allowance_mpcore_0;
+    uint32_t mc_latency_allowance_hc_0;
+    uint32_t mc_latency_allowance_hc_1;
+    uint32_t mc_latency_allowance_avpc_0;
+    uint32_t mc_latency_allowance_gpu_0;
+    uint32_t mc_latency_allowance_gpu2_0;
+    uint32_t mc_latency_allowance_nvenc_0;
+    uint32_t mc_latency_allowance_nvdec_0;
+    uint32_t mc_latency_allowance_vic_0;
+    uint32_t mc_latency_allowance_vi2_0;
+    uint32_t mc_latency_allowance_isp2_0;
+    uint32_t mc_latency_allowance_isp2_1;
+} t210_emc_la_scale_regs;
+
+typedef struct {
+    uint32_t rev;
+    char dvfs_ver[60];
+    uint32_t rate_khz;
+    uint32_t min_volt;
+    uint32_t gpu_min_volt;
+    char clock_src[32];
+    uint32_t clk_src_emc;
+    uint32_t pll_en_ssc;
+    uint32_t needs_training;
+    uint32_t training_pattern;
+    uint32_t trained;
+    uint32_t periodic_training;
+    uint32_t trained_dram_clktree_c0d0u0;
+    uint32_t trained_dram_clktree_c0d0u1;
+    uint32_t trained_dram_clktree_c0d1u0;
+    uint32_t trained_dram_clktree_c0d1u1;
+    uint32_t trained_dram_clktree_c1d0u0;
+    uint32_t trained_dram_clktree_c1d0u1;
+    uint32_t trained_dram_clktree_c1d1u0;
+    uint32_t trained_dram_clktree_c1d1u1;
+    uint32_t current_dram_clktree_c0d0u0;
+    uint32_t current_dram_clktree_c0d0u1;
+    uint32_t current_dram_clktree_c0d1u0;
+    uint32_t current_dram_clktree_c0d1u1;
+    uint32_t current_dram_clktree_c1d0u0;
+    uint32_t current_dram_clktree_c1d0u1;
+    uint32_t current_dram_clktree_c1d1u0;
+    uint32_t current_dram_clktree_c1d1u1;
+    uint32_t emc_fbio_cfg7;
+    uint32_t run_clocks;
+    uint32_t tree_margin;
+    uint32_t num_burst;
+    uint32_t num_burst_per_ch;
+    uint32_t num_trim;
+    uint32_t num_trim_per_ch;
+    uint32_t num_mc_regs;
+    uint32_t num_up_down;
+    uint32_t vref_num;
+    uint32_t training_mod_num;
+    uint32_t dram_timing_num;
+    t210_emc_ptfv_list_table ptfv_list;
+    union {
+        t210b01_emc_burst_regs burst_regs;
+        uint32_t burst_regs_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
+    };
+    union {
+        t210_emc_burst_reg_per_ch burst_reg_per_ch;
+        uint32_t burst_reg_per_ch_arr[sizeof(t210_emc_burst_reg_per_ch) / sizeof(uint32_t)];
+    };
+    union {
+        t210b01_emc_burst_regs shadow_regs_ca_train;
+        uint32_t shadow_regs_ca_train_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
+    };
+    union {
+        t210b01_emc_burst_regs shadow_regs_rdwr_train;
+        uint32_t shadow_regs_rdwr_train_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
+    };
+    union {
+        t210_emc_trim_regs trim_regs;
+        uint32_t trim_regs_arr[sizeof(t210_emc_trim_regs) / sizeof(uint32_t)];
+    };
+    union {
+        t210_emc_trim_perch_regs trim_perch_regs;
+        uint32_t trim_perch_regs_arr[sizeof(t210_emc_trim_perch_regs) / sizeof(uint32_t)];
+    };
+    union {
+        t210_emc_vref_perch_regs vref_perch_regs;
+        uint32_t vref_perch_regs_arr[sizeof(t210_emc_vref_perch_regs) / sizeof(uint32_t)];
+    };
+    t210_emc_dram_timings dram_timings;
+    uint32_t zq_op_cc_long_zcal;
+    uint32_t zq_op_cc_short_zcal;
+    uint32_t zcal_wait_time_ps_cc_long_zcal;
+    uint32_t zcal_wait_time_ps_cc_short_zcal;
+    uint32_t tZQCAL_lpddr4;
+    uint32_t zqcal_before_cc_cutoff;
+    uint32_t opt_cc_short_zcal;
+    uint32_t opt_short_zcal;
+    uint32_t opt_do_sw_qrst;
+    uint32_t save_restore_clkstop_pd;
+    uint32_t opt_E90;
+    uint32_t cya_allow_ref_cc;
+    uint32_t ref_b4_sref_en;
+    uint32_t cya_issue_pc_ref;
+    union {
+        t210_emc_training_mod_regs training_mod_regs;
+        uint32_t training_mod_regs_arr[sizeof(t210_emc_training_mod_regs) / sizeof(uint32_t)];
+    };
+    uint32_t save_restore_mod_regs[12];
+    union {
+        t210_emc_burst_mc_regs burst_mc_regs;
+        uint32_t burst_mc_regs_arr[sizeof(t210_emc_burst_mc_regs) / sizeof(uint32_t)];
+    };
+    union {
+        t210_emc_la_scale_regs la_scale_regs;
+        uint32_t la_scale_regs_arr[sizeof(t210_emc_la_scale_regs) / sizeof(uint32_t)];
+    };
+    uint32_t unk_0;
+    uint32_t vtt_vdda_ctrl_0;
+    uint32_t src_clock_div;
+    uint32_t vtt_vdda_dual_channel;
+    uint32_t vtt_vdda_ctrl_1;
+    uint32_t vtt_vdda_ctrl_2;
+    uint32_t vtt_vdda_ctrl_3;
+    uint32_t vtt_vdda_ctrl_4;
+    uint32_t misc_cfg_0;
+    uint32_t misc_cfg_1;
+    uint32_t misc_cfg_2;
+    uint32_t unk_1;
+    uint32_t unk_2;
+    uint32_t pipe_clk_delay;
+    uint32_t clkchange_delay;
+    uint32_t pllm_ss_cfg;
+    uint32_t pllm_ss_ctrl1;
+    uint32_t pllm_ss_ctrl2;
+    uint32_t pllmb_ss_cfg;
+    uint32_t pllmb_ss_ctrl1;
+    uint32_t pllmb_ss_ctrl2;
+    uint32_t pllmb_divm;
+    uint32_t pllmb_divn;
+    uint32_t pllmb_divp;
+    uint32_t min_mrs_wait;
+    uint32_t ramp_wait;
+    uint32_t emc_mrw;
+    uint32_t emc_mrw2;
+    uint32_t emc_mrw3;
+    uint32_t emc_mrw4;
+    uint32_t emc_mrw9;
+    uint32_t emc_mrs;
+    uint32_t emc_emrs;
+    uint32_t emc_emrs2;
+    uint32_t emc_auto_cal_config;
+    uint32_t emc_auto_cal_config2;
+    uint32_t emc_auto_cal_config3;
+    uint32_t emc_auto_cal_config4;
+    uint32_t emc_auto_cal_config5;
+    uint32_t emc_auto_cal_config6;
+    uint32_t emc_auto_cal_config7;
+    uint32_t emc_auto_cal_config8;
+    uint32_t emc_cfg_2;
+    uint32_t emc_sel_dpd_ctrl;
+    uint32_t emc_fdpd_ctrl_cmd_no_ramp;
+    uint32_t emc_tr_ctrl_0;
+    uint32_t dll_clk_src;
+    uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
+    uint32_t latency;
+    uint32_t pllm_misc1_0_pllm_clamp_ph90;
+} tegra_b01_emc_timing_t;
+_Static_assert(sizeof(tegra_b01_emc_timing_t) == 0x10CC);
+
+void train_dram_mariko(void);
+
+void restore_dram_mariko(void);
+
+#endif

fusee/fusee-secondary/src/nxboot.c

@@ -44,7 +44,6 @@
 #include "masterkey.h"
 #include "package1.h"
 #include "package2.h"
-#include "smmu.h"
 #include "tsec.h"
 #include "lp0.h"
 #include "loader.h"
@@ -59,11 +58,8 @@
 #include "exosphere_bin.h"
 #include "mariko_fatal_bin.h"
 #include "mesosphere_bin.h"
-#include "sept_secondary_00_enc.h"
-#include "sept_secondary_01_enc.h"
-#include "sept_secondary_dev_00_enc.h"
-#include "sept_secondary_dev_01_enc.h"
 #include "warmboot_bin.h"
+#include "tsec_keygen_bin.h"
 #include "emummc_kip.h"
 #undef u8
 #undef u32
@@ -285,7 +281,13 @@ static bool is_nca_present(const char *nca_name) {
 static uint32_t nxboot_get_specific_target_firmware(uint32_t target_firmware){
     #define CHECK_NCA(NCA_ID, VERSION) do { if (is_nca_present(NCA_ID)) { return ATMOSPHERE_TARGET_FIRMWARE_##VERSION; } } while(0)
 
-    if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_12_0_0) {
+    if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_12_1_0) {
+        CHECK_NCA("9d9d83d68d9517f245f3e8cd7f93c416", 12_1_0);
+    } else if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_12_0_2) {
+        CHECK_NCA("a1863a5c0e1cedd442f5e60b0422dc15", 12_0_3);
+        CHECK_NCA("63d928b5a3016fe8cc0e76d2f06f4e98", 12_0_2);
+    } else if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_12_0_0) {
+        CHECK_NCA("e65114b456f9d0b566a80e53bade2d89", 12_0_1);
         CHECK_NCA("bd4185843550fbba125b20787005d1d2", 12_0_0);
     } else if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_11_0_0) {
         CHECK_NCA("56211c7a5ed20a5332f5cdda67121e37", 11_0_1);
@@ -392,6 +394,10 @@ static uint32_t nxboot_get_target_firmware(const void *package1loader) {
                 return ATMOSPHERE_TARGET_FIRMWARE_11_0_0;
             } else if (memcmp(package1loader_header->build_timestamp, "20210129", 8) == 0) {
                 return ATMOSPHERE_TARGET_FIRMWARE_12_0_0;
+            } else if (memcmp(package1loader_header->build_timestamp, "20210422", 8) == 0) {
+                return ATMOSPHERE_TARGET_FIRMWARE_12_0_2;
+            } else if (memcmp(package1loader_header->build_timestamp, "20210607", 8) == 0) {
+                return ATMOSPHERE_TARGET_FIRMWARE_12_1_0;
             } else {
                 fatal_error("[NXBOOT] Unable to identify package1!\n");
             }
@@ -603,6 +609,11 @@ static void nxboot_configure_stratosphere(uint32_t target_firmware) {
         /* NOTE: 12.0.0 added a new lotus firmware, but did not burn a fuse. */
         /* This is literally undetectable using normal fuses.... */
         /* C'est la vie. */
+
+        /* Check if the fuses are < 12.0.0, but firmware is >= 12.0.0 */
+        if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_12_0_2 && !(fuse_get_reserved_odm(7) & ~0x00003FFF)) {
+            kip_patches_set_enable_nogc();
+        }
     }
 }
 
@@ -709,18 +720,11 @@ static void nxboot_move_bootconfig() {
     free(bootconfig);
 }
 
-static bool get_and_clear_has_run_sept(void) {
-    bool has_run_sept = (MAKE_EMC_REG(EMC_SCRATCH0) & 0x80000000) != 0;
-    MAKE_EMC_REG(EMC_SCRATCH0) &= ~0x80000000;
-    return has_run_sept;
-}
-
 static void get_mariko_warmboot_path(char *dst, size_t dst_size, uint32_t version) {
     snprintf(dst, dst_size, "warmboot_mariko/wb_%02" PRIx32 ".bin", version);
 }
 
 /* This is the main function responsible for booting Horizon. */
-static nx_keyblob_t __attribute__((aligned(16))) g_keyblobs[32];
 uint32_t nxboot_main(void) {
     volatile tegra_pmc_t *pmc = pmc_get_regs();
     loader_ctx_t *loader_ctx = get_loader_ctx();
@@ -730,8 +734,6 @@ uint32_t nxboot_main(void) {
     size_t package2_size;
     void *tsec_fw;
     size_t tsec_fw_size;
-    const void *sept_secondary_enc = NULL;
-    size_t sept_secondary_enc_size = 0;
     void *warmboot_fw;
     size_t warmboot_fw_size;
     void *warmboot_memaddr;
@@ -741,7 +743,6 @@ uint32_t nxboot_main(void) {
     size_t mesosphere_size;
     void *emummc;
     size_t emummc_size;
-    uint32_t available_revision;
     FILE *boot0, *pk2file;
     void *exosphere_memaddr;
     exo_emummc_config_t exo_emummc_cfg;
@@ -829,7 +830,7 @@ uint32_t nxboot_main(void) {
             fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
         }
     } else {
-        if (package1_read_and_parse_boot0_erista(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) {
+        if (package1_read_and_parse_boot0_erista(&package1loader, &package1loader_size, boot0) == -1) {
             fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno));
         }
     }
@@ -845,103 +846,26 @@ uint32_t nxboot_main(void) {
     }
 
     /* Handle TSEC and Sept (Erista only). */
-    uint8_t tsec_key[0x10] = {0};
-    uint8_t tsec_root_keys[0x20][0x10] = {0};
     if (!is_mariko) {
-        /* Read the TSEC firmware from a file, otherwise from PK1L. */
-        if (loader_ctx->tsecfw_path[0] != '\0') {
-            tsec_fw_size = get_file_size(loader_ctx->tsecfw_path);
-            if ((tsec_fw_size != 0) && (tsec_fw_size != 0xF00 && tsec_fw_size != 0x2900 && tsec_fw_size != 0x3000 && tsec_fw_size != 0x3300)) {
-                fatal_error("[NXBOOT] TSEC firmware from %s has a wrong size!\n", loader_ctx->tsecfw_path);
-            } else if (tsec_fw_size == 0) {
-                fatal_error("[NXBOOT] Could not read the TSEC firmware from %s!\n", loader_ctx->tsecfw_path);
-            }
+        /* Use Atmosphere's tsec_keygen implementation. */
+        tsec_fw_size = tsec_keygen_bin_size;
+        tsec_fw = memalign(0x100, tsec_fw_size);
 
-            /* Allocate memory for the TSEC firmware. */
-            tsec_fw = memalign(0x100, tsec_fw_size);
-
-            if (tsec_fw == NULL) {
-                fatal_error("[NXBOOT] Out of memory!\n");
-            }
-            if (read_from_file(tsec_fw, tsec_fw_size, loader_ctx->tsecfw_path) != tsec_fw_size) {
-                fatal_error("[NXBOOT] Could not read the TSEC firmware from %s!\n", loader_ctx->tsecfw_path);
-            }
-
-            if (tsec_fw_size == 0x3000) {
-                if (fuse_get_hardware_state() != 0) {
-                    sept_secondary_enc = sept_secondary_00_enc;
-                    sept_secondary_enc_size = sept_secondary_00_enc_size;
-                } else {
-                    sept_secondary_enc = sept_secondary_dev_00_enc;
-                    sept_secondary_enc_size = sept_secondary_dev_00_enc_size;
-                }
-            } else if (tsec_fw_size == 0x3300) {
-                if (fuse_get_hardware_state() != 0) {
-                    sept_secondary_enc = sept_secondary_01_enc;
-                    sept_secondary_enc_size = sept_secondary_01_enc_size;
-                } else {
-                    sept_secondary_enc = sept_secondary_dev_01_enc;
-                    sept_secondary_enc_size = sept_secondary_dev_01_enc_size;
-                }
-            } else {
-                fatal_error("[NXBOOT] Unable to identify sept revision to run.");
-            }
-        } else {
-            if (!package1_get_tsec_fw(&tsec_fw, package1loader, package1loader_size)) {
-                fatal_error("[NXBOOT] Failed to read the TSEC firmware from Package1loader!\n");
-            }
-            if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_8_1_0) {
-                if (fuse_get_hardware_state() != 0) {
-                    sept_secondary_enc = sept_secondary_01_enc;
-                    sept_secondary_enc_size = sept_secondary_01_enc_size;
-                } else {
-                    sept_secondary_enc = sept_secondary_dev_01_enc;
-                    sept_secondary_enc_size = sept_secondary_dev_01_enc_size;
-                }
-                tsec_fw_size = 0x3300;
-            } else if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
-                if (fuse_get_hardware_state() != 0) {
-                    sept_secondary_enc = sept_secondary_00_enc;
-                    sept_secondary_enc_size = sept_secondary_00_enc_size;
-                } else {
-                    sept_secondary_enc = sept_secondary_dev_00_enc;
-                    sept_secondary_enc_size = sept_secondary_dev_00_enc_size;
-                }
-                tsec_fw_size = 0x3000;
-            } else if (target_firmware == ATMOSPHERE_TARGET_FIRMWARE_6_2_0) {
-                tsec_fw_size = 0x2900;
-            } else {
-                tsec_fw_size = 0xF00;
-            }
+        if (tsec_fw == NULL) {
+            fatal_error("[NXBOOT] Out of memory!\n");
         }
 
-        print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Loaded firmware from eMMC...\n");
+        memcpy(tsec_fw, tsec_keygen_bin, tsec_fw_size);
 
-        /* Get the TSEC keys. */
-        if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
-            /* Detect whether we need to run sept-secondary in order to derive keys. */
-            if (!get_and_clear_has_run_sept()) {
-                reboot_to_sept(tsec_fw, tsec_fw_size, sept_secondary_enc, sept_secondary_enc_size);
-            } else {
-                if (mkey_detect_revision(fuse_get_hardware_state() != 0) != 0) {
-                    fatal_error("[NXBOOT] Sept derived incorrect keys!\n");
-                }
-            }
-            get_and_clear_has_run_sept();
-        } else if (target_firmware == ATMOSPHERE_TARGET_FIRMWARE_6_2_0) {
-            uint8_t tsec_keys[0x20] = {0};
+        if (tsec_fw_size == 0) {
+            fatal_error("[NXBOOT] Could not read the warmboot firmware from Package1!\n");
+        }
 
-            /* Emulate the TSEC payload on 6.2.0+. */
-            smmu_emulate_tsec((void *)tsec_keys, package1loader, package1loader_size, package1loader);
-
-            /* Copy back the keys. */
-            memcpy((void *)tsec_key, (void *)tsec_keys, 0x10);
-            memcpy((void *)tsec_root_keys, (void *)tsec_keys + 0x10, 0x10);
-        } else {
-            /* Run the TSEC payload and get the key. */
-            if (tsec_get_key(tsec_key, 1, tsec_fw, tsec_fw_size) != 0) {
-                fatal_error("[NXBOOT] Failed to get TSEC key!\n");
-            }
+        /* Get the TSEC keys into the security engine. */
+        int tsec_res = tsec_run_fw(tsec_fw, tsec_fw_size);
+        if (tsec_res != 0) {
+            volatile tegra_tsec_t *tsec = tsec_get_regs();
+            fatal_error("[NXBOOT] Failed to run TSEC firmware %d %08x %08x!\n", tsec_res, tsec->TSEC_FALCON_MAILBOX0, tsec->TSEC_FALCON_MAILBOX1);
         }
     }
 
@@ -954,8 +878,8 @@ uint32_t nxboot_main(void) {
         if (derive_nx_keydata_mariko(target_firmware) != 0) {
             fatal_error("[NXBOOT] Mariko key derivation failed!\n");
         }
-    } else if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {   /* If on 7.0.0+, sept has already derived keys for us (Erista only). */
-        if (derive_nx_keydata_erista(target_firmware, g_keyblobs, available_revision, tsec_key, tsec_root_keys, &keygen_type) != 0) {
+    } else {
+        if (derive_nx_keydata_erista(target_firmware) != 0) {
             fatal_error("[NXBOOT] Erista key derivation failed!\n");
         }
     }
@@ -1215,9 +1139,6 @@ uint32_t nxboot_main(void) {
 
     /* Clean up. */
     free(package1loader);
-    if (loader_ctx->tsecfw_path[0] != '\0') {
-        free(tsec_fw);
-    }
     if (loader_ctx->warmboot_path[0] != '\0') {
         free(warmboot_fw);
     }

fusee/fusee-secondary/src/nxboot_iram.c

@@ -24,18 +24,10 @@
 #include "mc.h"
 #include "nxboot.h"
 #include "se.h"
-#include "smmu.h"
 #include "timers.h"
 #include "sysreg.h"
 
-/* Determine the current SoC for Mariko specific code. */
-static bool is_soc_mariko() {
-    return (fuse_get_soc_type() == 1);
-}
-
 void nxboot_finish(uint32_t boot_memaddr) {
-    bool is_mariko = is_soc_mariko();
-
     /* Boot up Exosphère. */
     MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE = 0;
     MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_DRAM_INITIALIZED_4X;
@@ -43,26 +35,8 @@ void nxboot_finish(uint32_t boot_memaddr) {
     /* Terminate the display. */
     display_end();
 
-    if (is_mariko) {
-        /* Boot CPU0. */
-        cluster_boot_cpu0(boot_memaddr);
-    } else {
-        /* Check if SMMU emulation has been used. */
-        uint32_t smmu_magic = *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xFC);
-        if (smmu_magic == 0xDEADC0DE) {
-            /* Clear the magic. */
-            *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xFC) = 0;
-
-            /* Pass the boot address to the already running payload. */
-            *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xF0) = boot_memaddr;
-
-            /* Wait a while. */
-            mdelay(500);
-        } else {
-            /* Boot CPU0. */
-            cluster_boot_cpu0(boot_memaddr);
-        }
-    }
+    /* Boot CPU0. */
+    cluster_boot_cpu0(boot_memaddr);
 
     /* Wait for Exosphère to wake up. */
     while (MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE == 0) {

fusee/fusee-secondary/src/package1.c

@@ -58,16 +58,12 @@ bool package1_is_custom_public_key(const void *bct, bool mariko) {
     }
 }
 
-int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, nx_keyblob_t *keyblobs, uint32_t *revision, FILE *boot0) {
+int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, FILE *boot0) {
     nvboot_config_table *bct; /* Normal firmware BCT, primary. TODO: check? */
     nv_bootloader_info *pk1l_info; /* TODO: check? */
     size_t fpos, pk1l_offset;
-    union {
-        nx_keyblob_t keyblob;
-        uint8_t sector[0x200];
-    } d;
 
-    if (package1loader == NULL || package1loader_size == NULL || keyblobs == NULL || revision == NULL || boot0 == NULL) {
+    if (package1loader == NULL || package1loader_size == NULL || boot0 == NULL) {
         errno = EINVAL;
         return -1;
     }
@@ -105,7 +101,6 @@ int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1
         return -1;
     }
 
-    *revision = pk1l_info->version - 1;
     *package1loader_size = pk1l_info->length;
 
     pk1l_offset = 0x4000 * pk1l_info->start_blk + 0x200 * pk1l_info->start_page;
@@ -128,14 +123,6 @@ int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1
         return -1;
     }
 
-    /* Read the full keyblob area.*/
-    for (size_t i = 0; i < 32; i++) {
-        if (!fread(d.sector, 0x200, 1, boot0)) {
-            return -1;
-        }
-        keyblobs[i] = d.keyblob;
-    }
-
     return 0;
 }
 
@@ -211,24 +198,6 @@ bool package1_get_tsec_fw(void **tsec_fw, const void *package1loader, size_t pac
     return false;
 }
 
-size_t package1_get_encrypted_package1(package1_header_t **package1, uint8_t *ctr, const void *package1loader, size_t package1loader_size) {
-    const uint8_t *crypt_hdr = (const uint8_t *)package1loader + 0x4000 - 0x20;
-    if (package1loader_size < 0x4000) {
-        return 0; /* Shouldn't happen, ever. */
-    }
-
-    memcpy(ctr, crypt_hdr + 0x10, 0x10);
-    (*package1) = (package1_header_t *)(crypt_hdr + 0x20);
-    return *(uint32_t *)crypt_hdr;
-}
-
-bool package1_decrypt(package1_header_t *package1, size_t package1_size, const uint8_t *ctr) {
-    uint8_t __attribute__((aligned(16))) ctrbuf[16];
-    memcpy(ctrbuf, ctr, 16);
-    se_aes_ctr_crypt(0xB, package1, package1_size, package1, package1_size, ctrbuf, 16);
-    return memcmp(package1->magic, "PK11", 4) == 0;
-}
-
 void *package1_get_warmboot_fw(const package1_header_t *package1) {
     /*
         The layout of pk1 changes between versions.

fusee/fusee-secondary/src/package1.h

@@ -59,14 +59,10 @@ typedef struct {
 
 bool package1_is_custom_public_key(const void *bct, bool mariko);
 
-int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, nx_keyblob_t *keyblobs, uint32_t *revision, FILE *boot0);
+int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, FILE *boot0);
 int package1_read_and_parse_boot0_mariko(void **package1loader, size_t *package1loader_size, FILE *boot0);
 
-bool package1_get_tsec_fw(void **tsec_fw, const void *package1loader, size_t package1loader_size);
-size_t package1_get_encrypted_package1(package1_header_t **package1, uint8_t *ctr, const void *package1loader, size_t package1loader_size);
-
 /* Must be aligned to 16 bytes. */
-bool package1_decrypt(package1_header_t *package1, size_t package1_size, const uint8_t *ctr);
 void *package1_get_warmboot_fw(const package1_header_t *package1);
 
 #endif

fusee/fusee-secondary/src/package2.c

@@ -250,7 +250,7 @@ static bool package2_validate_metadata(package2_meta_t *metadata, uint8_t data[]
 
     /* Perform version checks. */
     /* We will be compatible with all package2s released before current, but not newer ones. */
-    if (metadata->version_max >= PACKAGE2_MINVER_THEORETICAL && metadata->version_min < PACKAGE2_MAXVER_1100_CURRENT) {
+    if (metadata->version_max >= PACKAGE2_MINVER_THEORETICAL && metadata->version_min < PACKAGE2_MAXVER_1202_CURRENT) {
         return true;
     }
 

fusee/fusee-secondary/src/package2.h

@@ -41,7 +41,8 @@
 #define PACKAGE2_MAXVER_900 0xC
 #define PACKAGE2_MAXVER_910_920 0xD
 #define PACKAGE2_MAXVER_1000 0xE
-#define PACKAGE2_MAXVER_1100_CURRENT 0xF
+#define PACKAGE2_MAXVER_1100 0xF
+#define PACKAGE2_MAXVER_1202_CURRENT 0x10
 
 #define PACKAGE2_MINVER_100 0x3
 #define PACKAGE2_MINVER_200 0x4
@@ -56,7 +57,8 @@
 #define PACKAGE2_MINVER_900 0xD
 #define PACKAGE2_MINVER_910_920 0xE
 #define PACKAGE2_MINVER_1000 0xF
-#define PACKAGE2_MINVER_1100_CURRENT 0x10
+#define PACKAGE2_MINVER_1100 0x10
+#define PACKAGE2_MINVER_1202_CURRENT 0x11
 
 #define NX_BOOTLOADER_PACKAGE2_LOAD_ADDRESS ((void *)(0xA9800000ull))
 

fusee/fusee-secondary/src/smmu.c

@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "smmu.h"
-#include "cluster.h"
-#include "mc.h"
-#include "timers.h"
-#include "tsec.h"
-
-#define TSEC_KEYGEN_MAX_RETRIES 25
-
-void *smmu_heap = (void *)SMMU_HEAP_BASE_ADDR;
-
-static void safe_memcpy(void *dst, void *src, uint32_t sz) {
-    /* Aligned memcpy to read MMIO correctly. */
-    for (size_t i = 0; i < (sz/4); i++) {
-        ((volatile uint32_t *)dst)[i] = ((volatile uint32_t *)src)[i];
-    }
-}
-
-static void smmu_flush_ppsb() {
-    /* Read-back barrier for interactions between the PPSB and the APB/AHB. */
-    (void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG);
-}
-
-static void smmu_flush_regs() {
-    /* Flush all TLB and PTC entries. */
-    MAKE_MC_REG(MC_SMMU_PTC_FLUSH) = 0;
-    smmu_flush_ppsb();
-    MAKE_MC_REG(MC_SMMU_TLB_FLUSH) = 0;
-    smmu_flush_ppsb();
-}
-
-static void *smmu_alloc_page(uint32_t page_count) {
-    void *cur_page = smmu_heap;
-    smmu_heap += (page_count * SMMU_PAGE_SIZE);
-    memset(cur_page, 0, (page_count * SMMU_PAGE_SIZE));
-    return cur_page;
-}
-
-static uint32_t *smmu_alloc_pdir() {
-    uint32_t *pdir = (uint32_t *)smmu_alloc_page(1);
-    for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) {
-        pdir[pdn] = _PDE_VACANT(pdn);
-    }
-    return pdir;
-}
-
-static uint32_t *smmu_locate_pte(uint32_t *pdir_page, uint32_t iova) {
-    uint32_t ptn = SMMU_ADDR_TO_PFN(iova);
-    uint32_t pdn = SMMU_ADDR_TO_PDN(iova);
-    uint32_t *pdir = pdir_page;
-    uint32_t *ptbl;
-
-    if (pdir[pdn] != _PDE_VACANT(pdn)) {
-        /* Mapped entry table already exists. */
-        ptbl = (uint32_t *)SMMU_EX_PTBL_PAGE(pdir[pdn]);
-    } else {
-        /* Allocate page table. */
-        ptbl = (uint32_t *)smmu_alloc_page(1);
-        uint32_t addr = SMMU_PDN_TO_ADDR(pdn);
-        for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE) {
-            ptbl[pn] = _PTE_VACANT(addr);
-        }
-        pdir[pdn] = SMMU_MK_PDE((uint32_t)ptbl, _PDE_ATTR | _PDE_NEXT);
-        smmu_flush_regs();
-    }
-
-    return &ptbl[ptn % SMMU_PTBL_COUNT];
-}
-
-static void smmu_map(uint32_t *pdir, uint32_t addr, uint32_t ptpage, int pcount, uint32_t pte_attr) {
-    for (int i = 0; i < pcount; i++) {
-        uint32_t *pte = smmu_locate_pte(pdir, addr);
-        *pte = SMMU_PFN_TO_PTE(SMMU_ADDR_TO_PFN(ptpage), pte_attr);
-        addr += SMMU_PAGE_SIZE;
-        ptpage += SMMU_PAGE_SIZE;
-    }
-    smmu_flush_regs();
-}
-
-static uint32_t *smmu_setup_tsec_as(uint32_t asid) {
-    /* Allocate the page directory. */
-    uint32_t *pdir_page = smmu_alloc_pdir();
-
-    /* Set the PTB ASID and point it to the PDIR. */
-    MAKE_MC_REG(MC_SMMU_PTB_ASID) = asid;
-    MAKE_MC_REG(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((uint32_t)pdir_page, _PDIR_ATTR);
-    smmu_flush_ppsb();
-    
-    /* Assign the ASID to TSEC. */
-    MAKE_MC_REG(MC_SMMU_TSEC_ASID) = SMMU_ASID_ENABLE((asid << 24) | (asid << 16) | (asid << 8) | asid);
-    smmu_flush_ppsb();
-
-    return pdir_page;
-}
-
-static void smmu_clear_tsec_as(uint32_t asid) {
-    /* Set the PTB ASID and clear it's data. */
-    MAKE_MC_REG(MC_SMMU_PTB_ASID) = asid;
-    MAKE_MC_REG(MC_SMMU_PTB_DATA) = 0;
-    
-    /* Clear the ASID from TSEC. */
-    MAKE_MC_REG(MC_SMMU_TSEC_ASID) = SMMU_ASID_DISABLE;
-    smmu_flush_ppsb();
-}
-
-static void smmu_enable() {
-    /* AARCH64 payload for enabling the SMMU. */
-    /* Write 1 to MC_SMMU_CONFIG, read back and write the result to 0x40003F80. */
-    /* This will leave the CPU waiting until 0x40003FF0 is set to Exosphère's address. */
-    static const uint32_t aarch64_payload[20] = {
-        0x52800020, 0x58000162, 0x58000183, 0xB9000040,
-        0xB9400041, 0xB9000061, 0x58000142, 0xF9400040,
-        0xF100001F, 0x54FFFFA0, 0xD61F0000, 0x00000000,
-        0x70019010, 0x00000000, 0x40003F80, 0x00000000,
-        0x40003FF0, 0x00000000, 0x00000000, 0x00000000
-    };
-    
-    /* Reset Translation Enable Registers. */
-    MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_0) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_1) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_2) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_3) = 0xFFFFFFFF;
-    MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_4) = 0xFFFFFFFF;
-    
-    /* Setup initial TLB and PTC configuration. */
-    MAKE_MC_REG(MC_SMMU_PTB_ASID) = 0;
-    MAKE_MC_REG(MC_SMMU_PTB_DATA) = 0;
-    MAKE_MC_REG(MC_SMMU_TLB_CONFIG) = 0x30000030;
-    MAKE_MC_REG(MC_SMMU_PTC_CONFIG) = 0x2800003F;
-    smmu_flush_regs();
-    
-    /* Power on the CCPLEX to enable the SMMU globally (requires a secure write). */
-    volatile uint32_t *aarch64_payload_res = (volatile uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0x80);
-    memset((void *)SMMU_AARCH64_PAYLOAD_ADDR, 0, 0x100);
-    memcpy((void *)SMMU_AARCH64_PAYLOAD_ADDR, aarch64_payload, 20 * 4);
-    cluster_boot_cpu0(SMMU_AARCH64_PAYLOAD_ADDR);
-    mdelay(500);
-    if (*aarch64_payload_res != 1) {
-        fatal_error("[SMMU]: Failed to enable SMMU!\n");
-    }
-    
-    /* Write magic for nxboot. */
-    *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xFC) = 0xDEADC0DE;
-    
-    /* Flush TLB and PTC entries. */
-    smmu_flush_regs();
-}
-
-void smmu_emulate_tsec(void *tsec_keys, const void *package1, size_t package1_size, void *package1_dec) {
-    volatile tegra_tsec_t *tsec = tsec_get_regs();
-    
-    /* Backup IRAM to DRAM. */
-    memcpy((void *)SMMU_IRAM_BACKUP_ADDR, (void *)0x40010000, 0x30000);
-    
-    /* Copy package1 into IRAM. */
-    memcpy((void *)0x40010000, package1, package1_size);
-    
-    /* Setup TSEC's address space. */
-    uint32_t *pdir = smmu_setup_tsec_as(1);
-
-    /* Allocate pages for MMIO and IRAM. */
-    volatile uint32_t *car_page = smmu_alloc_page(1);
-    volatile uint32_t *fuse_page = smmu_alloc_page(1);
-    volatile uint32_t *pmc_page = smmu_alloc_page(1);
-    volatile uint32_t *flow_page = smmu_alloc_page(1);
-    volatile uint32_t *se_page = smmu_alloc_page(1);
-    volatile uint32_t *mc_page = smmu_alloc_page(1);
-    volatile uint32_t *iram_pages = smmu_alloc_page(48);
-    volatile uint32_t *expv_page = smmu_alloc_page(1);
-    
-    /* Map all necessary pages. */
-    smmu_map(pdir, 0x60006000, (uint32_t)car_page, 1, _READABLE | _WRITABLE | _NONSECURE);
-    smmu_map(pdir, 0x7000F000, (uint32_t)fuse_page, 1, _READABLE | _NONSECURE);
-    smmu_map(pdir, 0x7000E000, (uint32_t)pmc_page, 1, _READABLE | _NONSECURE);
-    smmu_map(pdir, 0x60007000, (uint32_t)flow_page, 1, _WRITABLE | _NONSECURE);
-    smmu_map(pdir, 0x70012000, (uint32_t)se_page, 1, _READABLE | _WRITABLE | _NONSECURE);
-    smmu_map(pdir, 0x70019000, (uint32_t)mc_page, 1, _READABLE | _NONSECURE);
-    smmu_map(pdir, 0x40010000, (uint32_t)iram_pages, 48, _READABLE | _WRITABLE | _NONSECURE);
-    smmu_map(pdir, 0x6000F000, (uint32_t)expv_page, 1, _READABLE | _WRITABLE | _NONSECURE);
-
-    /* Enable the SMMU. */
-    smmu_enable();
-    
-    /* Loop retrying TSEC firmware execution, in case we lose the SE keydata race. */
-    uint32_t key_buf[0x20/4] = {0};
-    unsigned int retries = 0;
-    while (true) {
-        if (retries++ > TSEC_KEYGEN_MAX_RETRIES) {
-            fatal_error("[SMMU] TSEC key generation race was lost too many times!");
-        }
-    
-        /* Load the TSEC firmware from IRAM. */
-        if (tsec_load_fw((void *)(0x40010000 + 0xE00), 0x2900) < 0) {
-            fatal_error("[SMMU]: Failed to load TSEC firmware!\n");
-        }
-    
-        /* Disable the aperture since it has precedence over the SMMU. */
-        mc_disable_ahb_redirect();
-        
-        /* Clear all pages. */
-        memset((void *)car_page, 0, SMMU_PAGE_SIZE);
-        memset((void *)fuse_page, 0, SMMU_PAGE_SIZE);
-        memset((void *)pmc_page, 0, SMMU_PAGE_SIZE);
-        memset((void *)flow_page, 0, SMMU_PAGE_SIZE);
-        memset((void *)se_page, 0, SMMU_PAGE_SIZE);
-        memset((void *)mc_page, 0, SMMU_PAGE_SIZE);
-        memset((void *)iram_pages, 0, 48 * SMMU_PAGE_SIZE);
-        memset((void *)expv_page, 0, SMMU_PAGE_SIZE);
-        
-        /* Copy CAR, MC and FUSE. */
-        safe_memcpy((void *)car_page, (void *)0x60006000, 0x1000);
-        safe_memcpy((void *)mc_page, (void *)0x70019000, 0x1000);
-        safe_memcpy((void *)&fuse_page[0x800/4], (void *)0x7000F800, 0x400);
-        
-        /* Copy IRAM. */
-        memcpy((void *)iram_pages, (void *)0x40010000, 0x30000);
-            
-        /* TSEC wants CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0 to be equal to 2. */
-        car_page[0x1F4/4] = 2;
-        
-        /* TSEC wants the aperture fully open. */
-        mc_page[0x65C/4] = 0;
-        mc_page[0x660/4] = 0x80000000;
-        
-        /* Run the TSEC firmware. */
-        tsec_run_fw();
-    
-        /* Extract the keys from SE. */
-        volatile uint32_t *key_data = (volatile uint32_t *)((void *)se_page + 0x320);
-        uint32_t old_key_data = *key_data;
-        uint32_t buf_counter = 0;
-        while (!(tsec->TSEC_FALCON_CPUCTL & 0x10)) {
-            const uint32_t new_key_data = *key_data;
-            if (new_key_data != old_key_data) {
-                old_key_data = new_key_data;
-                key_buf[buf_counter] = new_key_data;
-                buf_counter++;
-            }
-        }
-    
-        /* Enable back the aperture. */
-        mc_enable_ahb_redirect();
-        
-        if (buf_counter == 8) {
-            break;
-        }
-    }
-    
-    /* Check if the TSEC firmware wrote over the exception vectors. */
-    volatile uint32_t *tsec_done_check = (volatile uint32_t *)((void *)expv_page + 0x200);
-    if (!(*tsec_done_check)) {
-        fatal_error("[SMMU]: Failed to emulate the TSEC firmware!\n");
-    }
-
-    /* Copy back the extracted keys. */
-    memcpy((void *)tsec_keys, (void *)key_buf, 0x20);
-    
-    /* Manually disable TSEC clocks. */
-    tsec_disable_clkrst();
-    
-    /* Clear TSEC's address space. */
-    smmu_clear_tsec_as(1);
-    
-    /* Return the decrypted package1 from emulated IRAM. */
-    memcpy(package1_dec, (void *)iram_pages, package1_size);
-    
-    /* Restore IRAM from DRAM. */
-    memcpy((void *)0x40010000, (void *)SMMU_IRAM_BACKUP_ADDR, 0x30000);
-}

fusee/fusee-secondary/src/smmu.h

@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_SMMU_H_
-#define FUSEE_SMMU_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-#define SMMU_HEAP_BASE_ADDR             0x81000000
-#define SMMU_IRAM_BACKUP_ADDR           0x82000000
-#define SMMU_AARCH64_PAYLOAD_ADDR       0x40003F00
-
-#define SMMU_PAGE_SHIFT 12
-#define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
-#define SMMU_PDIR_COUNT 1024
-#define SMMU_PDIR_SIZE  (sizeof(uint32_t) * SMMU_PDIR_COUNT)
-#define SMMU_PTBL_COUNT 1024
-#define SMMU_PTBL_SIZE  (sizeof(uint32_t) * SMMU_PTBL_COUNT)
-#define SMMU_PDIR_SHIFT 12
-#define SMMU_PDE_SHIFT  12
-#define SMMU_PTE_SHIFT  12
-#define SMMU_PFN_MASK   0x000fffff
-#define SMMU_PDE_NEXT_SHIFT     28
-#define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
-#define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
-#define SMMU_PDN_TO_ADDR(pdn)   ((pdn) << 22)
-#define _READABLE   (1 << 31)
-#define _WRITABLE   (1 << 30)
-#define _NONSECURE  (1 << 29)
-#define _PDE_NEXT   (1 << SMMU_PDE_NEXT_SHIFT)
-#define _MASK_ATTR  (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDIR_ATTR  (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDE_ATTR   (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
-#define _PDE_VACANT(pdn)    (((pdn) << 10) | _PDE_ATTR)
-#define _PTE_ATTR   (_READABLE | _WRITABLE | _NONSECURE)
-#define _PTE_VACANT(addr)   (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
-#define SMMU_MK_PDIR(page, attr)    (((page) >> SMMU_PDIR_SHIFT) | (attr))
-#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr))
-#define SMMU_EX_PTBL_PAGE(pde)  (((pde) & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT)
-#define SMMU_PFN_TO_PTE(pfn, attr)  ((pfn) | (attr))
-#define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
-#define SMMU_ASID_DISABLE   0
-#define SMMU_ASID_ASID(n)   ((n) & ~SMMU_ASID_ENABLE(0))
-
-void smmu_emulate_tsec(void *tsec_keys, const void *package1, size_t package1_size, void *package1_dec);
-
-#endif

fusee/fusee-secondary/src/start.s

@@ -108,6 +108,7 @@ _metadata:
 #define CONTENT_TYPE_KLD 9
 #define CONTENT_TYPE_KRN 10
 #define CONTENT_TYPE_EXF 11
+#define CONTENT_TYPE_TKG 12
 
 #define CONTENT_FLAG_NONE          (0 << 0)
 
@@ -213,39 +214,6 @@ _content_headers:
 .asciz "rebootstub"
 .align 5
 
-/* sept_primary content header */
-.word __sept_primary_bin_start__
-.word __sept_primary_bin_size__
-.byte CONTENT_TYPE_SP1
-.byte CONTENT_FLAG_NONE
-.byte CONTENT_FLAG_NONE
-.byte CONTENT_FLAG_NONE
-.word 0xCCCCCCCC
-.asciz "sept_primary"
-.align 5
-
-/* sept_secondary 00 content header */
-.word __sept_secondary_00_enc_start__
-.word __sept_secondary_00_enc_size__
-.byte CONTENT_TYPE_SP2
-.byte CONTENT_FLAG_NONE
-.byte CONTENT_FLAG_NONE
-.byte CONTENT_FLAG_NONE
-.word 0xCCCCCCCC
-.asciz "septsecondary00"
-.align 5
-
-/* sept_secondary 01 content header */
-.word __sept_secondary_01_enc_start__
-.word __sept_secondary_01_enc_size__
-.byte CONTENT_TYPE_SP2
-.byte CONTENT_FLAG_NONE
-.byte CONTENT_FLAG_NONE
-.byte CONTENT_FLAG_NONE
-.word 0xCCCCCCCC
-.asciz "septsecondary01"
-.align 5
-
 /* sm content header */
 .word __sm_kip_start__
 .word __sm_kip_size__
@@ -301,6 +269,17 @@ _content_headers:
 .asciz "exosphere_fatal"
 .align 5
 
+/* tsec_keygen content header */
+.word __tsec_keygen_bin_start__
+.word __tsec_keygen_bin_size__
+.byte CONTENT_TYPE_TKG
+.byte CONTENT_FLAG_NONE
+.byte CONTENT_FLAG_NONE
+.byte CONTENT_FLAG_NONE
+.word 0xCCCCCCCC
+.asciz "tsec_keygen"
+.align 5
+
 _content_headers_end:
 
 /* No need to include this in normal programs: */

fusee/fusee-secondary/src/tsec.c

@@ -14,15 +14,16 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #include "tsec.h"
 #include "di.h"
 #include "timers.h"
 #include "car.h"
+#include "mc.h"
 
 static int tsec_dma_wait_idle()
 {
-    volatile tegra_tsec_t *tsec = tsec_get_regs();    
+    volatile tegra_tsec_t *tsec = tsec_get_regs();
     uint32_t timeout = (get_time_ms() + 10000);
 
     while (!(tsec->TSEC_FALCON_DMATRFCMD & 2))
@@ -30,13 +31,13 @@ static int tsec_dma_wait_idle()
         if (get_time_ms() > timeout)
             return 0;
     }
-    
+
     return 1;
 }
 
 static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t phys_offset)
 {
-    volatile tegra_tsec_t *tsec = tsec_get_regs(); 
+    volatile tegra_tsec_t *tsec = tsec_get_regs();
     uint32_t cmd = 0;
 
     if (!is_imem)
@@ -52,16 +53,16 @@ static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t ph
 }
 
 static int tsec_kfuse_wait_ready()
-{  
+{
     uint32_t timeout = (get_time_ms() + 10000);
-    
+
     /* Wait for STATE_DONE. */
     while (!(KFUSE_STATE & 0x10000))
     {
         if (get_time_ms() > timeout)
             return 0;
     }
-    
+
     /* Check for STATE_CRCPASS. */
     if (!(KFUSE_STATE & 0x20000))
         return 0;
@@ -91,19 +92,19 @@ void tsec_disable_clkrst()
     clkrst_disable(CARDEVICE_HOST1X);
 }
 
-int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw_size)
+static int tsec_run_fw_impl(const void *tsec_fw, size_t tsec_fw_size)
 {
     volatile tegra_tsec_t *tsec = tsec_get_regs();
 
     /* Enable clocks. */
     tsec_enable_clkrst();
-    
+
     /* Make sure KFUSE is ready. */
     if (!tsec_kfuse_wait_ready())
     {
         /* Disable clocks. */
         tsec_disable_clkrst();
-    
+
         return -1;
     }
 
@@ -112,16 +113,16 @@ int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw
     tsec->TSEC_FALCON_IRQMSET = 0xFFF2;
     tsec->TSEC_FALCON_IRQDEST = 0xFFF0;
     tsec->TSEC_FALCON_ITFEN = 3;
-    
+
     /* Make sure the DMA block is idle. */
     if (!tsec_dma_wait_idle())
     {
         /* Disable clocks. */
         tsec_disable_clkrst();
-    
+
         return -2;
     }
-    
+
     /* Load firmware. */
     tsec->TSEC_FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8;
     for (uint32_t addr = 0; addr < tsec_fw_size; addr += 0x100)
@@ -130,128 +131,71 @@ int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw
         {
             /* Disable clocks. */
             tsec_disable_clkrst();
-        
+
             return -3;
         }
     }
-    
+
     /* Write magic value to HOST1X scratch register. */
     MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA;
-    
+
     /* Execute firmware. */
     tsec->TSEC_FALCON_MAILBOX1 = 0;
-    tsec->TSEC_FALCON_MAILBOX0 = rev;
+    tsec->TSEC_FALCON_MAILBOX0 = 1;
     tsec->TSEC_FALCON_BOOTVEC = 0;
     tsec->TSEC_FALCON_CPUCTL = 2;
-    
+
     /* Make sure the DMA block is idle. */
     if (!tsec_dma_wait_idle())
     {
         /* Disable clocks. */
         tsec_disable_clkrst();
-    
+
         return -4;
     }
-    
-    uint32_t timeout = (get_time_ms() + 2000);
-    while (!tsec->TSEC_FALCON_MAILBOX1)
-    {
-        if (get_time_ms() > timeout)
-        {
+
+    uint32_t timeout = (get_time_ms() + 4000);
+    while (!(tsec->TSEC_FALCON_CPUCTL & 0x10)) {
+        if (get_time_ms() > timeout) {
             /* Disable clocks. */
             tsec_disable_clkrst();
-        
+
             return -5;
         }
     }
-    
+
     if (tsec->TSEC_FALCON_MAILBOX1 != 0xB0B0B0B0)
     {
         /* Disable clocks. */
         tsec_disable_clkrst();
-    
+
         return -6;
     }
 
     /* Clear magic value from HOST1X scratch register. */
     MAKE_HOST1X_REG(0x3300) = 0;
 
-    /* Fetch result from SOR1. */
-    uint32_t tmp[0x4] = {0};
-    tmp[0] = SOR1_DP_HDCP_BKSV_LSB;
-    tmp[1] = SOR1_TMDS_HDCP_BKSV_LSB;
-    tmp[2] = SOR1_TMDS_HDCP_CN_MSB;
-    tmp[3] = SOR1_TMDS_HDCP_CN_LSB;
-    
-    /* Clear SOR1 registers. */
-    SOR1_DP_HDCP_BKSV_LSB = 0;
-    SOR1_TMDS_HDCP_BKSV_LSB = 0;
-    SOR1_TMDS_HDCP_CN_MSB = 0;
-    SOR1_TMDS_HDCP_CN_LSB = 0;
-    
-    /* Copy back the key. */
-    memcpy(key, &tmp, 0x10);
-
     return 0;
 }
 
-int tsec_load_fw(const void *tsec_fw, size_t tsec_fw_size)
-{
-    volatile tegra_tsec_t *tsec = tsec_get_regs();
+int tsec_run_fw(const void *tsec_fw, size_t tsec_fw_size) {
+    /* Ensure that the ahb redirect is enabled. */
+    mc_enable_ahb_redirect();
 
-    /* Enable clocks. */
-    tsec_enable_clkrst();
-    
-    /* Make sure KFUSE is ready. */
-    if (!tsec_kfuse_wait_ready())
-    {
-        /* Disable clocks. */
-        tsec_disable_clkrst();
-    
-        return -1;
-    }
+    /* Get bom/tom */
+    uint32_t bom = MAKE_MC_REG(MC_IRAM_BOM);
+    uint32_t tom = MAKE_MC_REG(MC_IRAM_TOM);
 
-    /* Configure Falcon. */
-    tsec->TSEC_FALCON_DMACTL = 0;
-    tsec->TSEC_FALCON_IRQMSET = 0xFFF2;
-    tsec->TSEC_FALCON_IRQDEST = 0xFFF0;
-    tsec->TSEC_FALCON_ITFEN = 3;
-    
-    /* Make sure the DMA block is idle. */
-    if (!tsec_dma_wait_idle())
-    {
-        /* Disable clocks. */
-        tsec_disable_clkrst();
-    
-        return -2;
-    }
-    
-    /* Load firmware. */
-    tsec->TSEC_FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8;
-    for (uint32_t addr = 0; addr < tsec_fw_size; addr += 0x100)
-    {
-        if (!tsec_dma_phys_to_flcn(true, addr, addr))
-        {
-            /* Disable clocks. */
-            tsec_disable_clkrst();
-        
-            return -3;
-        }
-    }
+    /* Override the ahb redirect extents. */
+    MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000;
+    MAKE_MC_REG(MC_IRAM_TOM) = 0x80000000;
 
-    return 0;
-}
+    /* Run the fw. */
+    int res = tsec_run_fw_impl(tsec_fw, tsec_fw_size);
 
-void tsec_run_fw()
-{
-    volatile tegra_tsec_t *tsec = tsec_get_regs();
-    
-    /* Write magic value to HOST1X scratch register. */
-    MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA;
-    
-    /* Execute firmware. */
-    tsec->TSEC_FALCON_MAILBOX1 = 0;
-    tsec->TSEC_FALCON_MAILBOX0 = 1;
-    tsec->TSEC_FALCON_BOOTVEC = 0;
-    tsec->TSEC_FALCON_CPUCTL = 2;
+    /* Reset the ahb redirect extents. */
+    MAKE_MC_REG(MC_IRAM_BOM) = bom;
+    MAKE_MC_REG(MC_IRAM_TOM) = tom;
+
+    return res;
 }

fusee/fusee-secondary/src/tsec.h

@@ -14,7 +14,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #ifndef FUSEE_TSEC_H_
 #define FUSEE_TSEC_H_
 
@@ -306,8 +306,7 @@ static inline volatile tegra_tsec_t *tsec_get_regs(void)
 
 void tsec_enable_clkrst();
 void tsec_disable_clkrst();
-int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw_size);
-int tsec_load_fw(const void *tsec_fw, size_t tsec_fw_size);
-void tsec_run_fw();
+
+int tsec_run_fw(const void *tsec_fw, size_t tsec_fw_size);
 
 #endif

fusee/fusee-secondary/src/utils.c

@@ -34,7 +34,6 @@
 #define u8 uint8_t
 #define u32 uint32_t
 #include "fusee_primary_bin.h"
-#include "sept_primary_bin.h"
 #include "rebootstub_bin.h"
 #undef u8
 #undef u32
@@ -131,42 +130,8 @@ __attribute__((noreturn)) void reboot_to_fusee_primary(void) {
     reboot_to_payload();
 }
 
-__attribute__((noreturn)) void reboot_to_sept(const void *tsec_fw, size_t tsec_fw_length, const void *stage2, size_t stage2_size) {
-    if (is_soc_mariko()) {
-        /* Reboot to sept isn't possible on mariko, so just do normal reboot. */
-        shutdown_system(true);
-    } else {
-        /* Copy tsec firmware. */
-        for (size_t i = 0; i < tsec_fw_length; i += sizeof(uint32_t)) {
-            write32le((void *)0x40010F00, i, read32le(tsec_fw, i));
-        }
-        MAKE_REG32(0x40010EFC) = tsec_fw_length;
-
-        /* Copy stage 2. */
-        for (size_t i = 0; i < stage2_size; i += sizeof(uint32_t)) {
-            write32le((void *)0x40016FE0, i, read32le(stage2, i));
-        }
-
-        /* Copy sept into IRAM low. */
-        for (size_t i = 0; i < sept_primary_bin_size; i += sizeof(uint32_t)) {
-            write32le((void *)0x4003F000, i, read32le(sept_primary_bin, i));
-        }
-
-        /* Patch SDRAM init to perform an SVC immediately after second write */
-        APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
-        APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
-        /* Set SVC handler to jump to reboot stub in IRAM. */
-        APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
-        APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
-
-        /* Trigger warm reboot. */
-        pmc_reboot(1 << 0);
-        while (true) { }
-    }
-}
-
 __attribute__((noreturn)) void reboot_to_iram_payload(void *payload, size_t payload_size) {
-    /* Copy sept into IRAM low. */
+    /* Copy payload into IRAM low. */
     for (size_t i = 0; i < payload_size; i += sizeof(uint32_t)) {
         write32le((void *)0x40010000, i, read32le(payload, i));
     }

fusee/fusee-secondary/src/utils.h

@@ -13,7 +13,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #ifndef FUSEE_UTILS_H
 #define FUSEE_UTILS_H
 
@@ -121,7 +121,6 @@ static inline bool check_32bit_address_range_in_program(uintptr_t addr, size_t s
 __attribute__((noreturn)) void watchdog_reboot(void);
 __attribute__((noreturn)) void pmc_reboot(uint32_t scratch0);
 __attribute__((noreturn)) void reboot_to_fusee_primary(void);
-__attribute__((noreturn)) void reboot_to_sept(const void *tsec_fw, size_t tsec_fw_length, const void *stage2, size_t stage2_size);
 __attribute__((noreturn)) void reboot_to_iram_payload(void *payload, size_t payload_size);
 __attribute__((noreturn)) void wait_for_button_and_reboot(void);
 void wait_for_button(void);

libraries/.gitrepo

@@ -6,7 +6,7 @@
 [subrepo]
 	remote = https://github.com/Atmosphere-NX/Atmosphere-libs
 	branch = master
-	commit = 86c2eec8e9e966a30c19692adb79faeda45c1940
-	parent = aa2d03d8e13bc5d3f34751b6105503a601dc958e
+	commit = 87a1de0b1d489c25a85e187a5bf059f6872465d1
+	parent = 9296a563036ef20664a2752c03a9695597d4c2b4
 	method = merge
 	cmdver = 0.4.1

libraries/config/common.mk

@@ -18,7 +18,7 @@ endif
 ATMOSPHERE_BUILD_SETTINGS ?=
 
 export ATMOSPHERE_DEFINES  := -DATMOSPHERE
-export ATMOSPHERE_SETTINGS := -fPIE -g $(ATMOSPHERE_BUILD_SETTINGS)
+export ATMOSPHERE_SETTINGS := -fPIE -g -gdwarf-4 $(ATMOSPHERE_BUILD_SETTINGS)
 export ATMOSPHERE_CFLAGS   := -Wall -ffunction-sections -fdata-sections -fno-strict-aliasing -fwrapv  \
                               -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-stack-protector \
                               -Wno-format-truncation -Wno-format-zero-length -Wno-stringop-truncation

libraries/config/templates/exosphere.mk

@@ -8,19 +8,25 @@ include  $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../common.mk
 #---------------------------------------------------------------------------------
 ifeq ($(strip $(ATMOSPHERE_ARCH_NAME)),arm64)
 DEFINES     := $(ATMOSPHERE_DEFINES) -DATMOSPHERE_IS_EXOSPHERE
-SETTINGS    := $(ATMOSPHERE_SETTINGS) -mgeneral-regs-only -ffixed-x18 -Os -Wextra -Werror -fno-non-call-exceptions
+SETTINGS    := $(ATMOSPHERE_SETTINGS) -mgeneral-regs-only -ffixed-x18 -Os -Wextra -Werror -fno-non-call-exceptions \
+               -Wno-array-bounds \
+               -Wno-stringop-overflow \
+               -Wno-stringop-overread
 CFLAGS      := $(ATMOSPHERE_CFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
 CXXFLAGS    := $(CFLAGS) $(ATMOSPHERE_CXXFLAGS) -fno-use-cxa-atexit
 ASFLAGS     := $(ATMOSPHERE_ASFLAGS) $(SETTINGS)
 else ifeq ($(strip $(ATMOSPHERE_ARCH_NAME)),arm)
 DEFINES     := $(ATMOSPHERE_DEFINES) -DATMOSPHERE_IS_EXOSPHERE
-SETTINGS    := $(ATMOSPHERE_SETTINGS) -Os -Werror -fno-non-call-exceptions
+SETTINGS    := $(ATMOSPHERE_SETTINGS) -Os -Werror -fno-non-call-exceptions \
+               -Wno-array-bounds \
+               -Wno-stringop-overflow \
+               -Wno-stringop-overread
 CFLAGS      := $(ATMOSPHERE_CFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
 CXXFLAGS    := $(CFLAGS) $(ATMOSPHERE_CXXFLAGS) -fno-use-cxa-atexit
 ASFLAGS     := $(ATMOSPHERE_ASFLAGS) $(SETTINGS)
 endif
 
-export LDFLAGS	=	-specs=$(TOPDIR)/$(notdir $(TOPDIR)).specs -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-exceptions -fno-rtti -fno-use-cxa-atexit -nostdlib -nostartfiles -g $(SETTINGS) -Wl,-Map,$(notdir $*.map) -Wl,-z,relro,-z,now
+export LDFLAGS	=	-specs=$(TOPDIR)/$(notdir $(TOPDIR)).specs -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-exceptions -fno-rtti -fno-use-cxa-atexit -nostdlib -nostartfiles -g -gdwarf-4 $(SETTINGS) -Wl,-Map,$(notdir $*.map) -Wl,-z,relro,-z,now
 
 export CXXWRAPS := -Wl,--wrap,__cxa_pure_virtual \
 			-Wl,--wrap,__cxa_throw \

libraries/config/templates/mesosphere.mk

@@ -12,7 +12,7 @@ export CFLAGS      := $(ATMOSPHERE_CFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
 export CXXFLAGS    := $(CFLAGS) $(ATMOSPHERE_CXXFLAGS) -fno-use-cxa-atexit
 export ASFLAGS     := $(ATMOSPHERE_ASFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
 
-export LDFLAGS	=	-specs=$(TOPDIR)/$(notdir $(TOPDIR)).specs -fno-asynchronous-unwind-tables -fno-unwind-tables -nostdlib -nostartfiles -g $(SETTINGS) -Wl,-Map,$(notdir $*.map) -Wl,-z,relro,-z,now
+export LDFLAGS	=	-specs=$(TOPDIR)/$(notdir $(TOPDIR)).specs -fno-asynchronous-unwind-tables -fno-unwind-tables -nostdlib -nostartfiles -g -gdwarf-4 $(SETTINGS) -Wl,-Map,$(notdir $*.map) -Wl,-z,relro,-z,now
 
 export CXXWRAPS := -Wl,--wrap,__cxa_pure_virtual \
 			-Wl,--wrap,__cxa_throw \

libraries/config/templates/stratosphere.mk

@@ -34,7 +34,8 @@ export CXXWRAPS := -Wl,--wrap,__cxa_pure_virtual \
 			-Wl,--wrap,_Unwind_Resume \
 			-Wl,--wrap,_ZSt19__throw_logic_errorPKc \
 			-Wl,--wrap,_ZSt20__throw_length_errorPKc \
-			-Wl,--wrap,_ZNSt11logic_errorC2EPKc
+			-Wl,--wrap,_ZNSt11logic_errorC2EPKc \
+			-Wl,--wrap,exit
 
 export LDFLAGS     = -specs=$(ATMOSPHERE_LIBRARIES_DIR)/libstratosphere/stratosphere.specs -specs=$(DEVKITPRO)/libnx/switch.specs $(SETTINGS) $(CXXWRAPS) -Wl,-Map,$(notdir $*.map)
 

libraries/libexosphere/arm.mk

@@ -16,7 +16,10 @@ include  $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../config/common.mk
 #---------------------------------------------------------------------------------
 
 DEFINES     := $(ATMOSPHERE_DEFINES) -DATMOSPHERE_IS_EXOSPHERE
-SETTINGS    := $(ATMOSPHERE_SETTINGS) -Os -Wextra -Werror -flto -fno-non-call-exceptions
+SETTINGS    := $(ATMOSPHERE_SETTINGS) -Os -Wextra -Werror -flto -fno-non-call-exceptions \
+               -Wno-array-bounds \
+               -Wno-stringop-overflow \
+               -Wno-stringop-overread
 CFLAGS      := $(ATMOSPHERE_CFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
 CXXFLAGS    := $(CFLAGS) $(ATMOSPHERE_CXXFLAGS) -fno-use-cxa-atexit
 ASFLAGS     := $(ATMOSPHERE_ASFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
@@ -93,6 +96,8 @@ clean-$(strip $1):
 	@rm -fr $$(foreach hdr,$$(GCH_DIRS),$$(hdr)/$$(ATMOSPHERE_BOARD_NAME)_$$(ATMOSPHERE_ARCH_NAME)_$(strip $1))
 	@for i in $$(GCH_DIRS) $$(ATMOSPHERE_BUILD_DIR) $$(ATMOSPHERE_LIBRARY_DIR); do [ -d $$$$i ] && rmdir --ignore-fail-on-non-empty $$$$i || true; done
 
+.PHONY: $(strip $1) clean-$(strip $1) $$(ATMOSPHERE_LIBRARY_DIR)/$(strip $2)
+
 endef
 
 $(eval $(call ATMOSPHERE_ADD_TARGET, release, $(TARGET).a, \
@@ -114,7 +119,7 @@ $(eval $(call ATMOSPHERE_ADD_TARGET, audit, $(TARGET)_audit.a, \
 ALL_GCH_IDENTIFIERS := $(foreach config,$(ATMOSPHERE_BUILD_CONFIGS),$(ATMOSPHERE_BOARD_NAME)_$(ATMOSPHERE_ARCH_NAME)_$(config))
 ALL_GCH_FILES       := $(foreach hdr,$(PRECOMPILED_HEADERS:.hpp=.hpp.gch),$(foreach id,$(ALL_GCH_IDENTIFIERS),$(hdr)/$(id)))
 
-.PHONY: clean all $(foreach config,$(ATMOSPHERE_BUILD_CONFIGS),$(config) clean-$(config))
+.PHONY: clean all
 
 $(ATMOSPHERE_LIBRARY_DIR) $(GCH_DIRS):
 	@[ -d $@ ] || mkdir -p $@

libraries/libexosphere/arm64.mk

@@ -16,7 +16,10 @@ include  $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../config/common.mk
 #---------------------------------------------------------------------------------
 
 DEFINES     := $(ATMOSPHERE_DEFINES) -DATMOSPHERE_IS_EXOSPHERE
-SETTINGS    := $(ATMOSPHERE_SETTINGS) -mgeneral-regs-only -ffixed-x18 -Os -Wextra -Werror -fno-non-call-exceptions
+SETTINGS    := $(ATMOSPHERE_SETTINGS) -mgeneral-regs-only -ffixed-x18 -Os -Wextra -Werror -fno-non-call-exceptions \
+               -Wno-array-bounds \
+               -Wno-stringop-overflow \
+               -Wno-stringop-overread
 CFLAGS      := $(ATMOSPHERE_CFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
 CXXFLAGS    := $(CFLAGS) $(ATMOSPHERE_CXXFLAGS) -fno-use-cxa-atexit
 ASFLAGS     := $(ATMOSPHERE_ASFLAGS) $(SETTINGS) $(DEFINES) $(INCLUDE)
@@ -93,6 +96,8 @@ clean-$(strip $1):
 	@rm -fr $$(foreach hdr,$$(GCH_DIRS),$$(hdr)/$$(ATMOSPHERE_BOARD_NAME)_$$(ATMOSPHERE_ARCH_NAME)_$(strip $1))
 	@for i in $$(GCH_DIRS) $$(ATMOSPHERE_BUILD_DIR) $$(ATMOSPHERE_LIBRARY_DIR); do [ -d $$$$i ] && rmdir --ignore-fail-on-non-empty $$$$i || true; done
 
+.PHONY: $(strip $1) clean-$(strip $1) $$(ATMOSPHERE_LIBRARY_DIR)/$(strip $2)
+
 endef
 
 $(eval $(call ATMOSPHERE_ADD_TARGET, release, $(TARGET).a, \
@@ -114,7 +119,7 @@ $(eval $(call ATMOSPHERE_ADD_TARGET, audit, $(TARGET)_audit.a, \
 ALL_GCH_IDENTIFIERS := $(foreach config,$(ATMOSPHERE_BUILD_CONFIGS),$(ATMOSPHERE_BOARD_NAME)_$(ATMOSPHERE_ARCH_NAME)_$(config))
 ALL_GCH_FILES       := $(foreach hdr,$(PRECOMPILED_HEADERS:.hpp=.hpp.gch),$(foreach id,$(ALL_GCH_IDENTIFIERS),$(hdr)/$(id)))
 
-.PHONY: clean all $(foreach config,$(ATMOSPHERE_BUILD_CONFIGS),$(config) clean-$(config))
+.PHONY: clean all
 
 $(ATMOSPHERE_LIBRARY_DIR) $(GCH_DIRS):
 	@[ -d $@ ] || mkdir -p $@

libraries/libexosphere/include/exosphere/pkg1/pkg1_key_generation.hpp

@@ -20,17 +20,18 @@ namespace ams::pkg1 {
 
     enum KeyGeneration : int {
 
-        KeyGeneration_1_0_0 = 0x00,
-        KeyGeneration_3_0_0 = 0x01,
-        KeyGeneration_3_0_1 = 0x02,
-        KeyGeneration_4_0_0 = 0x03,
-        KeyGeneration_5_0_0 = 0x04,
-        KeyGeneration_6_0_0 = 0x05,
-        KeyGeneration_6_2_0 = 0x06,
-        KeyGeneration_7_0_0 = 0x07,
-        KeyGeneration_8_1_0 = 0x08,
-        KeyGeneration_9_0_0 = 0x09,
-        KeyGeneration_9_1_0 = 0x0A,
+        KeyGeneration_1_0_0  = 0x00,
+        KeyGeneration_3_0_0  = 0x01,
+        KeyGeneration_3_0_1  = 0x02,
+        KeyGeneration_4_0_0  = 0x03,
+        KeyGeneration_5_0_0  = 0x04,
+        KeyGeneration_6_0_0  = 0x05,
+        KeyGeneration_6_2_0  = 0x06,
+        KeyGeneration_7_0_0  = 0x07,
+        KeyGeneration_8_1_0  = 0x08,
+        KeyGeneration_9_0_0  = 0x09,
+        KeyGeneration_9_1_0  = 0x0A,
+        KeyGeneration_12_1_0 = 0x0B,
 
         KeyGeneration_Count,