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Author SHA1 Message Date
CTCaer e47a819948 bdk: se: add more useful functions 
- aes cmac 128bit
- aes hashing
- option to clear updated aes iv
 2023-12-25 03:44:52 +02:00
CTCaer 39abeb9a28 nyx: improve fuses info 
Correct the Chip ID Revision and also add actual (derived) iddq values.
 2023-12-25 03:33:37 +02:00
CTCaer 80a32304cb nyx: rename 3rd gen hynix ram chips 2023-12-25 03:21:17 +02:00
CTCaer 913cdee8e8 bdk: sdram: rename 3rd gen t210b01 hynix ram 
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
 2023-12-25 03:02:11 +02:00
CTCaer eff55ff378 bdk: touch: rename samsung touch panel 
BH2109 is the board model and not the touch panel.
 2023-12-25 02:41:42 +02:00
CTCaer 09dfcfc57d bdk: display: deduplicate interrupt code 2023-12-25 02:40:38 +02:00
CTCaer 239c48c790 bdk: usb: hid: improve stick calibration 
Wait a bit before calibrating stick centers, in order to avoid bad values.
 2023-12-25 02:37:40 +02:00
CTCaer 2e1a773a08 nyx: relax joycon calibration init 
Wait a bit before actually doing stick calibration in order to avoid bad values.
 2023-12-25 02:36:27 +02:00
CTCaer d1ee0e35fd hos: pkg2: fix validation check for nogc 17.0.0 2023-10-13 07:58:56 +03:00
CTCaer 226b30b57c Bump hekate to v6.0.7 and Nyx to v1.5.6 2023-10-12 09:25:14 +03:00
CTCaer 7fab13b76d hos: correct meso version masking 
And also use the version instead to decide for relative INI1 base setting.
That's because MSS0 and MSS1 come with prepopulated INI1 base.
 2023-10-12 09:25:06 +03:00
CTCaer d3d3768c8f hos: correct max KB 2023-10-12 08:07:46 +03:00
CTCaer 7040f1ada2 l4t: allow setting dram voltage even if no OC 
Mostly for allowing undervolting.
 2023-10-12 07:44:00 +03:00
CTCaer 697bde8667 hos: 17.0.0 support 2023-10-12 07:41:12 +03:00
CTCaer 03f11370c7 hos: allow reusage of embedded INI1 region 2023-10-12 07:36:00 +03:00
CTCaer 533fb08a1c nyx: info: K4U6E3S4AB-MGCL is now validated 2023-10-12 07:28:28 +03:00
CTCaer c828539544 hos: pkg2: rename ini1 value offset 
And simplify the logic a bit.
 2023-10-12 07:26:55 +03:00
CTCaer d1be18821d hos: reduce pkg1 id to 8 chars to save space 2023-10-12 07:16:23 +03:00
CTCaer 613fdf621d hos: rename KB defines 
From KB_FIRMWARE_VERSION to HOS_KB_VERSION
 2023-10-12 07:11:22 +03:00
CTCaer 5b13e81141 Adjust about-screens copyright year 2023-10-12 07:01:28 +03:00
CTCaer ce137852b7 bdk: change some defines and comments 2023-10-12 06:59:15 +03:00
CTCaer e84367e302 nyx: swap and fix config save text 2023-08-23 00:10:10 +03:00
CTCaer e5a22230b1 Bump hekate to v6.0.6 and Nyx to v1.5.5 2023-08-22 16:56:59 +03:00
CTCaer ce42e27f45 bdk: minerva: do not handle oc freq 
Arachne already handles it.
 2023-08-22 16:44:41 +03:00
CTCaer 01a8f30925 nyx: add contact me for unknown ram chips 2023-08-22 16:44:03 +03:00
CTCaer d73a3fdd7c bdk: sdram: name 1a micron ram chips 
Again, as with 3rd gen samsung and hynix, that's an educated guess.
 2023-08-22 14:44:27 +03:00
CTCaer fdf0dcc636 bdk: joycon: add info about sio imu report 2023-08-22 14:36:23 +03:00
CTCaer 976a02f8bc nyx: clock: fix year off-by-one 2023-08-07 21:12:18 +03:00
CTCaer 187b6d843e nyx: emummc: allow migrating emummc backup 
Now if an eMMC backup is not found, emuMMC backup will be used.
 2023-08-07 21:11:17 +03:00
CTCaer 6de29094fe nyx: gfx: add column control 
gfx_getpos/setpos can now get/set column offset.
setpos column can be fully custom. Otherwise GFX_COL_KEEP or GFX_COL_AUTO (2 columns) can be used.

Additionally, always restore column when printing debug info in log screen.
 2023-08-07 21:09:37 +03:00
CTCaer f2bdc3f47c bdk: i2c: fix stack buffer overflow 2023-08-07 21:02:20 +03:00
CTCaer 09b1efe2a4 nyx: info: use updated defines 2023-07-31 17:09:04 +03:00
CTCaer bb0a1fd0a2 minerva: add freqs up to 2366 MHz 2023-07-31 17:05:09 +03:00
CTCaer 1cc97ebc51 bdk: update various comments 2023-07-31 17:03:15 +03:00
CTCaer 1e28320e5a bdk: t210: add more mmio addresses 
And simplify relevant drivers that hardcoded them.
 2023-07-31 16:59:15 +03:00
CTCaer 0fe17cfb41 l4t: add latest api version info 2023-07-28 15:42:16 +03:00
CTCaer 91393700ff nyx: use restore/emummc folder for restoring 
In order to avoid mistakes, emuMMC can now only be restored from `backup/{emmc_sn}/restore/emummc`.
 2023-07-28 04:07:43 +03:00
CTCaer cb964fe5d2 l4t: allow ram undervolting 2023-07-28 04:04:03 +03:00
CTCaer 010b08d4c7 l4t: t210b01: set real dram rate by default 
Since Arachne Register Cell (ARC) is now final and stable,
automatically set rated DRAM frequency for T210B01 by default.
1866 MHz for old ones and 2133 MHz for newer ones.

Setting anything from 1600000 and lower will disable that.
 2023-07-28 04:03:01 +03:00
CTCaer b5fcdad33f nyx: info: improve ram channel/rank detection 2023-07-28 03:40:32 +03:00
CTCaer 6061bb5213 nyx: info: add public key info 
And remove LOT Code 1 since it's not used.
 2023-07-28 03:38:40 +03:00
CTCaer 221614212a nyx: info: add more cal0 info 
Touch vendor, IMU type/mount and analog stick types.
 2023-07-28 03:36:10 +03:00
CTCaer 5b94e8cf8a nyx: info: use fuel gauge reg dump function 2023-07-28 03:35:08 +03:00
CTCaer f291a5cfa7 bdk: max17050: add reg dumping 2023-07-28 03:34:11 +03:00
CTCaer 7e397b3403 nyx: options: change autorcm icon 2023-07-28 03:33:09 +03:00
CTCaer f35c5b0596 nyx: fix first time config save unmounting 
SD card should not get unmounted on the first boot without hekate_ipl.ini.
Move sd card mounting management outside of it.
 2023-07-28 03:32:33 +03:00
CTCaer b142ca0f33 nyx: info: use new fuse names 2023-07-28 03:29:24 +03:00
CTCaer 21da947c02 nyx: hos: deduplicate cal0 dumping 2023-07-28 03:28:21 +03:00
CTCaer 317abb2f4e hekate: add bootwait for each entry 
Allow overriding global bootwait with the one from boot entry.
 2023-07-28 03:23:03 +03:00
CTCaer d3567736c8 hos: allow overriding uCID 2023-07-28 03:06:20 +03:00
CTCaer 9187fa7a8c bdk: fuse: add all t210b01 fuses 
And use B01 to distinguish the ones only on that SoC.
 2023-07-22 07:10:12 +03:00
CTCaer b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00
CTCaer 6e954f5cdf nyx: provide the raw calib for Lite gamepad 
Let L4T driver manage it.
 2023-06-11 13:29:04 +03:00
CTCaer d7ad9b874b bdk: use the typedefs on jc calib 2023-06-11 13:27:48 +03:00
CTCaer 820e6d5a6e bdk: update cal0 struct 2023-06-10 23:48:45 +03:00
CTCaer 0215d16405 Bump hekate to v6.0.4 and Nyx to v1.5.4 2023-06-09 11:08:13 +03:00
CTCaer c0c0e34ef0 nyx: info: update dram info 2023-06-09 11:04:31 +03:00
CTCaer 581ac8ec33 nyx: info: always report errors for eMMC 
Even if init fails.
 2023-06-09 11:04:07 +03:00
CTCaer 26bf148188 nyx: add Lite gamepad calibration data dumping 
Adds calibration data dumping via the Joycon BT pairing dumping function.

Calibration for everything about Sio is dumped. So Sticks and IMU.
 2023-06-09 11:03:29 +03:00
CTCaer dc8f6beb8d nyx: info: make cal0 dumping public 2023-06-09 11:01:08 +03:00
CTCaer 25b181bf36 nyx: add missing newlines 
Change line since the text does not fit like that in these places, effectively breaking text color.
 2023-06-09 10:59:03 +03:00
CTCaer 66e5e128f6 l4t: adjust revision amidst the new changes 
Also add helpful message if files are missing.
 2023-06-09 10:56:39 +03:00
CTCaer 84822726cb l4t: add fine tuned voltage support for DRAM 
1000-1175mV for T210 VDDIO/Q via `ram_oc_vdd2`
1000-1175mV for T210B01 VDDIO and 600-650mV for VDDQ via `ram_oc_vdd2` and `ram_oc_vddq`.
 2023-06-09 10:55:32 +03:00
CTCaer b6e1e0d412 l4t: add bpmp-fw support for T210 2023-06-09 10:53:03 +03:00
CTCaer 496737248c l4t: there was never a need to normalize dram freq 2023-06-09 10:51:31 +03:00
CTCaer 4f52e1f24a l4t: refactor bpmp-fw defines for T210B01 2023-06-09 10:50:29 +03:00
CTCaer 3f9c7a7da6 hos: prep boot freq in minerva for cfw also 2023-06-09 10:41:53 +03:00
CTCaer 93ed4d0899 bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
CTCaer 01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer 191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer 8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer 18f3a1b70c bdk: max77620: reduce max DRAM VDDIO/Q 
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
 2023-06-09 10:24:55 +03:00
CTCaer 418f029d11 lib: minerva: add 1966 and 2033 MHz in div table 2023-06-08 05:31:15 +03:00
CTCaer 066efda4cd lib: minerva: normalize output frequency 
Allow frequencies that are not exact to receive proper dividers from the supported ones from table.
 2023-06-08 04:56:14 +03:00
CTCaer d8d15bde44 lib: minerva: add Samsung 8GB support 
And remove frequencies smaller than deep sleep frequency from the tables.
 2023-06-08 04:50:59 +03:00
CTCaer 9d8ebc7e38 lib: minerva: refactor table 
Remove _idx used initially for RE at last.
 2023-06-08 04:49:16 +03:00
CTCaer c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210 
And remove Copper support completely.
 2023-06-08 04:16:51 +03:00
CTCaer 73a133556d bdk: sdram: correct sku related info 
Validated so rename accordingly.
 2023-06-08 02:57:30 +03:00
CTCaer 7d3663616e bdk: sdram: name 2 of the new ram chips 
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
 2023-06-08 02:52:03 +03:00
CTCaer e76aebabba bdk: mem: minerva: check table size in clock check 
Don't hardcode table size to 10.
 2023-06-08 02:45:34 +03:00
CTCaer bc0eea11f3 bdk: joycon: add calibration struct 2023-06-08 02:44:35 +03:00
CTCaer 937ab52d14 Bump hekate to v6.0.4 2023-05-09 11:15:34 +03:00
CTCaer e896d388ab hos: 16.0.3 support 2023-05-09 11:15:11 +03:00
CTCaer ded959c449 Bump hekate to v6.0.3 and Nyx to v1.5.3 2023-04-06 17:38:36 +03:00
CTCaer a7fd83c793 nyx: correct build flag 2023-04-06 17:36:22 +03:00
CTCaer dd380d4d47 l4t: increase bw priority to SDMMC1 for L4T 2023-04-06 17:34:26 +03:00
CTCaer 795b4ad26e bdk: sdmmc: increase bw priority to SDMMC1 for L4T 2023-04-06 17:30:01 +03:00
CTCaer bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00
CTCaer 811fa4c88b bdk: sdmmc: add SD registers debug printing 
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
 2023-04-06 10:13:35 +03:00
CTCaer 22462e4bf3 nyx: info: optimize random benchmarking 
Do not allow SD/eMMC to breath during random reads benchmarking. So only render progress at 15fps.
 2023-03-31 09:24:55 +03:00
CTCaer ca0263fa8c hekate: info: fully deinit/unmount sd card 2023-03-31 09:17:51 +03:00
CTCaer b1112e0949 hos: set proper exo hos version for 12.1.0 
Even if 12.0.0 one is api compatible, there was a master key change on 12.1.0.
 2023-03-31 09:17:13 +03:00
CTCaer 3c3fcb29f9 hekate: clear rtc interrupt and stop alarm 
Stopping rtc alarm is now done in the function that actually checks it, in order to avoid power offs from HOS if it's fired and user wants to continue booting.

Additionally, clear the interrupt which is the actual thing that is checked by HOS.
 2023-03-31 09:15:56 +03:00
CTCaer 8528e6a08a bdk: util: do not edit rtc alarm in power function 2023-03-31 09:12:58 +03:00
CTCaer 27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer 50811aacfa bdk: touch: reorder power on 
So touch IC reset can be properly done on a fast power cycle.
 2023-03-31 09:08:20 +03:00
CTCaer f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer d258c82d52 bdk: sdmmc: add UHS DDR200 support 
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
 2023-03-31 08:54:13 +03:00