OmniNX/hekate
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b352baea432e0758b38f8cc28688f44ad0929347
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589 Commits

Author SHA1 Message Date
CTCaer
74972a68df bdk: joycon: make init stricter but relax timings 
Additionally, if both Joy-Con are found, try to send rumble simultaneously.
 2026-01-20 20:03:38 +02:00
CTCaer
3134af6e92 bdk: display: reduce display off waiting time 
And align oled panel inside vblank.
Assumes display deinit happens before the rest of deinit.
 2026-01-20 06:13:02 +02:00
CTCaer
5936d9bad4 bdk: se: add T210 SHA256 silicon errata WAR 
Apparently, some T210 silicon have an undocumented errata where the MSG_LEFT2/3
registers are not ignored as they should.
When they have random data in POR they cause a hang as long as the message and
SHA calculation speed. So always clear them.
Additionally, clear MSG_LENGTH2/3 registers too even though they do not matter.
 2026-01-15 19:09:34 +02:00
CTCaer
68281d3051 bdk: se: adjust T210 silicon errata coherency WAR 
Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).
 2026-01-15 19:02:36 +02:00
CTCaer
e3267d1db7 bdk: se: correct result for < block size aes 2026-01-15 17:40:52 +02:00
CTCaer
8ab6f04243 bdk: hwinit: remove coreboot support 
Everything external is finally updated and beyond parity with old things that needed it.
 2026-01-12 03:57:39 +02:00
CTCaer
bf5a7b1a12 bdk: joycon: more refactoring 2026-01-12 03:08:20 +02:00
CTCaer
d94f356bf5 bdk: joycon: generalize _jc_packet_add_uart_hdr 
Correct its header construction in case it's used in the future.
Plus some unhardcoding of lengths.
 2026-01-11 17:24:18 +02:00
CTCaer
876d6adbe7 bdk: joycon: increase connection timeout to 1.8s 2026-01-11 17:06:48 +02:00
CTCaer
b4fcc72b6b bdk: joycon: refactor some fields 
And add better comments.
 2026-01-11 17:05:37 +02:00
CTCaer
928985ced1 bdk: joycon: use packed structs and bitfields 2026-01-10 13:39:06 +02:00
CTCaer
8123de714a bdk: joycon: correct crc8 offsets 
By luck the current offset and length of the calculation always worked.
Correct it though because the function might be used fully in the future.
 2026-01-10 13:36:34 +02:00
CTCaer
f05759e0f2 bdk: joycon: maintain consistent naming styles 2026-01-10 13:32:46 +02:00
CTCaer
76cb5422e3 bdk: joycon: optimize rumble enable 2026-01-06 23:14:11 +02:00
CTCaer
316650dda6 bdk: display: add OLED status pin 
Code is commented out for now until it gets used.
Status is set when RST is enabled.
 2026-01-06 23:10:42 +02:00
CTCaer
afa9715cf4 bdk: se: support multiple/partial blocks for RNG 2026-01-06 23:02:33 +02:00
CTCaer
1696dd8ebf bdk: se: use proper naming for ctx keys 2026-01-06 23:00:46 +02:00
CTCaer
c9208593af bdk: se: refactor and optimize SHA256 
- Simplify config and fix partial hashing
- Add partial function calls
- All partial state is handled internally
- All functions now use the classic naming convention.
 2026-01-06 22:59:20 +02:00
CTCaer
607b19067a bdk: se: use classic naming convention for XTS 2026-01-06 22:52:21 +02:00
CTCaer
b7f1641bce bdk: se: add AES OFB encryption/decryption support 2026-01-06 22:49:57 +02:00
CTCaer
2fa1a6a4af bdk: se: remove dst/src size argument requirement 
All operations expect the destination buffer to fit the selected size.
And for simplicity STATE_WAIT is not supported.

Additionally, remove single block ECB and just use the normal function.
 2026-01-06 22:47:54 +02:00
CTCaer
3463623126 bdk: se: optimize and update aes cmac hashing 
`se_aes_cmac_128` was also renamed to `se_aes_hash_cmac`.
By following the convention of 128bit functions not having size in their name.
 2026-01-06 22:32:26 +02:00
CTCaer
b4ca6cae21 bdk: se: handle original and updated IV in one go 
IV set now requires a size where the second block is updated IV
IV clear now clears both.
 2026-01-06 22:28:18 +02:00
CTCaer
d442390e9b bdk: se: support partial blocks for all aes modes 2026-01-06 22:23:25 +02:00
CTCaer
ca307e78c8 bdk: se: do a trivial refactor pass 2026-01-06 22:18:45 +02:00
CTCaer
13c91d2848 bdk: heap: use ultra fast defragmentation 
The defragmentation runs on every free and it only merges subsequent nodes.
So there's no point of looping all nodes.
So, just check if previous and next nodes are mergeable.
This makes free performant and achieves the same exact functionality.
 2026-01-05 12:33:31 +02:00
CTCaer
800bec2ec2 bdk: max17050: simplify calculations 
And make current readings a tiny bit (±0.16%) more accurate.
 2025-12-31 03:44:44 +02:00
CTCaer
067c12655b bdk: max17050: remove unused cached batt voltage 2025-12-27 06:06:56 +02:00
CTCaer
c03757e73d bdk: joycon: improve charger config 
Utilize charger config set command which allows for supplement mode.
Additionally, remove ping config when SIO and parse buttons/sticks on subcmd reports.
 2025-12-27 06:06:17 +02:00
CTCaer
0cab56293d bdk: ccplex: do not disable mselect on cpu pwrgate 2025-12-25 12:51:37 +02:00
CTCaer
ae7c5fdfdb bdk: heap: add more safe guards 
- Use magic for used regions
- Deduplicate calloc
Enable a print/abort in _heap_free() for debugging.
 2025-12-25 12:33:41 +02:00
CTCaer
a7ad3d4984 bdk: display: improve and deduplicate more 
- Add delay after a DSI soft reset
- Remove more duplicated configs
- Improve code to save code size
- Improve comments
- Do not allow display_backlight to be used with OLED
 2025-12-25 11:36:06 +02:00
CTCaer
67140d026c bdk: util: use volatile base for reg_write_array 2025-12-18 11:50:00 +02:00
CTCaer
998053f8db bdk: display: use a scratch reg for backlight 
Spare registers normally have hidden hw config usage, so avoid them just in case.
 2025-12-18 11:48:53 +02:00
CTCaer
b5a6c8eb64 bdk: display: simplify macros 
Expand register index in parent macro and remove _DI/_DSIREG macros.
 2025-12-18 11:17:43 +02:00
CTCaer
8faa1a6690 bdk: display: use spare reg to store dcs bl duty 
And also remove backlight pwm restoring from coreboot hw deinit path.
 2025-12-18 09:54:26 +02:00
CTCaer
ba95bb7494 bdk: fatfs: improve fat read/write 
- Convert access from min cluster size to block size
  Also allow read/writes to less than cluster size
- In case of intercluster access throw an error
- Do not error on zero size

On reads buffer still needs to be block (instead of cluster) aligned.
On writes, buffer still needs to be readable out of bounds.
 2025-12-17 07:11:51 +02:00
CTCaer
20a50988c5 bdk: fuse: return array size with fuse_read_array 2025-12-17 06:41:52 +02:00
CTCaer
0db758592a bdk: minerva: add IRB support 
Aka no table support.
 2025-12-17 05:24:16 +02:00
CTCaer
8d6bb5f427 bdk: clock: update some defines 2025-12-17 04:33:40 +02:00
CTCaer
4797b42e76 bdk: sdmmc: add defines for max block number 2025-12-17 04:30:12 +02:00
CTCaer
7cbefa3061 bdk: add reserved cfg to ipl meta and nyx storage 2025-11-27 12:17:33 +02:00
CTCaer
5176ce4394 bdk: sdmmc: correct drive ohms comment 2025-11-27 12:14:43 +02:00
CTCaer
a6d4e5adaa bdk: clock: add i2c to the errata affected list 2025-11-27 12:12:13 +02:00
CTCaer
4a24956f3a bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2025-11-27 12:04:12 +02:00
CTCaer
727d37c991 bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2025-11-27 11:25:08 +02:00
CTCaer
1fc92cfa33 bdk: nyx: rename disp_id to panel_id 2025-11-27 11:21:06 +02:00
CTCaer
62163f3255 bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2025-11-27 11:20:19 +02:00
CTCaer
fc71e405d2 bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2025-11-27 11:13:54 +02:00
CTCaer
e7783f0bd7 bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2025-11-26 16:53:19 +02:00