OmniNX/hekate
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94947672958d6d05c450cf1c9e575ce208a18ea7
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60 Commits

Author SHA1 Message Date
CTCaer
9494767295 bdk: mc: add offset to arc aperture 
And increase it back to 4KB for TSEC only, since the firmware actually checks for it.
 2026-03-20 13:34:55 +02:00
CTCaer
c6c89ce0b1 bdk: smmu: reset heap on disable 
And rename domain init/deinit
 2026-03-18 22:35:01 +02:00
CTCaer
392cda96d9 bdk: mc: always enable ahb redirection 2026-02-25 13:32:18 +02:00
CTCaer
0b7415f6d4 bdk: tsec: homogenize return values 2026-02-22 03:10:18 +02:00
CTCaer
d328d56268 bdk: se: homogenize return values 2026-02-22 03:08:34 +02:00
CTCaer
5936d9bad4 bdk: se: add T210 SHA256 silicon errata WAR 
Apparently, some T210 silicon have an undocumented errata where the MSG_LEFT2/3
registers are not ignored as they should.
When they have random data in POR they cause a hang as long as the message and
SHA calculation speed. So always clear them.
Additionally, clear MSG_LENGTH2/3 registers too even though they do not matter.
 2026-01-15 19:09:34 +02:00
CTCaer
68281d3051 bdk: se: adjust T210 silicon errata coherency WAR 
Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).
 2026-01-15 19:02:36 +02:00
CTCaer
e3267d1db7 bdk: se: correct result for < block size aes 2026-01-15 17:40:52 +02:00
CTCaer
afa9715cf4 bdk: se: support multiple/partial blocks for RNG 2026-01-06 23:02:33 +02:00
CTCaer
1696dd8ebf bdk: se: use proper naming for ctx keys 2026-01-06 23:00:46 +02:00
CTCaer
c9208593af bdk: se: refactor and optimize SHA256 
- Simplify config and fix partial hashing
- Add partial function calls
- All partial state is handled internally
- All functions now use the classic naming convention.
 2026-01-06 22:59:20 +02:00
CTCaer
607b19067a bdk: se: use classic naming convention for XTS 2026-01-06 22:52:21 +02:00
CTCaer
b7f1641bce bdk: se: add AES OFB encryption/decryption support 2026-01-06 22:49:57 +02:00
CTCaer
2fa1a6a4af bdk: se: remove dst/src size argument requirement 
All operations expect the destination buffer to fit the selected size.
And for simplicity STATE_WAIT is not supported.

Additionally, remove single block ECB and just use the normal function.
 2026-01-06 22:47:54 +02:00
CTCaer
3463623126 bdk: se: optimize and update aes cmac hashing 
`se_aes_cmac_128` was also renamed to `se_aes_hash_cmac`.
By following the convention of 128bit functions not having size in their name.
 2026-01-06 22:32:26 +02:00
CTCaer
b4ca6cae21 bdk: se: handle original and updated IV in one go 
IV set now requires a size where the second block is updated IV
IV clear now clears both.
 2026-01-06 22:28:18 +02:00
CTCaer
d442390e9b bdk: se: support partial blocks for all aes modes 2026-01-06 22:23:25 +02:00
CTCaer
ca307e78c8 bdk: se: do a trivial refactor pass 2026-01-06 22:18:45 +02:00
CTCaer
c63ccd0cdc bdk: pmc: rename pmc_enable_partition 2025-08-27 14:39:44 +03:00
CTCaer
129a70c32d bdk: se: heap is not used anymore 2025-04-30 09:13:55 +03:00
CTCaer
08872325c8 bdk: se: add 0 byte sha256 support 2025-04-30 08:15:15 +03:00
CTCaer
9ba94bae2d bdk: se: remove malloc usage 2025-01-24 15:15:03 +02:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
7a74761da9 bdk: bpmp: add and use bpmp_clk_rate_relaxed 2024-06-02 06:51:06 +03:00
CTCaer
d687b53249 bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
CTCaer
9e41aa7759 bdk: smmu: refactor and update driver 
- Allow ASID to be configured
- Allow 34-bit PAs
- Use special type for setting PDE/PTE config
- Initialize all pages as non accessible
- Add function for mapping 4MB regions directly
- Add SMMU heap reset function
- Correct address load OP to 32-bit and remove alignment on SMMU enable payload
- Refactor all defines
 2024-03-14 09:21:06 +02:00
CTCaer
9ba7c44b89 bdk: clock: use real source clock dividers 
Use CLK_SRC_DIV macro in order to have the actual divider showing.
 2024-03-13 02:01:01 +02:00
CTCaer
9a520d63a6 bdk: smmu: refactor driver and allow other asid 2024-03-13 01:54:46 +02:00
CTCaer
3a4fa12f42 bdk: smmu: powergate ccplex after enabling smmu 2024-03-13 01:44:58 +02:00
CTCaer
92093ff08e bdk: se: deduplicate sha hash extraction 2023-12-27 21:07:52 +02:00
CTCaer
e47a819948 bdk: se: add more useful functions 
- aes cmac 128bit
- aes hashing
- option to clear updated aes iv
 2023-12-25 03:44:52 +02:00
CTCaer
8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer
27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer
9a98c1afb9 bdk: stylistic corrections 
And update copyrights
 2023-02-11 23:46:38 +02:00
CTCaer
d0b22bf374 bdk: manage host1x only in hw init 2022-12-19 05:14:39 +02:00
CTCaer
b891657fb6 bdk: tsec: fix regression on HOS 6.2.0 not booting 
With the latest BDK changes on enabling always on AHB redirect with a compile time flag, TSEC fw boot was regressed because it needs it off.

Always disable redirect and if the flag is enabled, enable it on exit.
 2022-07-11 22:28:09 +03:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
b65b2d7f71 bdk: se: do not use heap for linked lists 2022-06-27 09:14:43 +03:00
CTCaer
7c74391754 bdk: bpmp: do not use full maintenance 
Instead use proper clean/invalidation of dcache.
 2022-02-15 00:14:14 +02:00
CTCaer
ef5790cc2c bdk: mc: always on ahb arbitration 
- Removed disables
- SDMMC code now just checks if it has access
 2022-01-29 01:29:02 +02:00
CTCaer
c1441a64c7 bdk: se: expose xts functions and add nx xts 2022-01-20 12:28:26 +02:00
CTCaer
0e35e68fd5 bdk: se: add t210b01 data coherency WAR 2022-01-20 12:27:25 +02:00
CTCaer
70504c295e bdk: various functionality independent changes 2022-01-16 01:03:24 +02:00
CTCaer
a5cd962f99 bdk: add global header 2022-01-15 23:58:27 +02:00
CTCaer
c801ef8dda bdk: use size defines where applicable 2021-10-01 15:03:18 +03:00
CTCaer
d5322f384b tsec: make sure cpu power rails are off 2021-09-17 23:10:57 +03:00
CTCaer
9cf0b0f484 tsec: change kb to type 
Now the path taken is decided by tsec fw type instead of mkey version
 2021-08-28 16:42:03 +03:00
CTCaer
9541d1bbd3 se: add encrypt/decrypt defines 2021-08-28 16:40:29 +03:00
CTCaer
d7ce2a81db bpmp: return previous fid when setting a new one 2021-05-11 09:21:12 +03:00