CTCaer 5a35a61753 bdk: se: adjust T210 silicon errata coherency WAR ...

Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).

2026-03-27 10:02:21 +01:00

..

se_t210.h

bdk: se: do a trivial refactor pass

2026-03-27 09:59:42 +01:00

se.c

bdk: se: adjust T210 silicon errata coherency WAR

2026-03-27 10:02:21 +01:00

se.h

bdk: se: support multiple/partial blocks for RNG

2026-03-27 09:59:42 +01:00

tsec_t210.h

bdk: tsec: refactor some register names

2023-06-09 10:28:28 +03:00

tsec.c

bdk: pmc: rename pmc_enable_partition

2026-03-27 09:44:06 +01:00

tsec.h

bdk: smmu: powergate ccplex after enabling smmu

2024-03-13 01:44:58 +02:00