Bump hekate to v5.3.4 and Nyx to v0.9.5

main: Fix update.bin creation on first boot
Refactor some names
2020-10-27 21:28:06 +02:00 · 2020-10-27 21:27:51 +02:00 · 2020-10-23 06:32:24 +03:00 · 2020-10-20 11:53:28 +03:00 · 2020-10-20 10:42:57 +03:00 · 2020-10-20 10:37:33 +03:00
39 changed files with 421 additions and 268 deletions
--- a/README.md
+++ b/README.md
@@ -55,6 +55,7 @@ You can find a template [Here](./res/hekate_ipl_template.ini)
 | bootwait=3         | 0: Disable (It also disables bootlogo. Having **VOL-** pressed since injection goes to menu.), #: Time to wait for **VOL-** to enter menu. |
 | autohosoff=1       | 0: Disable, 1: If woke up from HOS via an RTC alarm, shows logo, then powers off completely, 2: No logo, immediately powers off.|
 | autonogc=1         | 0: Disable, 1: Automatically applies nogc patch if unburnt fuses found and a >= 4.0.0 HOS is booted. |
+| bootprotect=0      | 0: Disable, 1: Protect bootloader folder from being corrupted by disallowing reading or editing in HOS. |
 | updater2p=0        | 0: Disable, 1: Force updates (if needed) the reboot2payload binary to be hekate. |
 | backlight=100      | Screen backlight level. 0-255.                             |

@@ -67,7 +68,8 @@ You can find a template [Here](./res/hekate_ipl_template.ini)
 | timeoff=100        | Sets time offset in HEX. Must be in HOS epoch format       |
 | homescreen=0       | Sets home screen. 0: Home menu, 1: All configs (merges Launch and More configs), 2: Launch, 3: More Configs. |
 | verification=1     | 0: Disable Backup/Restore verification, 1: Sparse (block based, fast and mostly reliable), 2: Full (sha256 based, slow and 100% reliable). |
-| umsemmcrw=1        | 1: eMMC/emuMMC UMS will be mounted as writable by default. |
+| umsemmcrw=0        | 1: eMMC/emuMMC UMS will be mounted as writable by default. |
+| jcdisable=0        | 1: Disables Joycon driver completely.                      |


 ### Boot entry key/value combinations:
--- a/Versions.inc
+++ b/Versions.inc
@@ -1,11 +1,11 @@
 # IPL Version.
 BLVERSION_MAJOR := 5
 BLVERSION_MINOR := 3
-BLVERSION_HOTFX := 3
+BLVERSION_HOTFX := 4
 BLVERSION_RSVD := 0

 # Nyx Version.
 NYXVERSION_MAJOR := 0
 NYXVERSION_MINOR := 9
-NYXVERSION_HOTFX := 4
+NYXVERSION_HOTFX := 5
 NYXVERSION_RSVD := 0
--- a/bdk/gfx/di.c
+++ b/bdk/gfx/di.c
@@ -56,7 +56,7 @@ static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
 void display_init()
 {
 	// Check if display is already initialized.
-	if (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) & 0x18000000)
+	if (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) & (BIT(CLK_L_DISP1) | BIT(CLK_L_HOST1X)))
 		display_end();

 	// Power on.
@@ -180,14 +180,15 @@ void display_init()
 	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000);

 	// Configure PLLD for DISP1.
-	plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 460.8 MHz.
+	plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 230.4 MHz.
 	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
 	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;
 	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN.

 	// Finalize DSI configuration.
 	exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 21);
-	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; // PCD1 | div3.
+	// Set pixel clock dividers: 230.4 / 3 / 1 = 76.8 MHz. 60 Hz.
+	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4); // 4: div3.
 	exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10);
 	usleep(10000);

--- a/bdk/gfx/di.inl
+++ b/bdk/gfx/di.inl
@@ -96,7 +96,7 @@ static const cfg_op_t _display_dc_setup_win_config[94] = {
 	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
 	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
 	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-	{0x4E4, 0},
+	{DC_DISP_BLEND_BACKGROUND_COLOR, 0},
 	{DC_COM_CRC_CONTROL, 0},
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
@@ -253,7 +253,7 @@ static const cfg_op_t _display_dsi_packet_config[21] = {
 	{DSI_PKT_LEN_2_3, 0x87001A2},
 	{DSI_PKT_LEN_4_5, 0x190},
 	{DSI_PKT_LEN_6_7, 0x190},
-	{DSI_HOST_CONTROL, 0},
+	{DSI_HOST_CONTROL, 0}
 };

 //DSI mode config.
@@ -372,16 +372,16 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
 	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
 	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
 	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-	{0x4E4, 0},
+	{DC_DISP_BLEND_BACKGROUND_COLOR, 0},
 	{DC_COM_CRC_CONTROL, 0},
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{0x716, 0x10000FF},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
 	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
@@ -394,14 +394,37 @@ static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
 	{DC_CMD_STATE_ACCESS, 0},
-	/* Set Display timings */
+
+	/* Set Display timings
+	 *
+	 * DC_DISP_REF_TO_SYNC:
+	 *  V_REF_TO_SYNC - 1
+	 *  H_REF_TO_SYNC - 0
+	 *
+	 * DC_DISP_SYNC_WIDTH:
+	 *  V_SYNC_WIDTH - 1
+	 *  H_SYNC_WIDTH - 72
+	 *
+	 * DC_DISP_BACK_PORCH:
+	 *  V_BACK_PORCH - 9
+	 *  H_BACK_PORCH - 72
+	 *
+	 * DC_DISP_ACTIVE:
+	 *  V_DISP_ACTIVE - 1280
+	 *  H_DISP_ACTIVE - 720
+	 *
+	 * DC_DISP_FRONT_PORCH:
+	 *  V_FRONT_PORCH - 10
+	 *  H_FRONT_PORCH - 136
+	 */
 	{DC_DISP_DISP_TIMING_OPTIONS, 0},
-	{DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
+	{DC_DISP_REF_TO_SYNC, 0x10000},
 	{DC_DISP_SYNC_WIDTH,  0x10048},
 	{DC_DISP_BACK_PORCH,  0x90048},
 	{DC_DISP_ACTIVE,      0x50002D0},
-	{DC_DISP_FRONT_PORCH, 0xA0088},   // Sources say that this should be above the DC_DISP_ACTIVE cmd.
+	{DC_DISP_FRONT_PORCH, 0xA0088},   // Sources say that this should happen before DC_DISP_ACTIVE cmd.
 	/* End of Display timings */
+
 	{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
 	{DC_COM_PIN_OUTPUT_ENABLE(1), 0},
 	{DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
--- a/bdk/input/joycon.c
+++ b/bdk/input/joycon.c
@@ -523,6 +523,9 @@ jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos)
 	u8 retries;
 	jc_bt_conn_t *bt_conn;

+	if (!jc_init_done)
+		return NULL;
+
 	bt_conn = &jc_gamepad.bt_conn_l;
 	memset(bt_conn->host_mac, 0, 6);
 	memset(bt_conn->ltk, 0, 16);
--- a/bdk/power/bm92t30_stub.c
+++ b/bdk/power/bm92t30_stub.c
@@ -1,65 +0,0 @@
-/*
- * USB-PD driver for Nintendo Switch's TI BM92T30
- *
- * Copyright (c) 2020 CTCaer
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * TODO:
- * This driver is a stub and relies on incorrect I2C requests.
- * The I2C driver needs to be updated with proper multi-xfer support.
- *
- * For now it replies its whole register range, according to request
- * size. That's because the IC does not support the classic single
- * transfer request-response style.
- */
-
-#include <string.h>
-
-#include "bm92t30_stub.h"
-#include <soc/i2c.h>
-#include <utils/util.h>
-
-#define STATUS1_INSERT 0x80
-
-typedef struct _pdo_t{
-	u32 amp:10;
-	u32 volt:10;
-	u32 info:10;
-	u32 type:2;
-} pdo_t;
-
-void bm92t30_get_charger_type(bool *inserted, usb_pd_objects_t *usb_pd)
-{
-	u8 buf[32];
-	pdo_t pdos[7];
-	i2c_recv_buf_big(buf, 32, I2C_1, BM92T30_I2C_ADDR, 0);
-
-	if (inserted)
-		*inserted = buf[6] & STATUS1_INSERT ? true : false;
-	memcpy(pdos, &buf[17], 15); // We can only get max 4 objects.
-
-	if (usb_pd)
-	{
-		memset(usb_pd, 0, sizeof(usb_pd_objects_t));
-		usb_pd->pdo_no = MIN(buf[16] / sizeof(pdo_t), 4);  // We can only get max 4 objects.
-
-		for (u32 i = 0; i < usb_pd->pdo_no; i++)
-		{
-			usb_pd->pdos[i].amperage = pdos[i].amp * 10;
-			usb_pd->pdos[i].voltage = (pdos[i].volt * 50) / 1000;
-		}
-	}
-}
--- a/bdk/power/bm92t36.c
+++ b/bdk/power/bm92t36.c
@@ -0,0 +1,99 @@
+/*
+ * USB-PD driver for Nintendo Switch's TI BM92T36
+ *
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "bm92t36.h"
+#include <soc/i2c.h>
+#include <utils/util.h>
+
+#define ALERT_STATUS_REG    0x2
+#define STATUS1_REG         0x3
+#define STATUS2_REG         0x4
+#define COMMAND_REG         0x5
+#define CONFIG1_REG         0x6
+#define DEV_CAPS_REG        0x7
+#define READ_PDOS_SRC_REG   0x8
+#define CONFIG2_REG         0x17
+#define DP_STATUS_REG       0x18
+#define DP_ALERT_EN_REG     0x19
+#define VENDOR_CONFIG_REG   0x1A
+#define AUTO_NGT_FIXED_REG  0x20
+#define AUTO_NGT_BATT_REG   0x23
+#define SYS_CONFIG1_REG     0x26
+#define SYS_CONFIG2_REG     0x27
+#define CURRENT_PDO_REG     0x28
+#define CURRENT_RDO_REG     0x2B
+#define ALERT_ENABLE_REG    0x2E
+#define SYS_CONFIG3_REG     0x2F
+#define SET_RDO_REG         0x30
+#define PDOS_SNK_REG        0x33
+#define PDOS_SRC_PROV_REG   0x3C
+#define FW_TYPE_REG         0x4B
+#define FW_REVISION_REG     0x4C
+#define MAN_ID_REG          0x4D
+#define DEV_ID_REG          0x4E
+#define REV_ID_REG          0x4F
+#define INCOMING_VDM_REG    0x50
+#define OUTGOING_VDM_REG    0x60
+
+#define STATUS1_INSERT      BIT(7)  // Cable inserted.
+
+typedef struct _pd_object_t {
+	unsigned int amp:10;
+	unsigned int volt:10;
+	unsigned int info:10;
+	unsigned int type:2;
+} __attribute__((packed)) pd_object_t;
+
+static int _bm92t36_read_reg(u8 *buf, u32 size, u32 reg)
+{
+	return i2c_recv_buf_big(buf, size, I2C_1, BM92T36_I2C_ADDR, reg);
+}
+
+void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd)
+{
+	u8 buf[32];
+	pd_object_t pdos[7];
+
+	if (inserted)
+	{
+		_bm92t36_read_reg(buf, 2, STATUS1_REG);
+		*inserted = buf[0] & STATUS1_INSERT ? true : false;
+	}
+
+	if (usb_pd)
+	{
+		_bm92t36_read_reg(buf, 29, READ_PDOS_SRC_REG);
+		memcpy(pdos, &buf[1], 28);
+
+		memset(usb_pd, 0, sizeof(usb_pd_objects_t));
+		usb_pd->pdo_no = buf[0] / sizeof(pd_object_t);
+
+		for (u32 i = 0; i < usb_pd->pdo_no; i++)
+		{
+			usb_pd->pdos[i].amperage = pdos[i].amp * 10;
+			usb_pd->pdos[i].voltage = (pdos[i].volt * 50) / 1000;
+		}
+
+		_bm92t36_read_reg(buf, 5, CURRENT_PDO_REG);
+		memcpy(pdos, &buf[1], 4);
+		usb_pd->selected_pdo.amperage = pdos[0].amp * 10;
+		usb_pd->selected_pdo.voltage = (pdos[0].volt * 50) / 1000;
+	}
+}
--- a/bdk/power/bm92t30_stub.h
+++ b/bdk/power/bm92t30_stub.h
@@ -1,5 +1,5 @@
 /*
- * USB-PD driver for Nintendo Switch's TI BM92T30
+ * USB-PD driver for Nintendo Switch's TI BM92T36
 *
 * Copyright (c) 2020 CTCaer
 *
@@ -16,12 +16,12 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

-#ifndef __BM92T30_H_
-#define __BM92T30_H_
+#ifndef __BM92T36_H_
+#define __BM92T36_H_

 #include <utils/types.h>

-#define BM92T30_I2C_ADDR 0x18
+#define BM92T36_I2C_ADDR 0x18

 typedef struct _usb_pd_object_t
 {
@@ -33,8 +33,9 @@ typedef struct _usb_pd_objects_t
 {
 	u32 pdo_no;
 	usb_pd_object_t pdos[7];
+	usb_pd_object_t selected_pdo;
 } usb_pd_objects_t;

-void bm92t30_get_charger_type(bool *inserted, usb_pd_objects_t *usb_pd);
+void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd);

 #endif
--- a/bdk/soc/hw_init.c
+++ b/bdk/soc/hw_init.c
@@ -56,7 +56,7 @@ extern volatile nyx_storage_t *nyx_str;
 * PCLK    - 68MHz  init (-> 136MHz -> OC/4).
 */

-void _config_oscillators()
+static void _config_oscillators()
 {
 	CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
 	SYSCTR0(SYSCTR0_CNTFID0) = 19200000;             // Set counter frequency.
@@ -79,7 +79,7 @@ void _config_oscillators()
 	CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2;             // Set HCLK div to 1 and PCLK div to 3.
 }

-void _config_gpios()
+static void _config_gpios()
 {
 	// Clamp inputs when tristated.
 	APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
@@ -123,14 +123,14 @@ void _config_gpios()
 	// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
 }

-void _config_pmc_scratch()
+static void _config_pmc_scratch()
 {
 	PMC(APBDEV_PMC_SCRATCH20)  &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
 	PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
 	PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
 }

-void _mbist_workaround()
+static void _mbist_workaround()
 {
 	// Make sure Audio clocks are enabled before accessing I2S.
 	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
@@ -232,13 +232,14 @@ void _mbist_workaround()
 	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC)  = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000;  // Set clock source to PLLP_OUT.
 }

-void _config_se_brom()
+static void _config_se_brom()
 {
 	// Enable fuse clock.
 	clock_enable_fuse(true);

 	// Skip SBK/SSK if sept was run.
-	if (!(b_cfg.boot_cfg & BOOT_CFG_SEPT_RUN))
+	bool sbk_skip = b_cfg.boot_cfg & BOOT_CFG_SEPT_RUN || FUSE(FUSE_PRIVATE_KEY0) == 0xFFFFFFFF;
+	if (!sbk_skip)
 	{
 		// Bootrom part we skipped.
 		u32 sbk[4] = {
@@ -268,7 +269,7 @@ void _config_se_brom()
 	APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
 }

-void _config_regulators()
+static void _config_regulators()
 {
 	// Disable low battery shutdown monitor.
 	max77620_low_battery_monitor_config(false);
--- a/bdk/soc/i2c.c
+++ b/bdk/soc/i2c.c
@@ -21,35 +21,44 @@
 #include <utils/util.h>

 #define I2C_PACKET_PROT_I2C  (1 << 4)
+#define I2C_HEADER_CONT_XFER (1 << 15)
+#define I2C_HEADER_REP_START (1 << 16)
 #define I2C_HEADER_IE_ENABLE (1 << 17)
 #define I2C_HEADER_READ      (1 << 19)

-#define I2C_CNFG             (0x00 / 4)
+#define I2C_CNFG              (0x00 / 4)
 #define  CMD1_WRITE           (0 << 6)
 #define  CMD1_READ            (1 << 6)
 #define  NORMAL_MODE_GO       (1 << 9)
 #define  PACKET_MODE_GO       (1 << 10)
 #define  NEW_MASTER_FSM       (1 << 11)
 #define  DEBOUNCE_CNT_4T      (2 << 12)
-#define I2C_CMD_ADDR0        (0x04 / 4)
+
+#define I2C_CMD_ADDR0         (0x04 / 4)
 #define  ADDR0_WRITE          0
 #define  ADDR0_READ           1
-#define I2C_CMD_DATA1        (0x0C / 4)
-#define I2C_CMD_DATA2        (0x10 / 4)
-#define I2C_STATUS           (0x1C / 4)
+
+#define I2C_CMD_DATA1         (0x0C / 4)
+#define I2C_CMD_DATA2         (0x10 / 4)
+
+#define I2C_STATUS            (0x1C / 4)
 #define  I2C_STATUS_NOACK     (0xF << 0)
 #define  I2C_STATUS_BUSY      (1 << 8)
-#define I2C_TX_FIFO          (0x50 / 4)
-#define I2C_RX_FIFO          (0x54 / 4)
-#define I2C_FIFO_CONTROL     (0x5C / 4)
+
+#define I2C_TX_FIFO           (0x50 / 4)
+#define I2C_RX_FIFO           (0x54 / 4)
+
+#define I2C_FIFO_CONTROL      (0x5C / 4)
 #define  RX_FIFO_FLUSH        (1 << 0)
 #define  TX_FIFO_FLUSH        (1 << 1)
-#define I2C_FIFO_STATUS      (0x60 / 4)
+
+#define I2C_FIFO_STATUS       (0x60 / 4)
 #define  RX_FIFO_FULL_CNT     (0xF << 0)
 #define  TX_FIFO_EMPTY_CNT    (0xF << 4)
-#define I2C_INT_EN           (0x64 / 4)
-#define I2C_INT_STATUS       (0x68 / 4)
-#define I2C_INT_SOURCE       (0x70 / 4)
+
+#define I2C_INT_EN            (0x64 / 4)
+#define I2C_INT_STATUS        (0x68 / 4)
+#define I2C_INT_SOURCE        (0x70 / 4)
 #define  RX_FIFO_DATA_REQ     (1 << 0)
 #define  TX_FIFO_DATA_REQ     (1 << 1)
 #define  ARB_LOST             (1 << 2)
@@ -59,12 +68,16 @@
 #define  ALL_PACKETS_COMPLETE (1 << 6)
 #define  PACKET_COMPLETE      (1 << 7)
 #define  BUS_CLEAR_DONE       (1 << 11)
-#define I2C_CLK_DIVISOR      (0x6C / 4)
-#define I2C_BUS_CLEAR_CONFIG (0x84 / 4)
+
+#define I2C_CLK_DIVISOR       (0x6C / 4)
+
+#define I2C_BUS_CLEAR_CONFIG  (0x84 / 4)
 #define  BC_ENABLE            (1 << 0)
 #define  BC_TERMINATE         (1 << 1)
-#define I2C_BUS_CLEAR_STATUS (0x88 / 4)
-#define I2C_CONFIG_LOAD      (0x8C / 4)
+
+#define I2C_BUS_CLEAR_STATUS  (0x88 / 4)
+
+#define I2C_CONFIG_LOAD       (0x8C / 4)
 #define  MSTR_CONFIG_LOAD     (1 << 0)
 #define  TIMEOUT_CONFIG_LOAD  (1 << 2)

@@ -178,7 +191,7 @@ static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 	return 1;
 }

-static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
+static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
 {
 	if (size > 32)
 		return 0;
@@ -210,7 +223,7 @@ static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
 	u32 hdr[3];
 	hdr[0] = I2C_PACKET_PROT_I2C;
 	hdr[1] = size - 1;
-	hdr[2] = I2C_HEADER_IE_ENABLE | (dev_addr << 1);
+	hdr[2] = I2C_HEADER_IE_ENABLE | I2C_HEADER_CONT_XFER | (dev_addr << 1);

 	// Send header with request.
 	base[I2C_TX_FIFO] = hdr[0];
@@ -279,17 +292,33 @@ static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg)
 	// Initiate transaction on packet mode.
 	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | PACKET_MODE_GO;

+	// Send reg request.
 	u32 hdr[3];
 	hdr[0] = I2C_PACKET_PROT_I2C;
-	hdr[1] = size - 1;
-	hdr[2] = I2C_HEADER_READ | I2C_HEADER_IE_ENABLE | (dev_addr << 1);
+	hdr[1] = 1 - 1;
+	hdr[2] = I2C_HEADER_REP_START | (dev_addr << 1);

-	// Send header with request.
+	// Send header with reg request.
+	base[I2C_TX_FIFO] = hdr[0];
+	base[I2C_TX_FIFO] = hdr[1];
+	base[I2C_TX_FIFO] = hdr[2];
+	base[I2C_TX_FIFO] = reg;
+
+	u32 timeout = get_tmr_ms() + 400;
+	while (!(base[I2C_FIFO_STATUS] & TX_FIFO_EMPTY_CNT))
+		if (get_tmr_ms() > timeout)
+			break;
+
+	// Send read request.
+	hdr[1] = size - 1;
+	hdr[2] = I2C_HEADER_READ | (dev_addr << 1);
+
+	// Send header with read request.
 	base[I2C_TX_FIFO] = hdr[0];
 	base[I2C_TX_FIFO] = hdr[1];
 	base[I2C_TX_FIFO] = hdr[2];

-	u32 timeout = get_tmr_ms() + 400;
+	timeout = get_tmr_ms() + 400;
 	while (size)
 	{
 		if (base[I2C_FIFO_STATUS] & RX_FIFO_FULL_CNT)
@@ -347,20 +376,17 @@ int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr)
 	return _i2c_recv_single(i2c_idx, buf, size, dev_addr);
 }

-int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size)
+int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
 {
 	if (size > 32)
 		return 0;

-	return _i2c_send_pkt(i2c_idx, buf, size, dev_addr, reg);
+	return _i2c_send_pkt(i2c_idx, buf, size, dev_addr);
 }

 int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg)
 {
-	int res = _i2c_send_single(i2c_idx, dev_addr, (u8 *)&reg, 1);
-	if (res)
-		res = _i2c_recv_pkt(i2c_idx, buf, size, dev_addr, reg);
-	return res;
+	return _i2c_recv_pkt(i2c_idx, buf, size, dev_addr, reg);
 }

 int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size)
--- a/bdk/soc/i2c.h
+++ b/bdk/soc/i2c.h
@@ -29,7 +29,7 @@

 void i2c_init(u32 i2c_idx);
 int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr);
-int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size);
+int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size);
 int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg);
 int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size);
 int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg);
--- a/bdk/storage/sdmmc.c
+++ b/bdk/storage/sdmmc.c
@@ -169,6 +169,8 @@ int sdmmc_storage_end(sdmmc_storage_t *storage)

 	sdmmc_end(storage->sdmmc);

+	storage->initialized = 0;
+
 	return 1;
 }

@@ -179,6 +181,10 @@ static int _sdmmc_storage_readwrite(sdmmc_storage_t *storage, u32 sector, u32 nu
 	u32 sct_total = num_sectors;
 	bool first_reinit = true;

+	// Exit if not initialized.
+	if (!storage->initialized)
+		return 0;
+
 	while (sct_total)
 	{
 		u32 blkcnt = 0;
@@ -213,7 +219,8 @@ reinit_try:
 					sd_error_count_increment(SD_ERROR_INIT_FAIL);
 			}

-			// Reset retries to a lower number.
+			// Reset values for a retry.
+			blkcnt = 0;
 			retries = 3;
 			first_reinit = false;

@@ -228,6 +235,7 @@ reinit_try:
 			}
 		}

+		// Failed.
 		return 0;

 out:
@@ -631,6 +639,8 @@ DPRINTF("[MMC] succesfully switched to HS mode\n");

 	sdmmc_card_clock_ctrl(storage->sdmmc, SDMMC_AUTO_CAL_ENABLE);

+	storage->initialized = 1;
+
 	return 1;
 }

@@ -643,6 +653,7 @@ int sdmmc_storage_set_mmc_partition(sdmmc_storage_t *storage, u32 partition)
 		return 0;

 	storage->partition = partition;
+
 	return 1;
 }

@@ -1306,6 +1317,8 @@ DPRINTF("[SD] enabled HS\n");
 DPRINTF("[SD] got sd status\n");
 	}

+	storage->initialized = 1;
+
 	return 1;
 }

@@ -1357,5 +1370,7 @@ DPRINTF("[gc] after tuning\n");

 	sdmmc_card_clock_ctrl(sdmmc, SDMMC_AUTO_CAL_ENABLE);

+	storage->initialized = 1;
+
 	return 1;
 }
--- a/bdk/storage/sdmmc.h
+++ b/bdk/storage/sdmmc.h
@@ -116,6 +116,7 @@ typedef struct _sdmmc_storage_t
 	mmc_ext_csd_t ext_csd;
 	sd_scr_t      scr;
 	sd_ssr_t      ssr;
+	int initialized;
 } sdmmc_storage_t;

 int sdmmc_storage_end(sdmmc_storage_t *storage);
--- a/bdk/storage/sdmmc_driver.c
+++ b/bdk/storage/sdmmc_driver.c
@@ -241,8 +241,9 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
 	}

 #ifdef SDMMC_EMMC_OC
+	 // Add -4 TX_DLY_CODE_OFFSET if HS533.
 	if (sdmmc->id == SDMMC_4 && overclock)
-		sdmmc->regs->vendllcalcfg = sdmmc->regs->vendllcalcfg &= 0xFFFFC07F | (0x7C << 7); // Add -4 TX_DLY_CODE_OFFSET if HS533.
+		sdmmc->regs->vendllcalcfg = sdmmc->regs->vendllcalcfg &= 0xFFFFC07F | (0x7C << 7);
 #endif

 	sdmmc->regs->vendllcalcfg |= TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE;
@@ -399,9 +400,8 @@ void sdmmc_card_clock_ctrl(sdmmc_t *sdmmc, int auto_cal_enable)
 	sdmmc->auto_cal_enabled = auto_cal_enable;
 	if (auto_cal_enable)
 	{
-		if (!(sdmmc->regs->clkcon & SDHCI_CLOCK_CARD_EN))
-			return;
-		sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
+		if (sdmmc->regs->clkcon & SDHCI_CLOCK_CARD_EN)
+			sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
 		return;
 	}

@@ -725,7 +725,6 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
 		off_pu = 5;
 		break;
 	case SDMMC_1:
-	case SDMMC_3:
 		if (power == SDMMC_POWER_1_8)
 		{
 			off_pd = 123;
@@ -995,7 +994,7 @@ DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
 			if (!result)
 			{
 #ifdef ERROR_EXTRA_PRINTING
-				EPRINTFARGS("SDMMC: Unknown response %08X!", sdmmc->rsp[0]);
+				EPRINTF("SDMMC: Unknown response type!");
 #endif
 			}
 		}
@@ -1117,10 +1116,7 @@ static void _sdmmc_config_emmc(u32 id)
 	case SDMMC_4:
 		// Unset park for pads.
 		APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) &= 0xF8003FFF;
-		// Set default pad cfg.
-		APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) = (APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) & 0xFFFFC003) | 0x1040;
-
-		// Enabled schmitt trigger.
+		// Enable schmitt trigger.
 		APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) |= 1; // Enable Schmitt trigger.
 		break;
 	}
@@ -1130,7 +1126,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int a
 {
 	const u32 trim_values[] = { 2, 8, 3, 8 };

-	if (id > SDMMC_4)
+	if (id > SDMMC_4 || id == SDMMC_3)
 		return 0;

 	memset(sdmmc, 0, sizeof(sdmmc_t));
--- a/bdk/usb/usb_descriptors.h
+++ b/bdk/usb/usb_descriptors.h
@@ -75,7 +75,7 @@ typedef struct _usb_dev_descr_t
 	u8  bNumConfigs;     // Number of possible configuration.
 } __attribute__((packed)) usb_dev_descr_t;

-/* Device Qualigier descriptor structure */
+/* Device Qualifier descriptor structure */
 typedef struct _usb_dev_qual_descr_t
 {
 	u8  bLength;          // Size of this descriptor in bytes.
--- a/bdk/usb/usb_t210.h
+++ b/bdk/usb/usb_t210.h
@@ -1,5 +1,5 @@
 /*
- * USB driver for Tegra X1
+ * Enhanced USB (EHCI) device driver for Tegra X1
 *
 * Copyright (c) 2019 CTCaer
 *
--- a/bdk/usb/usbd.c
+++ b/bdk/usb/usbd.c
@@ -1,5 +1,5 @@
 /*
- * USB Device driver for Tegra X1
+ * Enhanced USB (EHCI) Device driver for Tegra X1
 *
 * Copyright (c) 2019 CTCaer
 *
@@ -312,7 +312,7 @@ static void _usb_charger_detect()
 		gpio_config(GPIO_PORT_V, GPIO_PIN_3, GPIO_MODE_GPIO);

 		// Configure charger pin.
-		PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) &=
+		PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN1) &=
 			~(PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_MASK);
 		gpio_config(GPIO_PORT_CC, GPIO_PIN_5, GPIO_MODE_GPIO);
 		gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_5, GPIO_OUTPUT_ENABLE);
@@ -335,10 +335,10 @@ int usb_device_init()
 		return 0;

 	// Configure PLLU.
-	CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) = CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) | 0x20000000; // Disable reference clock.
-	u32 pllu_cfg = (((((CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) >> 8 << 8) | 2) & 0xFFFF00FF) | ((0x19 << 8) & 0xFFFF)) & 0xFFE0FFFF) | (1<< 16) | 0x1000000;
+	CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) |= (1 << 29); // Disable reference clock.
+	u32 pllu_cfg = (((((CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) >> 8 << 8) | 2) & 0xFFFF00FF) | ((0x19 << 8) & 0xFFFF)) & 0xFFE0FFFF) | (1 << 16) | (1 << 24);
 	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg;
-	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | 0x40000000; // Enable.
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | (1 << 30); // Enable.

 	// Wait for PLL to stabilize.
 	u32 timeout = (u32)TMR(TIMERUS_CNTR_1US) + 1300;
@@ -348,7 +348,7 @@ int usb_device_init()
 	usleep(10);

 	// Enable PLLU USB/HSIC/ICUSB/48M.
-	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) | 0x2600000 | 0x800000;
+	CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) |= 0x2E00000;

 	// Enable USBD clock.
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD);
@@ -1175,17 +1175,17 @@ static int _usbd_handle_ep0_control_transfer()

 	switch (_bmRequestType)
 	{
-	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_RECIPIENT_DEVICE    | USB_SETUP_TYPE_STANDARD):
+	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE):
 		ret = _usbd_handle_set_request(&ep_stall);
 		break;

-	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_RECIPIENT_INTERFACE | USB_SETUP_TYPE_STANDARD):
+	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_INTERFACE):
 		ret = _usbd_ep_ack(USB_EP_CTRL_IN);
 		if (!ret)
 			usbd_otg->interface = _wValue;
 		break;

-	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_RECIPIENT_ENDPOINT  | USB_SETUP_TYPE_STANDARD):
+	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_ENDPOINT):
 		switch (_bRequest)
 		{
 		case USB_REQUEST_CLEAR_FEATURE:
@@ -1227,10 +1227,12 @@ static int _usbd_handle_ep0_control_transfer()
 			break;
 		}
 		break;
-	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_RECIPIENT_INTERFACE | USB_SETUP_TYPE_CLASS):
+
+	case (USB_SETUP_HOST_TO_DEVICE | USB_SETUP_TYPE_CLASS    | USB_SETUP_RECIPIENT_INTERFACE):
 		_usbd_handle_get_class_request(&transmit_data, descriptor, &size, &ep_stall);
 		break;
-	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_RECIPIENT_DEVICE    | USB_SETUP_TYPE_STANDARD):
+
+	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_DEVICE):
 		switch (_bRequest)
 		{
 		case USB_REQUEST_GET_STATUS:
@@ -1253,7 +1255,7 @@ static int _usbd_handle_ep0_control_transfer()
 		}
 		break;

-	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_RECIPIENT_INTERFACE | USB_SETUP_TYPE_STANDARD):
+	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_INTERFACE):
 		if (_bRequest == USB_REQUEST_GET_INTERFACE)
 		{
 			descriptor = (void *)&usbd_otg->interface;
@@ -1287,7 +1289,7 @@ static int _usbd_handle_ep0_control_transfer()
 		transmit_data = 1;
 		break;

-	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_RECIPIENT_ENDPOINT  | USB_SETUP_TYPE_STANDARD):
+	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_ENDPOINT):
 		if (_bRequest == USB_REQUEST_GET_STATUS)
 		{
 			int ep_req;
@@ -1324,14 +1326,15 @@ static int _usbd_handle_ep0_control_transfer()
 			_usbd_stall_reset_ep1(3, USB_EP_CFG_STALL);
 		break;

-	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_RECIPIENT_INTERFACE | USB_SETUP_TYPE_CLASS):
+	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_TYPE_CLASS    | USB_SETUP_RECIPIENT_INTERFACE):
 		memset(descriptor, 0, _wLength);

 		_usbd_handle_get_class_request(&transmit_data, descriptor, &size, &ep_stall);
 		size = _wLength;
 		break;
-	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_RECIPIENT_INTERFACE | USB_SETUP_TYPE_VENDOR):
-	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_RECIPIENT_DEVICE    | USB_SETUP_TYPE_VENDOR):
+
+	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_TYPE_VENDOR   | USB_SETUP_RECIPIENT_INTERFACE):
+	case (USB_SETUP_DEVICE_TO_HOST | USB_SETUP_TYPE_VENDOR   | USB_SETUP_RECIPIENT_DEVICE):
 		if (_bRequest == USB_REQUEST_GET_MS_DESCRIPTOR)
 		{
 			switch (_wIndex)
--- a/bdk/usb/usbd.h
+++ b/bdk/usb/usbd.h
@@ -1,5 +1,5 @@
 /*
- * USB Device driver for Tegra X1
+ * Enhanced USB (EHCI) Device driver for Tegra X1
 *
 * Copyright (c) 2019 CTCaer
 *
--- a/bdk/utils/util.h
+++ b/bdk/utils/util.h
@@ -35,7 +35,7 @@ typedef enum
 	ERR_LIBSYS_MTC = (1 << 2),
 	ERR_SD_BOOT_EN = (1 << 3),
 	ERR_L4T_KERNEL = (1 << 24),
-	ERR_EXCEPT_ENB = (1 << 31),
+	ERR_EXCEPTION  = (1 << 31),
 } hekate_errors_t;

 #define byte_swap_32(num) (((num >> 24) & 0xff) | ((num << 8) & 0xff0000) | \
--- a/bootloader/config.c
+++ b/bootloader/config.c
@@ -42,8 +42,7 @@ void set_default_configuration()
 	h_cfg.autohosoff = 0;
 	h_cfg.autonogc = 1;
 	h_cfg.updater2p = 0;
-	h_cfg.brand = NULL;
-	h_cfg.tagline = NULL;
+	h_cfg.bootprotect = 0;
 	h_cfg.errors = 0;
 	h_cfg.eks = NULL;
 	h_cfg.sept_run = EMC(EMC_SCRATCH0) & EMC_SEPT_RUN;
@@ -107,16 +106,9 @@ int create_config_entry()
 	f_puts("\nupdater2p=", &fp);
 	itoa(h_cfg.updater2p, lbuf, 10);
 	f_puts(lbuf, &fp);
-	if (h_cfg.brand)
-	{
-		f_puts("\nbrand=", &fp);
-		f_puts(h_cfg.brand, &fp);
-	}
-	if (h_cfg.tagline)
-	{
-		f_puts("\ntagline=", &fp);
-		f_puts(h_cfg.tagline, &fp);
-	}
+	f_puts("\nbootprotect=", &fp);
+	itoa(h_cfg.bootprotect, lbuf, 10);
+	f_puts(lbuf, &fp);
 	f_puts("\n", &fp);

 	if (mainIniFound)
--- a/bootloader/config.h
+++ b/bootloader/config.h
@@ -30,8 +30,7 @@ typedef struct _hekate_config
 	u32 autohosoff;
 	u32 autonogc;
 	u32 updater2p;
-	char *brand;
-	char *tagline;
+	u32 bootprotect;
 	// Global temporary config.
 	bool se_keygen_done;
 	bool sept_run;
--- a/bootloader/hos/fss.c
+++ b/bootloader/hos/fss.c
@@ -165,7 +165,7 @@ int parse_fss(launch_ctxt_t *ctxt, const char *path, fss0_sept_t *sept_ctxt)
 				continue;

 			// If content is experimental and experimental flag is not enabled, skip it.
-			if ((curr_fss_cnt[i].flags0 & CNT_FLAG0_EXPERIMENTAL) && !ctxt->fss0_enable_experimental)
+			if ((curr_fss_cnt[i].flags0 & CNT_FLAG0_EXPERIMENTAL) && !ctxt->fss0_experimental)
 				continue;

 			// Parse content.
@@ -190,6 +190,10 @@ int parse_fss(launch_ctxt_t *ctxt, const char *path, fss0_sept_t *sept_ctxt)
 					ctxt->warmboot_size = curr_fss_cnt[i].size;
 					ctxt->warmboot = content;
 					break;
+				case CNT_TYPE_KRN:
+					ctxt->kernel_size = curr_fss_cnt[i].size;
+					ctxt->kernel = content;
+					break;
 				default:
 					continue;
 				}
--- a/bootloader/hos/hos.c
+++ b/bootloader/hos/hos.c
@@ -269,6 +269,10 @@ void hos_eks_save(u32 kb)
 			u8 *keys = (u8 *)calloc(0x1000, 1);
 			se_get_aes_keys(keys + 0x800, keys, 0x10);

+			// Set SBK back.
+			if (FUSE(FUSE_PRIVATE_KEY0) == 0xFFFFFFFF)
+				se_aes_key_set(14, keys + 14 * 0x10, 0x10);
+
 			// Set magic and personalized info.
 			h_cfg.eks->magic = HOS_EKS_MAGIC;
 			h_cfg.eks->enabled[key_idx] = kb;
@@ -854,13 +858,11 @@ int hos_launch(ini_sec_t *cfg)
 	if (!pkg2_hdr)
 	{
 		_hos_crit_error("Pkg2 decryption failed!");
-		if (kb >= KB_FIRMWARE_VERSION_700)
-		{
-			EPRINTF("Is Sept updated?");
+		EPRINTFARGS("Is hekate%s updated?", kb >= KB_FIRMWARE_VERSION_700 ? " or Sept" : "");

-			// Clear EKS slot, in case something went wrong with sept keygen.
+		// Clear EKS slot, in case something went wrong with sept keygen.
+		if (kb >= KB_FIRMWARE_VERSION_700)
 			hos_eks_clear(kb);
-		}
 		goto error;
 	}
 	else if (kb >= KB_FIRMWARE_VERSION_700)
@@ -949,11 +951,14 @@ int hos_launch(ini_sec_t *cfg)
 	{
 		EHPRINTFARGS("Failed to apply '%s'!", unappliedPatch);

-		gfx_puts("\nPress POWER to continue.\nPress VOL to go to the menu.\n");
-		display_backlight_brightness(h_cfg.backlight, 1000);
+		bool emmc_patch_failed = !strcmp(unappliedPatch, "emummc");
+		if (!emmc_patch_failed)
+		{
+			gfx_puts("\nPress POWER to continue.\nPress VOL to go to the menu.\n");
+			display_backlight_brightness(h_cfg.backlight, 1000);
+		}

-		u32 btn = btn_wait();
-		if (!(btn & BTN_POWER))
+		if (emmc_patch_failed || !(btn_wait() & BTN_POWER))
 		{
 			_free_launch_components(&ctxt);
 			goto error; // MUST stop here, because if user requests 'nogc' but it's not applied, their GC controller gets updated!
@@ -961,16 +966,12 @@ int hos_launch(ini_sec_t *cfg)
 	}

 	// Rebuild and encrypt package2.
-	pkg2_build_encrypt((void *)PKG2_LOAD_ADDR, ctxt.kernel, ctxt.kernel_size, &kip1_info, ctxt.new_pkg2, kb);
+	pkg2_build_encrypt((void *)PKG2_LOAD_ADDR, &ctxt, &kip1_info);

 	gfx_puts("Rebuilt & loaded pkg2\n");

 	gfx_printf("\n%kBooting...%k\n", 0xFF96FF00, 0xFFCCCCCC);

-	// Clear pkg1/pkg2 keys.
-	se_aes_key_clear(8);
-	se_aes_key_clear(11);
-
 	// Set initial mailbox values.
 	int bootStateDramPkg2 = 0;
 	int bootStatePkg2Continue = 0;
@@ -981,6 +982,10 @@ int hos_launch(ini_sec_t *cfg)
 	else if (kb == KB_FIRMWARE_VERSION_301)
 		PMC(APBDEV_PMC_SECURE_SCRATCH32) = 0x104; // Warmboot 3.0.1/.2 PA address id.

+	// Clear pkg1/pkg2 keys.
+	se_aes_key_clear(8);
+	se_aes_key_clear(11);
+
 	// Finalize per firmware key access. Skip access control if new exosphere.
 	switch (kb | (exo_new << 7))
 	{
--- a/bootloader/hos/hos.h
+++ b/bootloader/hos/hos.h
@@ -97,6 +97,7 @@ typedef struct _launch_ctxt_t

 	void  *kernel;
 	u32    kernel_size;
+
 	link_t kip1_list;
 	char*  kip1_patches;

@@ -105,7 +106,7 @@ typedef struct _launch_ctxt_t
 	bool debugmode;
 	bool stock;
 	bool atmosphere;
-	bool fss0_enable_experimental;
+	bool fss0_experimental;
 	bool emummc_forced;

 	exo_ctxt_t exo_ctx;
--- a/bootloader/hos/hos_config.c
+++ b/bootloader/hos/hos_config.c
@@ -253,7 +253,7 @@ static int _config_fss(launch_ctxt_t *ctxt, const char *value)
 	{
 		if (!strcmp("fss0experimental", kv->key))
 		{
-			ctxt->fss0_enable_experimental = *kv->val == '1';
+			ctxt->fss0_experimental = *kv->val == '1';
 			break;
 		}
 	}
--- a/bootloader/hos/pkg2.c
+++ b/bootloader/hos/pkg2.c
@@ -1410,9 +1410,16 @@ DPRINTF("adding kip1 '%s' @ %08X (%08X)\n", ki->kip1->name, (u32)ki->kip1, ki->s
 	return ini1_size;
 }

-void pkg2_build_encrypt(void *dst, void *kernel, u32 kernel_size, link_t *kips_info, bool new_pkg2, u8 kb)
+void pkg2_build_encrypt(void *dst, void *hos_ctxt, link_t *kips_info)
 {
 	u8 *pdst = (u8 *)dst;
+	launch_ctxt_t * ctxt = (launch_ctxt_t *)hos_ctxt;
+	u32 kernel_size = ctxt->kernel_size;
+	bool is_meso = *(u32 *)(ctxt->kernel + 4) == ATM_MESOSPHERE;
+
+	// Force new Package2 if Mesosphere.
+	if (is_meso)
+		ctxt->new_pkg2 = true;

 	// Signature.
 	memset(pdst, 0, 0x100);
@@ -1427,23 +1434,25 @@ void pkg2_build_encrypt(void *dst, void *kernel, u32 kernel_size, link_t *kips_i
 	hdr->bl_ver = 0;
 	hdr->pkg2_ver = 0xFF;

-	if (!new_pkg2)
+	if (!ctxt->new_pkg2)
 		hdr->base = 0x10000000;
 	else
 		hdr->base = 0x60000;
-DPRINTF("kernel @ %08X (%08X)\n", (u32)kernel, kernel_size);
+DPRINTF("%s @ %08X (%08X)\n", is_meso ? "Mesosphere": "kernel",(u32)ctxt->kernel, kernel_size);

 	pdst += sizeof(pkg2_hdr_t);

 	// Kernel.
-	memcpy(pdst, kernel, kernel_size);
-	if (!new_pkg2)
+	memcpy(pdst, ctxt->kernel, kernel_size);
+	if (!ctxt->new_pkg2)
 		hdr->sec_off[PKG2_SEC_KERNEL] = 0x10000000;
 	else
 	{
 		// Set new INI1 offset to kernel.
-		*(u32 *)(pdst + pkg2_newkern_ini1_val) = kernel_size;
-		kernel_size += _pkg2_ini1_build(pdst + kernel_size, hdr, kips_info, new_pkg2);
+		*(u32 *)(pdst + (is_meso ? 8 : pkg2_newkern_ini1_val)) = kernel_size;
+
+		// Build INI1 for new Package2.
+		kernel_size += _pkg2_ini1_build(pdst + kernel_size, hdr, kips_info, ctxt->new_pkg2);
 		hdr->sec_off[PKG2_SEC_KERNEL] = 0x60000;
 	}
 	hdr->sec_size[PKG2_SEC_KERNEL] = kernel_size;
@@ -1451,10 +1460,10 @@ DPRINTF("kernel @ %08X (%08X)\n", (u32)kernel, kernel_size);
 	pdst += kernel_size;
 DPRINTF("kernel encrypted\n");

-	// INI1.
+	/// Build INI1 for old Package2.
 	u32 ini1_size = 0;
-	if (!new_pkg2)
-		ini1_size = _pkg2_ini1_build(pdst, hdr, kips_info, new_pkg2);
+	if (!ctxt->new_pkg2)
+		ini1_size = _pkg2_ini1_build(pdst, hdr, kips_info, false);
 DPRINTF("INI1 encrypted\n");

 	// Calculate SHA256 over encrypted Kernel and INI1.
@@ -1466,7 +1475,7 @@ DPRINTF("INI1 encrypted\n");
 		(void *)pk2_hash_data, hdr->sec_size[PKG2_SEC_INI1]);

 	//Encrypt header.
-	u8 key_ver = kb ? kb + 1 : 0;
+	u8 key_ver = ctxt->pkg1_id->kb ? ctxt->pkg1_id->kb + 1 : 0;
 	*(u32 *)hdr->ctr = 0x100 + sizeof(pkg2_hdr_t) + kernel_size + ini1_size;
 	hdr->ctr[4] = key_ver;
 	se_aes_crypt_ctr(pkg2_keyslot, hdr, sizeof(pkg2_hdr_t), hdr, sizeof(pkg2_hdr_t), hdr);
--- a/bootloader/hos/pkg2.h
+++ b/bootloader/hos/pkg2.h
@@ -30,6 +30,8 @@
 #define PKG2_NEWKERN_GET_INI1_HEURISTIC 0xD2800015 // Offset of OP + 12 is the INI1 offset.
 #define PKG2_NEWKERN_START 0x800

+#define ATM_MESOSPHERE 0x3053534D
+
 extern u32 pkg2_newkern_ini1_val;
 extern u32 pkg2_newkern_ini1_start;
 extern u32 pkg2_newkern_ini1_end;
@@ -155,6 +157,6 @@ const char* pkg2_patch_kips(link_t *info, char* patchNames);

 const pkg2_kernel_id_t *pkg2_identify(u8 *hash);
 pkg2_hdr_t *pkg2_decrypt(void *data, u8 kb);
-void pkg2_build_encrypt(void *dst, void *kernel, u32 kernel_size, link_t *kips_info, bool new_pkg2, u8 kb);
+void pkg2_build_encrypt(void *dst, void *hos_ctxt, link_t *kips_info);

 #endif
--- a/bootloader/hos/secmon_exo.c
+++ b/bootloader/hos/secmon_exo.c
@@ -344,6 +344,8 @@ static const char *get_error_desc(u32 error_desc)
 		return "SYS";   // System Error.
 	case 0x301:
 		return "SVC";   // Bad arguments or unimplemented SVC.
+	case 0xF00:
+		return "KRNL";  // Kernel panic.
 	case 0xFFD:
 		return "SO";    // Stack Overflow.
 	case 0xFFE:
--- a/bootloader/main.c
+++ b/bootloader/main.c
@@ -293,8 +293,15 @@ void auto_launch_update()
 		EMC(EMC_SCRATCH0) &= ~EMC_HEKA_UPD;
 	else if (sd_mount())
 	{
+		// Check if update.bin exists and is newer and launch it. Otherwise create it.
 		if (!f_stat("bootloader/update.bin", NULL))
 			launch_payload("bootloader/update.bin", true);
+		else
+		{
+			u8 *buf = calloc(0x200, 1);
+			is_ipl_updated(buf, "bootloader/update.bin", true);
+			free(buf);
+		}
 	}
 }

@@ -767,6 +774,18 @@ static ini_sec_t *get_ini_sec_from_id(ini_sec_t *ini_sec, char **bootlogoCustomE
 	return cfg_sec;
 }

+static void _bootloader_corruption_protect()
+{
+	FILINFO fno;
+	if (!f_stat("bootloader", &fno))
+	{
+		if (!h_cfg.bootprotect && (fno.fattrib & AM_ARC))
+			f_chmod("bootloader", 0, AM_ARC);
+		else if (h_cfg.bootprotect && !(fno.fattrib & AM_ARC))
+			f_chmod("bootloader", AM_ARC, AM_ARC);
+	}
+}
+
 static void _auto_launch_firmware()
 {
 	if(b_cfg.extra_cfg & (EXTRA_CFG_NYX_DUMP | EXTRA_CFG_NYX_BIS))
@@ -775,8 +794,6 @@ static void _auto_launch_firmware()
 			EMC(EMC_SCRATCH0) |= EMC_HEKA_UPD;
 		check_sept(NULL);
 	}
-	else if (b_cfg.extra_cfg & EXTRA_CFG_NYX_UMS)
-		EMC(EMC_SCRATCH0) |= EMC_HEKA_UPD;

 	if (!h_cfg.sept_run)
 		auto_launch_update();
@@ -845,16 +862,8 @@ static void _auto_launch_firmware()
 								h_cfg.autonogc = atoi(kv->val);
 							else if (!strcmp("updater2p", kv->key))
 								h_cfg.updater2p = atoi(kv->val);
-							else if (!strcmp("brand", kv->key))
-							{
-								h_cfg.brand = malloc(strlen(kv->val) + 1);
-								strcpy(h_cfg.brand, kv->val);
-							}
-							else if (!strcmp("tagline", kv->key))
-							{
-								h_cfg.tagline = malloc(strlen(kv->val) + 1);
-								strcpy(h_cfg.tagline, kv->val);
-							}
+							else if (!strcmp("bootprotect", kv->key))
+								h_cfg.bootprotect = atoi(kv->val);
 						}
 						boot_entry_id++;

@@ -870,6 +879,9 @@ static void _auto_launch_firmware()
 							b_cfg.autoboot_list = h_cfg.autoboot_list;
 						}

+						// Apply bootloader protection against corruption.
+						_bootloader_corruption_protect();
+
 						continue;
 					}

@@ -1144,7 +1156,7 @@ static void _show_errors()
 	u32 *excp_lr = (u32 *)EXCP_LR_ADDR;

 	if (*excp_enabled == EXCP_MAGIC)
-		h_cfg.errors |= ERR_EXCEPT_ENB;
+		h_cfg.errors |= ERR_EXCEPTION;

 	//! FIXME: Find a better way to identify if that scratch has proper data.
 	if (0 && PMC(APBDEV_PMC_SCRATCH37) & PMC_SCRATCH37_KERNEL_PANIC_FLAG)
@@ -1161,23 +1173,23 @@ static void _show_errors()
 		display_backlight_brightness(150, 1000);

 		if (h_cfg.errors & ERR_SD_BOOT_EN)
-			WPRINTF("Failed to init SD!\n");
+			WPRINTF("Failed to mount SD!\n");

 		if (h_cfg.errors & ERR_LIBSYS_LP0)
 			WPRINTF("Missing LP0 (sleep mode) lib!\n");
 		if (h_cfg.errors & ERR_LIBSYS_MTC)
 			WPRINTF("Missing or old Minerva lib!\n");

-		if (h_cfg.errors & ~(ERR_EXCEPT_ENB | ERR_L4T_KERNEL))
+		if (h_cfg.errors & (ERR_LIBSYS_LP0 | ERR_LIBSYS_MTC))
 			WPRINTF("\nUpdate bootloader folder!\n\n");

-		if (h_cfg.errors & ERR_EXCEPT_ENB)
+		if (h_cfg.errors & ERR_EXCEPTION)
 		{
 			WPRINTFARGS("An exception occurred (LR %08X):\n", *excp_lr);
 			switch (*excp_type)
 			{
 			case EXCP_TYPE_RESET:
-				WPRINTF("RST");
+				WPRINTF("RESET");
 				break;
 			case EXCP_TYPE_UNDEF:
 				WPRINTF("UNDEF");
@@ -1195,7 +1207,7 @@ static void _show_errors()
 			*excp_enabled = 0;
 		}

-		if (h_cfg.errors & ERR_L4T_KERNEL)
+		if (0 && h_cfg.errors & ERR_L4T_KERNEL)
 		{
 			WPRINTF("Panic occurred while running L4T.\n");
 			if (!sd_save_to_file((void *)PSTORE_ADDR, PSTORE_SZ, "L4T_panic.bin"))
@@ -1480,7 +1492,7 @@ ment_t ment_top[] = {
 	MDEF_END()
 };

-menu_t menu_top = { ment_top, "hekate - CTCaer mod v5.3.3", 0, 0 };
+menu_t menu_top = { ment_top, "hekate - CTCaer mod v5.3.4", 0, 0 };

 extern void pivot_stack(u32 stack_top);

--- a/nyx/Makefile
+++ b/nyx/Makefile
@@ -37,7 +37,7 @@ OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
 	fuse.o kfuse.o \
 	mc.o sdram.o minerva.o ramdisk.o \
 	sdmmc.o sdmmc_driver.o nx_emmc.o nx_emmc_bis.o nx_sd.o \
-	bm92t30_stub.o bq24193.o max17050.o max7762x.o max77620-rtc.o regulator_5v.o \
+	bm92t36.o bq24193.o max17050.o max7762x.o max77620-rtc.o regulator_5v.o \
 	touch.o joycon.o tmp451.o fan.o \
 	usbd.o usb_gadget_ums.o usb_gadget_hid.o \
 	hw_init.o \
--- a/nyx/nyx_gui/config.c
+++ b/nyx/nyx_gui/config.c
@@ -42,13 +42,13 @@ void set_default_configuration()
 	h_cfg.autohosoff = 0;
 	h_cfg.autonogc = 1;
 	h_cfg.updater2p = 0;
-	h_cfg.brand = NULL;
-	h_cfg.tagline = NULL;
+	h_cfg.bootprotect = 0;
 	h_cfg.errors = 0;
 	h_cfg.eks = NULL;
 	h_cfg.sept_run = EMC(EMC_SCRATCH0) & EMC_SEPT_RUN;
 	h_cfg.aes_slots_new = false;
 	h_cfg.rcm_patched = fuse_check_patched_rcm();
+	h_cfg.sbk_set = FUSE(FUSE_PRIVATE_KEY0) == 0xFFFFFFFF;
 	h_cfg.emummc_force_disable = false;

 	sd_power_cycle_time_start = 0;
@@ -61,6 +61,7 @@ void set_nyx_default_configuration()
 	n_cfg.home_screen = 0;
 	n_cfg.verification = 1;
 	n_cfg.ums_emmc_rw = 0;
+	n_cfg.jc_disable = 0;
 }

 int create_config_entry()
@@ -118,16 +119,9 @@ int create_config_entry()
 	f_puts("\nupdater2p=", &fp);
 	itoa(h_cfg.updater2p, lbuf, 10);
 	f_puts(lbuf, &fp);
-	if (h_cfg.brand)
-	{
-		f_puts("\nbrand=", &fp);
-		f_puts(h_cfg.brand, &fp);
-	}
-	if (h_cfg.tagline)
-	{
-		f_puts("\ntagline=", &fp);
-		f_puts(h_cfg.tagline, &fp);
-	}
+	f_puts("\nbootprotect=", &fp);
+	itoa(h_cfg.bootprotect, lbuf, 10);
+	f_puts(lbuf, &fp);
 	f_puts("\n", &fp);

 	if (mainIniFound)
@@ -206,6 +200,9 @@ int create_nyx_config_entry()
 	f_puts("\numsemmcrw=", &fp);
 	itoa(n_cfg.ums_emmc_rw, lbuf, 10);
 	f_puts(lbuf, &fp);
+	f_puts("\njcdisable=", &fp);
+	itoa(n_cfg.jc_disable, lbuf, 10);
+	f_puts(lbuf, &fp);
 	f_puts("\n", &fp);

 	f_close(&fp);
--- a/nyx/nyx_gui/config.h
+++ b/nyx/nyx_gui/config.h
@@ -30,14 +30,14 @@ typedef struct _hekate_config
 	u32 autohosoff;
 	u32 autonogc;
 	u32 updater2p;
-	char *brand;
-	char *tagline;
+	u32 bootprotect;
 	// Global temporary config.
 	bool se_keygen_done;
 	bool sept_run;
 	bool aes_slots_new;
 	bool emummc_force_disable;
 	bool rcm_patched;
+	bool sbk_set;
 	u32  errors;
 	hos_eks_mbr_t *eks;
 } hekate_config;
@@ -49,6 +49,7 @@ typedef struct _nyx_config
 	u32 home_screen;
 	u32 verification;
 	u32 ums_emmc_rw;
+	u32 jc_disable;
 } nyx_config;

 void set_default_configuration();
--- a/nyx/nyx_gui/frontend/gui.c
+++ b/nyx/nyx_gui/frontend/gui.c
@@ -2234,8 +2234,11 @@ void nyx_load_and_run()
 	lv_disp_drv_register(&disp_drv);

 	// Initialize Joy-Con.
-	lv_task_t *task_jc_init_hw = lv_task_create(jc_init_hw, LV_TASK_ONESHOT, LV_TASK_PRIO_LOWEST, NULL);
-	lv_task_once(task_jc_init_hw);
+	if (!n_cfg.jc_disable)
+	{
+		lv_task_t *task_jc_init_hw = lv_task_create(jc_init_hw, LV_TASK_ONESHOT, LV_TASK_PRIO_LOWEST, NULL);
+		lv_task_once(task_jc_init_hw);
+	}
 	lv_indev_drv_t indev_drv_jc;
 	lv_indev_drv_init(&indev_drv_jc);
 	indev_drv_jc.type = LV_INDEV_TYPE_POINTER;
--- a/nyx/nyx_gui/frontend/gui_info.c
+++ b/nyx/nyx_gui/frontend/gui_info.c
@@ -28,7 +28,7 @@
 #include <mem/heap.h>
 #include <mem/sdram.h>
 #include <mem/smmu.h>
-#include <power/bm92t30_stub.h>
+#include <power/bm92t36.h>
 #include <power/bq24193.h>
 #include <power/max17050.h>
 #include <sec/se.h>
@@ -646,32 +646,32 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn)
 	switch ((ram_density.dev0_ch0 & 0x3C) >> 2)
 	{
 	case 2:
-		strcat(txt_buf, "4x512MB");
+		strcat(txt_buf, " x 512MB");
 		break;
 	case 3:
-		strcat(txt_buf, "4x768MB");
+		strcat(txt_buf, " x 768MB");
 		break;
 	case 4:
-		strcat(txt_buf, "4x1GB");
+		strcat(txt_buf, " x 1GB");
 		break;
 	default:
-		strcat(txt_buf, "4xUnk");
+		strcat(txt_buf, " x Unk");
 		break;
 	}
 	s_printf(txt_buf + strlen(txt_buf), " (%d) #FF8000 |# ", (ram_density.dev0_ch0 & 0x3C) >> 2);
 	switch ((ram_density.dev1_ch0 & 0x3C) >> 2)
 	{
 	case 2:
-		strcat(txt_buf, "4x512MB");
+		strcat(txt_buf, " x 512MB");
 		break;
 	case 3:
-		strcat(txt_buf, "4x768MB");
+		strcat(txt_buf, " x 768MB");
 		break;
 	case 4:
-		strcat(txt_buf, "4x1GB");
+		strcat(txt_buf, " x 1GB");
 		break;
 	default:
-		strcat(txt_buf, "2xUnk");
+		strcat(txt_buf, " x Unk");
 		break;
 	}
 	s_printf(txt_buf + strlen(txt_buf), " (%d)\n\n", (ram_density.dev1_ch0 & 0x3C) >> 2);
@@ -1014,7 +1014,7 @@ static lv_res_t _create_mbox_benchmark(bool sd_bench)

 	char *txt_buf = (char *)malloc(0x1000);

-	s_printf(txt_buf, "#FF8000 %s Benchmark#\n[3 x %s raw reads. Cancel: VOL- & VOL+]\n",
+	s_printf(txt_buf, "#FF8000 %s Benchmark#\n[3 x %s raw reads] Abort: VOL- & VOL+\n",
 		sd_bench ? "SD Card" : "eMMC", sd_bench ? "2GB" : "8GB");

 	lv_mbox_set_text(mbox, txt_buf);
@@ -1462,9 +1462,10 @@ static lv_res_t _create_window_sdcard_info_status(lv_obj_t *btn)

 		lv_obj_t * lb_val3 = lv_label_create(val3, lb_desc);

-		s_printf(txt_buf, "\n%s\n%d KiB\n%d MiB",
+		s_printf(txt_buf, "\n%s\n%d %s\n%d MiB",
 			sd_fs.fs_type == FS_EXFAT ? ("exFAT  "SYMBOL_SHRK) : ("FAT32"),
 			(sd_fs.csize > 1) ? (sd_fs.csize >> 1) : 512,
+			(sd_fs.csize > 1) ? "KiB" : "B",
 			sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF);

 		lv_label_set_text(lb_val3, txt_buf);
@@ -1688,27 +1689,31 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn)

 	bool inserted;
 	u32 wattage = 0;
-	u32 max_voltage = 5;
 	usb_pd_objects_t usb_pd;
-	bm92t30_get_charger_type(&inserted, &usb_pd);
+	bm92t36_get_sink_info(&inserted, &usb_pd);
 	strcat(txt_buf, "\n\n\n");
 	strcat(txt_buf, inserted ? "Connected" : "Disconnected");

-	for (u32 i = 0; i < usb_pd.pdo_no; i++)
-		if (usb_pd.pdos[i].voltage <= 15)
-			max_voltage = usb_pd.pdos[i].voltage;
-
-	wattage = iinlim * max_voltage;
+	// Select 5V is no PD contract.
+	wattage = iinlim * (usb_pd.pdo_no ? usb_pd.selected_pdo.voltage : 5);

 	s_printf(txt_buf + strlen(txt_buf), "\n%d.%d W", wattage / 1000, (wattage % 1000) / 100);

 	if (!usb_pd.pdo_no)
 		strcat(txt_buf, "\nNon PD");

+	// Limit to 5 profiles so it can fit.
+	usb_pd.pdo_no = MIN(usb_pd.pdo_no, 5);
+
 	for (u32 i = 0; i < usb_pd.pdo_no; i++)
 	{
-		s_printf(txt_buf + strlen(txt_buf), "\n%d mA, %2d V",
-			usb_pd.pdos[i].amperage, usb_pd.pdos[i].voltage);
+		bool selected =
+			usb_pd.pdos[i].amperage == usb_pd.selected_pdo.amperage &&
+			usb_pd.pdos[i].voltage == usb_pd.selected_pdo.voltage;
+		s_printf(txt_buf + strlen(txt_buf), "\n%s%d mA, %2d V%s",
+			selected ? "#D4FF00 " : "",
+			usb_pd.pdos[i].amperage, usb_pd.pdos[i].voltage,
+			selected ? "#" : "");
 	}

 	lv_label_set_text(lb_val2, txt_buf);
--- a/nyx/nyx_gui/frontend/gui_options.c
+++ b/nyx/nyx_gui/frontend/gui_options.c
@@ -740,10 +740,20 @@ void first_time_clock_edit(void *param)
 static lv_res_t _joycon_info_dump_action(lv_obj_t * btn)
 {
 	FIL fp;
+	int error;
 	bool is_l_hos = false;
 	bool is_r_hos = false;
 	jc_gamepad_rpt_t *jc_pad = jc_get_bt_pairing_info(&is_l_hos, &is_r_hos);

+	char *data = (char *)malloc(0x4000);
+	char *txt_buf = (char *)malloc(0x1000);
+
+	if (!jc_pad)
+	{
+		error = 255;
+		goto disabled;
+	}
+
 	// Count valid joycon.
 	u32 joycon_found = jc_pad->bt_conn_l.type ? 1 : 0;
 	if (jc_pad->bt_conn_r.type)
@@ -753,10 +763,7 @@ static lv_res_t _joycon_info_dump_action(lv_obj_t * btn)
 	jc_pad->bt_conn_l.type = is_l_hos ? jc_pad->bt_conn_l.type : 0;
 	jc_pad->bt_conn_r.type = is_r_hos ? jc_pad->bt_conn_r.type : 0;

-	int error = !sd_mount();
-
-	char *data = (char *)malloc(0x4000);
-	char *txt_buf = (char *)malloc(0x1000);
+	error = !sd_mount();

 	if (!error)
 	{
@@ -798,6 +805,7 @@ static lv_res_t _joycon_info_dump_action(lv_obj_t * btn)
 		sd_unmount();
 	}

+disabled:;
 	lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL);
 	lv_obj_set_style(dark_bg, &mbox_darken);
 	lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES);
--- a/nyx/nyx_gui/frontend/gui_tools_partition_manager.c
+++ b/nyx/nyx_gui/frontend/gui_tools_partition_manager.c
@@ -912,7 +912,7 @@ static lv_res_t _action_flash_android_data(lv_obj_t * btns, const char * txt)
 		lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES);

 		static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" };
-		static const char *mbox_btn_map2[] = { "\222Continue", "\222Cancel", "" };
+		static const char *mbox_btn_map2[] = { "\222Continue", "\222No", "" };
 		lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL);
 		lv_mbox_set_recolor_text(mbox, true);
 		lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6);
--- a/nyx/nyx_gui/hos/hos.c
+++ b/nyx/nyx_gui/hos/hos.c
@@ -214,6 +214,10 @@ void hos_eks_save(u32 kb)
 			u8 *keys = (u8 *)calloc(0x1000, 1);
 			se_get_aes_keys(keys + 0x800, keys, 0x10);

+			// Set SBK back.
+			if (h_cfg.sbk_set)
+				se_aes_key_set(14, keys + 14 * 0x10, 0x10);
+
 			// Set magic and personalized info.
 			h_cfg.eks->magic = HOS_EKS_MAGIC;
 			h_cfg.eks->enabled[key_idx] = kb;
@@ -659,15 +663,18 @@ void hos_bis_keys_clear()
 		se_aes_key_clear(i);

 	// Set SBK back.
-	u32 sbk[4] = {
+	if (!h_cfg.sbk_set)
+	{
+		u32 sbk[4] = {
 			FUSE(FUSE_PRIVATE_KEY0),
 			FUSE(FUSE_PRIVATE_KEY1),
 			FUSE(FUSE_PRIVATE_KEY2),
 			FUSE(FUSE_PRIVATE_KEY3)
 		};
-	// Set SBK to slot 14.
-	se_aes_key_set(14, sbk, 0x10);
+		// Set SBK to slot 14.
+		se_aes_key_set(14, sbk, 0x10);

-	// Lock SBK from being read.
-	se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
+		// Lock SBK from being read.
+		se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
+	}
 }
--- a/nyx/nyx_gui/nyx.c
+++ b/nyx/nyx_gui/nyx.c
@@ -241,10 +241,8 @@ void load_saved_configuration()
 						h_cfg.autonogc = atoi(kv->val);
 					else if (!strcmp("updater2p", kv->key))
 						h_cfg.updater2p = atoi(kv->val);
-					else if (!strcmp("brand", kv->key))
-						h_cfg.brand = kv->val;
-					else if (!strcmp("tagline", kv->key))
-						h_cfg.tagline = kv->val;
+					else if (!strcmp("bootprotect", kv->key))
+						h_cfg.bootprotect = atoi(kv->val);
 				}

 				break;
@@ -272,6 +270,8 @@ void load_saved_configuration()
 						n_cfg.verification = atoi(kv->val);
 					else if (!strcmp("umsemmcrw", kv->key))
 						n_cfg.ums_emmc_rw = atoi(kv->val) == 1;
+					else if (!strcmp("jcdisable", kv->key))
+						n_cfg.jc_disable = atoi(kv->val) == 1;
 				}

 				break;
@@ -307,7 +307,7 @@ static void _show_errors()
 		switch (*excp_type)
 		{
 		case EXCP_TYPE_RESET:
-			WPRINTF("RST");
+			WPRINTF("RESET");
 			break;
 		case EXCP_TYPE_UNDEF:
 			WPRINTF("UNDEF");
--- a/nyx/nyx_gui/storage/nx_sd.c
+++ b/nyx/nyx_gui/storage/nx_sd.c
@@ -174,7 +174,7 @@ bool sd_mount()

 static void _sd_deinit(bool deinit)
 {
-	if (sd_mode == SD_INIT_FAIL)
+	if (deinit && sd_mode == SD_INIT_FAIL)
 		sd_mode = SD_UHS_SDR104;

 	if (sd_init_done && sd_mounted)
Author	SHA1	Message	Date
CTCaer	5a6608dff4	Bump hekate to v5.3.4 and Nyx to v0.9.5	2020-10-27 21:28:06 +02:00
CTCaer	8f222fd0bd	main: Fix update.bin creation on first boot	2020-10-27 21:27:51 +02:00
CTCaer	1f5b371608	Refactor some names Additionally: - Do not retry to init sd if all modes failed in Nyx. - Do not try to read/write if sdmmc controller and card are not initialized.	2020-10-23 06:32:24 +03:00
CTCaer	ce156ab4e7	hos: Automate some eks and bis checks	2020-10-20 11:53:28 +03:00
CTCaer	94235dd005	bm92t30: Add proper info The driver will now show more charger supported profiles and will also show selected profile.	2020-10-20 10:42:57 +03:00
CTCaer	cb471162d2	i2c: Fix packet mode	2020-10-20 10:37:33 +03:00
CTCaer	9d1c0ce308	Create update.bin if missing This will allow l4t/Android to always use latest hekate in case of old r2p.	2020-10-20 10:34:33 +03:00
CTCaer	27b1f0e843	Various small fixes	2020-10-20 10:32:32 +03:00
CTCaer	dae7be8ec4	nyx: Allow disabling of Joycon Setting `jcdisable=1` in nyx.ini disables the usage of Joycon completely. This also disables the BT pairing data dumping tool.	2020-10-20 10:21:48 +03:00
CTCaer	2f5b52223c	config: Add bootloader protection `bootprotect=1` enables protection of the `bootloader` folder inside HOS. This disallows any reading/writing of the folder and its contents inside HOS, preventing any corruption of it. This of course has the side-effect of homebrew that depend on it (e.g. hekate Toolbox) to not work fully.	2020-10-20 10:16:12 +03:00
CTCaer	bf222290b8	hos: Add support for mesosphere The change adds support for mesosphere loading from fss0 or sd (kernel=).	2020-10-17 23:18:48 +03:00
CTCaer	d825be5eb2	hos: Tiny refactoring	2020-10-17 23:16:16 +03:00
CTCaer	9da0e0358b	Merge pull request #500 from AuroraWright/master hos: Prevent booting emummc with failed emummc patching	2020-10-17 23:02:34 +03:00
Aurora Wright	216d97aada	Push changes as requested	2020-10-17 21:11:21 +02:00
Aurora Wright	e3421fd44e	hos: Prevent sysmmc boot on emummc patch failure if emummc is forced	2020-10-14 19:37:36 +02:00