nyx: add OmniNX brand label and tab background fallback

Show hekate-pro | OmniNX pack on the home screen from manifest.ini via boot storage, and support background_etc.bmp for non-Home tabs.
return value fix
2026-07-09 22:26:32 +02:00 · 2026-06-18 02:21:45 +02:00 · 2026-06-17 06:43:23 +02:00 · 2026-06-17 06:41:48 +02:00 · 2026-06-17 06:41:48 +02:00 · 2026-06-17 06:36:14 +02:00
300 changed files with 62319 additions and 31045 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,9 @@
 .vscode
 build/*
 output/*
+loader/payload_00.h
+loader/payload_01.h
+tools/bin2c/bin2c
+tools/bin2c/bin2c.exe
+tools/lz/lz77
+tools/lz/lz77.exe
--- a/165
+++ b/165
@@ -14,48 +14,41 @@ include ./Versions.inc

 TARGET := hekate
 BUILDDIR := build
+BUILDTDIR := build/$(TARGET)
 OUTPUTDIR := output
 SOURCEDIR = bootloader
 BDKDIR := bdk
 BDKINC := -I./$(BDKDIR)
 VPATH = $(dir ./$(SOURCEDIR)/) $(dir $(wildcard ./$(SOURCEDIR)/*/)) $(dir $(wildcard ./$(SOURCEDIR)/*/*/))
-VPATH += $(dir $(wildcard ./$(BDKDIR)/*/)) $(dir $(wildcard ./$(BDKDIR)/*/*/))
+VPATH += $(dir $(wildcard ./$(BDKDIR)/)) $(dir $(wildcard ./$(BDKDIR)/*/)) $(dir $(wildcard ./$(BDKDIR)/*/*/))
+
+# Track compiler flags
+TRACK_CFLAGS = $(BUILDTDIR)/.cflags
+TRACK_LDFLAGS = $(BUILDTDIR)/.ldflags

 # Main and graphics.
-OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \
-	start.o exception_handlers.o \
-	main.o heap.o \
-	gfx.o tui.o \
-	fe_emmc_tools.o fe_info.o fe_tools.o \
-)
+OBJS =  start exception_handlers main heap gfx logos tui fe_info fe_tools

 # Hardware.
-OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
-	bpmp.o ccplex.o clock.o di.o gpio.o i2c.o irq.o mc.o sdram.o \
-	pinmux.o se.o smmu.o tsec.o uart.o \
-	fuse.o kfuse.o minerva.o \
-	sdmmc.o sdmmc_driver.o emummc.o nx_emmc.o nx_sd.o \
-	bq24193.o max17050.o max7762x.o max77620-rtc.o \
-	hw_init.o \
-)
+OBJS += bpmp ccplex clock di i2c irq timer \
+		mc sdram minerva smmu \
+		gpio pinmux pmc se tsec uart \
+		fuse kfuse \
+		sdmmc sdmmc_driver emmc sd emummc emummc_file_based emusd \
+		bq24193 max17050 max7762x max77620-rtc \
+		hw_init boot_storage file_based_storage

 # Utilities.
-OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
-	btn.o dirlist.o ianos.o util.o \
-	config.o ini.o \
-)
+OBJS += btn dirlist ianos ini util config

-# Horizon.
-OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
-	hos.o hos_config.o pkg1.o pkg2.o pkg2_ini_kippatch.o fss.o secmon_exo.o sept.o \
-)
+# OS loaders.
+OBJS += l4t hos hos_config pkg1 pkg2 pkg3 pkg2_ini_kippatch secmon_exo

 # Libraries.
-OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
-	lz.o blz.o \
-	diskio.o ff.o ffunicode.o ffsystem.o \
-	elfload.o elfreloc_arm.o \
-)
+OBJS += lz lz4 blz diskio ff ffunicode ffsystem elfload elfreloc_arm
+
+OBJS := $(addsuffix .o, $(OBJS))
+OBJS := $(addprefix $(BUILDTDIR)/, $(OBJS))

 GFX_INC   := '"../$(SOURCEDIR)/gfx/gfx.h"'
 FFCFG_INC := '"../$(SOURCEDIR)/libs/fatfs/ffconf.h"'
@@ -63,63 +56,113 @@ FFCFG_INC := '"../$(SOURCEDIR)/libs/fatfs/ffconf.h"'
 ################################################################################

 CUSTOMDEFINES := -DIPL_LOAD_ADDR=$(IPL_LOAD_ADDR) -DBL_MAGIC=$(IPL_MAGIC)
-CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_RESERVED=$(BLVERSION_RSVD)
-CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_RESERVED=$(NYXVERSION_RSVD)
-CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC)
+CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_VER_RL=$(BLVERSION_REL)
+CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_VER_RL=$(NYXVERSION_REL)

-# 0: UART_A, 1: UART_B.
-#CUSTOMDEFINES += -DDEBUG_UART_PORT=0
+# BDK defines.
+CUSTOMDEFINES += -DBDK_MALLOC_NO_DEFRAG -DBDK_EMUMMC_ENABLE
+CUSTOMDEFINES += -DBDK_WATCHDOG_FIQ_ENABLE -DBDK_RESTART_BL_ON_WDT
+CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC)

 #CUSTOMDEFINES += -DDEBUG

-ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-CFLAGS = $(ARCH) -O2 -g -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 -Wall $(CUSTOMDEFINES)
+# UART Logging: Max baudrate 12.5M.
+# DEBUG_UART_PORT - 0: UART_A, 1: UART_B, 2: UART_C.
+#CUSTOMDEFINES += -DDEBUG_UART_BAUDRATE=115200 -DDEBUG_UART_INVERT=0 -DDEBUG_UART_PORT=1
+
+#TODO: Considering reinstating some of these when pointer warnings have been fixed.
+WARNINGS := -Wall -Wsign-compare -Wtype-limits -Wno-array-bounds -Wno-stringop-overread -Wno-stringop-overflow
+#-fno-delete-null-pointer-checks
+#-Wstack-usage=byte-size -fstack-usage
+
+ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork $(WARNINGS)
+CFLAGS = $(ARCH) -O2 -g -gdwarf-4 -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 $(CUSTOMDEFINES)
 LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections -Xlinker --defsym=IPL_LOAD_ADDR=$(IPL_LOAD_ADDR)

 MODULEDIRS := $(wildcard modules/*)
 NYXDIR := $(wildcard nyx)
+LDRDIR := $(wildcard loader)
+TOOLSLZ := $(wildcard tools/lz)
+TOOLSB2C := $(wildcard tools/bin2c)
+TOOLS := $(TOOLSLZ) $(TOOLSB2C)
+
+ifndef IPLECHO
+T := $(shell $(MAKE) $(BUILDTDIR)/$(TARGET).elf --no-print-directory -nrRf $(firstword $(MAKEFILE_LIST)) IPLECHO="IPLOBJ" | grep -c "IPLOBJ")
+
+N := x
+C = $(words $N)$(eval N := x $N)
+IPLECHO = echo -ne "\r`expr "  [\`expr $C '*' 100 / $T\`" : '.*\(....\)$$'`%]\033[K"
+endif

 ################################################################################

-.PHONY: all clean $(MODULEDIRS) $(NYXDIR)
+.PHONY: all clean $(LDRDIR) $(TOOLS) $(NYXDIR) $(MODULEDIRS)

-all: $(TARGET).bin
-	@echo -n "Payload size is "
+all: $(TARGET).bin $(LDRDIR)
+	@printf ICTC49 >> $(OUTPUTDIR)/$(TARGET).bin
+	@echo "--------------------------------------"
+	@echo "$(TARGET) size:"
+	@echo -n "Uncompr:  "
+	$(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET)_unc.bin))
+	@echo $(BIN_SIZE)" Bytes"
+	@if [ ${BIN_SIZE} -gt 140288 ]; then echo "\e[1;33mUncompr size exceeds limit!\e[0m"; fi
+	@echo -n "Payload:  "
 	$(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET).bin))
-	@echo $(BIN_SIZE)
-	@echo "Max size is     126296 Bytes."
+	@echo $(BIN_SIZE)" Bytes"
 	@if [ ${BIN_SIZE} -gt 126296 ]; then echo "\e[1;33mPayload size exceeds limit!\e[0m"; fi
+	@echo "--------------------------------------"

-clean:
-	@rm -rf $(OBJS)
+clean: $(TOOLS)
 	@rm -rf $(BUILDDIR)
 	@rm -rf $(OUTPUTDIR)
+	@$(MAKE) --no-print-directory -C $(LDRDIR) $(MAKECMDGOALS) -$(MAKEFLAGS)

-$(MODULEDIRS):
-	@$(MAKE) -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)
+$(MODULEDIRS): $(BUILDTDIR)/$(TARGET).elf
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)

-$(NYXDIR):
-	@$(MAKE) -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)
+$(NYXDIR): $(BUILDTDIR)/$(TARGET).elf $(MODULEDIRS)
+	@echo --------------------------------------
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)

-$(TARGET).bin: $(BUILDDIR)/$(TARGET)/$(TARGET).elf $(MODULEDIRS) $(NYXDIR)
-	$(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$@
-	@printf ICTC49 >> $(OUTPUTDIR)/$@
+$(LDRDIR): $(TARGET).bin $(TOOLS) $(NYXDIR) $(MODULEDIRS)
+	@$(TOOLSLZ)/lz77 $(OUTPUTDIR)/$(TARGET).bin
+	@mv $(OUTPUTDIR)/$(TARGET).bin $(OUTPUTDIR)/$(TARGET)_unc.bin
+	@mv $(OUTPUTDIR)/$(TARGET).bin.00.lz payload_00
+	@mv $(OUTPUTDIR)/$(TARGET).bin.01.lz payload_01
+	@$(TOOLSB2C)/bin2c payload_00 > $(LDRDIR)/payload_00.h
+	@$(TOOLSB2C)/bin2c payload_01 > $(LDRDIR)/payload_01.h
+	@rm payload_00
+	@rm payload_01
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS) PAYLOAD_NAME=$(TARGET)

-$(BUILDDIR)/$(TARGET)/$(TARGET).elf: $(OBJS)
-	@$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@
-	@echo "hekate was built with the following flags:\nCFLAGS:  "$(CFLAGS)"\nLDFLAGS: "$(LDFLAGS)
+$(TOOLS):
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)

-$(BUILDDIR)/$(TARGET)/%.o: %.c
-	@echo Building $@
-	@$(CC) $(CFLAGS) $(BDKINC) -c $< -o $@
+$(TARGET).bin: $(BUILDTDIR)/$(TARGET).elf
+	@$(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$@
+	@echo --------------------------------------

-$(BUILDDIR)/$(TARGET)/%.o: %.S
-	@echo Building $@
-	@$(CC) $(CFLAGS) -c $< -o $@
+$(BUILDTDIR)/$(TARGET).elf: $(OBJS) $(TRACK_LDFLAGS)
+	@echo -ne "\r[100%] Linking $(TARGET).elf\033[K"
+	@$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $(OBJS) -o $@
+	@printf "\n$(TARGET) was built with the following flags:\nCFLAGS:  $(CFLAGS)\nLDFLAGS: $(LDFLAGS)\n"

-$(OBJS): $(BUILDDIR)/$(TARGET)
+$(BUILDTDIR)/%.o: %.c $(TRACK_CFLAGS) | $(BUILDTDIR)
+	@$(IPLECHO) Building $@
+	@$(CC) $(CFLAGS) $(BDKINC) -MMD -MP -c $< -o $@

-$(BUILDDIR)/$(TARGET):
+$(BUILDTDIR)/%.o: %.S $(TRACK_CFLAGS) | $(BUILDTDIR)
+	@$(IPLECHO) Building $@
+	@$(CC) $(CFLAGS) -MMD -MP -c $< -o $@
+
+$(BUILDTDIR):
 	@mkdir -p "$(BUILDDIR)"
-	@mkdir -p "$(BUILDDIR)/$(TARGET)"
+	@mkdir -p "$(BUILDTDIR)"
 	@mkdir -p "$(OUTPUTDIR)"
+
+# Non objects change detectors.
+$(TRACK_CFLAGS): $(BUILDTDIR)
+	@echo '$(CFLAGS)' | cmp -s - $@ || echo '$(CFLAGS)' > $@
+$(TRACK_LDFLAGS): $(BUILDTDIR)
+	@echo '$(LDFLAGS)' | cmp -s - $@ || echo '$(LDFLAGS)' > $@
+-include $(OBJS:.o=.d)
--- a/README.md
+++ b/README.md
@@ -6,96 +6,148 @@
 Custom Graphical Nintendo Switch bootloader, firmware patcher, tools, and many more.


+
+- [Features](#features)
+- [Bootloader folders and files](#bootloader-folders-and-files)
+- [Bootloader configuration](#bootloader-configuration)
+  * [hekate global Configuration keys/values](#hekate-global-configuration-keysvalues-when-entry-is-config)
+  * [Boot entry key/value combinations](#boot-entry-keyvalue-combinations)
+  * [Boot entry key/value combinations for Exosphère](#boot-entry-keyvalue-combinations-for-exosphère)
+  * [Payload storage](#payload-storage)
+  * [Nyx Configuration keys/values](#nyx-configuration-keysvalues-nyxini)
+
+
+
+## Features
+
+- **Fully Configurable and Graphical** with Touchscreen and Joycon input support
+- **Launcher Style, Background and Color Themes**
+- **HOS (Switch OS) Bootloader** -- For CFW Sys/Emu, OFW Sys and Stock Sys
+- **Android & Linux Bootloader**
+- **Payload Launcher**
+- **eMMC/emuMMC Backup/Restore Tools**
+- **SD Card Partition Manager** -- Prepares and formats SD Card for any combo of HOS (Sys/emuMMC), Android and Linux
+- **emuMMC Creation & Manager** -- Can also migrate and fix existing emuMMC
+- **Switch Android & Linux flasher**
+- **USB Mass Storage (UMS) for SD/eMMC/emuMMC** -- Converts Switch into a SD Card Reader
+- **USB Gamepad** -- Converts Switch with Joycon into a USB HID Gamepad
+- **Hardware and Peripherals info** (SoC, Fuses, RAM, Display, Touch, eMMC, SD, Battery, PSU, Charger)
+- **Many other tools** like Archive Bit Fixer, Touch Calibration, SD/eMMC Benchmark, AutoRCM enabler and more
+
+
 ## Bootloader folders and files

 | Folder/File              | Description                                                           |
 | ------------------------ | --------------------------------------------------------------------- |
 | bootloader               | Main folder.                                                          |
-|  \|__ bootlogo.bmp       | It is used when custom is on and no logopath found. Can be skipped.   |
-|  \|__ hekate_ipl.ini     | Main bootloader configuration and boot entries.                       |
+|  \|__ bootlogo.bmp       | It is used if no `logopath` key is found. User provided. Can be skipped. |
+|  \|__ hekate_ipl.ini     | Main bootloader configuration and boot entries in `Launch` menu.      |
+|  \|__ nyx.ini            | Nyx GUI configuration                                                 |
 |  \|__ patches.ini        | Add external patches. Can be skipped. A template can be found [here](./res/patches_template.ini) |
-|  \|__ update.bin         | If newer, it is loaded at boot. For modchips. Auto updated. Can be skipped. |
-| bootloader/ini/          | For individual inis. 'More configs...' menu. Autoboot is supported.   |
+|  \|__ update.bin         | If newer, it is loaded at boot. Normally for modchips. Auto updated and created at first boot. |
+| bootloader/ini/          | For individual inis. `More configs` menu. Autoboot is supported.   |
 | bootloader/res/          | Nyx user resources. Icons and more.                                   |
-|  \|__ background.bmp     | Nyx - custom background.                                              |
+|  \|__ background.bmp     | Nyx - Custom background. User provided.                               |
 |  \|__ icon_switch.bmp    | Nyx - Default icon for CFWs.                                          |
 |  \|__ icon_payload.bmp   | Nyx - Default icon for Payloads.                                      |
-|  \|__ icon_lakka.bmp     | Nyx - Default icon for Lakka.                                         |
-| bootloader/sys/          | For system modules.                                                   |
-|  \|__ emummc.kipm        | emuMMC KIP1 module. Important!                                        |
-|  \|__ libsys_lp0.bso     | LP0 (sleep mode) module. Important!                                   |
-|  \|__ libsys_minerva.bso | Minerva Training Cell. Used for DRAM Frequency training. Important!   |
-|  \|__ nyx.bin            | Nyx - Our GUI. Important!                                             |
-|  \|__ res.pak            | Nyx resources package. Important!                                     |
+| bootloader/sys/          | hekate and Nyx system modules folder. !Important!                     |
+|  \|__ emummc.kipm        | emuMMC KIP1 module.                                                   |
+|  \|__ libsys_lp0.bso     | LP0 (sleep mode) module.                                              |
+|  \|__ libsys_minerva.bso | Minerva Training Cell. Used for DRAM Frequency training.              |
+|  \|__ nyx.bin            | Nyx - hekate's GUI.                                                   |
+|  \|__ res.pak            | Nyx resources package.                                                |
+|  \|__ thk.bin            | Atmosphère Tsec Hovi Keygen.                                          |
+|  \|__ /l4t/              | Folder with firmware relevant to L4T (Linux/Android).                 |
 | bootloader/screenshots/  | Folder where Nyx screenshots are saved                                |
-| bootloader/payloads/     | For payloads. 'Payloads...' menu. Autoboot only supported by including them into an ini. All CFW bootloaders, tools, Linux payloads are supported. |
-| bootloader/libtools/     | Future reserved                                                       |
-| sept                     | Sept folder. This must always get updated via the Atmosphère release zip. Needed for tools and booting HOS on 7.0.0 and up. Unused for booting HOS if `fss0=` key is defined. |
+| bootloader/payloads/     | For the `Payloads` menu. All CFW bootloaders, tools, Linux payloads are supported. Autoboot only supported by including them into an ini. |
+| bootloader/libtools/     | Reserved                                                              |

-**Note**: Sept files for booting 7.0.0 and up are expected at /sept folder at root of sd card.


 ## Bootloader configuration

-The bootloader can be configured via 'bootloader/hekate_ipl.ini' (if it is present on the SD card). Each ini section represents a boot entry, except for the special section 'config' that controls the global configuration.
+The bootloader can be configured via `Nyx` -> `Options` or 'bootloader/hekate_ipl.ini'. The special section 'config' controls the actual global configuration. Any other ini section represents a boot entry and can only be edited manually via the ini.


 There are four possible type of entries. "**[ ]**": Boot entry, "**{ }**": Caption, "**#**": Comment, "*newline*": .ini cosmetic newline.


-You can find a template [Here](./res/hekate_ipl_template.ini)
+**You can find a template [Here](./res/hekate_ipl_template.ini)**


-### Global Configuration keys/values when boot entry is **config**:
+### hekate Configuration keys/values (section *[config]*)

-| Config option      | Description                                                |
-| ------------------ | ---------------------------------------------------------- |
-| autoboot=0         | 0: Disable, #: Boot entry number to auto boot.             |
+Use `Options` in Nyx to edit the following configuration:
+
+| Config option      | Description                                                    |
+| ------------------ | -------------------------------------------------------------- |
+| autoboot=0         | 0: Disable, #: Boot entry number to auto boot.                 |
 | autoboot_list=0    | 0: Read `autoboot` boot entry from hekate_ipl.ini, 1: Read from ini folder (ini files are ASCII ordered). |
-| bootwait=3         | 0: Disable (It also disables bootlogo. Having **VOL-** pressed since injection goes to menu.), #: Time to wait for **VOL-** to enter menu. |
+| bootwait=3         | 0: Disable (It also disables bootlogo. Having **VOL-** pressed since injection goes to menu.), #: Time to wait for **VOL-** to enter menu. Max: 20s. |
 | autohosoff=1       | 0: Disable, 1: If woke up from HOS via an RTC alarm, shows logo, then powers off completely, 2: No logo, immediately powers off.|
 | autonogc=1         | 0: Disable, 1: Automatically applies nogc patch if unburnt fuses found and a >= 4.0.0 HOS is booted. |
 | updater2p=0        | 0: Disable, 1: Force updates (if needed) the reboot2payload binary to be hekate. |
-| backlight=100      | Screen backlight level. 0-255.                             |
+| backlight=100      | Screen backlight level. 0-255.                                 |
+| ------------------ | --------- *The following can be edited via ini only* --------- |
+| noticker=0         | 0: Animated line is drawn during custom bootlogo, signifying time left to skip to menu. 1: Disable. |
+| bootprotect=0      | 0: Disable, 1: Protect bootloader folder from being corrupted by disallowing reading or editing in HOS. |


-### Nyx Global Configuration keys/values for (nyx.ini):
+### Boot entry key/value combinations

-| Config option      | Description                                                |
-| ------------------ | ---------------------------------------------------------- |
-| themecolor=167     | Sets Nyx color of text highlights.                         |
-| timeoff=100        | Sets time offset in HEX. Must be in HOS epoch format       |
-| homescreen=0       | Sets home screen. 0: Home menu, 1: All configs (merges Launch and More configs), 2: Launch, 3: More Configs. |
-| verification=1     | 0: Disable Backup/Restore verification, 1: Sparse (block based, fast and mostly reliable), 2: Full (sha256 based, slow and 100% reliable). |
-| umsemmcrw=1        | 1: eMMC/emuMMC UMS will be mounted as writable by default. |
-
-
-### Boot entry key/value combinations:
+A boot entry needs to be manually added/edited with the user's chosen key/value combos.

 | Config option          | Description                                                |
 | ---------------------- | ---------------------------------------------------------- |
-| warmboot={SD path}     | Replaces the warmboot binary                               |
-| secmon={SD path}       | Replaces the security monitor binary                       |
-| kernel={SD path}       | Replaces the kernel binary                                 |
-| kip1={SD path}         | Replaces/Adds kernel initial process. Multiple can be set. |
-| kip1={SD folder}/*     | Loads every .kip/.kip1 inside a folder. Compatible with single kip1 keys. |
-| fss0={SD path}         | Takes a fusee-secondary binary and `extracts` all needed parts from it. kips, exosphere, warmboot and sept. |
-| fss0experimental=1     | Enables loading of experimental content from a FSS0 storage |
-| kip1patch=patchname    | Enables a kip1 patch. Specify with multiple lines and/or as CSV. If not found, an error will show up |
-| fullsvcperm=1          | Disables SVC verification (full services permission)       |
-| debugmode=1            | Enables Debug mode. Obsolete when used with exosphere as secmon. |
-| atmosphere=1           | Enables Atmosphère patching.                               |
-| emupath={SD folder}    | Forces emuMMC to use the selected one. (=emuMMC/RAW1, =emuMMC/SD00, etc). emuMMC must be created by hekate because it uses the raw_based/file_based files. |
+| warmboot={FILE path}   | Replaces the warmboot binary                               |
+| secmon={FILE path}     | Replaces the security monitor binary                       |
+| kernel={FILE path}     | Replaces the kernel binary                                 |
+| kip1={FILE path}       | Replaces/Adds kernel initial process. Multiple can be set. |
+| kip1={FOLDER path}/*   | Loads every .kip/.kip1 inside a folder. Compatible with single kip1 keys. |
+| pkg3={FILE path}       | Takes an Atmosphere `package3` binary and `extracts` all needed parts from it. kips, exosphere, warmboot and mesophere. |
+| fss0={FILE path}       | Same as above. !Deprecated! |
+| pkg3ex=1               | Enables loading of experimental content from a PKG3/FSS0 storage |
+| pkg3kip1skip={KIP name} | Skips loading a kip from `pkg3`/`fss0`. Allows multiple and `,` as separator. The name must exactly match the name in `PKG3`. |
+| exofatal={FILE path}   | Replaces the exosphere fatal binary for Mariko             |
+| ---------------------- | ---------------------------------------------------------- |
+| kip1patch=patchname    | Enables a kip1 patch. Allows multiple and `,` as separator. If actual patch is not found, a warning will show up. |
+| emupath={FOLDER path}  | Forces emuMMC to use the selected one. (=emuMMC/RAW1, =emuMMC/SD00, etc). emuMMC must be created by hekate because it uses the raw_based/file_based files. |
 | emummcforce=1          | Forces the use of emuMMC. If emummc.ini is disabled or not found, then it causes an error. |
 | emummc_force_disable=1 | Disables emuMMC, if it's enabled.                           |
-| stock=1                | Disables unneeded kernel patching when running stock or semi-stock. `If emuMMC is enabled, emummc_force_disabled=1` is required. emuMMC is not supported on stock. If additional KIPs are needed other than OFW's, you can define them with `kip1` key. No kip should be used that relies on Atmosphère patching, because it will hang. If `NOGC` is needed, use `kip1patch=nogc`. |
-| id=idname              | Identifies boot entry for forced boot via id. Max 7 chars. |
-| payload={SD path}      | Payload launching. Tools, Linux, CFW bootloaders, etc.     |
-| logopath={SD path}     | If no logopath, `bootloader/bootlogo.bmp` will be used if exists. If logopath exists, it will load the specified bitmap. |
-| icon={SD path}         | Force Nyx to use the icon defined here. If this is not found, it will check for a bmp named as the boot entry ([Test 2] -> `bootloader/res/Test 2.bmp`). Otherwise default will be used. |
+| stock=1                | OFW via hekate bootloader. Disables unneeded kernel patching and CFW kips when running stock. `If emuMMC is enabled, emummc_force_disable=1` is required. emuMMC is not supported on stock. If additional KIPs are needed other than OFW's, you can define them with `kip1` key. No kip should be used that relies on Atmosphère patching, because it will hang. If `NOGC` is needed, use `kip1patch=nogc`. |
+| fullsvcperm=1          | Disables SVC verification (full services permission). Doesn't work with Mesosphere as kernel. |
+| debugmode=1            | Enables Debug mode. Obsolete when used with exosphere as secmon. |
+| kernelprocid=1         | Enables stock kernel process id send/recv patching. Not needed when `pkg3`/`fss0` is used. |
+| ---------------------- | ---------------------------------------------------------- |
+| payload={FILE path}    | Payload launching. Tools, Android/Linux, CFW bootloaders, etc. Any key above when used with that, doesn't get into account. |
+| ---------------------- | ---------------------------------------------------------- |
+| l4t=1                  | L4T Linux/Android native launching.                        |
+| boot_prefixes={FOLDER path} | L4T bootstack directory.                              |
+| ram_oc=0               | L4T RAM Overclocking. Check README_CONFIG.txt for more info. |
+| ram_oc_vdd2=1100       | L4T RAM VDD2 Voltage. Set VDD2 (T210B01) or VDD2/VDDQ (T210) voltage. 1050-1175. |
+| ram_oc_vddq=600        | L4T RAM VDDQ Voltage. Set VDDQ (T210B01). 550-650.         |
+| uart_port=0            | Enables logging on serial port for L4T uboot/kernel.       |
+| sld_type=0x31444C53    | Controls the type of seamless display support. 0x0: Disable, 0x31444C53: L4T seamless display. |
+| Additional keys        | Each distro supports more keys. Check README_CONFIG.txt  for more info. |
+| ---------------------- | ---------------------------------------------------------- |
+| bootwait=3             | Overrides global bootwait from `[config]`.                 |
+| id=IDNAME              | Identifies boot entry for forced boot via id. Max 7 chars. |
+| logopath={FILE path}   | If it exists, it will load the specified bitmap. Otherwise `bootloader/bootlogo.bmp` will be used if exists |
+| icon={FILE path}       | Force Nyx to use the icon defined here. If this is not found, it will check for a bmp named as the boot entry ([Test 2] -> `bootloader/res/Test 2.bmp`). Otherwise defaults will be used. |


-### Boot entry key/value Exosphère combinations:
+**Note1**: When using the wildcard (`/*`) with `kip1` you can still use the normal `kip1` after that to load extra single kips.
+
+**Note2**: When using PKG3/FSS0 it parses exosphere, warmboot and all core kips. You can override the first 2 by using `secmon`/`warmboot` after defining `pkg3`/`fss0`.
+You can define `kip1` to load an extra kip or many via the wildcard (`/*`) usage.
+
+**Warning**: Careful when you override *pkg3/fss core* kips with `kip1`.
+That's in case the kips are incompatible between them. If compatible, you can override `pkg3`/`fss0` kips with no issues (useful for testing with intermediate kip changes). In such cases, the `kip1` line must be **after** `pkg3`/`fss0` line.
+
+
+### Boot entry key/value combinations for Exosphère
+
+The following can be paired together with a HOS boot entry:

 | Config option          | Description                                                |
 | ---------------------- | ---------------------------------------------------------- |
@@ -103,52 +155,74 @@ You can find a template [Here](./res/hekate_ipl_template.ini)
 | userpmu=1              | Enables user access to PMU when paired with Exosphère.     |
 | cal0blank=1            | Overrides Exosphère config `blank_prodinfo_{sys/emu}mmc`. If that key doesn't exist, `exosphere.ini` will be used. |
 | cal0writesys=1         | Overrides Exosphère config `allow_writing_to_cal_sysmmc`. If that key doesn't exist, `exosphere.ini` will be used. |
+| usb3force=1            | Overrides system settings mitm config `usb30_force_enabled`. If that key doesn't exist, `system_settings.ini` will be used. |
+| memmode=1              | Enables boot config memory mode for retail units. By default, max ram is limited to 4GB. Enabling this will automatically choose size. |


-**Note1**: When using the wildcard (`/*`) with `kip1` you can still use the normal `kip1` after that to load extra single kips.
-
-**Note2**: When using FSS0 it parses exosphere, warmboot and all core kips. You can override the first 2 by using `secmon`/`warmboot` after defining `fss0`.
-You can define `kip1` to load an extra kip or many via the wildcard (`/*`) usage.
-
-**Warning**: Never define *fss0 core* kips when using `fss0` and make sure that the folder (when using `/*`), does not include them.
-This is in case the kips are incompatible between them. If compatible, you can override `fss0` kips with no issues (useful for testing with intermediate kip changes).
+**Note**: `cal0blank`, `cal0writesys`, `usb3force`, as stated override the `exosphere.ini` or `system_settings.ini`. 0: Disable, 1: Enable, Key Missing: Use original value.


-### Payload storage:
+**Note2**: `blank_prodinfo_{sys/emu}mmc`, `allow_writing_to_cal_sysmmc` and `usb30_force_enabled` in `exosphere.ini` and `system_settings.ini` respectively, are the only atmosphere config keys that can affect hekate booting configuration externally, **if** the equivalent keys in hekate config are missing.

-hekate has a boot storage in the binary that helps it configure it outside of BPMP enviroment:
+
+## Payload storage
+
+hekate has a boot storage in the binary that helps it configure it outside of BPMP environment:

 | Offset / Name           | Description                                                       |
 | ----------------------- | ----------------------------------------------------------------- |
-| '0x94' boot_cfg         | bit0: `Force AutoBoot`, bit1: `Show launch log`, bit2: `Boot from ID`, bit3: `Boot to emuMMC`, bit6: `Boot to UMS`, bit7: `sept run`. |
-| '0x95' autoboot         | If `Force AutoBoot`: 0: Force go to menu, else boot that entry.   |
+| '0x94' boot_cfg         | bit0: `Force AutoBoot`, bit1: `Show launch log`, bit2: `Boot from ID`, bit3: `Boot to emuMMC`. |
+| '0x95' autoboot         | If `Force AutoBoot`, 0: Force go to menu, else boot that entry.   |
 | '0x96' autoboot_list    | If `Force AutoBoot` and `autoboot` then it boots from ini folder. |
-| '0x97' extra_cfg        | bit7: Force Nyx to run `Dump pkg1/2`.                             |
+| '0x97' extra_cfg        | When menu is forced: bit5: `Run UMS`.                             |
 | '0x98' xt_str[128]      | Depends on the set cfg bits.                                      |
-| '0x98' ums[1]           | When `Boot to UMS` is set, it will launch the selected UMS. 0: SD, 1: eMMC BOOT0, 2: eMMC BOOT1, 3: eMMC GPP, 4: emuMMC BOOT0, 5: emuMMC BOOT1, 6: emuMMC GPP,  |
+| '0x98' ums[1]           | When `Run UMS` is set, it will launch the selected UMS. 0: SD, 1/2/3: eMMC BOOT0/BOOT1/GPP, 4/5/6: emuMMC BOOT0/BOOT1/GPP,  |
 | '0x98' id[8]            | When `Boot from ID` is set, it will search all inis automatically and find the boot entry with that id and boot it. Must be NULL terminated. |
 | '0xA0' emummc_path[120] | When `Boot to emuMMC` is set, it will override the current emuMMC (boot entry or emummc.ini). Must be NULL terminated. |


-If the main .ini is not found, it is created on the first hekate boot.
+## Nyx Configuration keys/values (nyx.ini)
+
+Use `Nyx Settings` in Nyx to edit the following configuration:
+
+| Config option      | Description                                                |
+| ------------------ | ---------------------------------------------------------- |
+| themebg=2d2d2d     | Sets Nyx background color in HEX. 0x0B0B0B to 0xC7C7C7.    |
+| themecolor=167     | Sets Nyx color of text highlights.                         |
+| entries5col=0      | 1: Sets Launch entry columns from 4 to 5 per line. For a total of 10 entries. |
+| timeoffset=0       | Sets time offset in HEX. Must be in epoch format           |
+| timedst=1          | Enables automatic daylight saving hour adjustment          |
+| homescreen=0       | Sets home screen. 0: Home menu, 1: All configs (merges Launch and More configs), 2: Launch, 3: More Configs. |
+| verification=1     | 0: Disable Backup/Restore verification, 1: Sparse (block based, fast and mostly reliable), 2: Full (sha256 based, slow and 100% reliable). |
+| ------------------ | ----- *The following can be edited via nyx.ini only* ----- |
+| umsemmcrw=0        | 1: eMMC/emuMMC UMS will be mounted as writable by default. |
+| jcdisable=0        | 1: Disables Joycon driver completely.                      |
+| jcforceright=0     | 1: Forces right joycon to be used as main mouse control.   |
+| bpmpclock=1        | 0: Auto, 1: 589 MHz, 2: 576 MHz, 3: 563 MHz, 4: 544 MHz, 5: 408 MHz. Use 2 to 5 if Nyx hangs or some functions like UMS/Backup Verification fail. |


 ```
 hekate  (c) 2018,      naehrwert, st4rk.
-        (c) 2018-2020, CTCaer.
+        (c) 2018-2026, CTCaer.

-Nyx GUI (c) 2019-2020, CTCaer.
+Nyx GUI (c) 2019-2026, CTCaer.

 Thanks to: derrek, nedwill, plutoo, shuffle2, smea, thexyz, yellows8.
 Greetings to: fincs, hexkyz, SciresM, Shiny Quagsire, WinterMute.

 Open source and free packages used:
- - FatFs R0.13a, Copyright (c) 2017, ChaN
- - bcl-1.2.0, Copyright (c) 2003-2006, Marcus Geelnard
- - Atmosphère (Exosphere types/panic, prc id kernel patches),
-   Copyright (c) 2018-2019, Atmosphère-NX
- - elfload, Copyright (c) 2014 Owen Shepherd, Copyright (c) 2018 M4xw
- - Littlev Graphics Library, Copyright (c) 2016 Gabor Kiss-Vamosi
+ - Littlev Graphics Library,
+   Copyright (c) 2016-2018 Gabor Kiss-Vamosi
+ - FatFs R0.13c,
+   Copyright (c) 2006-2018, ChaN
+   Copyright (c) 2018-2022, CTCaer
+ - bcl-1.2.0,
+   Copyright (c) 2003-2006, Marcus Geelnard
+ - blz,
+   Copyright (c) 2018, SciresM
+ - elfload,
+   Copyright (c) 2014 Owen Shepherd,
+   Copyright (c) 2018 M4xw

                         ___
                      .-'   `'.
--- a/README_BOOTLOGO.md
+++ b/README_BOOTLOGO.md
@@ -4,13 +4,16 @@ The bootlogo can be any size with a maximum of 720 x 1280.

 When it's smaller than 720 x 1280, it is automatically centered and the background takes the color of the first pixel.

-When saving a landscape bootlogo, it should be rotated 90 degrees counterclockwise.
+The process is to create a landscape bootlogo and then rotate it 90 degrees counterclockwise.

 Lastly, the supported format is 32-bit (ARGB) BMP. Classic 24-bit (RGB) BMPs are not supported for performance reasons.


 ## How to configure

-If the custom logo option is enabled, it will try to load /bootlogo.bmp. If this is not found, the default hekate's logo will be used.
+If a boot entry specifies a custom logo path (`logopath=`), this one will be loaded.

-If a boot entry specifies a custom logo path, this is one will be loaded. Again if this is not found, bootlogo.bmp will be loaded and if that fails, hekate's built-in will be used.
+If the above is not found or the format is not correct, it will try to load `bootloader/bootlogo.bmp`.
+If this is not found, the default hekate logo will be used.
+
+(`bootloader/bootlogo.bmp` is basically like a global bootlogo.)
--- a/Versions.inc
+++ b/Versions.inc
@@ -1,11 +1,11 @@
 # IPL Version.
-BLVERSION_MAJOR := 5
-BLVERSION_MINOR := 3
-BLVERSION_HOTFX := 0
-BLVERSION_RSVD := 0
+BLVERSION_MAJOR := 6
+BLVERSION_MINOR := 5
+BLVERSION_HOTFX := 3
+BLVERSION_REL   := 0

 # Nyx Version.
-NYXVERSION_MAJOR := 0
+NYXVERSION_MAJOR := 1
 NYXVERSION_MINOR := 9
-NYXVERSION_HOTFX := 2
-NYXVERSION_RSVD := 0
+NYXVERSION_HOTFX := 3
+NYXVERSION_REL   := 0
--- a/bdk/bdk.h
+++ b/bdk/bdk.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2022 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef BDK_H
+#define BDK_H
+
+#include <memory_map.h>
+
+#include <display/di.h>
+#include <display/vic.h>
+#include <input/als.h>
+#include <input/joycon.h>
+#include <input/touch.h>
+#include <mem/emc_t210.h>
+#include <mem/heap.h>
+#include <mem/mc.h>
+#include <mem/minerva.h>
+#include <mem/sdram.h>
+#include <mem/smmu.h>
+#include <module.h>
+#include <power/bm92t36.h>
+#include <power/bq24193.h>
+#include <power/max17050.h>
+#include <power/max77620.h>
+#include <power/max7762x.h>
+#include <power/max77812.h>
+#include <power/regulator_5v.h>
+#include <rtc/max77620-rtc.h>
+#include <sec/se.h>
+#include <sec/tsec.h>
+#include <soc/actmon.h>
+#include <soc/bpmp.h>
+#include <soc/ccplex.h>
+#include <soc/clock.h>
+#include <soc/fuse.h>
+#include <soc/gpio.h>
+#include <soc/hw_init.h>
+#include <soc/i2c.h>
+#include <soc/irq.h>
+#include <soc/kfuse.h>
+#include <soc/pinmux.h>
+#include <soc/pmc.h>
+#include <soc/timer.h>
+#include <soc/t210.h>
+#include <soc/uart.h>
+#include <storage/emmc.h>
+#include <storage/mbr_gpt.h>
+#include <storage/mmc_def.h>
+#include <storage/nx_emmc_bis.h>
+#include <storage/ramdisk.h>
+#include <storage/sd.h>
+#include <storage/sdmmc.h>
+#include <thermal/fan.h>
+#include <thermal/tmp451.h>
+#include <usb/usbd.h>
+#include <utils/aarch64_util.h>
+#include <utils/btn.h>
+#include <utils/dirlist.h>
+#include <utils/ini.h>
+#include <utils/list.h>
+#include <utils/sprintf.h>
+#include <utils/tegra_bct.h>
+#include <utils/tegra_bit.h>
+#include <utils/types.h>
+#include <utils/util.h>
+
+#include <gfx_utils.h>
+
+#endif
--- a/bdk/display/di.c
+++ b/bdk/display/di.c
--- a/bdk/display/di.h
+++ b/bdk/display/di.h
@@ -0,0 +1,925 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2025 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DI_H_
+#define _DI_H_
+
+#include <memory_map.h>
+#include <utils/types.h>
+
+#define DSI_VIDEO_DISABLED 0
+#define DSI_VIDEO_ENABLED  1
+
+#define WINDOW_A 0
+#define WINDOW_B 1
+#define WINDOW_C 2
+#define WINDOW_D 3
+
+/*! Display registers. */
+// All Display/DSI/MIPI register defines and macros are index based (not offset).
+// DC_CMD/DC_COM/WINC Non-shadowed. DC_DISP/DC_WIN/DC_WINBUF Shadowed.
+
+// Display controller scratch registers.
+#define DC_D_WINBUF_DD_SCRATCH_REGISTER_0 0xED
+#define DC_D_WINBUF_DD_SCRATCH_REGISTER_1 0xEE
+#define DC_T_WINBUF_TD_SCRATCH_REGISTER_0 0x16D
+#define DC_T_WINBUF_TD_SCRATCH_REGISTER_1 0x16E
+#define DC_COM_SCRATCH_REGISTER_A         0x325
+#define DC_COM_SCRATCH_REGISTER_B         0x326
+#define DC_A_WINBUF_AD_SCRATCH_REGISTER_0 0xBED
+#define DC_A_WINBUF_AD_SCRATCH_REGISTER_1 0xBEE
+#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0 0xDED
+#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1 0xDEE
+#define DC_C_WINBUF_CD_SCRATCH_REGISTER_0 0xFED
+#define DC_C_WINBUF_CD_SCRATCH_REGISTER_1 0xFEE
+
+// DC_CMD non-shadowed command/sync registers.
+#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
+#define  SYNCPT_GENERAL_INDX(x) (((x) & 0xFF) << 0)
+#define  SYNCPT_GENERAL_COND(x) (((x) & 0xFF) << 8)
+#define  COND_REG_WR_SAFE 3
+
+#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
+#define  SYNCPT_CNTRL_SOFT_RESET BIT(0)
+#define  SYNCPT_CNTRL_NO_STALL   BIT(8)
+
+#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
+#define  SYNCPT_VSYNC_INDX(x) (((x) & 0xFF) << 0)
+#define  SYNCPT_VSYNC_ENABLE  BIT(8)
+
+#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
+
+#define DC_CMD_DISPLAY_COMMAND 0x32
+#define  DISP_CTRL_MODE_STOP       (0 << 5)
+#define  DISP_CTRL_MODE_C_DISPLAY  (1 << 5)
+#define  DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
+#define  DISP_CTRL_MODE_MASK       (3 << 5)
+
+#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
+#define  PW0_ENABLE BIT(0)
+#define  PW1_ENABLE BIT(2)
+#define  PW2_ENABLE BIT(4)
+#define  PW3_ENABLE BIT(6)
+#define  PW4_ENABLE BIT(8)
+#define  PM0_ENABLE BIT(16)
+#define  PM1_ENABLE BIT(18)
+
+#define DC_CMD_INT_STATUS 0x37
+#define DC_CMD_INT_MASK 0x38
+#define DC_CMD_INT_ENABLE 0x39
+#define  DC_CMD_INT_FRAME_END_INT BIT(1)
+#define  DC_CMD_INT_V_BLANK_INT   BIT(2)
+#define DC_CMD_INT_POLARITY 0x3B
+
+#define DC_CMD_STATE_ACCESS 0x40
+#define  READ_MUX_ASSEMBLY  0x0
+#define  WRITE_MUX_ASSEMBLY 0x0
+#define  READ_MUX_ACTIVE    BIT(0)
+#define  WRITE_MUX_ACTIVE   BIT(2)
+
+#define DC_CMD_STATE_CONTROL 0x41
+#define  GENERAL_ACT_REQ BIT(0)
+#define  WIN_ACT_REQ     1
+#define  WIN_A_ACT_REQ   BIT(1)
+#define  WIN_B_ACT_REQ   BIT(2)
+#define  WIN_C_ACT_REQ   BIT(3)
+#define  WIN_D_ACT_REQ   BIT(4)
+#define  CURSOR_ACT_REQ  BIT(7)
+#define  GENERAL_UPDATE  BIT(8)
+#define  WIN_UPDATE      9
+#define  WIN_A_UPDATE    BIT(9)
+#define  WIN_B_UPDATE    BIT(10)
+#define  WIN_C_UPDATE    BIT(11)
+#define  WIN_D_UPDATE    BIT(12)
+#define  CURSOR_UPDATE   BIT(15)
+#define  NC_HOST_TRIG    BIT(24)
+
+#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
+#define  WINDOW_SELECT   4
+#define  WINDOW_A_SELECT BIT(4)
+#define  WINDOW_B_SELECT BIT(5)
+#define  WINDOW_C_SELECT BIT(6)
+#define  WINDOW_D_SELECT BIT(7)
+
+#define DC_CMD_REG_ACT_CONTROL 0x43
+#define  GENERAL_ACT_HCNTR_SEL BIT(0)
+#define  WIN_A_ACT_HCNTR_SEL   BIT(2)
+#define  WIN_B_ACT_HCNTR_SEL   BIT(4)
+#define  WIN_C_ACT_HCNTR_SEL   BIT(6)
+#define  CURSOR_ACT_HCNTR_SEL  BIT(7)
+#define  WIN_D_ACT_HCNTR_SEL   BIT(10)
+
+// DC_D_WIN_DD window D instance of DC_WIN
+#define DC_D_WIN_DD_WIN_OPTIONS 0x80
+#define DC_D_WIN_DD_COLOR_DEPTH 0x83
+#define DC_D_WIN_DD_POSITION    0x84
+#define DC_D_WIN_DD_SIZE        0x85
+#define DC_D_WIN_DD_LINE_STRIDE 0x8A
+#define DC_D_WIN_DD_BLEND_LAYER_CONTROL 0x96
+#define DC_D_WIN_DD_BLEND_MATCH_SELECT  0x97
+#define DC_D_WIN_DD_BLEND_ALPHA_1BIT    0x99
+
+// DC_D_WINBUF_DD window D instance of DC_WINBUF
+#define DC_D_WINBUF_DD_START_ADDR    0xC0
+#define DC_D_WINBUF_DD_ADDR_H_OFFSET 0xC6
+#define DC_D_WINBUF_DD_ADDR_V_OFFSET 0xC8
+#define DC_D_WINBUF_DD_START_ADDR_HI 0xCD
+#define DC_D_WINBUF_DD_MEMFETCH_CONTROL 0xEB
+
+// DC_T_WIN_TD macro for using DD defines.
+#define _DC_T(reg) ((reg) + 0x80)
+
+// DC_COM non-shadowed registers.
+#define DC_COM_CRC_CONTROL 0x300
+#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
+#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
+#define  LSC0_OUTPUT_POLARITY_LOW BIT(24)
+
+// CMU registers.
+#define DC_COM_CMU_CSC_KRR    0x32A
+#define DC_COM_CMU_CSC_KGR    0x32B
+#define DC_COM_CMU_CSC_KBR    0x32C
+#define DC_COM_CMU_CSC_KRG    0x32D
+#define DC_COM_CMU_CSC_KGG    0x32E
+#define DC_COM_CMU_CSC_KBG    0x32F
+#define DC_COM_CMU_CSC_KRB    0x330
+#define DC_COM_CMU_CSC_KGB    0x331
+#define DC_COM_CMU_CSC_KBB    0x332
+#define DC_COM_CMU_LUT1       0x336
+#define  LUT1_ADDR(x)      ((x) & 0xFF)
+#define  LUT1_DATA(x)      (((x) & 0xFFF) << 16)
+#define  LUT1_READ_DATA(x) (((x) >> 16) & 0xFFF)
+#define DC_COM_CMU_LUT2       0x337
+#define  LUT2_ADDR(x)      ((x) & 0x3FF)
+#define  LUT2_DATA(x)      (((x) & 0xFF) << 16)
+#define  LUT2_READ_DATA(x) (((x) >> 16) & 0xFF)
+#define DC_COM_CMU_LUT1_READ  0x338
+#define  LUT1_READ_ADDR(x) (((x) & 0xFF) << 8)
+#define  LUT1_READ_EN      BIT(0)
+#define DC_COM_CMU_LUT2_READ  0x339
+#define  LUT2_READ_ADDR(x) (((x) & 0x3FF) << 8)
+#define  LUT2_READ_EN      BIT(0)
+
+#define DC_COM_DSC_TOP_CTL 0x33E
+
+// DC_DISP shadowed registers.
+#define DC_DISP_DISP_WIN_OPTIONS 0x402
+#define  CURSOR_ENABLE   BIT(16)
+#define  SOR_ENABLE      BIT(25)
+#define  SOR1_ENABLE     BIT(26)
+#define  SOR1_TIMING_CYA BIT(27)
+#define  DSI_ENABLE      BIT(29)
+#define  HDMI_ENABLE     BIT(30)
+
+
+#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
+#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
+
+#define DC_DISP_DISP_TIMING_OPTIONS 0x405
+#define  VSYNC_H_POSITION(x) (((x) & 0x1FFF) << 0)
+
+#define DC_DISP_REF_TO_SYNC 0x406
+#define  H_REF_TO_SYNC(x) (((x) & 0x1FFF) <<  0) // Min 0 pixel clock.
+#define  V_REF_TO_SYNC(x) (((x) & 0x1FFF) << 16) // Min 1 line  clock.
+
+#define DC_DISP_SYNC_WIDTH 0x407
+#define  H_SYNC_WIDTH(x) (((x) & 0x1FFF) <<  0) // Min 1 pixel clock.
+#define  V_SYNC_WIDTH(x) (((x) & 0x1FFF) << 16) // Min 1 line  clock.
+
+#define DC_DISP_BACK_PORCH 0x408
+#define  H_BACK_PORCH(x) (((x) & 0x1FFF) <<  0)
+#define  V_BACK_PORCH(x) (((x) & 0x1FFF) << 16)
+
+#define DC_DISP_ACTIVE 0x409
+#define  H_DISP_ACTIVE(x) (((x) & 0x1FFF) <<  0) // Min 16 pixel clock.
+#define  V_DISP_ACTIVE(x) (((x) & 0x1FFF) << 16) // Min 16 line  clock.
+
+#define DC_DISP_FRONT_PORCH 0x40A
+#define  H_FRONT_PORCH(x) (((x) & 0x1FFF) <<  0) // Min -=PS_=-H_REF_TO_SYNC + 1
+#define  V_FRONT_PORCH(x) (((x) & 0x1FFF) << 16) // Min -=PS_=-V_REF_TO_SYNC + 1
+
+#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
+#define  SHIFT_CLK_DIVIDER(x)    ((x) & 0xFF)
+#define  PIXEL_CLK_DIVIDER_PCD1  (0 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD2  (2 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD3  (3 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD4  (4 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD6  (5 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD8  (6 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD9  (7 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
+
+#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
+#define  DISP_DATA_FORMAT_DF1P1C    (0 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
+#define  DISP_DATA_FORMAT_DF2S      (4 << 0)
+#define  DISP_DATA_FORMAT_DF3S      (5 << 0)
+#define  DISP_DATA_FORMAT_DFSPI     (6 << 0)
+#define  DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
+#define  DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
+#define  DISP_ALIGNMENT_MSB         (0 << 8)
+#define  DISP_ALIGNMENT_LSB         (1 << 8)
+#define  DISP_ORDER_RED_BLUE        (0 << 9)
+#define  DISP_ORDER_BLUE_RED        (1 << 9)
+
+#define DC_DISP_DISP_COLOR_CONTROL 0x430
+#define  BASE_COLOR_SIZE_MASK   (0xF << 0)
+#define  BASE_COLOR_SIZE_666    (0 << 0)
+#define  BASE_COLOR_SIZE_111    (1 << 0)
+#define  BASE_COLOR_SIZE_222    (2 << 0)
+#define  BASE_COLOR_SIZE_333    (3 << 0)
+#define  BASE_COLOR_SIZE_444    (4 << 0)
+#define  BASE_COLOR_SIZE_555    (5 << 0)
+#define  BASE_COLOR_SIZE_565    (6 << 0)
+#define  BASE_COLOR_SIZE_332    (7 << 0)
+#define  BASE_COLOR_SIZE_888    (8 << 0)
+#define  DITHER_CONTROL_MASK    (3 << 8)
+#define  DITHER_CONTROL_DISABLE (0 << 8)
+#define  DITHER_CONTROL_ORDERED (2 << 8)
+#define  DITHER_CONTROL_ERRDIFF (3 << 8)
+#define  DISP_COLOR_SWAP        BIT(16)
+#define  BLANK_COLOR_WHITE      BIT(17)
+#define  CMU_ENABLE             BIT(20)
+
+#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
+#define  SC0_H_QUALIFIER_NONE	BIT(0)
+#define  SC1_H_QUALIFIER_NONE	BIT(16)
+
+#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
+#define  DE_SELECT_ACTIVE_BLANK  (0 << 0)
+#define  DE_SELECT_ACTIVE        (1 << 0)
+#define  DE_SELECT_ACTIVE_IS     (2 << 0)
+#define  DE_CONTROL_ONECLK       (0 << 2)
+#define  DE_CONTROL_NORMAL       (1 << 2)
+#define  DE_CONTROL_EARLY_EXT    (2 << 2)
+#define  DE_CONTROL_EARLY        (3 << 2)
+#define  DE_CONTROL_ACTIVE_BLANK (4 << 2)
+
+// Cursor configuration registers.
+#define DC_DISP_CURSOR_FOREGROUND    0x43C
+#define DC_DISP_CURSOR_BACKGROUND    0x43D
+#define  CURSOR_COLOR(r,g,b) (((r) & 0xFF) | (((g) & 0xFF) << 8) | (((b) & 0xFF) << 16))
+
+#define DC_DISP_CURSOR_START_ADDR       0x43E
+#define DC_DISP_CURSOR_START_ADDR_NS    0x43F
+#define  CURSOR_CLIPPING(w) ((w) << 28)
+#define   CURSOR_CLIP_WIN_A 1
+#define   CURSOR_CLIP_WIN_B 2
+#define   CURSOR_CLIP_WIN_C 3
+#define  CURSOR_SIZE_32  (0 << 24)
+#define  CURSOR_SIZE_64  (1 << 24)
+#define  CURSOR_SIZE_128 (2 << 24)
+#define  CURSOR_SIZE_256 (3 << 24)
+#define DC_DISP_CURSOR_POSITION         0x440
+#define DC_DISP_CURSOR_START_ADDR_HI    0x4EC
+#define DC_DISP_CURSOR_START_ADDR_HI_NS 0x4ED
+#define DC_DISP_BLEND_CURSOR_CONTROL    0x4F1
+#define  CURSOR_BLEND_2BIT     (0 << 24)
+#define  CURSOR_BLEND_R8G8B8A8 (1 << 24)
+#define  CURSOR_BLEND_SRC_FACTOR(n) ((n) << 8)
+#define  CURSOR_BLEND_DST_FACTOR(n) ((n) << 16)
+#define   CURSOR_BLEND_ZRO 0
+#define   CURSOR_BLEND_K1  1
+#define   CURSOR_BLEND_NK1 2
+// End of cursor cfg regs.
+
+#define DC_DISP_DC_MCCIF_FIFOCTRL      0x480
+#define DC_DISP_SD_BL_PARAMETERS       0x4D7
+#define DC_DISP_SD_BL_CONTROL          0x4DC
+#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
+
+#define DC_DISP_DISPLAY_SPARE0         0x4F7 // Used by SW/HW.
+#define DC_DISP_DISPLAY_SPARE1         0x4F8
+
+#define DC_WINC_COLOR_PALETTE 0x500
+#define  COLOR_PALETTE_IDX(off) (DC_WINC_COLOR_PALETTE + (off))
+#define  COLOR_PALETTE_RGB(rgb) (byte_swap_32(rgb) >> 8)
+#define DC_WINC_PALETTE_COLOR_EXT 0x600
+
+#define DC_WINC_H_FILTER_P(p) (0x601 + (p))
+#define DC_WINC_V_FILTER_P(p) (0x619 + (p))
+#define DC_WINC_H_FILTER_HI_P(p) (0x629 + (p))
+
+#define DC_WINC_CSC_YOF 0x611
+#define DC_WINC_CSC_KYRGB 0x612
+#define DC_WINC_CSC_KUR 0x613
+#define DC_WINC_CSC_KVR 0x614
+#define DC_WINC_CSC_KUG 0x615
+#define DC_WINC_CSC_KVG 0x616
+#define DC_WINC_CSC_KUB 0x617
+#define DC_WINC_CSC_KVB 0x618
+#define DC_WIN_AD_WIN_OPTIONS 0xB80
+#define DC_WIN_BD_WIN_OPTIONS 0xD80
+#define DC_WIN_CD_WIN_OPTIONS 0xF80
+
+// The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
+#define DC_WIN_WIN_OPTIONS 0x700
+#define  H_DIRECTION          BIT(0)
+#define  V_DIRECTION          BIT(2)
+#define  SCAN_COLUMN          BIT(4)
+#define  COLOR_EXPAND         BIT(6)
+#define  H_FILTER_ENABLE      BIT(8)
+#define  V_FILTER_ENABLE      BIT(10)
+#define  COLOR_PALETTE_ENABLE BIT(16)
+#define  CSC_ENABLE           BIT(18)
+#define  DV_ENABLE            BIT(20)
+#define  WIN_ENABLE           BIT(30)
+#define  H_FILTER_EXPAND      BIT(31)
+
+#define DC_WIN_BUFFER_CONTROL 0x702
+#define  BUFFER_CONTROL_HOST  0
+#define  BUFFER_CONTROL_VI    1
+#define  BUFFER_CONTROL_SB2D  4
+
+#define DC_WIN_COLOR_DEPTH 0x703
+#define  WIN_COLOR_DEPTH_P1             0x0
+#define  WIN_COLOR_DEPTH_P2             0x1
+#define  WIN_COLOR_DEPTH_P4             0x2
+#define  WIN_COLOR_DEPTH_P8             0x3
+#define  WIN_COLOR_DEPTH_B4G4R4A4       0x4
+#define  WIN_COLOR_DEPTH_B5G5R5A        0x5
+#define  WIN_COLOR_DEPTH_B5G6R5         0x6
+#define  WIN_COLOR_DEPTH_AB5G5R5        0x7
+#define  WIN_COLOR_DEPTH_B8G8R8A8       0xC
+#define  WIN_COLOR_DEPTH_R8G8B8A8       0xD
+#define  WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE
+#define  WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF
+#define  WIN_COLOR_DEPTH_YCbCr422       0x10
+#define  WIN_COLOR_DEPTH_YUV422         0x11
+#define  WIN_COLOR_DEPTH_YCbCr420P      0x12
+#define  WIN_COLOR_DEPTH_YUV420P        0x13
+#define  WIN_COLOR_DEPTH_YCbCr422P      0x14
+#define  WIN_COLOR_DEPTH_YUV422P        0x15
+#define  WIN_COLOR_DEPTH_YCbCr422R      0x16
+#define  WIN_COLOR_DEPTH_YUV422R        0x17
+#define  WIN_COLOR_DEPTH_YCbCr422RA     0x18
+#define  WIN_COLOR_DEPTH_YUV422RA       0x19
+#define  WIN_COLOR_DEPTH_X1R5G5B5       0x1E
+#define  WIN_COLOR_DEPTH_R5G5B5X1       0x1F
+#define  WIN_COLOR_DEPTH_X1B5G5R5       0x20
+#define  WIN_COLOR_DEPTH_B5G5R5X1       0x21
+#define  WIN_COLOR_DEPTH_YCbCr444P      0x29
+#define  WIN_COLOR_DEPTH_YCrCb420SP     0x2A
+#define  WIN_COLOR_DEPTH_YCbCr420SP     0x2B
+#define  WIN_COLOR_DEPTH_YCrCb422SP     0x2C
+#define  WIN_COLOR_DEPTH_YCbCr422SP     0x2D
+#define  WIN_COLOR_DEPTH_YUV444P        0x34
+#define  WIN_COLOR_DEPTH_YVU420SP       0x35
+#define  WIN_COLOR_DEPTH_YUV420SP       0x36
+#define  WIN_COLOR_DEPTH_YVU422SP       0x37
+#define  WIN_COLOR_DEPTH_YUV422SP       0x38
+#define  WIN_COLOR_DEPTH_YVU444SP       0x3B
+#define  WIN_COLOR_DEPTH_YUV444SP       0x3C
+
+#define DC_WIN_POSITION 0x704
+#define  H_POSITION(x) (((x) & 0xFFFF) <<  0) // Support negative.
+#define  V_POSITION(x) (((x) & 0xFFFF) << 16) // Support negative.
+
+#define DC_WIN_SIZE 0x705
+#define  H_SIZE(x) (((x) & 0x1FFF) <<  0)
+#define  V_SIZE(x) (((x) & 0x1FFF) << 16)
+
+#define DC_WIN_PRESCALED_SIZE 0x706
+#define  H_PRESCALED_SIZE(x) (((x) & 0x7FFF) <<  0)
+#define  V_PRESCALED_SIZE(x) (((x) & 0x1FFF) << 16)
+
+#define DC_WIN_H_INITIAL_DDA 0x707
+#define DC_WIN_V_INITIAL_DDA 0x708
+
+#define DC_WIN_DDA_INC 0x709
+#define  H_DDA_INC(x) (((x) & 0xFFFF) <<  0)
+#define  V_DDA_INC(x) (((x) & 0xFFFF) << 16)
+
+#define DC_WIN_LINE_STRIDE 0x70A
+#define  LINE_STRIDE(x)	   (x)
+#define  UV_LINE_STRIDE(x) (((x) & 0xFFFF) << 16)
+
+#define DC_WIN_DV_CONTROL 0x70E
+#define DV_CTRL_R(r) (((r) & 7) << 16)
+#define DV_CTRL_G(g) (((g) & 7) << 8)
+#define DV_CTRL_B(b) (((b) & 7) << 0)
+
+#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716
+#define  WIN_BLEND_DEPTH(x) (((x) & 0xFF) << 0)
+#define  WIN_K1(x) (((x) & 0xFF) << 8)
+#define  WIN_K2(x) (((x) & 0xFF) << 16)
+#define  WIN_BLEND_ENABLE (0 << 24)
+#define  WIN_BLEND_BYPASS (1 << 24)
+
+#define DC_WINBUF_BLEND_MATCH_SELECT 0x717
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ZERO             (0 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ONE              (1 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1               (2 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_DST     (3 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (4 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC     (5 << 0)
+
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ZERO             (0 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ONE              (1 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1               (2 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K2               (3 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1_TIMES_DST     (4 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (5 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC (6 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1           (7 << 4)
+
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_ZERO             (0 << 8)
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K1               (1 << 8)
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2               (2 << 8)
+
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO             (0 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ONE              (1 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_NEG_K1_TIMES_SRC (2 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2               (3 << 12)
+
+#define DC_WINBUF_BLEND_ALPHA_1BIT 0x719
+#define  WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xFF) << 0)
+#define  WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xFF) << 8)
+
+/*! The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
+#define DC_WINBUF_START_ADDR 0x800
+#define DC_WINBUF_ADDR_H_OFFSET 0x806
+#define DC_WINBUF_ADDR_V_OFFSET 0x808
+#define DC_WINBUF_SURFACE_KIND 0x80B
+#define  PITCH	(0 << 0)
+#define  TILED	(1 << 0)
+#define  BLOCK	(2 << 0)
+#define  BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
+
+#define DC_WINBUF_MEMFETCH_CONTROL 0x82B
+
+/* Scratch register to store DCS backlight level (custom). */
+#define DC_DCS_BACKLIGHT_LEVEL DC_COM_SCRATCH_REGISTER_B
+
+/*! Display serial interface registers. */
+#define DSI_INCR_SYNCPT_CNTRL 0x1
+#define  DSI_INCR_SYNCPT_SOFT_RESET BIT(0)
+#define  DSI_INCR_SYNCPT_NO_STALL   BIT(8)
+
+#define DSI_RD_DATA 0x9
+#define DSI_WR_DATA 0xA
+
+#define DSI_POWER_CONTROL 0xB
+#define  DSI_POWER_CONTROL_ENABLE 1
+
+#define DSI_INT_ENABLE 0xC
+#define DSI_INT_STATUS 0xD
+#define DSI_INT_MASK 0xE
+
+#define DSI_HOST_CONTROL 0xF
+#define  DSI_HOST_CONTROL_ECC          BIT(0)
+#define  DSI_HOST_CONTROL_CS           BIT(1)
+#define  DSI_HOST_CONTROL_PKT_BTA      BIT(2)
+#define  DSI_HOST_CONTROL_IMM_BTA      BIT(3)
+#define  DSI_HOST_CONTROL_FIFO_SEL     BIT(4)
+#define  DSI_HOST_CONTROL_HS           BIT(5)
+#define  DSI_HOST_CONTROL_RAW          BIT(6)
+#define  DSI_HOST_CONTROL_TX_TRIG_MASK (3 << 12)
+#define  DSI_HOST_CONTROL_TX_TRIG_SOL  (0 << 12)
+#define  DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
+#define  DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
+#define  DSI_HOST_CONTROL_CRC_RESET    BIT(20)
+#define  DSI_HOST_CONTROL_FIFO_RESET   BIT(21)
+
+#define DSI_CONTROL 0x10
+#define  DSI_CONTROL_HOST_ENABLE  BIT(0)
+#define  DSI_CONTROL_VIDEO_ENABLE BIT(1)
+#define  DSI_CONTROL_SOURCE(s)    (((s) & 0x1) <<  2)
+#define  DSI_CONTROL_DCS_ENABLE   BIT(3)
+#define  DSI_CONTROL_LANES(n)     (((n) & 0x3) <<  4)
+#define  DSI_CONTROL_TX_TRIG(x)   (((x) & 0x3) <<  8)
+#define  DSI_CONTROL_FORMAT(f)    (((f) & 0x3) << 12)
+#define  DSI_CONTROL_CHANNEL(c)   (((c) & 0x3) << 16)
+#define  DSI_CONTROL_HS_CLK_CTRL  BIT(20)
+
+#define DSI_SOL_DELAY 0x11
+#define DSI_MAX_THRESHOLD 0x12
+
+#define DSI_TRIGGER 0x13
+#define  DSI_TRIGGER_VIDEO BIT(0)
+#define  DSI_TRIGGER_HOST  BIT(1)
+
+#define DSI_TX_CRC 0x14
+
+#define DSI_STATUS 0x15
+#define  DSI_STATUS_RX_FIFO_SIZE 0x1F
+#define  DSI_STATUS_TX_FIFO_SIZE 0x20 // Actual depth is 64.
+
+#define DSI_INIT_SEQ_CONTROL 0x1A
+#define DSI_INIT_SEQ_DATA_0 0x1B
+#define DSI_INIT_SEQ_DATA_1 0x1C
+#define DSI_INIT_SEQ_DATA_2 0x1D
+#define DSI_INIT_SEQ_DATA_3 0x1E
+#define DSI_PKT_SEQ_0_LO 0x23
+#define DSI_PKT_SEQ_0_HI 0x24
+#define DSI_PKT_SEQ_1_LO 0x25
+#define DSI_PKT_SEQ_1_HI 0x26
+#define DSI_PKT_SEQ_2_LO 0x27
+#define DSI_PKT_SEQ_2_HI 0x28
+#define DSI_PKT_SEQ_3_LO 0x29
+#define DSI_PKT_SEQ_3_HI 0x2A
+#define DSI_PKT_SEQ_4_LO 0x2B
+#define DSI_PKT_SEQ_4_HI 0x2C
+#define DSI_PKT_SEQ_5_LO 0x2D
+#define DSI_PKT_SEQ_5_HI 0x2E
+#define DSI_DCS_CMDS 0x33
+
+#define DSI_PKT_LEN_0_1 0x34
+#define DSI_PKT_LEN_2_3 0x35
+#define DSI_PKT_LEN_4_5 0x36
+#define DSI_PKT_LEN_6_7 0x37
+#define  PKT0_LEN(x) (((x) & 0xFFFF) <<  0)
+#define  PKT1_LEN(x) (((x) & 0xFFFF) << 16)
+
+#define DSI_PHY_TIMING_0 0x3C
+#define DSI_PHY_TIMING_1 0x3D
+#define DSI_PHY_TIMING_2 0x3E
+#define DSI_BTA_TIMING 0x3F
+
+#define DSI_TIMEOUT_0 0x44
+#define  DSI_TIMEOUT_HTX(x) (((x) & 0xFFFF) <<  0)
+#define  DSI_TIMEOUT_LRX(x) (((x) & 0xFFFF) << 16)
+
+#define DSI_TIMEOUT_1 0x45
+#define  DSI_TIMEOUT_TA(x) (((x) & 0xFFFF) <<  0)
+#define  DSI_TIMEOUT_PR(x) (((x) & 0xFFFF) << 16)
+
+#define DSI_TO_TALLY 0x46
+
+#define DSI_PAD_CONTROL_0 0x4B
+#define  DSI_PAD_CONTROL_VS1_PDIO_CLK   BIT(8)
+#define  DSI_PAD_CONTROL_VS1_PDIO(x)    (((x) & 0xF) <<  0)
+#define  DSI_PAD_CONTROL_VS1_PULLDN_CLK BIT(24)
+#define  DSI_PAD_CONTROL_VS1_PULLDN(x)  (((x) & 0xF) << 16)
+
+#define DSI_PAD_CONTROL_CD 0x4C
+#define DSI_VIDEO_MODE_CONTROL 0x4E
+#define  DSI_CMD_PKT_VID_ENABLE 1
+#define  DSI_DSI_LINE_TYPE(x) ((x) << 1)
+
+#define DSI_PAD_CONTROL_1 0x4F
+#define DSI_PAD_CONTROL_2 0x50
+
+#define DSI_PAD_CONTROL_3 0x51
+#define  DSI_PAD_PREEMP_PU(x)     (((x) & 0x3) << 0)
+#define  DSI_PAD_PREEMP_PD(x)     (((x) & 0x3) << 4)
+#define  DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
+#define  DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
+
+#define DSI_PAD_CONTROL_4 0x52
+#define DSI_PAD_CONTROL_5_B01 0x53
+#define DSI_PAD_CONTROL_6_B01 0x54
+#define DSI_PAD_CONTROL_7_B01 0x55
+#define DSI_INIT_SEQ_DATA_15 0x5F
+#define DSI_INIT_SEQ_DATA_15_B01 0x62
+
+/*! DSI packet defines */
+#define DSI_ESCAPE_CMD	0x87
+#define DSI_ACK_NO_ERR	0x84
+
+#define ACK_ERROR_RES   0x02
+#define GEN_LONG_RD_RES 0x1A
+#define DCS_LONG_RD_RES 0x1C
+#define GEN_1_BYTE_SHORT_RD_RES 0x11
+#define DCS_1_BYTE_SHORT_RD_RES 0x21
+#define GEN_2_BYTE_SHORT_RD_RES 0x12
+#define DCS_2_BYTE_SHORT_RD_RES 0x22
+
+/*! MIPI registers. */
+#define MIPI_CAL_MIPI_CAL_CTRL          (0x00 / 0x4)
+#define MIPI_CAL_CIL_MIPI_CAL_STATUS    (0x08 / 0x4)
+#define MIPI_CAL_CILA_MIPI_CAL_CONFIG   (0x14 / 0x4)
+#define MIPI_CAL_CILB_MIPI_CAL_CONFIG   (0x18 / 0x4)
+#define MIPI_CAL_CILC_MIPI_CAL_CONFIG   (0x1C / 0x4)
+#define MIPI_CAL_CILD_MIPI_CAL_CONFIG   (0x20 / 0x4)
+#define MIPI_CAL_CILE_MIPI_CAL_CONFIG   (0x24 / 0x4)
+#define MIPI_CAL_CILF_MIPI_CAL_CONFIG   (0x28 / 0x4)
+#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG   (0x38 / 0x4)
+#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG   (0x3C / 0x4)
+#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG   (0x40 / 0x4)
+#define MIPI_CAL_DSID_MIPI_CAL_CONFIG   (0x44 / 0x4)
+#define MIPI_CAL_MIPI_BIAS_PAD_CFG0     (0x58 / 0x4)
+#define MIPI_CAL_MIPI_BIAS_PAD_CFG1     (0x5C / 0x4)
+#define MIPI_CAL_MIPI_BIAS_PAD_CFG2     (0x60 / 0x4)
+#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x64 / 0x4)
+#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x68 / 0x4)
+#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x70 / 0x4)
+#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4)
+
+/*! MIPI CMDs. */
+#define MIPI_DSI_V_SYNC_START        0x01
+#define MIPI_DSI_COLOR_MODE_OFF      0x02
+#define MIPI_DSI_END_OF_TRANSMISSION 0x08
+#define MIPI_DSI_NULL_PACKET         0x09
+#define MIPI_DSI_V_SYNC_END          0x11
+#define MIPI_DSI_COLOR_MODE_ON       0x12
+#define MIPI_DSI_BLANKING_PACKET     0x19
+#define MIPI_DSI_H_SYNC_START        0x21
+#define MIPI_DSI_SHUTDOWN_PERIPHERAL 0x22
+#define MIPI_DSI_H_SYNC_END          0x31
+#define MIPI_DSI_TURN_ON_PERIPHERAL  0x32
+#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
+
+#define MIPI_DSI_DCS_SHORT_WRITE       0x05
+#define MIPI_DSI_DCS_READ              0x06
+#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15
+#define MIPI_DSI_DCS_LONG_WRITE        0x39
+
+#define MIPI_DSI_GENERIC_LONG_WRITE           0x29
+#define MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM  0x03
+#define MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM  0x13
+#define MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM  0x23
+#define MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM 0x04
+#define MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM 0x14
+#define MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM 0x24
+
+/*! MIPI DCS CMDs. */
+#define MIPI_DCS_NOP                   0x00
+#define MIPI_DCS_SOFT_RESET            0x01
+#define MIPI_DCS_GET_COMPRESSION_MODE  0x03
+#define MIPI_DCS_GET_DISPLAY_ID        0x04
+#define MIPI_DCS_GET_DISPLAY_ID1       0xDA // GET_DISPLAY_ID Byte0, Module Manufacturer ID.
+#define MIPI_DCS_GET_DISPLAY_ID2       0xDB // GET_DISPLAY_ID Byte1, Module/Driver Version ID.
+#define MIPI_DCS_GET_DISPLAY_ID3       0xDC // GET_DISPLAY_ID Byte2, Module/Driver ID.
+#define MIPI_DCS_GET_NUM_ERRORS        0x05 // 1 byte.
+#define MIPI_DCS_GET_RED_CHANNEL       0x06
+#define MIPI_DCS_GET_GREEN_CHANNEL     0x07
+#define MIPI_DCS_GET_BLUE_CHANNEL      0x08
+#define MIPI_DCS_GET_DISPLAY_STATUS    0x09 // 4 bytes.
+#define MIPI_DCS_GET_POWER_MODE	       0x0A // 1 byte. 2: DISON, 3: NORON, 4: SLPOUT, 7: BSTON.
+#define MIPI_DCS_GET_ADDRESS_MODE      0x0B // Display Access Control. 1 byte. 0: GS, 1: SS, 3: BGR.
+#define MIPI_DCS_GET_PIXEL_FORMAT      0x0C // 1 byte. 4-6: DPI.
+#define MIPI_DCS_GET_DISPLAY_MODE      0x0D // 1 byte. 0-2: GCS, 3: ALLPOFF, 4: ALLPON, 5: INVON.
+#define MIPI_DCS_GET_SIGNAL_MODE       0x0E // 1 byte. 0: EODSI, 2: DEON, 3: PCLKON, 4: VSON, 5: HSON, 7: TEON.
+#define MIPI_DCS_GET_DIAGNOSTIC_RESULT 0x0F // 1 byte. 6: FUNDT, 7: REGLD.
+#define MIPI_DCS_ENTER_SLEEP_MODE      0x10
+#define MIPI_DCS_EXIT_SLEEP_MODE       0x11
+#define MIPI_DCS_ENTER_PARTIAL_MODE    0x12
+#define MIPI_DCS_ENTER_NORMAL_MODE     0x13
+#define MIPI_DCS_EXIT_INVERT_MODE      0x20
+#define MIPI_DCS_ENTER_INVERT_MODE     0x21
+#define MIPI_DCS_ALL_PIXELS_OFF        0x22
+#define MIPI_DCS_ALL_PIXELS_ON         0x23
+#define MIPI_DCS_SET_CONTRAST          0x25 // VCON in 40mV steps. 7-bit integer.
+#define MIPI_DCS_SET_GAMMA_CURVE       0x26 // 1 byte. 0-7: GC.
+#define MIPI_DCS_SET_DISPLAY_OFF       0x28
+#define MIPI_DCS_SET_DISPLAY_ON        0x29
+#define MIPI_DCS_SET_COLUMN_ADDRESS    0x2A
+#define MIPI_DCS_SET_PAGE_ADDRESS      0x2B
+#define MIPI_DCS_WRITE_MEMORY_START    0x2C
+#define MIPI_DCS_WRITE_LUT             0x2D // 24-bit: 192 bytes.
+#define MIPI_DCS_READ_MEMORY_START     0x2E
+#define MIPI_DCS_SET_PARTIAL_ROWS      0x30
+#define MIPI_DCS_SET_PARTIAL_COLUMNS   0x31
+#define MIPI_DCS_SET_SCROLL_AREA       0x33
+#define MIPI_DCS_SET_TEAR_OFF          0x34
+#define MIPI_DCS_SET_TEAR_ON           0x35
+#define MIPI_DCS_SET_ADDRESS_MODE      0x36 // Display Access Control. 1 byte. 0: GS, 1: SS, 3: BGR.
+#define MIPI_DCS_SET_SCROLL_START      0x37
+#define MIPI_DCS_EXIT_IDLE_MODE        0x38
+#define MIPI_DCS_ENTER_IDLE_MODE       0x39
+#define MIPI_DCS_SET_PIXEL_FORMAT      0x3A // 1 byte. 4-6: DPI.
+#define MIPI_DCS_WRITE_MEMORY_CONTINUE 0x3C
+#define MIPI_DCS_READ_MEMORY_CONTINUE  0x3E
+#define MIPI_DCS_GET_3D_CONTROL        0x3F
+#define MIPI_DCS_SET_VSYNC_TIMING      0x40
+#define MIPI_DCS_SET_TEAR_SCANLINE     0x44
+#define MIPI_DCS_GET_SCANLINE          0x45
+#define MIPI_DCS_SET_TEAR_SCANLINE_WIDTH 0x46
+#define MIPI_DCS_GET_SCANLINE_WIDTH    0x47
+#define MIPI_DSI_AREA_COLOR_MODE       0x4C
+#define MIPI_DCS_SET_BRIGHTNESS        0x51 // DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL. 1 byte. 0-7: DBV.
+#define MIPI_DCS_GET_BRIGHTNESS        0x52 // 1 byte. 0-7: DBV.
+#define MIPI_DCS_SET_CONTROL_DISPLAY   0x53 // 1 byte. 2: BL, 3: DD, 5: BCTRL.
+#define MIPI_DCS_GET_CONTROL_DISPLAY   0x54 // 1 byte. 2: BL, 3: DD, 5: BCTRL.
+#define MIPI_DCS_SET_CABC_VALUE        0x55 // 1 byte. 0-32: C, 4-7: C.
+#define MIPI_DCS_GET_CABC_VALUE        0x56 // 1 byte. 0-32: C, 4-7: C.
+#define MIPI_DCS_SET_CABC_MIN_BRI      0x5E // 1 byte. 0-7: CMB.
+#define MIPI_DCS_GET_CABC_MIN_BRI      0x5F // 1 byte. 0-7: CMB.
+#define MIPI_DCS_GET_AUTO_BRI_DIAG_RES 0x68 // 1 byte. 6-7: D.
+#define MIPI_DCS_READ_DDB_START        0xA1
+#define MIPI_DCS_READ_DDB_CONTINUE     0xA8 // 0x100 size.
+
+/*! MIPI DCS Panel Private CMDs. */
+#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE 0xA0 // 43 bytes.
+#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET 0xB0
+#define MIPI_DCS_PRIV_SM_SET_ELVSS      0xB1 // OLED backlight tuning. Byte7: PWM transition time in frames.
+#define MIPI_DCS_PRIV_SET_POWER_CONTROL 0xB1
+#define MIPI_DCS_PRIV_SET_EXTC          0xB9 // Enable extended commands.
+#define MIPI_DCS_PRIV_UNK_BD            0xBD
+#define MIPI_DCS_PRIV_UNK_D5            0xD5
+#define MIPI_DCS_PRIV_UNK_D6            0xD6
+#define MIPI_DCS_PRIV_UNK_D8            0xD8
+#define MIPI_DCS_PRIV_UNK_D9            0xD9
+#define MIPI_DCS_PRIV_SM_DISPLAY_ID     0xDD
+											 //                          LVL1 LVL2 LVL3 UNK0 UNK1
+#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK  0xE2 // Samsung: Lock (default): 5A5A A5A5 A5A5 A500 A500. Lock/Unlock: A5/5A. LVL1 group is normal registers.
+#define MIPI_DCS_PRIV_READ_EXTC_CMD_SPI 0xFE // Read EXTC Command In SPI. 1 byte. 0-6: EXT_SPI_CNT, 7:EXT_SP.
+#define MIPI_DCS_PRIV_SET_EXTC_CMD_REG  0xFF // EXTC Command Set enable register. 5 bytes. Pass: FF 98 06 04, PAGE.
+
+/*! MIPI DCS Panel Private CMDs PAGE 1. */
+#define MIPI_DCS_PRIV_GET_DISPLAY_ID4   0x00
+#define MIPI_DCS_PRIV_GET_DISPLAY_ID5   0x01
+#define MIPI_DCS_PRIV_GET_DISPLAY_ID6   0x02
+
+/*! MIPI DCS CMD Defines. */
+#define DCS_POWER_MODE_DISPLAY_ON           BIT(2)
+#define DCS_POWER_MODE_NORMAL_MODE          BIT(3)
+#define DCS_POWER_MODE_SLEEP_MODE           BIT(4)
+#define DCS_POWER_MODE_PARTIAL_MODE         BIT(5)
+#define DCS_POWER_MODE_IDLE_MODE            BIT(6)
+
+#define DCS_ADDRESS_MODE_V_FLIP             BIT(0)
+#define DCS_ADDRESS_MODE_H_FLIP             BIT(1)
+#define DCS_ADDRESS_MODE_LATCH_RL           BIT(2) // Latch Data Order.
+#define DCS_ADDRESS_MODE_BGR_COLOR          BIT(3)
+#define DCS_ADDRESS_MODE_LINE_ORDER         BIT(4) // Line Refresh Order.
+#define DCS_ADDRESS_MODE_SWAP_XY            BIT(5) // Page/Column Addressing Reverse Order.
+#define DCS_ADDRESS_MODE_MIRROR_X           BIT(6) // Column Address Order.
+#define DCS_ADDRESS_MODE_MIRROR_Y           BIT(7) // Page Address Order.
+#define DCS_ADDRESS_MODE_ROTATION_MASK      (0xF << 4)
+#define DCS_ADDRESS_MODE_ROTATION_90        (DCS_ADDRESS_MODE_SWAP_XY | DCS_ADDRESS_MODE_LINE_ORDER)
+#define DCS_ADDRESS_MODE_ROTATION_180       (DCS_ADDRESS_MODE_MIRROR_X | DCS_ADDRESS_MODE_LINE_ORDER)
+#define DCS_ADDRESS_MODE_ROTATION_270       (DCS_ADDRESS_MODE_SWAP_XY)
+
+#define DCS_GAMMA_CURVE_NONE                0
+#define DCS_GAMMA_CURVE_GC0_1_8             BIT(0)
+#define DCS_GAMMA_CURVE_GC1_2_5             BIT(1)
+#define DCS_GAMMA_CURVE_GC2_1_0             BIT(2)
+#define DCS_GAMMA_CURVE_GC3_1_0             BIT(3) // Are there more?
+
+#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT   BIT(2)
+#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL  BIT(2)
+#define DCS_CONTROL_DISPLAY_DIMMING_CTRL    BIT(3) // Transition fading.
+#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5)
+#define DCS_CONTROL_DISPLAY_HBM_CTRL0       BIT(6)
+#define DCS_CONTROL_DISPLAY_HBM_CTRL1       BIT(7)
+
+#define DCS_SM_COLOR_MODE_SATURATED 0x00 // Disabled. Based on Vivid but over-saturated.
+#define DCS_SM_COLOR_MODE_WASHED    0x45
+#define DCS_SM_COLOR_MODE_BASIC     0x03 // Real natural profile.
+#define DCS_SM_COLOR_MODE_POR_RESET 0x20 // Reset value on power on.
+#define DCS_SM_COLOR_MODE_NATURAL   0x23 // Not actually natural.. Extra saturation.
+#define DCS_SM_COLOR_MODE_VIVID     0x65 // Saturated.
+#define DCS_SM_COLOR_MODE_NIGHT0    0x43 // Based on Washed Out.
+#define DCS_SM_COLOR_MODE_NIGHT1    0x15 // Based on Basic.
+#define DCS_SM_COLOR_MODE_NIGHT2    0x35 // Based on Natural.
+#define DCS_SM_COLOR_MODE_NIGHT3    0x75 // Based on Vivid.
+
+#define DCS_SM_COLOR_MODE_ENABLE    BIT(0)
+
+#define PANEL_SM_BL_CANDELA_MAX 2047
+
+/* Switch Panels:
+ *
+ * 6.2" panels for Icosa and Iowa SKUs:
+ * [10] 81 [26]: JDI LPM062M326A
+ * [10] 96 [09]: JDI LAM062M109A
+ * [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
+ * [20] 95 [0F]: InnoLux P062CCA-AZ2 (Rev B1)
+ * [20] 96 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [20] 97 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [20] 98 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [20] 99 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [30] 93 [0F]: AUO A062TAN00 (59.06A33.000)
+ * [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
+ * [30] 95 [0F]: AUO A062TAN02 (59.06A33.002)
+ * [30] 97 [0F]: AUO A062TAN02 (59.06A33.002) [From photo of assumed same panel]
+ * [30] 98 [0F]: AUO A062TAN0? [UNCONFIRMED MODEL]
+ * [30] XX [0F]: AUO A062TAN03 (59.06A33.003) [UNCONFIRMED ID]
+ * [E0] 01 [0F]: Retro Remake SUPER7 IPS (Rev 01)
+ * [E1] 01 [0F]: Retro Remake SUPER7 IPS HD (Rev 01)
+ * [E0] 11 [0F]: Retro Remake SUPER7 OLED (Rev 01)
+ * [E1] 11 [0F]: Retro Remake SUPER7 OLED HD (Rev 01)
+ *
+ * 5.5" panels for Hoag SKU:
+ * [20] 94 [10]: InnoLux 2J055IA-27A (Rev B1) (6203B001P4000)
+ * [20] 95 [10]: InnoLux 2J055IA-27A (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [20] 96 [10]: InnoLux 2J055IA-27A (Rev XX) [UNCONFIRMED MODEL+REV]
+ * [30] 93 [10]: AUO A055TAN01 (59.05A30.001)
+ * [30] 94 [10]: AUO A055TAN02 (59.05A30.002)
+ * [30] 95 [10]: AUO A055TAN03 (59.05A30.003)
+ * [40] 94 [10]: Sharp LQ055T1SW10 (Rev P)
+ * [E0] 01 [10]: Retro Remake SUPER5 OLED (Rev 01)
+ * [E1] 01 [10]: Retro Remake SUPER5 OLED HD (Rev 01)
+ *
+ * 7.0" OLED panels for Aula SKU:
+ * [50] 9B [20]: Samsung AMS699VC01-0 (Rev 2.5)
+ * [E0] 01 [20]: Retro Remake SUPER7 OLED (Rev 01)
+ * [E1] 01 [20]: Retro Remake SUPER7 OLED HD (Rev 01)
+ */
+
+/* Display ID Decoding:
+ *
+ * byte0: Vendor
+ * byte1: Model
+ * byte2: Board
+ *
+ * Vendors:
+ * 10h: Japan Display Inc.
+ * 20h: InnoLux Corporation
+ * 30h: AU Optronics
+ * 40h: Sharp
+ * 50h: Samsung
+ *
+ * Boards, Panel Size:
+ * 0Fh: Icosa/Iowa, 6.2"
+ * 10h: Hoag,       5.5"
+ * 20h: Aula,       7.0"
+ */
+
+enum
+{
+	PANEL_JDI_XXX062M     = 0x10,
+	PANEL_JDI_LAM062M109A = 0x0910, // SI.
+	PANEL_JDI_LPM062M326A = 0x2610, // LTPS.
+	PANEL_INL_P062CCA_AZ1 = 0x0F20,
+	PANEL_AUO_A062TAN01   = 0x0F30,
+	PANEL_INL_2J055IA_27A = 0x1020,
+	PANEL_AUO_A055TAN01   = 0x1030,
+	PANEL_SHP_LQ055T1SW10 = 0x1040,
+	PANEL_SAM_AMS699VC01  = 0x2050,
+	PANEL_RR_SUPER5_OLED_V1  = 0x10E0,
+	PANEL_RR_SUPER5_OLED_HD_V1  = 0x10E1,
+	PANEL_RR_SUPER7_IPS_V1  = 0x0FE0,
+	PANEL_RR_SUPER7_IPS_HD_V1  = 0x0FE1,
+	PANEL_RR_SUPER7_OLED_7V1  = 0x20E0,
+	PANEL_RR_SUPER7_OLED_HD_7V1  = 0x20E1,
+
+	// Found on 6/2" clones. Unknown markings. Clone of AUO A062TAN01.
+	// Quality seems JDI like. Has bad low backlight scaling. ID: [83] 94 [0F]. Sometimes reports [30] 94 [0F]. Both IDs have correct CRC16.
+	PANEL_OEM_CLONE_6_2   = 0x0F83,
+	// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
+	PANEL_OEM_CLONE_5_5   = 0x00B3,
+	// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
+	PANEL_OEM_CLONE       = 0x0000
+	//0x0F40 [40] 94 [0F], 5.5" clone
+};
+
+void display_init();
+void display_backlight_pwm_init();
+void display_end();
+
+/*! Interrupt management. */
+void display_enable_interrupt(u32 intr);
+void display_disable_interrupt(u32 intr);
+void display_wait_interrupt(u32 intr);
+
+/*! Get/Set Display panel ID. */
+u32  display_get_verbose_panel_id();
+u16  display_get_decoded_panel_id();
+void display_set_decoded_panel_id(u32 id);
+
+/*! MIPI DCS register management */
+int  display_dsi_read(u8 cmd, u32 len, void *data);
+int  display_dsi_vblank_read(u8 cmd, u32 len, void *data);
+void display_dsi_write(u8 cmd, u32 len, void *data);
+void display_dsi_vblank_write(u8 cmd, u32 len, void *data);
+
+/*! Show one single color on the display. */
+void display_color_screen(u32 color);
+
+/*! Screen backlight ON/OFF or set via duty and fading. */
+void display_backlight(bool enable);
+void display_backlight_brightness(u32 brightness, u32 step_delay);
+
+u32 *display_init_window_a_pitch();
+u32 *display_init_window_a_pitch_vic();
+u32 *display_init_window_a_pitch_inv();
+u32 *display_init_window_a_block();
+u32 *display_init_window_d_console();
+
+void display_window_disable(u32 window);
+
+void display_set_framebuffer(u32 window,  void *fb);
+void display_move_framebuffer(u32 window, void *fb);
+
+void display_window_d_console_enable();
+void display_window_d_console_disable();
+
+void display_cursor_init(void *crs_fb, u32 size);
+void display_cursor_set_pos(u32 x, u32 y);
+void display_cursor_deinit();
+
+#endif
--- a/bdk/display/di.inl
+++ b/bdk/display/di.inl
@@ -0,0 +1,549 @@
+/*
+* Copyright (c) 2018 naehrwert
+* Copyright (c) 2018-2025 CTCaer
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+// Display A config.
+static const reg_cfg_t _di_dc_init_config[] = {
+	/* Display init */
+	{DC_CMD_STATE_ACCESS, READ_MUX_ASSEMBLY | WRITE_MUX_ASSEMBLY},
+	{DC_CMD_REG_ACT_CONTROL, WIN_A_ACT_HCNTR_SEL | WIN_B_ACT_HCNTR_SEL | WIN_C_ACT_HCNTR_SEL | WIN_D_ACT_HCNTR_SEL},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_DISP_DC_MCCIF_FIFOCTRL, 0},
+	{DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
+	{DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
+	{DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
+	{DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
+	{DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | SYNCPT_VSYNC_INDX(9)},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_A_UPDATE  | WIN_B_UPDATE  | WIN_C_UPDATE  | WIN_D_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ},
+
+	/* Disable A/B/C/D Windows */
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT | WINDOW_D_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_WIN_DV_CONTROL,  0},
+
+	/* Setup default YUV colorspace conversion coefficients */
+	{DC_WINC_CSC_YOF,   0xF0},
+	{DC_WINC_CSC_KYRGB, 0x12A},
+	{DC_WINC_CSC_KUR,   0},
+	{DC_WINC_CSC_KVR,   0x198},
+	{DC_WINC_CSC_KUG,   0x39B},
+	{DC_WINC_CSC_KVG,   0x32F},
+	{DC_WINC_CSC_KUB,   0x204},
+	{DC_WINC_CSC_KVB,   0},
+
+	/* Init color, format and background */
+	{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
+	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
+	{DC_COM_PIN_OUTPUT_POLARITY(1), LSC0_OUTPUT_POLARITY_LOW},
+	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
+	{DC_DISP_BLEND_BACKGROUND_COLOR, 0},
+	{DC_COM_CRC_CONTROL, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_A_UPDATE  | WIN_B_UPDATE  | WIN_C_UPDATE  | WIN_D_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ},
+
+	/* Stop display */
+	{DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_BYPASS | WIN_BLEND_DEPTH(255)},
+	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_A_UPDATE  | WIN_B_UPDATE  | WIN_C_UPDATE  | WIN_D_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ}
+};
+
+// DSI Init config.
+static const reg_cfg_t _di_dsi_seq_pkt_reset_config0[] = {
+	{DSI_WR_DATA, 0},
+	{DSI_INT_ENABLE, 0},
+	{DSI_INT_STATUS, 0},
+	{DSI_INT_MASK,   0},
+	{DSI_INIT_SEQ_DATA_0, 0},
+	{DSI_INIT_SEQ_DATA_1, 0},
+	{DSI_INIT_SEQ_DATA_2, 0},
+	{DSI_INIT_SEQ_DATA_3, 0}
+};
+static const reg_cfg_t _di_dsi_seq_pkt_reset_config1[] = {
+	{DSI_DCS_CMDS, 0},
+	{DSI_PKT_SEQ_0_LO, 0},
+	{DSI_PKT_SEQ_1_LO, 0},
+	{DSI_PKT_SEQ_2_LO, 0},
+	{DSI_PKT_SEQ_3_LO, 0},
+	{DSI_PKT_SEQ_4_LO, 0},
+	{DSI_PKT_SEQ_5_LO, 0},
+	{DSI_PKT_SEQ_0_HI, 0},
+	{DSI_PKT_SEQ_1_HI, 0},
+	{DSI_PKT_SEQ_2_HI, 0},
+	{DSI_PKT_SEQ_3_HI, 0},
+	{DSI_PKT_SEQ_4_HI, 0},
+	{DSI_PKT_SEQ_5_HI, 0},
+	{DSI_CONTROL, 0}
+};
+static const reg_cfg_t _di_dsi_init_pads_t210b01[] = {
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PAD_CONTROL_2, 0},
+	{DSI_PAD_CONTROL_3, 0},
+	{DSI_PAD_CONTROL_4, 0},
+	{DSI_PAD_CONTROL_5_B01, 0},
+	{DSI_PAD_CONTROL_6_B01, 0},
+	{DSI_PAD_CONTROL_7_B01, 0}
+};
+static const reg_cfg_t _di_dsi_init_config[] = {
+	{DSI_PAD_CONTROL_CD, 0},
+	{DSI_SOL_DELAY,     24},
+	{DSI_MAX_THRESHOLD, 480},
+	{DSI_TRIGGER, 0},
+	{DSI_INIT_SEQ_CONTROL, 0},
+
+	{DSI_PKT_LEN_0_1, 0},
+	{DSI_PKT_LEN_2_3, 0},
+	{DSI_PKT_LEN_4_5, 0},
+	{DSI_PKT_LEN_6_7, 0},
+
+	{DSI_PAD_CONTROL_1, 0},
+
+	/* DSI PHY timings Init - 19.2 MHz */
+	{DSI_PHY_TIMING_0, 0x6070603},
+	{DSI_PHY_TIMING_1, 0x40A0E05},
+	{DSI_PHY_TIMING_2, 0x30109},
+	{DSI_BTA_TIMING,   0x190A14},
+	/* DSI timeout */
+	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
+	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765)   | DSI_TIMEOUT_TA(0x2000)},
+	{DSI_TO_TALLY, 0},
+
+	{DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Power up.
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+};
+
+// DSI LP config.
+static const reg_cfg_t _di_dsi_timing_lp_config[] = {
+	{DSI_PAD_CONTROL_1, 0},
+
+	/* DSI PHY timings LP - 50 MHz */
+	{DSI_PHY_TIMING_0, 0x6070603},
+	{DSI_PHY_TIMING_1, 0x40A0E05},
+	{DSI_PHY_TIMING_2, 0x30118},
+	{DSI_BTA_TIMING,   0x190A14},
+	/* DSI timeout */
+	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
+	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343)  | DSI_TIMEOUT_TA(0x2000)},
+	{DSI_TO_TALLY, 0},
+
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+	{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_MAX_THRESHOLD, 64},
+	{DSI_TRIGGER, 0},
+	{DSI_TX_CRC, 0},
+	{DSI_INIT_SEQ_CONTROL, 0}
+};
+
+// DSI panel JDI config.
+static const reg_cfg_t _di_dsi_panel_init_config_jdi[] = {
+	{DSI_WR_DATA, 0x0439},     // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xBD15},     // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0 to 0xBD.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x1939},     // MIPI_DSI_DCS_LONG_WRITE: 25 bytes.
+	{DSI_WR_DATA, 0xAAAAAAD8}, // Register: 0xD8.
+	{DSI_WR_DATA, 0xAAAAAAEB},
+	{DSI_WR_DATA, 0xAAEBAAAA},
+	{DSI_WR_DATA, 0xAAAAAAAA},
+	{DSI_WR_DATA, 0xAAAAAAEB},
+	{DSI_WR_DATA, 0xAAEBAAAA},
+	{DSI_WR_DATA, 0xAA},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x01BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 1 to 0xBD.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2739},     // MIPI_DSI_DCS_LONG_WRITE: 39 bytes.
+	{DSI_WR_DATA, 0xFFFFFFD8}, // Register: 0xD8.
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFF},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x02BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 2 to 0xBD.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xF39},      // MIPI_DSI_DCS_LONG_WRITE: 15 bytes.
+	{DSI_WR_DATA, 0xFFFFFFD8}, // Register: 0xD8.
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFF},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0 to 0xBD.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x06D915},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 6 to 0xD9.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x000000B9}, // MIPI_DCS_PRIV_SET_EXTC. Disable.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST}
+};
+
+// DSI HS packet config.
+static const reg_cfg_t _di_dsi_seq_pkt_video_non_burst_no_eot_config[] = {
+	{DSI_PAD_CONTROL_1, 0},
+
+	/* DSI PHY timings HP - 234 MHz */
+	{DSI_PHY_TIMING_0, 0x6070603},
+	{DSI_PHY_TIMING_1, 0x40A0E05},
+	{DSI_PHY_TIMING_2, 0x30172},
+	{DSI_BTA_TIMING,   0x190A14},
+	/* DSI timeout */
+	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
+	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F)  | DSI_TIMEOUT_TA(0x2000)},
+	{DSI_TO_TALLY, 0},
+
+	/* DSI packet sequence */
+	{DSI_PKT_SEQ_0_LO, 0x40000208},
+	{DSI_PKT_SEQ_2_LO, 0x40000308},
+	{DSI_PKT_SEQ_4_LO, 0x40000308},
+	{DSI_PKT_SEQ_1_LO, 0x40000308},
+	{DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
+	{DSI_PKT_SEQ_3_HI, 0x2CC},
+	{DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
+	{DSI_PKT_SEQ_5_HI, 0x2CC},
+	{DSI_PKT_LEN_0_1, PKT1_LEN(206)  | PKT0_LEN(0)},
+	{DSI_PKT_LEN_2_3, PKT1_LEN(2160) | PKT0_LEN(418)},
+	{DSI_PKT_LEN_4_5, PKT1_LEN(0)    | PKT0_LEN(400)},
+	{DSI_PKT_LEN_6_7, PKT1_LEN(0)    | PKT0_LEN(400)},
+	{DSI_HOST_CONTROL, 0}
+};
+
+// DSI mode config.
+static const reg_cfg_t _di_dsi_host_mode_config[] = {
+	{DSI_TRIGGER, 0},
+	{DSI_CONTROL, 0},
+	{DSI_SOL_DELAY, 6},
+	{DSI_MAX_THRESHOLD, 480},
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+	{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_TX_TRIG_SOL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_TX_TRIG_SOL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
+};
+
+// MIPI CAL config.
+static const reg_cfg_t _di_mipi_pad_cal_config[] = {
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0},
+	{MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000},
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG0,  0},
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0}
+};
+
+// DSI pad config.
+static const reg_cfg_t _di_dsi_pad_cal_config_t210[] = {
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PAD_CONTROL_2, 0},
+	{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
+	{DSI_PAD_CONTROL_4, 0}
+};
+static const reg_cfg_t _di_dsi_pad_cal_config_t210b01[] = {
+	{DSI_PAD_CONTROL_1,     0},
+	{DSI_PAD_CONTROL_2,     0},
+	{DSI_PAD_CONTROL_3,     0},
+	{DSI_PAD_CONTROL_4,     0x77777},
+	{DSI_PAD_CONTROL_5_B01, 0x77777},
+	{DSI_PAD_CONTROL_6_B01, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)},
+	{DSI_PAD_CONTROL_7_B01, 0}
+};
+
+// MIPI CAL config.
+static const reg_cfg_t _di_mipi_dsi_cal_prod_config_t210[] = {
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG,   0x200200},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG,   0x200200},
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}
+};
+static const reg_cfg_t _di_mipi_dsi_cal_prod_config_t210b01[] = {
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG,   0x200006},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG,   0x200006},
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}
+};
+static const reg_cfg_t _di_mipi_dsi_cal_unused_config[] = {
+	{MIPI_CAL_CILA_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILB_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILC_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILD_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILE_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILF_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_DSIC_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_DSID_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0},
+	{MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0},
+	{MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}
+};
+
+// Display A enable config.
+static const reg_cfg_t _di_dc_video_mode_config[] = {
+	/* Set panel timings */
+	{DC_DISP_DISP_TIMING_OPTIONS, VSYNC_H_POSITION(0)},
+	{DC_DISP_REF_TO_SYNC, V_REF_TO_SYNC(1)    | H_REF_TO_SYNC(0)},
+	{DC_DISP_SYNC_WIDTH,  V_SYNC_WIDTH(1)     | H_SYNC_WIDTH(72)},
+	{DC_DISP_BACK_PORCH,  V_BACK_PORCH(9)     | H_BACK_PORCH(72)},
+	{DC_DISP_FRONT_PORCH, V_FRONT_PORCH(10)   | H_FRONT_PORCH(136)},
+	{DC_DISP_ACTIVE,      V_DISP_ACTIVE(1280) | H_DISP_ACTIVE(720)},
+	/* End of Display timings */
+
+	{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
+	{DC_COM_PIN_OUTPUT_ENABLE(1), 0},
+	{DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
+
+	/* Start continuous display. */
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)},
+	{DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+};
+
+// Display A disable config.
+static const reg_cfg_t _di_dc_video_disable_config[] = {
+	{DC_CMD_INT_MASK, 0},
+	{DC_CMD_STATE_ACCESS, READ_MUX_ASSEMBLY | WRITE_MUX_ASSEMBLY},
+	{DC_CMD_INT_ENABLE, 0},
+	{DC_CMD_CONT_SYNCPT_VSYNC, 0},
+
+	/* Stop display. */
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)},
+	{DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	// TODO: LCD panels should sleep for 40ms here.
+	{DC_CMD_DISPLAY_POWER_CONTROL, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+};
+
+// DSI panel JDI deinit config.
+static const reg_cfg_t _di_dsi_panel_deinit_config_jdi[] = {
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2139},     // MIPI_DSI_DCS_LONG_WRITE: 33 bytes.
+	{DSI_WR_DATA, 0x191919D5}, // Register: 0xD5.
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
+	{DSI_WR_DATA, 0x4F0F41B1}, // MIPI_DCS_PRIV_SET_POWER_CONTROL.
+	{DSI_WR_DATA, 0xF179A433},
+	{DSI_WR_DATA, 0x002D81},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x000000B9}, // MIPI_DCS_PRIV_SET_EXTC. Disable.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST}
+};
+
+// DSI panel AUO deinit config.
+static const reg_cfg_t _di_dsi_panel_deinit_config_auo[] = {
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94).
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
+	{DSI_WR_DATA, 0x191919D5}, // Register: 0xD5.
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
+	{DSI_WR_DATA, 0x191919D6}, // Register: 0xD6.
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
+	{DSI_WR_DATA, 0x711148B1}, // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
+	// (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
+	{DSI_WR_DATA, 0x71143209},
+	{DSI_WR_DATA, 0x114D31},   // (Unknown).
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x000000B9}, // MIPI_DCS_PRIV_SET_EXTC. Disable.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST}
+};
+
+/*
+static const reg_cfg_t _di_init_config_invert[] = {
+	{DSI_WR_DATA, 0x239},
+	{DSI_WR_DATA, 0x02C1}, // INV_EN.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+};
+*/
+
+// Display A Window A one color config.
+static const reg_cfg_t _di_win_one_color[] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT | WINDOW_D_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} // Continuous display.
+};
+
+// Display A Window A linear pitch config.
+static const reg_cfg_t _di_winA_pitch[] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280)  | H_PRESCALED_SIZE(720 * 4)},
+	{DC_WIN_DDA_INC,        V_DDA_INC(0x1000)       | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE,           V_SIZE(1280)            | H_SIZE(720)},
+	{DC_WIN_LINE_STRIDE,    UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, PITCH},
+	{DC_WINBUF_START_ADDR, IPL_FB_ADDRESS}, // Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0},
+	{DC_WINBUF_ADDR_V_OFFSET, 0},
+	{DC_WIN_WIN_OPTIONS, WIN_ENABLE}, // Enable window AD.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_A_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
+};
+
+// Display A Window A linear pitch + Win D support config.
+static const reg_cfg_t _di_winA_pitch_vic[] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280)  | H_PRESCALED_SIZE(720 * 4)},
+	{DC_WIN_DDA_INC,        V_DDA_INC(0x1000)       | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE,           V_SIZE(1280)            | H_SIZE(720)},
+	{DC_WIN_LINE_STRIDE,    UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, PITCH},
+	{DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0},
+	{DC_WINBUF_ADDR_V_OFFSET, 0},
+	{DC_WIN_WIN_OPTIONS, WIN_ENABLE}, // Enable window AD.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_A_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
+};
+
+// Display A Window A linear pitch inverse + Win D support config.
+static const reg_cfg_t _di_winA_pitch_inv[] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280)  | H_PRESCALED_SIZE(720 * 4)},
+	{DC_WIN_DDA_INC,        V_DDA_INC(0x1000)       | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE,           V_SIZE(1280)            | H_SIZE(720)},
+	{DC_WIN_LINE_STRIDE,    UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, PITCH},
+	{DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0}, // Linear: 0x383FFC, Block: 0x3813FC.
+	{DC_WINBUF_ADDR_V_OFFSET, 1279}, // Linear: 1279, Block: 0.
+	{DC_WIN_WIN_OPTIONS, WIN_ENABLE | V_DIRECTION}, // Enable window AD.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_A_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
+};
+
+// Display A Window A block linear config.
+static const reg_cfg_t _di_winA_block[] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280)   | H_PRESCALED_SIZE(720 * 4)},
+	{DC_WIN_DDA_INC,        V_DDA_INC(0x1000)        | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE,           V_SIZE(1280)             | H_SIZE(720)},
+	{DC_WIN_LINE_STRIDE,    UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, BLOCK_HEIGHT(4) | BLOCK},
+	{DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, // Linear: 0x383FFC, Block: 0x3813FC. Block in HOS: 0x13FF.
+	{DC_WINBUF_ADDR_V_OFFSET, 0}, // Linear: 1279, Block: 0.
+	{DC_WIN_WIN_OPTIONS, WIN_ENABLE | SCAN_COLUMN | H_DIRECTION}, // Enable window AD. | SCAN_COLUMN | H_DIRECTION.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_A_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
+};
+
+// Display A Window D config.
+static const reg_cfg_t _di_winD_log[] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8},
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280)  | H_PRESCALED_SIZE(656 * 4)},
+	{DC_WIN_DDA_INC,        V_DDA_INC(0x1000)       | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE,           V_SIZE(1280)            | H_SIZE(656)},
+	{DC_WIN_LINE_STRIDE,    UV_LINE_STRIDE(656 * 2) | LINE_STRIDE(656 * 4)}, //656*2x656*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, PITCH},
+	{DC_WINBUF_START_ADDR, LOG_FB_ADDRESS}, // Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0},
+	{DC_WINBUF_ADDR_V_OFFSET, 0},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_ENABLE | WIN_K1(200) | WIN_BLEND_DEPTH(0)},
+	{DC_WINBUF_BLEND_MATCH_SELECT, WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 | WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE  | WIN_D_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_D_ACT_REQ},
+};
--- a/bdk/display/vic.c
+++ b/bdk/display/vic.c
@@ -0,0 +1,561 @@
+/*
+ * VIC (4.0) driver for Tegra X1
+ *
+ * Copyright (c) 2018-2024 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "vic.h"
+#include <mem/heap.h>
+#include <soc/bpmp.h>
+#include <soc/clock.h>
+#include <soc/timer.h>
+#include <soc/t210.h>
+#include <utils/types.h>
+
+/* VIC Private registers */
+#define PVIC_FALCON_PA_OFFSET 0x1000
+#define PVIC_FALCON_ADDR      0x10AC
+#define PVIC_FALCON_IDLESTATE 0x104C
+
+/* VIC Control and Status registers. */
+/* Fetch Control registers. */
+#define VIC_FC_COMPOSE                         0x10000
+#define  COMPOSE_START                          BIT(0)
+
+#define VIC_FC_CFG_STRUCT_SLOT_INDEX           0x10B00
+
+#define VIC_FC_CFG_STRUCT_SLOT_CFG0            0x10B04
+#define  SLOT_ENABLE                            BIT(0)
+#define  FIELD_CURRENT_ENABLE                   BIT(8)
+
+#define VIC_FC_CFG_STRUCT_SLOT_CFG2            0x10B0C
+#define  CACHE_WIDTH(n) ((n) << 16)
+#define  CACHE_WIDTH_16BX16                     0 // Block Linear.
+#define  CACHE_WIDTH_32BX8                      1 // Block Linear.
+#define  CACHE_WIDTH_64BX4                      2 // Block Linear, Pitch. Recommended.
+#define  CACHE_WIDTH_128BX2                     3 // Block Linear, Pitch.
+#define  CACHE_WIDTH_256BX1                     4 // Pitch.
+#define  OUTPUT_FLIP_X                          BIT(20)
+#define  OUTPUT_FLIP_Y                          BIT(21)
+#define  OUTPUT_TRANSPOSE                       BIT(22)
+
+#define VIC_FC_CFG_STRUCT_SLOT_SFC_SIZE        0x10B10
+#define VIC_FC_CFG_STRUCT_SLOT_LUMA_SIZE       0x10B14
+#define VIC_FC_CFG_STRUCT_SLOT_CHROMA_SIZE     0x10B18
+#define VIC_FC_CFG_STRUCT_SLOT_SRC_RECT_LR     0x10B1C
+#define VIC_FC_CFG_STRUCT_SLOT_SRC_RECT_TB     0x10B20
+#define VIC_FC_CFG_STRUCT_SLOT_DST_RECT_LR     0x10B30
+#define VIC_FC_CFG_STRUCT_SLOT_DST_RECT_TB     0x10B34
+#define VIC_FC_CFG_STRUCT_TGT_RECT_LR          0x10B38
+#define VIC_FC_CFG_STRUCT_TGT_RECT_TB          0x10B3C
+#define VIC_FC_SLOT_MAP                        0x10C00
+
+#define VIC_FC_FCE_CTRL                        0x11000
+#define  START_TRIGGER                          BIT(0)
+#define  HALT_TRIGGER                           BIT(1)
+#define  CLEAR_ERROR                            BIT(8)
+
+#define VIC_FC_FCE_UCODE_ADDR                  0x11200
+#define VIC_FC_FCE_UCODE_INST                  0x11300
+
+/* Surface List registers. */
+#define VIC_SL_CFG_STRUCT_SLOT_INDEX           0x12100
+#define VIC_SL_CFG_STRUCT_SLOT_DST_RECT_LR     0x12200
+#define VIC_SL_CFG_STRUCT_SLOT_DST_RECT_TB     0x12300
+#define VIC_SL_CFG_STRUCT_TGT_RECT_LR          0x12400
+#define VIC_SL_CFG_STRUCT_TGT_RECT_TB          0x12500
+#define VIC_SL_CFG_STRUCT_SLOT_CFG0            0x12600
+
+/* Surface Cache registers. */
+#define VIC_SC_PRAMBASE                        0x14000
+#define VIC_SC_PRAMSIZE                        0x14100
+#define VIC_SC_SFC0_BASE_LUMA(n)               (0x14300 + (n) * 0x100)
+
+/* Blending Output registers. */
+#define VIC_BL_TARGET_BASADR                   0x22000
+#define VIC_BL_CONFIG                          0x22800
+#define  SUBPARTITION_MODE                      BIT(0)
+#define  PROCESS_CFG_STRUCT_TRIGGER             BIT(2)
+#define  SLOTMASK(n) ((n) << 8)
+
+#define VIC_BL_CFG_STRUCT_CFG0                 0x22C00
+#define VIC_BL_CFG_STRUCT_SFC_SIZE             0x22C04
+#define VIC_BL_CFG_STRUCT_LUMA_SIZE            0x22C08
+#define VIC_BL_CFG_STRUCT_CHROMA_SIZE          0x22C0C
+#define VIC_BL_CFG_STRUCT_TGT_RECT_LR          0x22C10
+#define VIC_BL_CFG_STRUCT_TGT_RECT_TB          0x22C14
+
+// VIC_FC_CFG_STRUCT_SLOT_CFG2 & VIC_BL_CFG_STRUCT_CFG0.
+#define BLK_KIND(n)    ((n) << 8)
+#define  BLK_KIND_PITCH          0
+#define  BLK_KIND_GENERIC_16BX2  1
+#define BLK_HEIGHT(n)  ((n) << 12)
+#define  BLK_HEIGHT_ONE_GOB      0
+#define  BLK_HEIGHT_SIXTEEN_GOBS 4
+
+// Generic size macros.
+#define SIZE_WIDTH(n)  (((n) - 1) << 0)
+#define SIZE_HEIGHT(n) (((n) - 1) << 16)
+#define RECT_LEFT(n)   ((n) << 0)
+#define RECT_RIGHT(n)  (((n) - 1) << 16)
+#define RECT_TOP(n)    ((n) << 0)
+#define RECT_BOTTOM(n) (((n) - 1) << 16)
+
+#define FORMAT_PROGRESSIVE 0
+#define SOFT_CLAMP_MIN     0
+#define SOFT_CLAMP_MAX     0x3FFu
+#define ALPHA_1_0          0x3FFu
+
+typedef struct _OutputConfig {
+	u64 AlphaFillMode:3;
+	u64 AlphaFillSlot:3;
+	u64 BackgroundAlpha:10;
+	u64 BackgroundR:10;
+	u64 BackgroundG:10;
+	u64 BackgroundB:10;
+	u64 RegammaMode:2;
+	u64 OutputFlipX:1;
+	u64 OutputFlipY:1;
+	u64 OutputTranspose:1;
+	u64 rsvd1:1;
+	u64 rsvd2:12;
+	u64 TargetRectLeft:14;
+	u64 rsvd3:2;
+	u64 TargetRectRight:14;
+	u64 rsvd4:2;
+	u64 TargetRectTop:14;
+	u64 rsvd5:2;
+	u64 TargetRectBottom:14;
+	u64 rsvd6:2;
+} OutputConfig;
+
+typedef struct _OutputSurfaceConfig {
+	u64 OutPixelFormat:7;
+	u64 OutChromaLocHoriz:2;
+	u64 OutChromaLocVert:2;
+	u64 OutBlkKind:4;
+	u64 OutBlkHeight:4;
+	u64 rsvd0:3;
+	u64 rsvd1:10;
+	u64 OutSurfaceWidth:14;
+	u64 OutSurfaceHeight:14;
+	u64 rsvd2:4;
+	u64 OutLumaWidth:14;
+	u64 OutLumaHeight:14;
+	u64 rsvd3:4;
+	u64 OutChromaWidth:14;
+	u64 OutChromaHeight:14;
+	u64 rsvd4:4;
+} OutputSurfaceConfig;
+
+typedef struct _SlotConfig {
+	u64 SlotEnable:1;
+	u64 DeNoise:1;
+	u64 AdvancedDenoise:1;
+	u64 CadenceDetect:1;
+	u64 MotionMap:1;
+	u64 MMapCombine:1;
+	u64 IsEven:1;
+	u64 ChromaEven:1;
+	u64 CurrentFieldEnable:1;
+	u64 PrevFieldEnable:1;
+	u64 NextFieldEnable:1;
+	u64 NextNrFieldEnable:1;
+	u64 CurMotionFieldEnable:1;
+	u64 PrevMotionFieldEnable:1;
+	u64 PpMotionFieldEnable:1;
+	u64 CombMotionFieldEnable:1;
+	u64 FrameFormat:4;
+	u64 FilterLengthY:2;
+	u64 FilterLengthX:2;
+	u64 Panoramic:12;
+	u64 rsvd1:22;
+	u64 DetailFltClamp:6;
+	u64 FilterNoise:10;
+	u64 FilterDetail:10;
+	u64 ChromaNoise:10;
+	u64 ChromaDetail:10;
+	u64 DeinterlaceMode:4;
+	u64 MotionAccumWeight:3;
+	u64 NoiseIir:11;
+	u64 LightLevel:4;
+	u64 rsvd4:2;
+	u64 SoftClampLow:10;
+	u64 SoftClampHigh:10;
+	u64 rsvd5:3;
+	u64 rsvd6:9;
+	u64 PlanarAlpha:10;
+	u64 ConstantAlpha:1;
+	u64 StereoInterleave:3;
+	u64 ClipEnabled:1;
+	u64 ClearRectMask:8;
+	u64 DegammaMode:2;
+	u64 rsvd7:1;
+	u64 DecompressEnable:1;
+	u64 rsvd9:5;
+	u64 DecompressCtbCount:8;
+	u64 DecompressZbcColor:32;
+	u64 rsvd12:24;
+	u64 SourceRectLeft:30;
+	u64 rsvd14:2;
+	u64 SourceRectRight:30;
+	u64 rsvd15:2;
+	u64 SourceRectTop:30;
+	u64 rsvd16:2;
+	u64 SourceRectBottom:30;
+	u64 rsvd17:2;
+	u64 DestRectLeft:14;
+	u64 rsvd18:2;
+	u64 DestRectRight:14;
+	u64 rsvd19:2;
+	u64 DestRectTop:14;
+	u64 rsvd20:2;
+	u64 DestRectBottom:14;
+	u64 rsvd21:2;
+	u64 rsvd22:32;
+	u64 rsvd23:32;
+} SlotConfig;
+
+typedef struct _SlotSurfaceConfig {
+	u64 SlotPixelFormat:7;
+	u64 SlotChromaLocHoriz:2;
+	u64 SlotChromaLocVert:2;
+	u64 SlotBlkKind:4;
+	u64 SlotBlkHeight:4;
+	u64 SlotCacheWidth:3;
+	u64 rsvd0:10;
+	u64 SlotSurfaceWidth:14;
+	u64 SlotSurfaceHeight:14;
+	u64 rsvd1:4;
+	u64 SlotLumaWidth:14;
+	u64 SlotLumaHeight:14;
+	u64 rsvd2:4;
+	u64 SlotChromaWidth:14;
+	u64 SlotChromaHeight:14;
+	u64 rsvd3:4;
+} SlotSurfaceConfig;
+
+typedef struct _SlotStruct {
+	SlotConfig slot_cfg;
+	SlotSurfaceConfig slot_sfc_cfg;
+
+	// No need to configure. Reset to zeros.
+	u8 lumaKeyStruct[0x10];
+	u8 colorMatrixStruct[0x20];
+	u8 gamutMatrixStruct[0x20];
+	u8 blendingSlotStruct[0x10];
+} SlotStruct;
+
+typedef struct _vic_config_t {
+	// No need to configure. Reset to zeros.
+	u8 pipeConfig[0x10];
+
+	OutputConfig out_cfg;
+	OutputSurfaceConfig out_sfc_cfg;
+
+	// No need to configure. Reset to zeros.
+	u8 out_color_matrix[0x20];
+	u8 clear_rect[0x10 * 4];
+
+	SlotStruct slots[8];
+} vic_config_t;
+
+// VIC Fetch Control Engine microcode. Dumped from L4T r33.
+u8 vic_fce_ucode[] = {
+	0x66, 0x00, 0x00, 0x00, 0x60, 0x07, 0x00, 0x00, 0x42, 0x40, 0x10, 0x00, 0x4E, 0x01, 0x40, 0x00,
+	0x6A, 0x07, 0x00, 0x00, 0x6E, 0x23, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x4E, 0x01, 0x04, 0x00,
+	0x6A, 0x0B, 0x00, 0x00, 0x6E, 0x1F, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x4E, 0x01, 0x10, 0x00,
+	0x6A, 0x0F, 0x00, 0x00, 0x6E, 0x1F, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x48, 0x80, 0x02, 0x00,
+	0x0E, 0x11, 0x00, 0x00, 0x6A, 0x14, 0x00, 0x00, 0x6E, 0x08, 0x06, 0x00, 0x6C, 0x00, 0x00, 0x00,
+	0x4E, 0x01, 0x08, 0x00, 0x6A, 0x18, 0x00, 0x00, 0x6E, 0x26, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00,
+	0x4E, 0x01, 0x20, 0x00, 0x6A, 0x1C, 0x00, 0x00, 0x6E, 0x26, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00,
+	0x4E, 0x01, 0x02, 0x00, 0x6A, 0x20, 0x00, 0x00, 0x6E, 0x24, 0x00, 0x00, 0x6C, 0x00, 0x00, 0x00,
+	0x56, 0x00, 0x10, 0x00, 0x56, 0x40, 0x10, 0x00, 0x22, 0x41, 0x01, 0x00, 0x6C, 0x00, 0x00, 0x00,
+	0x62, 0x80, 0x01, 0x00, 0x60, 0x47, 0x00, 0x00, 0x60, 0x87, 0x00, 0x00, 0x01, 0x4A, 0x00, 0x00,
+	0x55, 0xC0, 0x20, 0x00, 0x00, 0x59, 0x00, 0x00, 0x60, 0x87, 0x00, 0x00, 0x60, 0xC7, 0x00, 0x00,
+	0x01, 0x93, 0x00, 0x00, 0x40, 0x82, 0x02, 0x00, 0x4E, 0x02, 0x00, 0x00, 0x6B, 0x34, 0x00, 0x00,
+	0x43, 0xC1, 0x10, 0x00, 0x42, 0x02, 0x03, 0x00, 0x00, 0x23, 0x01, 0x00, 0x24, 0xD4, 0x00, 0x00,
+	0x56, 0x40, 0x3D, 0x00, 0x04, 0xEB, 0x00, 0x00, 0x60, 0x07, 0x01, 0x00, 0x60, 0x47, 0x00, 0x00,
+	0x6A, 0x3E, 0x00, 0x00, 0x55, 0xC0, 0x30, 0x00, 0x48, 0x00, 0x01, 0x00, 0x48, 0x40, 0x01, 0x00,
+	0x48, 0x80, 0x01, 0x00, 0x6B, 0x28, 0x02, 0x00, 0x56, 0x40, 0x09, 0x00, 0x04, 0x4D, 0x01, 0x00,
+	0x06, 0x4D, 0x00, 0x00, 0x42, 0xC0, 0x03, 0x00, 0x56, 0x80, 0x09, 0x00, 0x04, 0xFE, 0x01, 0x00,
+	0x00, 0xF9, 0x01, 0x00, 0x4E, 0x02, 0x00, 0x00, 0x6B, 0x32, 0x02, 0x00, 0x55, 0x40, 0x2F, 0x00,
+	0x56, 0x80, 0x0D, 0x00, 0x4F, 0x00, 0x00, 0x00, 0x6A, 0x0D, 0x02, 0x00, 0x55, 0x40, 0x31, 0x00,
+	0x56, 0x80, 0x0B, 0x00, 0x0C, 0x2B, 0x00, 0x00, 0x6A, 0x13, 0x02, 0x00, 0x43, 0x45, 0x03, 0x00,
+	0x42, 0x86, 0x03, 0x00, 0x4D, 0x06, 0x02, 0x00, 0x6A, 0x0D, 0x02, 0x00, 0x42, 0x86, 0x03, 0x00,
+	0x22, 0x7E, 0x01, 0x00, 0x4E, 0x04, 0x00, 0x00, 0x6B, 0x32, 0x02, 0x00, 0x55, 0x40, 0x17, 0x00,
+	0x0D, 0x2C, 0x00, 0x00, 0x56, 0xC0, 0x09, 0x00, 0x6A, 0x1E, 0x02, 0x00, 0x48, 0xC0, 0x01, 0x00,
+	0x43, 0x04, 0x03, 0x00, 0x6C, 0x20, 0x02, 0x00, 0x55, 0x40, 0x19, 0x00, 0x01, 0x2C, 0x01, 0x00,
+	0x65, 0x23, 0x01, 0x00, 0x42, 0x42, 0x03, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x24, 0x14, 0x01, 0x00,
+	0x00, 0x2C, 0x01, 0x00, 0x24, 0x14, 0x01, 0x00, 0x00, 0x3C, 0x01, 0x00, 0x42, 0x04, 0x09, 0x00,
+	0x42, 0xC3, 0x02, 0x00, 0x65, 0x54, 0x01, 0x00, 0x65, 0x55, 0x01, 0x00, 0x42, 0x45, 0x0D, 0x00,
+	0x62, 0x03, 0x00, 0x00, 0x62, 0x44, 0x00, 0x00, 0x62, 0x85, 0x00, 0x00, 0x62, 0xC2, 0x00, 0x00,
+	0x22, 0x48, 0x1F, 0x00, 0x6F, 0x00, 0x00, 0x00, 0x48, 0x00, 0x01, 0x00, 0x6C, 0x28, 0x02, 0x00,
+	0x62, 0x80, 0x01, 0x00, 0x60, 0x07, 0x00, 0x00, 0x60, 0x47, 0x00, 0x00, 0x60, 0x87, 0x00, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x43, 0x00, 0x02, 0x00, 0x40, 0x00, 0x02, 0x00, 0x01, 0xCA, 0x01, 0x00,
+	0x60, 0x03, 0x01, 0x00, 0x01, 0xA0, 0x01, 0x00, 0x60, 0x40, 0x00, 0x00, 0x65, 0x01, 0x00, 0x00,
+	0x55, 0xC0, 0x2E, 0x00, 0x01, 0x18, 0x00, 0x00, 0x43, 0x00, 0x04, 0x00, 0x43, 0x41, 0x06, 0x00,
+	0x6F, 0x00, 0x00, 0x00, 0x61, 0xC1, 0x00, 0x00, 0x61, 0x42, 0x01, 0x00, 0x65, 0xB5, 0x00, 0x00,
+	0x65, 0x73, 0x01, 0x00, 0x65, 0x35, 0x01, 0x00, 0x65, 0x34, 0x01, 0x00, 0x42, 0x04, 0x0D, 0x00,
+	0x01, 0x14, 0x01, 0x00, 0x42, 0x04, 0x03, 0x00, 0x00, 0x20, 0x00, 0x00, 0x43, 0x03, 0x05, 0x00,
+	0x43, 0x85, 0x02, 0x00, 0x00, 0xAA, 0x00, 0x00, 0x48, 0x46, 0x01, 0x00, 0x65, 0xEB, 0x00, 0x00,
+	0x00, 0x9A, 0x00, 0x00, 0x65, 0xB2, 0x01, 0x00, 0x00, 0xA6, 0x01, 0x00, 0x42, 0x86, 0x0D, 0x00,
+	0x61, 0x42, 0x01, 0x00, 0x01, 0xAE, 0x01, 0x00, 0x00, 0x71, 0x00, 0x00, 0x42, 0x82, 0x08, 0x00,
+	0x42, 0xC3, 0x08, 0x00, 0x48, 0x40, 0x01, 0x00, 0x6F, 0x00, 0x00, 0x00, 0x6E, 0x34, 0x02, 0x00,
+	0x65, 0x79, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x6C, 0x36, 0x04, 0x00, 0x6E, 0x34, 0x02, 0x00,
+	0x48, 0x7F, 0x01, 0x00, 0x6C, 0x0A, 0x06, 0x00, 0x6E, 0x34, 0x02, 0x00, 0x6E, 0x05, 0x04, 0x00,
+	0x65, 0x79, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x41, 0x87, 0x03, 0x00, 0x65, 0xBA, 0x00, 0x00,
+	0x65, 0xB2, 0x00, 0x00, 0x42, 0x82, 0x02, 0x00, 0x00, 0x51, 0x00, 0x00, 0x61, 0xC1, 0x00, 0x00,
+	0x65, 0xFB, 0x00, 0x00, 0x65, 0xF3, 0x00, 0x00, 0x41, 0x87, 0x05, 0x00, 0x65, 0xF3, 0x00, 0x00,
+	0x42, 0xC3, 0x08, 0x00, 0x00, 0x59, 0x00, 0x00, 0x60, 0xC7, 0x00, 0x00, 0x60, 0xC7, 0x00, 0x00,
+	0x56, 0xC0, 0x21, 0x00, 0x04, 0xDF, 0x01, 0x00, 0x43, 0xC7, 0x15, 0x00, 0x00, 0x38, 0x00, 0x00,
+	0x00, 0x79, 0x00, 0x00, 0x42, 0xC3, 0x20, 0x00, 0x43, 0xC3, 0x04, 0x00, 0x42, 0x00, 0x30, 0x00,
+	0x42, 0x41, 0x30, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x4B, 0x00, 0x00, 0x60, 0xC7, 0x01, 0x00,
+	0x22, 0x78, 0x01, 0x00, 0x22, 0x79, 0x03, 0x00, 0x22, 0x7F, 0x1F, 0x00, 0x6F, 0x00, 0x00, 0x00,
+	0x6E, 0x34, 0x02, 0x00, 0x6E, 0x05, 0x04, 0x00, 0x4B, 0x41, 0x00, 0x00, 0x60, 0xC7, 0x01, 0x00,
+	0x60, 0x87, 0x01, 0x00, 0x43, 0x86, 0x15, 0x00, 0x00, 0x30, 0x00, 0x00, 0x65, 0x39, 0x01, 0x00,
+	0x42, 0x04, 0x05, 0x00, 0x4E, 0x05, 0x7E, 0x00, 0x6A, 0x1B, 0x06, 0x00, 0x55, 0xC0, 0x3D, 0x00,
+	0x0A, 0x3C, 0x01, 0x00, 0x60, 0xC7, 0x01, 0x00, 0x22, 0x78, 0x01, 0x00, 0x22, 0x79, 0x03, 0x00,
+	0x22, 0x7C, 0x09, 0x00, 0x22, 0x7F, 0x1F, 0x00, 0x6F, 0x00, 0x00, 0x00, 0x65, 0x7A, 0x01, 0x00,
+	0x42, 0x45, 0x05, 0x00, 0x65, 0xBB, 0x01, 0x00, 0x42, 0x86, 0x05, 0x00, 0x55, 0xC0, 0x3D, 0x00,
+	0x0A, 0x7D, 0x01, 0x00, 0x0A, 0xBE, 0x01, 0x00, 0x07, 0xC7, 0x01, 0x00, 0x0B, 0x7D, 0x01, 0x00,
+	0x0B, 0xBE, 0x01, 0x00, 0x55, 0xC0, 0x3D, 0x00, 0x0A, 0x3C, 0x01, 0x00, 0x60, 0xC7, 0x01, 0x00,
+	0x22, 0x78, 0x01, 0x00, 0x22, 0x79, 0x03, 0x00, 0x22, 0x7A, 0x05, 0x00, 0x22, 0x7B, 0x07, 0x00,
+	0x22, 0x7C, 0x09, 0x00, 0x22, 0x7D, 0x0B, 0x00, 0x22, 0x7E, 0x0D, 0x00, 0x22, 0x7F, 0x1F, 0x00,
+	0x6F, 0x00, 0x00, 0x00
+};
+
+vic_config_t __attribute__((aligned (0x100))) vic_cfg = {0};
+
+u32 _vic_read_priv(u32 addr)
+{
+	u32 addr_lsb = addr & 0xFF;
+
+	// Set address LSB.
+	if (addr_lsb)
+		VIC(PVIC_FALCON_ADDR) = addr_lsb >> 2;
+
+	// Set address.
+	u32 val = VIC(PVIC_FALCON_PA_OFFSET + (addr >> 6));
+
+	// Unset address LSB.
+	if (addr_lsb)
+		VIC(PVIC_FALCON_ADDR) = 0;
+
+	return val;
+}
+
+static void _vic_write_priv(u32 addr, u32 data)
+{
+	u32 addr_lsb = addr & 0xFF;
+
+	// Set address LSB.
+	if (addr_lsb)
+		VIC(PVIC_FALCON_ADDR) = addr_lsb >> 2;
+
+	// Set address.
+	VIC(PVIC_FALCON_PA_OFFSET + (addr >> 6)) = data;
+
+	// Unset address LSB.
+	if (addr_lsb)
+		VIC(PVIC_FALCON_ADDR) = 0;
+}
+
+int vic_wait_idle()
+{
+	u32 timeout_count = 15000; // 150ms.
+
+	while (VIC(PVIC_FALCON_IDLESTATE))
+	{
+		usleep(10);
+
+		timeout_count--;
+		if (!timeout_count)
+			return 1;
+	};
+
+	return 0;
+}
+
+void vic_set_surface(const vic_surface_t *sfc)
+{
+	u32 flip_x  = 0;
+	u32 flip_y  = 0;
+	u32 swap_xy = 0;
+	u32 const_alpha = 0;
+
+	u32 width   = sfc->width;
+	u32 height  = sfc->height;
+	u32 pix_fmt = sfc->pix_fmt;
+	u32 src_buf = sfc->src_buf;
+	u32 dst_buf = sfc->dst_buf;
+
+	// Get format alpha type.
+	switch (sfc->pix_fmt)
+	{
+	case VIC_PIX_FORMAT_L8:
+	case VIC_PIX_FORMAT_X1B5G5R5:
+	case VIC_PIX_FORMAT_B5G5R5X1:
+	case VIC_PIX_FORMAT_X8B8G8R8:
+	case VIC_PIX_FORMAT_X8R8G8B8:
+	case VIC_PIX_FORMAT_B8G8R8X8:
+	case VIC_PIX_FORMAT_R8G8B8X8:
+		const_alpha = 1;
+		break;
+
+	case VIC_PIX_FORMAT_A8B8G8R8:
+	case VIC_PIX_FORMAT_A8R8G8B8:
+	case VIC_PIX_FORMAT_B8G8R8A8:
+	case VIC_PIX_FORMAT_R8G8B8A8:
+	default:
+		break;
+	}
+
+	// Get rotation parameters.
+	switch (sfc->rotation)
+	{
+	case VIC_ROTATION_90:
+		swap_xy = 1;
+		break;
+
+	case VIC_ROTATION_180:
+		flip_x  = 1;
+		flip_y  = 1;
+		break;
+
+	case VIC_ROTATION_270:
+		flip_x  = 1;
+		swap_xy = 1;
+		break;
+
+	case VIC_ROTATION_0:
+	default:
+		break;
+	}
+
+	// Set output surface format.
+	vic_cfg.out_sfc_cfg.OutPixelFormat = pix_fmt;
+	vic_cfg.out_sfc_cfg.OutBlkKind     = BLK_KIND_PITCH;
+	vic_cfg.out_sfc_cfg.OutBlkHeight   = 0;
+
+	// Set output rotation/flip.
+	vic_cfg.out_cfg.OutputFlipX     = flip_x;
+	vic_cfg.out_cfg.OutputFlipY     = flip_y;
+	vic_cfg.out_cfg.OutputTranspose = swap_xy;
+
+	// Set output surface resolution.
+	vic_cfg.out_sfc_cfg.OutSurfaceWidth  = width  - 1;
+	vic_cfg.out_sfc_cfg.OutSurfaceHeight = height - 1;
+	vic_cfg.out_sfc_cfg.OutLumaWidth     = width  - 1;
+	vic_cfg.out_sfc_cfg.OutLumaHeight    = height - 1;
+
+	// Set output destination rectangle. Anything outside will not be touched at output buffer.
+	vic_cfg.out_cfg.TargetRectLeft   = 0;
+	vic_cfg.out_cfg.TargetRectRight  = width - 1;
+	vic_cfg.out_cfg.TargetRectTop    = 0;
+	vic_cfg.out_cfg.TargetRectBottom = height - 1;
+
+	// Initialize slot parameters.
+	vic_cfg.slots[0].slot_cfg.SlotEnable    = 1;
+	vic_cfg.slots[0].slot_cfg.SoftClampLow  = SOFT_CLAMP_MIN;
+	vic_cfg.slots[0].slot_cfg.SoftClampHigh = SOFT_CLAMP_MAX;
+	vic_cfg.slots[0].slot_cfg.PlanarAlpha   = ALPHA_1_0;
+	vic_cfg.slots[0].slot_cfg.ConstantAlpha = const_alpha;
+	vic_cfg.slots[0].slot_cfg.FrameFormat   = FORMAT_PROGRESSIVE;
+
+	// Set input source rectangle.
+	vic_cfg.slots[0].slot_cfg.SourceRectLeft   = 0;
+	vic_cfg.slots[0].slot_cfg.SourceRectRight  = (width  - 1) << 16;
+	vic_cfg.slots[0].slot_cfg.SourceRectTop    = 0;
+	vic_cfg.slots[0].slot_cfg.SourceRectBottom = (height - 1) << 16;
+
+	// Set input destination rectangle.
+	vic_cfg.slots[0].slot_cfg.DestRectLeft   = 0;
+	vic_cfg.slots[0].slot_cfg.DestRectRight  = (width  - 1);
+	vic_cfg.slots[0].slot_cfg.DestRectTop    = 0;
+	vic_cfg.slots[0].slot_cfg.DestRectBottom = (height - 1);
+
+	// Set input surface format.
+	vic_cfg.slots[0].slot_sfc_cfg.SlotPixelFormat = pix_fmt;
+	vic_cfg.slots[0].slot_sfc_cfg.SlotBlkKind     = BLK_KIND_PITCH;
+	vic_cfg.slots[0].slot_sfc_cfg.SlotBlkHeight   = 0;
+	vic_cfg.slots[0].slot_sfc_cfg.SlotCacheWidth  = CACHE_WIDTH_64BX4;
+
+	// Set input surface resolution.
+	vic_cfg.slots[0].slot_sfc_cfg.SlotSurfaceWidth  = width  - 1;
+	vic_cfg.slots[0].slot_sfc_cfg.SlotSurfaceHeight = height - 1;
+	vic_cfg.slots[0].slot_sfc_cfg.SlotLumaWidth     = width  - 1;
+	vic_cfg.slots[0].slot_sfc_cfg.SlotLumaHeight    = height - 1;
+
+	// Flush data.
+	bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false);
+
+	// Set parameters base and size. Causes a parse by surface cache.
+	_vic_write_priv(VIC_SC_PRAMBASE, (u32)&vic_cfg >> 8);
+	_vic_write_priv(VIC_SC_PRAMSIZE, sizeof(vic_config_t) >> 6);
+
+	// Wait for surface cache to get ready.
+	vic_wait_idle();
+
+	// Set slot mapping.
+	_vic_write_priv(VIC_FC_SLOT_MAP, 0xFFFFFFF0);
+
+	// Set input surface buffer.
+	_vic_write_priv(VIC_SC_SFC0_BASE_LUMA(0), src_buf >> 8);
+
+	// Set output surface buffer.
+	_vic_write_priv(VIC_BL_TARGET_BASADR, dst_buf >> 8);
+
+	// Set blending config and push changes to surface cache.
+	_vic_write_priv(VIC_BL_CONFIG, SLOTMASK(0x1F) | PROCESS_CFG_STRUCT_TRIGGER | SUBPARTITION_MODE);
+
+	// Wait for surface cache to get ready.
+	vic_wait_idle();
+}
+
+int vic_compose()
+{
+	// Wait for surface cache to get ready. Otherwise VIC will hang.
+	int res = vic_wait_idle();
+
+	// Start composition of a single frame.
+	_vic_write_priv(VIC_FC_COMPOSE, COMPOSE_START);
+
+	return res;
+}
+
+int vic_init()
+{
+	clock_enable_vic();
+
+	// Load Fetch Control Engine microcode.
+	for (u32 i = 0; i < sizeof(vic_fce_ucode) / sizeof(u32); i++)
+	{
+		_vic_write_priv(VIC_FC_FCE_UCODE_ADDR, (i * sizeof(u32)));
+		_vic_write_priv(VIC_FC_FCE_UCODE_INST, *(u32 *)&vic_fce_ucode[i * sizeof(u32)]);
+	}
+
+	// Start Fetch Control Engine.
+	_vic_write_priv(VIC_FC_FCE_CTRL, START_TRIGGER);
+
+	return vic_wait_idle();
+}
+
+void vic_end()
+{
+	clock_disable_vic();
+}
--- a/bdk/display/vic.h
+++ b/bdk/display/vic.h
@@ -0,0 +1,67 @@
+/*
+ * VIC driver for Tegra X1
+ *
+ * Copyright (c) 2018-2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _VIC_H_
+#define _VIC_H_
+
+#include <utils/types.h>
+
+#define VIC_THI_SLCG_OVERRIDE_LOW_A 0x8C
+
+typedef enum _vic_rotation_t
+{
+	VIC_ROTATION_0   = 0,
+	VIC_ROTATION_90  = 1,
+	VIC_ROTATION_180 = 2,
+	VIC_ROTATION_270 = 3,
+} vic_rotation_t;
+
+typedef enum _vic_pix_format_t
+{
+	VIC_PIX_FORMAT_L8       =  1, //  8-bit LUT.
+	VIC_PIX_FORMAT_X1B5G5R5 = 21, // 16-bit XBGR.
+	VIC_PIX_FORMAT_B5G5R5X1 = 23, // 16-bit BGRX.
+
+	VIC_PIX_FORMAT_A8B8G8R8 = 31, // 32-bit ABGR.
+	VIC_PIX_FORMAT_A8R8G8B8 = 32, // 32-bit ARGB.
+	VIC_PIX_FORMAT_B8G8R8A8 = 33, // 32-bit BGRA.
+	VIC_PIX_FORMAT_R8G8B8A8 = 34, // 32-bit RGBA.
+
+	VIC_PIX_FORMAT_X8B8G8R8 = 35, // 32-bit XBGR.
+	VIC_PIX_FORMAT_X8R8G8B8 = 36, // 32-bit XRGB.
+	VIC_PIX_FORMAT_B8G8R8X8 = 37, // 32-bit BGRX.
+	VIC_PIX_FORMAT_R8G8B8X8 = 38, // 32-bit RGBX.
+} vic_pix_format_t;
+
+typedef struct _vic_surface_t
+{
+	u32 src_buf;
+	u32 dst_buf;
+	u32 width;
+	u32 height;
+	u32 pix_fmt;
+	u32 rotation;
+} vic_surface_t;
+
+void vic_set_surface(const vic_surface_t *sfc);
+int  vic_wait_idle();
+int  vic_compose();
+int  vic_init();
+void vic_end();
+
+#endif
--- a/bdk/exception_handlers.S
+++ b/bdk/exception_handlers.S
@@ -41,9 +41,9 @@
 * 11111  | SYS  | r0–r7, SP,     LR,     PC, CPSR           | r0–r14,                   PC, CPSR
 */

-#define EXCP_EN_ADDR   0x4003FFFC
-#define EXCP_TYPE_ADDR 0x4003FFF8
-#define EXCP_LR_ADDR   0x4003FFF4
+#define EXCP_EN_ADDR   0x4003FF1C
+#define EXCP_TYPE_ADDR 0x4003FF18
+#define EXCP_LR_ADDR   0x4003FF14

 #define EXCP_VEC_BASE  0x6000F000
 #define EVP_COP_RESET_VECTOR          0x200
@@ -97,6 +97,10 @@ _irq_setup:
 	MSR CPSR, #(MODE_IRQ | IRQ | FIQ) /* IRQ mode, IRQ/FIQ disabled */
 	LDR SP, =0x40040000

+	/* Setup FIQ stack pointer */
+	MSR CPSR, #(MODE_FIQ | IRQ | FIQ) /* FIQ mode, IRQ/FIQ disabled */
+	LDR SP, =0x40040000
+
 	/* Setup SYS stack pointer */
 	MSR CPSR, #(MODE_SYS | IRQ | FIQ) /* SYSTEM mode, IRQ/FIQ disabled */
 	LDR SP, =0x4003FF00               /* Will be changed later to DRAM */
@@ -111,7 +115,9 @@ _irq_setup:
 	B ipl_main
 	B .

-_reset:
+.globl excp_reset
+.type excp_reset, %function
+excp_reset:
 	LDR R0, =EXCP_EN_ADDR
 	LDR R1, =0x30505645 /* EVP0 */
 	STR R1, [R0]        /* EVP0 in EXCP_EN_ADDR */
@@ -129,25 +135,25 @@ _reset_handler:
 	LDR R0, =EXCP_TYPE_ADDR
 	LDR R1, =0x545352   /* RST */
 	STR R1, [R0]        /* RST in EXCP_TYPE_ADDR */
-	B _reset
+	B excp_reset

 _undefined_handler:
 	LDR R0, =EXCP_TYPE_ADDR
 	LDR R1, =0x464455   /* UDF */
 	STR R1, [R0]        /* UDF in EXCP_TYPE_ADDR */
-	B _reset
+	B excp_reset

 _prefetch_abort_handler:
 	LDR R0, =EXCP_TYPE_ADDR
 	LDR R1, =0x54424150 /* PABT */
 	STR R1, [R0]        /* PABT in EXCP_TYPE_ADDR */
-	B _reset
+	B excp_reset

 _data_abort_handler:
 	LDR R0, =EXCP_TYPE_ADDR
 	LDR R1, =0x54424144 /* DABT */
 	STR R1, [R0]        /* DABT in EXCP_TYPE_ADDR */
-	B _reset
+	B excp_reset

 .globl irq_enable_cpu_irq_exceptions
 .type irq_enable_cpu_irq_exceptions, %function
--- a/bdk/fatfs_cfg.h
+++ b/bdk/fatfs_cfg.h
@@ -17,8 +17,12 @@
 #ifndef _FATFS_CFG_H_
 #define _FATFS_CFG_H_

+// define FFCFG_INC in a project to use a specific FatFS configuration.
+// Example: FFCFG_INC := '"../$(PROJECT_DIR)/libs/fatfs/ffconf.h"'
 #ifdef FFCFG_INC
 #include FFCFG_INC
+#else
+#include "fatfs_conf.h"
 #endif

 #endif
--- a/bdk/fatfs_conf.h
+++ b/bdk/fatfs_conf.h
@@ -0,0 +1,305 @@
+/*---------------------------------------------------------------------------/
+/  FatFs Functional Configurations
+/---------------------------------------------------------------------------*/
+
+#define FFCONF_DEF	86604	/* Revision ID */
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_READONLY	0
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+
+#define FF_FS_MINIMIZE	0
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: Basic functions are fully enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+
+#define FF_USE_STRFUNC	2
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+
+#define FF_USE_FIND		1
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+
+#define FF_USE_MKFS		0
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#if FF_USE_MKFS
+#define FF_MKFS_LABEL "SWITCH SD  "
+#endif
+/* This sets FAT/FAT32 label. Exactly 11 characters, all caps. */
+
+
+#define FF_USE_FASTSEEK	0
+/* This option switches fast seek function. (0:Disable or 1:Enable) */
+
+#define FF_FASTFS 0
+#if FF_FASTFS
+#undef FF_USE_FASTSEEK
+#define FF_USE_FASTSEEK	1
+#endif
+/* This option switches fast access to chained clusters. (0:Disable or 1:Enable) */
+
+
+#define FF_SIMPLE_GPT 1
+/* This option switches support for the first GPT partition. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_EXPAND	0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_CHMOD	1
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
+
+
+#define FF_USE_LABEL	0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FORWARD	0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_CODE_PAGE	850
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect code page setting can cause a file open failure.
+/
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+/     0 - Include all code pages above and configured by f_setcp()
+*/
+
+
+#define FF_USE_LFN		3
+#define FF_MAX_LFN		255
+/* The FF_USE_LFN switches the support for LFN (long file name).
+/
+/   0: Disable LFN. FF_MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
+/  requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
+/  additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
+/  The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
+/  be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
+/  specification.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree() in ffsystem.c, need to be added to the project. */
+
+
+#define FF_LFN_UNICODE	0
+/* This option switches the character encoding on the API when LFN is enabled.
+/
+/   0: ANSI/OEM in current CP (TCHAR = char)
+/   1: Unicode in UTF-16 (TCHAR = WCHAR)
+/   2: Unicode in UTF-8 (TCHAR = char)
+/   3: Unicode in UTF-32 (TCHAR = DWORD)
+/
+/  Also behavior of string I/O functions will be affected by this option.
+/  When LFN is not enabled, this option has no effect. */
+
+
+#define FF_LFN_BUF		255
+#define FF_SFN_BUF		12
+/* This set of options defines size of file name members in the FILINFO structure
+/  which is used to read out directory items. These values should be suffcient for
+/  the file names to read. The maximum possible length of the read file name depends
+/  on character encoding. When LFN is not enabled, these options have no effect. */
+
+
+#define FF_STRF_ENCODE	0
+/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
+/  f_putc(), f_puts and f_printf() convert the character encoding in it.
+/  This option selects assumption of character encoding ON THE FILE to be
+/  read/written via those functions.
+/
+/   0: ANSI/OEM in current CP
+/   1: Unicode in UTF-16LE
+/   2: Unicode in UTF-16BE
+/   3: Unicode in UTF-8
+*/
+
+
+#define FF_FS_RPATH		0
+/* This option configures support for relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_VOLUMES		1
+/* Number of volumes (logical drives) to be used. (1-10) */
+
+
+#define FF_STR_VOLUME_ID	0
+#define FF_VOLUME_STRS		"sd"
+/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
+/  When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
+/  number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
+/  logical drives. Number of items must not be less than FF_VOLUMES. Valid
+/  characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
+/  compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
+/  not defined, a user defined volume string table needs to be defined as:
+/
+/  const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
+/  Order is important. Any change to order, must also be reflected to diskio drive enum.
+*/
+
+
+#define FF_MULTI_PARTITION	0
+/* This option switches support for multiple volumes on the physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When this function is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  funciton will be available. */
+
+
+#define FF_MIN_SS		512
+#define FF_MAX_SS		512
+/* This set of options configures the range of sector size to be supported. (512,
+/  1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
+/  for variable sector size mode and disk_ioctl() function needs to implement
+/  GET_SECTOR_SIZE command. */
+
+
+#define FF_USE_TRIM		0
+/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+
+#define FF_FS_NOFSINFO	1
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_TINY		0
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the filesystem object (FATFS) is used for the file data transfer. */
+
+
+#define FF_FS_EXFAT		1
+/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
+/  To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
+/  Note that enabling exFAT discards ANSI C (C89) compatibility. */
+
+
+#define FF_FS_NORTC		1
+#define FF_NORTC_MON	1
+#define FF_NORTC_MDAY	1
+#define FF_NORTC_YEAR	2022
+/* The option FF_FS_NORTC switches timestamp function. If the system does not have
+/  any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
+/  the timestamp function. Every object modified by FatFs will have a fixed timestamp
+/  defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
+/  To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to read current time form real-time clock. FF_NORTC_MON,
+/  FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
+/  These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
+
+
+#define FF_FS_LOCK		0
+/* The option FF_FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+
+/* #include <somertos.h>	// O/S definitions */
+#define FF_FS_REENTRANT	0
+#define FF_FS_TIMEOUT	1000
+#define FF_SYNC_t		HANDLE
+/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this function.
+/
+/   0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The FF_FS_TIMEOUT defines timeout period in unit of time tick.
+/  The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
+/  included somewhere in the scope of ff.h. */
+
+
+
+/*--- End of configuration options ---*/
--- a/bdk/gfx/di.c
+++ b/bdk/gfx/di.c
@@ -1,446 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <string.h>
-
-#include "di.h"
-#include <power/max77620.h>
-#include <power/max7762x.h>
-#include <soc/clock.h>
-#include <soc/gpio.h>
-#include <soc/i2c.h>
-#include <soc/pinmux.h>
-#include <soc/pmc.h>
-#include <soc/t210.h>
-#include <utils/util.h>
-
-#include "di.inl"
-
-extern volatile nyx_storage_t *nyx_str;
-
-static u32 _display_id = 0;
-
-void display_end();
-
-static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
-{
-	u32 end = get_tmr_us() + timeout;
-	while (get_tmr_us() < end && DSI(off) & mask)
-		;
-	usleep(5);
-}
-
-static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
-{
-	DSI(_DSIREG(DSI_WR_DATA)) = (param << 8) | cmd;
-	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-
-	if (wait)
-		usleep(wait);
-}
-
-void display_init()
-{
-	// Check if display is already initialized.
-	if (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) & 0x18000000)
-		display_end();
-
-	// Power on.
-	max77620_regulator_set_volt_and_flags(REGULATOR_LDO0, 1200000, MAX77620_POWER_MODE_NORMAL); // Configure to 1.2V.
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL);
-
-	// Enable Display Interface specific clocks.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000;  // Clear reset DSI, MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000;  // Set enable clock DSI, MIPI_CAL.
-
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000; // Set enable clock DISP1, HOST1X.
-
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000;    // Set enable clock UART_FST_MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
-
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000;    // Set enable clock DSIA_LP.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10;    // Set PLLP_OUT and div 6 (68MHz).
-
-	// Disable deep power down.
-	PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
-	PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
-
-	// Config LCD and Backlight pins.
-	PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE;     // PULL_DOWN
-	PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE;    // PULL_DOWN
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE;  // PULL_DOWN
-	PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE;    // PULL_DOWN
-
-	// Set Backlight +-5V pins mode and direction
-	gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO);
-	gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE);
-
-	// Enable Backlight power.
-	gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // Backlight +5V enable.
-	usleep(10000);
-	gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // Backlight -5V enable.
-	usleep(10000);
-
-	// Configure Backlight pins (PWM, EN, RST).
-	gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO);
-	gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
-	gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Enable Backlight EN.
-
-	// Power up supply regulator for display interface.
-	MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0;
-
-	// Set DISP1 clock source and parent clock.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT.
-	u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 96 MHz.
-	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;    // PLLD_SETUP.
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2D0AAA; // PLLD_ENABLE_CLK.
-
-	// Setup display communication interfaces.
-	exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94);
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config, 61);
-	usleep(10000);
-
-	// Enable Backlight Reset.
-	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH);
-	usleep(60000);
-
-	// Setups DSI packet configuration and request display id.
-	DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
-	_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 3, 0);
-	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
-
-	_display_dsi_send_cmd(MIPI_DSI_DCS_READ, MIPI_DCS_GET_DISPLAY_ID, 0);
-	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
-
-	DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
-	_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
-
-	usleep(5000);
-
-	// MIPI_DCS_GET_DISPLAY_ID reply is a long read, size 3 u32.
-	for (u32 i = 0; i < 3; i++)
-		_display_id = DSI(_DSIREG(DSI_RD_DATA)); // Skip ack and msg type info and get the payload (display id).
-
-	// Save raw Display ID to Nyx storage.
-	nyx_str->info.disp_id = _display_id;
-
-	// Decode Display ID.
-	_display_id = ((_display_id >> 8) & 0xFF00) | (_display_id & 0xFF);
-
-	if ((_display_id & 0xFF) == PANEL_JDI_XXX062M)
-		_display_id = PANEL_JDI_XXX062M;
-
-	// Initialize display panel.
-	switch (_display_id)
-	{
-	case PANEL_JDI_XXX062M:
-		exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43);
-		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
-		break;
-	case PANEL_INL_P062CCA_AZ1:
-	case PANEL_AUO_A062TAN01:
-		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x439;          // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9;     // Enable extension cmd. (Pass: FF 83 94).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x739;          // MIPI_DSI_DCS_LONG_WRITE: 7 bytes.
-		if (_display_id == PANEL_INL_P062CCA_AZ1)
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
-		else
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x143209;       // (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		break;
-	case PANEL_INL_P062CCA_AZ2:
-	case PANEL_AUO_A062TAN02:
-	default: // Allow spare part displays to work.
-		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 120000);
-		break;
-	}
-
-	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000);
-
-	// Configure PLLD for DISP1.
-	plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 460.8 MHz.
-	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;
-	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN.
-
-	// Finalize DSI configuration.
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 21);
-	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; // PCD1 | div3.
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10);
-	usleep(10000);
-
-	// Calibrate display communication pads.
-	exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 6);
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config, 4);
-	exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 16);
-	usleep(10000);
-
-	// Enable video display controller.
-	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113);
-}
-
-void display_backlight_pwm_init()
-{
-	clock_enable_pwm();
-
-	PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; // Enable PWM and set it to 25KHz PFM.
-
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC) | 1; // PWM clock source.
-	gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
-}
-
-void display_backlight(bool enable)
-{
-	gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO.
-}
-
-void display_backlight_brightness(u32 brightness, u32 step_delay)
-{
-	u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF;
-	if (brightness == old_value)
-		return;
-
-	if (brightness > 255)
-		brightness = 255;
-
-	if (old_value < brightness)
-	{
-		for (u32 i = old_value; i < brightness + 1; i++)
-		{
-			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
-			usleep(step_delay);
-		}
-	}
-	else
-	{
-		for (u32 i = old_value; i > brightness; i--)
-		{
-			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
-			usleep(step_delay);
-		}
-	}
-	if (!brightness)
-		PWM(PWM_CONTROLLER_PWM_CSR_0) = 0;
-}
-
-void display_end()
-{
-	display_backlight_brightness(0, 1000);
-
-	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
-	DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
-
-	DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
-	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet.
-
-	// De-initialize video controller.
-	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17);
-	exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16);
-	usleep(10000);
-
-	// De-initialize display panel.
-	switch (_display_id)
-	{
-	case PANEL_JDI_XXX062M:
-		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22);
-		break;
-	case PANEL_AUO_A062TAN01:
-		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_auo, 37);
-		break;
-	case PANEL_INL_P062CCA_AZ2:
-	case PANEL_AUO_A062TAN02:
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x439; // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9; // Enable extension cmd. (Pass: FF 83 94).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		// Set Power.
-		DSI(_DSIREG(DSI_WR_DATA)) = 0xB39; // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
-		if (_display_id == PANEL_INL_P062CCA_AZ2)
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
-		else
-			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
-		// Set Power control. (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x71143209;
-		DSI(_DSIREG(DSI_WR_DATA)) = 0x114D31; // Set Power control. (Unknown).
-		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
-		usleep(5000);
-		break;
-	case PANEL_INL_P062CCA_AZ1:
-	default:
-		break;
-	}
-
-	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_ENTER_SLEEP_MODE, 50000);
-
-	// Disable display and backlight pins.
-	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
-	usleep(10000);
-
-	gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable.
-	usleep(10000);
-
-	gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable.
-	usleep(10000);
-
-	// Disable Display Interface specific clocks.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000;  // Set reset clock DSI, MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000;  // Clear enable clock DSI, MIPI_CAL.
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1X.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000; // Clear enable DISP1, HOST1X.
-
-	// Power down pads.
-	DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
-	DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
-
-	// Switch to automatic function mode.
-	gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
-
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
-	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC)| 1;
-}
-
-void display_color_screen(u32 color)
-{
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8);
-
-	// Configure display to show single color.
-	DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
-	DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
-	DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
-	DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
-	usleep(35000);
-
-	display_backlight(true);
-}
-
-u32 *display_init_framebuffer_pitch()
-{
-	// Sanitize framebuffer area.
-	memset((u32 *)IPL_FB_ADDRESS, 0, 0x3C0000);
-
-	// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32);
-	usleep(35000);
-
-	return (u32 *)IPL_FB_ADDRESS;
-}
-
-u32 *display_init_framebuffer_pitch_inv()
-{
-	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch_inv, 34);
-
-	usleep(35000);
-
-	return (u32 *)NYX_FB_ADDRESS;
-}
-
-u32 *display_init_framebuffer_block()
-{
-	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 34);
-
-	usleep(35000);
-
-	return (u32 *)NYX_FB_ADDRESS;
-}
-
-u32 *display_init_framebuffer_log()
-{
-	// This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
-	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_log, 20);
-
-	return (u32 *)LOG_FB_ADDRESS;
-}
-
-void display_activate_console()
-{
-	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
-	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD.
-	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-
-	for (u32 i = 0xFF80; i < 0x10000; i++)
-	{
-		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-		usleep(1000);
-	}
-
-	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-}
-
-void display_deactivate_console()
-{
-	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
-
-	for (u32 i = 0xFFFF; i > 0xFF7F; i--)
-	{
-		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-		usleep(500);
-	}
-
-	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
-	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; // Disable window DD.
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
-}
-
-void display_init_cursor(void *crs_fb, u32 size)
-{
-	// Setup cursor.
-	DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10);
-	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) =
-		CURSOR_BLEND_R8G8B8A8 | CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF;
-
-	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) |= CURSOR_ENABLE;
-
-	// Arm and activate changes.
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
-}
-
-void display_set_pos_cursor(u32 x, u32 y)
-{
-	DISPLAY_A(_DIREG(DC_DISP_CURSOR_POSITION)) = x | (y << 16);
-
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
-}
-
-void display_deinit_cursor()
-{
-	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = 0;
-	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) &= ~CURSOR_ENABLE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
-}
--- a/bdk/gfx/di.h
+++ b/bdk/gfx/di.h
@@ -1,540 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _DI_H_
-#define _DI_H_
-
-#include <memory_map.h>
-#include <utils/types.h>
-
-/*! Display registers. */
-#define _DIREG(reg) ((reg) * 4)
-
-// Display controller scratch registers.
-#define DC_D_WINBUF_DD_SCRATCH_REGISTER_0 0xED
-#define DC_D_WINBUF_DD_SCRATCH_REGISTER_1 0xEE
-#define DC_T_WINBUF_TD_SCRATCH_REGISTER_0 0x16D
-#define DC_T_WINBUF_TD_SCRATCH_REGISTER_1 0x16E
-#define DC_COM_SCRATCH_REGISTER_A 0x325
-#define DC_COM_SCRATCH_REGISTER_B 0x326
-#define DC_A_WINBUF_AD_SCRATCH_REGISTER_0 0xBED
-#define DC_A_WINBUF_AD_SCRATCH_REGISTER_1 0xBEE
-#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0 0xDED
-#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1 0xDEE
-#define DC_C_WINBUF_CD_SCRATCH_REGISTER_0 0xFED
-#define DC_C_WINBUF_CD_SCRATCH_REGISTER_1 0xFEE
-
-// DC_CMD non-shadowed command/sync registers.
-#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
-
-#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
-#define  SYNCPT_CNTRL_NO_STALL   (1 << 8)
-#define  SYNCPT_CNTRL_SOFT_RESET (1 << 0)
-
-#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
-#define  SYNCPT_VSYNC_ENABLE (1 << 8)
-
-#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
-
-#define DC_CMD_DISPLAY_COMMAND 0x32
-#define  DISP_CTRL_MODE_STOP       (0 << 5)
-#define  DISP_CTRL_MODE_C_DISPLAY  (1 << 5)
-#define  DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
-#define  DISP_CTRL_MODE_MASK       (3 << 5)
-
-#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
-#define  PW0_ENABLE (1 <<  0)
-#define  PW1_ENABLE (1 <<  2)
-#define  PW2_ENABLE (1 <<  4)
-#define  PW3_ENABLE (1 <<  6)
-#define  PW4_ENABLE (1 <<  8)
-#define  PM0_ENABLE (1 << 16)
-#define  PM1_ENABLE (1 << 18)
-
-#define DC_CMD_INT_STATUS 0x37
-#define DC_CMD_INT_MASK 0x38
-#define DC_CMD_INT_ENABLE 0x39
-
-#define DC_CMD_STATE_ACCESS 0x40
-#define  READ_MUX  (1 << 0)
-#define  WRITE_MUX (1 << 2)
-
-#define DC_CMD_STATE_CONTROL 0x41
-#define  GENERAL_ACT_REQ (1 <<  0)
-#define  WIN_A_ACT_REQ   (1 <<  1)
-#define  WIN_B_ACT_REQ   (1 <<  2)
-#define  WIN_C_ACT_REQ   (1 <<  3)
-#define  WIN_D_ACT_REQ   (1 <<  4)
-#define  CURSOR_ACT_REQ  (1 <<  7)
-#define  GENERAL_UPDATE  (1 <<  8)
-#define  WIN_A_UPDATE    (1 <<  9)
-#define  WIN_B_UPDATE    (1 << 10)
-#define  WIN_C_UPDATE    (1 << 11)
-#define  WIN_D_UPDATE    (1 << 12)
-#define  CURSOR_UPDATE   (1 << 15)
-#define  NC_HOST_TRIG    (1 << 24)
-
-#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
-#define  WINDOW_A_SELECT (1 << 4)
-#define  WINDOW_B_SELECT (1 << 5)
-#define  WINDOW_C_SELECT (1 << 6)
-#define  WINDOW_D_SELECT (1 << 7)
-
-#define DC_CMD_REG_ACT_CONTROL 0x043
-
-// DC_D_WIN_DD window D instance of DC_WIN
-#define DC_D_WIN_DD_WIN_OPTIONS 0x80
-#define DC_D_WIN_DD_COLOR_DEPTH 0x83
-#define DC_D_WIN_DD_POSITION    0x84
-#define DC_D_WIN_DD_SIZE        0x85
-#define DC_D_WIN_DD_LINE_STRIDE 0x8A
-#define DC_D_WIN_DD_BLEND_LAYER_CONTROL 0x96
-#define DC_D_WIN_DD_BLEND_MATCH_SELECT  0x97
-#define DC_D_WIN_DD_BLEND_ALPHA_1BIT    0x99
-
-// DC_D_WINBUF_DD window D instance of DC_WINBUF
-#define DC_D_WINBUF_DD_START_ADDR    0xC0
-#define DC_D_WINBUF_DD_ADDR_H_OFFSET 0xC6
-#define DC_D_WINBUF_DD_ADDR_V_OFFSET 0xC8
-#define DC_D_WINBUF_DD_START_ADDR_HI 0xCD
-#define DC_D_WINBUF_DD_MEMFETCH_CONTROL 0xEB
-
-// DC_T_WIN_TD macro for using DD defines.
-#define _DC_T(reg) ((reg) + 0x80)
-
-// DC_COM non-shadowed registers.
-#define DC_COM_CRC_CONTROL 0x300
-#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
-#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
-
-#define DC_COM_DSC_TOP_CTL 0x33E
-
-// DC_DISP shadowed registers.
-#define DC_DISP_DISP_WIN_OPTIONS 0x402
-#define  HDMI_ENABLE     (1 << 30)
-#define  DSI_ENABLE      (1 << 29)
-#define  SOR1_TIMING_CYA (1 << 27)
-#define  SOR1_ENABLE     (1 << 26)
-#define  SOR_ENABLE      (1 << 25)
-#define  CURSOR_ENABLE   (1 << 16)
-
-#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
-#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
-#define DC_DISP_DISP_TIMING_OPTIONS 0x405
-#define DC_DISP_REF_TO_SYNC 0x406
-#define DC_DISP_SYNC_WIDTH 0x407
-#define DC_DISP_BACK_PORCH 0x408
-#define DC_DISP_ACTIVE 0x409
-#define DC_DISP_FRONT_PORCH 0x40A
-
-#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
-#define  PIXEL_CLK_DIVIDER_PCD1  (0 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD2  (2 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD3  (3 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD4  (4 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD6  (5 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD8  (6 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD9  (7 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
-#define  PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
-#define  SHIFT_CLK_DIVIDER(x)    ((x) & 0xff)
-
-#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
-#define  DISP_DATA_FORMAT_DF1P1C    (0 << 0)
-#define  DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
-#define  DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
-#define  DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
-#define  DISP_DATA_FORMAT_DF2S      (4 << 0)
-#define  DISP_DATA_FORMAT_DF3S      (5 << 0)
-#define  DISP_DATA_FORMAT_DFSPI     (6 << 0)
-#define  DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
-#define  DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
-#define  DISP_ALIGNMENT_MSB         (0 << 8)
-#define  DISP_ALIGNMENT_LSB         (1 << 8)
-#define  DISP_ORDER_RED_BLUE        (0 << 9)
-#define  DISP_ORDER_BLUE_RED        (1 << 9)
-
-#define DC_DISP_DISP_COLOR_CONTROL 0x430
-#define  DITHER_CONTROL_MASK    (3 << 8)
-#define  DITHER_CONTROL_DISABLE (0 << 8)
-#define  DITHER_CONTROL_ORDERED (2 << 8)
-#define  DITHER_CONTROL_ERRDIFF (3 << 8)
-#define  BASE_COLOR_SIZE_MASK   (0xf << 0)
-#define  BASE_COLOR_SIZE_666    (0 << 0)
-#define  BASE_COLOR_SIZE_111    (1 << 0)
-#define  BASE_COLOR_SIZE_222    (2 << 0)
-#define  BASE_COLOR_SIZE_333    (3 << 0)
-#define  BASE_COLOR_SIZE_444    (4 << 0)
-#define  BASE_COLOR_SIZE_555    (5 << 0)
-#define  BASE_COLOR_SIZE_565    (6 << 0)
-#define  BASE_COLOR_SIZE_332    (7 << 0)
-#define  BASE_COLOR_SIZE_888    (8 << 0)
-
-#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
-#define  SC1_H_QUALIFIER_NONE	(1 << 16)
-#define  SC0_H_QUALIFIER_NONE	(1 <<  0)
-
-#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
-#define  DE_SELECT_ACTIVE_BLANK  (0 << 0)
-#define  DE_SELECT_ACTIVE        (1 << 0)
-#define  DE_SELECT_ACTIVE_IS     (2 << 0)
-#define  DE_CONTROL_ONECLK       (0 << 2)
-#define  DE_CONTROL_NORMAL       (1 << 2)
-#define  DE_CONTROL_EARLY_EXT    (2 << 2)
-#define  DE_CONTROL_EARLY        (3 << 2)
-#define  DE_CONTROL_ACTIVE_BLANK (4 << 2)
-
-// Cursor configuration registers.
-#define DC_DISP_CURSOR_FOREGROUND    0x43C
-#define DC_DISP_CURSOR_BACKGROUND    0x43D
-#define  CURSOR_COLOR(r,g,b) (((r) & 0xFF) | (((g) & 0xFF) << 8) | (((b) & 0xFF) << 16))
-
-#define DC_DISP_CURSOR_START_ADDR    0x43E
-#define  CURSOR_CLIPPING(w) ((w) << 28)
-#define   CURSOR_CLIP_WIN_A 1
-#define   CURSOR_CLIP_WIN_B 2
-#define   CURSOR_CLIP_WIN_C 3
-#define  CURSOR_SIZE_32  (0 << 24)
-#define  CURSOR_SIZE_64  (1 << 24)
-#define  CURSOR_SIZE_128 (2 << 24)
-#define  CURSOR_SIZE_256 (3 << 24)
-#define DC_DISP_CURSOR_POSITION      0x440
-#define DC_DISP_CURSOR_START_ADDR_HI 0x4EC
-#define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1
-#define  CURSOR_BLEND_2BIT     (0 << 24)
-#define  CURSOR_BLEND_R8G8B8A8 (1 << 24)
-#define  CURSOR_BLEND_SRC_FACTOR(n) ((n) << 8)
-#define  CURSOR_BLEND_DST_FACTOR(n) ((n) << 16)
-#define   CURSOR_BLEND_ZRO 0
-#define   CURSOR_BLEND_K1  1
-#define   CURSOR_BLEND_NK1 2
-// End of cursor cfg regs.
-
-#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
-#define DC_DISP_SD_BL_PARAMETERS 0x4D7
-#define DC_DISP_SD_BL_CONTROL 0x4DC
-#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
-
-#define DC_WIN_CSC_YOF 0x611
-#define DC_WIN_CSC_KYRGB 0x612
-#define DC_WIN_CSC_KUR 0x613
-#define DC_WIN_CSC_KVR 0x614
-#define DC_WIN_CSC_KUG 0x615
-#define DC_WIN_CSC_KVG 0x616
-#define DC_WIN_CSC_KUB 0x617
-#define DC_WIN_CSC_KVB 0x618
-#define DC_WIN_AD_WIN_OPTIONS 0xB80
-#define DC_WIN_BD_WIN_OPTIONS 0xD80
-#define DC_WIN_CD_WIN_OPTIONS 0xF80
-
-// The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
-#define DC_WIN_WIN_OPTIONS 0x700
-#define  H_DIRECTION  (1 <<  0)
-#define  V_DIRECTION  (1 <<  2)
-#define  SCAN_COLUMN  (1 <<  4)
-#define  COLOR_EXPAND (1 <<  6)
-#define  CSC_ENABLE   (1 << 18)
-#define  WIN_ENABLE   (1 << 30)
-
-#define DC_WIN_BUFFER_CONTROL 0x702
-#define  BUFFER_CONTROL_HOST  0
-#define  BUFFER_CONTROL_VI    1
-#define  BUFFER_CONTROL_EPP   2
-#define  BUFFER_CONTROL_MPEGE 3
-#define  BUFFER_CONTROL_SB2D  4
-
-#define DC_WIN_COLOR_DEPTH 0x703
-#define  WIN_COLOR_DEPTH_P1             0x0
-#define  WIN_COLOR_DEPTH_P2             0x1
-#define  WIN_COLOR_DEPTH_P4             0x2
-#define  WIN_COLOR_DEPTH_P8             0x3
-#define  WIN_COLOR_DEPTH_B4G4R4A4       0x4
-#define  WIN_COLOR_DEPTH_B5G5R5A        0x5
-#define  WIN_COLOR_DEPTH_B5G6R5         0x6
-#define  WIN_COLOR_DEPTH_AB5G5R5        0x7
-#define  WIN_COLOR_DEPTH_B8G8R8A8       0xC
-#define  WIN_COLOR_DEPTH_R8G8B8A8       0xD
-#define  WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE
-#define  WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF
-#define  WIN_COLOR_DEPTH_YCbCr422       0x10
-#define  WIN_COLOR_DEPTH_YUV422         0x11
-#define  WIN_COLOR_DEPTH_YCbCr420P      0x12
-#define  WIN_COLOR_DEPTH_YUV420P        0x13
-#define  WIN_COLOR_DEPTH_YCbCr422P      0x14
-#define  WIN_COLOR_DEPTH_YUV422P        0x15
-#define  WIN_COLOR_DEPTH_YCbCr422R      0x16
-#define  WIN_COLOR_DEPTH_YUV422R        0x17
-#define  WIN_COLOR_DEPTH_YCbCr422RA     0x18
-#define  WIN_COLOR_DEPTH_YUV422RA       0x19
-
-#define DC_WIN_POSITION 0x704
-#define  H_POSITION(x) (((x) & 0xFfff) <<  0)
-#define  V_POSITION(x) (((x) & 0x1fff) << 16)
-
-#define DC_WIN_SIZE 0x705
-#define  H_SIZE(x) (((x) & 0x1fff) <<  0)
-#define  V_SIZE(x) (((x) & 0x1fff) << 16)
-
-#define DC_WIN_PRESCALED_SIZE 0x706
-#define  H_PRESCALED_SIZE(x) (((x) & 0x7fff) <<  0)
-#define  V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
-
-#define DC_WIN_H_INITIAL_DDA 0x707
-#define DC_WIN_V_INITIAL_DDA 0x708
-
-#define DC_WIN_DDA_INC 0x709
-#define  H_DDA_INC(x) (((x) & 0xffff) <<  0)
-#define  V_DDA_INC(x) (((x) & 0xffff) << 16)
-
-#define DC_WIN_LINE_STRIDE 0x70A
-#define  LINE_STRIDE(x)	   (x)
-#define  UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
-#define DC_WIN_DV_CONTROL 0x70E
-
-#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716
-#define  WIN_K1(x) (((x) & 0xff) << 8)
-#define  WIN_K2(x) (((x) & 0xff) << 16)
-#define  WIN_BLEND_ENABLE (0 << 24)
-#define  WIN_BLEND_BYPASS (1 << 24)
-
-#define DC_WINBUF_BLEND_MATCH_SELECT 0x717
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ZERO             (0 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ONE              (1 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1               (2 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_DST     (3 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (4 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC     (5 << 0)
-
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ZERO             (0 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ONE              (1 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1               (2 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K2               (3 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1_TIMES_DST     (4 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (5 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC (6 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1           (7 << 4)
-
-#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_ZERO             (0 << 8)
-#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K1               (1 << 8)
-#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2               (2 << 8)
-
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO             (0 << 12)
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ONE              (1 << 12)
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_NEG_K1_TIMES_SRC (2 << 12)
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2               (3 << 12)
-
-#define DC_WINBUF_BLEND_ALPHA_1BIT 0x719
-#define  WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xff) << 0)
-#define  WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xff) << 8)
-
-/*! The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
-#define DC_WINBUF_START_ADDR 0x800
-#define DC_WINBUF_ADDR_H_OFFSET 0x806
-#define DC_WINBUF_ADDR_V_OFFSET 0x808
-#define DC_WINBUF_SURFACE_KIND 0x80B
-#define  PITCH	(0 << 0)
-#define  TILED	(1 << 0)
-#define  BLOCK	(2 << 0)
-#define  BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
-
-/*! Display serial interface registers. */
-#define _DSIREG(reg) ((reg) * 4)
-
-#define DSI_RD_DATA 0x9
-#define DSI_WR_DATA 0xA
-
-#define DSI_POWER_CONTROL 0xB
-#define  DSI_POWER_CONTROL_ENABLE 1
-
-#define DSI_INT_ENABLE 0xC
-#define DSI_INT_STATUS 0xD
-#define DSI_INT_MASK 0xE
-
-#define DSI_HOST_CONTROL 0xF
-#define  DSI_HOST_CONTROL_FIFO_RESET   (1 << 21)
-#define  DSI_HOST_CONTROL_CRC_RESET    (1 << 20)
-#define  DSI_HOST_CONTROL_TX_TRIG_SOL  (0 << 12)
-#define  DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
-#define  DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
-#define  DSI_HOST_CONTROL_RAW          (1 << 6)
-#define  DSI_HOST_CONTROL_HS           (1 << 5)
-#define  DSI_HOST_CONTROL_FIFO_SEL     (1 << 4)
-#define  DSI_HOST_CONTROL_IMM_BTA      (1 << 3)
-#define  DSI_HOST_CONTROL_PKT_BTA      (1 << 2)
-#define  DSI_HOST_CONTROL_CS           (1 << 1)
-#define  DSI_HOST_CONTROL_ECC          (1 << 0)
-
-#define DSI_CONTROL 0x10
-#define  DSI_CONTROL_HS_CLK_CTRL  (1 << 20)
-#define  DSI_CONTROL_CHANNEL(c)   (((c) & 0x3) << 16)
-#define  DSI_CONTROL_FORMAT(f)    (((f) & 0x3) << 12)
-#define  DSI_CONTROL_TX_TRIG(x)   (((x) & 0x3) <<  8)
-#define  DSI_CONTROL_LANES(n)     (((n) & 0x3) <<  4)
-#define  DSI_CONTROL_DCS_ENABLE   (1 << 3)
-#define  DSI_CONTROL_SOURCE(s)    (((s) & 0x1) <<  2)
-#define  DSI_CONTROL_VIDEO_ENABLE (1 << 1)
-#define  DSI_CONTROL_HOST_ENABLE  (1 << 0)
-
-#define DSI_SOL_DELAY 0x11
-#define DSI_MAX_THRESHOLD 0x12
-
-#define DSI_TRIGGER 0x13
-#define  DSI_TRIGGER_HOST  (1 << 1)
-#define  DSI_TRIGGER_VIDEO (1 << 0)
-
-#define DSI_TX_CRC 0x14
-#define DSI_STATUS 0x15
-#define DSI_INIT_SEQ_CONTROL 0x1A
-#define DSI_INIT_SEQ_DATA_0 0x1B
-#define DSI_INIT_SEQ_DATA_1 0x1C
-#define DSI_INIT_SEQ_DATA_2 0x1D
-#define DSI_INIT_SEQ_DATA_3 0x1E
-#define DSI_PKT_SEQ_0_LO 0x23
-#define DSI_PKT_SEQ_0_HI 0x24
-#define DSI_PKT_SEQ_1_LO 0x25
-#define DSI_PKT_SEQ_1_HI 0x26
-#define DSI_PKT_SEQ_2_LO 0x27
-#define DSI_PKT_SEQ_2_HI 0x28
-#define DSI_PKT_SEQ_3_LO 0x29
-#define DSI_PKT_SEQ_3_HI 0x2A
-#define DSI_PKT_SEQ_4_LO 0x2B
-#define DSI_PKT_SEQ_4_HI 0x2C
-#define DSI_PKT_SEQ_5_LO 0x2D
-#define DSI_PKT_SEQ_5_HI 0x2E
-#define DSI_DCS_CMDS 0x33
-#define DSI_PKT_LEN_0_1 0x34
-#define DSI_PKT_LEN_2_3 0x35
-#define DSI_PKT_LEN_4_5 0x36
-#define DSI_PKT_LEN_6_7 0x37
-#define DSI_PHY_TIMING_0 0x3C
-#define DSI_PHY_TIMING_1 0x3D
-#define DSI_PHY_TIMING_2 0x3E
-#define DSI_BTA_TIMING 0x3F
-
-#define DSI_TIMEOUT_0 0x44
-#define  DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
-#define  DSI_TIMEOUT_HTX(x) (((x) & 0xffff) <<  0)
-
-#define DSI_TIMEOUT_1 0x45
-#define  DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
-#define  DSI_TIMEOUT_TA(x) (((x) & 0xffff) <<  0)
-
-#define DSI_TO_TALLY 0x46
-
-#define DSI_PAD_CONTROL_0 0x4B
-#define  DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
-#define  DSI_PAD_CONTROL_VS1_PULLDN(x)  (((x) & 0xf) << 16)
-#define  DSI_PAD_CONTROL_VS1_PDIO_CLK   (1 <<  8)
-#define  DSI_PAD_CONTROL_VS1_PDIO(x)    (((x) & 0xf) <<  0)
-
-#define DSI_PAD_CONTROL_CD 0x4C
-#define DSI_VIDEO_MODE_CONTROL 0x4E
-#define  DSI_CMD_PKT_VID_ENABLE 1
-
-#define DSI_PAD_CONTROL_1 0x4F
-#define DSI_PAD_CONTROL_2 0x50
-
-#define DSI_PAD_CONTROL_3 0x51
-#define  DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
-#define  DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
-#define  DSI_PAD_PREEMP_PD(x)     (((x) & 0x3) << 4)
-#define  DSI_PAD_PREEMP_PU(x)     (((x) & 0x3) << 0)
-
-#define DSI_PAD_CONTROL_4 0x52
-#define DSI_INIT_SEQ_DATA_15 0x5F
-
-/*! MIPI registers. */
-#define MIPI_CAL_MIPI_CAL_CTRL          (0x00 / 0x4)
-#define MIPI_CAL_CIL_MIPI_CAL_STATUS    (0x08 / 0x4)
-#define MIPI_CAL_CILA_MIPI_CAL_CONFIG   (0x14 / 0x4)
-#define MIPI_CAL_CILB_MIPI_CAL_CONFIG   (0x18 / 0x4)
-#define MIPI_CAL_CILC_MIPI_CAL_CONFIG   (0x1C / 0x4)
-#define MIPI_CAL_CILD_MIPI_CAL_CONFIG   (0x20 / 0x4)
-#define MIPI_CAL_CILE_MIPI_CAL_CONFIG   (0x24 / 0x4)
-#define MIPI_CAL_CILF_MIPI_CAL_CONFIG   (0x28 / 0x4)
-#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG   (0x38 / 0x4)
-#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG   (0x3C / 0x4)
-#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG   (0x40 / 0x4)
-#define MIPI_CAL_DSID_MIPI_CAL_CONFIG   (0x44 / 0x4)
-#define MIPI_CAL_MIPI_BIAS_PAD_CFG0     (0x58 / 0x4)
-#define MIPI_CAL_MIPI_BIAS_PAD_CFG1     (0x5C / 0x4)
-#define MIPI_CAL_MIPI_BIAS_PAD_CFG2     (0x60 / 0x4)
-#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x64 / 0x4)
-#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x68 / 0x4)
-#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x70 / 0x4)
-#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4)
-
-/*! MIPI CMDs. */
-#define MIPI_DSI_DCS_SHORT_WRITE 0x05
-#define MIPI_DSI_DCS_READ 0x06
-#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15
-#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
-#define MIPI_DSI_DCS_LONG_WRITE 0x39
-
-/*! MIPI DCS CMDs. */
-#define MIPI_DCS_GET_DISPLAY_ID   0x04
-#define MIPI_DCS_ENTER_SLEEP_MODE 0x10
-#define MIPI_DCS_EXIT_SLEEP_MODE  0x11
-#define MIPI_DCS_SET_DISPLAY_ON   0x29
-
-/* Switch Panels:
- * [10] 81 [26]: JDI LPM062M326A
- * [10] 96 [09]: JDI LAM062M109A
- * [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
- * [20] XX [10]: InnoLux P062CCA-AZ2 [UNCONFIRMED ID]
- * [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
- * [30] XX [10]: AUO A062TAN02 (59.06A33.002) [UNCONFIRMED ID]
- */
-
-enum
-{
-	PANEL_JDI_XXX062M     = 0x10,
-	PANEL_JDI_LAM062M109A = 0x0910,
-	PANEL_JDI_LPM062M326A = 0x2610,
-	PANEL_INL_P062CCA_AZ1 = 0x0F20,
-	PANEL_AUO_A062TAN01   = 0x0F30,
-	PANEL_INL_P062CCA_AZ2 = 0x1020,
-	PANEL_AUO_A062TAN02   = 0x1030
-};
-
-void display_init();
-void display_backlight_pwm_init();
-void display_end();
-
-/*! Show one single color on the display. */
-void display_color_screen(u32 color);
-
-/*! Switches screen backlight ON/OFF. */
-void display_backlight(bool enable);
-void display_backlight_brightness(u32 brightness, u32 step_delay);
-
-/*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
-u32 *display_init_framebuffer_pitch();
-u32 *display_init_framebuffer_pitch_inv();
-u32 *display_init_framebuffer_block();
-u32 *display_init_framebuffer_log();
-void display_activate_console();
-void display_deactivate_console();
-void display_init_cursor(void *crs_fb, u32 size);
-void display_set_pos_cursor(u32 x, u32 y);
-void display_deinit_cursor();
-
-#endif
--- a/bdk/gfx/di.inl
+++ b/bdk/gfx/di.inl
@@ -1,696 +0,0 @@
-/*
-* Copyright (c) 2018 naehrwert
-* Copyright (c) 2018-2019 CTCaer
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms and conditions of the GNU General Public License,
-* version 2, as published by the Free Software Foundation.
-*
-* This program is distributed in the hope it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-* more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-//Display A config.
-static const cfg_op_t _display_dc_setup_win_config[94] = {
-	{DC_CMD_STATE_ACCESS, 0},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_REG_ACT_CONTROL, 0x54},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_DISP_DC_MCCIF_FIFOCTRL, 0},
-	{DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
-	{DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
-	{DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
-	{DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
-	{DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-	{DC_CMD_STATE_ACCESS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_DV_CONTROL, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	/* Setup default YUV colorspace conversion coefficients */
-	{DC_WIN_CSC_YOF,   0xF0},
-	{DC_WIN_CSC_KYRGB, 0x12A},
-	{DC_WIN_CSC_KUR,   0},
-	{DC_WIN_CSC_KVR,   0x198},
-	{DC_WIN_CSC_KUG,   0x39B},
-	{DC_WIN_CSC_KVG,   0x32F},
-	{DC_WIN_CSC_KUB,   0x204},
-	{DC_WIN_CSC_KVB,   0},
-	/* End of color coefficients */
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_DV_CONTROL, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	/* Setup default YUV colorspace conversion coefficients */
-	{DC_WIN_CSC_YOF,   0xF0},
-	{DC_WIN_CSC_KYRGB, 0x12A},
-	{DC_WIN_CSC_KUR,   0},
-	{DC_WIN_CSC_KVR,   0x198},
-	{DC_WIN_CSC_KUG,   0x39B},
-	{DC_WIN_CSC_KVG,   0x32F},
-	{DC_WIN_CSC_KUB,   0x204},
-	{DC_WIN_CSC_KVB,   0},
-	/* End of color coefficients */
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_DV_CONTROL, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	/* Setup default YUV colorspace conversion coefficients */
-	{DC_WIN_CSC_YOF,   0xF0},
-	{DC_WIN_CSC_KYRGB, 0x12A},
-	{DC_WIN_CSC_KUR,   0},
-	{DC_WIN_CSC_KVR,   0x198},
-	{DC_WIN_CSC_KUG,   0x39B},
-	{DC_WIN_CSC_KVG,   0x32F},
-	{DC_WIN_CSC_KUB,   0x204},
-	{DC_WIN_CSC_KVB,   0},
-	/* End of color coefficients */
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
-	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
-	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
-	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-	{0x4E4, 0},
-	{DC_COM_CRC_CONTROL, 0},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{0x716, 0x10000FF},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{0x716, 0x10000FF},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{0x716, 0x10000FF},
-	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
-};
-
-//DSI Init config.
-static const cfg_op_t _display_dsi_init_config[61] = {
-	{DSI_WR_DATA, 0},
-	{DSI_INT_ENABLE, 0},
-	{DSI_INT_STATUS, 0},
-	{DSI_INT_MASK, 0},
-	{DSI_INIT_SEQ_DATA_0, 0},
-	{DSI_INIT_SEQ_DATA_1, 0},
-	{DSI_INIT_SEQ_DATA_2, 0},
-	{DSI_INIT_SEQ_DATA_3, 0},
-	{DSI_INIT_SEQ_DATA_15, 0},
-	{DSI_DCS_CMDS, 0},
-	{DSI_PKT_SEQ_0_LO, 0},
-	{DSI_PKT_SEQ_1_LO, 0},
-	{DSI_PKT_SEQ_2_LO, 0},
-	{DSI_PKT_SEQ_3_LO, 0},
-	{DSI_PKT_SEQ_4_LO, 0},
-	{DSI_PKT_SEQ_5_LO, 0},
-	{DSI_PKT_SEQ_0_HI, 0},
-	{DSI_PKT_SEQ_1_HI, 0},
-	{DSI_PKT_SEQ_2_HI, 0},
-	{DSI_PKT_SEQ_3_HI, 0},
-	{DSI_PKT_SEQ_4_HI, 0},
-	{DSI_PKT_SEQ_5_HI, 0},
-	{DSI_CONTROL, 0},
-	{DSI_PAD_CONTROL_CD, 0},
-	{DSI_SOL_DELAY, 0x18},
-	{DSI_MAX_THRESHOLD, 0x1E0},
-	{DSI_TRIGGER, 0},
-	{DSI_INIT_SEQ_CONTROL, 0},
-	{DSI_PKT_LEN_0_1, 0},
-	{DSI_PKT_LEN_2_3, 0},
-	{DSI_PKT_LEN_4_5, 0},
-	{DSI_PKT_LEN_6_7, 0},
-	{DSI_PAD_CONTROL_1, 0},
-	{DSI_PHY_TIMING_0, 0x6070601},
-	{DSI_PHY_TIMING_1, 0x40A0E05},
-	{DSI_PHY_TIMING_2, 0x30109},
-	{DSI_BTA_TIMING, 0x190A14},
-	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
-	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
-	{DSI_TO_TALLY, 0},
-	{DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable
-	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-	{DSI_POWER_CONTROL, 0},
-	{DSI_POWER_CONTROL, 0},
-	{DSI_PAD_CONTROL_1, 0},
-	{DSI_PHY_TIMING_0, 0x6070601},
-	{DSI_PHY_TIMING_1, 0x40A0E05},
-	{DSI_PHY_TIMING_2, 0x30118},
-	{DSI_BTA_TIMING, 0x190A14},
-	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
-	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
-	{DSI_TO_TALLY, 0},
-	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-	{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
-	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-	{DSI_MAX_THRESHOLD, 0x40},
-	{DSI_TRIGGER, 0},
-	{DSI_TX_CRC, 0},
-	{DSI_INIT_SEQ_CONTROL, 0}
-};
-
-//DSI panel config.
-static const cfg_op_t _display_init_config_jdi[43] = {
-	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x1939},     // MIPI_DSI_DCS_LONG_WRITE: 25 bytes.
-	{DSI_WR_DATA, 0xAAAAAAD8},
-	{DSI_WR_DATA, 0xAAAAAAEB},
-	{DSI_WR_DATA, 0xAAEBAAAA},
-	{DSI_WR_DATA, 0xAAAAAAAA},
-	{DSI_WR_DATA, 0xAAAAAAEB},
-	{DSI_WR_DATA, 0xAAEBAAAA},
-	{DSI_WR_DATA, 0xAA},
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x01BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x1BD.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x2739},     // MIPI_DSI_DCS_LONG_WRITE: 39 bytes.
-	{DSI_WR_DATA, 0xFFFFFFD8},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFF},
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x02BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x2BD.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0xF39},      // MIPI_DSI_DCS_LONG_WRITE: 15 bytes.
-	{DSI_WR_DATA, 0xFFFFFFD8},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_WR_DATA, 0xFFFFFF},
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x06D915},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x6D9.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST}
-};
-
-//DSI packet config.
-static const cfg_op_t _display_dsi_packet_config[21] = {
-	{DSI_PAD_CONTROL_1, 0},
-	{DSI_PHY_TIMING_0, 0x6070601},
-	{DSI_PHY_TIMING_1, 0x40A0E05},
-	{DSI_PHY_TIMING_2, 0x30172},
-	{DSI_BTA_TIMING, 0x190A14},
-	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
-	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
-	{DSI_TO_TALLY, 0},
-	{DSI_PKT_SEQ_0_LO, 0x40000208},
-	{DSI_PKT_SEQ_2_LO, 0x40000308},
-	{DSI_PKT_SEQ_4_LO, 0x40000308},
-	{DSI_PKT_SEQ_1_LO, 0x40000308},
-	{DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
-	{DSI_PKT_SEQ_3_HI, 0x2CC},
-	{DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
-	{DSI_PKT_SEQ_5_HI, 0x2CC},
-	{DSI_PKT_LEN_0_1, 0xCE0000},
-	{DSI_PKT_LEN_2_3, 0x87001A2},
-	{DSI_PKT_LEN_4_5, 0x190},
-	{DSI_PKT_LEN_6_7, 0x190},
-	{DSI_HOST_CONTROL, 0},
-};
-
-//DSI mode config.
-static const cfg_op_t _display_dsi_mode_config[10] = {
-	{DSI_TRIGGER, 0},
-	{DSI_CONTROL, 0},
-	{DSI_SOL_DELAY, 6},
-	{DSI_MAX_THRESHOLD, 0x1E0},
-	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-	{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
-	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-	{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
-	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
-};
-
-//MIPI CAL config.
-static const cfg_op_t _display_mipi_pad_cal_config[6] = {
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0},
-	{MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000},
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG0,  0},
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0},
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0x10010},
-	{MIPI_CAL_MIPI_BIAS_PAD_CFG1,  0x300}
-};
-
-//DSI config.
-static const cfg_op_t _display_dsi_pad_cal_config[4] = {
-	{DSI_PAD_CONTROL_1, 0},
-	{DSI_PAD_CONTROL_2, 0},
-	{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
-	{DSI_PAD_CONTROL_4, 0}
-};
-
-//MIPI CAL config.
-static const cfg_op_t _display_mipi_apply_dsi_cal_config[16] = {
-	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG,   0x200200},
-	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG,   0x200200},
-	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002},
-	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002},
-	{MIPI_CAL_CILA_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_CILB_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_CILC_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_CILD_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_CILE_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_CILF_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_DSIC_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_DSID_MIPI_CAL_CONFIG,   0},
-	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0},
-	{MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0},
-	{MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0},
-	{MIPI_CAL_MIPI_CAL_CTRL,          0x2A000001}
-};
-
-//Display A config.
-static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
-	{DC_CMD_STATE_ACCESS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_DV_CONTROL, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	/* Setup default YUV colorspace conversion coefficients */
-	{DC_WIN_CSC_YOF,   0xF0},
-	{DC_WIN_CSC_KYRGB, 0x12A},
-	{DC_WIN_CSC_KUR,   0},
-	{DC_WIN_CSC_KVR,   0x198},
-	{DC_WIN_CSC_KUG,   0x39B},
-	{DC_WIN_CSC_KVG,   0x32F},
-	{DC_WIN_CSC_KUB,   0x204},
-	{DC_WIN_CSC_KVB,   0},
-	/* End of color coefficients */
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_DV_CONTROL, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	/* Setup default YUV colorspace conversion coefficients */
-	{DC_WIN_CSC_YOF,   0xF0},
-	{DC_WIN_CSC_KYRGB, 0x12A},
-	{DC_WIN_CSC_KUR,   0},
-	{DC_WIN_CSC_KVR,   0x198},
-	{DC_WIN_CSC_KUG,   0x39B},
-	{DC_WIN_CSC_KVG,   0x32F},
-	{DC_WIN_CSC_KUB,   0x204},
-	{DC_WIN_CSC_KVB,   0},
-	/* End of color coefficients */
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_DV_CONTROL, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	/* Setup default YUV colorspace conversion coefficients */
-	{DC_WIN_CSC_YOF,   0xF0},
-	{DC_WIN_CSC_KYRGB, 0x12A},
-	{DC_WIN_CSC_KUR,   0},
-	{DC_WIN_CSC_KVR,   0x198},
-	{DC_WIN_CSC_KUG,   0x39B},
-	{DC_WIN_CSC_KVG,   0x32F},
-	{DC_WIN_CSC_KUB,   0x204},
-	{DC_WIN_CSC_KVB,   0},
-	/* End of color coefficients */
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
-	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
-	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
-	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-	{0x4E4, 0},
-	{DC_COM_CRC_CONTROL, 0},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{0x716, 0x10000FF},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{0x716, 0x10000FF},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{0x716, 0x10000FF},
-	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-	{DC_CMD_STATE_ACCESS, 0},
-	/* Set Display timings */
-	{DC_DISP_DISP_TIMING_OPTIONS, 0},
-	{DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
-	{DC_DISP_SYNC_WIDTH,  0x10048},
-	{DC_DISP_BACK_PORCH,  0x90048},
-	{DC_DISP_ACTIVE,      0x50002D0},
-	{DC_DISP_FRONT_PORCH, 0xA0088},   // Sources say that this should be above the DC_DISP_ACTIVE cmd.
-	/* End of Display timings */
-	{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
-	{DC_COM_PIN_OUTPUT_ENABLE(1), 0},
-	{DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
-	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
-	{DC_DISP_DISP_CLOCK_CONTROL, 0},
-	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
-	{DC_DISP_FRONT_PORCH, 0xA0088},
-	{DC_CMD_STATE_ACCESS, 0},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_STATE_ACCESS, 0},
-	{DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
-	{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
-	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0}
-};
-
-////Display A config.
-static const cfg_op_t _display_video_disp_controller_disable_config[17] = {
-	{DC_DISP_FRONT_PORCH, 0xA0088},
-	{DC_CMD_INT_MASK, 0},
-	{DC_CMD_STATE_ACCESS, 0},
-	{DC_CMD_INT_ENABLE, 0},
-	{DC_CMD_CONT_SYNCPT_VSYNC, 0},
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-	{DC_CMD_DISPLAY_POWER_CONTROL, 0},
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-};
-
-//DSI config.
-static const cfg_op_t _display_dsi_timing_deinit_config[16] = {
-	{DSI_POWER_CONTROL, 0},
-	{DSI_PAD_CONTROL_1, 0},
-	{DSI_PHY_TIMING_0, 0x6070601},
-	{DSI_PHY_TIMING_1, 0x40A0E05},
-	{DSI_PHY_TIMING_2, 0x30118},
-	{DSI_BTA_TIMING, 0x190A14},
-	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
-	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
-	{DSI_TO_TALLY, 0},
-	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-	{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
-	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-	{DSI_MAX_THRESHOLD, 0x40},
-	{DSI_TRIGGER, 0},
-	{DSI_TX_CRC, 0},
-	{DSI_INIT_SEQ_CONTROL, 0}
-};
-
-//DSI config (if ver == 0x10).
-static const cfg_op_t _display_deinit_config_jdi[22] = {
-	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x2139},     // MIPI_DSI_DCS_LONG_WRITE: 33 bytes.
-	{DSI_WR_DATA, 0x191919D5},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19},
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
-	{DSI_WR_DATA, 0x4F0F41B1}, // Set Power control.
-	{DSI_WR_DATA, 0xF179A433},
-	{DSI_WR_DATA, 0x002D81},
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST}
-};
-
-static const cfg_op_t _display_deinit_config_auo[37] = {
-	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
-	{DSI_WR_DATA, 0x191919D5},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
-	{DSI_WR_DATA, 0x191919D6},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_WR_DATA, 0x19191919},
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
-	{DSI_WR_DATA, 0x711148B1}, // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
-	// Set Power control. (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
-	{DSI_WR_DATA, 0x71143209},
-	{DSI_WR_DATA, 0x114D31},   // Set Power control. (Unknown).
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
-	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST}
-};
-
-static const cfg_op_t _display_init_config_invert[3] = {
-	{DSI_WR_DATA, 0x239},
-	{DSI_WR_DATA, 0x02C1}, // INV_EN.
-	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-};
-
-//Display A config.
-static const cfg_op_t cfg_display_one_color[8] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} // Continuous display.
-};
-
-//Display A config linear pitch.
-static const cfg_op_t cfg_display_framebuffer_pitch[32] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_WIN_POSITION, 0}, //(0,0)
-	{DC_WIN_H_INITIAL_DDA, 0},
-	{DC_WIN_V_INITIAL_DDA, 0},
-	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)},
-	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
-	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
-	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
-	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
-	{DC_WINBUF_SURFACE_KIND, PITCH},
-	{DC_WINBUF_START_ADDR, IPL_FB_ADDRESS}, // Framebuffer address.
-	{DC_WINBUF_ADDR_H_OFFSET, 0},
-	{DC_WINBUF_ADDR_V_OFFSET, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, WIN_ENABLE}, // Enable window AD.
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
-};
-
-//Display A config linear pitch inverse + Win D support.
-static const cfg_op_t cfg_display_framebuffer_pitch_inv[34] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_WIN_POSITION, 0}, //(0,0)
-	{DC_WIN_H_INITIAL_DDA, 0},
-	{DC_WIN_V_INITIAL_DDA, 0},
-	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)},
-	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
-	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
-	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
-	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
-	{DC_WINBUF_SURFACE_KIND, PITCH},
-	{DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address.
-	{DC_WINBUF_ADDR_H_OFFSET, 0}, // Linear: 0x383FFC, Block: 0x3813FC.
-	{DC_WINBUF_ADDR_V_OFFSET, 1279}, // Linear: 1279, Block: 0.
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, WIN_ENABLE | V_DIRECTION}, // Enable window AD.
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
-};
-
-//Display A config block linear.
-static const cfg_op_t cfg_display_framebuffer_block[34] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_WIN_POSITION, 0}, //(0,0)
-	{DC_WIN_H_INITIAL_DDA, 0},
-	{DC_WIN_V_INITIAL_DDA, 0},
-	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)},
-	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
-	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
-	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
-	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
-	{DC_WINBUF_SURFACE_KIND, BLOCK_HEIGHT(4) | BLOCK},
-	{DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address.
-	{DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, // Linear: 0x383FFC, Block: 0x3813FC.
-	{DC_WINBUF_ADDR_V_OFFSET, 0}, // Linear: 1279, Block: 0.
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-	{DC_WIN_WIN_OPTIONS, WIN_ENABLE | SCAN_COLUMN | H_DIRECTION}, // Enable window AD. | SCAN_COLUMN | H_DIRECTION.
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
-};
-
-//Display D config.
-static const cfg_op_t cfg_display_framebuffer_log[20] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
-	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8},
-	{DC_WIN_POSITION, 0}, //(0,0)
-	{DC_WIN_H_INITIAL_DDA, 0},
-	{DC_WIN_V_INITIAL_DDA, 0},
-	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(656 * 4)},
-	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
-	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(656)},
-	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(656 * 2) | LINE_STRIDE(656 * 4)}, //656*2x656*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
-	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
-	{DC_WINBUF_SURFACE_KIND, PITCH},
-	{DC_WINBUF_START_ADDR, LOG_FB_ADDRESS}, // Framebuffer address.
-	{DC_WINBUF_ADDR_H_OFFSET, 0},
-	{DC_WINBUF_ADDR_V_OFFSET, 0},
-	{DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_ENABLE | WIN_K1(200)},
-	{DC_WINBUF_BLEND_MATCH_SELECT, WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 | WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1},
-	{DC_WIN_WIN_OPTIONS, 0}, // Enable window DD.
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_D_UPDATE},
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_D_ACT_REQ}
-};
--- a/bdk/ianos/elfload/elf.h
+++ b/bdk/ianos/elfload/elf.h
@@ -29,33 +29,34 @@

 #ifndef ELF_H
 #define ELF_H
-#include <stdint.h>

-typedef uint8_t Elf_Byte;
+#include <utils/types.h>

-typedef uint32_t Elf32_Addr; /* Unsigned program address */
-typedef uint32_t Elf32_Off;  /* Unsigned file offset */
-typedef int32_t Elf32_Sword; /* Signed large integer */
-typedef uint32_t Elf32_Word; /* Unsigned large integer */
-typedef uint16_t Elf32_Half; /* Unsigned medium integer */
+typedef u8 Elf_Byte;

-typedef uint64_t Elf64_Addr;
-typedef uint64_t Elf64_Off;
-typedef int32_t Elf64_Shalf;
+typedef u32 Elf32_Addr; /* Unsigned program address */
+typedef u32 Elf32_Off;  /* Unsigned file offset */
+typedef s32 Elf32_Sword; /* Signed large integer */
+typedef u32 Elf32_Word; /* Unsigned large integer */
+typedef u16 Elf32_Half; /* Unsigned medium integer */
+
+typedef u64 Elf64_Addr;
+typedef u64 Elf64_Off;
+typedef s32 Elf64_Shalf;

 #ifdef __alpha__
-typedef int64_t Elf64_Sword;
-typedef uint64_t Elf64_Word;
+typedef s64 Elf64_Sword;
+typedef u64 Elf64_Word;
 #else
-typedef int32_t Elf64_Sword;
-typedef uint32_t Elf64_Word;
+typedef s32 Elf64_Sword;
+typedef u32 Elf64_Word;
 #endif

-typedef int64_t Elf64_Sxword;
-typedef uint64_t Elf64_Xword;
+typedef s64 Elf64_Sxword;
+typedef u64 Elf64_Xword;

-typedef uint32_t Elf64_Half;
-typedef uint16_t Elf64_Quarter;
+typedef u32 Elf64_Half;
+typedef u16 Elf64_Quarter;

 /*
 * e_ident[] identification indexes
@@ -376,7 +377,7 @@ typedef struct

 #define ELF64_R_SYM(info) ((info) >> 32)
 #define ELF64_R_TYPE(info) ((info)&0xFFFFFFFF)
-#define ELF64_R_INFO(s, t) (((s) << 32) + (__uint32_t)(t))
+#define ELF64_R_INFO(s, t) (((s) << 32) + (u32)(t))

 #if defined(__mips64__) && defined(__MIPSEL__)
 /*
@@ -389,7 +390,7 @@ typedef struct
 #undef ELF64_R_INFO
 #define ELF64_R_TYPE(info) (swap32((info) >> 32))
 #define ELF64_R_SYM(info) ((info)&0xFFFFFFFF)
-#define ELF64_R_INFO(s, t) (((__uint64_t)swap32(t) << 32) + (__uint32_t)(s))
+#define ELF64_R_INFO(s, t) (((u64)swap32(t) << 32) + (u32)(s))
 #endif /* __mips64__ && __MIPSEL__ */

 /* Program Header */
@@ -444,7 +445,7 @@ typedef struct
 /* Dynamic structure */
 typedef struct
 {
-    Elf32_Sword d_tag; /* controls meaning of d_val */
+    Elf32_Word d_tag; /* controls meaning of d_val */
    union {
        Elf32_Word d_val; /* Multiple meanings - see d_tag */
        Elf32_Addr d_ptr; /* program virtual address */
--- a/bdk/ianos/elfload/elfload.c
+++ b/bdk/ianos/elfload/elfload.c
@@ -21,11 +21,11 @@

 el_status el_pread(el_ctx *ctx, void *def, size_t nb, size_t offset)
 {
-	return ctx->pread(ctx, def, nb, offset) ? EL_OK : EL_EIO;
+	return ctx->pread(ctx, def, nb, offset);
 }

 #define EL_PHOFF(ctx, num) (((ctx)->ehdr.e_phoff + (num) *(ctx)->ehdr.e_phentsize))
-el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, uint32_t type, unsigned *i)
+el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, u32 type, unsigned *i)
 {
 	el_status rv = EL_OK;
 	for (; *i < ctx->ehdr.e_phnum; (*i)++)
@@ -44,7 +44,7 @@ el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, uint32_t type, unsigned *i)
 }

 #define EL_SHOFF(ctx, num) (((ctx)->ehdr.e_shoff + (num) *(ctx)->ehdr.e_shentsize))
-el_status el_findshdr(el_ctx *ctx, Elf_Shdr *shdr, uint32_t type, unsigned *i)
+el_status el_findshdr(el_ctx *ctx, Elf_Shdr *shdr, u32 type, unsigned *i)
 {
 	el_status rv = EL_OK;

@@ -213,7 +213,7 @@ el_status el_load(el_ctx *ctx, el_alloc_cb alloc)
 	return rv;
 }

-el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, uint32_t tag)
+el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, u32 tag)
 {
 	el_status rv = EL_OK;
 	size_t ndyn = ctx->dynsize / sizeof(Elf_Dyn);
@@ -231,7 +231,7 @@ el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, uint32_t tag)
 	return EL_OK;
 }

-el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, uint32_t type)
+el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, u32 type)
 {
 	el_status rv = EL_OK;

--- a/bdk/ianos/elfload/elfload.h
+++ b/bdk/ianos/elfload/elfload.h
@@ -22,8 +22,6 @@
 #include "elfarch.h"
 #include "elf.h"

-#include <utils/types.h>
-
 #ifdef DEBUG
 #include <gfx_utils.h>
 #define EL_DEBUG(format, ...) \
@@ -55,7 +53,7 @@ typedef enum

 typedef struct el_ctx
 {
-	bool (*pread)(struct el_ctx *ctx, void *dest, size_t nb, size_t offset);
+	el_status (*pread)(struct el_ctx *ctx, void *dest, size_t nb, size_t offset);

 	/* base_load_* -> address we are actually going to load at
 	 */
@@ -63,6 +61,9 @@ typedef struct el_ctx
 		base_load_paddr,
 		base_load_vaddr;

+	/* original memory of binary */
+	Elf_Addr eaddr;
+
 	/* size in memory of binary */
 	Elf_Addr memsz;

@@ -100,7 +101,7 @@ el_status el_load(el_ctx *ctx, el_alloc_cb alloccb);
 * If the end of the phdrs table was reached, *i is set to -1 and the contents
 * of *phdr are undefined
 */
-el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, uint32_t type, unsigned *i);
+el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, u32 type, unsigned *i);

 /* Relocate the loaded executable */
 el_status el_relocate(el_ctx *ctx);
@@ -108,7 +109,7 @@ el_status el_relocate(el_ctx *ctx);
 /* find a dynamic table entry
 * returns the entry on success, dyn->d_tag = DT_NULL on failure
 */
-el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, uint32_t type);
+el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, u32 type);

 typedef struct
 {
@@ -122,6 +123,6 @@ typedef struct
 * pass DT_REL or DT_RELA for type
 * sets ri->entrysize = 0 if not found
 */
-el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, uint32_t type);
+el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, u32 type);

 #endif
--- a/bdk/ianos/elfload/elfreloc_aarch64.c
+++ b/bdk/ianos/elfload/elfreloc_aarch64.c
@@ -23,9 +23,9 @@

 el_status el_applyrela(el_ctx *ctx, Elf_RelA *rel)
 {
-	uintptr_t *p = (uintptr_t *)(rel->r_offset + ctx->base_load_paddr);
-	uint32_t type = ELF_R_TYPE(rel->r_info);
-	uint32_t sym = ELF_R_SYM(rel->r_info);
+	uptr *p = (uptr *)(rel->r_offset + ctx->base_load_paddr);
+	u32 type = ELF_R_TYPE(rel->r_info);
+	u32 sym = ELF_R_SYM(rel->r_info);

 	switch (type)
 	{
@@ -53,9 +53,9 @@ el_status el_applyrela(el_ctx *ctx, Elf_RelA *rel)

 el_status el_applyrel(el_ctx *ctx, Elf_Rel *rel)
 {
-	uintptr_t *p = (uintptr_t *)(rel->r_offset + ctx->base_load_paddr);
-	uint32_t type = ELF_R_TYPE(rel->r_info);
-	uint32_t sym = ELF_R_SYM(rel->r_info);
+	uptr *p = (uptr *)(rel->r_offset + ctx->base_load_paddr);
+	u32 type = ELF_R_TYPE(rel->r_info);
+	u32 sym = ELF_R_SYM(rel->r_info);

 	switch (type)
 	{
--- a/bdk/ianos/elfload/elfreloc_arm.c
+++ b/bdk/ianos/elfload/elfreloc_arm.c
@@ -20,9 +20,9 @@

 el_status el_applyrel(el_ctx *ctx, Elf_Rel *rel)
 {
-	uint32_t sym = ELF_R_SYM(rel->r_info);                              // Symbol offset
-	uint32_t type = ELF_R_TYPE(rel->r_info);                            // Relocation Type
-	uintptr_t *p = (uintptr_t *)(rel->r_offset + ctx->base_load_paddr); // Target Addr
+	u32 sym = ELF_R_SYM(rel->r_info);                              // Symbol offset
+	u32 type = ELF_R_TYPE(rel->r_info);                            // Relocation Type
+	uptr *p = (uptr *)(rel->r_offset + ctx->base_load_paddr); // Target Addr

 #if 0 // For later symbol usage
 	Elf32_Sym *elfSym;
--- a/bdk/ianos/ianos.c
+++ b/bdk/ianos/ianos.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 M4xw
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -15,107 +15,148 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

+#include <storage/boot_storage.h>
 #include <string.h>

 #include "ianos.h"
 #include "elfload/elfload.h"
 #include <module.h>
 #include <mem/heap.h>
-#include <storage/nx_sd.h>
+#include <storage/sd.h>
 #include <utils/types.h>

 #include <gfx_utils.h>

-#define IRAM_LIB_ADDR 0x4002B000
-#define DRAM_LIB_ADDR 0xE0000000
-
 extern heap_t _heap;

-void *elfBuf = NULL;
-void *fileBuf = NULL;
+static bdk_params_t _bdk_params = {
+	.gfx_con = (void *)&gfx_con,
+	.gfx_ctx = (void *)&gfx_ctxt,
+	.heap    = &_heap,
+	.memcpy  = (memcpy_t)&memcpy,
+	.memset  = (memset_t)&memset,

-static void _ianos_call_ep(moduleEntrypoint_t entrypoint, void *moduleConfig)
-{
-	bdkParams_t bdkParameters = (bdkParams_t)malloc(sizeof(struct _bdkParams_t));
-	bdkParameters->gfxCon = (void *)&gfx_con;
-	bdkParameters->gfxCtx = (void *)&gfx_ctxt;
-	bdkParameters->memcpy = (memcpy_t)&memcpy;
-	bdkParameters->memset = (memset_t)&memset;
-	bdkParameters->sharedHeap = &_heap;
-
-	entrypoint(moduleConfig, bdkParameters);
-}
+	.extension_magic = 0
+};

 static void *_ianos_alloc_cb(el_ctx *ctx, Elf_Addr phys, Elf_Addr virt, Elf_Addr size)
 {
-	(void)ctx;
-	(void)phys;
-	(void)size;
 	return (void *)virt;
 }

-static bool _ianos_read_cb(el_ctx *ctx, void *dest, size_t numberBytes, size_t offset)
+static el_status _ianos_read_cb(el_ctx *ctx, void *dest, size_t nb, size_t offset)
 {
-	(void)ctx;
+	memcpy(dest, (void *)(ctx->eaddr + offset), nb);

-	memcpy(dest, fileBuf + offset, numberBytes);
-
-	return true;
+	return EL_OK;
 }

 //TODO: Support shared libraries.
-uintptr_t ianos_loader(char *path, elfType_t type, void *moduleConfig)
+int ianos_loader(ianos_lib_t *lib, char *path)
 {
 	el_ctx ctx;
-	uintptr_t epaddr = 0;
-
-	if (!sd_mount())
-		goto elfLoadFinalOut;
+	lib->buf = NULL;
+	if (!lib->bdk)
+		lib->bdk = &_bdk_params;

 	// Read library.
-	fileBuf = sd_file_read(path, NULL);
-
-	if (!fileBuf)
-		goto elfLoadFinalOut;
+	ctx.eaddr = (Elf_Addr)boot_storage_file_read(path, NULL);
+	if (!ctx.eaddr)
+		goto error;

 	ctx.pread = _ianos_read_cb;

 	if (el_init(&ctx))
-		goto elfLoadFinalOut;
+		goto error;
+
+	if (lib->type & IA_SHARED_LIB)
+		goto error; // No support for shared libs now.

 	// Set our relocated library's buffer.
-	switch (type & 0xFFFF)
+	switch (lib->type & ~IA_SHARED_LIB)
 	{
-	case EXEC_ELF:
-	case AR64_ELF:
-		elfBuf = (void *)DRAM_LIB_ADDR;
+	case IA_DRAM_LIB:
+		lib->buf = malloc(ctx.memsz); // Aligned to 0x10 by default.
 		break;
+
+	case IA_IRAM_LIB:
+		break;
+
+	case IA_AUTO_LIB: // Default to DRAM for now.
 	default:
-		elfBuf = malloc(ctx.memsz); // Aligned to 0x10 by default.
+		lib->buf = malloc(ctx.memsz); // Aligned to 0x10 by default.
+		break;
 	}

-	if (!elfBuf)
-		goto elfLoadFinalOut;
+	if (!lib->buf)
+		goto error;

 	// Load and relocate library.
-	ctx.base_load_vaddr = ctx.base_load_paddr = (uintptr_t)elfBuf;
+	ctx.base_load_vaddr = ctx.base_load_paddr = (Elf_Addr)lib->buf;
 	if (el_load(&ctx, _ianos_alloc_cb))
-		goto elfFreeOut;
+		goto error;

 	if (el_relocate(&ctx))
-		goto elfFreeOut;
+		goto error;
+
+	free((void *)ctx.eaddr);

 	// Launch.
-	epaddr = ctx.ehdr.e_entry + (uintptr_t)elfBuf;
-	moduleEntrypoint_t ep = (moduleEntrypoint_t)epaddr;
+	Elf_Addr epaddr = ctx.ehdr.e_entry + (Elf_Addr)lib->buf;
+	moduleEntrypoint ep = (moduleEntrypoint)epaddr;
+	ep(lib->private, lib->bdk);

-	_ianos_call_ep(ep, moduleConfig);
+	return 0;

-elfFreeOut:
-	free(fileBuf);
-	elfBuf = NULL;
-	fileBuf = NULL;
+error:
+	free((void *)ctx.eaddr);
+	free(lib->buf);

-elfLoadFinalOut:
-	return epaddr;
-}
+	return 1;
+}
+
+uintptr_t ianos_static_module(char *path, void *private)
+{
+	el_ctx ctx;
+	Elf_Addr buf = 0;
+	Elf_Addr epaddr = 0;
+
+	// Read library.
+	ctx.eaddr = (Elf_Addr)sd_file_read(path, NULL);
+	if (!ctx.eaddr)
+		goto error;
+
+	ctx.pread = _ianos_read_cb;
+
+	// Initialize elfload context.
+	if (el_init(&ctx))
+		goto error;
+
+	// Set our relocated library's buffer.
+	buf = (Elf_Addr)malloc(ctx.memsz); // Aligned to 0x10 by default.
+	if (!buf)
+		goto error;
+
+	// Load and relocate library.
+	ctx.base_load_vaddr = ctx.base_load_paddr = buf;
+	if (el_load(&ctx, _ianos_alloc_cb))
+		goto error;
+
+	if (el_relocate(&ctx))
+		goto error;
+
+	free((void *)ctx.eaddr);
+
+	// Launch.
+	epaddr = ctx.ehdr.e_entry + buf;
+	moduleEntrypoint ep = (moduleEntrypoint)epaddr;
+	ep(private, &_bdk_params);
+
+	return (uintptr_t)epaddr;
+
+error:
+	free((void *)ctx.eaddr);
+	free((void *)buf);
+
+	return 0;
+}
--- a/bdk/ianos/ianos.h
+++ b/bdk/ianos/ianos.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 M4xw
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -19,16 +19,26 @@
 #define IANOS_H

 #include <utils/types.h>
+#include <module.h>

 typedef enum
 {
-	DRAM_LIB = 0, // DRAM library.
-	EXEC_ELF = 1, // Executable elf that does not return.
-	DR64_LIB = 2, // AARCH64 DRAM library.
-	AR64_ELF = 3, // Executable elf that does not return.
-	KEEP_IN_RAM = (1 << 31)  // Shared library mask.
-} elfType_t;
+	IA_DRAM_LIB   = 0, // DRAM library.
+	IA_IRAM_LIB   = 1, // IRAM library. No support for now.
+	IA_AUTO_LIB   = 2, // AUTO library. Defaults to DRAM for now.
+	IA_SHARED_LIB = BIT(7) // Shared library mask. No support for now.
+} ianos_type_t;

-uintptr_t ianos_loader(char *path, elfType_t type, void* config);
+typedef struct _ianos_lib_t
+{
+	uintptr_t epaddr;
+	void *buf;
+	void *private;
+	ianos_type_t type;
+	bdk_params_t *bdk;
+} ianos_lib_t;

-#endif
+int       ianos_loader(ianos_lib_t *lib, char *path);
+uintptr_t ianos_static_module(char *path, void *private); // Session-lived DRAM lib.
+
+#endif
--- a/bdk/input/als.c
+++ b/bdk/input/als.c
@@ -17,101 +17,138 @@
 */

 #include "als.h"
-#include <power/max77620.h>
+#include <power/max7762x.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/pinmux.h>
 #include <utils/util.h>

-#define HOS_GAIN  BH1730_GAIN_64X
-#define HOS_ITIME 38
+#define BH1730_DEFAULT_GAIN        BH1730_GAIN_64X
+#define BH1730_DEFAULT_ICYCLE       38

-void set_als_cfg(als_table_t *als_val, u8 gain, u8 itime)
+#define BH1730_INTERNAL_CLOCK_NS   2800
+#define BH1730_ADC_CALC_DELAY_US   2000 /* BH1730_INTERNAL_CLOCK_MS * 714 */
+#define BH1730_ITIME_CYCLE_TO_US   2700 /* BH1730_INTERNAL_CLOCK_MS * 964 */
+
+#define BH1730_DEFAULT_ITIME_MS	   100
+
+#define BH1730_LUX_MULTIPLIER      3600
+#define BH1730_LUX_MULTIPLIER_AULA 1410
+
+#define BH1730_LUX_MAX            100000
+
+typedef struct _opt_win_cal_t
 {
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), gain);
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - itime));
+	u32 rc;
+	u32 cv;
+	u32 ci;
+} opt_win_cal_t;

-	als_val->gain = gain;
-	als_val->itime = itime;
+// Nintendo Switch Icosa/Iowa Optical Window calibration.
+static const opt_win_cal_t opt_win_cal_default[] = {
+	{  500, 5002, 7502 },
+	{  754, 2250, 2000 },
+	{ 1029, 1999, 1667 },
+	{ 1373,  884,  583 },
+	{ 1879,  309,  165 }
+};
+
+// Nintendo Switch Aula Optical Window calibration.
+static const opt_win_cal_t opt_win_cal_aula[] = {
+	{  231, 9697, 30300 },
+	{  993, 3333,  2778 },
+	{ 1478, 1621,  1053 },
+	{ 7500,   81,    10 }
+};
+
+static const u32 als_gain_idx_tbl[4] = { 1, 2, 64, 128 };
+
+void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle)
+{
+	if (gain > BH1730_GAIN_128X)
+		gain = BH1730_GAIN_128X;
+
+	if (!cycle)
+		cycle = 1;
+
+	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG),   gain);
+	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - cycle));
+
+	als_ctxt->gain = gain;
+	als_ctxt->cycle = cycle;
 }

-void get_als_lux(als_table_t *als_val)
+void get_als_lux(als_ctxt_t *als_ctxt)
 {
 	u32 data[2];
-	float pre_gain_lux;
-	float visible_light;
-	float ir_light;
-	float light_ratio;
+	u32 vi_light;
+	u32 ir_light;
+	u64 lux = 0;
+	u32 itime_us = BH1730_ITIME_CYCLE_TO_US * als_ctxt->cycle;

-	u8 adc_ready = 0;
-	u8 retries = 100;
-
-	const float als_gain_idx_tbl[4] = { 1.0, 2.0, 64.0, 128.0 };
-	const float als_norm_res = 100.0;
-	const float als_multiplier = 3.6;
-	const float als_tint = 2.7;
-
-	// Wait for ADC to prepare new data.
-	while (!(adc_ready & BH1730_CTL_ADC_VALID) && retries)
-	{
-		retries--;
-		adc_ready = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_CONTROL_REG));
-	}
-
-	// Get visible and ir light raw data.
+	// Get visible and ir light raw data. Mode is continuous so waiting for new values doesn't matter.
 	data[0] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0LOW_REG)) +
-		(i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0HIGH_REG)) << 8);
+		     (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0HIGH_REG)) << 8);
 	data[1] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1LOW_REG)) +
-		(i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1HIGH_REG)) << 8);
+		     (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1HIGH_REG)) << 8);

-	als_val->over_limit = data[0] > 65534 || data[1] > 65534;
-	als_val->vi_light = data[0];
-	als_val->ir_light = data[1];
+	vi_light = data[0];
+	ir_light = data[1];

-	if (!data[0] || !retries)
+	als_ctxt->vi_light = vi_light;
+	als_ctxt->ir_light = ir_light;
+	als_ctxt->over_limit = vi_light > 65534 || ir_light > 65534;
+
+	if (!vi_light)
 	{
-		als_val->lux = 0.0;
+		als_ctxt->lux = 0;

 		return;
 	}

-	visible_light = (float)data[0];
-	ir_light = (float)data[1];
-	light_ratio = (float)data[1] / (float)data[0];
+	// Set calibration parameters.
+	u32 lux_multiplier = BH1730_LUX_MULTIPLIER;
+	u32 opt_win_cal_count = ARRAY_SIZE(opt_win_cal_default);
+	const opt_win_cal_t *opt_win_cal = opt_win_cal_default;

-	// The following are specific to the light filter Switch uses.
-	if (light_ratio < 0.5)
-		pre_gain_lux = visible_light * 5.002 - ir_light * 7.502;
-	else if (light_ratio < 0.754)
-		pre_gain_lux = visible_light * 2.250 - ir_light * 2.000;
-	else if (light_ratio < 1.029)
-		pre_gain_lux = visible_light * 1.999 - ir_light * 1.667;
-	else if (light_ratio < 1.373)
-		pre_gain_lux = visible_light * 0.884 - ir_light * 0.583;
-	else if (light_ratio < 1.879)
-		pre_gain_lux = visible_light * 0.309 - ir_light * 0.165;
-	else pre_gain_lux = 0.0;
+	// Apply optical window calibration coefficients.
+	for (u32 i = 0; i < opt_win_cal_count; i++)
+	{
+		if (1000 * ir_light / vi_light < opt_win_cal[i].rc)
+		{
+			lux = ((u64)opt_win_cal[i].cv * data[0]) - (opt_win_cal[i].ci * data[1]);
+			break;
+		}
+	}

-	als_val->lux = (pre_gain_lux / als_gain_idx_tbl[als_val->gain]) * (als_norm_res / ((float)als_val->itime * als_tint)) * als_multiplier;
+	lux *= BH1730_DEFAULT_ITIME_MS * lux_multiplier;
+	lux /= als_gain_idx_tbl[als_ctxt->gain] * itime_us;
+	lux /= 1000;
+
+	if (lux > BH1730_LUX_MAX)
+		lux = BH1730_LUX_MAX;
+
+	als_ctxt->lux = lux;
 }

-u8 als_init(als_table_t *als_val)
+u8 als_power_on(als_ctxt_t *als_ctxt)
 {
+	// Enable power to ALS IC.
+	max7762x_regulator_set_voltage(REGULATOR_LDO6, 2900000);
+	max7762x_regulator_enable(REGULATOR_LDO6, true);
+
+	// Init I2C2.
 	pinmux_config_i2c(I2C_2);
 	clock_enable_i2c(I2C_2);
 	i2c_init(I2C_2);

-	max77620_regulator_set_volt_and_flags(REGULATOR_LDO6, 2900000, MAX77620_POWER_MODE_NORMAL);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2, 0xD8 | MAX77620_LDO_CFG2_ADE_MASK);
-
+	// Initialize ALS.
 	u8 id = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(0x12));
 	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_SPEC(BH1730_SPECCMD_RESET), 0);
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), HOS_GAIN);
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - HOS_ITIME));
-	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_CONTROL_REG), BH1730_CTL_POWER_ON | BH1730_CTL_ADC_EN);

-	als_val->gain = HOS_GAIN;
-	als_val->itime = HOS_ITIME;
+	set_als_cfg(als_ctxt, BH1730_DEFAULT_GAIN, BH1730_DEFAULT_ICYCLE);
+
+	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_CONTROL_REG), BH1730_CTL_POWER_ON | BH1730_CTL_ADC_EN);

 	return id;
 }
--- a/bdk/input/als.h
+++ b/bdk/input/als.h
@@ -45,21 +45,21 @@
 #define BH1730_DATA1LOW_REG  0x16
 #define BH1730_DATA1HIGH_REG 0x17

-#define BH1730_ADDR(reg) (BH1730_CMD_MAGIC | BH1730_CMD_SETADDR | reg)
-#define BH1730_SPEC(cmd) (BH1730_CMD_MAGIC | BH1730_CMD_SPECCMD | cmd)
+#define BH1730_ADDR(reg) (BH1730_CMD_MAGIC | BH1730_CMD_SETADDR | (reg))
+#define BH1730_SPEC(cmd) (BH1730_CMD_MAGIC | BH1730_CMD_SPECCMD | (cmd))

-typedef struct _als_table_t
+typedef struct _als_ctxt_t
 {
-	float lux;
+	u32  lux;
 	bool over_limit;
-	u32 vi_light;
-	u32 ir_light;
-	u8 gain;
-	u8 itime;
-} als_table_t;
+	u32  vi_light;
+	u32  ir_light;
+	u8   gain;
+	u8   cycle;
+} als_ctxt_t;

-void set_als_cfg(als_table_t *als_val, u8 gain, u8 itime);
-void get_als_lux(als_table_t *als_val);
-u8 als_init(als_table_t *als_val);
+void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle);
+void get_als_lux(als_ctxt_t *als_ctxt);
+u8   als_power_on(als_ctxt_t *als_ctxt);

 #endif /* __ALS_H_ */
--- a/bdk/input/joycon.c
+++ b/bdk/input/joycon.c
--- a/bdk/input/joycon.h
+++ b/bdk/input/joycon.h
@@ -1,7 +1,7 @@
 /*
 * Ambient light sensor driver for Nintendo Switch's Rohm BH1730
 *
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -43,34 +43,34 @@ typedef struct _jc_gamepad_rpt_t
 		struct
 		{
 			// Joy-Con (R).
-			u32 y:1;
-			u32 x:1;
-			u32 b:1;
-			u32 a:1;
-			u32 sr_r:1;
-			u32 sl_r:1;
-			u32 r:1;
-			u32 zr:1;
+/*00*/		u32 y:1;
+/*01*/		u32 x:1;
+/*02*/		u32 b:1;
+/*03*/		u32 a:1;
+/*04*/		u32 sr_r:1;
+/*05*/		u32 sl_r:1;
+/*06*/		u32 r:1;
+/*07*/		u32 zr:1;

 			// Shared
-			u32 minus:1;
-			u32 plus:1;
-			u32 r3:1;
-			u32 l3:1;
-			u32 home:1;
-			u32 cap:1;
-			u32 pad:1;
-			u32 wired:1;
+/*08*/		u32 minus:1;
+/*09*/		u32 plus:1;
+/*10*/		u32 r3:1;
+/*11*/		u32 l3:1;
+/*12*/		u32 home:1;
+/*13*/		u32 cap:1;
+/*14*/		u32 pad:1;
+/*15*/		u32 wired:1;

 			// Joy-Con (L).
-			u32 down:1;
-			u32 up:1;
-			u32 right:1;
-			u32 left:1;
-			u32 sr_l:1;
-			u32 sl_l:1;
-			u32 l:1;
-			u32 zl:1;
+/*16*/		u32 down:1;
+/*17*/		u32 up:1;
+/*18*/		u32 right:1;
+/*19*/		u32 left:1;
+/*20*/		u32 sr_l:1;
+/*21*/		u32 sl_l:1;
+/*22*/		u32 l:1;
+/*23*/		u32 zl:1;
 		};
 		u32 buttons;
 	};
@@ -83,16 +83,28 @@ typedef struct _jc_gamepad_rpt_t
 	bool center_stick_r;
 	bool conn_l;
 	bool conn_r;
-	u8 batt_info_l;
-	u8 batt_info_r;
+	bool sio_mode;
+	u8 batt_info_l; // Also Sio Connected status.
+	u8 batt_info_r; // Also Sio IRQ.
+	u8 batt_chrg_l;
+	u8 batt_chrg_r;
 	jc_bt_conn_t bt_conn_l;
 	jc_bt_conn_t bt_conn_r;
 } jc_gamepad_rpt_t;

-void jc_power_supply(u8 uart, bool enable);
+typedef struct _jc_calib_t
+{
+	u16 x_max:12;
+	u16 y_max:12;
+	u16 x_center:12;
+	u16 y_center:12;
+	u16 x_min:12;
+	u16 y_min:12;
+} __attribute__((packed)) jc_calib_t;
+
 void jc_init_hw();
 void jc_deinit();
 jc_gamepad_rpt_t *joycon_poll();
 jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos);

-#endif
+#endif
--- a/bdk/input/touch.c
+++ b/bdk/input/touch.c
@@ -1,8 +1,8 @@
 /*
- * Touch driver for Nintendo Switch's STM FingerTip S (4CD60D) touch controller
+ * Touch driver for Nintendo Switch's STM FingerTip S (FTM4CD60DA1BE/FTM4CD50TA1BE) touch controller
 *
 * Copyright (c) 2018 langerhans
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -23,45 +23,67 @@
 #include <soc/i2c.h>
 #include <soc/pinmux.h>
 #include <power/max7762x.h>
-#include <power/max77620.h>
 #include <soc/gpio.h>
+#include <soc/timer.h>
 #include <soc/t210.h>
 #include <utils/btn.h>
-#include <utils/util.h>
 #include "touch.h"

-
-#include <gfx_utils.h>
-#define DPRINTF(...) gfx_printf(__VA_ARGS__)
-
-static int touch_command(u8 cmd, u8 *buf, u8 size)
+static touch_panel_info_t _panels[] =
 {
-	int res = i2c_send_buf_small(I2C_3, STMFTS_I2C_ADDR, cmd, buf, size);
-	if (!res)
-		return 1;
-	return 0;
+	{  0,  1, 1, 1,  "NISSHA NFT-K12D" },// 0.
+	{  1,  0, 1, 1,  "GiS GGM6 B2X"    },// 1.
+	{  2,  0, 0, 0,  "NISSHA NBF-K9A"  },// 3.
+	{  3,  1, 0, 0,  "GiS 5.5\""       },// 4.
+	{  4,  0, 0, 1,  "Samsung TSP"     },// 5?
+	{ -1,  1, 0, 1,  "GiS VA 6.2\""    } // 2.
+};
+
+static touch_info_t _touch_info = { 0 };
+static touch_panel_info_t _touch_panel_info = { 0 };
+
+static int _touch_command(u8 cmd, u8 *buf, u8 size)
+{
+	return i2c_send_buf_small(I2C_3, FTS4_I2C_ADDR, cmd, buf, size);
 }

-static int touch_read_reg(u8 *cmd, u32 csize, u8 *buf, u32 size)
+static int _touch_read_reg(u8 *cmd, u32 csize, u8 *buf, u32 size)
 {
-	int res = i2c_send_buf_small(I2C_3, STMFTS_I2C_ADDR, cmd[0], &cmd[1], csize - 1);
-	if (res)
-		res = i2c_recv_buf(buf, size, I2C_3, STMFTS_I2C_ADDR);
-	if (!res)
-		return 1;
-
-	return 0;
+	return i2c_xfer_packet(I2C_3, FTS4_I2C_ADDR, cmd, csize, buf, size);
 }

-static int touch_wait_event(u8 event, u8 status, u32 timeout)
+int touch_get_event_count()
+{
+	u8 cmd[3] = { FTS4_CMD_HW_REG_READ, 0, FTS4_HW_REG_EVENT_COUNT };
+	u8 buf[2];
+
+	if (_touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf)))
+		return 0;
+
+	return (buf[1] >> 1);
+}
+
+static int _touch_wait_event(u8 event, u8 status, u32 timeout, u8 *buf)
 {
 	u32 timer = get_tmr_ms() + timeout;
 	while (true)
 	{
-		u8 tmp[8] = {0};
-		i2c_recv_buf_small(tmp, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_READ_ONE_EVENT);
-		if (tmp[1] == event && tmp[2] == status)
+		if (!touch_get_event_count())
+			goto retry;
+
+		u8 tmp[FTS4_EVENT_SIZE];
+		int res = i2c_recv_buf_big(tmp, FTS4_EVENT_SIZE, I2C_3, FTS4_I2C_ADDR, FTS4_CMD_READ_ONE_EVENT);
+
+		// Check that event type and status match.
+		if (!res && tmp[0] == event && tmp[1] == status)
+		{
+			if (buf)
+				memcpy(buf, &tmp[2], 6);
 			return 0;
+		}
+
+retry:
+		usleep(500);

 		if (get_tmr_ms() > timer)
 			return 1;
@@ -72,145 +94,157 @@ static int touch_wait_event(u8 event, u8 status, u32 timeout)
 #define Y_REAL_MAX 704
 #define EDGE_OFFSET 15

-static void _touch_compensate_limits(touch_event *event, bool touching)
+static void _touch_compensate_limits(touch_event_t *event, bool touching)
 {
-	event->x = MAX(event->x, EDGE_OFFSET);
-	event->x = MIN(event->x, X_REAL_MAX);
+	event->x  = MAX(event->x, EDGE_OFFSET);
+	event->x  = MIN(event->x, X_REAL_MAX);
 	event->x -= EDGE_OFFSET;
 	u32 x_adj = (1280 * 1000) / (X_REAL_MAX - EDGE_OFFSET);
-	event->x = ((u32)event->x * x_adj) / 1000;
+	event->x  = ((u32)event->x * x_adj) / 1000;

 	if (touching)
 	{
-		event->y = MAX(event->y, EDGE_OFFSET);
-		event->y = MIN(event->y, Y_REAL_MAX);
+		event->y  = MAX(event->y, EDGE_OFFSET);
+		event->y  = MIN(event->y, Y_REAL_MAX);
 		event->y -= EDGE_OFFSET;
 		u32 y_adj = (720 * 1000) / (Y_REAL_MAX - EDGE_OFFSET);
-		event->y = ((u32)event->y * y_adj) / 1000;
+		event->y  = ((u32)event->y * y_adj) / 1000;
 	}
 }

-static void _touch_process_contact_event(touch_event *event, bool touching)
+static void _touch_process_contact_event(touch_event_t *event, bool touching)
 {
-	event->x = (event->raw[2] << 4) | ((event->raw[4] & STMFTS_MASK_Y_LSB) >> 4);
+	event->x = (event->raw[1] << 4) | ((event->raw[3] & FTS4_MASK_Y_LSB) >> 4);

 	// Normally, GUI elements have bigger horizontal estate.
 	// Avoid parsing y axis when finger is removed to minimize touch noise.
 	if (touching)
 	{
-		event->y = (event->raw[3] << 4) | (event->raw[4] & STMFTS_MASK_X_MSB);
+		event->y = (event->raw[2] << 4) | (event->raw[3] & FTS4_MASK_X_MSB);

-		event->z = event->raw[5] | (event->raw[6] << 8);
+		event->z = event->raw[4] | (event->raw[5] << 8);
 		event->z = event->z << 6;
+
 		u16 tmp = 0x40;
-		if ((event->raw[7] & 0x3F) != 1 && (event->raw[7] & 0x3F) != 0x3F)
-			tmp = event->raw[7] & 0x3F;
+		if ((event->raw[6] & 0x3F) != 1 && (event->raw[6] & 0x3F) != 0x3F)
+			tmp = event->raw[6] & 0x3F;
 		event->z /= tmp + 0x40;

-		event->fingers = ((event->raw[1] & STMFTS_MASK_TOUCH_ID) >> 4) + 1;
+		event->finger = ((event->raw[0] & FTS4_MASK_TOUCH_ID) >> 4) + 1;
 	}
 	else
-		event->fingers = 0;
+		event->finger = 0;

 	_touch_compensate_limits(event, touching);
 }

-static void _touch_parse_event(touch_event *event)
+static int _touch_parse_input_event(touch_event_t *event)
 {
-	event->type = event->raw[1] & STMFTS_MASK_EVENT_ID;
-
-	switch (event->type)
+	switch (event->raw[0] & FTS4_MASK_EVENT_ID)
 	{
-	case STMFTS_EV_MULTI_TOUCH_ENTER:
-	case STMFTS_EV_MULTI_TOUCH_MOTION:
+	case FTS4_EV_MULTI_TOUCH_ENTER:
+	case FTS4_EV_MULTI_TOUCH_MOTION:
 		_touch_process_contact_event(event, true);
-		if (event->z < 255) // Reject palm rest.
+		if (event->z < 500) // Reject palm rest.
 			event->touch = true;
 		else
-		{
 			event->touch = false;
-			event->type = STMFTS_EV_MULTI_TOUCH_LEAVE;
-		}
-		break;
-	case STMFTS_EV_MULTI_TOUCH_LEAVE:
+		return 0;
+
+	case FTS4_EV_MULTI_TOUCH_LEAVE:
 		event->touch = false;
 		_touch_process_contact_event(event, false);
-		break;
-	case STMFTS_EV_NO_EVENT:
-		if (event->touch)
-			event->type = STMFTS_EV_MULTI_TOUCH_MOTION;
-		break;
+		return 0;
+
 	default:
-		if (event->touch && event->raw[0] == STMFTS_EV_MULTI_TOUCH_MOTION)
-			event->type = STMFTS_EV_MULTI_TOUCH_MOTION;
-		else
-			event->type = STMFTS_EV_MULTI_TOUCH_LEAVE;
+		return 1; // No event.
+	}
+}
+
+int touch_poll(touch_event_t *event)
+{
+	u8 cmd = !_touch_info.clone ? FTS4_CMD_LATEST_EVENT : FTS4_CMD_READ_ONE_EVENT;
+
+	int res = i2c_recv_buf_big(event->raw, FTS4_EVENT_SIZE, I2C_3, FTS4_I2C_ADDR, cmd);
+	if (!res)
+		res = _touch_parse_input_event(event);
+
+	return res;
+}
+
+touch_info_t *touch_get_chip_info()
+{
+	u8 buf[7] = { 0 };
+
+	// Get chip info.
+	u8 cmd[3] = { FTS4_CMD_HW_REG_READ, 0, FTS4_HW_REG_CHIP_ID_INFO };
+	if (_touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf)))
+	{
+		memset(&_touch_info, 0, sizeof(touch_info_t));
+		goto exit;
 	}

-	// gfx_con_setpos(&gfx_con, 0, 300);
-	// DPRINTF("x = %d    \ny = %d    \nz = %d  \n", event->x, event->y, event->z);
-	// DPRINTF("0 = %02X\n1 = %02x\n2 = %02x\n3 = %02x\n", event->raw[0], event->raw[1], event->raw[2], event->raw[3]);
-	// DPRINTF("4 = %02X\n5 = %02x\n6 = %02x\n7 = %02x\n", event->raw[4], event->raw[5], event->raw[6], event->raw[7]);
+	_touch_info.chip_id    = buf[1] << 8 | buf[2];
+	_touch_info.fw_ver     = buf[3] << 8 | buf[4];
+	_touch_info.config_id  = buf[5];
+	_touch_info.config_ver = buf[6];
+
+	// Validate that device is genuine or proper.
+	cmd[2] = 2;
+	_touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf));
+	_touch_info.clone = _touch_info.chip_id != (buf[3] << 8 | buf[4]);
+
+exit:
+	return &_touch_info;
 }

-void touch_poll(touch_event *event)
+touch_panel_info_t *touch_get_panel_vendor()
 {
-	i2c_recv_buf_small(event->raw, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_LATEST_EVENT);
+	_touch_panel_info.idx = -2;

-	_touch_parse_event(event);
-}
+	u8 cmd = FTS4_VENDOR_GPIO_STATE;
+	if (_touch_command(FTS4_CMD_VENDOR, &cmd, 1))
+		return NULL;

-touch_event touch_poll_wait()
-{
-	touch_event event;
-	do
+	u8 buf[6] = { 0 };
+	if (_touch_wait_event(FTS4_EV_VENDOR, FTS4_VENDOR_GPIO_STATE, 2000, buf))
+		return NULL;
+
+	for (u32 i = 0; i < ARRAY_SIZE(_panels); i++)
 	{
-		touch_poll(&event);
-	} while (event.type != STMFTS_EV_MULTI_TOUCH_LEAVE);
+		touch_panel_info_t *panel = &_panels[i];
+		if (buf[0] == panel->gpio0 && buf[1] == panel->gpio1 && buf[2] == panel->gpio2)
+			return panel;
+	}

-	return event;
-}
+	// Touch panel not found, return current gpios.
+	_touch_panel_info.gpio0 = buf[0];
+	_touch_panel_info.gpio1 = buf[1];
+	_touch_panel_info.gpio2 = buf[2];

-touch_info touch_get_info()
-{
-	touch_info info;
-	u8 buf[8];
-	memset(&buf, 0, 8);
-	i2c_recv_buf_small(buf, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_READ_INFO);
-
-	info.chip_id = buf[0] << 8 | buf[1];
-	info.fw_ver = buf[2] << 8 | buf[3];
-	info.config_id = buf[4];
-	info.config_ver = buf[5];
-
-	//DPRINTF("ID: %04X, FW Ver: %d.%02d\nCfg ID: %02x, Cfg Ver: %d\n",
-	//	info.chip_id, info.fw_ver >> 8, info.fw_ver & 0xFF, info.config_id, info.config_ver);
-
-	return info;
+	return &_touch_panel_info;
 }

 int touch_get_fw_info(touch_fw_info_t *fw)
 {
-	u8 buf[8] = {0};
+	u8 buf[9] = { 0 };
+
+	memset(fw, 0, sizeof(touch_fw_info_t));

 	// Get fw address info.
-	u8 cmd[3] = { STMFTS_RW_FRAMEBUFFER_REG, 0, 0x60 };
-	int res = touch_read_reg(cmd, 3, buf, 3);
+	u8 cmd[3] = { FTS4_CMD_FB_REG_READ, 0, 0x60 };
+	int res = _touch_read_reg(cmd, sizeof(cmd), buf, 3);
 	if (!res)
 	{
 		// Get fw info.
 		cmd[1] = buf[2]; cmd[2] = buf[1];
-		res = touch_read_reg(cmd, 3, buf, 8);
+		res = _touch_read_reg(cmd, sizeof(cmd), buf, sizeof(buf));
 		if (!res)
 		{
-			fw->fw_id = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4];
-			fw->ftb_ver = (buf[6] << 8) | buf[5];
+			fw->fw_id   = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4];
+			fw->ftb_ver = (buf[6] <<  8) |  buf[5];
+			fw->fw_rev  = (buf[8] <<  8) |  buf[7];
 		}
-
-		cmd[2]++;
-		res = touch_read_reg(cmd, 3, buf, 8);
-		if (!res)
-			fw->fw_rev = (buf[7] << 8) | buf[6];
 	}

 	return res;
@@ -218,16 +252,17 @@ int touch_get_fw_info(touch_fw_info_t *fw)

 int touch_sys_reset()
 {
-	u8 cmd[3] = { 0, 0x28, 0x80 }; // System reset cmd.
+	u8 cmd[3] = { 0, FTS4_HW_REG_SYS_RESET, 0x80 }; // System reset cmd.
 	for (u8 retries = 0; retries < 3; retries++)
 	{
-		if (touch_command(STMFTS_WRITE_REG, cmd, 3))
+		if (_touch_command(FTS4_CMD_HW_REG_WRITE, cmd, 3))
 		{
 			msleep(10);
 			continue;
 		}
 		msleep(10);
-		if (touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20))
+
+		if (_touch_wait_event(FTS4_EV_CONTROLLER_READY, 0, 20, NULL))
 			continue;
 		else
 			return 0;
@@ -238,36 +273,25 @@ int touch_sys_reset()

 int touch_panel_ito_test(u8 *err)
 {
-	int res = 0;
+	// Check that touch IC is supported.
+	touch_info_t *info = touch_get_chip_info();
+	if (info->chip_id != FTS4_I2C_CHIP_ID || info->clone)
+		return 1;

 	// Reset touchscreen module.
 	if (touch_sys_reset())
-		return res;
+		return 1;

 	// Do ITO Production test.
-	u8 cmd[2] = { 1, 0 };
-	if (touch_command(STMFTS_ITO_CHECK, cmd, 2))
-		return res;
+	if (_touch_command(FTS4_CMD_ITO_CHECK, NULL, 0))
+		return 1;

-	u32 timer = get_tmr_ms() + 2000;
-	while (true)
+	u8 buf[6] = { 0 };
+	int res = _touch_wait_event(FTS4_EV_ERROR, FTS4_EV_ERROR_ITO_TEST, 2000, buf);
+	if (!res && err)
 	{
-		u8 tmp[8] = {0};
-		i2c_recv_buf_small(tmp, 8, I2C_3, STMFTS_I2C_ADDR, STMFTS_READ_ONE_EVENT);
-		if (tmp[1] == 0xF && tmp[2] == 0x5)
-		{
-			if (err)
-			{
-				err[0] = tmp[3];
-				err[1] = tmp[4];
-			}
-
-			res = 1;
-			break;
-		}
-
-		if (get_tmr_ms() > timer)
-			break;
+		err[0] = buf[0];
+		err[1] = buf[1];
 	}

 	// Reset touchscreen module.
@@ -278,20 +302,19 @@ int touch_panel_ito_test(u8 *err)

 int touch_get_fb_info(u8 *buf)
 {
-	u8 tmp[5];
-
-	u8 cmd[3] = { STMFTS_RW_FRAMEBUFFER_REG, 0, 0 };
+	u8 cmd[3] = { FTS4_CMD_FB_REG_READ, 0, 0 };
 	int res = 0;

-
-	for (u32 i = 0; i < 0x10000; i+=4)
+	for (u32 i = 0; i < 0x10000; i += 4)
 	{
 		if (!res)
 		{
 			cmd[1] = (i >> 8) & 0xFF;
 			cmd[2] = i & 0xFF;
-			memset(tmp, 0xCC, 5);
-			res = touch_read_reg(cmd, 3, tmp, 5);
+
+			u8 tmp[5];
+			memset(tmp, 0xCC, sizeof(tmp));
+			res = _touch_read_reg(cmd, sizeof(cmd), tmp, sizeof(tmp));
 			memcpy(&buf[i], tmp + 1, 4);
 		}
 	}
@@ -299,99 +322,124 @@ int touch_get_fb_info(u8 *buf)
 	return res;
 }

+int touch_switch_sense_mode(u8 mode, bool gis_6_2)
+{
+	// Set detection config.
+	u8 cmd[3] = { 1, 0x64, 0 };
+
+	switch (mode)
+	{
+	case FTS4_STYLUS_MODE:
+		cmd[2] = !gis_6_2 ? 0xC8 : 0xAD;
+		break;
+	case FTS4_FINGER_MODE:
+		cmd[2] = !gis_6_2 ? 0x8C : 0x79;
+		break;
+	}
+
+	if (_touch_command(FTS4_CMD_DETECTION_CONFIG, cmd, 3))
+		return 1;
+
+	// Sense mode.
+	cmd[0] = mode;
+
+	return _touch_command(FTS4_CMD_SWITCH_SENSE_MODE, cmd, 1);
+}
+
 int touch_sense_enable()
 {
-	// Enable auto tuning calibration and multi-touch sensing.
-	u8 cmd = 1;
-	if (touch_command(STMFTS_AUTO_CALIBRATION, &cmd, 1))
-		return 0;
+	// Switch sense mode and enable multi-touch sensing.
+	u8 cmd = FTS4_FINGER_MODE;
+	if (_touch_command(FTS4_CMD_SWITCH_SENSE_MODE, &cmd, 1))
+		return 1;

-	if (touch_command(STMFTS_MS_MT_SENSE_ON, NULL, 0))
-		return 0;
+	if (_touch_command(FTS4_CMD_MS_MT_SENSE_ON, NULL, 0))
+		return 1;

-	if (touch_command(STMFTS_CLEAR_EVENT_STACK, NULL, 0))
-		return 0;
+	if (_touch_command(FTS4_CMD_CLEAR_EVENT_STACK, NULL, 0))
+		return 1;

-	return 1;
+	return 0;
 }

 int touch_execute_autotune()
 {
+	u8 buf[6] = { 0 };
+
 	// Reset touchscreen module.
 	if (touch_sys_reset())
-		return 0;
+		return 1;

 	// Trim low power oscillator.
-	if (touch_command(STMFTS_LP_TIMER_CALIB, NULL, 0))
-		return 0;
+	if (_touch_command(FTS4_CMD_LP_TIMER_CALIB, NULL, 0))
+		return 1;
+
 	msleep(200);

 	// Apply Mutual Sense Compensation tuning.
-	if (touch_command(STMFTS_MS_CX_TUNING, NULL, 0))
-		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_MS_CX_TUNING_DONE, 2000))
-		return 0;
+	if (_touch_command(FTS4_CMD_MS_CX_TUNING, NULL, 0))
+		return 1;
+	if (_touch_wait_event(FTS4_EV_STATUS, FTS4_EV_STATUS_MS_CX_TUNING_DONE, 2000, buf) || buf[0] || buf[1])
+		return 1;

 	// Apply Self Sense Compensation tuning.
-	if (touch_command(STMFTS_SS_CX_TUNING, NULL, 0))
-		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_SS_CX_TUNING_DONE, 2000))
-		return 0;
+	if (_touch_command(FTS4_CMD_SS_CX_TUNING, NULL, 0))
+		return 1;
+	if (_touch_wait_event(FTS4_EV_STATUS, FTS4_EV_STATUS_SS_CX_TUNING_DONE, 2000, buf) || buf[0] || buf[1])
+		return 1;

 	// Save Compensation data to EEPROM.
-	if (touch_command(STMFTS_SAVE_CX_TUNING, NULL, 0))
-		return 0;
-	if (touch_wait_event(STMFTS_EV_STATUS, STMFTS_EV_STATUS_WRITE_CX_TUNE_DONE, 2000))
-		return 0;
+	if (_touch_command(FTS4_CMD_SAVE_CX_TUNING, NULL, 0))
+		return 1;
+	if (_touch_wait_event(FTS4_EV_STATUS, FTS4_EV_STATUS_WRITE_CX_TUNE_DONE, 2000, buf) || buf[0] || buf[1])
+		return 1;

 	return touch_sense_enable();
 }

 static int touch_init()
 {
+	// Check that touch IC is supported.
+	touch_info_t *info = touch_get_chip_info();
+	if (info->chip_id != FTS4_I2C_CHIP_ID)
+		return 1;
+
 	// Initialize touchscreen module.
 	if (touch_sys_reset())
-		return 0;
+		return 1;

 	return touch_sense_enable();
 }

 int touch_power_on()
 {
-	// Enables LDO6 for touchscreen VDD/AVDD supply
-	max77620_regulator_set_volt_and_flags(REGULATOR_LDO6, 2900000, MAX77620_POWER_MODE_NORMAL);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2,
-		MAX77620_LDO_CFG2_ADE_ENABLE | (3 << 3) | (MAX77620_POWER_MODE_NORMAL << MAX77620_LDO_POWER_MODE_SHIFT));
-
-	// Configure touchscreen GPIO.
+	// Configure touchscreen Touch Reset pin.
 	PINMUX_AUX(PINMUX_AUX_DAP4_SCLK) = PINMUX_PULL_DOWN | 1;
-	gpio_config(GPIO_PORT_J, GPIO_PIN_7, GPIO_MODE_GPIO);
-	gpio_output_enable(GPIO_PORT_J, GPIO_PIN_7, GPIO_OUTPUT_ENABLE);
-	gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_HIGH);
+	gpio_direction_output(GPIO_PORT_J, GPIO_PIN_7, GPIO_LOW);
+	usleep(20);

-	// IRQ and more.
-	// PINMUX_AUX(PINMUX_AUX_TOUCH_INT) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 3;
-	// gpio_config(GPIO_PORT_X, GPIO_PIN_1, GPIO_MODE_GPIO);
-	// gpio_write(GPIO_PORT_X, GPIO_PIN_1, GPIO_LOW);
-
-	// Configure Touscreen and GCAsic shared GPIO.
-	PINMUX_AUX(PINMUX_AUX_CAM_I2C_SDA) = PINMUX_LPDR | PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 2;
-	PINMUX_AUX(PINMUX_AUX_CAM_I2C_SCL) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_TRISTATE | PINMUX_PULL_DOWN | 2;
-	gpio_config(GPIO_PORT_S, GPIO_PIN_3, GPIO_MODE_GPIO);
+	// Enable LDO6 for touchscreen AVDD and DVDD supply.
+	max7762x_regulator_set_voltage(REGULATOR_LDO6, 2900000);
+	max7762x_regulator_enable(REGULATOR_LDO6, true);

 	// Initialize I2C3.
 	pinmux_config_i2c(I2C_3);
 	clock_enable_i2c(I2C_3);
 	i2c_init(I2C_3);
+	usleep(1000);
+
+	// Set Touch Reset pin.
+	gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_HIGH);
+	usleep(10000);

 	// Wait for the touchscreen module to get ready.
-	touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20);
+	_touch_wait_event(FTS4_EV_CONTROLLER_READY, 0, 20, NULL);

 	// Check for forced boot time calibration.
 	if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN))
 	{
 		u8 err[2];
-		if (touch_panel_ito_test(err))
+		if (!touch_panel_ito_test(err))
 			if (!err[0] && !err[1])
 				return touch_execute_autotune();
 	}
@@ -400,12 +448,12 @@ int touch_power_on()
 	u32 retries = 3;
 	while (retries)
 	{
-		if (touch_init())
-			return 1;
+		if (!touch_init())
+			return 0;
 		retries--;
 	}

-	return 0;
+	return 1;
 }

 void touch_power_off()
@@ -414,9 +462,7 @@ void touch_power_off()
 	gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_LOW);

 	// Disables LDO6 for touchscreen VDD, AVDD supply
-	max77620_regulator_enable(REGULATOR_LDO6, 0);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2,
-		MAX77620_LDO_CFG2_ADE_ENABLE | (2 << 3) | (MAX77620_POWER_MODE_NORMAL << MAX77620_LDO_POWER_MODE_SHIFT));
+	max7762x_regulator_enable(REGULATOR_LDO6, false);

 	clock_disable_i2c(I2C_3);
-}
+}
--- a/bdk/input/touch.h
+++ b/bdk/input/touch.h
@@ -2,7 +2,7 @@
 * Touch driver for Nintendo Switch's STM FingerTip S (4CD60D) touch controller
 *
 * Copyright (c) 2018 langerhans
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -22,83 +22,100 @@

 #include <utils/types.h>

-#define STMFTS_I2C_ADDR 0x49
+#define FTS4_I2C_ADDR 0x49

-/* I2C commands */
-#define STMFTS_READ_INFO               0x80
-#define STMFTS_READ_STATUS             0x84
-#define STMFTS_READ_ONE_EVENT          0x85
-#define STMFTS_READ_ALL_EVENT          0x86
-#define STMFTS_LATEST_EVENT            0x87
-#define STMFTS_SLEEP_IN                0x90
-#define STMFTS_SLEEP_OUT               0x91
-#define STMFTS_MS_MT_SENSE_OFF         0x92
-#define STMFTS_MS_MT_SENSE_ON          0x93
-#define STMFTS_SS_HOVER_SENSE_OFF      0x94
-#define STMFTS_SS_HOVER_SENSE_ON       0x95
-#define STMFTS_LP_TIMER_CALIB          0x97
-#define STMFTS_MS_KEY_SENSE_OFF        0x9A
-#define STMFTS_MS_KEY_SENSE_ON         0x9B
-#define STMFTS_SYSTEM_RESET            0xA0
-#define STMFTS_CLEAR_EVENT_STACK       0xA1
-#define STMFTS_FULL_FORCE_CALIBRATION  0xA2
-#define STMFTS_MS_CX_TUNING            0xA3
-#define STMFTS_SS_CX_TUNING            0xA4
-#define STMFTS_ITO_CHECK               0xA7
-#define STMFTS_RELEASEINFO             0xAA
-#define STMFTS_WRITE_REG               0xB6
-#define STMFTS_AUTO_CALIBRATION        0xC3
-#define STMFTS_NOISE_WRITE             0xC7
-#define STMFTS_NOISE_READ              0xC8
-#define STMFTS_RW_FRAMEBUFFER_REG      0xD0
-#define STMFTS_SAVE_CX_TUNING          0xFC
+#define FTS4_I2C_CHIP_ID 0x3670

-#define STMFTS_UNK0 0xB8 //Request compensation
-#define STMFTS_UNK1 0xCF
-#define STMFTS_UNK2 0xF7
-#define STMFTS_UNK3 0xFA
-#define STMFTS_UNK4 0xF9
-#define STMFTS_UNK5 0x62
+/* I2C commands. */
+#define FTS4_CMD_READ_INFO           0x80
+#define FTS4_CMD_READ_STATUS         0x84
+#define FTS4_CMD_READ_ONE_EVENT      0x85
+#define FTS4_CMD_READ_ALL_EVENT      0x86
+#define FTS4_CMD_LATEST_EVENT        0x87 // Clears event stack.
+#define FTS4_CMD_SLEEP_IN            0x90
+#define FTS4_CMD_SLEEP_OUT           0x91
+#define FTS4_CMD_MS_MT_SENSE_OFF     0x92
+#define FTS4_CMD_MS_MT_SENSE_ON      0x93
+#define FTS4_CMD_SS_HOVER_SENSE_OFF  0x94
+#define FTS4_CMD_SS_HOVER_SENSE_ON   0x95
+#define FTS4_CMD_LP_TIMER_CALIB      0x97
+#define FTS4_CMD_MS_KEY_SENSE_OFF    0x9A
+#define FTS4_CMD_MS_KEY_SENSE_ON     0x9B
+#define FTS4_CMD_SYSTEM_RESET        0xA0
+#define FTS4_CMD_CLEAR_EVENT_STACK   0xA1
+#define FTS4_CMD_FULL_FORCE_CALIB    0xA2
+#define FTS4_CMD_MS_CX_TUNING        0xA3
+#define FTS4_CMD_SS_CX_TUNING        0xA4
+#define FTS4_CMD_ITO_CHECK           0xA7
+#define FTS4_CMD_RELEASEINFO         0xAA
+#define FTS4_CMD_HW_REG_READ         0xB6                 // u16be address offset. Any size read.
+#define FTS4_CMD_HW_REG_WRITE        FTS4_CMD_HW_REG_READ // u16be address offset, bytes to write.
+#define FTS4_CMD_SWITCH_SENSE_MODE   0xC3
+#define FTS4_CMD_NOISE_WRITE         0xC7
+#define FTS4_CMD_NOISE_READ          0xC8
+#define FTS4_CMD_FB_REG_READ         0xD0
+#define FTS4_CMD_FB_REG_WRITE        FTS4_CMD_FB_REG_READ
+#define FTS4_CMD_SAVE_CX_TUNING      0xFC

+#define FTS4_CMD_DETECTION_CONFIG    0xB0
+#define FTS4_CMD_REQ_CX_DATA         0xB8
+#define FTS4_CMD_VENDOR              0xCF
+#define FTS4_CMD_FLASH_UNLOCK        0xF7
+#define FTS4_CMD_FLASH_WRITE_64K     0xF8
+#define FTS4_CMD_FLASH_STATUS        0xF9
+#define FTS4_CMD_FLASH_OP            0xFA
+#define FTS4_CMD_UNK_62 0x62

-/* events */
-#define STMFTS_EV_NO_EVENT             0x00
-#define STMFTS_EV_MULTI_TOUCH_DETECTED 0x02
-#define STMFTS_EV_MULTI_TOUCH_ENTER    0x03
-#define STMFTS_EV_MULTI_TOUCH_LEAVE    0x04
-#define STMFTS_EV_MULTI_TOUCH_MOTION   0x05
-#define STMFTS_EV_HOVER_ENTER          0x07
-#define STMFTS_EV_HOVER_LEAVE          0x08
-#define STMFTS_EV_HOVER_MOTION         0x09
-#define STMFTS_EV_KEY_STATUS           0x0e
-#define STMFTS_EV_ERROR                0x0f
-#define STMFTS_EV_NOISE_READ           0x17
-#define STMFTS_EV_NOISE_WRITE          0x18
+/* Command parameters. */
+#define FTS4_VENDOR_GPIO_STATE       0x01
+#define FTS4_VENDOR_SENSE_MODE       0x02
+#define FTS4_STYLUS_MODE             0x00
+#define FTS4_FINGER_MODE             0x01
+#define FTS4_HOVER_MODE              0x02

-#define STMFTS_EV_CONTROLLER_READY     0x10
-#define STMFTS_EV_STATUS               0x16
-#define STMFTS_EV_DEBUG                0xDB
+/* HW Registers */
+#define FTS4_HW_REG_CHIP_ID_INFO     0x0004
+#define FTS4_HW_REG_EVENT_COUNT      0x0023
+#define FTS4_HW_REG_SYS_RESET        0x0028

-#define STMFTS_EV_STATUS_MS_CX_TUNING_DONE  1
-#define STMFTS_EV_STATUS_SS_CX_TUNING_DONE  2
-#define STMFTS_EV_STATUS_WRITE_CX_TUNE_DONE 4
+/* FB Addresses */
+#define FTS4_FB_REG_FW_INFO_ADDRESS  0x0060

-/* multi touch related event masks */
-#define STMFTS_MASK_EVENT_ID   0x0F
-#define STMFTS_MASK_TOUCH_ID   0xF0
-#define STMFTS_MASK_LEFT_EVENT 0x0F
-#define STMFTS_MASK_X_MSB      0x0F
-#define STMFTS_MASK_Y_LSB      0xF0
+/* Events. */
+#define FTS4_EV_NO_EVENT             0x00
+#define FTS4_EV_MULTI_TOUCH_DETECTED 0x02
+#define FTS4_EV_MULTI_TOUCH_ENTER    0x03
+#define FTS4_EV_MULTI_TOUCH_LEAVE    0x04
+#define FTS4_EV_MULTI_TOUCH_MOTION   0x05
+#define FTS4_EV_HOVER_ENTER          0x07
+#define FTS4_EV_HOVER_LEAVE          0x08
+#define FTS4_EV_HOVER_MOTION         0x09
+#define FTS4_EV_KEY_STATUS           0x0E
+#define FTS4_EV_ERROR                0x0F
+#define FTS4_EV_CONTROLLER_READY     0x10
+#define FTS4_EV_STATUS               0x16
+#define FTS4_EV_NOISE_READ           0x17
+#define FTS4_EV_NOISE_WRITE          0x18
+#define FTS4_EV_VENDOR               0x20
+#define FTS4_EV_DEBUG                0xDB

-/* key related event masks */
-#define STMFTS_MASK_KEY_NO_TOUCH 0x00
-#define STMFTS_MASK_KEY_MENU     0x01
-#define STMFTS_MASK_KEY_BACK     0x02
+/* FTS4_EV_STATUS Events. */
+#define FTS4_EV_STATUS_MS_CX_TUNING_DONE  0x01
+#define FTS4_EV_STATUS_SS_CX_TUNING_DONE  0x02
+#define FTS4_EV_STATUS_WRITE_CX_TUNE_DONE 0x04

-#define STMFTS_EVENT_SIZE     8
-#define STMFTS_STACK_DEPTH   32
-#define STMFTS_DATA_MAX_SIZE (STMFTS_EVENT_SIZE * STMFTS_STACK_DEPTH)
-#define STMFTS_MAX_FINGERS   10
+#define FTS4_EV_ERROR_ITO_TEST            0x05
+
+/* Multi touch related event masks. */
+#define FTS4_MASK_EVENT_ID   0x0F
+#define FTS4_MASK_TOUCH_ID   0xF0
+#define FTS4_MASK_X_MSB      0x0F
+#define FTS4_MASK_Y_LSB      0xF0
+
+#define FTS4_EVENT_SIZE     8
+#define FTS4_STACK_DEPTH   32 // Actual 128.
+#define FTS4_DATA_MAX_SIZE (FTS4_EVENT_SIZE * FTS4_STACK_DEPTH)
+#define FTS4_MAX_FINGERS   10

 typedef enum _touch_ito_error {
 	ITO_NO_ERROR = 0,
@@ -121,22 +138,30 @@ typedef enum _touch_ito_error {
 	ITO_MAX_ERR_REACHED = 0xFF
 } touch_ito_error;

-typedef struct _touch_event {
-	u8   raw[8];
-	u16  type; // Event type.
-	u16  x;    // Horizontal coordinates.
-	u16  y;    // Vertical coordinates.
-	u32  z;
-	u8   fingers;
+typedef struct _touch_event_t {
+	u8   raw[FTS4_EVENT_SIZE];
+	u16  x, y; // Coordinates.
+	u32  z;    // Orientation.
 	bool touch;
-} touch_event;
+	int  finger;
+} touch_event_t;

-typedef struct _touch_info {
-	u16 chip_id;
-	u16 fw_ver;
-	u16 config_id;
-	u16 config_ver;
-} touch_info;
+typedef struct _touch_panel_info_t
+{
+	u8 idx;
+	u8 gpio0;
+	u8 gpio1;
+	u8 gpio2;
+	char *vendor;
+} touch_panel_info_t;
+
+typedef struct _touch_info_t {
+	u16  chip_id;
+	u16  fw_ver;
+	u16  config_id;
+	u16  config_ver;
+	bool clone;
+} touch_info_t;

 typedef struct _touch_fw_info_t {
 	u32 fw_id;
@@ -144,14 +169,16 @@ typedef struct _touch_fw_info_t {
 	u16 fw_rev;
 } touch_fw_info_t;

-void touch_poll(touch_event *event);
-touch_event touch_poll_wait();
+int touch_poll(touch_event_t *event);
+touch_info_t *touch_get_chip_info();
+touch_panel_info_t *touch_get_panel_vendor();
 int touch_get_fw_info(touch_fw_info_t *fw);
-touch_info touch_get_info();
+int touch_get_event_count();
 int touch_panel_ito_test(u8 *err);
 int touch_execute_autotune();
+int touch_switch_sense_mode(u8 mode, bool gis_6_2);
 int touch_sense_enable();
 int touch_power_on();
 void touch_power_off();

-#endif /* __TOUCH_H_ */
+#endif /* __TOUCH_H_ */
--- a/bdk/libs/compr/blz.c
+++ b/bdk/libs/compr/blz.c
@@ -20,33 +20,33 @@

 #include "blz.h"

-const blz_footer *blz_get_footer(const unsigned char *compData, unsigned int compDataLen, blz_footer *outFooter)
+const blz_footer *blz_get_footer(const u8 *comp_data, u32 comp_data_size, blz_footer *out_footer)
 {
-	if (compDataLen < sizeof(blz_footer))
+	if (comp_data_size < sizeof(blz_footer))
 		return NULL;

-	const blz_footer *srcFooter = (const blz_footer*)&compData[compDataLen - sizeof(blz_footer)];
-	if (outFooter != NULL)
-		memcpy(outFooter, srcFooter, sizeof(blz_footer)); // Must be a memcpy because no umaligned accesses on ARMv4.
+	const blz_footer *src_footer = (const blz_footer *)&comp_data[comp_data_size - sizeof(blz_footer)];
+	if (out_footer)
+		memcpy(out_footer, src_footer, sizeof(blz_footer)); // Must be a memcpy because no unaligned accesses on ARMv4.

-	return srcFooter;
+	return src_footer;
 }

 // From https://github.com/SciresM/hactool/blob/master/kip.c which is exactly how kernel does it, thanks SciresM!
-int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const blz_footer *footer)
+int blz_uncompress_inplace(u8 *data, u32 comp_size, const blz_footer *footer)
 {
 	u32 addl_size = footer->addl_size;
 	u32 header_size = footer->header_size;
 	u32 cmp_and_hdr_size = footer->cmp_and_hdr_size;

-	unsigned char* cmp_start = &dataBuf[compSize] - cmp_and_hdr_size;
+	u8 *cmp_start = &data[comp_size] - cmp_and_hdr_size;
 	u32 cmp_ofs = cmp_and_hdr_size - header_size;
 	u32 out_ofs = cmp_and_hdr_size + addl_size;

 	while (out_ofs)
 	{
-		unsigned char control = cmp_start[--cmp_ofs];
-		for (unsigned int i=0; i<8; i++)
+		u8 control = cmp_start[--cmp_ofs];
+		for (u32 i = 0; i < 8; i++)
 		{
 			if (control & 0x80)
 			{
@@ -54,45 +54,48 @@ int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const
 					return 0; // Out of bounds.

 				cmp_ofs -= 2;
-				u16 seg_val = ((unsigned int)(cmp_start[cmp_ofs + 1]) << 8) | cmp_start[cmp_ofs];
+				u16 seg_val = ((u32)(cmp_start[cmp_ofs + 1]) << 8) | cmp_start[cmp_ofs];
 				u32 seg_size = ((seg_val >> 12) & 0xF) + 3;
 				u32 seg_ofs = (seg_val & 0x0FFF) + 3;
-				if (out_ofs < seg_size) // Kernel restricts segment copy to stay in bounds.
+
+				// Kernel restricts segment copy to stay in bounds.
+				if (out_ofs < seg_size)
 					seg_size = out_ofs;

 				out_ofs -= seg_size;

-				for (unsigned int j = 0; j < seg_size; j++)
+				for (u32 j = 0; j < seg_size; j++)
 					cmp_start[out_ofs + j] = cmp_start[out_ofs + j + seg_ofs];
 			}
-			else
+			else // Copy directly.
 			{
-				// Copy directly.
 				if (cmp_ofs < 1)
-					return 0; //out of bounds
+					return 0; // Out of bounds.

 				cmp_start[--out_ofs] = cmp_start[--cmp_ofs];
 			}
+
 			control <<= 1;
-			if (out_ofs == 0) // Blz works backwards, so if it reaches byte 0, it's done.
+
+			if (!out_ofs) // Blz works backwards, so if it reaches byte 0, it's done.
 				return 1;
-			}
 		}
+	}

 	return 1;
 }

-int blz_uncompress_srcdest(const unsigned char *compData, unsigned int compDataLen, unsigned char *dstData, unsigned int dstSize)
+int blz_uncompress_srcdest(const u8 *comp_data, u32 comp_data_size, u8 *dst_data, u32 dst_size)
 {
 	blz_footer footer;
-	const blz_footer *compFooterPtr = blz_get_footer(compData, compDataLen, &footer);
-	if (compFooterPtr == NULL)
+	const blz_footer *comp_footer = blz_get_footer(comp_data, comp_data_size, &footer);
+	if (!comp_footer)
 		return 0;

-	// Decompression must be done in-place, so need to copy the relevant compressed data first.
-	unsigned int numCompBytes = (const unsigned char*)(compFooterPtr)-compData;
-	memcpy(dstData, compData, numCompBytes);
-	memset(&dstData[numCompBytes], 0, dstSize - numCompBytes);
+	// Decompression happens in-place, so need to copy the relevant compressed data first.
+	u32 comp_bytes = (const u8 *)comp_footer - comp_data;
+	memcpy(dst_data, comp_data, comp_bytes);
+	memset(&dst_data[comp_bytes], 0, dst_size - comp_bytes);

-	return blz_uncompress_inplace(dstData, compDataLen, &footer);
+	return blz_uncompress_inplace(dst_data, comp_data_size, &footer);
 }
--- a/bdk/libs/compr/blz.h
+++ b/bdk/libs/compr/blz.h
@@ -26,11 +26,11 @@ typedef struct _blz_footer
 	u32 addl_size;
 } blz_footer;

-// Returns pointer to footer in compData if present, additionally copies it to outFooter if not NULL.
-const blz_footer *blz_get_footer(const unsigned char *compData, unsigned int compDataLen, blz_footer *outFooter);
+// Returns pointer to footer in comp_data if present, additionally copies it to out_footer if not NULL.
+const blz_footer *blz_get_footer(const u8 *comp_data, u32 comp_data_size, blz_footer *out_footer);
 // Returns 0 on failure.
-int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const blz_footer *footer);
+int blz_uncompress_inplace(u8 *data, u32 comp_size, const blz_footer *footer);
 // Returns 0 on failure.
-int blz_uncompress_srcdest(const unsigned char *compData, unsigned int compDataLen, unsigned char *dstData, unsigned int dstSize);
+int blz_uncompress_srcdest(const u8 *comp_data, u32 comp_data_size, u8 *dst_data, u32 dst_size);

 #endif
--- a/bdk/libs/compr/lz.c
+++ b/bdk/libs/compr/lz.c
@@ -125,7 +125,7 @@ static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf )
 *  insize  - Number of input bytes.
 *************************************************************************/

-void LZ_Uncompress( const unsigned char *in, unsigned char *out,
+unsigned int LZ_Uncompress( const unsigned char *in, unsigned char *out,
    unsigned int insize )
 {
    unsigned char marker, symbol;
@@ -134,7 +134,7 @@ void LZ_Uncompress( const unsigned char *in, unsigned char *out,
    /* Do we have anything to uncompress? */
    if( insize < 1 )
    {
-        return;
+        return 0;
    }

    /* Get marker symbol from input stream */
@@ -176,4 +176,6 @@ void LZ_Uncompress( const unsigned char *in, unsigned char *out,
        }
    }
    while( inpos < insize );
+
+    return outpos;
 }
--- a/bdk/libs/compr/lz.h
+++ b/bdk/libs/compr/lz.h
@@ -41,7 +41,7 @@ extern "C" {
 * Function prototypes
 *************************************************************************/

-void LZ_Uncompress( const unsigned char *in, unsigned char *out,
+unsigned int LZ_Uncompress( const unsigned char *in, unsigned char *out,
                    unsigned int insize );


--- a/bdk/libs/compr/lz4.c
+++ b/bdk/libs/compr/lz4.c
--- a/bdk/libs/compr/lz4.h
+++ b/bdk/libs/compr/lz4.h
@@ -0,0 +1,569 @@
+/*
+ *  LZ4 - Fast LZ compression algorithm
+ *  Header File
+ *  Copyright (C) 2011-2017, Yann Collet.
+
+   BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+
+       * Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above
+   copyright notice, this list of conditions and the following disclaimer
+   in the documentation and/or other materials provided with the
+   distribution.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+   You can contact the author at :
+    - LZ4 homepage : http://www.lz4.org
+    - LZ4 source repository : https://github.com/lz4/lz4
+*/
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+#ifndef LZ4_H_2983827168210
+#define LZ4_H_2983827168210
+
+/* --- Dependency --- */
+#include <stddef.h>   /* size_t */
+
+
+/**
+  Introduction
+
+  LZ4 is lossless compression algorithm, providing compression speed at 400 MB/s per core,
+  scalable with multi-cores CPU. It features an extremely fast decoder, with speed in
+  multiple GB/s per core, typically reaching RAM speed limits on multi-core systems.
+
+  The LZ4 compression library provides in-memory compression and decompression functions.
+  Compression can be done in:
+    - a single step (described as Simple Functions)
+    - a single step, reusing a context (described in Advanced Functions)
+    - unbounded multiple steps (described as Streaming compression)
+
+  lz4.h provides block compression functions. It gives full buffer control to user.
+  Decompressing an lz4-compressed block also requires metadata (such as compressed size).
+  Each application is free to encode such metadata in whichever way it wants.
+
+  An additional format, called LZ4 frame specification (doc/lz4_Frame_format.md),
+  take care of encoding standard metadata alongside LZ4-compressed blocks.
+  If your application requires interoperability, it's recommended to use it.
+  A library is provided to take care of it, see lz4frame.h.
+*/
+
+/*^***************************************************************
+*  Export parameters
+*****************************************************************/
+/*
+*  LZ4_DLL_EXPORT :
+*  Enable exporting of functions when building a Windows DLL
+*  LZ4LIB_VISIBILITY :
+*  Control library symbols visibility.
+*/
+#ifndef LZ4LIB_VISIBILITY
+#  if defined(__GNUC__) && (__GNUC__ >= 4)
+#    define LZ4LIB_VISIBILITY __attribute__ ((visibility ("default")))
+#  else
+#    define LZ4LIB_VISIBILITY
+#  endif
+#endif
+#if defined(LZ4_DLL_EXPORT) && (LZ4_DLL_EXPORT==1)
+#  define LZ4LIB_API __declspec(dllexport) LZ4LIB_VISIBILITY
+#elif defined(LZ4_DLL_IMPORT) && (LZ4_DLL_IMPORT==1)
+#  define LZ4LIB_API __declspec(dllimport) LZ4LIB_VISIBILITY /* It isn't required but allows to generate better code, saving a function pointer load from the IAT and an indirect jump.*/
+#else
+#  define LZ4LIB_API LZ4LIB_VISIBILITY
+#endif
+
+/*------   Version   ------*/
+#define LZ4_VERSION_MAJOR    1    /* for breaking interface changes  */
+#define LZ4_VERSION_MINOR    8    /* for new (non-breaking) interface capabilities */
+#define LZ4_VERSION_RELEASE  2    /* for tweaks, bug-fixes, or development */
+
+#define LZ4_VERSION_NUMBER (LZ4_VERSION_MAJOR *100*100 + LZ4_VERSION_MINOR *100 + LZ4_VERSION_RELEASE)
+
+#define LZ4_LIB_VERSION LZ4_VERSION_MAJOR.LZ4_VERSION_MINOR.LZ4_VERSION_RELEASE
+#define LZ4_QUOTE(str) #str
+#define LZ4_EXPAND_AND_QUOTE(str) LZ4_QUOTE(str)
+#define LZ4_VERSION_STRING LZ4_EXPAND_AND_QUOTE(LZ4_LIB_VERSION)
+
+LZ4LIB_API int LZ4_versionNumber (void);  /**< library version number; useful to check dll version */
+LZ4LIB_API const char* LZ4_versionString (void);   /**< library version string; unseful to check dll version */
+
+
+/*-************************************
+*  Tuning parameter
+**************************************/
+/*!
+ * LZ4_MEMORY_USAGE :
+ * Memory usage formula : N->2^N Bytes (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB; etc.)
+ * Increasing memory usage improves compression ratio
+ * Reduced memory usage may improve speed, thanks to cache effect
+ * Default value is 14, for 16KB, which nicely fits into Intel x86 L1 cache
+ */
+#ifndef LZ4_MEMORY_USAGE
+# define LZ4_MEMORY_USAGE 14
+#endif
+
+/*-************************************
+*  Simple Functions
+**************************************/
+/*! LZ4_compress_default() :
+    Compresses 'srcSize' bytes from buffer 'src'
+    into already allocated 'dst' buffer of size 'dstCapacity'.
+    Compression is guaranteed to succeed if 'dstCapacity' >= LZ4_compressBound(srcSize).
+    It also runs faster, so it's a recommended setting.
+    If the function cannot compress 'src' into a more limited 'dst' budget,
+    compression stops *immediately*, and the function result is zero.
+    Note : as a consequence, 'dst' content is not valid.
+    Note 2 : This function is protected against buffer overflow scenarios (never writes outside 'dst' buffer, nor read outside 'source' buffer).
+        srcSize : max supported value is LZ4_MAX_INPUT_SIZE.
+        dstCapacity : size of buffer 'dst' (which must be already allocated)
+        return  : the number of bytes written into buffer 'dst' (necessarily <= dstCapacity)
+                  or 0 if compression fails */
+LZ4LIB_API int LZ4_compress_default(const char* src, char* dst, int srcSize, int dstCapacity);
+
+/*! LZ4_decompress_safe() :
+    compressedSize : is the exact complete size of the compressed block.
+    dstCapacity : is the size of destination buffer, which must be already allocated.
+    return : the number of bytes decompressed into destination buffer (necessarily <= dstCapacity)
+             If destination buffer is not large enough, decoding will stop and output an error code (negative value).
+             If the source stream is detected malformed, the function will stop decoding and return a negative result.
+             This function is protected against malicious data packets.
+*/
+LZ4LIB_API int LZ4_decompress_safe (const char* src, char* dst, int compressedSize, int dstCapacity);
+
+
+/*-************************************
+*  Advanced Functions
+**************************************/
+#define LZ4_MAX_INPUT_SIZE        0x7E000000   /* 2 113 929 216 bytes */
+#define LZ4_COMPRESSBOUND(isize)  ((unsigned)(isize) > (unsigned)LZ4_MAX_INPUT_SIZE ? 0 : (isize) + ((isize)/255) + 16)
+
+/*!
+LZ4_compressBound() :
+    Provides the maximum size that LZ4 compression may output in a "worst case" scenario (input data not compressible)
+    This function is primarily useful for memory allocation purposes (destination buffer size).
+    Macro LZ4_COMPRESSBOUND() is also provided for compilation-time evaluation (stack memory allocation for example).
+    Note that LZ4_compress_default() compresses faster when dstCapacity is >= LZ4_compressBound(srcSize)
+        inputSize  : max supported value is LZ4_MAX_INPUT_SIZE
+        return : maximum output size in a "worst case" scenario
+              or 0, if input size is incorrect (too large or negative)
+*/
+LZ4LIB_API int LZ4_compressBound(int inputSize);
+
+/*!
+LZ4_compress_fast() :
+    Same as LZ4_compress_default(), but allows selection of "acceleration" factor.
+    The larger the acceleration value, the faster the algorithm, but also the lesser the compression.
+    It's a trade-off. It can be fine tuned, with each successive value providing roughly +~3% to speed.
+    An acceleration value of "1" is the same as regular LZ4_compress_default()
+    Values <= 0 will be replaced by ACCELERATION_DEFAULT (currently == 1, see lz4.c).
+*/
+LZ4LIB_API int LZ4_compress_fast (const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+
+/*!
+LZ4_compress_fast_extState() :
+    Same compression function, just using an externally allocated memory space to store compression state.
+    Use LZ4_sizeofState() to know how much memory must be allocated,
+    and allocate it on 8-bytes boundaries (using malloc() typically).
+    Then, provide it as 'void* state' to compression function.
+*/
+LZ4LIB_API int LZ4_sizeofState(void);
+LZ4LIB_API int LZ4_compress_fast_extState (void* state, const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+
+/*!
+LZ4_compress_destSize() :
+    Reverse the logic : compresses as much data as possible from 'src' buffer
+    into already allocated buffer 'dst' of size 'targetDestSize'.
+    This function either compresses the entire 'src' content into 'dst' if it's large enough,
+    or fill 'dst' buffer completely with as much data as possible from 'src'.
+        *srcSizePtr : will be modified to indicate how many bytes where read from 'src' to fill 'dst'.
+                      New value is necessarily <= old value.
+        return : Nb bytes written into 'dst' (necessarily <= targetDestSize)
+                 or 0 if compression fails
+*/
+LZ4LIB_API int LZ4_compress_destSize (const char* src, char* dst, int* srcSizePtr, int targetDstSize);
+
+
+/*!
+LZ4_decompress_fast() : **unsafe!**
+This function is a bit faster than LZ4_decompress_safe(),
+but doesn't provide any security guarantee.
+    originalSize : is the uncompressed size to regenerate
+                   Destination buffer must be already allocated, and its size must be >= 'originalSize' bytes.
+    return : number of bytes read from source buffer (== compressed size).
+             If the source stream is detected malformed, the function stops decoding and return a negative result.
+    note : This function respects memory boundaries for *properly formed* compressed data.
+           However, it does not provide any protection against malicious input.
+           It also doesn't know 'src' size, and implies it's >= compressed size.
+           Use this function in trusted environment **only**.
+*/
+LZ4LIB_API int LZ4_decompress_fast (const char* src, char* dst, int originalSize);
+
+/*!
+LZ4_decompress_safe_partial() :
+    This function decompress a compressed block of size 'srcSize' at position 'src'
+    into destination buffer 'dst' of size 'dstCapacity'.
+    The function will decompress a minimum of 'targetOutputSize' bytes, and stop after that.
+    However, it's not accurate, and may write more than 'targetOutputSize' (but always <= dstCapacity).
+   @return : the number of bytes decoded in the destination buffer (necessarily <= dstCapacity)
+        Note : this number can also be < targetOutputSize, if compressed block contains less data.
+            Therefore, always control how many bytes were decoded.
+            If source stream is detected malformed, function returns a negative result.
+            This function is protected against malicious data packets.
+*/
+LZ4LIB_API int LZ4_decompress_safe_partial (const char* src, char* dst, int srcSize, int targetOutputSize, int dstCapacity);
+
+
+/*-*********************************************
+*  Streaming Compression Functions
+***********************************************/
+typedef union LZ4_stream_u LZ4_stream_t;  /* incomplete type (defined later) */
+
+/*! LZ4_createStream() and LZ4_freeStream() :
+ *  LZ4_createStream() will allocate and initialize an `LZ4_stream_t` structure.
+ *  LZ4_freeStream() releases its memory.
+ */
+LZ4LIB_API LZ4_stream_t* LZ4_createStream(void);
+LZ4LIB_API int           LZ4_freeStream (LZ4_stream_t* streamPtr);
+
+/*! LZ4_resetStream() :
+ *  An LZ4_stream_t structure can be allocated once and re-used multiple times.
+ *  Use this function to start compressing a new stream.
+ */
+LZ4LIB_API void LZ4_resetStream (LZ4_stream_t* streamPtr);
+
+/*! LZ4_loadDict() :
+ *  Use this function to load a static dictionary into LZ4_stream_t.
+ *  Any previous data will be forgotten, only 'dictionary' will remain in memory.
+ *  Loading a size of 0 is allowed, and is the same as reset.
+ * @return : dictionary size, in bytes (necessarily <= 64 KB)
+ */
+LZ4LIB_API int LZ4_loadDict (LZ4_stream_t* streamPtr, const char* dictionary, int dictSize);
+
+/*! LZ4_compress_fast_continue() :
+ *  Compress 'src' content using data from previously compressed blocks, for better compression ratio.
+ *  'dst' buffer must be already allocated.
+ *  If dstCapacity >= LZ4_compressBound(srcSize), compression is guaranteed to succeed, and runs faster.
+ *
+ *  Important : The previous 64KB of compressed data is assumed to remain present and unmodified in memory!
+ *
+ *  Special 1 : When input is a double-buffer, they can have any size, including < 64 KB.
+ *              Make sure that buffers are separated by at least one byte.
+ *              This way, each block only depends on previous block.
+ *  Special 2 : If input buffer is a ring-buffer, it can have any size, including < 64 KB.
+ *
+ * @return : size of compressed block
+ *           or 0 if there is an error (typically, cannot fit into 'dst').
+ *  After an error, the stream status is invalid, it can only be reset or freed.
+ */
+LZ4LIB_API int LZ4_compress_fast_continue (LZ4_stream_t* streamPtr, const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+/*! LZ4_saveDict() :
+ *  If last 64KB data cannot be guaranteed to remain available at its current memory location,
+ *  save it into a safer place (char* safeBuffer).
+ *  This is schematically equivalent to a memcpy() followed by LZ4_loadDict(),
+ *  but is much faster, because LZ4_saveDict() doesn't need to rebuild tables.
+ * @return : saved dictionary size in bytes (necessarily <= maxDictSize), or 0 if error.
+ */
+LZ4LIB_API int LZ4_saveDict (LZ4_stream_t* streamPtr, char* safeBuffer, int maxDictSize);
+
+
+/*-**********************************************
+*  Streaming Decompression Functions
+*  Bufferless synchronous API
+************************************************/
+typedef union LZ4_streamDecode_u LZ4_streamDecode_t;   /* incomplete type (defined later) */
+
+/*! LZ4_createStreamDecode() and LZ4_freeStreamDecode() :
+ *  creation / destruction of streaming decompression tracking structure.
+ *  A tracking structure can be re-used multiple times sequentially. */
+LZ4LIB_API LZ4_streamDecode_t* LZ4_createStreamDecode(void);
+LZ4LIB_API int                 LZ4_freeStreamDecode (LZ4_streamDecode_t* LZ4_stream);
+
+/*! LZ4_setStreamDecode() :
+ *  An LZ4_streamDecode_t structure can be allocated once and re-used multiple times.
+ *  Use this function to start decompression of a new stream of blocks.
+ *  A dictionary can optionnally be set. Use NULL or size 0 for a reset order.
+ * @return : 1 if OK, 0 if error
+ */
+LZ4LIB_API int LZ4_setStreamDecode (LZ4_streamDecode_t* LZ4_streamDecode, const char* dictionary, int dictSize);
+
+/*! LZ4_decompress_*_continue() :
+ *  These decoding functions allow decompression of consecutive blocks in "streaming" mode.
+ *  A block is an unsplittable entity, it must be presented entirely to a decompression function.
+ *  Decompression functions only accept one block at a time.
+ *  The last 64KB of previously decoded data *must* remain available and unmodified at the memory position where they were decoded.
+ *  If less than 64KB of data has been decoded all the data must be present.
+ *
+ *  Special : if application sets a ring buffer for decompression, it must respect one of the following conditions :
+ *  - Exactly same size as encoding buffer, with same update rule (block boundaries at same positions)
+ *    In which case, the decoding & encoding ring buffer can have any size, including very small ones ( < 64 KB).
+ *  - Larger than encoding buffer, by a minimum of maxBlockSize more bytes.
+ *    maxBlockSize is implementation dependent. It's the maximum size of any single block.
+ *    In which case, encoding and decoding buffers do not need to be synchronized,
+ *    and encoding ring buffer can have any size, including small ones ( < 64 KB).
+ *  - _At least_ 64 KB + 8 bytes + maxBlockSize.
+ *    In which case, encoding and decoding buffers do not need to be synchronized,
+ *    and encoding ring buffer can have any size, including larger than decoding buffer.
+ *  Whenever these conditions are not possible, save the last 64KB of decoded data into a safe buffer,
+ *  and indicate where it is saved using LZ4_setStreamDecode() before decompressing next block.
+*/
+LZ4LIB_API int LZ4_decompress_safe_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* src, char* dst, int srcSize, int dstCapacity);
+LZ4LIB_API int LZ4_decompress_fast_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* src, char* dst, int originalSize);
+
+
+/*! LZ4_decompress_*_usingDict() :
+ *  These decoding functions work the same as
+ *  a combination of LZ4_setStreamDecode() followed by LZ4_decompress_*_continue()
+ *  They are stand-alone, and don't need an LZ4_streamDecode_t structure.
+ */
+LZ4LIB_API int LZ4_decompress_safe_usingDict (const char* src, char* dst, int srcSize, int dstCapcity, const char* dictStart, int dictSize);
+LZ4LIB_API int LZ4_decompress_fast_usingDict (const char* src, char* dst, int originalSize, const char* dictStart, int dictSize);
+
+
+/*^**********************************************
+ * !!!!!!   STATIC LINKING ONLY   !!!!!!
+ ***********************************************/
+
+/*-************************************
+ *  Unstable declarations
+ **************************************
+ * Declarations in this section should be considered unstable.
+ * Use at your own peril, etc., etc.
+ * They may be removed in the future.
+ * Their signatures may change.
+ **************************************/
+
+#ifdef LZ4_STATIC_LINKING_ONLY
+
+/*! LZ4_resetStream_fast() :
+ *  When an LZ4_stream_t is known to be in a internally coherent state,
+ *  it can often be prepared for a new compression with almost no work, only
+ *  sometimes falling back to the full, expensive reset that is always required
+ *  when the stream is in an indeterminate state (i.e., the reset performed by
+ *  LZ4_resetStream()).
+ *
+ *  LZ4_streams are guaranteed to be in a valid state when:
+ *  - returned from LZ4_createStream()
+ *  - reset by LZ4_resetStream()
+ *  - memset(stream, 0, sizeof(LZ4_stream_t))
+ *  - the stream was in a valid state and was reset by LZ4_resetStream_fast()
+ *  - the stream was in a valid state and was then used in any compression call
+ *    that returned success
+ *  - the stream was in an indeterminate state and was used in a compression
+ *    call that fully reset the state (LZ4_compress_fast_extState()) and that
+ *    returned success
+ */
+LZ4LIB_API void LZ4_resetStream_fast (LZ4_stream_t* streamPtr);
+
+/*! LZ4_compress_fast_extState_fastReset() :
+ *  A variant of LZ4_compress_fast_extState().
+ *
+ *  Using this variant avoids an expensive initialization step. It is only safe
+ *  to call if the state buffer is known to be correctly initialized already
+ *  (see above comment on LZ4_resetStream_fast() for a definition of "correctly
+ *  initialized"). From a high level, the difference is that this function
+ *  initializes the provided state with a call to LZ4_resetStream_fast() while
+ *  LZ4_compress_fast_extState() starts with a call to LZ4_resetStream().
+ */
+LZ4LIB_API int LZ4_compress_fast_extState_fastReset (void* state, const char* src, char* dst, int srcSize, int dstCapacity, int acceleration);
+
+/*! LZ4_attach_dictionary() :
+ *  This is an experimental API that allows for the efficient use of a
+ *  static dictionary many times.
+ *
+ *  Rather than re-loading the dictionary buffer into a working context before
+ *  each compression, or copying a pre-loaded dictionary's LZ4_stream_t into a
+ *  working LZ4_stream_t, this function introduces a no-copy setup mechanism,
+ *  in which the working stream references the dictionary stream in-place.
+ *
+ *  Several assumptions are made about the state of the dictionary stream.
+ *  Currently, only streams which have been prepared by LZ4_loadDict() should
+ *  be expected to work.
+ *
+ *  Alternatively, the provided dictionary stream pointer may be NULL, in which
+ *  case any existing dictionary stream is unset.
+ *
+ *  If a dictionary is provided, it replaces any pre-existing stream history.
+ *  The dictionary contents are the only history that can be referenced and
+ *  logically immediately precede the data compressed in the first subsequent
+ *  compression call.
+ *
+ *  The dictionary will only remain attached to the working stream through the
+ *  first compression call, at the end of which it is cleared. The dictionary
+ *  stream (and source buffer) must remain in-place / accessible / unchanged
+ *  through the completion of the first compression call on the stream.
+ */
+LZ4LIB_API void LZ4_attach_dictionary(LZ4_stream_t *working_stream, const LZ4_stream_t *dictionary_stream);
+
+#endif
+
+/*-************************************
+ *  Private definitions
+ **************************************
+ * Do not use these definitions.
+ * They are exposed to allow static allocation of `LZ4_stream_t` and `LZ4_streamDecode_t`.
+ * Using these definitions will expose code to API and/or ABI break in future versions of the library.
+ **************************************/
+#define LZ4_HASHLOG   (LZ4_MEMORY_USAGE-2)
+#define LZ4_HASHTABLESIZE (1 << LZ4_MEMORY_USAGE)
+#define LZ4_HASH_SIZE_U32 (1 << LZ4_HASHLOG)       /* required as macro for static allocation */
+
+#if defined(__cplusplus) || (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */)
+#include <stdint.h>
+
+typedef struct LZ4_stream_t_internal LZ4_stream_t_internal;
+struct LZ4_stream_t_internal {
+    uint32_t hashTable[LZ4_HASH_SIZE_U32];
+    uint32_t currentOffset;
+    uint16_t initCheck;
+    uint16_t tableType;
+    const uint8_t* dictionary;
+    const LZ4_stream_t_internal* dictCtx;
+    uint32_t dictSize;
+};
+
+typedef struct {
+    const uint8_t* externalDict;
+    size_t extDictSize;
+    const uint8_t* prefixEnd;
+    size_t prefixSize;
+} LZ4_streamDecode_t_internal;
+
+#else
+
+typedef struct LZ4_stream_t_internal LZ4_stream_t_internal;
+struct LZ4_stream_t_internal {
+    unsigned int hashTable[LZ4_HASH_SIZE_U32];
+    unsigned int currentOffset;
+    unsigned short initCheck;
+    unsigned short tableType;
+    const unsigned char* dictionary;
+    const LZ4_stream_t_internal* dictCtx;
+    unsigned int dictSize;
+};
+
+typedef struct {
+    const unsigned char* externalDict;
+    size_t extDictSize;
+    const unsigned char* prefixEnd;
+    size_t prefixSize;
+} LZ4_streamDecode_t_internal;
+
+#endif
+
+/*!
+ * LZ4_stream_t :
+ * information structure to track an LZ4 stream.
+ * init this structure before first use.
+ * note : only use in association with static linking !
+ *        this definition is not API/ABI safe,
+ *        it may change in a future version !
+ */
+#define LZ4_STREAMSIZE_U64 ((1 << (LZ4_MEMORY_USAGE-3)) + 4)
+#define LZ4_STREAMSIZE     (LZ4_STREAMSIZE_U64 * sizeof(unsigned long long))
+union LZ4_stream_u {
+    unsigned long long table[LZ4_STREAMSIZE_U64];
+    LZ4_stream_t_internal internal_donotuse;
+} ;  /* previously typedef'd to LZ4_stream_t */
+
+
+/*!
+ * LZ4_streamDecode_t :
+ * information structure to track an LZ4 stream during decompression.
+ * init this structure  using LZ4_setStreamDecode (or memset()) before first use
+ * note : only use in association with static linking !
+ *        this definition is not API/ABI safe,
+ *        and may change in a future version !
+ */
+#define LZ4_STREAMDECODESIZE_U64  4
+#define LZ4_STREAMDECODESIZE     (LZ4_STREAMDECODESIZE_U64 * sizeof(unsigned long long))
+union LZ4_streamDecode_u {
+    unsigned long long table[LZ4_STREAMDECODESIZE_U64];
+    LZ4_streamDecode_t_internal internal_donotuse;
+} ;   /* previously typedef'd to LZ4_streamDecode_t */
+
+
+/*-************************************
+*  Obsolete Functions
+**************************************/
+
+/*! Deprecation warnings
+   Should deprecation warnings be a problem,
+   it is generally possible to disable them,
+   typically with -Wno-deprecated-declarations for gcc
+   or _CRT_SECURE_NO_WARNINGS in Visual.
+   Otherwise, it's also possible to define LZ4_DISABLE_DEPRECATE_WARNINGS */
+#ifdef LZ4_DISABLE_DEPRECATE_WARNINGS
+#  define LZ4_DEPRECATED(message)   /* disable deprecation warnings */
+#else
+#  define LZ4_GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)
+#  if defined (__cplusplus) && (__cplusplus >= 201402) /* C++14 or greater */
+#    define LZ4_DEPRECATED(message) [[deprecated(message)]]
+#  elif (LZ4_GCC_VERSION >= 405) || defined(__clang__)
+#    define LZ4_DEPRECATED(message) __attribute__((deprecated(message)))
+#  elif (LZ4_GCC_VERSION >= 301)
+#    define LZ4_DEPRECATED(message) __attribute__((deprecated))
+#  elif defined(_MSC_VER)
+#    define LZ4_DEPRECATED(message) __declspec(deprecated(message))
+#  else
+#    pragma message("WARNING: You need to implement LZ4_DEPRECATED for this compiler")
+#    define LZ4_DEPRECATED(message)
+#  endif
+#endif /* LZ4_DISABLE_DEPRECATE_WARNINGS */
+
+/* Obsolete compression functions */
+LZ4_DEPRECATED("use LZ4_compress_default() instead") LZ4LIB_API int LZ4_compress               (const char* source, char* dest, int sourceSize);
+LZ4_DEPRECATED("use LZ4_compress_default() instead") LZ4LIB_API int LZ4_compress_limitedOutput (const char* source, char* dest, int sourceSize, int maxOutputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_extState() instead") LZ4LIB_API int LZ4_compress_withState               (void* state, const char* source, char* dest, int inputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_extState() instead") LZ4LIB_API int LZ4_compress_limitedOutput_withState (void* state, const char* source, char* dest, int inputSize, int maxOutputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_continue() instead") LZ4LIB_API int LZ4_compress_continue                (LZ4_stream_t* LZ4_streamPtr, const char* source, char* dest, int inputSize);
+LZ4_DEPRECATED("use LZ4_compress_fast_continue() instead") LZ4LIB_API int LZ4_compress_limitedOutput_continue  (LZ4_stream_t* LZ4_streamPtr, const char* source, char* dest, int inputSize, int maxOutputSize);
+
+/* Obsolete decompression functions */
+LZ4_DEPRECATED("use LZ4_decompress_fast() instead") LZ4LIB_API int LZ4_uncompress (const char* source, char* dest, int outputSize);
+LZ4_DEPRECATED("use LZ4_decompress_safe() instead") LZ4LIB_API int LZ4_uncompress_unknownOutputSize (const char* source, char* dest, int isize, int maxOutputSize);
+
+/* Obsolete streaming functions; degraded functionality; do not use!
+ *
+ * In order to perform streaming compression, these functions depended on data
+ * that is no longer tracked in the state. They have been preserved as well as
+ * possible: using them will still produce a correct output. However, they don't
+ * actually retain any history between compression calls. The compression ratio
+ * achieved will therefore be no better than compressing each chunk
+ * independently.
+ */
+LZ4_DEPRECATED("Use LZ4_createStream() instead") LZ4LIB_API void* LZ4_create (char* inputBuffer);
+LZ4_DEPRECATED("Use LZ4_createStream() instead") LZ4LIB_API int   LZ4_sizeofStreamState(void);
+LZ4_DEPRECATED("Use LZ4_resetStream() instead") LZ4LIB_API  int   LZ4_resetStreamState(void* state, char* inputBuffer);
+LZ4_DEPRECATED("Use LZ4_saveDict() instead") LZ4LIB_API     char* LZ4_slideInputBuffer (void* state);
+
+/* Obsolete streaming decoding functions */
+LZ4_DEPRECATED("use LZ4_decompress_safe_usingDict() instead") LZ4LIB_API int LZ4_decompress_safe_withPrefix64k (const char* src, char* dst, int compressedSize, int maxDstSize);
+LZ4_DEPRECATED("use LZ4_decompress_fast_usingDict() instead") LZ4LIB_API int LZ4_decompress_fast_withPrefix64k (const char* src, char* dst, int originalSize);
+
+#endif /* LZ4_H_2983827168210 */
+
+
+#if defined (__cplusplus)
+}
+#endif
--- a/bdk/libs/fatfs/diskio.h
+++ b/bdk/libs/fatfs/diskio.h
@@ -10,6 +10,7 @@ extern "C" {
 #endif

 #include <utils/types.h>
+#include <fatfs_cfg.h>

 /* Status of Disk Functions */
 typedef BYTE	DSTATUS;
@@ -23,13 +24,6 @@ typedef enum {
 	RES_PARERR		/* 4: Invalid Parameter */
 } DRESULT;

-typedef enum {
-	DRIVE_SD   = 0,
-	DRIVE_RAM  = 1,
-	DRIVE_EMMC = 2,
-	DRIVE_BIS  = 3
-} DDRIVE;
-

 /*---------------------------------------*/
 /* Prototypes for disk control functions */
@@ -59,27 +53,8 @@ DRESULT disk_set_info (BYTE pdrv, BYTE cmd, void *buff);
 #define GET_SECTOR_SIZE		2	/* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
 #define GET_BLOCK_SIZE		3	/* Get erase block size (needed at FF_USE_MKFS == 1) */
 #define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
-
-/* Generic command (Not used by FatFs) */
-#define CTRL_POWER			5	/* Get/Set power status */
-#define CTRL_LOCK			6	/* Lock/Unlock media removal */
-#define CTRL_EJECT			7	/* Eject media */
-#define CTRL_FORMAT			8	/* Create physical format on the media */
-
-/* MMC/SDC specific ioctl command */
-#define MMC_GET_TYPE		10	/* Get card type */
-#define MMC_GET_CSD			11	/* Get CSD */
-#define MMC_GET_CID			12	/* Get CID */
-#define MMC_GET_OCR			13	/* Get OCR */
-#define MMC_GET_SDSTAT		14	/* Get SD status */
-#define ISDIO_READ			55	/* Read data form SD iSDIO register */
-#define ISDIO_WRITE			56	/* Write data to SD iSDIO register */
-#define ISDIO_MRITE			57	/* Masked write data to SD iSDIO register */
-
-/* ATA/CF specific ioctl command */
-#define ATA_GET_REV			20	/* Get F/W revision */
-#define ATA_GET_MODEL		21	/* Get model name */
-#define ATA_GET_SN			22	/* Get serial number */
+#define SET_SECTOR_OFFSET	5	/* Set media logical offset */
+#define SET_WRITE_PROTECT	6	/* Lock/Unlock media removal */

 #ifdef __cplusplus
 }
--- a/bdk/libs/fatfs/ff.c
+++ b/bdk/libs/fatfs/ff.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -38,10 +38,12 @@

 #include "ff.h"			/* Declarations of FatFs API */
 #include "diskio.h"		/* Declarations of device I/O functions */
+#include <storage/mbr_gpt.h>
+#include <utils/util.h>
 #include <gfx_utils.h>

-#define EFSPRINTF(text, ...) print_error(); gfx_printf("%k"text"%k\n", 0xFFFFFF00, 0xFFFFFFFF);
-//#define EFSPRINTF(...)
+// #define EFSPRINTF(text, ...) print_error(); gfx_printf("%k"text"%k\n", 0xFFFFFF00, 0xFFFFFFFF);
+#define EFSPRINTF(...)

 /*--------------------------------------------------------------------------

@@ -472,6 +474,10 @@ static const char* const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS};	/* Pre-define
 #endif
 #endif

+#if FF_SIMPLE_GPT
+static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0x87,0xC0,0x68,0xB6,0xB7,0x26,0x99,0xC7};
+#endif
+

 /*--------------------------------*/
 /* LFN/Directory working buffer   */
@@ -3273,7 +3279,6 @@ static FRESULT find_volume (	/* FR_OK(0): successful, !=0: an error occurred */
 		stat = disk_status(fs->pdrv);
 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
 			if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
-				EFSPRINTF("WPEN1");
 				return FR_WRITE_PROTECTED;
 			}
 			return FR_OK;				/* The filesystem object is valid */
@@ -3284,14 +3289,13 @@ static FRESULT find_volume (	/* FR_OK(0): successful, !=0: an error occurred */
 	/* Following code attempts to mount the volume. (analyze BPB and initialize the filesystem object) */

 	fs->fs_type = 0;					/* Clear the filesystem object */
+	fs->part_type = 0;					/* Clear the Partition object */
 	fs->pdrv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
 	stat = disk_initialize(fs->pdrv);	/* Initialize the physical drive */
 	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
-		EFSPRINTF("MDNR");
 		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
 	}
 	if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
-		EFSPRINTF("WPEN2");
 		return FR_WRITE_PROTECTED;
 	}
 #if FF_MAX_SS != FF_MIN_SS				/* Get sector size (multiple sector size cfg only) */
@@ -3318,6 +3322,33 @@ static FRESULT find_volume (	/* FR_OK(0): successful, !=0: an error occurred */
 		EFSPRINTF("BRNL");
 		return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
 	}
+#if FF_SIMPLE_GPT
+	if (fmt >= 2) {
+		/* If GPT, iterate over all part entries and check MS Basic partitions */
+		gpt_header_t *gpt_header = (gpt_header_t *)fs->win;
+		if (move_window(fs, 1) != FR_OK) return FR_DISK_ERR;
+		if (!mem_cmp(&gpt_header->signature, "EFI PART", 8)) {
+			DWORD cur_entry, ofs, part;
+			part = LD2PT(vol);
+			cur_entry = 0;
+			for(i = 0; i < gpt_header->num_part_ents; i++){
+				if (move_window(fs, gpt_header->part_ent_lba + i * sizeof(gpt_entry_t) / SS(fs))) return FR_DISK_ERR;
+				ofs = i * sizeof(gpt_entry_t) % SS(fs);
+				gpt_entry_t *gpt_entry = (gpt_entry_t *)fs->win + ofs;
+				if (!mem_cmp(gpt_entry->type_guid, GUID_MS_Basic, 16)){
+					cur_entry++;
+					bsect = gpt_entry->lba_start;
+					fmt = bsect ? check_fs(fs, bsect) : 3;
+					if(part == 0 && fmt <= 1) break;
+					if(part != 0 && cur_entry == part) break;
+				}
+			}
+			if(part && part != cur_entry){
+				fmt = 3;
+			}
+		}
+	}
+#endif
 	if (fmt >= 2) {
 		EFSPRINTF("NOFAT");
 		return FR_NO_FILESYSTEM;	/* No FAT volume is found */
@@ -3919,15 +3950,12 @@ FRESULT f_read_fast (
 {
 	FRESULT res;
 	FATFS *fs;
-	UINT csize_bytes;
-	DWORD clst;
-	UINT count = 0;
+	UINT csize_bytes, count;
+	DWORD clst, work_bytes;
 	FSIZE_t work_sector = 0;
 	FSIZE_t sector_base = 0;
 	BYTE *wbuff = (BYTE*)buff;

-	// TODO support sector reading inside a cluster
-
 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
 		EFSPRINTF("FOV");
@@ -3937,9 +3965,15 @@ FRESULT f_read_fast (
 	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
 	FSIZE_t remain = fp->obj.objsize - fp->fptr;
 	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+	if (!btr)
+		goto out;

 	csize_bytes = fs->csize * SS(fs);

+	//!TODO: support sector reading inside a cluster
+	DWORD csect = (UINT)((fp->fptr / SS(fs)) & (fs->csize - 1));	/* Sector offset in the cluster */
+	if (csect) { EFSPRINTF("ICSR"); ABORT(fs, FR_INT_ERR); }
+
 	if (!fp->fptr) {	/* On the top of the file? */
 		clst = fp->obj.sclust;	/* Follow from the origin */
 	} else {
@@ -3952,9 +3986,10 @@ FRESULT f_read_fast (
 	fp->clust = clst;	/* Set working cluster */

 	sector_base = clst2sect(fs, fp->clust);
-	count += fs->csize;
-	btr -= csize_bytes;
-	fp->fptr += csize_bytes;
+	work_bytes = MIN(btr, csize_bytes);
+	count = work_bytes / SS(fs);
+	fp->fptr += work_bytes;
+	btr -= work_bytes;

 	while (btr) {
 		clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
@@ -3965,26 +4000,27 @@ FRESULT f_read_fast (
 		fp->clust = clst;

 		work_sector = clst2sect(fs, fp->clust);
-		if ((work_sector - sector_base) == count) count += fs->csize;
+		work_bytes = MIN(btr, csize_bytes);
+		if ((work_sector - sector_base) == count) count += work_bytes / SS(fs);
 		else {
 			if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
 			wbuff += count * SS(fs);

 			sector_base = work_sector;
-			count = fs->csize;
+			count = work_bytes / SS(fs);
 		}

-		fp->fptr += MIN(btr, csize_bytes);
-		btr -= MIN(btr, csize_bytes);
-
-		// TODO: what about if data is smaller than cluster?
-		// Must read-write back that cluster.
-
-		if (!btr) {	/* Final cluster/sectors read. */
-			if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
-		}
+		fp->fptr += work_bytes;
+		btr -= work_bytes;
 	}

+	if (!btr) {	/* Final cluster/sectors read. */
+		if (work_bytes % SS(fs))
+			count++; /* Read an extra block. Expects buffer being big enough. */
+		if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+	}
+
+out:
 	LEAVE_FF(fs, FR_OK);
 }
 #endif
@@ -4144,15 +4180,12 @@ FRESULT f_write_fast (
 {
 	FRESULT res;
 	FATFS *fs;
-	UINT csize_bytes;
-	DWORD clst;
-	UINT count = 0;
+	UINT csize_bytes, count;
+	DWORD clst, work_bytes;
 	FSIZE_t work_sector = 0;
 	FSIZE_t sector_base = 0;
 	const BYTE *wbuff = (const BYTE*)buff;

-	// TODO support sector writing inside a cluster
-
 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
 		EFSPRINTF("FOV");
@@ -4160,6 +4193,9 @@ FRESULT f_write_fast (
 	}

 	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+	if (!btw)
+		goto out;
+
 	/* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */
 	if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
 		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
@@ -4167,22 +4203,26 @@ FRESULT f_write_fast (

 	csize_bytes = fs->csize * SS(fs);

+	// TODO support sector writing inside a cluster
+	DWORD csect = (UINT)((fp->fptr / SS(fs)) & (fs->csize - 1));	/* Sector offset in the cluster */
+	if (csect) { EFSPRINTF("ICSR"); ABORT(fs, FR_INT_ERR); }
+
 	if (!fp->fptr) {	/* On the top of the file? */
 		clst = fp->obj.sclust;	/* Follow from the origin */
 	} else {
 		if (fp->cltbl) clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
 		else { EFSPRINTF("CLTBL"); ABORT(fs, FR_CLTBL_NO_INIT); }
 	}
-
 	if (clst < 2) { EFSPRINTF("CCHK"); ABORT(fs, FR_INT_ERR); }
 	else if (clst == 0xFFFFFFFF) { EFSPRINTF("DERR"); ABORT(fs, FR_DISK_ERR); }

 	fp->clust = clst;	/* Set working cluster */

 	sector_base = clst2sect(fs, fp->clust);
-	count += fs->csize;
-	btw -= csize_bytes;
-	fp->fptr += csize_bytes;
+	work_bytes = MIN(btw, csize_bytes);
+	count = work_bytes / SS(fs);
+	fp->fptr += work_bytes;
+	btw -= work_bytes;

 	while (btw) {
 		clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
@@ -4193,28 +4233,30 @@ FRESULT f_write_fast (
 		fp->clust = clst;

 		work_sector = clst2sect(fs, fp->clust);
-		if ((work_sector - sector_base) == count) count += fs->csize;
+		work_bytes = MIN(btw, csize_bytes);
+		if ((work_sector - sector_base) == count) count += work_bytes / SS(fs);
 		else {
 			if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
 			wbuff += count * SS(fs);

 			sector_base = work_sector;
-			count = fs->csize;
+			count = work_bytes / SS(fs);
 		}

-		fp->fptr += MIN(btw, csize_bytes);
-		btw -= MIN(btw, csize_bytes);
+		fp->fptr += work_bytes;
+		btw -= work_bytes;
+	}

-		// what about if data is smaller than cluster?
-		// Probably must read-write back that cluster.
-		if (!btw) {	/* Final cluster/sectors write. */
-			if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
-			fp->flag &= (BYTE)~FA_DIRTY;
-		}
+	if (!btw) {	/* Final cluster/sectors write. */
+		if (work_bytes % SS(fs))
+			count++; /* Write an extra block. Cluster is always > storage block. */
+		if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		fp->flag &= (BYTE)~FA_DIRTY;
 	}

 	fp->flag |= FA_MODIFIED;	/* Set file change flag */

+out:
 	LEAVE_FF(fs, FR_OK);
 }
 #endif
@@ -4685,20 +4727,27 @@ FRESULT f_lseek (

 DWORD *f_expand_cltbl (
 	FIL* fp,		/* Pointer to the file object */
-	UINT tblsz,		/* Size of table */
+	UINT tblsz,		/* Size of table (2 DWORDs + 2 DWORDs per fragment) */
 	FSIZE_t ofs		/* File pointer from top of file */
 )
 {
+	/*
+	 * Cluster table structure:
+	 * Size (DWORD)
+	 * Padding (DWORD)
+	 * (Cluster Offset (DWORD) + Sequential clusters (DWORD)) * Fragments
+	 */
 	if (fp->flag & FA_WRITE) f_lseek(fp, ofs);	/* Expand file if write is enabled */
 	if (!fp->cltbl) {	/* Allocate memory for cluster link table */
 		fp->cltbl = (DWORD *)ff_memalloc(tblsz);
+		if (!fp->cltbl) return (void *)0;
 		fp->cltbl[0] = tblsz;
 	}
 	if (f_lseek(fp, CREATE_LINKMAP)) {	/* Create cluster link table */
 		ff_memfree(fp->cltbl);
-		fp->cltbl = NULL;
+		fp->cltbl = (void *)0;
 		EFSPRINTF("CLTBLSZ");
-		return NULL;
+		return (void *)0;
 	}
 	f_lseek(fp, 0);

@@ -5866,7 +5915,7 @@ FRESULT f_mkfs (
 	stat = disk_initialize(pdrv);
 	if (stat & STA_NOINIT) return FR_NOT_READY;
 	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
-	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1;	/* Erase block to align data area */
+	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 131072 || (sz_blk & (sz_blk - 1))) sz_blk = 2048;	/* Erase block to align data area. 1MB minimum */
 #if FF_MAX_SS != FF_MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
 	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
 	if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
@@ -5902,7 +5951,7 @@ FRESULT f_mkfs (
 	} else {
 		/* Create a single-partition in this function */
 		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
-		b_vol = (opt & FM_SFD) ? 0 : 32768;		/* Volume start sector. Align to 16MB */
+		b_vol = (opt & FM_SFD) ? 0 : sz_blk;		/* Volume start sector */
 		if (sz_vol < b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);
 		sz_vol -= b_vol;						/* Volume size */
 	}
@@ -6098,10 +6147,26 @@ FRESULT f_mkfs (
 					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
 				}
 				n_clst = sz_vol / pau;	/* Number of clusters */
-				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
-				sz_rsv = 32;	/* Number of reserved sectors */
-				sz_dir = 0;		/* No static directory */
-				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED);
+				while (1) {
+					/* Do not account for reserved/root cluster on FAT size for better alignment. */
+					sz_fat = (n_clst * 4 + ss - 1) / ss;	/* FAT size [sector]. */
+					sz_rsv = 2048;	/* Number of reserved sectors. Use 1MB for better performance (for flash memory media) */
+					sz_dir = 0;		/* No static directory */
+					if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED);
+					b_fat = b_vol + sz_rsv;						/* FAT base */
+					b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+
+					/* Align data base to erase block boundary (for flash memory media) */
+					n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data;	/* Next nearest erase block from current data base */
+					b_fat += n;		/* FAT32: Move FAT base */
+					/* Make sure FAT base is aligned to reserved size for performance (PRF2SAFE min cluster alignment) */
+					if ((b_fat & (sz_rsv - 1) || (n_fats == 2 && sz_fat & (sz_rsv - 1)))) {
+						n_clst++;	/* FAT size must always be bigger than real free size */
+						continue;
+					}
+					sz_rsv += n;
+					break;
+				}
 			} else {				/* FAT volume */
 				if (pau == 0) {	/* au auto-selection */
 					n = sz_vol / 0x1000;	/* Volume size in unit of 4KS */
@@ -6117,17 +6182,13 @@ FRESULT f_mkfs (
 				sz_fat = (n + ss - 1) / ss;		/* FAT size [sector] */
 				sz_rsv = 1;						/* Number of reserved sectors */
 				sz_dir = (DWORD)n_rootdir * SZDIRE / ss;	/* Rootdir size [sector] */
-			}
-			b_fat = b_vol + sz_rsv;						/* FAT base */
-			b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+				b_fat = b_vol + sz_rsv;						/* FAT base */
+				b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */

-			/* Align data base to erase block boundary (for flash memory media) */
-			n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data;	/* Next nearest erase block from current data base */
-			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
-				sz_rsv += n; b_fat += n;
-			} else {					/* FAT: Expand FAT size */
+				/* Align data base to erase block boundary (for flash memory media) */
+				n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data;	/* Next nearest erase block from current data base */
 				if (n % n_fats) {	/* Adjust fractional error if needed */
-					n--; sz_rsv++; b_fat++;
+					n--; sz_rsv++; b_fat++;	/* FAT: Expand FAT size */
 				}
 				sz_fat += n / n_fats;
 			}
@@ -6169,7 +6230,9 @@ FRESULT f_mkfs (
 #endif
 		/* Create FAT VBR */
 		mem_set(buf, 0, ss);
-		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+		/* Boot jump code (x86), OEM name */
+		if (!(opt & FM_PRF2)) mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "NYX1.8.0", 11);
+		else mem_cpy(buf + BS_JmpBoot, "\xEB\xE9\x90\x00\x00\x00\x00\x00\x00\x00\x00", 11);
 		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
 		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
 		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
@@ -6182,23 +6245,27 @@ FRESULT f_mkfs (
 		}
 		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
 		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
-		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+		st_word(buf + BPB_NumHeads, (opt & FM_PRF2) ? 16 : 255);	/* Number of heads (for int13) */
 		st_dword(buf + BPB_HiddSec, b_vol);				/* Volume offset in the physical drive [sector] */
 		if (fmt == FS_FAT32) {
-			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+			st_dword(buf + BS_VolID32, (opt & FM_PRF2) ? 0 : GET_FATTIME());	/* VSN */
 			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
 			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
 			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
 			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
 			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
 			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
-			mem_cpy(buf + BS_VolLab32, "SWITCH SD  " "FAT32   ", 19);	/* Volume label, FAT signature */
+			/* Volume label, FAT signature */
+			if (!(opt & FM_PRF2)) mem_cpy(buf + BS_VolLab32, FF_MKFS_LABEL "FAT32   ", 19);
+			else mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);
 		} else {
 			st_dword(buf + BS_VolID, GET_FATTIME());	/* VSN */
 			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
 			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
 			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
-			mem_cpy(buf + BS_VolLab, "SWITCH SD  " "FAT     ", 19);	/* Volume label, FAT signature */
+			/* Volume label, FAT signature */
+			if (!(opt & FM_PRF2)) mem_cpy(buf + BS_VolLab, FF_MKFS_LABEL "FAT     ", 19);
+			else mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);
 		}
 		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
 		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Write it to the VBR sector */
@@ -6209,13 +6276,24 @@ FRESULT f_mkfs (
 			mem_set(buf, 0, ss);
 			st_dword(buf + FSI_LeadSig, 0x41615252);
 			st_dword(buf + FSI_StrucSig, 0x61417272);
-			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
-			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+			if (opt & FM_PRF2) {
+				st_dword(buf + FSI_Free_Count, 0xFFFFFFFF);	/* Invalidate free count */
+				st_dword(buf + FSI_Nxt_Free, 0xFFFFFFFF);	/* Invalidate last allocated cluster */
+			} else {
+				st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+				st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+			}
 			st_word(buf + BS_55AA, 0xAA55);
 			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
 			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
 		}

+		/* Clear PRF2SAFE info so PrFILE2 can recreate it and upgrade it if old */
+		if (fmt == FS_FAT32 && opt & FM_PRF2) {
+			mem_set(buf, 0, ss);
+			disk_write(pdrv, buf, b_vol + 3, 1);			/* Write PRF2SAFE info (VBR + 3) */
+		}
+
 		/* Initialize FAT area */
 		mem_set(buf, 0, (UINT)szb_buf);
 		sect = b_fat;		/* FAT start sector */
@@ -6704,6 +6782,7 @@ int f_puts (
 {
 	putbuff pb;

+	if (str == (void *)0) return EOF; /* String is NULL */

 	putc_init(&pb, fp);
 	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
@@ -6730,6 +6809,7 @@ int f_printf (
 	DWORD v;
 	TCHAR c, d, str[32], *p;

+	if (fmt == (void *)0) return EOF; /* String is NULL */

 	putc_init(&pb, fp);

--- a/bdk/libs/fatfs/ff.h
+++ b/bdk/libs/fatfs/ff.h
@@ -95,8 +95,8 @@ typedef DWORD FSIZE_t;
 /* Filesystem object structure (FATFS) */

 typedef struct {
-	BYTE	win[FF_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
 	BYTE	fs_type;		/* Filesystem type (0:not mounted) */
+	BYTE	part_type;		/* Partition type (0:MBR, 1:GPT) */
 	BYTE	pdrv;			/* Associated physical drive */
 	BYTE	n_fats;			/* Number of FATs (1 or 2) */
 	BYTE	wflag;			/* win[] flag (b0:dirty) */
@@ -138,6 +138,7 @@ typedef struct {
 	DWORD	bitbase;		/* Allocation bitmap base sector */
 #endif
 	DWORD	winsect;		/* Current sector appearing in the win[] */
+	BYTE	win[FF_MAX_SS] __attribute__((aligned(8)));	/* Disk access window for Directory, FAT (and file data at tiny cfg). DMA aligned. */
 } FATFS;


@@ -168,9 +169,6 @@ typedef struct {
 /* File object structure (FIL) */

 typedef struct {
-#if !FF_FS_TINY
-	BYTE	buf[FF_MAX_SS];	/* File private data read/write window */
-#endif
 	FFOBJID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
 	BYTE	flag;			/* File status flags */
 	BYTE	err;			/* Abort flag (error code) */
@@ -184,6 +182,9 @@ typedef struct {
 #if FF_USE_FASTSEEK
 	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
 #endif
+#if !FF_FS_TINY
+	BYTE	buf[FF_MAX_SS] __attribute__((aligned(8)));	/* File private data read/write window. DMA aligned. */
+#endif
 } FIL;


@@ -263,8 +264,10 @@ FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a f
 FRESULT f_close (FIL* fp);											/* Close an open file object */
 FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
 FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
+#if FF_FASTFS /* buff needs to be block aligned. Intercluster data access is not supported. */
 FRESULT f_read_fast (FIL* fp, const void* buff, UINT btr);			/* Fast read data from the file */
 FRESULT f_write_fast (FIL* fp, const void* buff, UINT btw);         /* Fast write data to the file */
+#endif
 FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
 FRESULT f_truncate (FIL* fp);										/* Truncate the file */
 FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
@@ -286,7 +289,9 @@ FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get numbe
 FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
 FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
 FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+#if FF_FASTFS
 DWORD  *f_expand_cltbl (FIL* fp, UINT tblsz, FSIZE_t ofs);			/* Expand file and populate cluster table */
+#endif
 FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt);					/* Allocate a contiguous block to the file */
 FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
 FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
@@ -365,6 +370,7 @@ int ff_del_syncobj (FF_SYNC_t sobj);	/* Delete a sync object */
 #define FM_EXFAT	0x04
 #define FM_ANY		0x07
 #define FM_SFD		0x08
+#define FM_PRF2		0x10

 /* Filesystem type (FATFS.fs_type) */
 #define FS_FAT12	1
--- a/nyx/nyx_gui/libs/fatfs/ffsystem.c
+++ b/nyx/nyx_gui/libs/fatfs/ffsystem.c
@@ -1,16 +1,12 @@
 /*------------------------------------------------------------------------*/
 /* Sample Code of OS Dependent Functions for FatFs                        */
-/* (C) ChaN, 2018                                                          */
-/* (C) CTCaer, 2018                                                       */
+/* (C) ChaN, 2018                                                         */
+/* (C) CTCaer, 2018-2024                                                  */
 /*------------------------------------------------------------------------*/

+#include <bdk.h>

 #include <libs/fatfs/ff.h>
-#include "../../config.h"
-#include <mem/heap.h>
-#include <rtc/max77620-rtc.h>
-
-extern nyx_config n_cfg;

 #if FF_USE_LFN == 3	/* Dynamic memory allocation */

@@ -22,7 +18,8 @@ void* ff_memalloc (	/* Returns pointer to the allocated memory block (null if no
 	UINT msize		/* Number of bytes to allocate */
 )
 {
-	return malloc(msize);	/* Allocate a new memory block with POSIX API */
+	// Ensure size is aligned to SDMMC block size.
+	return malloc(ALIGN(msize, SDMMC_DAT_BLOCKSIZE));	/* Allocate a new memory block with POSIX API */
 }


@@ -51,12 +48,7 @@ DWORD get_fattime (
 {
 	rtc_time_t time;

-	max77620_rtc_get_time(&time);
-	if (n_cfg.timeoff)
-	{
-		u32 epoch = (u32)((s32)max77620_rtc_date_to_epoch(&time) + (s32)n_cfg.timeoff);
-		max77620_rtc_epoch_to_date(epoch, &time);
-	}
+	max77620_rtc_get_time_adjusted(&time);

 	return (((DWORD)(time.year - 1980) << 25) | ((DWORD)time.month << 21) | ((DWORD)time.day << 16) |
 		((DWORD)time.hour << 11) | ((DWORD)time.min << 5) | (time.sec >> 1));
--- a/bdk/libs/lv_conf.h
+++ b/bdk/libs/lv_conf.h
@@ -17,7 +17,7 @@
 #ifndef LV_CONF_H
 #define LV_CONF_H

-#include <utils/types.h>
+#include <soc/timer.h>
 #include <memory_map.h>
 /*===================
   Dynamic memory
@@ -116,8 +116,8 @@
 #define LV_INDEV_POINT_MARKER           0                      /*Mark the pressed points  (required: USE_LV_REAL_DRAW = 1)*/
 #define LV_INDEV_DRAG_LIMIT             10                     /*Drag threshold in pixels */
 #define LV_INDEV_DRAG_THROW             20                     /*Drag throw slow-down in [%]. Greater value means faster slow-down */
-#define LV_INDEV_LONG_PRESS_TIME        400                    /*Long press time in milliseconds*/
-#define LV_INDEV_LONG_PRESS_REP_TIME    1000 //Fix keyb        /*Repeated trigger period in long press [ms] */
+#define LV_INDEV_LONG_PRESS_TIME        5000                   /*Long press time in milliseconds*/
+#define LV_INDEV_LONG_PRESS_REP_TIME    1000 //Fix lv_kb       /*Repeated trigger period in long press [ms] */

 /*Color settings*/
 #define LV_COLOR_DEPTH         32                /*Color depth: 1/8/16/32*/
@@ -147,15 +147,19 @@
 #define LV_COMPILER_VLA_SUPPORTED            1  /* 1: Variable length array is supported*/

 /*HAL settings*/
-#define LV_TICK_CUSTOM               1                       /*1: use a custom tick source (removing the need to manually update the tick with `lv_tick_inc`) */
+#define LV_TICK_CUSTOM               1                      /*1: use a custom tick source (removing the need to manually update the tick with `lv_tick_inc`) */
 #if LV_TICK_CUSTOM == 1
-#define LV_TICK_CUSTOM_INCLUDE       <utils/util.h>          /*Header for the sys time function*/
-#define LV_TICK_CUSTOM_SYS_TIME_EXPR (get_tmr_ms())          /*Expression evaluating to current systime in ms*/
+#define LV_TICK_CUSTOM_INCLUDE       <soc/timer.h>          /*Header for the sys time function*/
+#define LV_TICK_CUSTOM_SYS_TIME_EXPR ((u32)get_tmr_ms())         /*Expression evaluating to current systime in ms*/
 #endif     /*LV_TICK_CUSTOM*/


 /*Log settings*/
-#define USE_LV_LOG        0   /*Enable/disable the log module*/
+#ifdef DEBUG_UART_LV_LOG
+#  define USE_LV_LOG        1   /*Enable/disable the log module*/
+#else
+#  define USE_LV_LOG        0   /*Enable/disable the log module*/
+#endif
 #if USE_LV_LOG
 /* How important log should be added:
 * LV_LOG_LEVEL_TRACE       A lot of logs to give detailed information
@@ -292,6 +296,9 @@

 /*Message box (dependencies: lv_rect, lv_btnm, lv_label)*/
 #define USE_LV_MBOX     1
+#if USE_LV_MBOX != 0
+#  define LV_MBOX_CLOSE_ANIM_TIME 200     /*ms*/
+#endif

 /*Text area (dependencies: lv_label, lv_page)*/
 #define USE_LV_TA       1
@@ -339,7 +346,7 @@
 #define USE_LV_KB       0

 /*Check box (dependencies: lv_btn, lv_label)*/
-#define USE_LV_CB       1
+#define USE_LV_CB       0

 /*List (dependencies: lv_page, lv_btn, lv_label, (lv_img optionally for icons ))*/
 #define USE_LV_LIST     1
@@ -363,7 +370,7 @@
 #define USE_LV_SLIDER    1

 /*Switch (dependencies: lv_slider)*/
-#define USE_LV_SW        1
+#define USE_LV_SW        0

 #endif /*LV_CONF_H*/

--- a/bdk/libs/lvgl/lv_core/lv_group.c
+++ b/bdk/libs/lvgl/lv_core/lv_group.c
@@ -546,8 +546,8 @@ static void obj_to_foreground(lv_obj_t * obj)
        /*Move the last_top object to the foreground*/
        lv_obj_t * par = lv_obj_get_parent(last_top);
        /*After list change it will be the new head*/
-        lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top);
-        lv_obj_invalidate(last_top);
+        if (lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top))
+            lv_obj_invalidate(last_top); /*Only invalidate if not top*/
    }
 }

--- a/bdk/libs/lvgl/lv_core/lv_indev.c
+++ b/bdk/libs/lvgl/lv_core/lv_indev.c
@@ -646,8 +646,8 @@ static void indev_proc_press(lv_indev_proc_t * proc)
                /*Move the last_top object to the foreground*/
                lv_obj_t * par = lv_obj_get_parent(last_top);
                /*After list change it will be the new head*/
-                lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top);
-                lv_obj_invalidate(last_top);
+                if (lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top))
+                    lv_obj_invalidate(last_top); /*Only invalidate if not top*/
            }

            /*Send a signal about the press*/
--- a/bdk/libs/lvgl/lv_misc/lv_color.h
+++ b/bdk/libs/lvgl/lv_misc/lv_color.h
@@ -412,17 +412,17 @@ static inline uint8_t lv_color_brightness(lv_color_t color)
 #endif

 #if LV_COLOR_DEPTH == 32 // Concatenate into one 32-bit set. 
-#define LV_COLOR_HEX(c) ((lv_color_t){.full = (c | 0xFF000000)})
+#define LV_COLOR_HEX(c) ((lv_color_t){.full = ((c) | 0xFF000000)})
 #else
-#define LV_COLOR_HEX(c) LV_COLOR_MAKE(((uint32_t)((uint32_t)c >> 16) & 0xFF), \
-                                ((uint32_t)((uint32_t)c >> 8) & 0xFF), \
-                                ((uint32_t) c & 0xFF))
+#define LV_COLOR_HEX(c) LV_COLOR_MAKE(((uint32_t)((uint32_t)(c) >> 16) & 0xFF), \
+                                ((uint32_t)((uint32_t)(c) >> 8) & 0xFF), \
+                                ((uint32_t) (c) & 0xFF))
 #endif

 /*Usage LV_COLOR_HEX3(0x16C) which means LV_COLOR_HEX(0x1166CC)*/
-#define LV_COLOR_HEX3(c) LV_COLOR_MAKE((((c >> 4) & 0xF0) | ((c >> 8) & 0xF)),   \
-                                ((uint32_t)(c & 0xF0)       | ((c & 0xF0) >> 4)), \
-                                ((uint32_t)(c & 0xF)         | ((c & 0xF) << 4)))
+#define LV_COLOR_HEX3(c) LV_COLOR_MAKE(((((c) >> 4) & 0xF0) | (((c) >> 8) & 0xF)),   \
+                                ((uint32_t)((c) & 0xF0)       | (((c) & 0xF0) >> 4)), \
+                                ((uint32_t)((c) & 0xF)         | (((c) & 0xF) << 4)))


 /**
--- a/bdk/libs/lvgl/lv_misc/lv_ll.c
+++ b/bdk/libs/lvgl/lv_misc/lv_ll.c
@@ -215,9 +215,12 @@ void lv_ll_clear(lv_ll_t * ll_p)
 * @param ll_ori_p pointer to the original (old) linked list
 * @param ll_new_p pointer to the new linked list
 * @param node pointer to a node
+ * @return head changed
 */
-void lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node)
+bool lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node)
 {
+    bool changed = ll_new_p->head != node;
+
    lv_ll_rem(ll_ori_p, node);

    /*Set node as head*/
@@ -232,6 +235,8 @@ void lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node)
    if(ll_new_p->tail == NULL) {     /*If there is no tail (first node) set the tail too*/
        ll_new_p->tail = node;
    }
+
+    return changed;
 }

 /**
--- a/bdk/libs/lvgl/lv_misc/lv_ll.h
+++ b/bdk/libs/lvgl/lv_misc/lv_ll.h
@@ -89,8 +89,9 @@ void lv_ll_clear(lv_ll_t * ll_p);
 * @param ll_ori_p pointer to the original (old) linked list
 * @param ll_new_p pointer to the new linked list
 * @param node pointer to a node
+ * @return head changed
 */
-void lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node);
+bool lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node);

 /**
 * Return with head node of the linked list
--- a/bdk/libs/lvgl/lv_misc/lv_log.c
+++ b/bdk/libs/lvgl/lv_misc/lv_log.c
@@ -63,11 +63,11 @@ void lv_log_add(lv_log_level_t level, const char * file, int line, const char *

    if(level >= LV_LOG_LEVEL) {

-#if LV_LOG_PRINTF
+#if LV_LOG_PRINTF && defined(DEBUG_UART_PORT)
        static const char * lvl_prefix[] = {"Trace", "Info", "Warn", "Error"};
        char *log = (char *)malloc(0x1000);
        s_printf(log, "%s: %s \t(%s #%d)\r\n", lvl_prefix[level], dsc,  file, line);
-        uart_send(UART_B, (u8 *)log, strlen(log) + 1);
+        uart_send(DEBUG_UART_PORT, (u8 *)log, strlen(log) + 1);
        //gfx_printf("%s: %s \t(%s #%d)\n", lvl_prefix[level], dsc,  file, line);
 #else
        if(print_cb) print_cb(level, file, line, dsc);
--- a/bdk/libs/lvgl/lv_misc/lv_task.c
+++ b/bdk/libs/lvgl/lv_misc/lv_task.c
@@ -316,7 +316,8 @@ static bool lv_task_exec(lv_task_t * lv_task_p)
        lv_task_p->last_run = lv_tick_get();
        task_deleted = false;
        task_created = false;
-        lv_task_p->task(lv_task_p->param);
+		if (lv_task_p->task)
+			lv_task_p->task(lv_task_p->param);

        /*Delete if it was a one shot lv_task*/
        if(task_deleted == false) {			/*The task might be deleted by itself as well*/
--- a/bdk/libs/lvgl/lv_objx/lv_line.c
+++ b/bdk/libs/lvgl/lv_objx/lv_line.c
@@ -1,3 +1,19 @@
+/*
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
 /**
 * @file lv_line.c
 *
--- a/bdk/libs/lvgl/lv_objx/lv_slider.c
+++ b/bdk/libs/lvgl/lv_objx/lv_slider.c
@@ -1,3 +1,18 @@
+/*
+ * Copyright (c) 2026 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */

 /**
 * @file lv_slider.c
@@ -437,16 +452,17 @@ static lv_res_t lv_slider_signal(lv_obj_t * slider, lv_signal_t sign, void * par
        lv_indev_get_point(param, &p);
        int16_t tmp = 0;
        if(w > h) {
-            lv_coord_t knob_w = h;
-            p.x -= slider->coords.x1 + h / 2;    /*Modify the point to shift with half knob (important on the start and end)*/
-            tmp = (int32_t)((int32_t) p.x * (ext->bar.max_value - ext->bar.min_value + 1)) / (w - knob_w);
-            tmp += ext->bar.min_value;
+			lv_coord_t knob_w = h;
+			lv_coord_t offset = (ext->knob_in == 0) ? w : w - knob_w;
+			p.x -= slider->coords.x1 + ((ext->knob_in == 0) ? 0 : knob_w / 2);
+			tmp = ((int32_t)p.x * (ext->bar.max_value - ext->bar.min_value) + offset / 2) / offset;
        } else {
-            lv_coord_t knob_h = w;
-            p.y -= slider->coords.y1 + w / 2;    /*Modify the point to shift with half knob (important on the start and end)*/
-            tmp = (int32_t)((int32_t) p.y * (ext->bar.max_value - ext->bar.min_value + 1)) / (h - knob_h);
-            tmp = ext->bar.max_value - tmp;     /*Invert the value: smaller value means higher y*/
+			lv_coord_t knob_h = w;
+			lv_coord_t offset = (ext->knob_in == 0) ? h : h - knob_h;
+			p.y -= slider->coords.y1 + ((ext->knob_in == 0) ? 0 : knob_h / 2);
+			tmp = ((int32_t)p.y * (ext->bar.max_value - ext->bar.min_value) + offset / 2) / offset;
        }
+		tmp += ext->bar.min_value;

        if(tmp < ext->bar.min_value) tmp = ext->bar.min_value;
        else if(tmp > ext->bar.max_value) tmp = ext->bar.max_value;
--- a/bdk/libs/lvgl/lv_themes/lv_theme.h
+++ b/bdk/libs/lvgl/lv_themes/lv_theme.h
@@ -82,13 +82,6 @@ typedef struct {
    } label;
 #endif

-#if USE_LV_IMG != 0
-    struct {
-        lv_style_t *light;
-        lv_style_t *dark;
-    } img;
-#endif
-
 #if USE_LV_LINE != 0
    struct {
        lv_style_t *decor;
--- a/bdk/libs/lvgl/lv_themes/lv_theme_hekate.c
+++ b/bdk/libs/lvgl/lv_themes/lv_theme_hekate.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -25,20 +25,28 @@
 *      DEFINES
 *********************/
 #define DEF_RADIUS             4
-#define COLOR_SHADOW_LIGHT     LV_COLOR_HEX(0xAAAAAA)
-#define COLOR_SHADOW_DARK      LV_COLOR_HEX(0x1F1F1F)
-#define COLOR_HOS_TURQUOISE    (lv_color_hsv_to_rgb(_hue, 100, 100)) // 0x00FFC9
-#define COLOR_HOS_TEAL_LIGHTER (lv_color_hsv_to_rgb(_hue, 100,  93)) // 0x00EDBA
-#define COLOR_HOS_TEAL_LIGHT   (lv_color_hsv_to_rgb(_hue, 100,  72)) // 0x00B78F
-#define COLOR_HOS_TEAL         (lv_color_hsv_to_rgb(_hue, 100,  64)) // 0x00A273
+
+#define COLOR_HOS_TURQUOISE    (_hue ? lv_color_hsv_to_rgb(_hue, 100, 100) : lv_color_hsv_to_rgb(53, 8, 90)) // 0x00FFC9
+#define COLOR_HOS_TEAL_LIGHTER (_hue ? lv_color_hsv_to_rgb(_hue, 100,  93) : lv_color_hsv_to_rgb(53, 8, 81)) // 0x00EDBA
+#define COLOR_HOS_TEAL_LIGHT   (_hue ? lv_color_hsv_to_rgb(_hue, 100,  72) : lv_color_hsv_to_rgb(53, 8, 65)) // 0x00B78F
+#define COLOR_HOS_TEAL         (_hue ? lv_color_hsv_to_rgb(_hue, 100,  64) : lv_color_hsv_to_rgb(53, 8, 58)) // 0x00A273
 #define COLOR_HOS_ORANGE       LV_COLOR_HEX(0xFF5500)
-#define COLOR_HOS_BG_DARKER    LV_COLOR_HEX(0x1B1B1B)
-#define COLOR_HOS_BG_DARK      LV_COLOR_HEX(0x222222)
-#define COLOR_HOS_BG           LV_COLOR_HEX(0x2D2D2D)
-#define COLOR_HOS_BG_LIGHT     LV_COLOR_HEX(0x3D3D3D)
-#define COLOR_HOS_LIGHT_BORDER LV_COLOR_HEX(0x4D4D4D)
 #define COLOR_HOS_TXT_WHITE    LV_COLOR_HEX(0xFBFBFB)

+#define COLOR_BG_DARK          LV_COLOR_HEX(theme_bg_color ? (theme_bg_color - 0x0B0B0B) : 0x121212) // 0x222222.
+#define COLOR_BG               LV_COLOR_HEX(theme_bg_color)                                          // 0x2D2D2D.
+#define COLOR_BG_LIGHT         LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x101010) : 0x2D2D2D) // 0x3D3D3D.
+#define COLOR_BG_LIGHTER       LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x191919) : 0x363636) // 0x464646.
+
+#define COLOR_INACTIVE         LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x171717) : 0x343434) // 0x444444.
+#define COLOR_BAR              LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x202020) : 0x3D3D3D) // 0x4D4D4D.
+#define COLOR_PRESS            LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x232323) : 0x404040) // 0x505050.
+#define COLOR_LINE             LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x383838) : 0x555555) // 0x656565.
+
+#define COLOR_SHADOW_LIGHT     LV_COLOR_HEX(0xAAAAAA)
+#define COLOR_SHADOW           LV_COLOR_HEX(theme_bg_color ? theme_bg_color : 0x181818) // 0x2D2D2D.
+#define COLOR_SHADOW_DARK      LV_COLOR_HEX(theme_bg_color ? 0x1F1F1F : 0x0A0A0A)
+
 /**********************
 *      TYPEDEFS
 **********************/
@@ -57,8 +65,9 @@ static lv_style_t def;
 static lv_style_t sb;

 /*Saved input parameters*/
-static uint16_t _hue;
+static uint16_t    _hue;
 static lv_font_t * _font;
+uint32_t theme_bg_color;

 /**********************
 *      MACROS
@@ -80,18 +89,17 @@ static void basic_init(void)
 	//def.image.opa = LV_OPA_COVER;

 	lv_style_copy(&bg, &def);
-	bg.body.main_color = COLOR_HOS_BG;
-	//bg.body.main_color = LV_COLOR_BLACK;
+	bg.body.main_color = COLOR_BG;
 	bg.body.grad_color = bg.body.main_color;
 	bg.body.radius = 0;
 	bg.body.empty = 1;

 	lv_style_copy(&panel, &def);
 	panel.body.radius = DEF_RADIUS;
-	panel.body.main_color = COLOR_HOS_BG;
-	panel.body.grad_color = COLOR_HOS_BG;
+	panel.body.main_color = COLOR_BG;
+	panel.body.grad_color = panel.body.main_color;
 	panel.body.border.width = 1;
-	panel.body.border.color = COLOR_HOS_LIGHT_BORDER;
+	panel.body.border.color = COLOR_BAR;
 	panel.body.border.opa = LV_OPA_COVER;
 	panel.body.shadow.color = COLOR_SHADOW_LIGHT;
 	panel.body.shadow.type = LV_SHADOW_BOTTOM;
@@ -103,7 +111,7 @@ static void basic_init(void)

 	lv_style_copy(&sb, &def);
 	sb.body.main_color = LV_COLOR_BLACK;
-	sb.body.grad_color = LV_COLOR_BLACK;
+	sb.body.grad_color = sb.body.grad_color;
 	sb.body.opa = LV_OPA_40;
 	sb.body.padding.hor = LV_DPI / 25;

@@ -129,7 +137,7 @@ static void btn_init(void)
 	static lv_style_t rel, pr, tgl_rel, tgl_pr, ina;

 	lv_style_copy(&rel, &def);
-	rel.body.main_color = COLOR_HOS_BG_LIGHT;
+	rel.body.main_color = COLOR_BG_LIGHT;
 	rel.body.grad_color = rel.body.main_color;
 	rel.body.radius = 6;
 	rel.body.padding.hor = LV_DPI / 3;
@@ -139,12 +147,12 @@ static void btn_init(void)
 	rel.body.shadow.type = LV_SHADOW_BOTTOM;
 	rel.body.shadow.width = 6;
 	rel.body.border.width = 0;
-	rel.body.border.color = COLOR_HOS_BG_LIGHT;
+	rel.body.border.color = COLOR_BG_LIGHT;
 	rel.body.border.part = LV_BORDER_FULL;
 	//rel.text.color = COLOR_HOS_TXT_WHITE;

 	lv_style_copy(&pr, &rel);
-	pr.body.main_color = LV_COLOR_HEX(0x505050);
+	pr.body.main_color = COLOR_PRESS;
 	pr.body.grad_color = pr.body.main_color;
 	pr.body.shadow.width = 0;
 	pr.body.border.color = COLOR_HOS_TEAL_LIGHTER;
@@ -156,13 +164,13 @@ static void btn_init(void)
 	tgl_rel.body.border.width = 4;

 	lv_style_copy(&tgl_pr, &tgl_rel);
-	tgl_pr.body.main_color = LV_COLOR_HEX(0x505050);
+	tgl_pr.body.main_color = COLOR_PRESS;
 	tgl_pr.body.grad_color = tgl_pr.body.main_color;
 	tgl_pr.text.color = COLOR_HOS_TURQUOISE;
 	tgl_pr.body.shadow.width = 0;

 	lv_style_copy(&ina, &rel);
-	ina.body.main_color = COLOR_HOS_BG_DARK;
+	ina.body.main_color = COLOR_BG_DARK;
 	ina.body.grad_color = ina.body.main_color;
 	//ina.body.shadow.width = 0;
 	ina.text.color = LV_COLOR_HEX(0x888888);
@@ -198,30 +206,12 @@ static void label_init(void)
 #endif
 }

-static void img_init(void)
-{
-#if USE_LV_IMG != 0
-	static lv_style_t img_light, img_dark;
-	lv_style_copy(&img_light, &def);
-	img_light.image.color = LV_COLOR_WHITE;
-	img_light.image.intense = LV_OPA_80;
-
-	lv_style_copy(&img_dark, &def);
-	img_dark.image.color = COLOR_HOS_BG_DARKER;
-	img_dark.image.intense = LV_OPA_80;
-
-
-	theme.img.light = &def;
-	theme.img.dark = &def;
-#endif
-}
-
 static void line_init(void)
 {
 #if USE_LV_LINE != 0
 	static lv_style_t line;
 	lv_style_copy(&line, &def);
-	line.line.color = LV_COLOR_HEX(0x656565);
+	line.line.color = COLOR_LINE;
 	theme.line.decor = &line;
 #endif
 }
@@ -236,7 +226,7 @@ static void led_init(void)
 	led.body.border.width = LV_DPI / 30;
 	led.body.border.opa = LV_OPA_30;
 	led.body.main_color = lv_color_hsv_to_rgb(_hue, 100, 100);
-	led.body.grad_color = lv_color_hsv_to_rgb(_hue, 100, 100);
+	led.body.grad_color = led.body.main_color;
 	led.body.border.color = lv_color_hsv_to_rgb(_hue, 60, 60);
 	led.body.shadow.color = lv_color_hsv_to_rgb(_hue, 100, 100);

@@ -250,7 +240,7 @@ static void bar_init(void)
 	static lv_style_t bar_bg, bar_indic;

 	lv_style_copy(&bar_bg, &def);
-	bar_bg.body.main_color = COLOR_HOS_LIGHT_BORDER;
+	bar_bg.body.main_color = COLOR_BAR;
 	bar_bg.body.grad_color = bar_bg.body.main_color;
 	bar_bg.body.radius = 3;
 	bar_bg.body.border.width = 0;
@@ -399,7 +389,7 @@ static void calendar_init(void)
 	static lv_style_t week_box;
 	lv_style_copy(&week_box, &def);
 	week_box.body.main_color = lv_color_hsv_to_rgb(_hue, 40, 100);
-	week_box.body.grad_color = lv_color_hsv_to_rgb(_hue, 40, 100);
+	week_box.body.grad_color = week_box.body.main_color;
 	week_box.body.padding.ver = LV_DPI / 20;
 	week_box.body.padding.hor = theme.panel->body.padding.hor;
 	week_box.body.border.color = theme.panel->body.border.color;
@@ -410,7 +400,7 @@ static void calendar_init(void)
 	static lv_style_t today_box;
 	lv_style_copy(&today_box, &def);
 	today_box.body.main_color = LV_COLOR_WHITE;
-	today_box.body.grad_color = LV_COLOR_WHITE;
+	today_box.body.grad_color = today_box.body.main_color;
 	today_box.body.padding.ver = LV_DPI / 20;
 	today_box.body.radius = 0;

@@ -536,9 +526,9 @@ static void mbox_init(void)
 	static lv_style_t bg;

 	lv_style_copy(&bg, theme.panel);
-	bg.body.main_color = LV_COLOR_HEX(0x464646);
+	bg.body.main_color = COLOR_BG_LIGHTER;
 	bg.body.grad_color = bg.body.main_color;
-	bg.body.shadow.color = COLOR_HOS_BG;
+	bg.body.shadow.color = COLOR_SHADOW;
 	bg.body.shadow.type = LV_SHADOW_FULL;
 	bg.body.shadow.width = 8;

@@ -614,13 +604,13 @@ static void list_init(void)
 	rel.body.padding.hor = LV_DPI / 8;
 	rel.body.padding.ver = LV_DPI / 6;
 	rel.body.radius = 0;
-	rel.body.border.color = LV_COLOR_HEX(0x444444);
+	rel.body.border.color = COLOR_INACTIVE;
 	rel.body.border.width = 1;
 	rel.body.border.part = LV_BORDER_BOTTOM;

 	lv_style_copy(&pr, &rel);
 	pr.glass = 0;
-	pr.body.main_color = LV_COLOR_HEX(0x505050);
+	pr.body.main_color = COLOR_PRESS;
 	pr.body.grad_color = pr.body.main_color;
 	//pr.body.border.width = 1;
 	pr.body.empty = 0;
@@ -628,18 +618,18 @@ static void list_init(void)
   // pr.text.font = _font;

 	lv_style_copy(&tgl_rel, &pr);
-	tgl_rel.body.main_color = COLOR_HOS_BG_LIGHT;
+	tgl_rel.body.main_color = COLOR_BG_LIGHT;
 	tgl_rel.body.grad_color = tgl_rel.body.main_color;
 	//tgl_rel.text.color = lv_color_hsv_to_rgb(_hue, 5, 95);
 	tgl_rel.text.color = COLOR_HOS_TEAL_LIGHTER;

 	lv_style_copy(&tgl_pr, &tgl_rel);
-	tgl_pr.body.main_color = LV_COLOR_HEX(0x505050);
+	tgl_pr.body.main_color = COLOR_PRESS;
 	tgl_pr.body.grad_color = tgl_pr.body.main_color;
 	tgl_pr.body.border.width = 0;

 	lv_style_copy(&ina, &pr);
-	ina.body.main_color = COLOR_HOS_BG_DARK;
+	ina.body.main_color = COLOR_BG_DARK;
 	ina.body.grad_color = ina.body.main_color;

 	theme.list.sb = &sb;
@@ -667,7 +657,7 @@ static void ddlist_init(void)
 	bg.text.color = COLOR_HOS_TURQUOISE;

 	lv_style_copy(&sel, &bg);
-	sel.body.main_color = COLOR_HOS_BG_LIGHT;
+	sel.body.main_color = COLOR_BG_LIGHT;
 	sel.body.grad_color = sel.body.main_color;

 	theme.ddlist.bg = &bg;
@@ -689,7 +679,7 @@ static void roller_init(void)
 	roller_bg.text.line_space = LV_DPI / 8;
 	roller_bg.text.font = _font;
 	roller_bg.glass = 0;
-	roller_bg.text.color = LV_COLOR_HEX(0x444444);
+	roller_bg.text.color = COLOR_INACTIVE;

 	lv_style_copy(&roller_sel, &roller_bg);
 	roller_sel.text.color = COLOR_HOS_TURQUOISE;
@@ -713,7 +703,7 @@ static void tabview_init(void)
 	indic.body.opa = LV_OPA_0;

 	lv_style_copy(&btn_bg, &def);
-	btn_bg.body.main_color = COLOR_HOS_BG;
+	btn_bg.body.main_color = COLOR_BG;
 	btn_bg.body.grad_color = btn_bg.body.main_color;
 	btn_bg.body.radius = 0;
 	btn_bg.body.empty = 1;
@@ -734,7 +724,7 @@ static void tabview_init(void)
 	rel.text.font = _font;

 	lv_style_copy(&pr, &def);
-	pr.body.main_color = COLOR_HOS_BG_LIGHT;
+	pr.body.main_color = COLOR_BG_LIGHT;
 	pr.body.grad_color = pr.body.main_color;
 	pr.body.border.width = 0;
 	pr.body.empty = 0;
@@ -750,7 +740,7 @@ static void tabview_init(void)
 	tgl_rel.text.color = COLOR_HOS_TURQUOISE;

 	lv_style_copy(&tgl_pr, &def);
-	tgl_pr.body.main_color = COLOR_HOS_BG_LIGHT;
+	tgl_pr.body.main_color = COLOR_BG_LIGHT;
 	tgl_pr.body.grad_color = tgl_pr.body.main_color;
 	tgl_pr.body.border.width = 0;
 	tgl_pr.body.empty = 0;
@@ -797,7 +787,7 @@ static void win_init(void)
 	static lv_style_t header, rel, pr;

 	lv_style_copy(&header, &def);
-	header.body.main_color = COLOR_HOS_BG;
+	header.body.main_color = COLOR_BG;
 	header.body.grad_color = header.body.main_color;
 	header.body.radius = 0;
 	header.body.border.width = 0;
@@ -843,10 +833,11 @@ static void win_init(void)
 * @param font pointer to a font (NULL to use the default)
 * @return pointer to the initialized theme
 */
-lv_theme_t * lv_theme_hekate_init(uint16_t hue, lv_font_t * font)
+lv_theme_t * lv_theme_hekate_init(uint32_t bg_color, uint16_t hue, lv_font_t * font)
 {
 	if(font == NULL) font = LV_FONT_DEFAULT;

+	theme_bg_color = bg_color;
 	_hue = hue;
 	_font = font;

@@ -862,7 +853,6 @@ lv_theme_t * lv_theme_hekate_init(uint16_t hue, lv_font_t * font)
 	cont_init();
 	btn_init();
 	label_init();
-	img_init();
 	line_init();
 	led_init();
 	bar_init();
--- a/bdk/libs/lvgl/lv_themes/lv_theme_hekate.h
+++ b/bdk/libs/lvgl/lv_themes/lv_theme_hekate.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -35,6 +35,17 @@ extern "C" {
 /*********************
 *      DEFINES
 *********************/
+#define COLOR_BG_BASE_MIN      0x0B0B0B
+#define COLOR_BG_BASE_MAX      0xC7C7C7
+
+#define COLOR_HOS_BG_DARKER    LV_COLOR_HEX(0x1B1B1B)
+#define COLOR_HOS_BG_DARK      LV_COLOR_HEX(0x222222)
+#define COLOR_HOS_BG           LV_COLOR_HEX(0x2D2D2D)
+#define COLOR_HOS_BG_RGB       0x2D2D2D
+#define COLOR_HOS_BG_LIGHT     LV_COLOR_HEX(0x3D3D3D)
+#define COLOR_HOS_BG_LIGHTER   LV_COLOR_HEX(0x4D4D4D)
+
+#define COLOR_HOS_TURQUOISE_EX(hue) (hue ? lv_color_hsv_to_rgb(hue, 100, 100) : lv_color_hsv_to_rgb(53, 8, 90)) // 0x00FFC9

 /**********************
 *      TYPEDEFS
@@ -44,13 +55,15 @@ extern "C" {
 * GLOBAL PROTOTYPES
 **********************/

+extern uint32_t theme_bg_color;
+
 /**
 * Initialize the material theme
 * @param hue [0..360] hue value from HSV color space to define the theme's base color
 * @param font pointer to a font (NULL to use the default)
 * @return pointer to the initialized theme
 */
-lv_theme_t * lv_theme_hekate_init(uint16_t hue, lv_font_t *font);
+lv_theme_t * lv_theme_hekate_init(uint32_t bg_color, uint16_t hue, lv_font_t *font);

 /**
 * Get a pointer to the theme
--- a/bdk/mem/emc.h
+++ b/bdk/mem/emc.h
@@ -1,693 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra21_emc.h
- *
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
- * Copyright (c) 2019-2020, CTCaer.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- */
-
-#ifndef _EMC_H_
-#define _EMC_H_
-
-#define EMC_DBG                                   0x8
-#define EMC_CFG                                   0xC
-#define EMC_CONFIG_SAMPLE_DELAY                   0x5f0
-#define EMC_CFG_UPDATE                            0x5f4
-#define EMC_ADR_CFG                               0x10
-#define EMC_REFCTRL                               0x20
-#define EMC_PIN                                   0x24
-#define EMC_TIMING_CONTROL                        0x28
-#define EMC_RC                                    0x2c
-#define EMC_RFC                                   0x30
-#define EMC_RFCPB                                 0x590
-#define EMC_RAS                                   0x34
-#define EMC_RP                                    0x38
-#define EMC_R2W                                   0x3c
-#define EMC_W2R                                   0x40
-#define EMC_R2P                                   0x44
-#define EMC_W2P                                   0x48
-#define EMC_CCDMW                                 0x5c0
-#define EMC_RD_RCD                                0x4c
-#define EMC_WR_RCD                                0x50
-#define EMC_RRD                                   0x54
-#define EMC_REXT                                  0x58
-#define EMC_WDV                                   0x5c
-#define EMC_QUSE                                  0x60
-#define EMC_QRST                                  0x64
-#define EMC_ISSUE_QRST                            0x428
-#define EMC_QSAFE                                 0x68
-#define EMC_RDV                                   0x6c
-#define EMC_REFRESH                               0x70
-#define EMC_BURST_REFRESH_NUM                     0x74
-#define EMC_PDEX2WR                               0x78
-#define EMC_PDEX2RD                               0x7c
-#define EMC_PDEX2CKE                              0x118
-#define EMC_PCHG2PDEN                             0x80
-#define EMC_ACT2PDEN                              0x84
-#define EMC_AR2PDEN                               0x88
-#define EMC_RW2PDEN                               0x8c
-#define EMC_CKE2PDEN                              0x11c
-#define EMC_TXSR                                  0x90
-#define EMC_TCKE                                  0x94
-#define EMC_TFAW                                  0x98
-#define EMC_TRPAB                                 0x9c
-#define EMC_TCLKSTABLE                            0xa0
-#define EMC_TCLKSTOP                              0xa4
-#define EMC_TREFBW                                0xa8
-#define EMC_TPPD                                  0xac
-#define EMC_PDEX2MRR                              0xb4
-#define EMC_ODT_WRITE                             0xb0
-#define EMC_WEXT                                  0xb8
-#define EMC_RFC_SLR                               0xc0
-#define EMC_MRS_WAIT_CNT2                         0xc4
-#define EMC_MRS_WAIT_CNT                          0xc8
-#define EMC_MRS                                   0xcc
-#define EMC_EMRS                                  0xd0
-#define EMC_REF                                   0xd4
-#define EMC_PRE                                   0xd8
-#define EMC_NOP                                   0xdc
-#define EMC_SELF_REF                              0xe0
-#define EMC_DPD                                   0xe4
-#define EMC_MRW                                   0xe8
-#define EMC_MRR                                   0xec
-#define EMC_CMDQ                                  0xf0
-#define EMC_MC2EMCQ                               0xf4
-#define EMC_FBIO_SPARE                            0x100
-#define EMC_FBIO_CFG5                             0x104
-#define EMC_CFG_RSV                               0x120
-#define EMC_ACPD_CONTROL                          0x124
-#define EMC_MPC                                   0x128
-#define EMC_EMRS2                                 0x12c
-#define EMC_EMRS3                                 0x130
-#define EMC_MRW2                                  0x134
-#define EMC_MRW3                                  0x138
-#define EMC_MRW4                                  0x13c
-#define EMC_MRW5                                  0x4a0
-#define EMC_MRW6                                  0x4a4
-#define EMC_MRW7                                  0x4a8
-#define EMC_MRW8                                  0x4ac
-#define EMC_MRW9                                  0x4b0
-#define EMC_MRW10                                 0x4b4
-#define EMC_MRW11                                 0x4b8
-#define EMC_MRW12                                 0x4bc
-#define EMC_MRW13                                 0x4c0
-#define EMC_MRW14                                 0x4c4
-#define EMC_MRW15                                 0x4d0
-#define EMC_CFG_SYNC                              0x4d4
-#define EMC_CLKEN_OVERRIDE                        0x140
-#define EMC_R2R                                   0x144
-#define EMC_W2W                                   0x148
-#define EMC_EINPUT                                0x14c
-#define EMC_EINPUT_DURATION                       0x150
-#define EMC_PUTERM_EXTRA                          0x154
-#define EMC_TCKESR                                0x158
-#define EMC_TPD                                   0x15c
-#define EMC_STAT_CONTROL                          0x160
-#define EMC_STAT_STATUS                           0x164
-#define EMC_STAT_DRAM_CLOCK_LIMIT_LO              0x19c
-#define EMC_STAT_DRAM_CLOCK_LIMIT_HI              0x1a0
-#define EMC_STAT_DRAM_CLOCKS_LO                   0x1a4
-#define EMC_STAT_DRAM_CLOCKS_HI                   0x1a8
-#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO        0x1ac
-#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI        0x1b0
-#define EMC_STAT_DRAM_DEV0_READ_CNT_LO            0x1b4
-#define EMC_STAT_DRAM_DEV0_READ_CNT_HI            0x1b8
-#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO           0x1bc
-#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI           0x1c0
-#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO           0x1c4
-#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI           0x1c8
-#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO          0x1cc
-#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI          0x1d0
-#define EMC_STAT_DRAM_DEV0_REF_CNT_LO             0x1d4
-#define EMC_STAT_DRAM_DEV0_REF_CNT_HI             0x1d8
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c
-#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214
-#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218
-#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO     0x21c
-#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI     0x220
-#define EMC_STAT_DRAM_DEV0_DSR                    0x224
-#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO        0x228
-#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI        0x22c
-#define EMC_STAT_DRAM_DEV1_READ_CNT_LO            0x230
-#define EMC_STAT_DRAM_DEV1_READ_CNT_HI            0x234
-#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO           0x238
-#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI           0x23c
-#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO           0x240
-#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI           0x244
-#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO          0x248
-#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI          0x24c
-#define EMC_STAT_DRAM_DEV1_REF_CNT_LO             0x250
-#define EMC_STAT_DRAM_DEV1_REF_CNT_HI             0x254
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288
-#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290
-#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294
-#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO     0x298
-#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI     0x29c
-#define EMC_STAT_DRAM_DEV1_DSR                    0x2a0
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc
-#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4
-#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8
-#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO       0xccc
-#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI       0xcd0
-#define EMC_STAT_DRAM_IO_DSR                      0xcd4
-#define EMC_AUTO_CAL_CONFIG                       0x2a4
-#define EMC_AUTO_CAL_CONFIG2                      0x458
-#define EMC_AUTO_CAL_CONFIG3                      0x45c
-#define EMC_AUTO_CAL_CONFIG4                      0x5b0
-#define EMC_AUTO_CAL_CONFIG5                      0x5b4
-#define EMC_AUTO_CAL_CONFIG6                      0x5cc
-#define EMC_AUTO_CAL_CONFIG7                      0x574
-#define EMC_AUTO_CAL_CONFIG8                      0x2dc
-#define EMC_AUTO_CAL_VREF_SEL_0                   0x2f8
-#define EMC_AUTO_CAL_VREF_SEL_1                   0x300
-#define EMC_AUTO_CAL_INTERVAL                     0x2a8
-#define EMC_AUTO_CAL_STATUS                       0x2ac
-#define EMC_AUTO_CAL_STATUS2                      0x3d4
-#define EMC_AUTO_CAL_CHANNEL                      0x464
-#define EMC_PMACRO_RX_TERM                        0xc48
-#define EMC_PMACRO_DQ_TX_DRV                      0xc70
-#define EMC_PMACRO_CA_TX_DRV                      0xc74
-#define EMC_PMACRO_CMD_TX_DRV                     0xc4c
-#define EMC_PMACRO_AUTOCAL_CFG_0                  0x700
-#define EMC_PMACRO_AUTOCAL_CFG_1                  0x704
-#define EMC_PMACRO_AUTOCAL_CFG_2                  0x708
-#define EMC_PMACRO_AUTOCAL_CFG_COMMON             0xc78
-#define EMC_PMACRO_ZCTRL                          0xc44
-#define EMC_XM2COMPPADCTRL                        0x30c
-#define EMC_XM2COMPPADCTRL2                       0x578
-#define EMC_XM2COMPPADCTRL3                       0x2f4
-#define EMC_COMP_PAD_SW_CTRL                      0x57c
-#define EMC_REQ_CTRL                              0x2b0
-#define EMC_EMC_STATUS                            0x2b4
-#define  EMC_STATUS_MRR_DIVLD (1 << 20)
-#define EMC_CFG_2                                 0x2b8
-#define EMC_CFG_DIG_DLL                           0x2bc
-#define EMC_CFG_DIG_DLL_PERIOD                    0x2c0
-#define EMC_DIG_DLL_STATUS                        0x2c4
-#define EMC_CFG_DIG_DLL_1                         0x2c8
-#define EMC_RDV_MASK                              0x2cc
-#define EMC_WDV_MASK                              0x2d0
-#define EMC_RDV_EARLY_MASK                        0x2d4
-#define EMC_RDV_EARLY                             0x2d8
-#define EMC_WDV_CHK                               0x4e0
-#define EMC_ZCAL_INTERVAL                         0x2e0
-#define EMC_ZCAL_WAIT_CNT                         0x2e4
-#define EMC_ZCAL_MRW_CMD                          0x2e8
-#define EMC_ZQ_CAL                                0x2ec
-#define EMC_SCRATCH0                              0x324
-#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE       0x3c8
-#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE        0x3cc
-#define EMC_UNSTALL_RW_AFTER_CLKCHANGE            0x3d0
-#define EMC_FDPD_CTRL_CMD_NO_RAMP                 0x4d8
-#define EMC_SEL_DPD_CTRL                          0x3d8
-#define EMC_FDPD_CTRL_DQ                          0x310
-#define EMC_FDPD_CTRL_CMD                         0x314
-#define EMC_PRE_REFRESH_REQ_CNT                   0x3dc
-#define EMC_REFCTRL2                              0x580
-#define EMC_FBIO_CFG7                             0x584
-#define EMC_DATA_BRLSHFT_0                        0x588
-#define EMC_DATA_BRLSHFT_1                        0x58c
-#define EMC_DQS_BRLSHFT_0                         0x594
-#define EMC_DQS_BRLSHFT_1                         0x598
-#define EMC_CMD_BRLSHFT_0                         0x59c
-#define EMC_CMD_BRLSHFT_1                         0x5a0
-#define EMC_CMD_BRLSHFT_2                         0x5a4
-#define EMC_CMD_BRLSHFT_3                         0x5a8
-#define EMC_QUSE_BRLSHFT_0                        0x5ac
-#define EMC_QUSE_BRLSHFT_1                        0x5b8
-#define EMC_QUSE_BRLSHFT_2                        0x5bc
-#define EMC_QUSE_BRLSHFT_3                        0x5c4
-#define EMC_FBIO_CFG8                             0x5c8
-#define EMC_CMD_MAPPING_CMD0_0                    0x380
-#define EMC_CMD_MAPPING_CMD0_1                    0x384
-#define EMC_CMD_MAPPING_CMD0_2                    0x388
-#define EMC_CMD_MAPPING_CMD1_0                    0x38c
-#define EMC_CMD_MAPPING_CMD1_1                    0x390
-#define EMC_CMD_MAPPING_CMD1_2                    0x394
-#define EMC_CMD_MAPPING_CMD2_0                    0x398
-#define EMC_CMD_MAPPING_CMD2_1                    0x39c
-#define EMC_CMD_MAPPING_CMD2_2                    0x3a0
-#define EMC_CMD_MAPPING_CMD3_0                    0x3a4
-#define EMC_CMD_MAPPING_CMD3_1                    0x3a8
-#define EMC_CMD_MAPPING_CMD3_2                    0x3ac
-#define EMC_CMD_MAPPING_BYTE                      0x3b0
-#define EMC_DYN_SELF_REF_CONTROL                  0x3e0
-#define EMC_TXSRDLL                               0x3e4
-#define EMC_CCFIFO_ADDR                           0x3e8
-#define EMC_CCFIFO_DATA                           0x3ec
-#define EMC_CCFIFO_STATUS                         0x3f0
-#define EMC_SWIZZLE_RANK0_BYTE0                   0x404
-#define EMC_SWIZZLE_RANK0_BYTE1                   0x408
-#define EMC_SWIZZLE_RANK0_BYTE2                   0x40c
-#define EMC_SWIZZLE_RANK0_BYTE3                   0x410
-#define EMC_SWIZZLE_RANK1_BYTE0                   0x418
-#define EMC_SWIZZLE_RANK1_BYTE1                   0x41c
-#define EMC_SWIZZLE_RANK1_BYTE2                   0x420
-#define EMC_SWIZZLE_RANK1_BYTE3                   0x424
-#define EMC_TR_TIMING_0                           0x3b4
-#define EMC_TR_CTRL_0                             0x3b8
-#define EMC_TR_CTRL_1                             0x3bc
-#define EMC_TR_DVFS                               0x460
-#define EMC_SWITCH_BACK_CTRL                      0x3c0
-#define EMC_TR_RDV                                0x3c4
-#define EMC_TR_QPOP                               0x3f4
-#define EMC_TR_RDV_MASK                           0x3f8
-#define EMC_TR_QSAFE                              0x3fc
-#define EMC_TR_QRST                               0x400
-#define EMC_IBDLY                                 0x468
-#define EMC_OBDLY                                 0x46c
-#define EMC_TXDSRVTTGEN                           0x480
-#define EMC_WE_DURATION                           0x48c
-#define EMC_WS_DURATION                           0x490
-#define EMC_WEV                                   0x494
-#define EMC_WSV                                   0x498
-#define EMC_CFG_3                                 0x49c
-#define EMC_CFG_PIPE_2                            0x554
-#define EMC_CFG_PIPE_CLK                          0x558
-#define EMC_CFG_PIPE_1                            0x55c
-#define EMC_CFG_PIPE                              0x560
-#define EMC_QPOP                                  0x564
-#define EMC_QUSE_WIDTH                            0x568
-#define EMC_PUTERM_WIDTH                          0x56c
-#define EMC_PROTOBIST_CONFIG_ADR_1                0x5d0
-#define EMC_PROTOBIST_CONFIG_ADR_2                0x5d4
-#define EMC_PROTOBIST_MISC                        0x5d8
-#define EMC_PROTOBIST_WDATA_LOWER                 0x5dc
-#define EMC_PROTOBIST_WDATA_UPPER                 0x5e0
-#define EMC_PROTOBIST_RDATA                       0x5ec
-#define EMC_DLL_CFG_0                             0x5e4
-#define EMC_DLL_CFG_1                             0x5e8
-#define EMC_TRAINING_CMD                          0xe00
-#define EMC_TRAINING_CTRL                         0xe04
-#define EMC_TRAINING_STATUS                       0xe08
-#define EMC_TRAINING_QUSE_CORS_CTRL               0xe0c
-#define EMC_TRAINING_QUSE_FINE_CTRL               0xe10
-#define EMC_TRAINING_QUSE_CTRL_MISC               0xe14
-#define EMC_TRAINING_WRITE_FINE_CTRL              0xe18
-#define EMC_TRAINING_WRITE_CTRL_MISC              0xe1c
-#define EMC_TRAINING_WRITE_VREF_CTRL              0xe20
-#define EMC_TRAINING_READ_FINE_CTRL               0xe24
-#define EMC_TRAINING_READ_CTRL_MISC               0xe28
-#define EMC_TRAINING_READ_VREF_CTRL               0xe2c
-#define EMC_TRAINING_CA_FINE_CTRL                 0xe30
-#define EMC_TRAINING_CA_CTRL_MISC                 0xe34
-#define EMC_TRAINING_CA_CTRL_MISC1                0xe38
-#define EMC_TRAINING_CA_VREF_CTRL                 0xe3c
-#define EMC_TRAINING_CA_TADR_CTRL                 0xe40
-#define EMC_TRAINING_SETTLE                       0xe44
-#define EMC_TRAINING_DEBUG_CTRL                   0xe48
-#define EMC_TRAINING_DEBUG_DQ0                    0xe4c
-#define EMC_TRAINING_DEBUG_DQ1                    0xe50
-#define EMC_TRAINING_DEBUG_DQ2                    0xe54
-#define EMC_TRAINING_DEBUG_DQ3                    0xe58
-#define EMC_TRAINING_MPC                          0xe5c
-#define EMC_TRAINING_PATRAM_CTRL                  0xe60
-#define EMC_TRAINING_PATRAM_DQ                    0xe64
-#define EMC_TRAINING_PATRAM_DMI                   0xe68
-#define EMC_TRAINING_VREF_SETTLE                  0xe6c
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0       0xe70
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1       0xe74
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2       0xe78
-#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3       0xe7c
-#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC        0xe80
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0       0xe84
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1       0xe88
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2       0xe8c
-#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3       0xe90
-#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC        0xe94
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE0           0xe98
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE1           0xe9c
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE2           0xea0
-#define EMC_TRAINING_RW_OFFSET_IB_BYTE3           0xea4
-#define EMC_TRAINING_RW_OFFSET_IB_MISC            0xea8
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE0           0xeac
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE1           0xeb0
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE2           0xeb4
-#define EMC_TRAINING_RW_OFFSET_OB_BYTE3           0xeb8
-#define EMC_TRAINING_RW_OFFSET_OB_MISC            0xebc
-#define EMC_TRAINING_OPT_CA_VREF                  0xec0
-#define EMC_TRAINING_OPT_DQ_OB_VREF               0xec4
-#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0         0xec8
-#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1         0xecc
-#define EMC_TRAINING_QUSE_VREF_CTRL               0xed0
-#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0        0xed4
-#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1        0xed8
-#define EMC_TRAINING_DRAMC_TIMING                 0xedc
-#define EMC_PMACRO_QUSE_DDLL_RANK0_0              0x600
-#define EMC_PMACRO_QUSE_DDLL_RANK0_1              0x604
-#define EMC_PMACRO_QUSE_DDLL_RANK0_2              0x608
-#define EMC_PMACRO_QUSE_DDLL_RANK0_3              0x60c
-#define EMC_PMACRO_QUSE_DDLL_RANK0_4              0x610
-#define EMC_PMACRO_QUSE_DDLL_RANK0_5              0x614
-#define EMC_PMACRO_QUSE_DDLL_RANK1_0              0x620
-#define EMC_PMACRO_QUSE_DDLL_RANK1_1              0x624
-#define EMC_PMACRO_QUSE_DDLL_RANK1_2              0x628
-#define EMC_PMACRO_QUSE_DDLL_RANK1_3              0x62c
-#define EMC_PMACRO_QUSE_DDLL_RANK1_4              0x630
-#define EMC_PMACRO_QUSE_DDLL_RANK1_5              0x634
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0        0x640
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1        0x644
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2        0x648
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3        0x64c
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4        0x650
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5        0x654
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0        0x660
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1        0x664
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2        0x668
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3        0x66c
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4        0x670
-#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5        0x674
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0       0x680
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1       0x684
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2       0x688
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3       0x68c
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4       0x690
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5       0x694
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0       0x6a0
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1       0x6a4
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2       0x6a8
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3       0x6ac
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4       0x6b0
-#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5       0x6b4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0       0x6c0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1       0x6c4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2       0x6c8
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3       0x6cc
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4       0x6d0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5       0x6d4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0       0x6e0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1       0x6e4
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2       0x6e8
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3       0x6ec
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4       0x6f0
-#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5       0x6f4
-#define EMC_PMACRO_TX_PWRD_0                      0x720
-#define EMC_PMACRO_TX_PWRD_1                      0x724
-#define EMC_PMACRO_TX_PWRD_2                      0x728
-#define EMC_PMACRO_TX_PWRD_3                      0x72c
-#define EMC_PMACRO_TX_PWRD_4                      0x730
-#define EMC_PMACRO_TX_PWRD_5                      0x734
-#define EMC_PMACRO_TX_SEL_CLK_SRC_0               0x740
-#define EMC_PMACRO_TX_SEL_CLK_SRC_1               0x744
-#define EMC_PMACRO_TX_SEL_CLK_SRC_3               0x74c
-#define EMC_PMACRO_TX_SEL_CLK_SRC_2               0x748
-#define EMC_PMACRO_TX_SEL_CLK_SRC_4               0x750
-#define EMC_PMACRO_TX_SEL_CLK_SRC_5               0x754
-#define EMC_PMACRO_DDLL_BYPASS                    0x760
-#define EMC_PMACRO_DDLL_PWRD_0                    0x770
-#define EMC_PMACRO_DDLL_PWRD_1                    0x774
-#define EMC_PMACRO_DDLL_PWRD_2                    0x778
-#define EMC_PMACRO_CMD_CTRL_0                     0x780
-#define EMC_PMACRO_CMD_CTRL_1                     0x784
-#define EMC_PMACRO_CMD_CTRL_2                     0x788
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0  0x880
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1  0x884
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2  0x888
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3  0x88c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0  0x890
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1  0x894
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2  0x898
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3  0x89c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0  0x8a0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1  0x8a4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2  0x8a8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3  0x8ac
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0  0x8b0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1  0x8b4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2  0x8b8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3  0x8bc
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0  0x980
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1  0x984
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2  0x988
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3  0x98c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0  0x990
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1  0x994
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2  0x998
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3  0x99c
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0  0x9a0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1  0x9a4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2  0x9a8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3  0x9ac
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0  0x9b0
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1  0x9b4
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2  0x9b8
-#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3  0x9bc
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0  0xa80
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1  0xa84
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2  0xa88
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0  0xa90
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1  0xa94
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2  0xa98
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0  0xaa0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1  0xaa4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2  0xaa8
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0  0xab0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1  0xab4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2  0xab8
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0  0xb80
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1  0xb84
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2  0xb88
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0  0xb90
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1  0xb94
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2  0xb98
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0  0xba0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1  0xba4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2  0xba8
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0  0xbb0
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1  0xbb4
-#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2  0xbb8
-#define EMC_PMACRO_IB_VREF_DQ_0                   0xbe0
-#define EMC_PMACRO_IB_VREF_DQ_1                   0xbe4
-#define EMC_PMACRO_IB_VREF_DQ_2                   0xbe8
-#define EMC_PMACRO_IB_VREF_DQS_0                  0xbf0
-#define EMC_PMACRO_IB_VREF_DQS_1                  0xbf4
-#define EMC_PMACRO_IB_VREF_DQS_2                  0xbf8
-#define EMC_PMACRO_IB_RXRT                        0xcf4
-#define EMC_PMACRO_DDLL_LONG_CMD_0                0xc00
-#define EMC_PMACRO_DDLL_LONG_CMD_1                0xc04
-#define EMC_PMACRO_DDLL_LONG_CMD_2                0xc08
-#define EMC_PMACRO_DDLL_LONG_CMD_3                0xc0c
-#define EMC_PMACRO_DDLL_LONG_CMD_4                0xc10
-#define EMC_PMACRO_DDLL_LONG_CMD_5                0xc14
-#define EMC_PMACRO_DDLL_SHORT_CMD_0               0xc20
-#define EMC_PMACRO_DDLL_SHORT_CMD_1               0xc24
-#define EMC_PMACRO_DDLL_SHORT_CMD_2               0xc28
-#define EMC_PMACRO_CFG_PM_GLOBAL_0                0xc30
-#define EMC_PMACRO_VTTGEN_CTRL_0                  0xc34
-#define EMC_PMACRO_VTTGEN_CTRL_1                  0xc38
-#define EMC_PMACRO_VTTGEN_CTRL_2                  0xcf0
-#define EMC_PMACRO_BG_BIAS_CTRL_0                 0xc3c
-#define EMC_PMACRO_PAD_CFG_CTRL                   0xc40
-#define EMC_PMACRO_CMD_PAD_RX_CTRL                0xc50
-#define EMC_PMACRO_DATA_PAD_RX_CTRL               0xc54
-#define EMC_PMACRO_CMD_RX_TERM_MODE               0xc58
-#define EMC_PMACRO_DATA_RX_TERM_MODE              0xc5c
-#define EMC_PMACRO_CMD_PAD_TX_CTRL                0xc60
-#define EMC_PMACRO_DATA_PAD_TX_CTRL               0xc64
-#define EMC_PMACRO_COMMON_PAD_TX_CTRL             0xc68
-#define EMC_PMACRO_BRICK_MAPPING_0                0xc80
-#define EMC_PMACRO_BRICK_MAPPING_1                0xc84
-#define EMC_PMACRO_BRICK_MAPPING_2                0xc88
-#define EMC_PMACRO_DDLLCAL_CAL                    0xce0
-#define EMC_PMACRO_DDLL_OFFSET                    0xce4
-#define EMC_PMACRO_DDLL_PERIODIC_OFFSET           0xce8
-#define EMC_PMACRO_BRICK_CTRL_RFU1                0x330
-#define EMC_PMACRO_BRICK_CTRL_RFU2                0x334
-#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD            0x318
-#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD           0x31c
-#define EMC_PMACRO_TRAINING_CTRL_0                0xcf8
-#define EMC_PMACRO_TRAINING_CTRL_1                0xcfc
-#define EMC_PMC_SCRATCH1                          0x440
-#define EMC_PMC_SCRATCH2                          0x444
-#define EMC_PMC_SCRATCH3                          0x448
-
-#define EMC_STATUS_UPDATE_TIMEOUT 1000
-
-typedef enum _emc_mr_t
-{
-	MR5_MAN_ID  = 5,
-	MR6_REV_ID1 = 6,
-	MR7_REV_ID2 = 7,
-	MR8_DENSITY = 8,
-} emc_mr_t;
-
-enum
-{
-	EMC_CHAN0 = 0,
-	EMC_CHAN1 = 1
-};
-
-typedef struct _emc_mr_data_t
-{
-	u8 dev0_ch0;
-	u8 dev0_ch1;
-	u8 dev1_ch0;
-	u8 dev1_ch1;
-} emc_mr_data_t;
-
-#endif
--- a/bdk/mem/emc_t210.h
+++ b/bdk/mem/emc_t210.h
--- a/bdk/mem/heap.c
+++ b/bdk/mem/heap.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -19,33 +19,46 @@
 #include "heap.h"
 #include <gfx_utils.h>

-static void _heap_create(heap_t *heap, u32 start)
+#define HEAP_USED_MAGIC 0x50414548 // "HEAP".
+
+heap_t _heap;
+
+static void _heap_create(void *start)
 {
-	heap->start = start;
-	heap->first = NULL;
+	_heap.start = start;
+	_heap.first = NULL;
+	_heap.last  = NULL;
 }

 // Node info is before node address.
-static u32 _heap_alloc(heap_t *heap, u32 size)
+static void *_heap_alloc(u32 size)
 {
 	hnode_t *node, *new_node;

 	// Align to cache line size.
 	size = ALIGN(size, sizeof(hnode_t));

-	if (!heap->first)
+	// First allocation.
+	if (!_heap.first)
 	{
-		node = (hnode_t *)heap->start;
-		node->used = 1;
+		node = (hnode_t *)_heap.start;
+		node->used = HEAP_USED_MAGIC;
 		node->size = size;
 		node->prev = NULL;
 		node->next = NULL;
-		heap->first = node;

-		return (u32)node + sizeof(hnode_t);
+		_heap.first = node;
+		_heap.last = node;
+
+		return (void *)node + sizeof(hnode_t);
 	}

-	node = heap->first;
+#ifdef BDK_MALLOC_NO_DEFRAG
+	// Get the last allocated block.
+	node = _heap.last;
+#else
+	// Get first block and find the first available one.
+	node = _heap.first;
 	while (true)
 	{
 		// Check if there's available unused node.
@@ -53,14 +66,14 @@ static u32 _heap_alloc(heap_t *heap, u32 size)
 		{
 			// Size and offset of the new unused node.
 			u32 new_size = node->size - size;
-			new_node = (hnode_t *)((u32)node + sizeof(hnode_t) + size);
+			new_node = (hnode_t *)((void *)node + sizeof(hnode_t) + size);

 			// If there's aligned unused space from the old node,
 			// create a new one and set the leftover size.
 			if (new_size >= (sizeof(hnode_t) << 2))
 			{
-				new_node->size = new_size - sizeof(hnode_t);
 				new_node->used = 0;
+				new_node->size = new_size - sizeof(hnode_t);
 				new_node->next = node->next;

 				// Check that we are not on first node.
@@ -74,9 +87,9 @@ static u32 _heap_alloc(heap_t *heap, u32 size)
 				size += new_size;

 			node->size = size;
-			node->used = 1;
+			node->used = HEAP_USED_MAGIC;

-			return (u32)node + sizeof(hnode_t);
+			return (void *)node + sizeof(hnode_t);
 		}

 		// No unused node found, try the next one.
@@ -85,68 +98,92 @@ static u32 _heap_alloc(heap_t *heap, u32 size)
 		else
 			break;
 	}
+#endif

 	// No unused node found, create a new one.
-	new_node = (hnode_t *)((u32)node + sizeof(hnode_t) + node->size);
-	new_node->used = 1;
+	new_node = (hnode_t *)((void *)node + sizeof(hnode_t) + node->size);
+	new_node->used = HEAP_USED_MAGIC;
 	new_node->size = size;
 	new_node->prev = node;
 	new_node->next = NULL;
-	node->next = new_node;

-	return (u32)new_node + sizeof(hnode_t);
+	node->next = new_node;
+	_heap.last = new_node;
+
+	return (void *)new_node + sizeof(hnode_t);
 }

-static void _heap_free(heap_t *heap, u32 addr)
+static void _heap_free(void *addr)
 {
 	hnode_t *node = (hnode_t *)(addr - sizeof(hnode_t));
-	node->used = 0;
-	node = heap->first;
-	while (node)
+
+	// Check if heap owns this address.
+	if (addr < _heap.start || node->used != HEAP_USED_MAGIC)
 	{
-		if (!node->used)
-		{
-			if (node->prev && !node->prev->used)
-			{
-				node->prev->size += node->size + sizeof(hnode_t);
-				node->prev->next = node->next;
-
-				if (node->next)
-					node->next->prev = node->prev;
-			}
-		}
-		node = node->next;
+		//! BUGPRINTF("free error: addr %08p, used %08X!\n");
+		return;
 	}
+
+	node->used = 0;
+
+#ifndef BDK_MALLOC_NO_DEFRAG
+	// Merge with previous node if empty.
+	hnode_t *prev = node->prev;
+	if (prev && !prev->used)
+	{
+		prev->size += node->size + sizeof(hnode_t);
+		prev->next  = node->next;
+
+		if (node->next)
+			node->next->prev = prev;
+
+		// Set node to resized one.
+		node = prev;
+	}
+
+	// Merge with next node if empty.
+	hnode_t *next = node->next;
+	if (next && !next->used)
+	{
+		node->size += next->size + sizeof(hnode_t);
+		node->next  = next->next;
+
+		if (next->next)
+			next->next->prev = node;
+	}
+#endif
 }

-heap_t _heap;
-
-void heap_init(u32 base)
+void heap_init(void *base)
 {
-	_heap_create(&_heap, base);
+	_heap_create(base);
 }

-void heap_copy(heap_t *heap)
+void heap_set(heap_t *heap)
 {
 	memcpy(&_heap, heap, sizeof(heap_t));
 }

 void *malloc(u32 size)
 {
-	return (void *)_heap_alloc(&_heap, size);
+	return _heap_alloc(size);
+}
+
+void *zalloc(u32 size)
+{
+	void *buf = (void *)_heap_alloc(size);
+	memset(buf, 0, ALIGN(size, sizeof(hnode_t))); // Clear the aligned size.
+	return buf;
 }

 void *calloc(u32 num, u32 size)
 {
-	void *res = (void *)_heap_alloc(&_heap, num * size);
-	memset(res, 0, ALIGN(num * size, sizeof(hnode_t))); // Clear the aligned size.
-	return res;
+	return zalloc(num * size);
 }

 void free(void *buf)
 {
-	if ((u32)buf >= _heap.start)
-		_heap_free(&_heap, (u32)buf);
+	_heap_free(buf);
 }

 void heap_monitor(heap_monitor_t *mon, bool print_node_stats)
@@ -158,7 +195,10 @@ void heap_monitor(heap_monitor_t *mon, bool print_node_stats)
 	while (true)
 	{
 		if (node->used)
+		{
+			mon->nodes_used++;
 			mon->used += node->size + sizeof(hnode_t);
+		}
 		else
 			mon->total += node->size + sizeof(hnode_t);

@@ -174,4 +214,5 @@ void heap_monitor(heap_monitor_t *mon, bool print_node_stats)
 			break;
 	}
 	mon->total += mon->used;
+	mon->nodes_total = count;
 }
--- a/bdk/mem/heap.h
+++ b/bdk/mem/heap.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -31,20 +31,24 @@ typedef struct _hnode

 typedef struct _heap
 {
-	u32 start;
+	void *start;
 	hnode_t *first;
+	hnode_t *last;
 } heap_t;

 typedef struct
 {
-    u32 total;
-    u32 used;
+	u32 total;
+	u32 used;
+	u32 nodes_total;
+	u32 nodes_used;
 } heap_monitor_t;

-void heap_init(u32 base);
-void heap_copy(heap_t *heap);
+void heap_init(void *base);
+void heap_set(heap_t *heap);
 void *malloc(u32 size);
 void *calloc(u32 num, u32 size);
+void *zalloc(u32 size);
 void free(void *buf);
 void heap_monitor(heap_monitor_t *mon, bool print_node_stats);

--- a/bdk/mem/mc.c
+++ b/bdk/mem/mc.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -15,120 +15,105 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

+#include <memory_map.h>
 #include <mem/mc.h>
+#include <soc/bpmp.h>
+#include <soc/timer.h>
 #include <soc/t210.h>
 #include <soc/clock.h>
-#include <utils/util.h>

-void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)
-{
-	MC(MC_SEC_CARVEOUT_BOM) = bom;
-	MC(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
-	if (lock)
-		MC(MC_SEC_CARVEOUT_REG_CTRL) = 1;
-}
+#define HOS_WPR1_BASE 0x80020000

-void mc_config_carveout()
+void mc_config_carveout_hos()
 {
-	*(vu32 *)0x8005FFFC = 0xC0EDBBCC;
-	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
+	// Enable ACR GSR3 and flush data to ram.
+	*(u32 *)(HOS_WPR1_BASE + SZ_256K - sizeof(u32)) = ACR_GSC3_ENABLE_MAGIC;
+	bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false);
+
+	// Set VPR CYA TRUSTED DEFAULT.
+	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = VPR_OVR0_CYA_TRUST_DEFAULT;
 	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
-	MC(MC_VIDEO_PROTECT_BOM) = 0;
-	MC(MC_VIDEO_PROTECT_SIZE_MB) = 0;
-	MC(MC_VIDEO_PROTECT_REG_CTRL) = 1;

-	// Configure TSEC carveout @ 0x90000000, 1MB.
-	//mc_config_tsec_carveout(0x90000000, 1, false);
-	mc_config_tsec_carveout(0, 0, true);
+	// Disable VPR carveout.
+	MC(MC_VIDEO_PROTECT_BOM)      = 0;
+	MC(MC_VIDEO_PROTECT_SIZE_MB)  = 0;
+	MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_LOCKED;

-	MC(MC_MTS_CARVEOUT_BOM) = 0;
-	MC(MC_MTS_CARVEOUT_SIZE_MB) = 0;
-	MC(MC_MTS_CARVEOUT_ADR_HI) = 0;
-	MC(MC_MTS_CARVEOUT_REG_CTRL) = 1;
+	// Disable TZDRAM carveout.
+	MC(MC_SEC_CARVEOUT_BOM)      = 0;
+	MC(MC_SEC_CARVEOUT_SIZE_MB)  = 0;
+	MC(MC_SEC_CARVEOUT_REG_CTRL) = BIT(0);

-	MC(MC_SECURITY_CARVEOUT1_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
+	// Disable CPU FW carveout.
+	MC(MC_MTS_CARVEOUT_BOM)      = 0;
+	MC(MC_MTS_CARVEOUT_SIZE_MB)  = 0;
+	MC(MC_MTS_CARVEOUT_REG_CTRL) = BIT(0);
+
+	// Disable GEN1 carveout.
 	MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
+	MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_APERTURE_ID(0)    |
+									 SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;

-	MC(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
-	MC(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
-	MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3100000;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
+	// Enable GEN2 carveout as WPR1.
+	MC(MC_SECURITY_CARVEOUT2_BOM)        = HOS_WPR1_BASE;
+	MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = SZ_256K / SZ_128K;
+	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU  | SEC_CARVEOUT_CA2_W_GPU | SEC_CARVEOUT_CA2_R_TSEC;
+	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2;
+	MC(MC_SECURITY_CARVEOUT2_CFG0) = SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_RD_SEC            |
+									 SEC_CARVEOUT_CFG_RD_FALCON_LS      |
+									 SEC_CARVEOUT_CFG_RD_FALCON_HS      |
+									 SEC_CARVEOUT_CFG_WR_FALCON_LS      |
+									 SEC_CARVEOUT_CFG_WR_FALCON_HS      |
+									 SEC_CARVEOUT_CFG_APERTURE_ID(2)    |
+									 SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU   |
+									 SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;

-	MC(MC_SECURITY_CARVEOUT3_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
+	// Prepare GEN3 carveout as WPR2.
 	MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
+	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU  | SEC_CARVEOUT_CA2_W_GPU;
+	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2;
+	MC(MC_SECURITY_CARVEOUT3_CFG0) = SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_RD_SEC            |
+									 SEC_CARVEOUT_CFG_RD_FALCON_LS      |
+									 SEC_CARVEOUT_CFG_RD_FALCON_HS      |
+									 SEC_CARVEOUT_CFG_WR_FALCON_LS      |
+									 SEC_CARVEOUT_CFG_WR_FALCON_HS      |
+									 SEC_CARVEOUT_CFG_APERTURE_ID(3)    |
+									 SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU   |
+									 SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;

-	MC(MC_SECURITY_CARVEOUT4_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
+	// Disable GEN4 carveout.
 	MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
+	MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE         |
+									 SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_WR_NS;

-	MC(MC_SECURITY_CARVEOUT5_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
+	// Disable GEN5 carveout.
 	MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
+	MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE         |
+									 SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_WR_NS;
 }

-void mc_enable_ahb_redirect()
+// SDMMC, TSEC, XUSB and probably more need it to access < DRAM_START.
+void mc_enable_ahb_redirect(u32 offset)
 {
-	// Enable ARC_CLK_OVR_ON.
-	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000;
-	//MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE;
-	MC(MC_IRAM_BOM) = 0x40000000;
-	MC(MC_IRAM_TOM) = 0x4003F000;
+	// Bypass ARC clock gating.
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19);
+	//MC(MC_IRAM_REG_CTRL) &= ~BIT(0);
+	MC(MC_IRAM_BOM) = IRAM_BASE;
+	MC(MC_IRAM_TOM) = DRAM_START - offset; // Default is only IRAM: 0x4003F000.
 }

 void mc_disable_ahb_redirect()
@@ -136,25 +121,34 @@ void mc_disable_ahb_redirect()
 	MC(MC_IRAM_BOM) = 0xFFFFF000;
 	MC(MC_IRAM_TOM) = 0;
 	// Disable IRAM_CFG_WRITE_ACCESS (sticky).
-	//MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1;
-	// Disable ARC_CLK_OVR_ON.
-	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= 0xFFF7FFFF;
+	//MC(MC_IRAM_REG_CTRL) |= BIT(0);
+	// Set ARC clock gating to automatic.
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= ~BIT(19);
+}
+
+bool mc_client_has_access(void *address)
+{
+	// Check if address is in DRAM or if arbitration for IRAM is enabled.
+	if ((u32)address >= DRAM_START)
+		return true; // Access by default.
+	else if ((u32)address >= IRAM_BASE && MC(MC_IRAM_BOM) == IRAM_BASE)
+		return true; // Access by AHB arbitration.
+
+	// No access to address space.
+	return false;
 }

 void mc_enable()
 {
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000;
-	// Enable EMC clock.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF) | 0x2000000;
-	// Enable MC clock.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE) | 1;
-	// Enable EMC DLL clock.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000;
-	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001; //Clear EMC and MC reset.
+	// Reset EMC source to PLLP.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29u);
+
+	// Enable and clear reset for memory clocks.
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
 	usleep(5);

-	//#ifdef CONFIG_ENABLE_AHB_REDIRECT
-	mc_disable_ahb_redirect();
-	//mc_enable_ahb_redirect();
-	//#endif
+	// Enable redirection by default.
+	mc_enable_ahb_redirect(1);
 }
--- a/bdk/mem/mc.h
+++ b/bdk/mem/mc.h
@@ -21,10 +21,10 @@
 #include <mem/mc_t210.h>

 void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock);
-void mc_config_carveout();
-void mc_config_carveout_finalize();
-void mc_enable_ahb_redirect();
+void mc_config_carveout_hos();
+void mc_enable_ahb_redirect(u32 offset);
 void mc_disable_ahb_redirect();
+bool mc_client_has_access(void *address);
 void mc_enable();

 #endif
--- a/bdk/mem/mc_t210.h
+++ b/bdk/mem/mc_t210.h
--- a/bdk/mem/minerva.c
+++ b/bdk/mem/minerva.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -19,129 +19,277 @@

 #include "minerva.h"

-#include <soc/clock.h>
 #include <ianos/ianos.h>
+#include <mem/emc_t210.h>
 #include <soc/clock.h>
 #include <soc/fuse.h>
+#include <soc/hw_init.h>
 #include <soc/t210.h>
-#include <utils/util.h>

-extern volatile nyx_storage_t *nyx_str;
+#define FREQ_NO_TABLE_MAX FREQ_408

-void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
+#define TABLE_FREQ_KHZ_OFFSET        0x40
+#define TABLE_LA_REGS_T210_OFFSET    0x1284
+#define TABLE_LA_REGS_T210B01_OFFSET 0xFA4
+#define LA_SDMMC1_INDEX 6

-u32 minerva_init()
+static bool no_table = false;
+static mtc_config_t *mtc_cfg = NULL;
+void (*mtc_call)(mtc_config_t *mtc_cfg, void *);
+
+int minerva_init(minerva_str_t *mtc_str)
 {
-	u32 curr_ram_idx = 0;
+	mtc_call = NULL;
+	mtc_cfg  = (mtc_config_t *)&mtc_str->mtc_cfg;
+	no_table = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01;

-	minerva_cfg = NULL;
-	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
-
-#ifdef NYX
+#ifdef BDK_MINERVA_CFG_FROM_RAM
 	// Set table to nyx storage.
-	mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
+	mtc_cfg->mtc_table = (emc_table_t *)mtc_str->mtc_table;

 	// Check if Minerva is already initialized.
 	if (mtc_cfg->init_done == MTC_INIT_MAGIC)
 	{
-		mtc_cfg->train_mode = OP_PERIODIC_TRAIN; // Retrain if needed.
-		u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
-		minerva_cfg = (void *)ep_addr;
+		// Load library and do a periodic training if needed.
+		mtc_cfg->train_mode = OP_PERIODIC_TRAIN;
+		mtc_call = (void *)ianos_static_module("bootloader/sys/libsys_minerva.bso", (void *)mtc_cfg);

-		return 0;
+		return !mtc_call ? 1 : 0;
 	}
 	else
 	{
 		mtc_config_t mtc_tmp;

-		mtc_tmp.mtc_table = mtc_cfg->mtc_table;
-		mtc_tmp.sdram_id = (fuse_read_odm(4) >> 3) & 0x1F;
-		mtc_tmp.init_done = MTC_NEW_MAGIC;
+		// Initialize table.
+		mtc_tmp.mtc_table  = mtc_cfg->mtc_table;
+		mtc_tmp.sdram_id   = fuse_read_dramid(false);
+		mtc_tmp.init_done  = !no_table ? MTC_NEW_MAGIC : MTC_IRB_MAGIC;

-		u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)&mtc_tmp);
+		// Load library and get table.
+		u32 ep_addr = ianos_static_module("bootloader/sys/libsys_minerva.bso", (void *)&mtc_tmp);

-		// Ensure that Minerva is new.
+		// Ensure that Minerva is initialized.
 		if (mtc_tmp.init_done == MTC_INIT_MAGIC)
-			minerva_cfg = (void *)ep_addr;
+			mtc_call = (void *)ep_addr;
 		else
 			mtc_cfg->init_done = 0;

 		// Copy Minerva context to Nyx storage.
-		if (minerva_cfg)
+		if (mtc_call)
 			memcpy(mtc_cfg, (void *)&mtc_tmp, sizeof(mtc_config_t));
 	}
 #else
+	// Fully initialize Minerva.
 	memset(mtc_cfg, 0, sizeof(mtc_config_t));

-	// Set table to nyx storage.
-	mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
+	// Initialize mtc table.
+	mtc_cfg->mtc_table  = mtc_str->mtc_table;
+	mtc_cfg->sdram_id   = fuse_read_dramid(false);
+	mtc_cfg->init_done  = !no_table ? MTC_NEW_MAGIC : MTC_IRB_MAGIC;

-	mtc_cfg->sdram_id = (fuse_read_odm(4) >> 3) & 0x1F;
-	mtc_cfg->init_done = MTC_NEW_MAGIC; // Initialize mtc table.
+	u32 ep_addr = ianos_static_module("bootloader/sys/libsys_minerva.bso", (void *)mtc_cfg);

-	u32 ep_addr = ianos_loader("bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
-
-	// Ensure that Minerva is new.
+	// Ensure that Minerva is initialized.
 	if (mtc_cfg->init_done == MTC_INIT_MAGIC)
-		minerva_cfg = (void *)ep_addr;
+		mtc_call = (void *)ep_addr;
 	else
 		mtc_cfg->init_done = 0;
 #endif

-	if (!minerva_cfg)
+	if (!mtc_call)
 		return 1;

-	// Get current frequency
-	for (curr_ram_idx = 0; curr_ram_idx < 10; curr_ram_idx++)
+	if (no_table)
 	{
-		if (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) == mtc_cfg->mtc_table[curr_ram_idx].clk_src_emc)
-			break;
+		mtc_cfg->train_mode = OP_SWITCH;
+		mtc_cfg->rate_from = FREQ_204;
+		mtc_cfg->rate_to = FREQ_NO_TABLE_MAX;
+		mtc_call(mtc_cfg, NULL);
+
+		return 0;
 	}

-	mtc_cfg->rate_from = mtc_cfg->mtc_table[curr_ram_idx].rate_khz;
-	mtc_cfg->rate_to = 204000;
+	// Train frequencies.
 	mtc_cfg->train_mode = OP_TRAIN;
-	minerva_cfg(mtc_cfg, NULL);
-	mtc_cfg->rate_to = 800000;
-	minerva_cfg(mtc_cfg, NULL);
-	mtc_cfg->rate_to = 1600000;
-	minerva_cfg(mtc_cfg, NULL);
+	mtc_cfg->rate_from = FREQ_204;
+	mtc_cfg->rate_to = FREQ_204;
+	mtc_call(mtc_cfg, NULL);
+	mtc_cfg->rate_to = FREQ_800;
+	mtc_call(mtc_cfg, NULL);
+	mtc_cfg->rate_to = FREQ_1600;
+	mtc_call(mtc_cfg, NULL);

 	// FSP WAR.
 	mtc_cfg->train_mode = OP_SWITCH;
-	mtc_cfg->rate_to = 800000;
-	minerva_cfg(mtc_cfg, NULL);
+	mtc_cfg->rate_to = FREQ_800;
+	mtc_call(mtc_cfg, NULL);

 	// Switch to max.
-	mtc_cfg->rate_to = 1600000;
-	minerva_cfg(mtc_cfg, NULL);
+	mtc_cfg->rate_to = FREQ_1600;
+	mtc_call(mtc_cfg, NULL);

 	return 0;
 }

 void minerva_change_freq(minerva_freq_t freq)
 {
-	if (!minerva_cfg)
+	if (!mtc_call)
 		return;

-	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
+	// Clamp max allowed frequency when no table exists.
+	if (no_table && freq > FREQ_NO_TABLE_MAX)
+		freq = FREQ_NO_TABLE_MAX;
+
+	// Check if requested frequency is different. Do not allow otherwise because it will hang.
 	if (mtc_cfg->rate_from != freq)
 	{
-		mtc_cfg->rate_to = freq;
 		mtc_cfg->train_mode = OP_SWITCH;
-		minerva_cfg(mtc_cfg, NULL);
+		mtc_cfg->rate_to = freq;
+		mtc_call(mtc_cfg, NULL);
 	}
 }

+void minerva_deinit()
+{
+	if (!mtc_cfg)
+		return;
+
+	minerva_change_freq(FREQ_204);
+	mtc_cfg->init_done = 0;
+}
+
+void minerva_sdmmc_la_program(void *table, bool t210b01)
+{
+	u32 freq = *(u32 *)(table + TABLE_FREQ_KHZ_OFFSET);
+	u32 *la_scale_regs = (u32 *)(table + (t210b01 ? TABLE_LA_REGS_T210B01_OFFSET : TABLE_LA_REGS_T210_OFFSET));
+
+	// Adjust SDMMC1 latency allowance.
+	switch (freq)
+	{
+	case 204000:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 50;
+		break;
+	case 408000:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 25;
+		break;
+	default:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 20;
+		break;
+	}
+}
+
+void minerva_prep_boot_hos()
+{
+	if (!mtc_call)
+		return;
+
+	// Restore boot frequency for no table mode.
+	if (no_table)
+	{
+		minerva_deinit();
+
+		return;
+	}
+
+	// Check if there's RAM OC. If not exit.
+	if (mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600)
+		return;
+
+	// FSP WAR.
+	minerva_change_freq(FREQ_204);
+	// Scale down to 800 MHz boot freq.
+	minerva_change_freq(FREQ_800);
+}
+
+void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom, bool prg_sdmmc_la)
+{
+	if (!mtc_call || no_table)
+		return;
+
+	// Program SDMMC LA regs.
+	if (prg_sdmmc_la)
+		for (u32 i = 0; i < mtc_cfg->table_entries; i++)
+			minerva_sdmmc_la_program(&mtc_cfg->mtc_table[i], false);
+
+	// Add OC frequency.
+	if (oc_freq && mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600)
+	{
+		memcpy(&mtc_cfg->mtc_table[mtc_cfg->table_entries],
+			   &mtc_cfg->mtc_table[mtc_cfg->table_entries - 1],
+			   sizeof(emc_table_t));
+
+		mtc_cfg->mtc_table[mtc_cfg->table_entries].opt_custom = opt_custom;
+		mtc_cfg->mtc_table[mtc_cfg->table_entries].rate_khz   = oc_freq;
+		mtc_cfg->table_entries++;
+	}
+
+	// Trim table.
+	int entries = 0;
+	for (u32 i = 0; i < mtc_cfg->table_entries; i++)
+	{
+		// Copy frequencies from 204/408/800 MHz and 1333+ MHz.
+		int rate = mtc_cfg->mtc_table[i].rate_khz;
+		if (rate == FREQ_204 ||
+			rate == FREQ_408 ||
+			rate == FREQ_800 ||
+			rate >= FREQ_1333)
+		{
+			memcpy(&mtc_cfg->mtc_table[entries], &mtc_cfg->mtc_table[i], sizeof(emc_table_t));
+			entries++;
+		}
+	}
+	mtc_cfg->table_entries = entries;
+
+	// Set init frequency.
+	minerva_change_freq(FREQ_204);
+
+	// Train the rest of the frequencies.
+	mtc_cfg->train_mode = OP_TRAIN;
+	for (u32 i = 0; i < mtc_cfg->table_entries; i++)
+	{
+		// Skip already trained frequencies and OC freq (Arachne handles it).
+		if (mtc_cfg->mtc_table[i].trained || mtc_cfg->rate_to == oc_freq)
+			continue;
+
+		// Train frequency.
+		mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz;
+		mtc_call(mtc_cfg, NULL);
+	}
+
+	// Do FSP WAR and scale to 800 MHz as boot freq.
+	bool fsp_opwr_disabled = !(EMC(EMC_MRW3) & 0xC0);
+	if (fsp_opwr_disabled)
+		minerva_change_freq(FREQ_1333);
+	minerva_change_freq(FREQ_800);
+
+	// Do not let other mtc ops.
+	mtc_cfg->init_done = 0;
+}
+
 void minerva_periodic_training()
 {
-	if (!minerva_cfg)
+	if (!mtc_call)
 		return;

-	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
-	if (mtc_cfg->rate_from == FREQ_1600)
+	if (mtc_cfg->rate_from >= FREQ_1066)
 	{
 		mtc_cfg->train_mode = OP_PERIODIC_TRAIN;
-		minerva_cfg(mtc_cfg, NULL);
+		mtc_call(mtc_cfg, NULL);
 	}
-}
+}
+
+emc_table_t *minerva_get_mtc_table()
+{
+	if (!mtc_call || no_table)
+		return NULL;
+
+	return mtc_cfg->mtc_table;
+}
+
+int minerva_get_mtc_table_entries()
+{
+	if (!mtc_call || no_table)
+		return 0;
+
+	return mtc_cfg->table_entries;
+}
--- a/bdk/mem/minerva.h
+++ b/bdk/mem/minerva.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -22,13 +22,14 @@

 #define MTC_INIT_MAGIC 0x3043544D
 #define MTC_NEW_MAGIC  0x5243544D
+#define MTC_IRB_MAGIC  0x4943544D

 #define EMC_PERIODIC_TRAIN_MS 250

 typedef struct
 {
-	s32 rate_to;
-	s32 rate_from;
+	u32 rate_to;
+	u32 rate_from;
 	emc_table_t *mtc_table;
 	u32 table_entries;
 	emc_table_t *current_emc_table;
@@ -38,9 +39,15 @@ typedef struct
 	bool emc_2X_clk_src_is_pllmb;
 	bool fsp_for_src_freq;
 	bool train_ram_patterns;
-	bool init_done;
+	u32  init_done;
 } mtc_config_t;

+typedef struct
+{
+	mtc_config_t mtc_cfg;
+	emc_table_t mtc_table[11]; // 10 + 1.
+} minerva_str_t;
+
 enum train_mode_t
 {
 	OP_SWITCH         = 0,
@@ -53,13 +60,26 @@ enum train_mode_t
 typedef enum
 {
 	FREQ_204  = 204000,
+	FREQ_408  = 408000,
+	FREQ_666  = 665600,
 	FREQ_800  = 800000,
-	FREQ_1600 = 1600000
+	FREQ_1066 = 1065600,
+	FREQ_1333 = 1331200,
+	FREQ_1600 = 1600000,
+
+	FREQ_MIN  = FREQ_204,
+	FREQ_MAX  = FREQ_1600
 } minerva_freq_t;

 extern void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
-u32  minerva_init();
+int  minerva_init(minerva_str_t *mtc_str);
+void minerva_deinit();
 void minerva_change_freq(minerva_freq_t freq);
+void minerva_sdmmc_la_program(void *table, bool t210b01);
+void minerva_prep_boot_hos();
+void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom, bool prg_sdmmc_la);
 void minerva_periodic_training();
+emc_table_t *minerva_get_mtc_table();
+int minerva_get_mtc_table_entries();

 #endif
--- a/bdk/mem/mtc_table.h
+++ b/bdk/mem/mtc_table.h
@@ -481,7 +481,8 @@ typedef struct
 	u32 rate_khz;
 	u32 min_volt;
 	u32 gpu_min_volt;
-	char clock_src[32];
+	char clock_src[28];
+	u32 opt_custom;
 	u32 clk_src_emc;
 	u32 needs_training;
 	u32 training_pattern;
--- a/bdk/mem/sdram.c
+++ b/bdk/mem/sdram.c
--- a/bdk/mem/sdram.h
+++ b/bdk/mem/sdram.h
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -17,12 +18,122 @@
 #ifndef _SDRAM_H_
 #define _SDRAM_H_

-#include <mem/emc.h>
-#include <mem/sdram_param_t210.h>
+#include <mem/emc_t210.h>
+
+/*
+ * Tegra X1/X1+ EMC/DRAM Bandwidth Chart:
+ *
+ * Note: Max BWbits = Hz x ddr x bus width x channels = Hz x 2 x 32 x 2.
+ *       Max BWbits = Hz x ddr x bus width x channels = Hz x 2 x 64 x 1.
+ *       Configurations supported: 1x32, 2x32, 1x64.
+ *       x64 ram modules can be used by combining the 2 32-bit channels into one.
+ *
+ *  204.0 MHz:  3.04 <-- Tegra X1/X1+ Init/SC7 Frequency
+ *  408.0 MHz:  6.08
+ *  665.6 MHz:  9.92
+ *  800.0 MHz: 11.92 <-- Tegra X1/X1+ Nvidia OS Boot Frequency
+ * 1065.6 MHz: 15.89
+ * 1331.2 MHz: 19.84
+ * 1600.0 MHz: 23.84
+ * 1862.4 MHz: 27.75 <-- Tegra X1  Official Max Frequency
+ * 2131.2 MHz: 31.76 <-- Tegra X1+ Official Max Frequency. Not all regs have support for > 2046 MHz.
+ */
+
+enum sdram_ids_erista
+{
+	// LPDDR4 3200Mbps.
+	LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH        = 0, // Die-B. (2y-01).
+	LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE       = 1, // Die-M. (2y-01).
+	LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC = 2, // Die-C. (2y-01).
+
+	LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH        = 4, // Die-C. (2y-01).
+
+	/*
+	 * Custom hekate/L4T supported 8GB. 7 dram id can be easily applied in fuses.
+	 *
+	 * 4GB modules:
+	 * Samsung K4FBE3D4HM-MGCH/CJ/CL. MG/TF/GF/TH/GH: Package + Temperature.
+	 * Hynix   H9HCNNNCPUMLXR-NME/NEE/NEI. E/I: Temperature.
+	 * Hynix   H54G56BYYVX046/QX046/PX046. V/Q/P: Package + Temperature.
+	 */
+	LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX        = 7, // XX: CH/CJ/CL.
+};
+
+enum sdram_ids_mariko
+{
+	/*
+	 * Nintendo Switch LPDRR4X generations:
+	 * - 1x   nm are 1st-gen
+	 * - 1y   nm are 2nd-gen
+	 * - 1z/a nm are 3rd-gen
+	 */
+
+	// LPDDR4X 4266Mbps.
+	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 3, // Die-M. (1y-01).
+	LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 5, // Die-M. (1y-01).
+	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 6, // Die-M. (1y-01).
+
+	// LPDDR4X 3733Mbps.
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 8,  // Die-M. (1x-03).
+	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 9,  // Die-M. (1x-03).
+	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 10, // Die-M. (1x-03).
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // Die-E. (1x-03). D9WGB. 4266Mbps.
+
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 12, // Die-M. (1x-03).
+	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 13, // Die-M. (1x-03).
+	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 14, // Die-M. (1x-03).
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // Die-E. (1x-03). D9WGB. 4266Mbps.
+
+	// LPDDR4X 4266Mbps.
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 17, // Die-A. (1y-X03).
+	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 18, // Die-A. (1y-X03).
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 19, // Die-A. (1y-X03).
+
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 20, // Die-B. (1z-01). 40% lp.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 21, // Die-B. (1z-01). 40% lp.
+	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 22, // Die-B. (1z-01). 40% lp.
+
+	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 23, // Die-A. (1y-X03).
+	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 24, // Die-A. (1y-X03).
+
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // Die-F. (1y-01). D9XRR.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // Die-F. (1y-01). D9XRR.
+	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // Die-F. (1y-01). D9XRR.
+
+	LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 28, // Die-A. (1y-X03). 2nd gen.
+
+	// Old naming scheme: H9HCNNNBKMCLXR-NEE
+	LPDDR4X_IOWA_4GB_HYNIX_H54G46CYRBX267           = 29, // Die-C. (1a-01). 61% lp.
+	LPDDR4X_HOAG_4GB_HYNIX_H54G46CYRBX267           = 30, // Die-C. (1a-01). 61% lp.
+	LPDDR4X_AULA_4GB_HYNIX_H54G46CYRBX267           = 31, // Die-C. (1a-01). 61% lp.
+
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 32, // Die-B. (1a-01). D8BQM. 61% lp.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D1NP_046_WTB = 33, // Die-B. (1a-01). D8BQM. 61% lp.
+	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 34, // Die-B. (1a-01). D8BQM. 61% lp.
+};
+
+enum sdram_codes_mariko
+{
+	LPDDR4X_NO_PATCH                           = 0,
+	LPDDR4X_UNUSED                             = 0,
+
+	// LPDDR4X_4GB_SAMSUNG_K4U6E3S4AM_MGCJ          DRAM IDs: 08, 12.
+	// LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLHR_NME         DRAM IDs: 10, 14.
+
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 1, // DRAM IDs: 09, 13.
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 2, // DRAM IDs: 11, 15.
+	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 3, // DRAM IDs: 17, 19, 24.
+	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 4, // DRAM IDs: 18, 23, 28.
+	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 5, // DRAM IDs: 20, 21, 22.
+	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 6, // DRAM IDs: 25, 26, 27.
+	LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 7, // DRAM IDs: 03, 05, 06.
+	LPDDR4X_4GB_HYNIX_H54G46CYRBX267           = 8, // DRAM IDs: 29, 30, 31.
+	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB = 9, // DRAM IDs: 32, 33, 34.
+};

 void sdram_init();
-sdram_params_t *sdram_get_params();
-sdram_params_t *sdram_get_params_patched();
+void *sdram_get_params_patched();
+void *sdram_get_params_t210b01();
 void sdram_lp0_save_params(const void *params);
 emc_mr_data_t sdram_read_mrx(emc_mr_t mrx);

--- a/bdk/mem/sdram_config.inl
+++ b/bdk/mem/sdram_config.inl
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020 CTCaer
+ * Copyright (c) 2020-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -15,26 +15,9 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

-#define DRAM_CFG_SIZE 1896
+#define DRAM_CFG_T210_SIZE 1896

-#define DRAM_ID(x) (1 << (x))
-
-#define DRAM_4GB_SAMSUNG_K4F6E304HB_MGCH       0
-#define DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN      1
-#define DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT 2
-#define DRAM_4GB_COPPER_SAMSUNG                3
-#define DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH       4
-#define DRAM_4GB_COPPER_HYNIX                  5
-#define DRAM_4GB_COPPER_MICRON                 6
-
-typedef struct _sdram_vendor_patch_t
-{
-	u32 val;
-	u16 addr:9;
-	u16 dramid:7;
-} sdram_vendor_patch_t;
-
-static const sdram_params_t _dram_cfg_0_samsung_4gb = {
+static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	/* Specifies the type of memory device */
 	.memory_type                                     = MEMORY_TYPE_LPDDR4,

@@ -112,7 +95,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	 * DRAM size information
 	 * Specifies the value for EMC_ADR_CFG
 	 */
-	.emc_adr_cfg                                     = 0x00000001,
+	.emc_adr_cfg                                     = 0x00000001, // 2 Ranks.

 	/*
 	 * Specifies the time to wait after asserting pin
@@ -258,7 +241,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.emc_cfg_dig_dll                                 = 0x002C00A0,
 	.emc_cfg_dig_dll_1                               = 0x00003701,
 	.emc_cfg_dig_dll_period                          = 0x00008000,
-	.emc_dev_select                                  = 0x00000000,
+	.emc_dev_select                                  = 0x00000000, // Both Ranks.
 	.emc_sel_dpd_ctrl                                = 0x00040008,

 	/* Pads trimmer delays */
@@ -421,7 +404,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.pmc_ddr_ctrl                                    = 0x0007FF8B,
 	.emc_acpd_control                                = 0x00000000,

-	.emc_swizzle_rank0_byte0                         = 0x76543201,
+	.emc_swizzle_rank0_byte0                         = 0x76543201, // Overridden to 0x76543201 by spare6/7.
 	.emc_swizzle_rank0_byte1                         = 0x65324710,
 	.emc_swizzle_rank0_byte2                         = 0x25763410,
 	.emc_swizzle_rank0_byte3                         = 0x25673401,
@@ -451,9 +434,9 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.emc_dll_cfg0                                    = 0x1F13412F,
 	.emc_dll_cfg1                                    = 0x00010014,

-	.emc_pmc_scratch1                                = 0x4FAFFFFF,
+	.emc_pmc_scratch1                                = 0x4FAFFFFF, // APBDEV_PMC_IO_DPD3_REQ.
 	.emc_pmc_scratch2                                = 0x7FFFFFFF,
-	.emc_pmc_scratch3                                = 0x4006D70B,
+	.emc_pmc_scratch3                                = 0x4006D70B, // APBDEV_PMC_DDR_CNTRL.

 	.emc_pmacro_pad_cfg_ctrl                         = 0x00020000,
 	.emc_pmacro_vttgen_ctrl0                         = 0x00030808,
@@ -469,7 +452,7 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.emc_pmacro_data_rx_term_mode                    = 0x00000010,
 	.emc_pmacro_cmd_rx_term_mode                     = 0x00003000,
 	.emc_pmacro_data_pad_tx_ctrl                     = 0x02000111,
-	.emc_pmacro_common_pad_tx_ctrl                   = 0x00000008,
+	.emc_pmacro_common_pad_tx_ctrl                   = 0x00000008, // Overridden to 0x0000000A by spare4/5.
 	.emc_pmacro_cmd_pad_tx_ctrl                      = 0x0A000000,

 	.emc_cfg3                                        = 0x00000040,
@@ -505,18 +488,18 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.emc_pmacro_cmd_ctrl2                            = 0x0A0A0A0A,

 	/* DRAM size information */
-	.mc_emem_adr_cfg                                 = 0x00000001,
-	.mc_emem_adr_cfg_dev0                            = 0x00070302,
-	.mc_emem_adr_cfg_dev1                            = 0x00070302,
+	.mc_emem_adr_cfg                                 = 0x00000001, // 2 Ranks.
+	.mc_emem_adr_cfg_dev0                            = 0x00070302, // Chip 0 Density 512MB.
+	.mc_emem_adr_cfg_dev1                            = 0x00070302, // Chip 1 Density 512MB.
 	.mc_emem_adr_cfg_channel_mask                    = 0xFFFF2400,
 	.mc_emem_adr_cfg_bank_mask0                      = 0x6E574400,
 	.mc_emem_adr_cfg_bank_mask1                      = 0x39722800,
 	.mc_emem_adr_cfg_bank_mask2                      = 0x4B9C1000,
 	/*
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
-	 * size (in KBytes)
+	 * size (in MBytes)
 	 */
-	.mc_emem_cfg                                     = 0x00001000,
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.

 	/* MC arbitration configuration */
 	.mc_emem_arb_cfg                                 = 0x08000001,
@@ -555,16 +538,36 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	.mc_clken_override                               = 0x00008000,

 	.mc_stat_control                                 = 0x00000000,
+
+	/* VPR carveout configuration */
 	.mc_video_protect_bom                            = 0xFFF00000,
 	.mc_video_protect_bom_adr_hi                     = 0x00000000,
 	.mc_video_protect_size_mb                        = 0x00000000,
-	.mc_video_protect_vpr_override                   = 0xE4BAC343,
-	.mc_video_protect_vpr_override1                  = 0x00001ED3,
-	.mc_video_protect_gpu_override0                  = 0x00000000,
-	.mc_video_protect_gpu_override1                  = 0x00000000,
+
+	// Disable access:
+	//  AFI (PCIE), BPMP, HC (HOST1x), ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1 (WinT), SDMMC1/2/3. Plus TSEC, NVENC.
+	// Enable access:
+	//  DC, DCB, HDA, VIC.
+	.mc_video_protect_vpr_override                   = 0xE4FACB43, // Stock/Reset: 0xE4BAC343. HOS new: 0xE4FACB43. + TSEC, NVENC.
+	// Disable access:
+	//  SDMMC4, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus TSECB, TSEC1, TSECB1.
+	// Enable access:
+	//  GPU, GPUB, NVDEC, NVJPG, NVDEC1.
+	.mc_video_protect_vpr_override1                  = 0x0000FED3, // Stock/Reset: 0x00001ED3. HOS new: 0x0000FED3. + TSECB, TSEC1, TSECB1.
+
+	// VPR CYA. L4T override (set PD, SCC, SKED, L1 as UNTRUSTED).
+	.mc_video_protect_gpu_override0                  = VPR_OVR0_CYA_TRUST_GCC(VPR_TRUST_GRAPHICS)    |
+													   VPR_OVR0_CYA_TRUST_RASTER(VPR_TRUST_GRAPHICS) |
+													   VPR_OVR0_CYA_TRUST_PE(VPR_TRUST_GRAPHICS)     |
+													   VPR_OVR0_CYA_TRUST_TEX(VPR_TRUST_GRAPHICS)    |
+													   VPR_OVR0_CYA_TRUST_OVERRIDE,                 // Stock: 0. HOS: VPR_OVR0_CYA_TRUST_DEFAULT.
+	.mc_video_protect_gpu_override1                  = VPR_OVR1_CYA_TRUST_PROP(VPR_TRUST_GRAPHICS), // Stock: 0. HOS: 0.
+
+	/* TZDRAM carveout configuration */
 	.mc_sec_carveout_bom                             = 0xFFF00000,
 	.mc_sec_carveout_adr_hi                          = 0x00000000,
 	.mc_sec_carveout_size_mb                         = 0x00000000,
+
 	.mc_video_protect_write_access                   = 0x00000000,
 	.mc_sec_carveout_protect_write_access            = 0x00000000,

@@ -653,54 +656,36 @@ static const sdram_params_t _dram_cfg_0_samsung_4gb = {
 	/* Specifies data for patched boot rom write */
 	.boot_rom_patch_data                             = 0x00000000,

+	/* CPU FW carveout configuration */
 	.mc_mts_carveout_bom                             = 0xFFF00000,
 	.mc_mts_carveout_adr_hi                          = 0x00000000,
 	.mc_mts_carveout_size_mb                         = 0x00000000,
 	.mc_mts_carveout_reg_ctrl                        = 0x00000000
 };

-static const sdram_vendor_patch_t sdram_cfg_vendor_patches[] = {
+#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210_t, m) / 4)
+static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210[] = {
 	// Hynix timing config.
-	{ 0x0000000D,  67, DRAM_ID(1) | DRAM_ID(5) }, // emc_r2w.
-	{ 0x00000001,  91, DRAM_ID(1) | DRAM_ID(5) }, // emc_puterm_extra.
-	{ 0x80000000,  92, DRAM_ID(1) | DRAM_ID(5) }, // emc_puterm_width.
-	{ 0x00000210, 317, DRAM_ID(1) | DRAM_ID(5) }, // emc_pmacro_data_rx_term_mode.
-	{ 0x00000005, 368, DRAM_ID(1) | DRAM_ID(5) }, // mc_emem_arb_timing_r2w.
+	{ 0x0000000D, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_r2w)                      },
+	{ 0x00000001, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_extra)             },
+	{ 0x80000000, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_width)             },
+	{ 0x00000210, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_pmacro_data_rx_term_mode) },
+	{ 0x00000005, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(mc_emem_arb_timing_r2w)       },

 	// Samsung 6GB density config.
-	{ 0x000C0302, 347, DRAM_ID(4) },              // mc_emem_adr_cfg_dev0. 768MB sub-partition density.
-	{ 0x000C0302, 348, DRAM_ID(4) },              // mc_emem_adr_cfg_dev1. 768MB sub-partition density.
-	{ 0x00001800, 353, DRAM_ID(4) },              // mc_emem_cfg. 6GB total density.
+	{ 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0)         }, // 768MB Chip 0 density.
+	{ 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1)         }, // 768MB Chip 1 density.
+	{ 0x00001800, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_cfg)                  }, // 6GB total density. Max 8GB.

-#ifdef CONFIG_SDRAM_COPPER_SUPPORT
-	// Copper prototype Samsung/Hynix/Micron timing configs.
-	{ 0x0000003A,  59, DRAM_ID(6) },              // emc_rfc. Auto refresh.
-	{ 0x0000001D,  60, DRAM_ID(6) },              // emc_rfc_pb. Bank Auto refresh.
-	{ 0x00000012, 108, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_rw2pden.
-	{ 0x0000003B, 112, DRAM_ID(6) },              // emc_txsr.
-	{ 0x0000003B, 113, DRAM_ID(6) },              // emc_txsr_dll.
-	{ 0x00000003, 119, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_tclkstable.
-	{ 0x00120015, 205, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
-	{ 0x00160012, 206, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_5.
-	{ 0x00120015, 211, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
-	{ 0x00160012, 212, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_5.
-	{ 0x002F0032, 213, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
-	{ 0x00310032, 214, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
-	{ 0x00360034, 215, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
-	{ 0x0033002F, 216, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_3.
-	{ 0x00000006, 217, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
-	{ 0x002F0032, 219, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
-	{ 0x00310032, 220, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
-	{ 0x00360034, 221, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
-	{ 0x0033002F, 222, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_3.
-	{ 0x00000006, 223, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
-	{ 0x00150015, 233, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_0.
-	{ 0x00120012, 235, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_2.
-	{ 0x00160016, 236, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_3.
-	{ 0x00000015, 237, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_4.
-	{ 0x00000012, 295, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft2.
-	{ 0x00000012, 296, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft3.
-	{ 0x00000007, 370, DRAM_ID(6) },              // mc_emem_arb_timing_rfcpb. Bank refresh.
-	{ 0x72A30504, 373, DRAM_ID(6) },              // mc_emem_arb_misc0.
-#endif
+	// Samsung 8GB density config.
+	{ 0x0000003A, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_rfc)                      },
+	{ 0x0000001D, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_rfc_pb)                   },
+	{ 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_txsr)                     },
+	{ 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_txsr_dll)                 },
+	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0)         }, // 1024MB Chip 0 density.
+	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1)         }, // 1024MB Chip 1 density.
+	{ 0x00002000, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_cfg)                  }, // 8GB total density. Max 8GB.
+	{ 0x00000007, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_arb_timing_rfcpb)     },
+	{ 0x72A30504, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_arb_misc0)            },
 };
+#undef DCFG_OFFSET_OF
--- a/bdk/mem/sdram_config_lz.inl
+++ b/bdk/mem/sdram_config_lz.inl
@@ -1,124 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-static const u8 _dram_cfg_lz[1262] = {
-	0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
-	0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08,
-	0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00,
-	0x00, 0x04, 0xB4, 0x01, 0x70, 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00,
-	0x70, 0x17, 0x10, 0x24, 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40,
-	0x00, 0x00, 0x00, 0x17, 0x04, 0x04, 0x17, 0x09, 0x18, 0xFF, 0xFF, 0x1F,
-	0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, 0x77,
-	0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x08, 0x08, 0xA6, 0xA6,
-	0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, 0x04, 0x04,
-	0x04, 0x04, 0x17, 0x04, 0x04, 0x17, 0x04, 0x3C, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x17, 0x04, 0x04, 0x17, 0x06, 0x06, 0x00, 0x00, 0x04, 0x08, 0x17, 0x06,
-	0x46, 0xA1, 0x01, 0x00, 0x00, 0x32, 0x17, 0x0B, 0x64, 0x01, 0x17, 0x04,
-	0x7C, 0x17, 0x07, 0x0C, 0x03, 0x17, 0x04, 0x04, 0x00, 0x00, 0x00, 0x1E,
-	0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x13,
-	0x17, 0x0B, 0x2C, 0x09, 0x00, 0x00, 0x00, 0x17, 0x05, 0x5D, 0x17, 0x07,
-	0x10, 0x0B, 0x17, 0x07, 0x28, 0x08, 0x17, 0x07, 0x0C, 0x17, 0x04, 0x1C,
-	0x20, 0x00, 0x00, 0x00, 0x06, 0x17, 0x04, 0x04, 0x17, 0x07, 0x08, 0x17,
-	0x04, 0x50, 0x17, 0x04, 0x2C, 0x17, 0x04, 0x1C, 0x17, 0x04, 0x10, 0x17,
-	0x08, 0x6C, 0x17, 0x04, 0x10, 0x17, 0x04, 0x38, 0x17, 0x04, 0x40, 0x05,
-	0x17, 0x07, 0x1C, 0x17, 0x08, 0x58, 0x17, 0x04, 0x24, 0x17, 0x04, 0x18,
-	0x17, 0x08, 0x64, 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14,
-	0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x17, 0x09, 0x0C, 0x17, 0x05, 0x82,
-	0x58, 0x17, 0x07, 0x61, 0xC1, 0x17, 0x07, 0x50, 0x17, 0x04, 0x04, 0x17,
-	0x08, 0x81, 0x48, 0x17, 0x04, 0x04, 0x17, 0x04, 0x28, 0x17, 0x04, 0x60,
-	0x17, 0x08, 0x54, 0x27, 0x17, 0x04, 0x04, 0x17, 0x07, 0x14, 0x17, 0x04,
-	0x04, 0x04, 0x17, 0x07, 0x81, 0x58, 0x17, 0x0C, 0x0C, 0x1C, 0x03, 0x00,
-	0x00, 0x0D, 0xA0, 0x60, 0x91, 0xBF, 0x3B, 0x17, 0x04, 0x5A, 0xF3, 0x0C,
-	0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05,
-	0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03,
-	0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02,
-	0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08,
-	0x24, 0x06, 0x07, 0x9A, 0x12, 0x17, 0x05, 0x83, 0x41, 0x00, 0xFF, 0x17,
-	0x10, 0x83, 0x6C, 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00,
-	0x00, 0x0D, 0x08, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00,
-	0x00, 0x0B, 0x08, 0x72, 0x72, 0x0E, 0x0C, 0x17, 0x04, 0x20, 0x08, 0x08,
-	0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x17, 0x06,
-	0x2C, 0x11, 0x08, 0x17, 0x10, 0x84, 0x67, 0x15, 0x00, 0xCC, 0x00, 0x0A,
-	0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, 0xFF,
-	0x0F, 0xFF, 0x0F, 0x17, 0x08, 0x83, 0x4C, 0x01, 0x03, 0x00, 0x70, 0x00,
-	0x0C, 0x00, 0x01, 0x17, 0x04, 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04,
-	0x00, 0x06, 0x13, 0x07, 0x00, 0x80, 0x17, 0x04, 0x10, 0xA0, 0x00, 0x2C,
-	0x00, 0x01, 0x37, 0x00, 0x00, 0x00, 0x80, 0x17, 0x06, 0x48, 0x08, 0x00,
-	0x04, 0x00, 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28,
-	0x28, 0x28, 0x17, 0x04, 0x04, 0x11, 0x11, 0x11, 0x11, 0x17, 0x04, 0x04,
-	0xBE, 0x00, 0x00, 0x17, 0x05, 0x58, 0x17, 0x08, 0x5C, 0x17, 0x22, 0x85,
-	0x6A, 0x17, 0x1A, 0x1A, 0x14, 0x00, 0x12, 0x00, 0x10, 0x17, 0x05, 0x83,
-	0x0A, 0x17, 0x16, 0x18, 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00,
-	0x33, 0x00, 0x35, 0x00, 0x30, 0x00, 0x32, 0x17, 0x05, 0x83, 0x0C, 0x17,
-	0x04, 0x20, 0x17, 0x18, 0x18, 0x28, 0x00, 0x28, 0x17, 0x04, 0x04, 0x17,
-	0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x14, 0x17, 0x05, 0x5A, 0x17, 0x04,
-	0x5C, 0x17, 0x04, 0x5E, 0x17, 0x04, 0x0E, 0x17, 0x0E, 0x78, 0x17, 0x09,
-	0x82, 0x50, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51,
-	0x17, 0x08, 0x18, 0x80, 0x01, 0x00, 0x00, 0x40, 0x17, 0x04, 0x20, 0x03,
-	0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x17, 0x08, 0x82, 0x58,
-	0x17, 0x0C, 0x38, 0x17, 0x1B, 0x81, 0x6C, 0x17, 0x08, 0x85, 0x60, 0x17,
-	0x08, 0x86, 0x50, 0x17, 0x08, 0x86, 0x60, 0x17, 0x06, 0x83, 0x21, 0x22,
-	0x04, 0xFF, 0xFF, 0xAF, 0x4F, 0x17, 0x0C, 0x86, 0x74, 0x17, 0x08, 0x2C,
-	0x8B, 0xFF, 0x07, 0x17, 0x06, 0x81, 0x04, 0x32, 0x54, 0x76, 0x10, 0x47,
-	0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75,
-	0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45,
-	0x32, 0x67, 0x17, 0x04, 0x24, 0x49, 0x92, 0x24, 0x17, 0x04, 0x04, 0x17,
-	0x11, 0x7C, 0x1B, 0x17, 0x04, 0x04, 0x17, 0x13, 0x81, 0x14, 0x2F, 0x41,
-	0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x17, 0x04, 0x7C, 0xFF, 0xFF, 0xFF,
-	0x7F, 0x0B, 0xD7, 0x06, 0x40, 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03,
-	0x00, 0x00, 0x5C, 0x01, 0x00, 0x10, 0x10, 0x10, 0x17, 0x06, 0x86, 0x59,
-	0x17, 0x0F, 0x89, 0x14, 0x37, 0x17, 0x07, 0x82, 0x72, 0x10, 0x17, 0x06,
-	0x83, 0x0D, 0x00, 0x11, 0x01, 0x17, 0x05, 0x85, 0x39, 0x17, 0x04, 0x0E,
-	0x0A, 0x17, 0x07, 0x89, 0x29, 0x17, 0x04, 0x1B, 0x17, 0x08, 0x86, 0x77,
-	0x17, 0x09, 0x12, 0x20, 0x00, 0x00, 0x00, 0x81, 0x10, 0x09, 0x28, 0x93,
-	0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76, 0x17, 0x18, 0x82, 0x2C, 0xFF,
-	0xEF, 0xFF, 0xEF, 0xC0, 0xC0, 0xC0, 0xC0, 0x17, 0x04, 0x04, 0xDC, 0xDC,
-	0xDC, 0xDC, 0x0A, 0x0A, 0x0A, 0x0A, 0x17, 0x04, 0x04, 0x17, 0x04, 0x04,
-	0x17, 0x05, 0x82, 0x24, 0x03, 0x07, 0x17, 0x04, 0x04, 0x00, 0x00, 0x24,
-	0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, 0x10,
-	0x9C, 0x4B, 0x17, 0x04, 0x64, 0x01, 0x00, 0x00, 0x08, 0x4C, 0x00, 0x00,
-	0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x17, 0x06, 0x85, 0x60, 0x17,
-	0x10, 0x82, 0x74, 0x17, 0x08, 0x08, 0x17, 0x08, 0x88, 0x00, 0x17, 0x04,
-	0x10, 0x04, 0x17, 0x0B, 0x87, 0x6C, 0x01, 0x00, 0x02, 0x02, 0x01, 0x02,
-	0x03, 0x00, 0x04, 0x05, 0xC3, 0x71, 0x0F, 0x0F, 0x17, 0x08, 0x8B, 0x18,
-	0x1F, 0x17, 0x09, 0x81, 0x73, 0x00, 0xFF, 0x00, 0xFF, 0x17, 0x05, 0x86,
-	0x48, 0x17, 0x04, 0x0C, 0x17, 0x07, 0x86, 0x34, 0x00, 0x00, 0xF0, 0x17,
-	0x09, 0x87, 0x54, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x17, 0x0C, 0x81,
-	0x52, 0x17, 0x0A, 0x1C, 0x17, 0x10, 0x81, 0x6C, 0x17, 0x0A, 0x82, 0x21,
-	0x17, 0x07, 0x82, 0x4D, 0x17, 0x0A, 0x8A, 0x1B, 0x17, 0x11, 0x2C, 0x76,
-	0x0C, 0x17, 0x0A, 0x8A, 0x67, 0x17, 0x0F, 0x84, 0x28, 0x17, 0x06, 0x34,
-	0x17, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x17, 0x0C, 0x8B, 0x1F, 0x17, 0x2A,
-	0x38, 0x1E, 0x17, 0x0A, 0x38, 0x17, 0x13, 0x81, 0x28, 0x00, 0xC0, 0x17,
-	0x17, 0x55, 0x46, 0x24, 0x17, 0x0A, 0x81, 0x28, 0x17, 0x14, 0x38, 0x17,
-	0x18, 0x81, 0x60, 0x46, 0x2C, 0x17, 0x06, 0x38, 0xEC, 0x17, 0x0D, 0x16,
-	0x17, 0x0E, 0x82, 0x3C, 0x17, 0x82, 0x0C, 0x8E, 0x68, 0x17, 0x04, 0x24,
-	0x17, 0x5C, 0x8E, 0x68, 0x17, 0x07, 0x82, 0x5F, 0x80, 0x17, 0x87, 0x01,
-	0x8E, 0x68, 0x02, 0x17, 0x81, 0x4A, 0x8E, 0x68, 0x17, 0x0C, 0x87, 0x78,
-	0x17, 0x85, 0x28, 0x8E, 0x68, 0x17, 0x8E, 0x68, 0x9D, 0x50, 0x17, 0x81,
-	0x24, 0x8E, 0x68, 0x17, 0x04, 0x2C, 0x17, 0x28, 0x8E, 0x68, 0x17, 0x04,
-	0x30, 0x17, 0x85, 0x3C, 0x8E, 0x68, 0x12, 0x17, 0x07, 0x85, 0x70, 0x17,
-	0x88, 0x74, 0x8E, 0x68, 0x17, 0x87, 0x3E, 0x9D, 0x50, 0x0C, 0x17, 0x04,
-	0x04, 0x17, 0x12, 0x8E, 0x68, 0x18, 0x17, 0x87, 0x12, 0xBB, 0x20, 0x17,
-	0x83, 0x04, 0x9D, 0x50, 0x15, 0x17, 0x05, 0x8D, 0x76, 0x17, 0x0F, 0x8B,
-	0x49, 0x17, 0x0B, 0x18, 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00,
-	0x34, 0x00, 0x36, 0x00, 0x2F, 0x00, 0x33, 0x17, 0x09, 0x84, 0x0C, 0x17,
-	0x18, 0x18, 0x17, 0x20, 0x8E, 0x68, 0x15, 0x17, 0x07, 0x5A, 0x17, 0x06,
-	0x5E, 0x16, 0x00, 0x15, 0x17, 0x82, 0x40, 0x9D, 0x50, 0x17, 0x86, 0x5F,
-	0xBB, 0x20, 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x17, 0x81, 0x4F, 0xAC, 0x38,
-	0x3B, 0x17, 0x04, 0x04, 0x17, 0x86, 0x30, 0x8E, 0x68, 0x17, 0x81, 0x53,
-	0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10,
-	0x8E, 0x68
-};
--- a/bdk/mem/sdram_config_t210b01.inl
+++ b/bdk/mem/sdram_config_t210b01.inl
@@ -0,0 +1,824 @@
+/*
+ * Copyright (c) 2020-2026 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define DRAM_CFG_T210B01_SIZE 2104
+
+static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
+	/* Specifies the type of memory device */
+	.memory_type                                     = MEMORY_TYPE_LPDDR4,
+
+	/* MC/EMC clock source configuration */
+	.pllm_input_divider                              = 0x00000001, // M div.
+	.pllm_feedback_divider                           = 0x00000022, // N div.
+	.pllm_stable_time                                = 0x0000012C,
+	.pllm_setup_control                              = 0x00000000,
+	.pllm_post_divider                               = 0x00000000, // P div.
+	.pllm_kcp                                        = 0x00000000,
+	.pllm_kvco                                       = 0x00000000,
+
+	/* Spare BCT params */
+	.emc_bct_spare0                                  = 0x00000000,
+	.emc_bct_spare1                                  = 0x00000000,
+	.emc_bct_spare2                                  = 0x00000000,
+	.emc_bct_spare3                                  = 0x00000000,
+	.emc_bct_spare4                                  = 0x00000000,
+	.emc_bct_spare5                                  = 0x00000000,
+	.emc_bct_spare6                                  = 0x00000000,
+	.emc_bct_spare7                                  = 0x00000000,
+	.emc_bct_spare8                                  = 0x00000000,
+	.emc_bct_spare9                                  = 0x00000000,
+	.emc_bct_spare10                                 = 0x00000000,
+	.emc_bct_spare11                                 = 0x00000000,
+	.emc_bct_spare12                                 = 0x00000000,
+	.emc_bct_spare13                                 = 0x00000000,
+
+	.emc_bct_spare_secure0                           = 0x00000000,
+	.emc_bct_spare_secure1                           = 0x00000000,
+	.emc_bct_spare_secure2                           = 0x00000000,
+	.emc_bct_spare_secure3                           = 0x00000000,
+	.emc_bct_spare_secure4                           = 0x00000000,
+	.emc_bct_spare_secure5                           = 0x00000000,
+	.emc_bct_spare_secure6                           = 0x00000000,
+	.emc_bct_spare_secure7                           = 0x00000000,
+	.emc_bct_spare_secure8                           = 0x00000000,
+	.emc_bct_spare_secure9                           = 0x00000000,
+	.emc_bct_spare_secure10                          = 0x00000000,
+	.emc_bct_spare_secure11                          = 0x00000000,
+	.emc_bct_spare_secure12                          = 0x00000000,
+	.emc_bct_spare_secure13                          = 0x00000000,
+	.emc_bct_spare_secure14                          = 0x00000000,
+	.emc_bct_spare_secure15                          = 0x00000000,
+	.emc_bct_spare_secure16                          = 0x00000000,
+	.emc_bct_spare_secure17                          = 0x00000000,
+	.emc_bct_spare_secure18                          = 0x00000000,
+	.emc_bct_spare_secure19                          = 0x00000000,
+	.emc_bct_spare_secure20                          = 0x00000000,
+	.emc_bct_spare_secure21                          = 0x00000000,
+	.emc_bct_spare_secure22                          = 0x00000000,
+	.emc_bct_spare_secure23                          = 0x00000000,
+
+	/* EMC clock configuration */
+	.emc_clock_source                                = 0x40188002,
+	.emc_clock_source_dll                            = 0x40000000,
+
+	.clk_rst_pllm_misc20_override                    = 0x00000000,
+	.clk_rst_pllm_misc20_override_enable             = 0x00000000,
+
+	.clear_clock2_mc1                                = 0x00000000,
+
+	/* Auto-calibration of EMC pads */
+	.emc_auto_cal_interval                           = 0x001FFFFF,
+
+	.emc_auto_cal_config                             = 0xA01A51D8,
+	.emc_auto_cal_config2                            = 0x00000000,
+	.emc_auto_cal_config3                            = 0x00880000,
+
+	.emc_auto_cal_config4                            = 0x00880000,
+	.emc_auto_cal_config5                            = 0x00001220,
+	.emc_auto_cal_config6                            = 0x00880000,
+	.emc_auto_cal_config7                            = 0x00880000,
+	.emc_auto_cal_config8                            = 0x00880000,
+	.emc_auto_cal_config9                            = 0x00000000,
+
+	.emc_auto_cal_vref_sel0                          = 0xB3C5BCBC,
+	.emc_auto_cal_vref_sel1                          = 0x00009E3C,
+
+	.emc_auto_cal_channel                            = 0xC1E00302,
+
+	.emc_pmacro_auto_cal_cfg0                        = 0x04040404,
+	.emc_pmacro_auto_cal_cfg1                        = 0x04040404,
+	.emc_pmacro_auto_cal_cfg2                        = 0x04040404,
+
+	.emc_pmacro_rx_term                              = 0x3F3F3F3F,
+	.emc_pmacro_dq_tx_drive                          = 0x3F3F3F3F,
+	.emc_pmacro_ca_tx_drive                          = 0x3F3F3F3F,
+	.emc_pmacro_cmd_tx_drive                         = 0x00001220,
+	.emc_pmacro_auto_cal_common                      = 0x00000804,
+	.emc_pmacro_zcrtl                                = 0x00505050,
+
+	/* Specifies the time for the calibration to stabilize (in microseconds) */
+	.emc_auto_cal_wait                               = 0x000001A1,
+
+	.emc_xm2_comp_pad_ctrl                           = 0x00000030,
+	.emc_xm2_comp_pad_ctrl2                          = 0x16001000,
+	.emc_xm2_comp_pad_ctrl3                          = 0x00901000,
+
+	/*
+	 * DRAM size information
+	 * Specifies the value for EMC_ADR_CFG
+	 */
+	.emc_adr_cfg                                     = 0x00000000, // 1 Rank.
+
+	/*
+	 * Specifies the time to wait after asserting pin
+	 * CKE (in microseconds)
+	 */
+	.emc_pin_program_wait                            = 0x00000002,
+	/* Specifies the extra delay before/after pin RESET/CKE command */
+	.emc_pin_extra_wait                              = 0x00000000,
+
+	.emc_pin_gpio_enable                             = 0x00000003,
+	.emc_pin_gpio                                    = 0x00000003,
+
+	/* Specifies the extra delay after the first writing of EMC_TIMING_CONTROL */
+	.emc_timing_control_wait                         = 0x0000001E,
+
+	/* Timing parameters required for the SDRAM */
+	.emc_rc                                          = 0x0000000D,
+	.emc_rfc                                         = 0x0000003A,
+	.emc_rfc_pb                                      = 0x0000001D,
+	.emc_ref_ctrl2                                   = 0x00000000,
+	.emc_rfc_slr                                     = 0x00000000,
+	.emc_ras                                         = 0x00000009,
+	.emc_rp                                          = 0x00000004,
+	.emc_r2r                                         = 0x00000000,
+	.emc_w2w                                         = 0x00000000,
+	.emc_r2w                                         = 0x0000000B,
+	.emc_w2r                                         = 0x0000000D,
+	.emc_r2p                                         = 0x00000008,
+	.emc_w2p                                         = 0x0000000B,
+	.emc_tppd                                        = 0x00000004,
+	.emc_trtm                                        = 0x00000017,
+	.emc_twtm                                        = 0x00000015,
+	.emc_tratm                                       = 0x00000017,
+	.emc_twatm                                       = 0x0000001B,
+	.emc_tr2ref                                      = 0x00000000,
+	.emc_ccdmw                                       = 0x00000020,
+	.emc_rd_rcd                                      = 0x00000006,
+	.emc_wr_rcd                                      = 0x00000006,
+	.emc_rrd                                         = 0x00000006,
+	.emc_rext                                        = 0x00000003,
+	.emc_wext                                        = 0x00000000,
+	.emc_wdv                                         = 0x00000004,
+	.emc_wdv_chk                                     = 0x00000006,
+	.emc_wsv                                         = 0x00000002,
+	.emc_wev                                         = 0x00000000,
+	.emc_wdv_mask                                    = 0x00000004,
+	.emc_ws_duration                                 = 0x00000008,
+	.emc_we_duration                                 = 0x0000000E,
+	.emc_quse                                        = 0x00000005,
+	.emc_quse_width                                  = 0x00000006,
+	.emc_ibdly                                       = 0x00000000,
+	.emc_obdly                                       = 0x00000000,
+	.emc_einput                                      = 0x00000002,
+	.emc_einput_duration                             = 0x0000000D,
+	.emc_puterm_extra                                = 0x00000001,
+	.emc_puterm_width                                = 0x80000000,
+	.emc_qrst                                        = 0x00010000,
+	.emc_qsafe                                       = 0x00000012,
+	.emc_rdv                                         = 0x00000018,
+	.emc_rdv_mask                                    = 0x0000001A,
+	.emc_rdv_early                                   = 0x00000016,
+	.emc_rdv_early_mask                              = 0x00000018,
+	.emc_qpop                                        = 0x0000000A,
+	.emc_refresh                                     = 0x00000304,
+	.emc_burst_refresh_num                           = 0x00000000,
+	.emc_prerefresh_req_cnt                          = 0x000000C1,
+	.emc_pdex2wr                                     = 0x00000008,
+	.emc_pdex2rd                                     = 0x00000008,
+	.emc_pchg2pden                                   = 0x00000003,
+	.emc_act2pden                                    = 0x0000000A,
+	.emc_ar2pden                                     = 0x00000003,
+	.emc_rw2pden                                     = 0x00000014,
+	.emc_cke2pden                                    = 0x00000005,
+	.emc_pdex2che                                    = 0x00000002,
+	.emc_pdex2mrr                                    = 0x0000000D,
+	.emc_txsr                                        = 0x0000003B,
+	.emc_txsr_dll                                    = 0x0000003B,
+	.emc_tcke                                        = 0x00000005,
+	.emc_tckesr                                      = 0x00000005,
+	.emc_tpd                                         = 0x00000004,
+	.emc_tfaw                                        = 0x00000009,
+	.emc_trpab                                       = 0x00000005,
+	.emc_tclkstable                                  = 0x00000004,
+	.emc_tclkstop                                    = 0x00000009,
+	.emc_trefbw                                      = 0x0000031C,
+
+	/* FBIO configuration values */
+	.emc_fbio_cfg5                                   = 0x9160A00D,
+	.emc_fbio_cfg7                                   = 0x00003A3F,
+	.emc_fbio_cfg8                                   = 0x0CF30000,
+
+	/* Command mapping for CMD brick 0 */
+	.emc_cmd_mapping_cmd0_0                          = 0x061B0504,
+	.emc_cmd_mapping_cmd0_1                          = 0x1C070302,
+	.emc_cmd_mapping_cmd0_2                          = 0x05252523,
+	.emc_cmd_mapping_cmd1_0                          = 0x0A091D08,
+	.emc_cmd_mapping_cmd1_1                          = 0x0D1E0B24,
+	.emc_cmd_mapping_cmd1_2                          = 0x0326260C,
+	.emc_cmd_mapping_cmd2_0                          = 0x231C1B02,
+	.emc_cmd_mapping_cmd2_1                          = 0x05070403,
+	.emc_cmd_mapping_cmd2_2                          = 0x02252506,
+	.emc_cmd_mapping_cmd3_0                          = 0x0D1D0B0A,
+	.emc_cmd_mapping_cmd3_1                          = 0x1E090C08,
+	.emc_cmd_mapping_cmd3_2                          = 0x08262624,
+	.emc_cmd_mapping_byte                            = 0x9A070624,
+
+	.emc_fbio_spare                                  = 0x00000012,
+	.emc_cfg_rsv                                     = 0xFF00FF00,
+
+	/* MRS command values */
+	.emc_mrs                                         = 0x00000000,
+	.emc_emrs                                        = 0x00000000,
+	.emc_emrs2                                       = 0x00000000,
+	.emc_emrs3                                       = 0x00000000,
+	.emc_mrw1                                        = 0x88010004,
+	.emc_mrw2                                        = 0x88020000,
+	.emc_mrw3                                        = 0x880D0000,
+	.emc_mrw4                                        = 0xC0000000,
+	.emc_mrw6                                        = 0x88033131,
+	.emc_mrw8                                        = 0x880B0000,
+	.emc_mrw9                                        = 0x8C0E5D5D,
+	.emc_mrw10                                       = 0x880C5D5D,
+	.emc_mrw12                                       = 0x8C0D0808,
+	.emc_mrw13                                       = 0x8C0D0000,
+	.emc_mrw14                                       = 0x88161616,
+	.emc_mrw_extra                                   = 0x88010004,
+	.emc_warm_boot_mrw_extra                         = 0x08110000,
+	.emc_warm_boot_extramode_reg_write_enable        = 0x00000001,
+	.emc_extramode_reg_write_enable                  = 0x00000000,
+	.emc_mrw_reset_command                           = 0x00000000,
+	.emc_mrw_reset_ninit_wait                        = 0x00000000,
+	.emc_mrs_wait_cnt                                = 0x00CC0010,
+	.emc_mrs_wait_cnt2                               = 0x0033000A,
+
+	/* EMC miscellaneous configurations */
+	.emc_cfg                                         = 0xF3200000,
+	.emc_cfg2                                        = 0x00110825,
+	.emc_cfg_pipe                                    = 0x0FFF0000,
+	.emc_cfg_pipe_clk                                = 0x00000000,
+	.emc_fdpd_ctrl_cmd_no_ramp                       = 0x00000001,
+	.emc_cfg_update                                  = 0x70000301,
+	.emc_dbg                                         = 0x01000C00,
+	.emc_dbg_write_mux                               = 0x00000001,
+	.emc_cmd_q                                       = 0x10004408,
+	.emc_mc2emc_q                                    = 0x06000404,
+	.emc_dyn_self_ref_control                        = 0x00000713,
+	.ahb_arbitration_xbar_ctrl_meminit_done          = 0x00000001,
+	.emc_cfg_dig_dll                                 = 0x002C00A0,
+	.emc_cfg_dig_dll_1                               = 0x000F3701,
+	.emc_cfg_dig_dll_period                          = 0x00008000,
+	.emc_dev_select                                  = 0x00000002, // Rank 0 only.
+	.emc_sel_dpd_ctrl                                = 0x0004000C,
+
+	/* Pads trimmer delays */
+	.emc_fdpd_ctrl_dq                                = 0x8020221F,
+	.emc_fdpd_ctrl_cmd                               = 0x0220F40F,
+	.emc_pmacro_ib_vref_dq_0                         = 0x29292929,
+	.emc_pmacro_ib_vref_dq_1                         = 0x29292929,
+	.emc_pmacro_ib_vref_dqs_0                        = 0x29292929,
+	.emc_pmacro_ib_vref_dqs_1                        = 0x29292929,
+	.emc_pmacro_ib_rxrt                              = 0x00000078,
+	.emc_cfg_pipe1                                   = 0x0FFF0000,
+	.emc_cfg_pipe2                                   = 0x00000000,
+
+	.emc_pmacro_quse_ddll_rank0_0                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_1                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_2                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_3                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_4                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank0_5                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_0                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_1                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_2                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_3                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_4                    = 0x00000000,
+	.emc_pmacro_quse_ddll_rank1_5                    = 0x00000000,
+
+	.emc_pmacro_ob_ddll_long_dq_rank0_0              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_1              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_2              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_3              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank0_4              = 0x000D0016,
+	.emc_pmacro_ob_ddll_long_dq_rank0_5              = 0x0017000B,
+	.emc_pmacro_ob_ddll_long_dq_rank1_0              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_1              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_2              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_3              = 0x00000000,
+	.emc_pmacro_ob_ddll_long_dq_rank1_4              = 0x000D0016,
+	.emc_pmacro_ob_ddll_long_dq_rank1_5              = 0x0017000B,
+
+	.emc_pmacro_ob_ddll_long_dqs_rank0_0             = 0x00450043,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_1             = 0x00430045,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_2             = 0x00470046,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_3             = 0x00460041,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_4             = 0x0003000C,
+	.emc_pmacro_ob_ddll_long_dqs_rank0_5             = 0x000D0000,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_0             = 0x00450043,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_1             = 0x00430045,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_2             = 0x00470046,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_3             = 0x00460041,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_4             = 0x0003000C,
+	.emc_pmacro_ob_ddll_long_dqs_rank1_5             = 0x000D0000,
+
+	.emc_pmacro_ib_ddll_long_dqs_rank0_0             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank0_1             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank0_2             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank0_3             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_0             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_1             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_2             = 0x00280028,
+	.emc_pmacro_ib_ddll_long_dqs_rank1_3             = 0x00280028,
+
+	.emc_pmacro_ddll_long_cmd_0                      = 0x00160016,
+	.emc_pmacro_ddll_long_cmd_1                      = 0x000D000D,
+	.emc_pmacro_ddll_long_cmd_2                      = 0x000B000B,
+	.emc_pmacro_ddll_long_cmd_3                      = 0x00170017,
+	.emc_pmacro_ddll_long_cmd_4                      = 0x00000016,
+	.emc_pmacro_ddll_short_cmd_0                     = 0x00000000,
+	.emc_pmacro_ddll_short_cmd_1                     = 0x00000000,
+	.emc_pmacro_ddll_short_cmd_2                     = 0x00000000,
+
+	.emc_pmacro_ddll_periodic_offset                 = 0x00000000,
+
+	/*
+	 * Specifies the delay after asserting CKE pin during a WarmBoot0
+	 * sequence (in microseconds)
+	 */
+	.warm_boot_wait                                  = 0x00000001,
+
+	.emc_odt_write                                   = 0x00000000,
+
+	/* Periodic ZQ calibration */
+
+	/*
+	 * Specifies the value for EMC_ZCAL_INTERVAL
+	 * Value 0 disables ZQ calibration
+	 */
+	.emc_zcal_interval                               = 0x00064000,
+	.emc_zcal_wait_cnt                               = 0x000900CC,
+	.emc_zcal_mrw_cmd                                = 0x8051004F,
+
+	/* DRAM initialization sequence flow control */
+	.emc_mrs_reset_dll                               = 0x00000000,
+	.emc_zcal_init_dev0                              = 0x80000001,
+	.emc_zcal_init_dev1                              = 0x00000000,
+	/*
+	 * Specifies the wait time after programming a ZQ initialization
+	 * command (in microseconds)
+	 */
+	.emc_zcal_init_wait                              = 0x00000001,
+	/*
+	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
+	 * and warm boot [bit 1]
+	 */
+	.emc_zcal_warm_cold_boot_enables                 = 0x00000003,
+
+	/*
+	 * Specifies the MRW command to LPDDR2 for ZQ calibration
+	 * on warmboot
+	 */
+	/* Is issued to both devices separately */
+	.emc_mrw_lpddr2zcal_warm_boot                    = 0x040A00AB,
+	/*
+	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
+	 * Is issued to both devices separately
+	 */
+	.emc_zqcal_ddr3_warm_boot                        = 0x00000011,
+	.emc_zqcal_lpddr4_warm_boot                      = 0x00000001,
+
+	/*
+	 * Specifies the wait time for ZQ calibration on warmboot
+	 * (in microseconds)
+	 */
+	.emc_zcal_warm_boot_wait                         = 0x00000001,
+	/*
+	 * Specifies the enable for DRAM Mode Register programming
+	 * at warm boot
+	 */
+	.emc_mrs_warm_boot_enable                        = 0x00000001,
+	.emc_mrs_reset_dll_wait                          = 0x00000000,
+	.emc_mrs_extra                                   = 0x00000000,
+	.emc_warm_boot_mrs_extra                         = 0x00000000,
+	.emc_emrs_ddr2_dll_enable                        = 0x00000000,
+	.emc_mrs_ddr2_dll_reset                          = 0x00000000,
+	.emc_emrs_ddr2_ocd_calib                         = 0x00000000,
+	/*
+	 * Specifies the wait between initializing DDR and setting OCD
+	 * calibration (in microseconds)
+	 */
+	.emc_ddr2_wait                                   = 0x00000000,
+	.emc_clken_override                              = 0x00000000,
+	/*
+	 * Specifies LOG2 of the extra refresh numbers after booting
+	 * Program 0 to disable
+	 */
+	.emc_extra_refresh_num                           = 0x00000002,
+	.emc_clken_override_allwarm_boot                 = 0x00000000,
+	.mc_clken_override_allwarm_boot                  = 0x00000000,
+	/* Specifies digital dll period, choosing between 4 to 64 ms */
+	.emc_cfg_dig_dll_period_warm_boot                = 0x00000003,
+
+	/* Pad controls */
+	.pmc_vddp_sel                                    = 0x00000001,
+	.pmc_vddp_sel_wait                               = 0x00000002,
+	.pmc_ddr_cfg                                     = 0x04220100,
+	.pmc_io_dpd3_req                                 = 0x4FAF9FFF,
+	.pmc_io_dpd3_req_wait                            = 0x00000001,
+	.pmc_io_dpd4_req_wait                            = 0x00000002,
+	.pmc_reg_short                                   = 0x00000000,
+	.pmc_no_io_power                                 = 0x00000000,
+	.pmc_ddr_ctrl_wait                               = 0x00000000,
+	.pmc_ddr_ctrl                                    = 0x0037FF9F,
+	.emc_acpd_control                                = 0x00000000,
+
+	.emc_swizzle_rank0_byte0                         = 0x76543201,
+	.emc_swizzle_rank0_byte1                         = 0x65324710,
+	.emc_swizzle_rank0_byte2                         = 0x25763410,
+	.emc_swizzle_rank0_byte3                         = 0x25673401,
+	.emc_swizzle_rank1_byte0                         = 0x32647501,
+	.emc_swizzle_rank1_byte1                         = 0x34567201,
+	.emc_swizzle_rank1_byte2                         = 0x56742310,
+	.emc_swizzle_rank1_byte3                         = 0x67324501,
+
+	.emc_txdsrvttgen                                 = 0x00000000,
+
+	.emc_data_brlshft0                               = 0x00249249,
+	.emc_data_brlshft1                               = 0x00249249,
+
+	.emc_dqs_brlshft0                                = 0x00000000,
+	.emc_dqs_brlshft1                                = 0x00000000,
+
+	.emc_cmd_brlshft0                                = 0x00000000,
+	.emc_cmd_brlshft1                                = 0x00000000,
+	.emc_cmd_brlshft2                                = 0x00000012,
+	.emc_cmd_brlshft3                                = 0x00000012,
+
+	.emc_quse_brlshft0                               = 0x00000000,
+	.emc_quse_brlshft1                               = 0x00000000,
+	.emc_quse_brlshft2                               = 0x00000000,
+	.emc_quse_brlshft3                               = 0x00000000,
+
+	.emc_dll_cfg0                                    = 0x1F134120,
+	.emc_dll_cfg1                                    = 0x00010014,
+
+	.emc_pmc_scratch1                                = 0x4FAF9FFF,
+	.emc_pmc_scratch2                                = 0x7FFFFFFF,
+	.emc_pmc_scratch3                                = 0x4036D71F,
+
+	.emc_pmacro_pad_cfg_ctrl                         = 0x00000000,
+	.emc_pmacro_vttgen_ctrl0                         = 0x00090000,
+	.emc_pmacro_vttgen_ctrl1                         = 0x00103400,
+	.emc_pmacro_vttgen_ctrl2                         = 0x00000000,
+	.emc_pmacro_dsr_vttgen_ctrl0                     = 0x00000009,
+	.emc_pmacro_brick_ctrl_rfu1                      = 0x00000000,
+	.emc_pmacro_cmd_brick_ctrl_fdpd                  = 0x00000000,
+	.emc_pmacro_brick_ctrl_rfu2                      = 0x00000000,
+	.emc_pmacro_data_brick_ctrl_fdpd                 = 0x00000000,
+	.emc_pmacro_bg_bias_ctrl0                        = 0x00000000,
+	.emc_pmacro_data_pad_rx_ctrl                     = 0x05050003,
+	.emc_pmacro_cmd_pad_rx_ctrl                      = 0x05000000,
+	.emc_pmacro_data_rx_term_mode                    = 0x00000210,
+	.emc_pmacro_cmd_rx_term_mode                     = 0x00002000,
+	.emc_pmacro_data_pad_tx_ctrl                     = 0x00000421,
+	.emc_pmacro_cmd_pad_tx_ctrl                      = 0x00000000,
+
+	.emc_cfg3                                        = 0x00000040,
+
+	.emc_pmacro_tx_pwrd0                             = 0x10000000,
+	.emc_pmacro_tx_pwrd1                             = 0x00000000,
+	.emc_pmacro_tx_pwrd2                             = 0x00000000,
+	.emc_pmacro_tx_pwrd3                             = 0x00000000,
+	.emc_pmacro_tx_pwrd4                             = 0x00400080,
+	.emc_pmacro_tx_pwrd5                             = 0x00801004,
+
+	.emc_config_sample_delay                         = 0x00000020,
+
+	.emc_pmacro_brick_mapping0                       = 0x28091081,
+	.emc_pmacro_brick_mapping1                       = 0x44A53293,
+	.emc_pmacro_brick_mapping2                       = 0x76678A5B,
+
+	.emc_pmacro_tx_sel_clk_src0                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src1                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src2                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src3                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src4                      = 0x00000000,
+	.emc_pmacro_tx_sel_clk_src5                      = 0x00000000,
+
+	.emc_pmacro_perbit_fgcg_ctrl0                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl1                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl2                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl3                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl4                    = 0x00000000,
+	.emc_pmacro_perbit_fgcg_ctrl5                    = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl0                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl1                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl2                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl3                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl4                     = 0x00000000,
+	.emc_pmacro_perbit_rfu_ctrl5                     = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl0                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl1                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl2                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl3                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl4                    = 0x00000000,
+	.emc_pmacro_perbit_rfu1_ctrl5                    = 0x00000000,
+
+	.emc_pmacro_data_pi_ctrl                         = 0x00001010,
+	.emc_pmacro_cmd_pi_ctrl                          = 0x00001010,
+
+	.emc_pmacro_ddll_bypass                          = 0xEF00EF00,
+
+	.emc_pmacro_ddll_pwrd0                           = 0x00000000,
+	.emc_pmacro_ddll_pwrd1                           = 0x00000000,
+	.emc_pmacro_ddll_pwrd2                           = 0x1C1C1C1C,
+
+	.emc_pmacro_cmd_ctrl0                            = 0x00000000,
+	.emc_pmacro_cmd_ctrl1                            = 0x00000000,
+	.emc_pmacro_cmd_ctrl2                            = 0x00000000,
+
+	/* DRAM size information */
+	.mc_emem_adr_cfg                                 = 0x00000000, // 1 Rank.
+	.mc_emem_adr_cfg_dev0                            = 0x00080302, // Chip 0 Density 1024MB.
+	.mc_emem_adr_cfg_dev1                            = 0x00080302, // Chip 1 Density 1024MB.
+	.mc_emem_adr_cfg_channel_mask                    = 0xFFFF2400,
+	.mc_emem_adr_cfg_bank_mask0                      = 0x6E574400,
+	.mc_emem_adr_cfg_bank_mask1                      = 0x39722800,
+	.mc_emem_adr_cfg_bank_mask2                      = 0x4B9C1000,
+	/*
+	 * Specifies the value for MC_EMEM_CFG which holds the external memory
+	 * size (in MBytes)
+	 */
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.
+
+	/* MC arbitration configuration */
+	.mc_emem_arb_cfg                                 = 0x08000001,
+	.mc_emem_arb_outstanding_req                     = 0x8000004C,
+	.emc_emem_arb_refpb_hp_ctrl                      = 0x000A1020,
+	.emc_emem_arb_refpb_bank_ctrl                    = 0x80001028,
+
+	.mc_emem_arb_timing_rcd                          = 0x00000001,
+	.mc_emem_arb_timing_rp                           = 0x00000000,
+	.mc_emem_arb_timing_rc                           = 0x00000003,
+	.mc_emem_arb_timing_ras                          = 0x00000001,
+	.mc_emem_arb_timing_faw                          = 0x00000002,
+	.mc_emem_arb_timing_rrd                          = 0x00000001,
+	.mc_emem_arb_timing_rap2pre                      = 0x00000002,
+	.mc_emem_arb_timing_wap2pre                      = 0x00000005,
+	.mc_emem_arb_timing_r2r                          = 0x00000001,
+	.mc_emem_arb_timing_w2w                          = 0x00000001,
+	.mc_emem_arb_timing_r2w                          = 0x00000004,
+	.mc_emem_arb_timing_w2r                          = 0x00000005,
+	.mc_emem_arb_timing_rfcpb                        = 0x00000007,
+
+	.mc_emem_arb_da_turns                            = 0x02020000,
+	.mc_emem_arb_da_covers                           = 0x00030201,
+	.mc_emem_arb_misc0                               = 0x72A30504,
+	.mc_emem_arb_misc1                               = 0x70000F0F,
+	.mc_emem_arb_misc2                               = 0x00000000,
+
+	.mc_emem_arb_ring1_throttle                      = 0x001F0000,
+	.mc_emem_arb_override                            = 0x10000000,
+	.mc_emem_arb_override1                           = 0x00000000,
+	.mc_emem_arb_rsv                                 = 0xFF00FF00,
+
+	.mc_da_cfg0                                      = 0x00000001,
+	.mc_emem_arb_timing_ccdmw                        = 0x00000008,
+
+	.mc_clken_override                               = 0x00008000,
+
+	.mc_stat_control                                 = 0x00000000,
+	.mc_video_protect_bom                            = 0xFFF00000,
+	.mc_video_protect_bom_adr_hi                     = 0x00000000,
+	.mc_video_protect_size_mb                        = 0x00000000,
+
+	// Disable access:
+	//  AFI (PCIE), BPMP, HC (HOST1x), ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1 (WinT), SDMMC1/2/3. Plus TSEC, NVENC.
+	// Enable access:
+	//  DC, DCB, HDA, VIC.
+	.mc_video_protect_vpr_override                   = 0xE4FACB43, // Stock/Reset: 0xE4BAC343. HOS new: 0xE4FACB43. + TSEC, NVENC.
+	// Disable access:
+	//  SDMMC4, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR, SE2, SE2B. Plus TSECB, TSEC1, TSECB1.
+	// Enable access:
+	//  GPU, GPUB, NVDEC, NVJPG, NVDEC1.
+	.mc_video_protect_vpr_override1                  = 0x0600FED3, // Reset: 0x06001ED3. HOS new: 0x0600FED3. + TSECB, TSEC1, TSECB1.
+
+	// VPR CYA. L4T override (set PD, SCC, SKED, L1 as UNTRUSTED).
+	.mc_video_protect_gpu_override0                  = VPR_OVR0_CYA_TRUST_GCC(VPR_TRUST_GRAPHICS)    |
+													   VPR_OVR0_CYA_TRUST_RASTER(VPR_TRUST_GRAPHICS) |
+													   VPR_OVR0_CYA_TRUST_PE(VPR_TRUST_GRAPHICS)     |
+													   VPR_OVR0_CYA_TRUST_TEX(VPR_TRUST_GRAPHICS)    |
+													   VPR_OVR0_CYA_TRUST_OVERRIDE,                 // Stock: 0. HOS: VPR_OVR0_CYA_TRUST_DEFAULT.
+	.mc_video_protect_gpu_override1                  = VPR_OVR1_CYA_TRUST_PROP(VPR_TRUST_GRAPHICS), // Stock: 0. HOS: 0.
+
+	/* TZDRAM carveout configuration */
+	.mc_sec_carveout_bom                             = 0xFFF00000,
+	.mc_sec_carveout_adr_hi                          = 0x00000000,
+	.mc_sec_carveout_size_mb                         = 0x00000000,
+
+	.mc_video_protect_write_access                   = 0x00000000,
+	.mc_sec_carveout_protect_write_access            = 0x00000000,
+
+	.mc_generalized_carveout1_bom                    = 0x00000000,
+	.mc_generalized_carveout1_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout1_size_128kb             = 0x00000008,
+	.mc_generalized_carveout1_access0                = 0x00000000,
+	.mc_generalized_carveout1_access1                = 0x00000000,
+	.mc_generalized_carveout1_access2                = 0x00300000,
+	.mc_generalized_carveout1_access3                = 0x03000000,
+	.mc_generalized_carveout1_access4                = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout1_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout1_cfg0                   = 0x04000C76,
+
+	.mc_generalized_carveout2_bom                    = 0x00000000,
+	.mc_generalized_carveout2_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout2_size_128kb             = 0x00000002,
+	.mc_generalized_carveout2_access0                = 0x00000000,
+	.mc_generalized_carveout2_access1                = 0x00000000,
+	.mc_generalized_carveout2_access2                = 0x03000000,
+	.mc_generalized_carveout2_access3                = 0x00000000,
+	.mc_generalized_carveout2_access4                = 0x00000300,
+	.mc_generalized_carveout2_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout2_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout2_cfg0                   = 0x0440167E,
+
+	.mc_generalized_carveout3_bom                    = 0x00000000,
+	.mc_generalized_carveout3_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout3_size_128kb             = 0x00000000,
+	.mc_generalized_carveout3_access0                = 0x00000000,
+	.mc_generalized_carveout3_access1                = 0x00000000,
+	.mc_generalized_carveout3_access2                = 0x03000000,
+	.mc_generalized_carveout3_access3                = 0x00000000,
+	.mc_generalized_carveout3_access4                = 0x00000300,
+	.mc_generalized_carveout3_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout3_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout3_cfg0                   = 0x04401E7E,
+
+	.mc_generalized_carveout4_bom                    = 0x00000000,
+	.mc_generalized_carveout4_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout4_size_128kb             = 0x00000008,
+	.mc_generalized_carveout4_access0                = 0x00000000,
+	.mc_generalized_carveout4_access1                = 0x00000000,
+	.mc_generalized_carveout4_access2                = 0x00300000,
+	.mc_generalized_carveout4_access3                = 0x00000000,
+	.mc_generalized_carveout4_access4                = 0x000000C0,
+	.mc_generalized_carveout4_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout4_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout4_cfg0                   = 0x04002446,
+
+	.mc_generalized_carveout5_bom                    = 0x00000000,
+	.mc_generalized_carveout5_bom_hi                 = 0x00000000,
+	.mc_generalized_carveout5_size_128kb             = 0x00000008,
+	.mc_generalized_carveout5_access0                = 0x00000000,
+	.mc_generalized_carveout5_access1                = 0x00000000,
+	.mc_generalized_carveout5_access2                = 0x00300000,
+	.mc_generalized_carveout5_access3                = 0x00000000,
+	.mc_generalized_carveout5_access4                = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access0 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access1 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access2 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access3 = 0x00000000,
+	.mc_generalized_carveout5_force_internal_access4 = 0x00000000,
+	.mc_generalized_carveout5_cfg0                   = 0x04002C46,
+
+	/* Specifies enable for CA training */
+	.emc_ca_training_enable                          = 0x00000000,
+	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
+	.swizzle_rank_byte_encode                        = 0x000000EC,
+
+	/* Specifies enable and offset for patched boot rom write */
+	.boot_rom_patch_control                          = 0x00000000,
+	/* Specifies data for patched boot rom write */
+	.boot_rom_patch_data                             = 0x00000000,
+
+	.mc_mts_carveout_bom                             = 0xFFF00000,
+	.mc_mts_carveout_adr_hi                          = 0x00000000,
+	.mc_mts_carveout_size_mb                         = 0x00000000,
+	.mc_mts_carveout_reg_ctrl                        = 0x00000000,
+
+	/* Specifies the untranslated memory access control */
+	.mc_untranslated_region_check                    = 0x00000000,
+
+	/* Just a place holder for special usage when there is no BCT for certain registers */
+	.bct_na                                          = 0x00000000,
+};
+
+#define DRAM_CC_LPDDR4X_PMACRO_IB      (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ))
+
+#define DRAM_CC_LPDDR4X_PUPD_VPR       (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
+										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))
+
+#define DRAM_CC_LPDDR4X_DSR            (DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))
+
+#define DRAM_CC_LPDDR4X_QUSE           (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
+										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))
+
+#define DRAM_CC_LPDDR4X_FAW            (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB))
+
+#define DRAM_CC_LPDDR4X_VPR            (DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))
+
+#define DRAM_CC_LPDDR4X_8GB            (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL))
+
+#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210b01_t, m) / 4)
+static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {
+
+	// Samsung LPDDR4X 8GB K4UBE3D4AM-MGCJ Die-M for SDEV Iowa and Hoag.
+	{ 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_0)             },
+	{ 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_1)             },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_0) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_1) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_2) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_3) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_0) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_1) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_2) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_3) },
+
+	/*! Shared patched between DRAM Codes. */
+	{ 0x05500000, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(emc_auto_cal_config2)                },
+	{ 0xC9AFBCBC, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(emc_auto_cal_vref_sel0)              },
+
+	// Moved to default config.
+	// { 0x2A800000, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(mc_video_protect_gpu_override0)      },
+	// { 0x00000002, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(mc_video_protect_gpu_override1)      },
+
+	{ 0x88161414, DRAM_CC_LPDDR4X_DSR,       DCFG_OFFSET_OF(emc_mrw14)                           },
+	{ 0x80000713, DRAM_CC_LPDDR4X_DSR,       DCFG_OFFSET_OF(emc_dyn_self_ref_control)            },
+
+	{ 0x00000006, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_quse)                            },
+	{ 0x00000005, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_quse_width)                      },
+	{ 0x00000003, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_einput)                          },
+	{ 0x0000000C, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_einput_duration)                 },
+
+	{ 0x00000008, DRAM_CC_LPDDR4X_FAW,       DCFG_OFFSET_OF(emc_tfaw)                            },
+	{ 0x00000001, DRAM_CC_LPDDR4X_FAW,       DCFG_OFFSET_OF(mc_emem_arb_timing_faw)              },
+
+	// Moved to default config.
+	// { 0xE4FACB43, DRAM_CC_LPDDR4X_VPR,       DCFG_OFFSET_OF(mc_video_protect_vpr_override)       }, // + TSEC,  NVENC.
+	// { 0x0600FED3, DRAM_CC_LPDDR4X_VPR,       DCFG_OFFSET_OF(mc_video_protect_vpr_override1)      }, // + TSECB, TSEC1, TSECB1.
+
+	{ 0x00000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_adr_cfg)                         }, // 2 Ranks.
+	{ 0x08010004, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw1)                            },
+	{ 0x08020000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw2)                            },
+	{ 0x080D0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw3)                            },
+	{ 0x08033131, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw6)                            },
+	{ 0x080B0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw8)                            },
+	{ 0x0C0E5D5D, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw9)                            },
+	{ 0x080C5D5D, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw10)                           },
+	{ 0x0C0D0808, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw12)                           },
+	{ 0x0C0D0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw13)                           },
+	{ 0x08161414, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw14)                           },
+	{ 0x08010004, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw_extra)                       },
+	{ 0x00000000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_dev_select)                      }, // Both devices.
+	{ 0x0051004F, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_zcal_mrw_cmd)                    },
+	{ 0x40000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_zcal_init_dev1)                  },
+	{ 0x00000000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_pmacro_tx_pwrd4)                 },
+	{ 0x00001000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_pmacro_tx_pwrd5)                 },
+	{ 0x00000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_adr_cfg)                     }, // 2 Ranks.
+	{ 0x00002000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_cfg)                         }, // 8GB total density. Max 8GB.
+	{ 0x00000002, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_arb_timing_r2r)              },
+	{ 0x02020001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_arb_da_turns)                },
+};
+#undef DCFG_OFFSET_OF
--- a/bdk/mem/sdram_lp0.c
+++ b/bdk/mem/sdram_lp0.c
--- a/bdk/mem/sdram_lp0_param_t210.h
+++ b/bdk/mem/sdram_lp0_param_t210.h
@@ -1,964 +0,0 @@
-/*
- * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
- * Copyright 2014 Google Inc.
- * Copyright (c) 2018 CTCaer
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-/**
- * Defines the SDRAM parameter structure.
- *
- * Note that PLLM is used by EMC. The field names are in camel case to ease
- * directly converting BCT config files (*.cfg) into C structure.
- */
-
-#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
-#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
-
-#include <utils/types.h>
-
-enum
-{
-	/* Specifies the memory type to be undefined */
-	NvBootMemoryType_None = 0,
-
-	/* Specifies the memory type to be DDR SDRAM */
-	NvBootMemoryType_Ddr = 0,
-
-	/* Specifies the memory type to be LPDDR SDRAM */
-	NvBootMemoryType_LpDdr = 0,
-
-	/* Specifies the memory type to be DDR2 SDRAM */
-	NvBootMemoryType_Ddr2 = 0,
-
-	/* Specifies the memory type to be LPDDR2 SDRAM */
-	NvBootMemoryType_LpDdr2,
-
-	/* Specifies the memory type to be DDR3 SDRAM */
-	NvBootMemoryType_Ddr3,
-
-	/* Specifies the memory type to be LPDDR4 SDRAM */
-	NvBootMemoryType_LpDdr4,
-
-	NvBootMemoryType_Num,
-
-	/* Specifies an entry in the ram_code table that's not in use */
-	NvBootMemoryType_Unused = 0X7FFFFFF,
-};
-
-/**
- * Defines the SDRAM parameter structure
- */
-struct sdram_params
-{
-
-	/* Specifies the type of memory device */
-	u32 MemoryType;
-
-	/* MC/EMC clock source configuration */
-
-	/* Specifies the M value for PllM */
-	u32 PllMInputDivider;
-	/* Specifies the N value for PllM */
-	u32 PllMFeedbackDivider;
-	/* Specifies the time to wait for PLLM to lock (in microseconds) */
-	u32 PllMStableTime;
-	/* Specifies misc. control bits */
-	u32 PllMSetupControl;
-	/* Specifies the P value for PLLM */
-	u32 PllMPostDivider;
-	/* Specifies value for Charge Pump Gain Control */
-	u32 PllMKCP;
-	/* Specifies VCO gain */
-	u32 PllMKVCO;
-	/* Spare BCT param */
-	u32 EmcBctSpare0;
-	/* Spare BCT param */
-	u32 EmcBctSpare1;
-	/* Spare BCT param */
-	u32 EmcBctSpare2;
-	/* Spare BCT param */
-	u32 EmcBctSpare3;
-	/* Spare BCT param */
-	u32 EmcBctSpare4;
-	/* Spare BCT param */
-	u32 EmcBctSpare5;
-	/* Spare BCT param */
-	u32 EmcBctSpare6;
-	/* Spare BCT param */
-	u32 EmcBctSpare7;
-	/* Spare BCT param */
-	u32 EmcBctSpare8;
-	/* Spare BCT param */
-	u32 EmcBctSpare9;
-	/* Spare BCT param */
-	u32 EmcBctSpare10;
-	/* Spare BCT param */
-	u32 EmcBctSpare11;
-	/* Spare BCT param */
-	u32 EmcBctSpare12;
-	/* Spare BCT param */
-	u32 EmcBctSpare13;
-
-	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
-	u32 EmcClockSource;
-	u32 EmcClockSourceDll;
-
-	/* Defines possible override for PLLLM_MISC2 */
-	u32 ClkRstControllerPllmMisc2Override;
-	/* enables override for PLLLM_MISC2 */
-	u32 ClkRstControllerPllmMisc2OverrideEnable;
-	/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
-	u32 ClearClk2Mc1;
-
-	/* Auto-calibration of EMC pads */
-
-	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
-	u32 EmcAutoCalInterval;
-	/*
-	 * Specifies the value for EMC_AUTO_CAL_CONFIG
-	 * Note: Trigger bits are set by the SDRAM code.
-	 */
-	u32 EmcAutoCalConfig;
-
-	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
-	u32 EmcAutoCalConfig2;
-
-	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
-	u32 EmcAutoCalConfig3;
-
-	/* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */
-	u32 EmcAutoCalConfig4;
-	u32 EmcAutoCalConfig5;
-	u32 EmcAutoCalConfig6;
-	u32 EmcAutoCalConfig7;
-	u32 EmcAutoCalConfig8;
-
-	/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
-	u32 EmcAutoCalVrefSel0;
-	u32 EmcAutoCalVrefSel1;
-
-	/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
-	u32 EmcAutoCalChannel;
-
-	/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
-	u32 EmcPmacroAutocalCfg0;
-	u32 EmcPmacroAutocalCfg1;
-	u32 EmcPmacroAutocalCfg2;
-	u32 EmcPmacroRxTerm;
-	u32 EmcPmacroDqTxDrv;
-	u32 EmcPmacroCaTxDrv;
-	u32 EmcPmacroCmdTxDrv;
-	u32 EmcPmacroAutocalCfgCommon;
-	u32 EmcPmacroZctrl;
-
-	/*
-	 * Specifies the time for the calibration
-	 * to stabilize (in microseconds)
-	 */
-	u32 EmcAutoCalWait;
-
-	u32 EmcXm2CompPadCtrl;
-	u32 EmcXm2CompPadCtrl2;
-	u32 EmcXm2CompPadCtrl3;
-
-	/*
-	 * DRAM size information
-	 * Specifies the value for EMC_ADR_CFG
-	 */
-	u32 EmcAdrCfg;
-
-	/*
-	 * Specifies the time to wait after asserting pin
-	 * CKE (in microseconds)
-	 */
-	u32 EmcPinProgramWait;
-	/* Specifies the extra delay before/after pin RESET/CKE command */
-	u32 EmcPinExtraWait;
-
-	u32 EmcPinGpioEn;
-	u32 EmcPinGpio;
-
-	/*
-	 * Specifies the extra delay after the first writing
-	 * of EMC_TIMING_CONTROL
-	 */
-	u32 EmcTimingControlWait;
-
-	/* Timing parameters required for the SDRAM */
-
-	/* Specifies the value for EMC_RC */
-	u32 EmcRc;
-	/* Specifies the value for EMC_RFC */
-	u32 EmcRfc;
-	/* Specifies the value for EMC_RFC_PB */
-	u32 EmcRfcPb;
-	/* Specifies the value for EMC_RFC_CTRL2 */
-	u32 EmcRefctrl2;
-	/* Specifies the value for EMC_RFC_SLR */
-	u32 EmcRfcSlr;
-	/* Specifies the value for EMC_RAS */
-	u32 EmcRas;
-	/* Specifies the value for EMC_RP */
-	u32 EmcRp;
-	/* Specifies the value for EMC_R2R */
-	u32 EmcR2r;
-	/* Specifies the value for EMC_W2W */
-	u32 EmcW2w;
-	/* Specifies the value for EMC_R2W */
-	u32 EmcR2w;
-	/* Specifies the value for EMC_W2R */
-	u32 EmcW2r;
-	/* Specifies the value for EMC_R2P */
-	u32 EmcR2p;
-	/* Specifies the value for EMC_W2P */
-	u32 EmcW2p;
-
-	u32 EmcTppd;
-	u32 EmcCcdmw;
-
-	/* Specifies the value for EMC_RD_RCD */
-	u32 EmcRdRcd;
-	/* Specifies the value for EMC_WR_RCD */
-	u32 EmcWrRcd;
-	/* Specifies the value for EMC_RRD */
-	u32 EmcRrd;
-	/* Specifies the value for EMC_REXT */
-	u32 EmcRext;
-	/* Specifies the value for EMC_WEXT */
-	u32 EmcWext;
-	/* Specifies the value for EMC_WDV */
-	u32 EmcWdv;
-
-	u32 EmcWdvChk;
-	u32 EmcWsv;
-	u32 EmcWev;
-
-	/* Specifies the value for EMC_WDV_MASK */
-	u32 EmcWdvMask;
-
-	u32 EmcWsDuration;
-	u32 EmcWeDuration;
-
-	/* Specifies the value for EMC_QUSE */
-	u32 EmcQUse;
-	/* Specifies the value for EMC_QUSE_WIDTH */
-	u32 EmcQuseWidth;
-	/* Specifies the value for EMC_IBDLY */
-	u32 EmcIbdly;
-	/* Specifies the value for EMC_OBDLY */
-	u32 EmcObdly;
-	/* Specifies the value for EMC_EINPUT */
-	u32 EmcEInput;
-	/* Specifies the value for EMC_EINPUT_DURATION */
-	u32 EmcEInputDuration;
-	/* Specifies the value for EMC_PUTERM_EXTRA */
-	u32 EmcPutermExtra;
-	/* Specifies the value for EMC_PUTERM_WIDTH */
-	u32 EmcPutermWidth;
-	/* Specifies the value for EMC_PUTERM_ADJ */
-	////u32 EmcPutermAdj;
-
-	/* Specifies the value for EMC_QRST */
-	u32 EmcQRst;
-	/* Specifies the value for EMC_QSAFE */
-	u32 EmcQSafe;
-	/* Specifies the value for EMC_RDV */
-	u32 EmcRdv;
-	/* Specifies the value for EMC_RDV_MASK */
-	u32 EmcRdvMask;
-	/* Specifies the value for EMC_RDV_EARLY */
-	u32 EmcRdvEarly;
-	/* Specifies the value for EMC_RDV_EARLY_MASK */
-	u32 EmcRdvEarlyMask;
-	/* Specifies the value for EMC_QPOP */
-	u32 EmcQpop;
-
-	/* Specifies the value for EMC_REFRESH */
-	u32 EmcRefresh;
-	/* Specifies the value for EMC_BURST_REFRESH_NUM */
-	u32 EmcBurstRefreshNum;
-	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
-	u32 EmcPreRefreshReqCnt;
-	/* Specifies the value for EMC_PDEX2WR */
-	u32 EmcPdEx2Wr;
-	/* Specifies the value for EMC_PDEX2RD */
-	u32 EmcPdEx2Rd;
-	/* Specifies the value for EMC_PCHG2PDEN */
-	u32 EmcPChg2Pden;
-	/* Specifies the value for EMC_ACT2PDEN */
-	u32 EmcAct2Pden;
-	/* Specifies the value for EMC_AR2PDEN */
-	u32 EmcAr2Pden;
-	/* Specifies the value for EMC_RW2PDEN */
-	u32 EmcRw2Pden;
-	/* Specifies the value for EMC_CKE2PDEN */
-	u32 EmcCke2Pden;
-	/* Specifies the value for EMC_PDEX2CKE */
-	u32 EmcPdex2Cke;
-	/* Specifies the value for EMC_PDEX2MRR */
-	u32 EmcPdex2Mrr;
-	/* Specifies the value for EMC_TXSR */
-	u32 EmcTxsr;
-	/* Specifies the value for EMC_TXSRDLL */
-	u32 EmcTxsrDll;
-	/* Specifies the value for EMC_TCKE */
-	u32 EmcTcke;
-	/* Specifies the value for EMC_TCKESR */
-	u32 EmcTckesr;
-	/* Specifies the value for EMC_TPD */
-	u32 EmcTpd;
-	/* Specifies the value for EMC_TFAW */
-	u32 EmcTfaw;
-	/* Specifies the value for EMC_TRPAB */
-	u32 EmcTrpab;
-	/* Specifies the value for EMC_TCLKSTABLE */
-	u32 EmcTClkStable;
-	/* Specifies the value for EMC_TCLKSTOP */
-	u32 EmcTClkStop;
-	/* Specifies the value for EMC_TREFBW */
-	u32 EmcTRefBw;
-
-	/* FBIO configuration values */
-
-	/* Specifies the value for EMC_FBIO_CFG5 */
-	u32 EmcFbioCfg5;
-	/* Specifies the value for EMC_FBIO_CFG7 */
-	u32 EmcFbioCfg7;
-	/* Specifies the value for EMC_FBIO_CFG8 */
-	u32 EmcFbioCfg8;
-
-	/* Command mapping for CMD brick 0 */
-	u32 EmcCmdMappingCmd0_0;
-	u32 EmcCmdMappingCmd0_1;
-	u32 EmcCmdMappingCmd0_2;
-	u32 EmcCmdMappingCmd1_0;
-	u32 EmcCmdMappingCmd1_1;
-	u32 EmcCmdMappingCmd1_2;
-	u32 EmcCmdMappingCmd2_0;
-	u32 EmcCmdMappingCmd2_1;
-	u32 EmcCmdMappingCmd2_2;
-	u32 EmcCmdMappingCmd3_0;
-	u32 EmcCmdMappingCmd3_1;
-	u32 EmcCmdMappingCmd3_2;
-	u32 EmcCmdMappingByte;
-
-	/* Specifies the value for EMC_FBIO_SPARE */
-	u32 EmcFbioSpare;
-
-	/* Specifies the value for EMC_CFG_RSV */
-	u32 EmcCfgRsv;
-
-	/* MRS command values */
-
-	/* Specifies the value for EMC_MRS */
-	u32 EmcMrs;
-	/* Specifies the MP0 command to initialize mode registers */
-	u32 EmcEmrs;
-	/* Specifies the MP2 command to initialize mode registers */
-	u32 EmcEmrs2;
-	/* Specifies the MP3 command to initialize mode registers */
-	u32 EmcEmrs3;
-	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
-	u32 EmcMrw1;
-	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
-	u32 EmcMrw2;
-	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
-	u32 EmcMrw3;
-	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
-	u32 EmcMrw4;
-	/* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */
-	u32 EmcMrw6;
-	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
-	u32 EmcMrw8;
-	/* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */
-	u32 EmcMrw9;
-	/* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */
-	u32 EmcMrw10;
-	/* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */
-	u32 EmcMrw12;
-	/* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */
-	u32 EmcMrw13;
-	/* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */
-	u32 EmcMrw14;
-	/*
-	 * Specifies the programming to extra LPDDR2 Mode Register
-	 * at cold boot
-	 */
-	u32 EmcMrwExtra;
-	/*
-	 * Specifies the programming to extra LPDDR2 Mode Register
-	 * at warm boot
-	 */
-	u32 EmcWarmBootMrwExtra;
-	/*
-	 * Specify the enable of extra Mode Register programming at
-	 * warm boot
-	 */
-	u32 EmcWarmBootExtraModeRegWriteEnable;
-	/*
-	 * Specify the enable of extra Mode Register programming at
-	 * cold boot
-	 */
-	u32 EmcExtraModeRegWriteEnable;
-
-	/* Specifies the EMC_MRW reset command value */
-	u32 EmcMrwResetCommand;
-	/* Specifies the EMC Reset wait time (in microseconds) */
-	u32 EmcMrwResetNInitWait;
-	/* Specifies the value for EMC_MRS_WAIT_CNT */
-	u32 EmcMrsWaitCnt;
-	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
-	u32 EmcMrsWaitCnt2;
-
-	/* EMC miscellaneous configurations */
-
-	/* Specifies the value for EMC_CFG */
-	u32 EmcCfg;
-	/* Specifies the value for EMC_CFG_2 */
-	u32 EmcCfg2;
-	/* Specifies the pipe bypass controls */
-	u32 EmcCfgPipe;
-	u32 EmcCfgPipeClk;
-	u32 EmcFdpdCtrlCmdNoRamp;
-	u32 EmcCfgUpdate;
-
-	/* Specifies the value for EMC_DBG */
-	u32 EmcDbg;
-	u32 EmcDbgWriteMux;
-
-	/* Specifies the value for EMC_CMDQ */
-	u32 EmcCmdQ;
-	/* Specifies the value for EMC_MC2EMCQ */
-	u32 EmcMc2EmcQ;
-	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
-	u32 EmcDynSelfRefControl;
-
-	/* Specifies the value for MEM_INIT_DONE */
-	u32 AhbArbitrationXbarCtrlMemInitDone;
-
-	/* Specifies the value for EMC_CFG_DIG_DLL */
-	u32 EmcCfgDigDll;
-	u32 EmcCfgDigDll_1;
-	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
-	u32 EmcCfgDigDllPeriod;
-	/* Specifies the value of *DEV_SELECTN of various EMC registers */
-	u32 EmcDevSelect;
-
-	/* Specifies the value for EMC_SEL_DPD_CTRL */
-	u32 EmcSelDpdCtrl;
-
-	/* Pads trimmer delays */
-	u32 EmcFdpdCtrlDq;
-	u32 EmcFdpdCtrlCmd;
-	u32 EmcPmacroIbVrefDq_0;
-	u32 EmcPmacroIbVrefDq_1;
-	u32 EmcPmacroIbVrefDqs_0;
-	u32 EmcPmacroIbVrefDqs_1;
-	u32 EmcPmacroIbRxrt;
-	u32 EmcCfgPipe1;
-	u32 EmcCfgPipe2;
-
-	/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
-	u32 EmcPmacroQuseDdllRank0_0;
-	u32 EmcPmacroQuseDdllRank0_1;
-	u32 EmcPmacroQuseDdllRank0_2;
-	u32 EmcPmacroQuseDdllRank0_3;
-	u32 EmcPmacroQuseDdllRank0_4;
-	u32 EmcPmacroQuseDdllRank0_5;
-	u32 EmcPmacroQuseDdllRank1_0;
-	u32 EmcPmacroQuseDdllRank1_1;
-	u32 EmcPmacroQuseDdllRank1_2;
-	u32 EmcPmacroQuseDdllRank1_3;
-	u32 EmcPmacroQuseDdllRank1_4;
-	u32 EmcPmacroQuseDdllRank1_5;
-
-	u32 EmcPmacroObDdllLongDqRank0_0;
-	u32 EmcPmacroObDdllLongDqRank0_1;
-	u32 EmcPmacroObDdllLongDqRank0_2;
-	u32 EmcPmacroObDdllLongDqRank0_3;
-	u32 EmcPmacroObDdllLongDqRank0_4;
-	u32 EmcPmacroObDdllLongDqRank0_5;
-	u32 EmcPmacroObDdllLongDqRank1_0;
-	u32 EmcPmacroObDdllLongDqRank1_1;
-	u32 EmcPmacroObDdllLongDqRank1_2;
-	u32 EmcPmacroObDdllLongDqRank1_3;
-	u32 EmcPmacroObDdllLongDqRank1_4;
-	u32 EmcPmacroObDdllLongDqRank1_5;
-
-	u32 EmcPmacroObDdllLongDqsRank0_0;
-	u32 EmcPmacroObDdllLongDqsRank0_1;
-	u32 EmcPmacroObDdllLongDqsRank0_2;
-	u32 EmcPmacroObDdllLongDqsRank0_3;
-	u32 EmcPmacroObDdllLongDqsRank0_4;
-	u32 EmcPmacroObDdllLongDqsRank0_5;
-	u32 EmcPmacroObDdllLongDqsRank1_0;
-	u32 EmcPmacroObDdllLongDqsRank1_1;
-	u32 EmcPmacroObDdllLongDqsRank1_2;
-	u32 EmcPmacroObDdllLongDqsRank1_3;
-	u32 EmcPmacroObDdllLongDqsRank1_4;
-	u32 EmcPmacroObDdllLongDqsRank1_5;
-
-	u32 EmcPmacroIbDdllLongDqsRank0_0;
-	u32 EmcPmacroIbDdllLongDqsRank0_1;
-	u32 EmcPmacroIbDdllLongDqsRank0_2;
-	u32 EmcPmacroIbDdllLongDqsRank0_3;
-	u32 EmcPmacroIbDdllLongDqsRank1_0;
-	u32 EmcPmacroIbDdllLongDqsRank1_1;
-	u32 EmcPmacroIbDdllLongDqsRank1_2;
-	u32 EmcPmacroIbDdllLongDqsRank1_3;
-
-	u32 EmcPmacroDdllLongCmd_0;
-	u32 EmcPmacroDdllLongCmd_1;
-	u32 EmcPmacroDdllLongCmd_2;
-	u32 EmcPmacroDdllLongCmd_3;
-	u32 EmcPmacroDdllLongCmd_4;
-	u32 EmcPmacroDdllShortCmd_0;
-	u32 EmcPmacroDdllShortCmd_1;
-	u32 EmcPmacroDdllShortCmd_2;
-
-	/*
-	 * Specifies the delay after asserting CKE pin during a WarmBoot0
-	 * sequence (in microseconds)
-	 */
-	u32 WarmBootWait;
-
-	/* Specifies the value for EMC_ODT_WRITE */
-	u32 EmcOdtWrite;
-
-	/* Periodic ZQ calibration */
-
-	/*
-	 * Specifies the value for EMC_ZCAL_INTERVAL
-	 * Value 0 disables ZQ calibration
-	 */
-	u32 EmcZcalInterval;
-	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
-	u32 EmcZcalWaitCnt;
-	/* Specifies the value for EMC_ZCAL_MRW_CMD */
-	u32 EmcZcalMrwCmd;
-
-	/* DRAM initialization sequence flow control */
-
-	/* Specifies the MRS command value for resetting DLL */
-	u32 EmcMrsResetDll;
-	/* Specifies the command for ZQ initialization of device 0 */
-	u32 EmcZcalInitDev0;
-	/* Specifies the command for ZQ initialization of device 1 */
-	u32 EmcZcalInitDev1;
-	/*
-	 * Specifies the wait time after programming a ZQ initialization
-	 * command (in microseconds)
-	 */
-	u32 EmcZcalInitWait;
-	/*
-	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
-	 * and warm boot [bit 1]
-	 */
-	u32 EmcZcalWarmColdBootEnables;
-
-	/*
-	 * Specifies the MRW command to LPDDR2 for ZQ calibration
-	 * on warmboot
-	 */
-	/* Is issued to both devices separately */
-	u32 EmcMrwLpddr2ZcalWarmBoot;
-	/*
-	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
-	 * Is issued to both devices separately
-	 */
-	u32 EmcZqCalDdr3WarmBoot;
-	u32 EmcZqCalLpDdr4WarmBoot;
-	/*
-	 * Specifies the wait time for ZQ calibration on warmboot
-	 * (in microseconds)
-	 */
-	u32 EmcZcalWarmBootWait;
-	/*
-	 * Specifies the enable for DRAM Mode Register programming
-	 * at warm boot
-	 */
-	u32 EmcMrsWarmBootEnable;
-	/*
-	 * Specifies the wait time after sending an MRS DLL reset command
-	 * in microseconds)
-	 */
-	u32 EmcMrsResetDllWait;
-	/* Specifies the extra MRS command to initialize mode registers */
-	u32 EmcMrsExtra;
-	/* Specifies the extra MRS command at warm boot */
-	u32 EmcWarmBootMrsExtra;
-	/* Specifies the EMRS command to enable the DDR2 DLL */
-	u32 EmcEmrsDdr2DllEnable;
-	/* Specifies the MRS command to reset the DDR2 DLL */
-	u32 EmcMrsDdr2DllReset;
-	/* Specifies the EMRS command to set OCD calibration */
-	u32 EmcEmrsDdr2OcdCalib;
-	/*
-	 * Specifies the wait between initializing DDR and setting OCD
-	 * calibration (in microseconds)
-	 */
-	u32 EmcDdr2Wait;
-	/* Specifies the value for EMC_CLKEN_OVERRIDE */
-	u32 EmcClkenOverride;
-
-	/*
-	 * Specifies LOG2 of the extra refresh numbers after booting
-	 * Program 0 to disable
-	 */
-	u32 EmcExtraRefreshNum;
-	/* Specifies the master override for all EMC clocks */
-	u32 EmcClkenOverrideAllWarmBoot;
-	/* Specifies the master override for all MC clocks */
-	u32 McClkenOverrideAllWarmBoot;
-	/* Specifies digital dll period, choosing between 4 to 64 ms */
-	u32 EmcCfgDigDllPeriodWarmBoot;
-
-	/* Pad controls */
-
-	/* Specifies the value for PMC_VDDP_SEL */
-	u32 PmcVddpSel;
-	/* Specifies the wait time after programming PMC_VDDP_SEL */
-	u32 PmcVddpSelWait;
-	/* Specifies the value for PMC_DDR_PWR */
-	u32 PmcDdrPwr;
-	/* Specifies the value for PMC_DDR_CFG */
-	u32 PmcDdrCfg;
-	/* Specifies the value for PMC_IO_DPD3_REQ */
-	u32 PmcIoDpd3Req;
-	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
-	u32 PmcIoDpd3ReqWait;
-	u32 PmcIoDpd4ReqWait;
-
-	/* Specifies the value for PMC_REG_SHORT */
-	u32 PmcRegShort;
-	/* Specifies the value for PMC_NO_IOPOWER */
-	u32 PmcNoIoPower;
-
-	u32 PmcDdrCntrlWait;
-	u32 PmcDdrCntrl;
-
-	/* Specifies the value for EMC_ACPD_CONTROL */
-	u32 EmcAcpdControl;
-
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
-	////u32 EmcSwizzleRank0ByteCfg;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
-	u32 EmcSwizzleRank0Byte0;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
-	u32 EmcSwizzleRank0Byte1;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
-	u32 EmcSwizzleRank0Byte2;
-	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
-	u32 EmcSwizzleRank0Byte3;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
-	////u32 EmcSwizzleRank1ByteCfg;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
-	u32 EmcSwizzleRank1Byte0;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
-	u32 EmcSwizzleRank1Byte1;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
-	u32 EmcSwizzleRank1Byte2;
-	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
-	u32 EmcSwizzleRank1Byte3;
-
-	/* Specifies the value for EMC_TXDSRVTTGEN */
-	u32 EmcTxdsrvttgen;
-
-	/* Specifies the value for EMC_DATA_BRLSHFT_0 */
-	u32 EmcDataBrlshft0;
-	u32 EmcDataBrlshft1;
-
-	u32 EmcDqsBrlshft0;
-	u32 EmcDqsBrlshft1;
-
-	u32 EmcCmdBrlshft0;
-	u32 EmcCmdBrlshft1;
-	u32 EmcCmdBrlshft2;
-	u32 EmcCmdBrlshft3;
-
-	u32 EmcQuseBrlshft0;
-	u32 EmcQuseBrlshft1;
-	u32 EmcQuseBrlshft2;
-	u32 EmcQuseBrlshft3;
-
-	u32 EmcDllCfg0;
-	u32 EmcDllCfg1;
-
-	u32 EmcPmcScratch1;
-	u32 EmcPmcScratch2;
-	u32 EmcPmcScratch3;
-
-	u32 EmcPmacroPadCfgCtrl;
-
-	u32 EmcPmacroVttgenCtrl0;
-	u32 EmcPmacroVttgenCtrl1;
-	u32 EmcPmacroVttgenCtrl2;
-
-	u32 EmcPmacroBrickCtrlRfu1;
-	u32 EmcPmacroCmdBrickCtrlFdpd;
-	u32 EmcPmacroBrickCtrlRfu2;
-	u32 EmcPmacroDataBrickCtrlFdpd;
-	u32 EmcPmacroBgBiasCtrl0;
-	u32 EmcPmacroDataPadRxCtrl;
-	u32 EmcPmacroCmdPadRxCtrl;
-	u32 EmcPmacroDataRxTermMode;
-	u32 EmcPmacroCmdRxTermMode;
-	u32 EmcPmacroDataPadTxCtrl;
-	u32 EmcPmacroCommonPadTxCtrl;
-	u32 EmcPmacroCmdPadTxCtrl;
-	u32 EmcCfg3;
-
-	u32 EmcPmacroTxPwrd0;
-	u32 EmcPmacroTxPwrd1;
-	u32 EmcPmacroTxPwrd2;
-	u32 EmcPmacroTxPwrd3;
-	u32 EmcPmacroTxPwrd4;
-	u32 EmcPmacroTxPwrd5;
-
-	u32 EmcConfigSampleDelay;
-
-	u32 EmcPmacroBrickMapping0;
-	u32 EmcPmacroBrickMapping1;
-	u32 EmcPmacroBrickMapping2;
-
-	u32 EmcPmacroTxSelClkSrc0;
-	u32 EmcPmacroTxSelClkSrc1;
-	u32 EmcPmacroTxSelClkSrc2;
-	u32 EmcPmacroTxSelClkSrc3;
-	u32 EmcPmacroTxSelClkSrc4;
-	u32 EmcPmacroTxSelClkSrc5;
-
-	u32 EmcPmacroDdllBypass;
-
-	u32 EmcPmacroDdllPwrd0;
-	u32 EmcPmacroDdllPwrd1;
-	u32 EmcPmacroDdllPwrd2;
-
-	u32 EmcPmacroCmdCtrl0;
-	u32 EmcPmacroCmdCtrl1;
-	u32 EmcPmacroCmdCtrl2;
-
-	/* DRAM size information */
-
-	/* Specifies the value for MC_EMEM_ADR_CFG */
-	u32 McEmemAdrCfg;
-	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
-	u32 McEmemAdrCfgDev0;
-	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
-	u32 McEmemAdrCfgDev1;
-	u32 McEmemAdrCfgChannelMask;
-
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */
-	u32 McEmemAdrCfgBankMask0;
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
-	u32 McEmemAdrCfgBankMask1;
-	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
-	u32 McEmemAdrCfgBankMask2;
-
-	/*
-	 * Specifies the value for MC_EMEM_CFG which holds the external memory
-	 * size (in KBytes)
-	 */
-	u32 McEmemCfg;
-
-	/* MC arbitration configuration */
-
-	/* Specifies the value for MC_EMEM_ARB_CFG */
-	u32 McEmemArbCfg;
-	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
-	u32 McEmemArbOutstandingReq;
-
-	u32 McEmemArbRefpbHpCtrl;
-	u32 McEmemArbRefpbBankCtrl;
-
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
-	u32 McEmemArbTimingRcd;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
-	u32 McEmemArbTimingRp;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
-	u32 McEmemArbTimingRc;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
-	u32 McEmemArbTimingRas;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
-	u32 McEmemArbTimingFaw;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
-	u32 McEmemArbTimingRrd;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
-	u32 McEmemArbTimingRap2Pre;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
-	u32 McEmemArbTimingWap2Pre;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
-	u32 McEmemArbTimingR2R;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
-	u32 McEmemArbTimingW2W;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
-	u32 McEmemArbTimingR2W;
-	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
-	u32 McEmemArbTimingW2R;
-
-	u32 McEmemArbTimingRFCPB;
-
-	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
-	u32 McEmemArbDaTurns;
-	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
-	u32 McEmemArbDaCovers;
-	/* Specifies the value for MC_EMEM_ARB_MISC0 */
-	u32 McEmemArbMisc0;
-	/* Specifies the value for MC_EMEM_ARB_MISC1 */
-	u32 McEmemArbMisc1;
-	u32 McEmemArbMisc2;
-
-	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
-	u32 McEmemArbRing1Throttle;
-	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
-	u32 McEmemArbOverride;
-	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
-	u32 McEmemArbOverride1;
-	/* Specifies the value for MC_EMEM_ARB_RSV */
-	u32 McEmemArbRsv;
-
-	u32 McDaCfg0;
-	u32 McEmemArbTimingCcdmw;
-
-	/* Specifies the value for MC_CLKEN_OVERRIDE */
-	u32 McClkenOverride;
-
-	/* Specifies the value for MC_STAT_CONTROL */
-	u32 McStatControl;
-
-	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
-	u32 McVideoProtectBom;
-	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
-	u32 McVideoProtectBomAdrHi;
-	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
-	u32 McVideoProtectSizeMb;
-	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
-	u32 McVideoProtectVprOverride;
-	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
-	u32 McVideoProtectVprOverride1;
-	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
-	u32 McVideoProtectGpuOverride0;
-	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
-	u32 McVideoProtectGpuOverride1;
-	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
-	u32 McSecCarveoutBom;
-	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
-	u32 McSecCarveoutAdrHi;
-	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
-	u32 McSecCarveoutSizeMb;
-	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
-	   VIDEO_PROTECT_WRITEAccess */
-	u32 McVideoProtectWriteAccess;
-	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
-	   SEC_CARVEOUT_WRITEAccess */
-	u32 McSecCarveoutProtectWriteAccess;
-
-	/* Write-Protect Regions (WPR) */
-	u32 McGeneralizedCarveout1Bom;
-	u32 McGeneralizedCarveout1BomHi;
-	u32 McGeneralizedCarveout1Size128kb;
-	u32 McGeneralizedCarveout1Access0;
-	u32 McGeneralizedCarveout1Access1;
-	u32 McGeneralizedCarveout1Access2;
-	u32 McGeneralizedCarveout1Access3;
-	u32 McGeneralizedCarveout1Access4;
-	u32 McGeneralizedCarveout1ForceInternalAccess0;
-	u32 McGeneralizedCarveout1ForceInternalAccess1;
-	u32 McGeneralizedCarveout1ForceInternalAccess2;
-	u32 McGeneralizedCarveout1ForceInternalAccess3;
-	u32 McGeneralizedCarveout1ForceInternalAccess4;
-	u32 McGeneralizedCarveout1Cfg0;
-
-	u32 McGeneralizedCarveout2Bom;
-	u32 McGeneralizedCarveout2BomHi;
-	u32 McGeneralizedCarveout2Size128kb;
-	u32 McGeneralizedCarveout2Access0;
-	u32 McGeneralizedCarveout2Access1;
-	u32 McGeneralizedCarveout2Access2;
-	u32 McGeneralizedCarveout2Access3;
-	u32 McGeneralizedCarveout2Access4;
-	u32 McGeneralizedCarveout2ForceInternalAccess0;
-	u32 McGeneralizedCarveout2ForceInternalAccess1;
-	u32 McGeneralizedCarveout2ForceInternalAccess2;
-	u32 McGeneralizedCarveout2ForceInternalAccess3;
-	u32 McGeneralizedCarveout2ForceInternalAccess4;
-	u32 McGeneralizedCarveout2Cfg0;
-
-	u32 McGeneralizedCarveout3Bom;
-	u32 McGeneralizedCarveout3BomHi;
-	u32 McGeneralizedCarveout3Size128kb;
-	u32 McGeneralizedCarveout3Access0;
-	u32 McGeneralizedCarveout3Access1;
-	u32 McGeneralizedCarveout3Access2;
-	u32 McGeneralizedCarveout3Access3;
-	u32 McGeneralizedCarveout3Access4;
-	u32 McGeneralizedCarveout3ForceInternalAccess0;
-	u32 McGeneralizedCarveout3ForceInternalAccess1;
-	u32 McGeneralizedCarveout3ForceInternalAccess2;
-	u32 McGeneralizedCarveout3ForceInternalAccess3;
-	u32 McGeneralizedCarveout3ForceInternalAccess4;
-	u32 McGeneralizedCarveout3Cfg0;
-
-	u32 McGeneralizedCarveout4Bom;
-	u32 McGeneralizedCarveout4BomHi;
-	u32 McGeneralizedCarveout4Size128kb;
-	u32 McGeneralizedCarveout4Access0;
-	u32 McGeneralizedCarveout4Access1;
-	u32 McGeneralizedCarveout4Access2;
-	u32 McGeneralizedCarveout4Access3;
-	u32 McGeneralizedCarveout4Access4;
-	u32 McGeneralizedCarveout4ForceInternalAccess0;
-	u32 McGeneralizedCarveout4ForceInternalAccess1;
-	u32 McGeneralizedCarveout4ForceInternalAccess2;
-	u32 McGeneralizedCarveout4ForceInternalAccess3;
-	u32 McGeneralizedCarveout4ForceInternalAccess4;
-	u32 McGeneralizedCarveout4Cfg0;
-
-	u32 McGeneralizedCarveout5Bom;
-	u32 McGeneralizedCarveout5BomHi;
-	u32 McGeneralizedCarveout5Size128kb;
-	u32 McGeneralizedCarveout5Access0;
-	u32 McGeneralizedCarveout5Access1;
-	u32 McGeneralizedCarveout5Access2;
-	u32 McGeneralizedCarveout5Access3;
-	u32 McGeneralizedCarveout5Access4;
-	u32 McGeneralizedCarveout5ForceInternalAccess0;
-	u32 McGeneralizedCarveout5ForceInternalAccess1;
-	u32 McGeneralizedCarveout5ForceInternalAccess2;
-	u32 McGeneralizedCarveout5ForceInternalAccess3;
-	u32 McGeneralizedCarveout5ForceInternalAccess4;
-	u32 McGeneralizedCarveout5Cfg0;
-
-	/* Specifies enable for CA training */
-	u32 EmcCaTrainingEnable;
-
-	/* Set if bit 6 select is greater than bit 7 select; uses aremc.
-	   spec packet SWIZZLE_BIT6_GT_BIT7 */
-	u32 SwizzleRankByteEncode;
-	/* Specifies enable and offset for patched boot ROM write */
-	u32 BootRomPatchControl;
-	/* Specifies data for patched boot ROM write */
-	u32 BootRomPatchData;
-
-	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
-	u32 McMtsCarveoutBom;
-	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
-	u32 McMtsCarveoutAdrHi;
-	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
-	u32 McMtsCarveoutSizeMb;
-	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
-	u32 McMtsCarveoutRegCtrl;
-
-	/* End */
-};
-
-#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */
--- a/bdk/mem/sdram_param_t210.h
+++ b/bdk/mem/sdram_param_t210.h
@@ -37,7 +37,7 @@
 /**
 * Defines the SDRAM parameter structure
 */
-typedef struct _sdram_params
+typedef struct _sdram_params_t210_t
 {
 	/* Specifies the type of memory device */
 	u32 memory_type;
@@ -925,6 +925,6 @@ typedef struct _sdram_params
 	u32 mc_mts_carveout_size_mb;
 	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
 	u32 mc_mts_carveout_reg_ctrl;
-} sdram_params_t;
+} sdram_params_t210_t;

 #endif
--- a/bdk/mem/sdram_param_t210b01.h
+++ b/bdk/mem/sdram_param_t210b01.h
@@ -0,0 +1,989 @@
+/*
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _SDRAM_PARAM_T210B01_H_
+#define _SDRAM_PARAM_T210B01_H_
+
+typedef struct _sdram_params_t210b01_t
+{
+	/* Specifies the type of memory device */
+	u32 memory_type;
+
+	/* MC/EMC clock source configuration */
+
+	/* Specifies the M value for PllM */
+	u32 pllm_input_divider;
+	/* Specifies the N value for PllM */
+	u32 pllm_feedback_divider;
+	/* Specifies the time to wait for PLLM to lock (in microseconds) */
+	u32 pllm_stable_time;
+	/* Specifies misc. control bits */
+	u32 pllm_setup_control;
+	/* Specifies the P value for PLLM */
+	u32 pllm_post_divider;
+	/* Specifies value for Charge Pump Gain Control */
+	u32 pllm_kcp;
+	/* Specifies VCO gain */
+	u32 pllm_kvco;
+	/* Spare BCT param */
+	u32 emc_bct_spare0;
+	/* Spare BCT param */
+	u32 emc_bct_spare1;
+	/* Spare BCT param */
+	u32 emc_bct_spare2;
+	/* Spare BCT param */
+	u32 emc_bct_spare3;
+	/* Spare BCT param */
+	u32 emc_bct_spare4;
+	/* Spare BCT param */
+	u32 emc_bct_spare5;
+	/* Spare BCT param */
+	u32 emc_bct_spare6;
+	/* Spare BCT param */
+	u32 emc_bct_spare7;
+	/* Spare BCT param */
+	u32 emc_bct_spare8;
+	/* Spare BCT param */
+	u32 emc_bct_spare9;
+	/* Spare BCT param */
+	u32 emc_bct_spare10;
+	/* Spare BCT param */
+	u32 emc_bct_spare11;
+	/* Spare BCT param */
+	u32 emc_bct_spare12;
+	/* Spare BCT param */
+	u32 emc_bct_spare13;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure0;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure1;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure2;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure3;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure4;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure5;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure6;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure7;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure8;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure9;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure10;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure11;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure12;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure13;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure14;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure15;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure16;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure17;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure18;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure19;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure20;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure21;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure22;
+	/* Spare BCT param */
+	u32 emc_bct_spare_secure23;
+
+	/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
+	u32 emc_clock_source;
+	u32 emc_clock_source_dll;
+
+	/* Defines possible override for PLLLM_MISC2 */
+	u32 clk_rst_pllm_misc20_override;
+	/* enables override for PLLLM_MISC2 */
+	u32 clk_rst_pllm_misc20_override_enable;
+	/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
+	u32 clear_clock2_mc1;
+
+	/* Auto-calibration of EMC pads */
+
+	/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
+	u32 emc_auto_cal_interval;
+	/*
+	 * Specifies the value for EMC_AUTO_CAL_CONFIG
+	 * Note: Trigger bits are set by the SDRAM code.
+	 */
+	u32 emc_auto_cal_config;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
+	u32 emc_auto_cal_config2;
+
+	/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
+	u32 emc_auto_cal_config3;
+	u32 emc_auto_cal_config4;
+	u32 emc_auto_cal_config5;
+	u32 emc_auto_cal_config6;
+	u32 emc_auto_cal_config7;
+	u32 emc_auto_cal_config8;
+	u32 emc_auto_cal_config9;
+
+	/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
+	u32 emc_auto_cal_vref_sel0;
+	u32 emc_auto_cal_vref_sel1;
+
+	/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
+	u32 emc_auto_cal_channel;
+
+	/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
+	u32 emc_pmacro_auto_cal_cfg0;
+	u32 emc_pmacro_auto_cal_cfg1;
+	u32 emc_pmacro_auto_cal_cfg2;
+
+	u32 emc_pmacro_rx_term;
+	u32 emc_pmacro_dq_tx_drive;
+	u32 emc_pmacro_ca_tx_drive;
+	u32 emc_pmacro_cmd_tx_drive;
+	u32 emc_pmacro_auto_cal_common;
+	u32 emc_pmacro_zcrtl;
+
+	/*
+	 * Specifies the time for the calibration
+	 * to stabilize (in microseconds)
+	 */
+	u32 emc_auto_cal_wait;
+
+	u32 emc_xm2_comp_pad_ctrl;
+	u32 emc_xm2_comp_pad_ctrl2;
+	u32 emc_xm2_comp_pad_ctrl3;
+
+	/*
+	 * DRAM size information
+	 * Specifies the value for EMC_ADR_CFG
+	 */
+	u32 emc_adr_cfg;
+
+	/*
+	 * Specifies the time to wait after asserting pin
+	 * CKE (in microseconds)
+	 */
+	u32 emc_pin_program_wait;
+	/* Specifies the extra delay before/after pin RESET/CKE command */
+	u32 emc_pin_extra_wait;
+
+	u32 emc_pin_gpio_enable;
+	u32 emc_pin_gpio;
+
+	/*
+	 * Specifies the extra delay after the first writing
+	 * of EMC_TIMING_CONTROL
+	 */
+	u32 emc_timing_control_wait;
+
+	/* Timing parameters required for the SDRAM */
+
+	/* Specifies the value for EMC_RC */
+	u32 emc_rc;
+	/* Specifies the value for EMC_RFC */
+	u32 emc_rfc;
+
+	u32 emc_rfc_pb;
+	u32 emc_ref_ctrl2;
+
+	/* Specifies the value for EMC_RFC_SLR */
+	u32 emc_rfc_slr;
+	/* Specifies the value for EMC_RAS */
+	u32 emc_ras;
+	/* Specifies the value for EMC_RP */
+	u32 emc_rp;
+	/* Specifies the value for EMC_R2R */
+	u32 emc_r2r;
+	/* Specifies the value for EMC_W2W */
+	u32 emc_w2w;
+	/* Specifies the value for EMC_R2W */
+	u32 emc_r2w;
+	/* Specifies the value for EMC_W2R */
+	u32 emc_w2r;
+	/* Specifies the value for EMC_R2P */
+	u32 emc_r2p;
+	/* Specifies the value for EMC_W2P */
+	u32 emc_w2p;
+
+	u32 emc_tppd;
+	u32 emc_trtm;
+	u32 emc_twtm;
+	u32 emc_tratm;
+	u32 emc_twatm;
+	u32 emc_tr2ref;
+	u32 emc_ccdmw;
+
+	/* Specifies the value for EMC_RD_RCD */
+	u32 emc_rd_rcd;
+	/* Specifies the value for EMC_WR_RCD */
+	u32 emc_wr_rcd;
+	/* Specifies the value for EMC_RRD */
+	u32 emc_rrd;
+	/* Specifies the value for EMC_REXT */
+	u32 emc_rext;
+	/* Specifies the value for EMC_WEXT */
+	u32 emc_wext;
+	/* Specifies the value for EMC_WDV */
+	u32 emc_wdv;
+
+	u32 emc_wdv_chk;
+	u32 emc_wsv;
+	u32 emc_wev;
+
+	/* Specifies the value for EMC_WDV_MASK */
+	u32 emc_wdv_mask;
+
+	u32 emc_ws_duration;
+	u32 emc_we_duration;
+
+	/* Specifies the value for EMC_QUSE */
+	u32 emc_quse;
+	/* Specifies the value for EMC_QUSE_WIDTH */
+	u32 emc_quse_width;
+	/* Specifies the value for EMC_IBDLY */
+	u32 emc_ibdly;
+
+	u32 emc_obdly;
+
+	/* Specifies the value for EMC_EINPUT */
+	u32 emc_einput;
+	/* Specifies the value for EMC_EINPUT_DURATION */
+	u32 emc_einput_duration;
+	/* Specifies the value for EMC_PUTERM_EXTRA */
+	u32 emc_puterm_extra;
+	/* Specifies the value for EMC_PUTERM_WIDTH */
+	u32 emc_puterm_width;
+
+	u32 emc_qrst;
+	u32 emc_qsafe;
+	u32 emc_rdv;
+	u32 emc_rdv_mask;
+
+	u32 emc_rdv_early;
+	u32 emc_rdv_early_mask;
+
+	/* Specifies the value for EMC_QPOP */
+	u32 emc_qpop;
+
+	/* Specifies the value for EMC_REFRESH */
+	u32 emc_refresh;
+	/* Specifies the value for EMC_BURST_REFRESH_NUM */
+	u32 emc_burst_refresh_num;
+	/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
+	u32 emc_prerefresh_req_cnt;
+	/* Specifies the value for EMC_PDEX2WR */
+	u32 emc_pdex2wr;
+	/* Specifies the value for EMC_PDEX2RD */
+	u32 emc_pdex2rd;
+	/* Specifies the value for EMC_PCHG2PDEN */
+	u32 emc_pchg2pden;
+	/* Specifies the value for EMC_ACT2PDEN */
+	u32 emc_act2pden;
+	/* Specifies the value for EMC_AR2PDEN */
+	u32 emc_ar2pden;
+	/* Specifies the value for EMC_RW2PDEN */
+	u32 emc_rw2pden;
+
+	u32 emc_cke2pden;
+	u32 emc_pdex2che;
+	u32 emc_pdex2mrr;
+
+	/* Specifies the value for EMC_TXSR */
+	u32 emc_txsr;
+	/* Specifies the value for EMC_TXSRDLL */
+	u32 emc_txsr_dll;
+	/* Specifies the value for EMC_TCKE */
+	u32 emc_tcke;
+	/* Specifies the value for EMC_TCKESR */
+	u32 emc_tckesr;
+	/* Specifies the value for EMC_TPD */
+	u32 emc_tpd;
+	/* Specifies the value for EMC_TFAW */
+	u32 emc_tfaw;
+	/* Specifies the value for EMC_TRPAB */
+	u32 emc_trpab;
+	/* Specifies the value for EMC_TCLKSTABLE */
+	u32 emc_tclkstable;
+	/* Specifies the value for EMC_TCLKSTOP */
+	u32 emc_tclkstop;
+	/* Specifies the value for EMC_TREFBW */
+	u32 emc_trefbw;
+
+	/* FBIO configuration values */
+
+	/* Specifies the value for EMC_FBIO_CFG5 */
+	u32 emc_fbio_cfg5;
+	/* Specifies the value for EMC_FBIO_CFG7 */
+	u32 emc_fbio_cfg7;
+	u32 emc_fbio_cfg8;
+
+	/* Command mapping for CMD brick 0 */
+	u32 emc_cmd_mapping_cmd0_0;
+	u32 emc_cmd_mapping_cmd0_1;
+	u32 emc_cmd_mapping_cmd0_2;
+	u32 emc_cmd_mapping_cmd1_0;
+	u32 emc_cmd_mapping_cmd1_1;
+	u32 emc_cmd_mapping_cmd1_2;
+	u32 emc_cmd_mapping_cmd2_0;
+	u32 emc_cmd_mapping_cmd2_1;
+	u32 emc_cmd_mapping_cmd2_2;
+	u32 emc_cmd_mapping_cmd3_0;
+	u32 emc_cmd_mapping_cmd3_1;
+	u32 emc_cmd_mapping_cmd3_2;
+	u32 emc_cmd_mapping_byte;
+
+	/* Specifies the value for EMC_FBIO_SPARE */
+	u32 emc_fbio_spare;
+
+	/* Specifies the value for EMC_CFG_RSV */
+	u32 emc_cfg_rsv;
+
+	/* MRS command values */
+
+	/* Specifies the value for EMC_MRS */
+	u32 emc_mrs;
+	/* Specifies the MP0 command to initialize mode registers */
+	u32 emc_emrs;
+	/* Specifies the MP2 command to initialize mode registers */
+	u32 emc_emrs2;
+	/* Specifies the MP3 command to initialize mode registers */
+	u32 emc_emrs3;
+	/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
+	u32 emc_mrw1;
+	/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
+	u32 emc_mrw2;
+	/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
+	u32 emc_mrw3;
+	/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
+	u32 emc_mrw4;
+
+	/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
+	u32 emc_mrw6;
+	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
+	u32 emc_mrw8;
+	/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
+	u32 emc_mrw9;
+	/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
+	u32 emc_mrw10;
+	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
+	u32 emc_mrw12;
+	/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
+	u32 emc_mrw13;
+	/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
+	u32 emc_mrw14;
+
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at cold boot
+	 */
+	u32 emc_mrw_extra;
+	/*
+	 * Specifies the programming to extra LPDDR2 Mode Register
+	 * at warm boot
+	 */
+	u32 emc_warm_boot_mrw_extra;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * warm boot
+	 */
+	u32 emc_warm_boot_extramode_reg_write_enable;
+	/*
+	 * Specify the enable of extra Mode Register programming at
+	 * cold boot
+	 */
+	u32 emc_extramode_reg_write_enable;
+
+	/* Specifies the EMC_MRW reset command value */
+	u32 emc_mrw_reset_command;
+	/* Specifies the EMC Reset wait time (in microseconds) */
+	u32 emc_mrw_reset_ninit_wait;
+	/* Specifies the value for EMC_MRS_WAIT_CNT */
+	u32 emc_mrs_wait_cnt;
+	/* Specifies the value for EMC_MRS_WAIT_CNT2 */
+	u32 emc_mrs_wait_cnt2;
+
+	/* EMC miscellaneous configurations */
+
+	/* Specifies the value for EMC_CFG */
+	u32 emc_cfg;
+	/* Specifies the value for EMC_CFG_2 */
+	u32 emc_cfg2;
+	/* Specifies the pipe bypass controls */
+	u32 emc_cfg_pipe;
+
+	u32 emc_cfg_pipe_clk;
+	u32 emc_fdpd_ctrl_cmd_no_ramp;
+	u32 emc_cfg_update;
+
+	/* Specifies the value for EMC_DBG */
+	u32 emc_dbg;
+
+	u32 emc_dbg_write_mux;
+
+	/* Specifies the value for EMC_CMDQ */
+	u32 emc_cmd_q;
+	/* Specifies the value for EMC_MC2EMCQ */
+	u32 emc_mc2emc_q;
+	/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
+	u32 emc_dyn_self_ref_control;
+
+	/* Specifies the value for MEM_INIT_DONE */
+	u32 ahb_arbitration_xbar_ctrl_meminit_done;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL */
+	u32 emc_cfg_dig_dll;
+	u32 emc_cfg_dig_dll_1;
+
+	/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
+	u32 emc_cfg_dig_dll_period;
+	/* Specifies the value of *DEV_SELECTN of various EMC registers */
+	u32 emc_dev_select;
+
+	/* Specifies the value for EMC_SEL_DPD_CTRL */
+	u32 emc_sel_dpd_ctrl;
+
+	/* Pads trimmer delays */
+	u32 emc_fdpd_ctrl_dq;
+	u32 emc_fdpd_ctrl_cmd;
+	u32 emc_pmacro_ib_vref_dq_0;
+	u32 emc_pmacro_ib_vref_dq_1;
+	u32 emc_pmacro_ib_vref_dqs_0;
+	u32 emc_pmacro_ib_vref_dqs_1;
+	u32 emc_pmacro_ib_rxrt;
+	u32 emc_cfg_pipe1;
+	u32 emc_cfg_pipe2;
+
+	/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
+	u32 emc_pmacro_quse_ddll_rank0_0;
+	u32 emc_pmacro_quse_ddll_rank0_1;
+	u32 emc_pmacro_quse_ddll_rank0_2;
+	u32 emc_pmacro_quse_ddll_rank0_3;
+	u32 emc_pmacro_quse_ddll_rank0_4;
+	u32 emc_pmacro_quse_ddll_rank0_5;
+	u32 emc_pmacro_quse_ddll_rank1_0;
+	u32 emc_pmacro_quse_ddll_rank1_1;
+	u32 emc_pmacro_quse_ddll_rank1_2;
+	u32 emc_pmacro_quse_ddll_rank1_3;
+	u32 emc_pmacro_quse_ddll_rank1_4;
+	u32 emc_pmacro_quse_ddll_rank1_5;
+
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_0;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_1;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_2;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_3;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_4;
+	u32 emc_pmacro_ob_ddll_long_dq_rank0_5;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_0;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_1;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_2;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_3;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_4;
+	u32 emc_pmacro_ob_ddll_long_dq_rank1_5;
+
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_0;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_1;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_2;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_3;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_4;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank0_5;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_0;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_1;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_2;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_3;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_4;
+	u32 emc_pmacro_ob_ddll_long_dqs_rank1_5;
+
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_0;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_1;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_2;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank0_3;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_0;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_1;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_2;
+	u32 emc_pmacro_ib_ddll_long_dqs_rank1_3;
+
+	u32 emc_pmacro_ddll_long_cmd_0;
+	u32 emc_pmacro_ddll_long_cmd_1;
+	u32 emc_pmacro_ddll_long_cmd_2;
+	u32 emc_pmacro_ddll_long_cmd_3;
+	u32 emc_pmacro_ddll_long_cmd_4;
+	u32 emc_pmacro_ddll_short_cmd_0;
+	u32 emc_pmacro_ddll_short_cmd_1;
+	u32 emc_pmacro_ddll_short_cmd_2;
+
+	u32 emc_pmacro_ddll_periodic_offset;
+
+	/*
+	 * Specifies the delay after asserting CKE pin during a WarmBoot0
+	 * sequence (in microseconds)
+	 */
+	u32 warm_boot_wait;
+
+	/* Specifies the value for EMC_ODT_WRITE */
+	u32 emc_odt_write;
+
+	/* Periodic ZQ calibration */
+
+	/*
+	 * Specifies the value for EMC_ZCAL_INTERVAL
+	 * Value 0 disables ZQ calibration
+	 */
+	u32 emc_zcal_interval;
+	/* Specifies the value for EMC_ZCAL_WAIT_CNT */
+	u32 emc_zcal_wait_cnt;
+	/* Specifies the value for EMC_ZCAL_MRW_CMD */
+	u32 emc_zcal_mrw_cmd;
+
+	/* DRAM initialization sequence flow control */
+
+	/* Specifies the MRS command value for resetting DLL */
+	u32 emc_mrs_reset_dll;
+	/* Specifies the command for ZQ initialization of device 0 */
+	u32 emc_zcal_init_dev0;
+	/* Specifies the command for ZQ initialization of device 1 */
+	u32 emc_zcal_init_dev1;
+	/*
+	 * Specifies the wait time after programming a ZQ initialization
+	 * command (in microseconds)
+	 */
+	u32 emc_zcal_init_wait;
+	/*
+	 * Specifies the enable for ZQ calibration at cold boot [bit 0]
+	 * and warm boot [bit 1]
+	 */
+	u32 emc_zcal_warm_cold_boot_enables;
+
+	/*
+	 * Specifies the MRW command to LPDDR2 for ZQ calibration
+	 * on warmboot
+	 */
+	/* Is issued to both devices separately */
+	u32 emc_mrw_lpddr2zcal_warm_boot;
+	/*
+	 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
+	 * Is issued to both devices separately
+	 */
+	u32 emc_zqcal_ddr3_warm_boot;
+
+	u32 emc_zqcal_lpddr4_warm_boot;
+
+	/*
+	 * Specifies the wait time for ZQ calibration on warmboot
+	 * (in microseconds)
+	 */
+	u32 emc_zcal_warm_boot_wait;
+	/*
+	 * Specifies the enable for DRAM Mode Register programming
+	 * at warm boot
+	 */
+	u32 emc_mrs_warm_boot_enable;
+	/*
+	 * Specifies the wait time after sending an MRS DLL reset command
+	 * in microseconds)
+	 */
+	u32 emc_mrs_reset_dll_wait;
+	/* Specifies the extra MRS command to initialize mode registers */
+	u32 emc_mrs_extra;
+	/* Specifies the extra MRS command at warm boot */
+	u32 emc_warm_boot_mrs_extra;
+	/* Specifies the EMRS command to enable the DDR2 DLL */
+	u32 emc_emrs_ddr2_dll_enable;
+	/* Specifies the MRS command to reset the DDR2 DLL */
+	u32 emc_mrs_ddr2_dll_reset;
+	/* Specifies the EMRS command to set OCD calibration */
+	u32 emc_emrs_ddr2_ocd_calib;
+	/*
+	 * Specifies the wait between initializing DDR and setting OCD
+	 * calibration (in microseconds)
+	 */
+	u32 emc_ddr2_wait;
+	/* Specifies the value for EMC_CLKEN_OVERRIDE */
+	u32 emc_clken_override;
+	/*
+	 * Specifies LOG2 of the extra refresh numbers after booting
+	 * Program 0 to disable
+	 */
+	u32 emc_extra_refresh_num;
+	/* Specifies the master override for all EMC clocks */
+	u32 emc_clken_override_allwarm_boot;
+	/* Specifies the master override for all MC clocks */
+	u32 mc_clken_override_allwarm_boot;
+	/* Specifies digital dll period, choosing between 4 to 64 ms */
+	u32 emc_cfg_dig_dll_period_warm_boot;
+
+	/* Pad controls */
+
+	/* Specifies the value for PMC_VDDP_SEL */
+	u32 pmc_vddp_sel;
+	/* Specifies the wait time after programming PMC_VDDP_SEL */
+	u32 pmc_vddp_sel_wait;
+	/* Specifies the value for PMC_DDR_CFG */
+	u32 pmc_ddr_cfg;
+	/* Specifies the value for PMC_IO_DPD3_REQ */
+	u32 pmc_io_dpd3_req;
+	/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
+	u32 pmc_io_dpd3_req_wait;
+
+	u32 pmc_io_dpd4_req_wait;
+
+	/* Specifies the value for PMC_REG_SHORT */
+	u32 pmc_reg_short;
+	/* Specifies the value for PMC_NO_IOPOWER */
+	u32 pmc_no_io_power;
+
+	u32 pmc_ddr_ctrl_wait;
+	u32 pmc_ddr_ctrl;
+
+	/* Specifies the value for EMC_ACPD_CONTROL */
+	u32 emc_acpd_control;
+
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
+	u32 emc_swizzle_rank0_byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
+	u32 emc_swizzle_rank0_byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
+	u32 emc_swizzle_rank0_byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
+	u32 emc_swizzle_rank0_byte3;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
+	u32 emc_swizzle_rank1_byte0;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
+	u32 emc_swizzle_rank1_byte1;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
+	u32 emc_swizzle_rank1_byte2;
+	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
+	u32 emc_swizzle_rank1_byte3;
+
+	/* Specifies the value for EMC_TXDSRVTTGEN */
+	u32 emc_txdsrvttgen;
+
+	/* Specifies the value for EMC_DATA_BRLSHFT_0 */
+	u32 emc_data_brlshft0;
+	u32 emc_data_brlshft1;
+
+	u32 emc_dqs_brlshft0;
+	u32 emc_dqs_brlshft1;
+
+	u32 emc_cmd_brlshft0;
+	u32 emc_cmd_brlshft1;
+	u32 emc_cmd_brlshft2;
+	u32 emc_cmd_brlshft3;
+
+	u32 emc_quse_brlshft0;
+	u32 emc_quse_brlshft1;
+	u32 emc_quse_brlshft2;
+	u32 emc_quse_brlshft3;
+
+	u32 emc_dll_cfg0;
+	u32 emc_dll_cfg1;
+
+	u32 emc_pmc_scratch1;
+	u32 emc_pmc_scratch2;
+	u32 emc_pmc_scratch3;
+
+	u32 emc_pmacro_pad_cfg_ctrl;
+
+	u32 emc_pmacro_vttgen_ctrl0;
+	u32 emc_pmacro_vttgen_ctrl1;
+	u32 emc_pmacro_vttgen_ctrl2;
+	u32 emc_pmacro_dsr_vttgen_ctrl0;
+	u32 emc_pmacro_brick_ctrl_rfu1;
+	u32 emc_pmacro_cmd_brick_ctrl_fdpd;
+	u32 emc_pmacro_brick_ctrl_rfu2;
+	u32 emc_pmacro_data_brick_ctrl_fdpd;
+	u32 emc_pmacro_bg_bias_ctrl0;
+	u32 emc_pmacro_data_pad_rx_ctrl;
+	u32 emc_pmacro_cmd_pad_rx_ctrl;
+	u32 emc_pmacro_data_rx_term_mode;
+	u32 emc_pmacro_cmd_rx_term_mode;
+	u32 emc_pmacro_data_pad_tx_ctrl;
+	u32 emc_pmacro_cmd_pad_tx_ctrl;
+	u32 emc_cfg3;
+
+	u32 emc_pmacro_tx_pwrd0;
+	u32 emc_pmacro_tx_pwrd1;
+	u32 emc_pmacro_tx_pwrd2;
+	u32 emc_pmacro_tx_pwrd3;
+	u32 emc_pmacro_tx_pwrd4;
+	u32 emc_pmacro_tx_pwrd5;
+
+	u32 emc_config_sample_delay;
+
+	u32 emc_pmacro_brick_mapping0;
+	u32 emc_pmacro_brick_mapping1;
+	u32 emc_pmacro_brick_mapping2;
+
+	u32 emc_pmacro_tx_sel_clk_src0;
+	u32 emc_pmacro_tx_sel_clk_src1;
+	u32 emc_pmacro_tx_sel_clk_src2;
+	u32 emc_pmacro_tx_sel_clk_src3;
+	u32 emc_pmacro_tx_sel_clk_src4;
+	u32 emc_pmacro_tx_sel_clk_src5;
+
+	u32 emc_pmacro_perbit_fgcg_ctrl0;
+	u32 emc_pmacro_perbit_fgcg_ctrl1;
+	u32 emc_pmacro_perbit_fgcg_ctrl2;
+	u32 emc_pmacro_perbit_fgcg_ctrl3;
+	u32 emc_pmacro_perbit_fgcg_ctrl4;
+	u32 emc_pmacro_perbit_fgcg_ctrl5;
+	u32 emc_pmacro_perbit_rfu_ctrl0;
+	u32 emc_pmacro_perbit_rfu_ctrl1;
+	u32 emc_pmacro_perbit_rfu_ctrl2;
+	u32 emc_pmacro_perbit_rfu_ctrl3;
+	u32 emc_pmacro_perbit_rfu_ctrl4;
+	u32 emc_pmacro_perbit_rfu_ctrl5;
+	u32 emc_pmacro_perbit_rfu1_ctrl0;
+	u32 emc_pmacro_perbit_rfu1_ctrl1;
+	u32 emc_pmacro_perbit_rfu1_ctrl2;
+	u32 emc_pmacro_perbit_rfu1_ctrl3;
+	u32 emc_pmacro_perbit_rfu1_ctrl4;
+	u32 emc_pmacro_perbit_rfu1_ctrl5;
+
+	u32 emc_pmacro_data_pi_ctrl;
+	u32 emc_pmacro_cmd_pi_ctrl;
+
+	u32 emc_pmacro_ddll_bypass;
+
+	u32 emc_pmacro_ddll_pwrd0;
+	u32 emc_pmacro_ddll_pwrd1;
+	u32 emc_pmacro_ddll_pwrd2;
+
+	u32 emc_pmacro_cmd_ctrl0;
+	u32 emc_pmacro_cmd_ctrl1;
+	u32 emc_pmacro_cmd_ctrl2;
+
+	/* DRAM size information */
+
+	/* Specifies the value for MC_EMEM_ADR_CFG */
+	u32 mc_emem_adr_cfg;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
+	u32 mc_emem_adr_cfg_dev0;
+	/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
+	u32 mc_emem_adr_cfg_dev1;
+
+	u32 mc_emem_adr_cfg_channel_mask;
+
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
+	u32 mc_emem_adr_cfg_bank_mask0;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
+	u32 mc_emem_adr_cfg_bank_mask1;
+	/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
+	u32 mc_emem_adr_cfg_bank_mask2;
+
+	/*
+	 * Specifies the value for MC_EMEM_CFG which holds the external memory
+	 * size (in KBytes)
+	 */
+	u32 mc_emem_cfg;
+
+	/* MC arbitration configuration */
+
+	/* Specifies the value for MC_EMEM_ARB_CFG */
+	u32 mc_emem_arb_cfg;
+	/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
+	u32 mc_emem_arb_outstanding_req;
+
+	u32 emc_emem_arb_refpb_hp_ctrl;
+	u32 emc_emem_arb_refpb_bank_ctrl;
+
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
+	u32 mc_emem_arb_timing_rcd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
+	u32 mc_emem_arb_timing_rp;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
+	u32 mc_emem_arb_timing_rc;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
+	u32 mc_emem_arb_timing_ras;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
+	u32 mc_emem_arb_timing_faw;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
+	u32 mc_emem_arb_timing_rrd;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
+	u32 mc_emem_arb_timing_rap2pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
+	u32 mc_emem_arb_timing_wap2pre;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
+	u32 mc_emem_arb_timing_r2r;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
+	u32 mc_emem_arb_timing_w2w;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
+	u32 mc_emem_arb_timing_r2w;
+	/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
+	u32 mc_emem_arb_timing_w2r;
+
+	u32 mc_emem_arb_timing_rfcpb;
+
+	/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
+	u32 mc_emem_arb_da_turns;
+	/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
+	u32 mc_emem_arb_da_covers;
+	/* Specifies the value for MC_EMEM_ARB_MISC0 */
+	u32 mc_emem_arb_misc0;
+	/* Specifies the value for MC_EMEM_ARB_MISC1 */
+	u32 mc_emem_arb_misc1;
+	u32 mc_emem_arb_misc2;
+
+	/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
+	u32 mc_emem_arb_ring1_throttle;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
+	u32 mc_emem_arb_override;
+	/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
+	u32 mc_emem_arb_override1;
+	/* Specifies the value for MC_EMEM_ARB_RSV */
+	u32 mc_emem_arb_rsv;
+
+	u32 mc_da_cfg0;
+	u32 mc_emem_arb_timing_ccdmw;
+
+	/* Specifies the value for MC_CLKEN_OVERRIDE */
+	u32 mc_clken_override;
+
+	/* Specifies the value for MC_STAT_CONTROL */
+	u32 mc_stat_control;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM */
+	u32 mc_video_protect_bom;
+	/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
+	u32 mc_video_protect_bom_adr_hi;
+	/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
+	u32 mc_video_protect_size_mb;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
+	u32 mc_video_protect_vpr_override;
+	/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
+	u32 mc_video_protect_vpr_override1;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
+	u32 mc_video_protect_gpu_override0;
+	/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
+	u32 mc_video_protect_gpu_override1;
+	/* Specifies the value for MC_SEC_CARVEOUT_BOM */
+	u32 mc_sec_carveout_bom;
+	/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
+	u32 mc_sec_carveout_adr_hi;
+	/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
+	u32 mc_sec_carveout_size_mb;
+	/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
+	u32 mc_video_protect_write_access;
+	/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
+	u32 mc_sec_carveout_protect_write_access;
+
+	u32 mc_generalized_carveout1_bom;
+	u32 mc_generalized_carveout1_bom_hi;
+	u32 mc_generalized_carveout1_size_128kb;
+	u32 mc_generalized_carveout1_access0;
+	u32 mc_generalized_carveout1_access1;
+	u32 mc_generalized_carveout1_access2;
+	u32 mc_generalized_carveout1_access3;
+	u32 mc_generalized_carveout1_access4;
+	u32 mc_generalized_carveout1_force_internal_access0;
+	u32 mc_generalized_carveout1_force_internal_access1;
+	u32 mc_generalized_carveout1_force_internal_access2;
+	u32 mc_generalized_carveout1_force_internal_access3;
+	u32 mc_generalized_carveout1_force_internal_access4;
+	u32 mc_generalized_carveout1_cfg0;
+
+	u32 mc_generalized_carveout2_bom;
+	u32 mc_generalized_carveout2_bom_hi;
+	u32 mc_generalized_carveout2_size_128kb;
+	u32 mc_generalized_carveout2_access0;
+	u32 mc_generalized_carveout2_access1;
+	u32 mc_generalized_carveout2_access2;
+	u32 mc_generalized_carveout2_access3;
+	u32 mc_generalized_carveout2_access4;
+	u32 mc_generalized_carveout2_force_internal_access0;
+	u32 mc_generalized_carveout2_force_internal_access1;
+	u32 mc_generalized_carveout2_force_internal_access2;
+	u32 mc_generalized_carveout2_force_internal_access3;
+	u32 mc_generalized_carveout2_force_internal_access4;
+	u32 mc_generalized_carveout2_cfg0;
+
+	u32 mc_generalized_carveout3_bom;
+	u32 mc_generalized_carveout3_bom_hi;
+	u32 mc_generalized_carveout3_size_128kb;
+	u32 mc_generalized_carveout3_access0;
+	u32 mc_generalized_carveout3_access1;
+	u32 mc_generalized_carveout3_access2;
+	u32 mc_generalized_carveout3_access3;
+	u32 mc_generalized_carveout3_access4;
+	u32 mc_generalized_carveout3_force_internal_access0;
+	u32 mc_generalized_carveout3_force_internal_access1;
+	u32 mc_generalized_carveout3_force_internal_access2;
+	u32 mc_generalized_carveout3_force_internal_access3;
+	u32 mc_generalized_carveout3_force_internal_access4;
+	u32 mc_generalized_carveout3_cfg0;
+
+	u32 mc_generalized_carveout4_bom;
+	u32 mc_generalized_carveout4_bom_hi;
+	u32 mc_generalized_carveout4_size_128kb;
+	u32 mc_generalized_carveout4_access0;
+	u32 mc_generalized_carveout4_access1;
+	u32 mc_generalized_carveout4_access2;
+	u32 mc_generalized_carveout4_access3;
+	u32 mc_generalized_carveout4_access4;
+	u32 mc_generalized_carveout4_force_internal_access0;
+	u32 mc_generalized_carveout4_force_internal_access1;
+	u32 mc_generalized_carveout4_force_internal_access2;
+	u32 mc_generalized_carveout4_force_internal_access3;
+	u32 mc_generalized_carveout4_force_internal_access4;
+	u32 mc_generalized_carveout4_cfg0;
+
+	u32 mc_generalized_carveout5_bom;
+	u32 mc_generalized_carveout5_bom_hi;
+	u32 mc_generalized_carveout5_size_128kb;
+	u32 mc_generalized_carveout5_access0;
+	u32 mc_generalized_carveout5_access1;
+	u32 mc_generalized_carveout5_access2;
+	u32 mc_generalized_carveout5_access3;
+	u32 mc_generalized_carveout5_access4;
+	u32 mc_generalized_carveout5_force_internal_access0;
+	u32 mc_generalized_carveout5_force_internal_access1;
+	u32 mc_generalized_carveout5_force_internal_access2;
+	u32 mc_generalized_carveout5_force_internal_access3;
+	u32 mc_generalized_carveout5_force_internal_access4;
+	u32 mc_generalized_carveout5_cfg0;
+
+	/* Specifies enable for CA training */
+	u32 emc_ca_training_enable;
+	/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
+	u32 swizzle_rank_byte_encode;
+	/* Specifies enable and offset for patched boot rom write */
+	u32 boot_rom_patch_control;
+	/* Specifies data for patched boot rom write */
+	u32 boot_rom_patch_data;
+
+	/* Specifies the value for MC_MTS_CARVEOUT_BOM */
+	u32 mc_mts_carveout_bom;
+	/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
+	u32 mc_mts_carveout_adr_hi;
+	/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
+	u32 mc_mts_carveout_size_mb;
+	/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
+	u32 mc_mts_carveout_reg_ctrl;
+
+	/* Specifies the clients that are allowed to access untranslated memory */
+	u32 mc_untranslated_region_check;
+
+	/* Just a place holder for special usage when there is no BCT for certain registers */
+	u32 bct_na;
+} sdram_params_t210b01_t;
+
+#endif
--- a/bdk/mem/smmu.c
+++ b/bdk/mem/smmu.c
@@ -1,6 +1,7 @@
 /*
 * Copyright (c) 2018 naehrwert
 * Copyright (c) 2018 balika011
+ * Copyright (c) 2018-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -17,155 +18,255 @@

 #include <string.h>

+#include <soc/bpmp.h>
 #include <soc/ccplex.h>
+#include <soc/timer.h>
 #include <soc/t210.h>
 #include <mem/mc_t210.h>
 #include <mem/smmu.h>
-#include <utils/util.h>
-#include <utils/aarch64_util.h>
+#include <memory_map.h>

-bool smmu_used = false;
-u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
+/*! SMMU register defines */
+#define SMMU_ASID(asid)          (((asid) << 24u) | ((asid) << 16u) | ((asid) << 8u) | (asid))
+#define SMMU_ENABLE              BIT(31)
+#define SMMU_TLB_ACTIVE_LINES(l) ((l) << 0u)
+#define SMMU_TLB_RR_ARBITRATION  BIT(28)
+#define SMMU_TLB_HIT_UNDER_MISS  BIT(29)
+#define SMMU_TLB_STATS_ENABLE    BIT(31)
+#define SMUU_PTC_INDEX_MAP(m)    ((m) << 0u)
+#define SMUU_PTC_LINE_MASK(m)    ((m) << 8u)
+#define SMUU_PTC_REQ_LIMIT(l)    ((l) << 24u)
+#define SMUU_PTC_CACHE_ENABLE    BIT(29)
+#define SMUU_PTC_STATS_ENABLE    BIT(31)

-//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
-u8 smmu_payload[] __attribute__((aligned(16))) = {
-	0x41, 0x01, 0x00, 0x58, // 0x00: LDR  X1, =0x70019010
+/*! Page table defines */
+#define SMMU_4MB_REGION 0
+#define SMMU_PAGE_TABLE 1
+#define SMMU_PDIR_COUNT 1024
+#define SMMU_PTBL_COUNT 1024
+#define SMMU_PAGE_SHIFT 12u
+#define SMMU_PTN_SHIFT  SMMU_PAGE_SHIFT
+#define SMMU_PDN_SHIFT  22u
+#define SMMU_ADDR_TO_PFN(addr) ((addr) >> SMMU_PAGE_SHIFT)
+#define SMMU_ADDR_TO_PTN(addr) ((addr) >> SMMU_PTN_SHIFT)
+#define SMMU_ADDR_TO_PDN(addr) ((addr) >> SMMU_PDN_SHIFT)
+#define SMMU_PTN_TO_ADDR(ptn)  ((ptn)  << SMMU_PTN_SHIFT)
+#define SMMU_PDN_TO_ADDR(pdn)  ((pdn)  << SMMU_PDN_SHIFT)
+#define SMMU_PTB(page, attr) (((attr) << 29u) | ((page) >> SMMU_PAGE_SHIFT))
+
+#define SMMU_PAYLOAD_EN_SHIFT 4
+#define SMMU_PAYLOAD_EN_SET   0x20
+#define SMMU_PAYLOAD_EN_UNSET 0x00
+
+// Enabling SMMU requires a TZ (EL3) secure write. MC(MC_SMMU_CONFIG) = 1;
+static u8 smmu_enable_payload[] = {
+	0xC1, 0x00, 0x00, 0x18, // 0x00: LDR  W1, =0x70019010
 	0x20, 0x00, 0x80, 0xD2, // 0x04: MOV  X0, #0x1
 	0x20, 0x00, 0x00, 0xB9, // 0x08: STR  W0, [X1]
 	0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC   IALLUIS
 	0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB  ISH
 	0xFE, 0xFF, 0xFF, 0x17, // 0x14: B    loop
-	0x00, 0x00, 0x80, 0xD2, // 0x18: MOV  X0, #0x0
-	0x20, 0x00, 0x00, 0xB9, // 0x1C: STR  W0, [X1]
-	0x80, 0x00, 0x00, 0x58, // 0x20: LDR  X0, =0x4002B000
-	0x00, 0x00, 0x1F, 0xD6, // 0x28: BR   X0
-	0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG
-	0x00, 0x00, 0x00, 0x00, // 0x2C:
-	0x00, 0x00, 0x00, 0x00, // 0x30: secmon address
-	0x00, 0x00, 0x00, 0x00  // 0x34:
+	0x10, 0x90, 0x01, 0x70, // 0x18: MC_SMMU_CONFIG
 };

-void *page_alloc(u32 num)
+static void *smmu_heap    = (void *)SMMU_HEAP_ADDR;
+static bool  smmu_enabled = false;
+
+void *smmu_page_zalloc(u32 num)
 {
-	u8 *res = _pageheap;
-	_pageheap += 0x1000 * num;
-	memset(res, 0, 0x1000 * num);
-	return res;
+	void *page = smmu_heap;
+	memset(page, 0, SZ_PAGE * num);
+
+	smmu_heap += SZ_PAGE * num;
+
+	return page;
 }

-u32 *smmu_alloc_pdir()
+static pde_t *_smmu_pdir_alloc()
 {
-	u32 *pdir = (u32 *)page_alloc(1);
-	for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
-		pdir[pdn] = _PDE_VACANT(pdn);
+	pde_t *pdir = (pde_t *)smmu_page_zalloc(1);
+
+	// Initialize pdes with no permissions.
+	for (u32 pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
+		pdir[pdn].huge.page = pdn;
+
 	return pdir;
 }

-void smmu_flush_regs()
+static void _smmu_flush_regs()
 {
 	(void)MC(MC_SMMU_PTB_DATA);
 }

 void smmu_flush_all()
 {
+	// Flush the entire page table cache.
 	MC(MC_SMMU_PTC_FLUSH) = 0;
-	smmu_flush_regs();
+	_smmu_flush_regs();
+
+	// Flush the entire table.
 	MC(MC_SMMU_TLB_FLUSH) = 0;
-	smmu_flush_regs();
+	_smmu_flush_regs();
 }

-void smmu_init(u32 secmon_base)
+void smmu_init()
 {
-	MC(MC_SMMU_PTB_ASID) = 0;
-	MC(MC_SMMU_PTB_DATA) = 0;
-	MC(MC_SMMU_TLB_CONFIG) = 0x30000030;
-	MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
-	MC(MC_SMMU_PTC_FLUSH) = 0;
-	MC(MC_SMMU_TLB_FLUSH) = 0;
-
-	// Set the secmon address
-	*(u32 *)(smmu_payload + 0x30) = secmon_base;
+	MC(MC_SMMU_PTB_ASID)   = 0;
+	MC(MC_SMMU_PTB_DATA)   = 0;
+	MC(MC_SMMU_TLB_CONFIG) = SMMU_TLB_HIT_UNDER_MISS | SMMU_TLB_RR_ARBITRATION | SMMU_TLB_ACTIVE_LINES(48);
+	MC(MC_SMMU_PTC_CONFIG) = SMUU_PTC_CACHE_ENABLE | SMUU_PTC_REQ_LIMIT(8) | SMUU_PTC_LINE_MASK(0xF) | SMUU_PTC_INDEX_MAP(0x3F);
+	MC(MC_SMMU_PTC_FLUSH)  = 0;
+	MC(MC_SMMU_TLB_FLUSH)  = 0;
 }

 void smmu_enable()
 {
-	if (smmu_used)
+	if (smmu_enabled)
 		return;

-	ccplex_boot_cpu0((u32)smmu_payload);
-	smmu_used = true;
-	msleep(150);
+	// Launch payload on CCPLEX in order to set SMMU enable bit.
+	ccplex_boot_cpu0((u32)smmu_enable_payload, false);
+	msleep(100);
+	ccplex_powergate_cpu0();

 	smmu_flush_all();
+
+	smmu_enabled = true;
 }

-bool smmu_is_used()
+void smmu_disable()
 {
-	return smmu_used;
+	if (!smmu_enabled)
+		return;
+
+	// Set payload to disable SMMU.
+	smmu_enable_payload[SMMU_PAYLOAD_EN_SHIFT] = SMMU_PAYLOAD_EN_UNSET;
+
+	smmu_flush_all();
+	bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
+
+	// Launch payload on CCPLEX in order to set SMMU enable bit.
+	ccplex_boot_cpu0((u32)smmu_enable_payload, false);
+	msleep(100);
+	ccplex_powergate_cpu0();
+
+	smmu_flush_all();
+
+	// Restore payload to SMMU enable.
+	smmu_enable_payload[SMMU_PAYLOAD_EN_SHIFT] = SMMU_PAYLOAD_EN_SET;
+
+	smmu_enabled = false;
+	smmu_heap    = (void *)SMMU_HEAP_ADDR;
 }

-void smmu_exit()
+void smmu_reset_heap()
 {
-	*(u32 *)(smmu_payload + 0x14) = _NOP();
+	smmu_heap = (void *)SMMU_HEAP_ADDR;
 }

-u32 *smmu_init_domain4(u32 dev_base, u32 asid)
+void *smmu_domain_init(u32 dev_base, u32 asid)
 {
-	u32 *pdir = smmu_alloc_pdir();
+	void *ptb = _smmu_pdir_alloc();

 	MC(MC_SMMU_PTB_ASID) = asid;
-	MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR);
-	smmu_flush_regs();
+	MC(MC_SMMU_PTB_DATA) = SMMU_PTB((u32)ptb, SMMU_ATTR_ALL);
+	_smmu_flush_regs();

-	MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid);
-	smmu_flush_regs();
+	// Use the same macro for both quad and single domains. Reserved bits are not set anyway.
+	MC(dev_base) = SMMU_ENABLE | SMMU_ASID(asid);
+	_smmu_flush_regs();

-	return pdir;
+	return ptb;
 }

-u32 *smmu_get_pte(u32 *pdir, u32 iova)
+void smmu_domain_deinit(u32 dev_base, u32 asid)
 {
-	u32 ptn = SMMU_ADDR_TO_PFN(iova);
-	u32 pdn = SMMU_ADDR_TO_PDN(iova);
-	u32 *ptbl;
+	MC(MC_SMMU_PTB_ASID) = asid;
+	MC(MC_SMMU_PTB_DATA) = 0;
+	MC(dev_base)         = 0;
+	_smmu_flush_regs();
+}

-	if (pdir[pdn] != _PDE_VACANT(pdn))
-		ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT);
+void smmu_domain_bypass(u32 dev_base, bool bypass)
+{
+	if (bypass)
+	{
+		smmu_flush_all();
+		bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
+		MC(dev_base) &= ~SMMU_ENABLE;
+	}
 	else
 	{
-		ptbl = (u32 *)page_alloc(1);
+		bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
+		MC(dev_base) |=  SMMU_ENABLE;
+		smmu_flush_all();
+	}
+	_smmu_flush_regs();
+}
+
+static pte_t *_smmu_get_pte(pde_t *pdir, u32 iova)
+{
+	u32 pdn = SMMU_ADDR_TO_PDN(iova);
+	pte_t *ptbl;
+
+	// Get 4MB page table or initialize one.
+	if (pdir[pdn].tbl.attr)
+		ptbl = (pte_t *)(SMMU_PTN_TO_ADDR(pdir[pdn].tbl.table));
+	else
+	{
+		// Allocate page table.
+		ptbl = (pte_t *)smmu_page_zalloc(1);
+
+		// Get address.
 		u32 addr = SMMU_PDN_TO_ADDR(pdn);
-		for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE)
-			ptbl[pn] = _PTE_VACANT(addr);
-		pdir[pdn] = SMMU_MK_PDE((u32)ptbl, _PDE_ATTR | _PDE_NEXT);
+
+		// Initialize page table with no permissions.
+		for (u32 pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SZ_PAGE)
+			ptbl[pn].page = SMMU_ADDR_TO_PFN(addr);
+
+		// Set page table to the page directory.
+		pdir[pdn].tbl.table = SMMU_ADDR_TO_PTN((u32)ptbl);
+		pdir[pdn].tbl.next  = SMMU_PAGE_TABLE;
+		pdir[pdn].tbl.attr  = SMMU_ATTR_ALL;
+
 		smmu_flush_all();
 	}

-	return &ptbl[ptn % SMMU_PTBL_COUNT];
+	return &ptbl[SMMU_ADDR_TO_PTN(iova) % SMMU_PTBL_COUNT];
 }

-void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
+void smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr)
 {
-	for (int i = 0; i < cnt; i++)
+	// Map pages to page table entries. VA/PA should be aligned to 4KB.
+	for (u32 i = 0; i < pages; i++)
 	{
-		u32 *pte = smmu_get_pte(pdir, addr);
-		*pte = SMMU_ADDR_TO_PFN(page) | attr;
-		addr += 0x1000;
-		page += 0x1000;
+		pte_t *pte = _smmu_get_pte((pde_t *)ptb, iova);
+
+		pte->page = SMMU_ADDR_TO_PFN(iopa);
+		pte->attr = attr;
+
+		iova += SZ_PAGE;
+		iopa += SZ_PAGE;
 	}
+
 	smmu_flush_all();
 }

-u32 *smmu_init_for_tsec()
+void smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr)
 {
-	return smmu_init_domain4(MC_SMMU_TSEC_ASID, 1);
-}
+	pde_t *pdir = (pde_t *)ptb;

-void smmu_deinit_for_tsec()
-{
-	MC(MC_SMMU_PTB_ASID) = 1;
-	MC(MC_SMMU_PTB_DATA) = 0;
-	MC(MC_SMMU_TSEC_ASID) = 0;
-	smmu_flush_regs();
-}
+	// Map 4MB regions to page directory entries. VA/PA should be aligned to 4MB.
+	for (u32 i = 0; i < regions; i++)
+	{
+		u32 pdn = SMMU_ADDR_TO_PDN(iova);
+		pdir[pdn].huge.page = SMMU_ADDR_TO_PDN(iopa);
+		pdir[pdn].huge.next = SMMU_4MB_REGION;
+		pdir[pdn].huge.attr = attr;

+		iova += SZ_4M;
+		iopa += SZ_4M;
+	}
+
+	smmu_flush_all();
+}
--- a/bdk/mem/smmu.h
+++ b/bdk/mem/smmu.h
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -14,69 +15,62 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

+#ifndef _SMMU_H_
+#define _SMMU_H_
+
 #include <utils/types.h>
+#include <assert.h>

-#define SMMU_HEAP_ADDR 0xA0000000
-
-#define MC_INTSTATUS                 0x0
-#define MC_INTMASK                   0x4
-#define MC_ERR_STATUS                0x8
-#define MC_ERR_ADR                   0xc
-#define MC_SMMU_CONFIG               0x10
-#define MC_SMMU_TLB_CONFIG           0x14
-#define MC_SMMU_PTC_CONFIG           0x18
-#define MC_SMMU_PTB_ASID             0x1c
-#define MC_SMMU_PTB_DATA             0x20
-#define MC_SMMU_TLB_FLUSH            0x30
-#define MC_SMMU_PTC_FLUSH            0x34
-#define MC_SMMU_ASID_SECURITY        0x38
+#define MC_SMMU_AVPC_ASID            0x23C
 #define MC_SMMU_TSEC_ASID            0x294
-#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98

-#define SMMU_PDE_NEXT_SHIFT 28
-#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29
-#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT  30
-#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT  31
-#define SMMU_PAGE_SHIFT 12
-#define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
-#define SMMU_PDIR_COUNT 1024
-#define SMMU_PDIR_SIZE  (sizeof(u32) * SMMU_PDIR_COUNT)
-#define SMMU_PTBL_COUNT 1024
-#define SMMU_PTBL_SIZE  (sizeof(u32) * SMMU_PTBL_COUNT)
-#define SMMU_PDIR_SHIFT 12
-#define SMMU_PDE_SHIFT  12
-#define SMMU_PTE_SHIFT  12
-#define SMMU_PFN_MASK   0x000FFFFF
-#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
-#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
-#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
-#define _READABLE  (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT)
-#define _WRITABLE  (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT)
-#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT)
-#define _PDE_NEXT  (1 << SMMU_PDE_NEXT_SHIFT)
-#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDE_ATTR  (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
-#define _PTE_ATTR  (_READABLE | _WRITABLE | _NONSECURE)
-#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
-#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
-#define SMMU_MK_PDE(page, attr)  (((page) >> SMMU_PDE_SHIFT) | (attr))
+#define SMMU_NS    BIT(0)
+#define SMMU_WRITE BIT(1)
+#define SMMU_READ  BIT(2)
+#define SMMU_ATTR_ALL (SMMU_READ | SMMU_WRITE | SMMU_NS)

-void *page_alloc(u32 num);
-u32 *smmu_alloc_pdir();
-void smmu_flush_regs();
-void smmu_flush_all();
-void smmu_init(u32 secmon_base);
-void smmu_enable();
-bool smmu_is_used();
-void smmu_exit();
-u32 *smmu_init_domain4(u32 dev_base, u32 asid);
-u32 *smmu_get_pte(u32 *pdir, u32 iova);
-void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
-u32 *smmu_init_for_tsec();
-void smmu_deinit_for_tsec();
+typedef struct _pde_t {
+	union {
+		union {
+			struct {
+				u32 table:22;
+				u32 rsvd:6;
+				u32 next:1;
+				u32 attr:3;
+			} tbl;
+
+			struct {
+				u32 rsvd_:10;
+				u32 page:12;
+				u32 rsvd:6;
+				u32 next:1;
+				u32 attr:3;
+			} huge;
+		};
+
+		u32 pde;
+	};
+} pde_t;
+
+typedef struct _pte_t {
+	u32 page:22;
+	u32 rsvd:7;
+	u32 attr:3;
+} pte_t;
+
+static_assert(sizeof(pde_t) == sizeof(u32), "pde_t size is wrong!");
+static_assert(sizeof(pte_t) == sizeof(u32), "pte_t size is wrong!");
+
+void *smmu_page_zalloc(u32 num);
+void  smmu_flush_all();
+void  smmu_init();
+void  smmu_enable();
+void  smmu_disable();
+void  smmu_reset_heap();
+void *smmu_domain_init(u32 dev_base, u32 asid);
+void  smmu_domain_deinit(u32 dev_base, u32 asid);
+void  smmu_domain_bypass(u32 dev_base, bool bypass);
+void  smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr);
+void  smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr);
+
+#endif
--- a/bdk/memory_map.h
+++ b/bdk/memory_map.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -17,50 +17,76 @@
 #ifndef _MEMORY_MAP_H_
 #define _MEMORY_MAP_H_

-//#define IPL_STACK_TOP  0x4003FF00
 /* --- BIT/BCT: 0x40000000 - 0x40003000 --- */
 /* ---     IPL: 0x40008000 - 0x40028000 --- */
+#define LDR_LOAD_ADDR     0x40007000
+
 #define IPL_LOAD_ADDR     0x40008000
-#define  IPL_SZ_MAX          0x20000 // 128KB.
-//#define IRAM_LIB_ADDR     0x4002B000
+#define  IPL_SZ_MAX          SZ_128K
+
+#define XUSB_RING_ADDR    0x40020000 // XUSB EP context and TRB ring buffers.
+
+#define SECMON_MIN_START  0x4002B000 // Minimum reserved address for secmon.
+
 #define SDRAM_PARAMS_ADDR 0x40030000 // SDRAM extraction buffer during sdram init.
-#define CBFS_DRAM_EN_ADDR 0x4003e000 // u32.
+#define  SDRAM_PARAMS_SZ       0x838
+
+/* start.S / exception_handlers.S */
+#define SYS_STACK_TOP_INIT 0x4003FF00
+#define FIQ_STACK_TOP      0x40040000
+#define IRQ_STACK_TOP      0x40040000
+#define IPL_RELOC_ADDR     0x4003FF00
+#define  IPL_RELOC_SZ            0x10
+#define EXCP_STORAGE_ADDR  0x4003FF10
+#define  EXCP_STORAGE_SZ         0x10

 /* --- DRAM START --- */
 #define DRAM_START     0x80000000
-#define  HOS_RSVD       0x1000000 // Do not write anything in this area.
+#define  HOS_RSVD          SZ_16M // Do not write anything in this area.

 #define NYX_LOAD_ADDR  0x81000000
-#define  NYX_SZ_MAX     0x1000000 // 16MB
+#define  NYX_SZ_MAX        SZ_16M
 /* --- Gap: 0x82000000 - 0x82FFFFFF --- */

-/* Stack theoretical max: 33MB */
-#define IPL_STACK_TOP  0x83100000
-#define IPL_HEAP_START 0x84000000
-#define  IPL_HEAP_SZ   0x20000000 // 512MB.
-/* --- Gap: 1040MB 0xA4000000 - 0xE4FFFFFF --- */
+// Heap buffer.
+#define IPL_HEAP_START 0x82000000
+#define  IPL_HEAP_SZ     (SZ_256M)
+
+#define SMMU_HEAP_ADDR 0x92000000
+/* --- Gap: 1280MB 0x96000000 - 0xE4FFFFFF --- */

 // Virtual disk / Chainloader buffers.
-#define RAM_DISK_ADDR     0xA4000000
-#define  RAM_DISK_SZ      0x41000000 // 1040MB.
+#define RAM_DISK_ADDR 0x95000000
+#define  RAM_DISK_SZ  0x50000000 // 1280MB.
+
+// L4T Kernel Panic Storage (PSTORE).
+#define PSTORE_ADDR   0xB0000000
+#define  PSTORE_SZ         SZ_2M
+
+// NX BIS driver sector cache.
+#define NX_BIS_CACHE_ADDR  0xC7000000
+#define  NX_BIS_CACHE_SZ   0x10020000 // 256MB.
+#define NX_BIS_LOOKUP_ADDR 0xD8000000
+#define  NX_BIS_LOOKUP_SZ   0x8000000 // 128MB. 512GB eMMC partition max.

 //#define DRAM_LIB_ADDR    0xE0000000
 /* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading.

-// SDMMC DMA buffers 1
-#define SDMMC_UPPER_BUFFER 0xE5000000
-#define  SDMMC_UP_BUF_SZ    0x8000000 // 128MB.
+// SDMMC DMA buffer. Used for unaligned DMA buffer address.
+#define SDMMC_ALT_DMA_BUFFER 0xE5000000
+#define  SDMMC_ALT_DMA_BUF_SZ   SZ_128M

-// Nyx buffers.
+// Nyx buffers. !Do not change!
 #define NYX_STORAGE_ADDR 0xED000000
+#define  NYX_STR_SZ          SZ_16M
 #define NYX_RES_ADDR     0xEE000000
-#define  NYX_RES_SZ       0x1000000 // 16MB.
+#define  NYX_RES_SZ          SZ_16M

-// SDMMC DMA buffers 2
-#define SDXC_BUF_ALIGNED   0xEF000000
-#define MIXD_BUF_ALIGNED   0xF0000000
-#define EMMC_BUF_ALIGNED   MIXD_BUF_ALIGNED
-#define  SDMMC_DMA_BUF_SZ   0x1000000 // 16MB (4MB currently used).
+// SDMMC Application DMA aligned buffers.
+#define SDXC_BUF_ALIGNED   0xEF000000 // Also used by UMS.
+#define EMMC_BUF_ALIGNED   0xF0000000
+#define MIXD_BUF_ALIGNED   EMMC_BUF_ALIGNED
+#define  SDMMC_DMA_BUF_SZ      SZ_16M // 4MB currently used.

 // Nyx LvGL buffers.
 #define NYX_LV_VDB_ADR   0xF1000000
@@ -68,7 +94,7 @@
 #define NYX_LV_MEM_ADR   0xF1400000
 #define  NYX_LV_MEM_SZ    0x6600000 // 70MB.

-// Framebuffer addresses.
+// Framebuffer addresses. !Do not change!
 #define IPL_FB_ADDRESS   0xF5A00000
 #define  IPL_FB_SZ         0x384000 // 720 x 1280 x 4.
 #define LOG_FB_ADDRESS   0xF5E00000
@@ -77,25 +103,15 @@
 #define NYX_FB2_ADDRESS  0xF6600000
 #define  NYX_FB_SZ         0x384000 // 1280 x 720 x 4.

-#define DRAM_MEM_HOLE_ADR 0xF6A00000
-#define DRAM_MEM_HOLE_SZ   0x8140000
-/* ---   Hole: 129MB 0xF6A00000 - 0xFEB3FFFF --- */
-#define DRAM_START2       0xFEB40000
-
-// NX BIS driver sector cache.
-#define NX_BIS_CACHE_ADDR 0xFEE00000
-#define  NX_BIS_CACHE_SZ    0x100000
-
 // USB buffers.
 #define USBD_ADDR                 0xFEF00000
 #define USB_DESCRIPTOR_ADDR       0xFEF40000
 #define USB_EP_CONTROL_BUF_ADDR   0xFEF80000
 #define USB_EP_BULK_IN_BUF_ADDR   0xFF000000
 #define USB_EP_BULK_OUT_BUF_ADDR  0xFF800000
-#define  USB_EP_BULK_OUT_MAX_XFER   0x800000
+#define  USB_EP_BULK_OUT_MAX_XFER      SZ_8M

 // #define EXT_PAYLOAD_ADDR    0xC0000000
 // #define RCM_PAYLOAD_ADDR    (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))
-// #define COREBOOT_ADDR       (0xD0000000 - rom_size)

 #endif
--- a/bdk/module.h
+++ b/bdk/module.h
@@ -1,6 +1,7 @@
 /*
 * Common Module Header
 * Copyright (c) 2018 M4xw
+ * Copyright (c) 2018-2026 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -21,21 +22,25 @@
 #include <stddef.h>
 #include <mem/heap.h>

+#define IANOS_EXT1 0x314E4149
+
 // Module Callback
 typedef void (*cbMainModule_t)(const char *s);
 typedef void (*memcpy_t)(void *, void *, size_t);
 typedef void (*memset_t)(void *, int, size_t);
+typedef int  (*reg_voltage_set_t)(u32, u32);

 typedef struct _bdkParams_t
 {
-	void *gfxCon;
-	void *gfxCtx;
-	heap_t *sharedHeap;
+	void *gfx_con;
+	void *gfx_ctx;
+	heap_t *heap;
 	memcpy_t memcpy;
 	memset_t memset;
-} *bdkParams_t;
+	u32 extension_magic;
+} bdk_params_t;

-// Module Entrypoint
-typedef void (*moduleEntrypoint_t)(void *, bdkParams_t);
+// Module Caller.
+typedef void (*moduleEntrypoint)(void *, bdk_params_t *);

 #endif
--- a/bdk/power/bm92t36.c
+++ b/bdk/power/bm92t36.c
@@ -0,0 +1,138 @@
+/*
+ * USB-PD driver for Nintendo Switch's TI BM92T36
+ *
+ * Copyright (c) 2020-2026 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "bm92t36.h"
+#include <soc/i2c.h>
+#include <utils/util.h>
+
+#define ALERT_STATUS_REG    0x2
+#define STATUS1_REG         0x3
+#define STATUS2_REG         0x4
+#define COMMAND_REG         0x5
+#define CONFIG1_REG         0x6
+#define DEV_CAPS_REG        0x7
+#define READ_PDOS_SRC_REG   0x8
+#define CONFIG2_REG         0x17
+#define DP_STATUS_REG       0x18
+#define DP_ALERT_EN_REG     0x19
+#define VENDOR_CONFIG_REG   0x1A
+#define AUTO_NGT_FIXED_REG  0x20
+#define AUTO_NGT_BATT_REG   0x23
+#define SYS_CONFIG1_REG     0x26
+#define SYS_CONFIG2_REG     0x27
+#define CURRENT_PDO_REG     0x28
+#define CURRENT_RDO_REG     0x2B
+#define ALERT_ENABLE_REG    0x2E
+#define SYS_CONFIG3_REG     0x2F
+#define SET_RDO_REG         0x30
+#define PDOS_SNK_REG        0x33
+#define PDOS_SRC_PROV_REG   0x3C
+#define FW_TYPE_REG         0x4B
+#define FW_REVISION_REG     0x4C
+#define MAN_ID_REG          0x4D
+#define DEV_ID_REG          0x4E
+#define REV_ID_REG          0x4F
+#define INCOMING_VDM_REG    0x50
+#define OUTGOING_VDM_REG    0x60
+
+#define STATUS1_INSERT      BIT(7)  // Cable inserted.
+
+#define VER_36     0x36
+#define MAN_ROHM  0x4B5
+#define DEV_BM92T 0x3B0
+
+#define PDO_TYPE_FIXED  0
+#define PDO_TYPE_BATT   1
+#define PDO_TYPE_VAR    2
+#define PDO_TYPE_APDO   3
+
+typedef struct _pd_object_t {
+	unsigned int amp:10;
+	unsigned int volt:10;
+	unsigned int info:10;
+	unsigned int type:2;
+} __attribute__((packed)) pd_object_t;
+
+static int _bm92t36_read_reg(u8 *buf, u32 size, u32 reg)
+{
+	memset(buf, 0, size);
+	return i2c_recv_buf_big(buf, size, I2C_1, BM92T36_I2C_ADDR, reg);
+}
+
+int bm92t36_get_version(u32 *value)
+{
+	u8 buf[2];
+	u16 version, man, dev;
+	_bm92t36_read_reg(buf, 2, FW_TYPE_REG);
+	version = (buf[0] << 4) | buf[1];
+	_bm92t36_read_reg(buf, 2, MAN_ID_REG);
+	man = (buf[1] << 8) | buf[0];
+	_bm92t36_read_reg(buf, 2, DEV_ID_REG);
+	dev = (buf[1] << 8) | buf[0];
+	if (value)
+		*value = (dev << 16) | version;
+
+	if (version == VER_36 && man == MAN_ROHM && dev == DEV_BM92T)
+	 	return 0;
+	else
+		return 1;
+}
+
+void bm92t36_get_source_info(bool *inserted, usb_pd_objects_t *usb_pd)
+{
+	u8 buf[32];
+	pd_object_t pdos[7];
+
+	if (inserted)
+	{
+		_bm92t36_read_reg(buf, 2, STATUS1_REG);
+		*inserted = (buf[0] & STATUS1_INSERT) ? true : false;
+	}
+
+	if (usb_pd)
+	{
+		_bm92t36_read_reg(buf, 29, READ_PDOS_SRC_REG);
+		memcpy(pdos, &buf[1], 28);
+
+		memset(usb_pd, 0, sizeof(usb_pd_objects_t));
+		usb_pd->pdo_no = buf[0] / sizeof(pd_object_t);
+
+		if (usb_pd->pdo_no > 7)
+			usb_pd->pdo_no = 7;
+
+		u32 idx = 0;
+		for (u32 i = 0; i < usb_pd->pdo_no; i++)
+		{
+			// Parse fixed type pdos only.
+			if (pdos[i].type != PDO_TYPE_FIXED)
+				continue;
+
+			usb_pd->pdos[idx].amperage =  pdos[i].amp  * 10;
+			usb_pd->pdos[idx].voltage  = (pdos[i].volt * 50) / 1000;
+			idx++;
+		}
+		usb_pd->pdo_no = idx;
+
+		_bm92t36_read_reg(buf, 5, CURRENT_PDO_REG);
+		memcpy(pdos, &buf[1], 4);
+		usb_pd->selected_pdo.amperage =  pdos[0].amp  * 10;
+		usb_pd->selected_pdo.voltage  = (pdos[0].volt * 50) / 1000;
+	}
+}
--- a/bootloader/hos/fss.h
+++ b/bootloader/hos/fss.h
@@ -1,5 +1,7 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * USB-PD driver for Nintendo Switch's TI BM92T36
+ *
+ * Copyright (c) 2020 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -14,21 +16,27 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

-#ifndef _FSS_H_
-#define _FSS_H_
+#ifndef __BM92T36_H_
+#define __BM92T36_H_

-#include "hos.h"
+#include <utils/types.h>

-typedef struct _fss0_sept_t
+#define BM92T36_I2C_ADDR 0x18
+
+typedef struct _usb_pd_object_t
 {
-	u32 kb;
-	ini_sec_t *cfg_sec;
-	void *sept_primary;
-	void *sept_secondary;
+	u32 amperage;
+	u32 voltage;
+} usb_pd_object_t;

-} fss0_sept_t;
+typedef struct _usb_pd_objects_t
+{
+	u32 pdo_no;
+	usb_pd_object_t pdos[7];
+	usb_pd_object_t selected_pdo;
+} usb_pd_objects_t;

-int parse_fss(launch_ctxt_t *ctxt, const char *path, fss0_sept_t *sept_ctxt);
-int load_sept_from_ffs0(fss0_sept_t *sept_ctxt);
+int  bm92t36_get_version(u32 *value);
+void bm92t36_get_source_info(bool *inserted, usb_pd_objects_t *usb_pd);

 #endif
--- a/bdk/power/bq24193.c
+++ b/bdk/power/bq24193.c
@@ -1,7 +1,7 @@
 /*
 * Battery charger driver for Nintendo Switch's TI BQ24193
 *
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -25,131 +25,144 @@ static u8 bq24193_get_reg(u8 reg)
 	return i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, reg);
 }

+int bq24193_get_version(u32 *value)
+{
+	u16 data = bq24193_get_reg(BQ24193_VendorPart);
+	if (value)
+		*value = data;
+
+	if (data == 0x2F)
+		return 0;
+	else
+		return 1;
+}
+
 int bq24193_get_property(enum BQ24193_reg_prop prop, int *value)
 {
 	u8 data;

-	switch (prop) {
-		case BQ24193_InputVoltageLimit: // Input voltage limit (mV).
-			data = bq24193_get_reg(BQ24193_InputSource);
-			data = (data & BQ24193_INCONFIG_VINDPM_MASK) >> 3;
-			*value = 0;
-			*value += ((data >> 0) & 1) ? 80 : 0;
-			*value += ((data >> 1) & 1) ? 160 : 0;
-			*value += ((data >> 2) & 1) ? 320 : 0;
-			*value += ((data >> 3) & 1) ? 640 : 0;
-			*value += 3880;
+	switch (prop)
+	{
+	case BQ24193_InputVoltageLimit: // Input voltage limit (mV).
+		data = bq24193_get_reg(BQ24193_InputSource);
+		data = (data & BQ24193_INCONFIG_VINDPM_MASK) >> 3;
+		*value = 0;
+		*value += ((data >> 0) & 1) ? 80 : 0;
+		*value += ((data >> 1) & 1) ? 160 : 0;
+		*value += ((data >> 2) & 1) ? 320 : 0;
+		*value += ((data >> 3) & 1) ? 640 : 0;
+		*value += 3880;
+		break;
+	case BQ24193_InputCurrentLimit: // Input current limit (mA).
+		data = bq24193_get_reg(BQ24193_InputSource);
+		data &= BQ24193_INCONFIG_INLIMIT_MASK;
+		switch (data)
+		{
+		case 0:
+			*value = 100;
 			break;
-		case BQ24193_InputCurrentLimit: // Input current limit (mA).
-			data = bq24193_get_reg(BQ24193_InputSource);
-			data &= BQ24193_INCONFIG_INLIMIT_MASK;
-			switch (data)
-			{
-			case 0:
-				*value = 100;
-				break;
-			case 1:
-				*value = 150;
-				break;
-			case 2:
-				*value = 500;
-				break;
-			case 3:
-				*value = 900;
-				break;
-			case 4:
-				*value = 1200;
-				break;
-			case 5:
-				*value = 1500;
-				break;
-			case 6:
-				*value = 2000;
-				break;
-			case 7:
-				*value = 3000;
-				break;
-			}
+		case 1:
+			*value = 150;
 			break;
-		case BQ24193_SystemMinimumVoltage: // Minimum system voltage limit (mV).
-			data = bq24193_get_reg(BQ24193_PORConfig);
-			*value = (data & BQ24193_PORCONFIG_SYSMIN_MASK) >> 1;
-			*value *= 100;
-			*value += 3000;
+		case 2:
+			*value = 500;
 			break;
-		case BQ24193_FastChargeCurrentLimit: // Fast charge current limit (mA).
-			data = bq24193_get_reg(BQ24193_ChrgCurr);
-			data = (data & BQ24193_CHRGCURR_ICHG_MASK) >> 2;
-			*value = 0;
-			*value += ((data >> 0) & 1) ? 64 : 0;
-			*value += ((data >> 1) & 1) ? 128 : 0;
-			*value += ((data >> 2) & 1) ? 256 : 0;
-			*value += ((data >> 3) & 1) ? 512 : 0;
-			*value += ((data >> 4) & 1) ? 1024 : 0;
-			*value += ((data >> 5) & 1) ? 2048 : 0;
-			*value += 512;
-			data = bq24193_get_reg(BQ24193_ChrgCurr);
-			data &= BQ24193_CHRGCURR_20PCT_MASK;
-			if (data)
-				*value = *value * 20 / 100; // Fast charge current limit is 20%.
+		case 3:
+			*value = 900;
 			break;
-		case BQ24193_ChargeVoltageLimit: // Charge voltage limit (mV).
-			data = bq24193_get_reg(BQ24193_ChrgVolt);
-			data = (data & BQ24193_CHRGVOLT_VREG) >> 2;
-			*value = 0;
-			*value += ((data >> 0) & 1) ? 16 : 0;
-			*value += ((data >> 1) & 1) ? 32 : 0;
-			*value += ((data >> 2) & 1) ? 64 : 0;
-			*value += ((data >> 3) & 1) ? 128 : 0;
-			*value += ((data >> 4) & 1) ? 256 : 0;
-			*value += ((data >> 5) & 1) ? 512 : 0;
-			*value += 3504;
+		case 4:
+			*value = 1200;
 			break;
-		case BQ24193_RechargeThreshold: // Recharge voltage threshold less than voltage limit (mV).
-			data = bq24193_get_reg(BQ24193_ChrgVolt);
-			data &= BQ24193_IRTHERMAL_THERM_MASK;
-			if (data)
-				*value = 300;
-			else
-				*value = 100;
+		case 5:
+			*value = 1500;
 			break;
-		case BQ24193_ThermalRegulation: // Thermal regulation threshold (oC).
-			data = bq24193_get_reg(BQ24193_IRCompThermal);
-			data &= BQ24193_IRTHERMAL_THERM_MASK;
-			switch (data)
-			{
-			case 0:
-				*value = 60;
-				break;
-			case 1:
-				*value = 80;
-				break;
-			case 2:
-				*value = 100;
-				break;
-			case 3:
-				*value = 120;
-				break;
-			}
+		case 6:
+			*value = 2000;
 			break;
-		case BQ24193_ChargeStatus: // 0: Not charging, 1: Pre-charge, 2: Fast charging, 3: Charge termination done
-			data = bq24193_get_reg(BQ24193_Status);
-			*value = (data & BQ24193_STATUS_CHRG_MASK) >> 4;
+		case 7:
+			*value = 3000;
 			break;
-		case BQ24193_TempStatus: // 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot.
-			data = bq24193_get_reg(BQ24193_FaultReg);
-			*value = data & BQ24193_FAULT_THERM_MASK;
+		}
+		break;
+	case BQ24193_SystemMinimumVoltage: // Minimum system voltage limit (mV).
+		data = bq24193_get_reg(BQ24193_PORConfig);
+		*value = (data & BQ24193_PORCONFIG_SYSMIN_MASK) >> 1;
+		*value *= 100;
+		*value += 3000;
+		break;
+	case BQ24193_FastChargeCurrentLimit: // Fast charge current limit (mA).
+		data = bq24193_get_reg(BQ24193_ChrgCurr);
+		data = (data & BQ24193_CHRGCURR_ICHG_MASK) >> 2;
+		*value = 0;
+		*value += ((data >> 0) & 1) ? 64 : 0;
+		*value += ((data >> 1) & 1) ? 128 : 0;
+		*value += ((data >> 2) & 1) ? 256 : 0;
+		*value += ((data >> 3) & 1) ? 512 : 0;
+		*value += ((data >> 4) & 1) ? 1024 : 0;
+		*value += ((data >> 5) & 1) ? 2048 : 0;
+		*value += 512;
+		data = bq24193_get_reg(BQ24193_ChrgCurr);
+		data &= BQ24193_CHRGCURR_20PCT_MASK;
+		if (data)
+			*value = *value * 20 / 100; // Fast charge current limit is 20%.
+		break;
+	case BQ24193_ChargeVoltageLimit: // Charge voltage limit (mV).
+		data = bq24193_get_reg(BQ24193_ChrgVolt);
+		data = (data & BQ24193_CHRGVOLT_VREG) >> 2;
+		*value = 0;
+		*value += ((data >> 0) & 1) ? 16 : 0;
+		*value += ((data >> 1) & 1) ? 32 : 0;
+		*value += ((data >> 2) & 1) ? 64 : 0;
+		*value += ((data >> 3) & 1) ? 128 : 0;
+		*value += ((data >> 4) & 1) ? 256 : 0;
+		*value += ((data >> 5) & 1) ? 512 : 0;
+		*value += 3504;
+		break;
+	case BQ24193_RechargeThreshold: // Recharge voltage threshold less than voltage limit (mV).
+		data = bq24193_get_reg(BQ24193_ChrgVolt);
+		data &= BQ24193_IRTHERMAL_THERM_MASK;
+		if (data)
+			*value = 300;
+		else
+			*value = 100;
+		break;
+	case BQ24193_ThermalRegulation: // Thermal regulation threshold (oC).
+		data = bq24193_get_reg(BQ24193_IRCompThermal);
+		data &= BQ24193_IRTHERMAL_THERM_MASK;
+		switch (data)
+		{
+		case 0:
+			*value = 60;
 			break;
-		case BQ24193_DevID: // Dev ID.
-			data = bq24193_get_reg(BQ24193_VendorPart);
-			*value = data & BQ24193_VENDORPART_DEV_MASK;
+		case 1:
+			*value = 80;
 			break;
-		case BQ24193_ProductNumber: // Product number.
-			data = bq24193_get_reg(BQ24193_VendorPart);
-			*value = (data & BQ24193_VENDORPART_PN_MASK) >> 3;
+		case 2:
+			*value = 100;
 			break;
-		default:
-			return -1;
+		case 3:
+			*value = 120;
+			break;
+		}
+		break;
+	case BQ24193_ChargeStatus: // 0: Not charging, 1: Pre-charge, 2: Fast charging, 3: Charge termination done
+		data = bq24193_get_reg(BQ24193_Status);
+		*value = (data & BQ24193_STATUS_CHRG_MASK) >> 4;
+		break;
+	case BQ24193_TempStatus: // 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot.
+		data = bq24193_get_reg(BQ24193_FaultReg);
+		*value = data & BQ24193_FAULT_THERM_MASK;
+		break;
+	case BQ24193_DevID: // Dev ID.
+		data = bq24193_get_reg(BQ24193_VendorPart);
+		*value = data & BQ24193_VENDORPART_DEV_MASK;
+		break;
+	case BQ24193_ProductNumber: // Product number.
+		data = bq24193_get_reg(BQ24193_VendorPart);
+		*value = (data & BQ24193_VENDORPART_PN_MASK) >> 3;
+		break;
+	default:
+		return 1;
 	}
 	return 0;
 }
--- a/bdk/power/bq24193.h
+++ b/bdk/power/bq24193.h
@@ -19,6 +19,8 @@
 #ifndef __BQ24193_H_
 #define __BQ24193_H_

+#include <utils/types.h>
+
 #define BQ24193_I2C_ADDR 0x6B

 // REG 0 masks.
@@ -28,7 +30,7 @@

 // REG 1 masks.
 #define BQ24193_PORCONFIG_BOOST_MASK       (1<<0)
-#define BQ24193_PORCONFIG_SYSMIN_MASK      (7<<1)
+#define BQ24193_PORCONFIG_SYSMIN_MASK      (7<<1) // 3000uV HOS default.
 #define BQ24193_PORCONFIG_CHGCONFIG_MASK   (3<<4)
 #define BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN (1<<4)
 #define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1<<6)
@@ -114,7 +116,8 @@ enum BQ24193_reg_prop {
 	BQ24193_ProductNumber,          // REG A.
 };

-int bq24193_get_property(enum BQ24193_reg_prop prop, int *value);
+int  bq24193_get_version(u32 *value);
+int  bq24193_get_property(enum BQ24193_reg_prop prop, int *value);
 void bq24193_enable_charger();
 void bq24193_fake_battery_removal();

--- a/bdk/power/max17050.c
+++ b/bdk/power/max17050.c
@@ -3,7 +3,7 @@
 *
 * Copyright (c) 2011 Samsung Electronics
 * MyungJoo Ham <myungjoo.ham@samsung.com>
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -24,31 +24,33 @@

 #include "max17050.h"
 #include <soc/i2c.h>
-#include <utils/util.h>
+#include <soc/timer.h>
+
+/* Board default values */
+#define BOARD_CGAIN       2 /* Actual: 1.99993 */
+#define BOARD_RSENSE_MOHM 5 /* 0.005 Ohm */
+#define ADJ_RSENSE_MOHM   (BOARD_RSENSE_MOHM * BOARD_CGAIN) /* 0.01 Ohm */
+
+/* Consider RepCap which is less then 10 units below FullCAP full */
+#define FULL_THRESHOLD 10

 /* Status register bits */
-#define STATUS_POR_BIT (1 << 1)
-#define STATUS_BST_BIT (1 << 3)
-#define STATUS_VMN_BIT (1 << 8)
-#define STATUS_TMN_BIT (1 << 9)
-#define STATUS_SMN_BIT (1 << 10)
-#define STATUS_BI_BIT  (1 << 11)
-#define STATUS_VMX_BIT (1 << 12)
-#define STATUS_TMX_BIT (1 << 13)
-#define STATUS_SMX_BIT (1 << 14)
-#define STATUS_BR_BIT  (1 << 15)
+#define STATUS_POR_BIT BIT(1)
+#define STATUS_BST_BIT BIT(3)
+#define STATUS_VMN_BIT BIT(8)
+#define STATUS_TMN_BIT BIT(9)
+#define STATUS_SMN_BIT BIT(10)
+#define STATUS_BI_BIT  BIT(11)
+#define STATUS_VMX_BIT BIT(12)
+#define STATUS_TMX_BIT BIT(13)
+#define STATUS_SMX_BIT BIT(14)
+#define STATUS_BR_BIT  BIT(15)

 #define VFSOC0_LOCK   0x0000
 #define VFSOC0_UNLOCK 0x0080

 #define MAX17050_VMAX_TOLERANCE 50 /* 50 mV */

-static u32 battery_voltage = 0;
-u32 max17050_get_cached_batt_volt()
-{
-	return battery_voltage;
-}
-
 static u16 max17050_get_reg(u8 reg)
 {
 	u16 data = 0;
@@ -58,6 +60,18 @@ static u16 max17050_get_reg(u8 reg)
 	return data;
 }

+int max17050_get_version(u32 *value)
+{
+	u16 data = max17050_get_reg(MAX17050_DevName);
+	if (value)
+		*value = data;
+
+	if (data == 0x00AC)
+		return 0;
+	else
+		return 1;
+}
+
 int max17050_get_property(enum MAX17050_reg reg, int *value)
 {
 	u16 data;
@@ -85,31 +99,30 @@ int max17050_get_property(enum MAX17050_reg reg, int *value)
 		break;
 	case MAX17050_VCELL: // Voltage now.
 		data = max17050_get_reg(MAX17050_VCELL);
-		*value = data * 625 / 8 / 1000;
-		battery_voltage = *value;
+		*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
 		break;
 	case MAX17050_AvgVCELL: // Voltage avg.
 		data = max17050_get_reg(MAX17050_AvgVCELL);
-		*value = data * 625 / 8 / 1000;
+		*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
 		break;
 	case MAX17050_OCVInternal: // Voltage ocv.
 		data = max17050_get_reg(MAX17050_OCVInternal);
-		*value = data * 625 / 8 / 1000;
+		*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
 		break;
 	case MAX17050_RepSOC: // Capacity %.
 		*value = max17050_get_reg(MAX17050_RepSOC);
 		break;
 	case MAX17050_DesignCap: // Charge full design.
 		data = max17050_get_reg(MAX17050_DesignCap);
-		*value = data * 5 / 10;
+		*value = (u32)data * 5 / ADJ_RSENSE_MOHM; /* Units of LSB = 5uVh / Rsense = 0.5mAh */
 		break;
 	case MAX17050_FullCAP: // Charge full.
 		data = max17050_get_reg(MAX17050_FullCAP);
-		*value = data * 5 / 10;
+		*value = (u32)data * 5 / ADJ_RSENSE_MOHM; /* Units of LSB = 5uVh / Rsense = 0.5mAh */
 		break;
 	case MAX17050_RepCap: // Charge now.
 		data = max17050_get_reg(MAX17050_RepCap);
-		*value = data * 5 / 10;
+		*value = (u32)data * 5 / ADJ_RSENSE_MOHM; /* Units of LSB = 5uVh / Rsense = 0.5mAh */
 		break;
 	case MAX17050_TEMP: // Temp.
 		data = max17050_get_reg(MAX17050_TEMP);
@@ -118,16 +131,14 @@ int max17050_get_property(enum MAX17050_reg reg, int *value)
 		break;
 	case MAX17050_Current: // Current now.
 		data = max17050_get_reg(MAX17050_Current);
-		*value = (s16)data;
-		*value *= 1562500 / MAX17050_DEFAULT_SNS_RESISTOR;
+		*value = (int)(s16)data * 15625 / ADJ_RSENSE_MOHM / 10; /* Units of LSB = 1.5625uV / Rsense = 156.25uA */
 		break;
 	case MAX17050_AvgCurrent: // Current avg.
 		data = max17050_get_reg(MAX17050_AvgCurrent);
-		*value = (s16)data;
-		*value *= 1562500 / MAX17050_DEFAULT_SNS_RESISTOR;
+		*value = (int)(s16)data * 15625 / ADJ_RSENSE_MOHM / 10; /* Units of LSB = 1.5625uV / Rsense = 156.25uA */
 		break;
 	default:
-		return -1;
+		return 1;
 	}
 	return 0;
 }
@@ -136,18 +147,14 @@ static int _max17050_write_verify_reg(u8 reg, u16 value)
 {
 	int retries = 8;
 	int ret;
-	u16 read_value;

 	do
 	{
 		ret = i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, reg, (u8 *)&value, 2);
-		read_value = max17050_get_reg(reg);
-		if (read_value != value)
-		{
-			ret = -1;
-			retries--;
-		}
-	} while (retries && read_value != value);
+		u16 read_value = max17050_get_reg(reg);
+		if (!ret && read_value == value)
+			break;
+	} while (--retries);

 	return ret;
 }
@@ -240,7 +247,7 @@ static void _max17050_set_por_bit(u16 value)
 	_max17050_write_verify_reg(MAX17050_STATUS, value);
 }

-int max17050_fix_configuration()
+void max17050_fix_configuration()
 {
 	/* Init phase, set the POR bit */
 	_max17050_set_por_bit(STATUS_POR_BIT);
@@ -274,6 +281,27 @@ int max17050_fix_configuration()

 	// Sets POR, BI, BR.
 	_max17050_set_por_bit(0x8801);
-
-	return 0;
+}
+
+void max17050_dump_regs(void *buf)
+{
+	u16 *buff = (u16 *)buf;
+
+	// Unlock model table.
+	u16 unlock = 0x59;
+	i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable1, (u8 *)&unlock, 2);
+	unlock = 0xC4;
+	i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable2, (u8 *)&unlock, 2);
+
+	// Dump all battery fuel gauge registers.
+	for (u32 i = 0; i < 0x100; i++)
+	{
+		buff[i] = max17050_get_reg(i);
+		msleep(1);
+	}
+
+	// Lock model table.
+	unlock = 0;
+	i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable1, (u8 *)&unlock, 2);
+	i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable2, (u8 *)&unlock, 2);
 }
--- a/bdk/power/max17050.h
+++ b/bdk/power/max17050.h
@@ -1,6 +1,5 @@
 /*
 * Fuel gauge driver for Nintendo Switch's Maxim 17050
- *  Note that Maxim 8966 and 8997 are mfd and this is its subdevice.
 *
 * Copyright (c) 2011 Samsung Electronics
 * MyungJoo Ham <myungjoo.ham@samsung.com>
@@ -26,14 +25,6 @@

 #include <utils/types.h>

-#define MAX17050_STATUS_BattAbsent    (1 << 3)
-#define MAX17050_DEFAULT_SNS_RESISTOR 10000
-
-/* Consider RepCap which is less then 10 units below FullCAP full */
-#define MAX17050_FULL_THRESHOLD 10
-
-#define MAX17050_CHARACTERIZATION_DATA_SIZE 48
-
 #define MAXIM17050_I2C_ADDR 0x36

 enum MAX17050_reg {
@@ -128,8 +119,9 @@ enum MAX17050_reg {
 	MAX17050_VFSOC			= 0xFF,
 };

-int max17050_get_property(enum MAX17050_reg reg, int *value);
-int max17050_fix_configuration();
-u32 max17050_get_cached_batt_volt();
+int  max17050_get_version(u32 *value);
+int  max17050_get_property(enum MAX17050_reg reg, int *value);
+void max17050_fix_configuration();
+void max17050_dump_regs(void *buf);

 #endif /* __MAX17050_H_ */
--- a/bdk/power/max77620.h
+++ b/bdk/power/max77620.h
@@ -1,8 +1,7 @@
 /*
 * Defining registers address and its bit definitions of MAX77620 and MAX20024
 *
- * Copyright (c) 2016 NVIDIA CORPORATION. All rights reserved.
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2020 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -16,13 +15,7 @@

 /* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
 #define MAX77620_REG_CNFGGLBL1      0x00
-#define  MAX77620_CNFGGLBL1_LBDAC_EN          (1 << 7)
-#define  MAX77620_CNFGGLBL1_MPPLD             (1 << 6)
-#define  MAX77620_CNFGGLBL1_LBHYST            ((1 << 5) | (1 << 4))
-#define  MAX77620_CNFGGLBL1_LBHYST_100        (0 << 4)
-#define  MAX77620_CNFGGLBL1_LBHYST_200        (1 << 4)
-#define  MAX77620_CNFGGLBL1_LBHYST_300        (2 << 4)
-#define  MAX77620_CNFGGLBL1_LBHYST_400        (3 << 4)
+#define  MAX77620_CNFGGLBL1_LBRSTEN           BIT(0)
 #define  MAX77620_CNFGGLBL1_LBDAC_MASK        0x0E
 #define  MAX77620_CNFGGLBL1_LBDAC_2700        (0 << 1)
 #define  MAX77620_CNFGGLBL1_LBDAC_2800        (1 << 1)
@@ -32,30 +25,45 @@
 #define  MAX77620_CNFGGLBL1_LBDAC_3200        (5 << 1)
 #define  MAX77620_CNFGGLBL1_LBDAC_3300        (6 << 1)
 #define  MAX77620_CNFGGLBL1_LBDAC_3400        (7 << 1)
-#define  MAX77620_CNFGGLBL1_LBRSTEN           (1 << 0)
+#define  MAX77620_CNFGGLBL1_LBHYST_100        (0 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_200        (1 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_300        (2 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_400        (3 << 4)
+#define  MAX77620_CNFGGLBL1_MPPLD             BIT(6)
+#define  MAX77620_CNFGGLBL1_LBDAC_EN          BIT(7)

 #define MAX77620_REG_CNFGGLBL2      0x01
-#define MAX77620_REG_CNFGGLBL3      0x02
-#define  MAX77620_WDTC_MASK                   0x3
-#define  MAX77620_WDTOFFC                     (1 << 4)
-#define  MAX77620_WDTSLPC                     (1 << 3)
-#define  MAX77620_WDTEN                       (1 << 2)
 #define  MAX77620_TWD_MASK                    0x3
 #define  MAX77620_TWD_2s                      0x0
 #define  MAX77620_TWD_16s                     0x1
 #define  MAX77620_TWD_64s                     0x2
 #define  MAX77620_TWD_128s                    0x3
+#define  MAX77620_WDTEN                       BIT(2)
+#define  MAX77620_WDTSLPC                     BIT(3)
+#define  MAX77620_WDTOFFC                     BIT(4)
+#define  MAX77620_GLBL_LPM                    BIT(5)
+#define  MAX77620_I2CTWD_MASK                 0xC0
+#define  MAX77620_I2CTWD_DISABLED             0x00
+#define  MAX77620_I2CTWD_1_33ms               0x40
+#define  MAX77620_I2CTWD_35_7ms               0x80
+#define  MAX77620_I2CTWD_41_7ms               0xC0
+
+#define MAX77620_REG_CNFGGLBL3      0x02
+#define  MAX77620_WDTC_MASK                   0x3

 #define MAX77620_REG_CNFG1_32K      0x03
-#define  MAX77620_CNFG1_32K_OUT0_EN           (1 << 2)
+#define  MAX77620_CNFG1_PWR_MD_32K_MASK       0x3
+#define  MAX77620_CNFG1_32K_OUT0_EN           BIT(2)
+#define  MAX77620_CNFG1_32KLOAD_MASK          0x30
+#define  MAX77620_CNFG1_32K_OK                BIT(7)

 #define MAX77620_REG_CNFGBBC        0x04
-#define  MAX77620_CNFGBBC_ENABLE              (1 << 0)
+#define  MAX77620_CNFGBBC_ENABLE              BIT(0)
 #define  MAX77620_CNFGBBC_CURRENT_MASK        0x06
 #define  MAX77620_CNFGBBC_CURRENT_SHIFT       1
 #define  MAX77620_CNFGBBC_VOLTAGE_MASK        0x18
 #define  MAX77620_CNFGBBC_VOLTAGE_SHIFT       3
-#define  MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5)
+#define  MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
 #define  MAX77620_CNFGBBC_RESISTOR_MASK       0xC0
 #define  MAX77620_CNFGBBC_RESISTOR_SHIFT      6
 #define  MAX77620_CNFGBBC_RESISTOR_100        (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
@@ -64,37 +72,63 @@
 #define  MAX77620_CNFGBBC_RESISTOR_6K         (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)

 #define MAX77620_REG_IRQTOP         0x05
-#define  MAX77620_IRQ_TOP_GLBL_MASK           (1 << 7)
-#define  MAX77620_IRQ_TOP_SD_MASK             (1 << 6)
-#define  MAX77620_IRQ_TOP_LDO_MASK            (1 << 5)
-#define  MAX77620_IRQ_TOP_GPIO_MASK           (1 << 4)
-#define  MAX77620_IRQ_TOP_RTC_MASK            (1 << 3)
-#define  MAX77620_IRQ_TOP_32K_MASK            (1 << 2)
-#define  MAX77620_IRQ_TOP_ONOFF_MASK          (1 << 1)
+#define MAX77620_REG_IRQTOPM        0x0D
+#define  MAX77620_IRQ_TOP_ONOFF_MASK          BIT(1)
+#define  MAX77620_IRQ_TOP_32K_MASK            BIT(2)
+#define  MAX77620_IRQ_TOP_RTC_MASK            BIT(3)
+#define  MAX77620_IRQ_TOP_GPIO_MASK           BIT(4)
+#define  MAX77620_IRQ_TOP_LDO_MASK            BIT(5)
+#define  MAX77620_IRQ_TOP_SD_MASK             BIT(6)
+#define  MAX77620_IRQ_TOP_GLBL_MASK           BIT(7)

 #define MAX77620_REG_INTLBT         0x06
-#define MAX77620_REG_IRQTOPM        0x0D
-#define  MAX77620_IRQ_LBM_MASK                (1 << 3)
-#define  MAX77620_IRQ_TJALRM1_MASK            (1 << 2)
-#define  MAX77620_IRQ_TJALRM2_MASK            (1 << 1)
+#define MAX77620_REG_INTENLBT       0x0E
+#define  MAX77620_IRQ_GLBLM_MASK              BIT(0)
+#define  MAX77620_IRQ_TJALRM2_MASK            BIT(1)
+#define  MAX77620_IRQ_TJALRM1_MASK            BIT(2)
+#define  MAX77620_IRQ_LBM_MASK                BIT(3)

 #define MAX77620_REG_IRQSD          0x07
-#define MAX77620_REG_IRQ_LVL2_L0_7  0x08
-#define MAX77620_REG_IRQ_LVL2_L8    0x09
-#define MAX77620_REG_IRQ_LVL2_GPIO  0x0A
-#define MAX77620_REG_ONOFFIRQ       0x0B
-#define MAX77620_REG_NVERC          0x0C
-
-#define MAX77620_REG_INTENLBT       0x0E
-#define  MAX77620_GLBLM_MASK                  (1 << 0)
-
 #define MAX77620_REG_IRQMASKSD      0x0F
+#define  MAX77620_IRQSD_PFI_SD3               BIT(4)
+#define  MAX77620_IRQSD_PFI_SD2               BIT(5)
+#define  MAX77620_IRQSD_PFI_SD1               BIT(6)
+#define  MAX77620_IRQSD_PFI_SD0               BIT(7)
+
+#define MAX77620_REG_IRQ_LVL2_L0_7  0x08 // LDO number that irq occurred.
 #define MAX77620_REG_IRQ_MSK_L0_7   0x10
+#define MAX77620_REG_IRQ_LVL2_L8    0x09 // LDO number that irq occurred. Only bit0: LDO8 is valid.
 #define MAX77620_REG_IRQ_MSK_L8     0x11
+#define MAX77620_REG_IRQ_LVL2_GPIO  0x0A // Edge detection interrupt.
+
+#define MAX77620_REG_ONOFFIRQ       0x0B
 #define MAX77620_REG_ONOFFIRQM      0x12
+#define  MAX77620_ONOFFIRQ_MRWRN              BIT(0)
+#define  MAX77620_ONOFFIRQ_EN0_1SEC           BIT(1)
+#define  MAX77620_ONOFFIRQ_EN0_F              BIT(2)
+#define  MAX77620_ONOFFIRQ_EN0_R              BIT(3)
+#define  MAX77620_ONOFFIRQ_LID_F              BIT(4)
+#define  MAX77620_ONOFFIRQ_LID_R              BIT(5)
+#define  MAX77620_ONOFFIRQ_ACOK_F             BIT(6)
+#define  MAX77620_ONOFFIRQ_ACOK_R             BIT(7)
+
+#define MAX77620_REG_NVERC          0x0C // Shutdown reason (non-volatile).
+#define  MAX77620_NVERC_SHDN                  BIT(0)
+#define  MAX77620_NVERC_WTCHDG                BIT(1)
+#define  MAX77620_NVERC_HDRST                 BIT(2)
+#define  MAX77620_NVERC_TOVLD                 BIT(3)
+#define  MAX77620_NVERC_MBLSD                 BIT(4)
+#define  MAX77620_NVERC_MBO                   BIT(5)
+#define  MAX77620_NVERC_MBU                   BIT(6)
+#define  MAX77620_NVERC_RSTIN                 BIT(7)
+
 #define MAX77620_REG_STATLBT        0x13
 #define MAX77620_REG_STATSD         0x14
+
 #define MAX77620_REG_ONOFFSTAT      0x15
+#define  MAX77620_ONOFFSTAT_LID     BIT(0)
+#define  MAX77620_ONOFFSTAT_ACOK    BIT(1)
+#define  MAX77620_ONOFFSTAT_EN0     BIT(2)

 /* SD and LDO Registers */
 #define MAX77620_REG_SD0            0x16
@@ -102,18 +136,42 @@
 #define MAX77620_REG_SD2            0x18
 #define MAX77620_REG_SD3            0x19
 #define MAX77620_REG_SD4            0x1A
-#define  MAX77620_SDX_VOLT_MASK               0xFF
-#define  MAX77620_SD0_VOLT_MASK               0x3F
-#define  MAX77620_SD1_VOLT_MASK               0x7F
-#define  MAX77620_LDO_VOLT_MASK               0x3F
 #define MAX77620_REG_DVSSD0         0x1B
 #define MAX77620_REG_DVSSD1         0x1C
+#define  MAX77620_SDX_VOLT_MASK               0xFF
+#define  MAX77620_SD0_VOLT_MASK               0x7F // Max is 0x40.
+#define  MAX77620_SD1_VOLT_MASK               0x7F // Max is 0x4C.
+#define  MAX77620_LDO_VOLT_MASK               0x3F
+
 #define MAX77620_REG_SD0_CFG        0x1D
 #define MAX77620_REG_SD1_CFG        0x1E
 #define MAX77620_REG_SD2_CFG        0x1F
 #define MAX77620_REG_SD3_CFG        0x20
 #define MAX77620_REG_SD4_CFG        0x21
+#define  MAX77620_SD_SR_MASK                  0xC0
+#define  MAX77620_SD_SR_SHIFT                 6
+#define  MAX77620_SD_POWER_MODE_MASK          0x30
+#define  MAX77620_SD_POWER_MODE_SHIFT         4
+#define  MAX77620_SD_CFG1_ADE_MASK            BIT(3)
+#define  MAX77620_SD_CFG1_ADE_DISABLE         0
+#define  MAX77620_SD_CFG1_ADE_ENABLE          BIT(3)
+#define  MAX77620_SD_FPWM_MASK                0x04
+#define  MAX77620_SD_FPWM_SHIFT               2
+#define  MAX77620_SD_FSRADE_MASK              0x01
+#define  MAX77620_SD_FSRADE_SHIFT             0
+#define  MAX77620_SD_CFG1_FPWM_SD_MASK        BIT(2)
+#define  MAX77620_SD_CFG1_FPWM_SD_SKIP        0
+#define  MAX77620_SD_CFG1_FPWM_SD_FPWM        BIT(2)
+#define  MAX77620_SD_CFG1_MPOK_MASK           BIT(1)
+#define  MAX77620_SD_CFG1_FSRADE_SD_MASK      BIT(0)
+#define  MAX77620_SD_CFG1_FSRADE_SD_DISABLE   0
+#define  MAX77620_SD_CFG1_FSRADE_SD_ENABLE    BIT(0)
+
 #define MAX77620_REG_SD_CFG2        0x22
+#define  MAX77620_SD_CNF2_RSVD                BIT(0)
+#define  MAX77620_SD_CNF2_ROVS_EN_SD1         BIT(1)
+#define  MAX77620_SD_CNF2_ROVS_EN_SD0         BIT(2)
+
 #define MAX77620_REG_LDO0_CFG       0x23
 #define MAX77620_REG_LDO0_CFG2      0x24
 #define MAX77620_REG_LDO1_CFG       0x25
@@ -132,25 +190,35 @@
 #define MAX77620_REG_LDO7_CFG2      0x32
 #define MAX77620_REG_LDO8_CFG       0x33
 #define MAX77620_REG_LDO8_CFG2      0x34
-#define  MAX77620_LDO_POWER_MODE_MASK         0xC0
+/*! LDO CFG */
 #define  MAX77620_LDO_POWER_MODE_SHIFT        6
+#define  MAX77620_LDO_POWER_MODE_MASK         (3 << MAX77620_LDO_POWER_MODE_SHIFT)
 #define  MAX77620_POWER_MODE_NORMAL	          3
 #define  MAX77620_POWER_MODE_LPM              2
 #define  MAX77620_POWER_MODE_GLPM             1
 #define  MAX77620_POWER_MODE_DISABLE          0
-#define  MAX20024_LDO_CFG2_MPOK_MASK          (1 << 2)
+/*! LDO CFG2 */
+#define  MAX77620_LDO_CFG2_SS_MASK            (1 << 0)
+#define  MAX77620_LDO_CFG2_SS_FAST            (0 << 0)
+#define  MAX77620_LDO_CFG2_SS_SLOW            (1 << 0)
 #define  MAX77620_LDO_CFG2_ADE_MASK           (1 << 1)
 #define  MAX77620_LDO_CFG2_ADE_DISABLE        (0 << 1)
 #define  MAX77620_LDO_CFG2_ADE_ENABLE         (1 << 1)
-#define  MAX77620_LDO_CFG2_SS_MASK            (1 << 0)
-#define  MAX77620_LDO_CFG2_SS_FAST            (1 << 0)
-#define  MAX77620_LDO_CFG2_SS_SLOW            0
+#define  MAX77620_LDO_CFG2_MPOK_MASK          BIT(2)
+#define  MAX77620_LDO_CFG2_POK_MASK           BIT(3)
+#define  MAX77620_LDO_CFG2_COMP_SHIFT         4
+#define  MAX77620_LDO_CFG2_COMP_MASK          (3 << MAX77620_LDO_COMP_SHIFT)
+#define  MAX77620_LDO_CFG2_COMP_SLOW 	      3
+#define  MAX77620_LDO_CFG2_COMP_MID_SLOW      2
+#define  MAX77620_LDO_CFG2_COMP_MID_FAST      1
+#define  MAX77620_LDO_CFG2_COMP_FAST          0
+#define  MAX77620_LDO_CFG2_ALPM_EN_MASK       BIT(6)
+#define  MAX77620_LDO_CFG2_OVCLMP_MASK        BIT(7)

 #define MAX77620_REG_LDO_CFG3       0x35
-#define  MAX77620_TRACK4_MASK                 (1 << 5)
+#define  MAX77620_LDO_BIAS_EN                 BIT(0)
 #define  MAX77620_TRACK4_SHIFT                5
-
-#define MAX77620_LDO_SLEW_RATE_MASK 0x1
+#define  MAX77620_TRACK4_MASK                 (1 << MAX77620_TRACK4_SHIFT)

 #define MAX77620_REG_GPIO0          0x36
 #define MAX77620_REG_GPIO1          0x37
@@ -160,9 +228,6 @@
 #define MAX77620_REG_GPIO5          0x3B
 #define MAX77620_REG_GPIO6          0x3C
 #define MAX77620_REG_GPIO7          0x3D
-#define MAX77620_REG_PUE_GPIO       0x3E
-#define MAX77620_REG_PDE_GPIO       0x3F
-#define MAX77620_REG_AME_GPIO       0x40
 #define  MAX77620_CNFG_GPIO_DRV_MASK          (1 << 0)
 #define  MAX77620_CNFG_GPIO_DRV_PUSHPULL      (1 << 0)
 #define  MAX77620_CNFG_GPIO_DRV_OPENDRAIN     (0 << 0)
@@ -181,26 +246,44 @@
 #define  MAX77620_CNFG_GPIO_DBNC_8ms          (0x1 << 6)
 #define  MAX77620_CNFG_GPIO_DBNC_16ms         (0x2 << 6)
 #define  MAX77620_CNFG_GPIO_DBNC_32ms         (0x3 << 6)
+#define  MAX77620_GPIO_OUTPUT_DISABLE         0
+#define  MAX77620_GPIO_OUTPUT_ENABLE          1
+
+#define MAX77620_REG_PUE_GPIO       0x3E // Gpio Pullup resistor enable.
+#define MAX77620_REG_PDE_GPIO       0x3F // Gpio Pulldown resistor enable.
+
+#define MAX77620_REG_AME_GPIO       0x40 // Gpio pinmuxing. Clear bits are Standard GPIO.

 #define MAX77620_REG_ONOFFCNFG1     0x41
-#define  MAX77620_ONOFFCNFG1_SFT_RST          (1 << 7)
-#define  MAX77620_ONOFFCNFG1_MRT_MASK         0x38
-#define  MAX77620_ONOFFCNFG1_MRT_SHIFT        0x3
-#define  MAX77620_ONOFFCNFG1_SLPEN            (1 << 2)
-#define  MAX77620_ONOFFCNFG1_PWR_OFF          (1 << 1)
 #define  MAX20024_ONOFFCNFG1_CLRSE            0x18
+#define  MAX77620_ONOFFCNFG1_PWR_OFF          BIT(1)
+#define  MAX77620_ONOFFCNFG1_SLPEN            BIT(2)
+#define  MAX77620_ONOFFCNFG1_MRT_SHIFT        0x3
+#define  MAX77620_ONOFFCNFG1_MRT_MASK         0x38
+#define  MAX77620_ONOFFCNFG1_RSVD             BIT(6)
+#define  MAX77620_ONOFFCNFG1_SFT_RST          BIT(7)

 #define MAX77620_REG_ONOFFCNFG2     0x42
-#define  MAX77620_ONOFFCNFG2_SFT_RST_WK       (1 << 7)
-#define  MAX77620_ONOFFCNFG2_WD_RST_WK        (1 << 6)
-#define  MAX77620_ONOFFCNFG2_SLP_LPM_MSK      (1 << 5)
-#define  MAX77620_ONOFFCNFG2_WK_ALARM1        (1 << 2)
-#define  MAX77620_ONOFFCNFG2_WK_EN0           (1 << 0)
+#define  MAX77620_ONOFFCNFG2_WK_EN0           BIT(0)
+#define  MAX77620_ONOFFCNFG2_WK_ALARM2        BIT(1)
+#define  MAX77620_ONOFFCNFG2_WK_ALARM1        BIT(2)
+#define  MAX77620_ONOFFCNFG2_WK_MBATT         BIT(3) // MBATT event generates a wakeup signal. use it in android/l4t?
+#define  MAX77620_ONOFFCNFG2_WK_ACOK          BIT(4)
+#define  MAX77620_ONOFFCNFG2_SLP_LPM_MSK      BIT(5)
+#define  MAX77620_ONOFFCNFG2_WD_RST_WK        BIT(6)
+#define  MAX77620_ONOFFCNFG2_SFT_RST_WK       BIT(7)

 /* FPS Registers */
-#define MAX77620_REG_FPS_CFG0       0x43
-#define MAX77620_REG_FPS_CFG1       0x44
-#define MAX77620_REG_FPS_CFG2       0x45
+#define MAX77620_REG_FPS_CFG0       0x43 // FPS0.
+#define MAX77620_REG_FPS_CFG1       0x44 // FPS1.
+#define MAX77620_REG_FPS_CFG2       0x45 // FPS2.
+#define  MAX77620_FPS_ENFPS_SW_MASK           0x01
+#define  MAX77620_FPS_ENFPS_SW                0x01
+#define  MAX77620_FPS_EN_SRC_SHIFT            1
+#define  MAX77620_FPS_EN_SRC_MASK             0x06
+#define  MAX77620_FPS_TIME_PERIOD_SHIFT       3
+#define  MAX77620_FPS_TIME_PERIOD_MASK        0x38
+
 #define MAX77620_REG_FPS_LDO0       0x46
 #define MAX77620_REG_FPS_LDO1       0x47
 #define MAX77620_REG_FPS_LDO2       0x48
@@ -215,86 +298,48 @@
 #define MAX77620_REG_FPS_SD2        0x51
 #define MAX77620_REG_FPS_SD3        0x52
 #define MAX77620_REG_FPS_SD4        0x53
-#define MAX77620_REG_FPS_NONE       0
-#define  MAX77620_FPS_SRC_MASK                0xC0
-#define  MAX77620_FPS_SRC_SHIFT               6
-#define  MAX77620_FPS_PU_PERIOD_MASK          0x38
-#define  MAX77620_FPS_PU_PERIOD_SHIFT         3
-#define  MAX77620_FPS_PD_PERIOD_MASK          0x07
-#define  MAX77620_FPS_PD_PERIOD_SHIFT         0
-
-/* Minimum and maximum FPS period time (in microseconds) are
- * different for MAX77620 and Max20024.
- */
-#define MAX77620_FPS_COUNT 3
-
-#define MAX77620_FPS_PERIOD_MIN_US 40
-#define MAX20024_FPS_PERIOD_MIN_US 20
-
-#define MAX77620_FPS_PERIOD_MAX_US 2560
-#define MAX20024_FPS_PERIOD_MAX_US 5120
-
 #define MAX77620_REG_FPS_GPIO1      0x54
 #define MAX77620_REG_FPS_GPIO2      0x55
 #define MAX77620_REG_FPS_GPIO3      0x56
-#define  MAX77620_FPS_TIME_PERIOD_MASK        0x38
-#define  MAX77620_FPS_TIME_PERIOD_SHIFT       3
-#define  MAX77620_FPS_EN_SRC_MASK             0x06
-#define  MAX77620_FPS_EN_SRC_SHIFT            1
-#define  MAX77620_FPS_ENFPS_SW_MASK           0x01
-#define  MAX77620_FPS_ENFPS_SW                0x01
-
 #define MAX77620_REG_FPS_RSO        0x57
+#define  MAX77620_FPS_PD_PERIOD_SHIFT         0
+#define  MAX77620_FPS_PD_PERIOD_MASK          0x07
+#define  MAX77620_FPS_PU_PERIOD_SHIFT         3
+#define  MAX77620_FPS_PU_PERIOD_MASK          0x38
+#define  MAX77620_FPS_SRC_SHIFT               6
+#define  MAX77620_FPS_SRC_MASK                0xC0
+
+#define MAX77620_FPS_COUNT 3
+#define MAX77620_FPS_PERIOD_MIN_US 40
+#define MAX77620_FPS_PERIOD_MAX_US 2560
+
 #define MAX77620_REG_CID0           0x58
 #define MAX77620_REG_CID1           0x59
 #define MAX77620_REG_CID2           0x5A
 #define MAX77620_REG_CID3           0x5B
-#define MAX77620_REG_CID4           0x5C
-#define MAX77620_REG_CID5           0x5D
-
-#define MAX77620_REG_DVSSD4         0x5E
-#define MAX20024_REG_MAX_ADD        0x70
-
-#define MAX77620_CID_DIDM_MASK                0xF0
-#define MAX77620_CID_DIDM_SHIFT               4
-
-/* CNCG2SD */
-#define MAX77620_SD_CNF2_ROVS_EN_SD1          (1 << 1)
-#define MAX77620_SD_CNF2_ROVS_EN_SD0          (1 << 2)
+#define MAX77620_REG_CID4           0x5C // OTP version.
+#define MAX77620_REG_CID5           0x5D // ES version.
+#define  MAX77620_CID_DIDO_MASK               0xF
+#define  MAX77620_CID_DIDO_SHIFT              0
+#define  MAX77620_CID_DIDM_MASK               0xF0
+#define  MAX77620_CID_DIDM_SHIFT              4

 /* Device Identification Metal */
 #define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
 /* Device Indentification OTP */
 #define MAX77620_CID5_DIDO(n) ((n) & 0xF)

-/* SD CNFG1 */
-#define MAX77620_SD_SR_MASK                   0xC0
-#define MAX77620_SD_SR_SHIFT                  6
-#define MAX77620_SD_POWER_MODE_MASK           0x30
-#define MAX77620_SD_POWER_MODE_SHIFT          4
-#define MAX77620_SD_CFG1_ADE_MASK             (1 << 3)
-#define MAX77620_SD_CFG1_ADE_DISABLE          0
-#define MAX77620_SD_CFG1_ADE_ENABLE           (1 << 3)
-#define MAX77620_SD_FPWM_MASK                 0x04
-#define MAX77620_SD_FPWM_SHIFT                2
-#define MAX77620_SD_FSRADE_MASK               0x01
-#define MAX77620_SD_FSRADE_SHIFT              0
-#define MAX77620_SD_CFG1_FPWM_SD_MASK         (1 << 2)
-#define MAX77620_SD_CFG1_FPWM_SD_SKIP         0
-#define MAX77620_SD_CFG1_FPWM_SD_FPWM         (1 << 2)
-#define MAX20024_SD_CFG1_MPOK_MASK            (1 << 1)
-#define MAX77620_SD_CFG1_FSRADE_SD_MASK       (1 << 0)
-#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE    0
-#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE     (1 << 0)
+#define MAX77620_REG_DVSSD4         0x5E
+#define MAX20024_REG_MAX_ADD        0x70

-#define MAX77620_IRQ_LVL2_GPIO_EDGE0          (1 << 0)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE1          (1 << 1)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE2          (1 << 2)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE3          (1 << 3)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE4          (1 << 4)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE5          (1 << 5)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE6          (1 << 6)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE7          (1 << 7)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE0          BIT(0)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE1          BIT(1)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE2          BIT(2)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE3          BIT(3)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE4          BIT(4)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE5          BIT(5)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE6          BIT(6)
+#define MAX77620_IRQ_LVL2_GPIO_EDGE7          BIT(7)

 /* Interrupts */
 enum {
@@ -332,9 +377,4 @@ enum max77620_fps_src {
 	MAX77620_FPS_SRC_DEF,
 };

-enum max77620_chip_id {
-	MAX77620,
-	MAX20024,
-};
-
 #endif /* _MFD_MAX77620_H_ */
--- a/bdk/power/max7762x.c
+++ b/bdk/power/max7762x.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2020 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -17,161 +17,334 @@

 #include <power/max7762x.h>
 #include <power/max77620.h>
+#include <power/max77812.h>
+#include <soc/fuse.h>
 #include <soc/i2c.h>
-#include <utils/util.h>
+#include <soc/timer.h>
+#include <soc/t210.h>

-#define REGULATOR_SD 0
+#define REGULATOR_SD  0
 #define REGULATOR_LDO 1
+#define REGULATOR_BC0 2
+#define REGULATOR_BC1 3

-typedef struct _max77620_regulator_t
+typedef struct _max77620_fps_t
 {
-	u8 type;
-	const char *name;
-	u8 reg_sd;
-
-	u32 mv_step;
-	u32 mv_min;
-	u32 mv_default;
-	u32 mv_max;
-
-	u8 volt_addr;
-	u8 cfg_addr;
-
-	u8 volt_mask;
-	u8 enable_mask;
-	u8 enable_shift;
-	u8 status_mask;
-
 	u8 fps_addr;
 	u8 fps_src;
 	u8 pd_period;
 	u8 pu_period;
+} max77620_fps_t;
+
+typedef struct _max77621_ctrl_t
+{
+	u8 ctrl1_por;
+	u8 ctrl1_hos;
+	u8 ctrl2_por;
+	u8 ctrl2_hos;
+} max77621_ctrl_t;
+
+typedef struct _max77812_ctrl_t
+{
+	u8 mask;
+	u8 shift;
+	u8 rsvd0;
+	u8 rsvd1;
+} max77812_en_t;
+
+typedef struct _max77620_regulator_t
+{
+	const char *name;
+
+	u32 uv_step;
+	u32 uv_min;
+	u32 uv_default;
+	u32 uv_max;
+
+	u8 type;
+	u8 volt_addr;
+	u8 cfg_addr;
+	u8 volt_mask;
+
+	union {
+		max77620_fps_t fps;
+		max77621_ctrl_t ctrl;
+		max77812_en_t enable;
+	};
 } max77620_regulator_t;

 static const max77620_regulator_t _pmic_regulators[] = {
-	{  REGULATOR_SD,  "sd0", 0x16,  12500, 600000,  625000, 1400000,      MAX77620_REG_SD0,   MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x80,  MAX77620_REG_FPS_SD0,  1, 7, 1 },
-	{  REGULATOR_SD,  "sd1", 0x17,  12500, 600000, 1125000, 1125000,      MAX77620_REG_SD1,   MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x40,  MAX77620_REG_FPS_SD1,  0, 1, 5 },
-	{  REGULATOR_SD,  "sd2", 0x18,  12500, 600000, 1325000, 1350000,      MAX77620_REG_SD2,   MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x20,  MAX77620_REG_FPS_SD2,  1, 5, 2 },
-	{  REGULATOR_SD,  "sd3", 0x19,  12500, 600000, 1800000, 1800000,      MAX77620_REG_SD3,   MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, MAX77620_SD_POWER_MODE_MASK,  MAX77620_SD_POWER_MODE_SHIFT,  0x10,  MAX77620_REG_FPS_SD3,  0, 3, 3 },
-	{ REGULATOR_LDO, "ldo0", 0x00,  25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO0, 3, 7, 0 },
-	{ REGULATOR_LDO, "ldo1", 0x00,  25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO1, 3, 7, 0 },
-	{ REGULATOR_LDO, "ldo2", 0x00,  50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO2, 3, 7, 0 },
-	{ REGULATOR_LDO, "ldo3", 0x00,  50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO3, 3, 7, 0 },
-	{ REGULATOR_LDO, "ldo4", 0x00,  12500, 800000,  850000,  850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO4, 0, 7, 1 },
-	{ REGULATOR_LDO, "ldo5", 0x00,  50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO5, 3, 7, 0 },
-	{ REGULATOR_LDO, "ldo6", 0x00,  50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO6, 3, 7, 0 },
-	{ REGULATOR_LDO, "ldo7", 0x00,  50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO7, 1, 4, 3 },
-	{ REGULATOR_LDO, "ldo8", 0x00,  50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, MAX77620_LDO_POWER_MODE_MASK, MAX77620_LDO_POWER_MODE_SHIFT, 0x00,  MAX77620_REG_FPS_LDO8, 3, 7, 0 }
+	{  "sd0",  12500, 600000,  625000, 1400000,  REGULATOR_SD,  MAX77620_REG_SD0,      MAX77620_REG_SD0_CFG,    MAX77620_SD0_VOLT_MASK,  {{ MAX77620_REG_FPS_SD0,  1, 7, 1 }} },
+	{  "sd1",  12500, 600000, 1125000, 1300000,  REGULATOR_SD,  MAX77620_REG_SD1,      MAX77620_REG_SD1_CFG,    MAX77620_SD1_VOLT_MASK,  {{ MAX77620_REG_FPS_SD1,  0, 1, 5 }} },
+	{  "sd2",  12500, 600000, 1325000, 1350000,  REGULATOR_SD,  MAX77620_REG_SD2,      MAX77620_REG_SD2_CFG,    MAX77620_SDX_VOLT_MASK,  {{ MAX77620_REG_FPS_SD2,  1, 5, 2 }} },
+	{  "sd3",  12500, 600000, 1800000, 1800000,  REGULATOR_SD,  MAX77620_REG_SD3,      MAX77620_REG_SD3_CFG,    MAX77620_SDX_VOLT_MASK,  {{ MAX77620_REG_FPS_SD3,  0, 3, 3 }} },
+	{ "ldo0",  25000, 800000, 1200000, 1200000,  REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} },
+	{ "ldo1",  25000, 800000, 1050000, 1050000,  REGULATOR_LDO, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO1, 3, 7, 0 }} },
+	{ "ldo2",  50000, 800000, 1800000, 3300000,  REGULATOR_LDO, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO2, 3, 7, 0 }} },
+	{ "ldo3",  50000, 800000, 3100000, 3100000,  REGULATOR_LDO, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO3, 3, 7, 0 }} },
+	{ "ldo4",  12500, 800000,  850000, 1000000,  REGULATOR_LDO, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO4, 0, 7, 1 }} },
+	{ "ldo5",  50000, 800000, 1800000, 1800000,  REGULATOR_LDO, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO5, 3, 7, 0 }} },
+	{ "ldo6",  50000, 800000, 2900000, 2900000,  REGULATOR_LDO, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO6, 3, 7, 0 }} },
+	{ "ldo7",  50000, 800000, 1050000, 1050000,  REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} },
+	{ "ldo8",  50000, 800000, 1050000, 2800000,  REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} },
+
+	{ "max77621_CPU", 6250, 606250, 1000000, 1400000,  REGULATOR_BC0, MAX77621_REG_VOUT,    MAX77621_REG_VOUT_DVS,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
+	{ "max77621_GPU", 6250, 606250, 1200000, 1400000,  REGULATOR_BC0, MAX77621_REG_VOUT,    MAX77621_REG_VOUT_DVS,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
+	{ "max77812_CPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
+	{ "max77812_RAM", 5000, 250000,  600000,  650000,  REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
+	//{ "max77812_GPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
 };

-static void _max77620_try_set_reg(u8 reg, u8 val)
+static u8 _max77812_get_address()
 {
-	u8 tmp;
-	do
+	static u8 max77812_i2c_addr = 0;
+
+	if (max77812_i2c_addr)
+		return max77812_i2c_addr;
+
+	max77812_i2c_addr =
+		!(FUSE(FUSE_RESERVED_ODM28_B01) & 1) ? MAX77812_PHASE31_CPU_I2C_ADDR : MAX77812_PHASE211_CPU_I2C_ADDR;
+
+	return max77812_i2c_addr;
+}
+
+static u8 _max7762x_get_i2c_address(u32 id)
+{
+	const max77620_regulator_t *reg = &_pmic_regulators[id];
+
+	// Choose the correct i2c address.
+	switch (reg->type)
 	{
-		i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, reg, val);
-		tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg);
-	} while (val != tmp);
+	case REGULATOR_SD:
+	case REGULATOR_LDO:
+		return MAX77620_I2C_ADDR;
+	case REGULATOR_BC0:
+		return (id == REGULATOR_CPU0 ? MAX77621_CPU_I2C_ADDR : MAX77621_GPU_I2C_ADDR);
+	case REGULATOR_BC1:
+		{
+		u8 reg_addr = _max77812_get_address();
+		if (id == REGULATOR_RAM0 && reg_addr == MAX77812_PHASE31_CPU_I2C_ADDR)
+			reg_addr = 0;
+		return reg_addr;
+		}
+	default:
+		return 0;
+	}
+}
+
+static void _max7762x_set_reg(u8 addr, u8 reg, u8 val)
+{
+	u32 retries = 100;
+	while (retries)
+	{
+		if (!i2c_send_byte(I2C_5, addr, reg, val))
+			break;
+
+		usleep(50);
+		retries--;
+	}
 }

 int max77620_regulator_get_status(u32 id)
 {
-	if (id > REGULATOR_MAX)
+	if (id > REGULATOR_LDO8)
 		return 0;

 	const max77620_regulator_t *reg = &_pmic_regulators[id];

+	// SD power OK status.
 	if (reg->type == REGULATOR_SD)
-		return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & reg->status_mask) ? 0 : 1;
-	return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & 8) ? 1 : 0;
+	{
+		u8 mask = 1u << (7 - id);
+		return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & mask) ? 0 : 1;
+	}
+
+	// LDO power OK status.
+	return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & MAX77620_LDO_CFG2_POK_MASK) ? 1 : 0;
 }

 int max77620_regulator_config_fps(u32 id)
 {
-	if (id > REGULATOR_MAX)
-		return 0;
+	if (id > REGULATOR_LDO8)
+		return 1;

 	const max77620_regulator_t *reg = &_pmic_regulators[id];

-	_max77620_try_set_reg(reg->fps_addr,
-		(reg->fps_src << MAX77620_FPS_SRC_SHIFT) | (reg->pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) | (reg->pd_period));
+	// Set FPS configuration.
+	_max7762x_set_reg(MAX77620_I2C_ADDR,
+		reg->fps.fps_addr,
+		(reg->fps.fps_src   << MAX77620_FPS_SRC_SHIFT)       |
+		(reg->fps.pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) |
+		(reg->fps.pd_period << MAX77620_FPS_PD_PERIOD_SHIFT));

-	return 1;
+	return 0;
 }

-int max77620_regulator_set_voltage(u32 id, u32 mv)
+int max7762x_regulator_set_voltage(u32 id, u32 uv)
 {
 	if (id > REGULATOR_MAX)
-		return 0;
+		return 1;

 	const max77620_regulator_t *reg = &_pmic_regulators[id];

-	if (mv < reg->mv_min || mv > reg->mv_max)
-		return 0;
+	if (uv < reg->uv_min || uv > reg->uv_max)
+		return 1;

-	u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
-	u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->volt_addr);
+	u8 addr = _max7762x_get_i2c_address(id);
+	if (!addr)
+		return 1;
+
+	// Calculate voltage multiplier.
+	u32 mult = (uv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
+	u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr);
 	val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
-	_max77620_try_set_reg(reg->volt_addr, val);
+
+	// Set voltage.
+	_max7762x_set_reg(addr, reg->volt_addr, val);
+
+	// If max77621 set DVS voltage also.
+	if (reg->type == REGULATOR_BC0)
+		_max7762x_set_reg(addr, reg->cfg_addr, MAX77621_VOUT_ENABLE_MASK | val);
+
+	// Wait for ramp up/down delay.
 	usleep(1000);

-	return 1;
+	return 0;
 }

-int max77620_regulator_enable(u32 id, int enable)
+int max7762x_regulator_enable(u32 id, bool enable)
 {
+	u8 reg_addr;
+	u8 enable_val;
+	u8 enable_mask;
+	u8 enable_shift;
+
 	if (id > REGULATOR_MAX)
-		return 0;
+		return 1;

 	const max77620_regulator_t *reg = &_pmic_regulators[id];

-	u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr;
-	u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, addr);
+	// Choose the correct i2c and register addresses and mask/shift for each type.
+	switch (reg->type)
+	{
+	case REGULATOR_SD:
+		reg_addr     = reg->cfg_addr;
+		enable_val   = MAX77620_POWER_MODE_NORMAL;
+		enable_mask  = MAX77620_SD_POWER_MODE_MASK;
+		enable_shift = MAX77620_SD_POWER_MODE_SHIFT;
+		break;
+	case REGULATOR_LDO:
+		reg_addr     = reg->volt_addr;
+		enable_val   = MAX77620_POWER_MODE_NORMAL;
+		enable_mask  = MAX77620_LDO_POWER_MODE_MASK;
+		enable_shift = MAX77620_LDO_POWER_MODE_SHIFT;
+		break;
+	case REGULATOR_BC0:
+		reg_addr     = reg->volt_addr;
+		enable_val   = MAX77621_VOUT_ENABLE;
+		enable_mask  = MAX77621_DVC_DVS_ENABLE_MASK;
+		enable_shift = MAX77621_DVC_DVS_ENABLE_SHIFT;
+		break;
+	case REGULATOR_BC1:
+		reg_addr     = reg->cfg_addr;
+		enable_val   = MAX77812_EN_CTRL_ENABLE;
+		enable_mask  = reg->enable.mask;
+		enable_shift = reg->enable.shift;
+		break;
+	default:
+		return 1;
+	}
+
+	u8 addr = _max7762x_get_i2c_address(id);
+	if (!addr)
+		return 1;
+
+	// Read and enable/disable.
+	u8 val = i2c_recv_byte(I2C_5, addr, reg_addr);
+	val &= ~enable_mask;
+
 	if (enable)
-		val = (val & ~reg->enable_mask) | ((MAX77620_POWER_MODE_NORMAL << reg->enable_shift) & reg->enable_mask);
-	else
-		val &= ~reg->enable_mask;
-	_max77620_try_set_reg(addr, val);
+		val |= (enable_val << enable_shift);
+
+	// Set enable.
+	_max7762x_set_reg(addr, reg_addr, val);
+
+	// Wait for enable/disable ramp delay.
 	usleep(1000);

-	return 1;
+	return 0;
 }

-// LDO only.
-int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags)
+void max77620_config_gpio(u32 gpio_id, bool enable)
 {
-	if (id > REGULATOR_MAX)
-		return 0;
+	if (gpio_id > 7)
+		return;

+	// Configure as standard GPIO.
+	u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO);
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, val & ~BIT(gpio_id));
+
+	// Set GPIO configuration.
+	if (enable)
+		val = MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DIR_OUTPUT | MAX77620_CNFG_GPIO_DRV_PUSHPULL;
+	else
+		val = MAX77620_CNFG_GPIO_DIR_INPUT | MAX77620_CNFG_GPIO_DRV_OPENDRAIN;
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO0 + gpio_id, val);
+}
+
+void max77621_config_default(u32 id, bool por)
+{
 	const max77620_regulator_t *reg = &_pmic_regulators[id];

-	if (mv < reg->mv_min || mv > reg->mv_max)
-		return 0;
+	if (reg->type != REGULATOR_BC0)
+		return;

-	u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
-	u8 val = ((flags << reg->enable_shift) & ~reg->volt_mask) | (mult & reg->volt_mask);
-	_max77620_try_set_reg(reg->volt_addr, val);
-	usleep(1000);
+	u8 addr = _max7762x_get_i2c_address(id);
+	if (!addr)
+		return;

-	return 1;
+	if (por)
+	{
+		// Set voltage and disable power before changing the inductor.
+		max7762x_regulator_set_voltage(id, 1000000);
+		max7762x_regulator_enable(id, false);
+
+		// Configure to default.
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_por);
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_por);
+	}
+	else
+	{
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_hos);
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_hos);
+	}
 }

 void max77620_config_default()
 {
-	for (u32 i = 1; i <= REGULATOR_MAX; i++)
+	// Check if Erista OTP.
+	if (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4) != 0x35)
+		return;
+
+	// Set default voltages and enable regulators.
+	for (u32 i = REGULATOR_SD1; i <= REGULATOR_LDO8; i++)
 	{
-		i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4);
 		max77620_regulator_config_fps(i);
-		max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
-		if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE)
-			max77620_regulator_enable(i, 1);
+		max7762x_regulator_set_voltage(i, _pmic_regulators[i].uv_default);
+		if (_pmic_regulators[i].fps.fps_src != MAX77620_FPS_SRC_NONE)
+			max7762x_regulator_enable(i, true);
 	}
-	_max77620_try_set_reg(MAX77620_REG_SD_CFG2, 4);
+
+	// Enable SD0 output voltage sense and disable for SD1. Additionally disable the reserved bit.
+	_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, MAX77620_SD_CNF2_ROVS_EN_SD0);
 }

+// Stock HOS: disabled.
 void max77620_low_battery_monitor_config(bool enable)
 {
-	_max77620_try_set_reg(MAX77620_REG_CNFGGLBL1,
-		MAX77620_CNFGGLBL1_LBDAC_EN | (enable ? MAX77620_CNFGGLBL1_MPPLD : 0) |
-		MAX77620_CNFGGLBL1_LBHYST_200 | MAX77620_CNFGGLBL1_LBDAC_2800);
+	_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_CNFGGLBL1,
+		MAX77620_CNFGGLBL1_LBDAC_EN             |
+		(enable ? MAX77620_CNFGGLBL1_MPPLD : 0) |
+		MAX77620_CNFGGLBL1_LBHYST_200           |
+		MAX77620_CNFGGLBL1_LBDAC_2800);
 }
--- a/bdk/power/max7762x.h
+++ b/bdk/power/max7762x.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2020 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -20,6 +20,14 @@

 #include <utils/types.h>

+/*
+ * SDx actual min is 625 mV. Multipliers 0/1 reserved.
+ * SD0 max is 1400 mV
+ * SD1 max is 1550 mV
+ * SD2 max is 3787.5 mV
+ * SD3 max is 3787.5 mV
+ */
+
 /*
 * Switch Power domains (max77620):
 * Name  | Usage         | uV step | uV min | uV default | uV max  | Init
@@ -32,23 +40,44 @@
 *  ldo1 | XUSB, PCIE    | 25000   | 800000 | 1050000    | 1050000 | 1.05V  (pcv)
 *  ldo2 | SDMMC1        | 50000   | 800000 | 1800000    | 3300000 |
 *  ldo3 | GC ASIC       | 50000   | 800000 | 3100000    | 3100000 | 3.1V   (pcv)
-*  ldo4 | RTC           | 12500   | 800000 |  850000    |  850000 |
+*  ldo4 | RTC           | 12500   | 800000 |  850000    |  850000 | 0.85V  (AO, pcv)
 *  ldo5 | GC Card       | 50000   | 800000 | 1800000    | 1800000 | 1.8V   (pcv)
-*  ldo6 | Touch, ALS    | 50000   | 800000 | 2900000    | 2900000 | 2.9V
-*  ldo7 | XUSB          | 50000   | 800000 | 1050000    | 1050000 |
-*  ldo8 | XUSB, DC      | 50000   | 800000 | 1050000    | 1050000 |
+*  ldo6 | Touch, ALS    | 50000   | 800000 | 2900000    | 2900000 | 2.9V   (pcv)
+*  ldo7 | XUSB          | 50000   | 800000 | 1050000    | 1050000 | 1.05V  (pcv)
+*  ldo8 | XUSB, DP, MCU | 50000   | 800000 | 1050000    | 2800000 | 1.05V/2.8V (pcv)
 */

+
+// GPIOs T210: 3: 3.3V, 5: CPU PMIC, 6: GPU PMIC, 7: DSI/VI 1.2V powered by ldo0.
+
+/*
+ * OTP:  T210 - T210B01:
+ * SD0:  1.0V   1.05V - SoC. EN Based on FPSSRC.
+ * SD1:  1.15V  1.1V  - DRAM for T210. EN Based on FPSSRC.
+ * SD2:  1.35V  1.35V
+ * SD3:  1.8V   1.8V
+ * All powered off?
+ * LDO0:   --   --    - Display
+ * LDO1: 1.05V  1.05V
+ * LDO2:   --   --    - SD
+ * LDO3: 3.1V   3.1V  - GC ASIC
+ * LDO4: 1.0V   0.8V  - Needed for RTC domain on T210.
+ * LDO5: 3.1V   3.1V
+ * LDO6: 2.8V   2.9V  - Touch.
+ * LDO7: 1.05V  1.0V
+ * LDO8: 1.05V  1.0V
+ */
+
 /*
 * MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode
 * MAX77620_REG_GPIOx: 0x9 sets output and enable
 */

 /*! MAX77620 partitions. */
-#define REGULATOR_SD0 0
-#define REGULATOR_SD1 1
-#define REGULATOR_SD2 2
-#define REGULATOR_SD3 3
+#define REGULATOR_SD0  0
+#define REGULATOR_SD1  1
+#define REGULATOR_SD2  2
+#define REGULATOR_SD3  3
 #define REGULATOR_LDO0 4
 #define REGULATOR_LDO1 5
 #define REGULATOR_LDO2 6
@@ -58,61 +87,89 @@
 #define REGULATOR_LDO6 10
 #define REGULATOR_LDO7 11
 #define REGULATOR_LDO8 12
-#define REGULATOR_MAX 12
+#define REGULATOR_CPU0 13 // T210 CPU.
+#define REGULATOR_GPU0 14 // T210 CPU.
+#define REGULATOR_CPU1 15 // T210B01 CPU.
+#define REGULATOR_RAM0 16 // T210B01 RAM for PHASE211.
+//#define REGULATOR_GPU1 17 // T210B01 CPU.
+#define REGULATOR_MAX  REGULATOR_RAM0

 #define MAX77621_CPU_I2C_ADDR 0x1B
 #define MAX77621_GPU_I2C_ADDR 0x1C

-#define MAX77621_VOUT_REG 0
-#define MAX77621_VOUT_DVS_REG 1
-#define MAX77621_CONTROL1_REG 2
-#define MAX77621_CONTROL2_REG 3
-
-/* MAX77621_VOUT */
-#define MAX77621_VOUT_ENABLE  (1 << 7)
-#define MAX77621_VOUT_MASK    0x7F
-#define  MAX77621_VOUT_0_95V  0x37
-#define  MAX77621_VOUT_1_09V  0x4F
+#define MAX77621_REG_VOUT     0x00
+#define MAX77621_REG_VOUT_DVS 0x01
+#define MAX77621_REG_CONTROL1 0x02
+#define MAX77621_REG_CONTROL2 0x03
+#define MAX77621_REG_CHIPID1  0x04
+#define MAX77621_REG_CHIPID2  0x05

 /* MAX77621_VOUT_DVC_DVS */
-#define MAX77621_DVS_VOUT_MASK 0x7F
+#define MAX77621_DVC_DVS_VOLT_MASK    0x7F
+#define MAX77621_DVC_DVS_ENABLE_SHIFT 7
+#define MAX77621_DVC_DVS_ENABLE_MASK  (1 << MAX77621_DVC_DVS_ENABLE_SHIFT)
+
+/* MAX77621_VOUT */
+#define MAX77621_VOUT_DISABLE     0
+#define MAX77621_VOUT_ENABLE      1
+#define MAX77621_VOUT_ENABLE_MASK (MAX77621_VOUT_ENABLE << MAX77621_DVC_DVS_ENABLE_SHIFT)

 /* MAX77621_CONTROL1 */
-#define MAX77621_SNS_ENABLE        (1 << 7)
-#define MAX77621_FPWM_EN_M         (1 << 6)
-#define MAX77621_NFSR_ENABLE       (1 << 5)
-#define MAX77621_AD_ENABLE         (1 << 4)
-#define MAX77621_BIAS_ENABLE       (1 << 3)
-#define MAX77621_FREQSHIFT_9PER    (1 << 2)
-
 #define MAX77621_RAMP_12mV_PER_US  0x0
 #define MAX77621_RAMP_25mV_PER_US  0x1
 #define MAX77621_RAMP_50mV_PER_US  0x2
 #define MAX77621_RAMP_200mV_PER_US 0x3
 #define MAX77621_RAMP_MASK         0x3

+#define MAX77621_FREQSHIFT_9PER    BIT(2)
+#define MAX77621_BIAS_ENABLE       BIT(3)
+#define MAX77621_AD_ENABLE         BIT(4)
+#define MAX77621_NFSR_ENABLE       BIT(5)
+#define MAX77621_FPWM_EN_M         BIT(6)
+#define MAX77621_SNS_ENABLE        BIT(7)
+
 /* MAX77621_CONTROL2 */
-#define MAX77621_WDTMR_ENABLE    (1 << 6)
-#define MAX77621_DISCH_ENBABLE   (1 << 5)
-#define MAX77621_FT_ENABLE		 (1 << 4)
-#define MAX77621_T_JUNCTION_120	 (1 << 7)
+#define MAX77621_INDUCTOR_MIN_30_PER  0
+#define MAX77621_INDUCTOR_NOMINAL     1
+#define MAX77621_INDUCTOR_PLUS_30_PER 2
+#define MAX77621_INDUCTOR_PLUS_60_PER 3
+#define MAX77621_INDUCTOR_MASK        3

-#define MAX77621_CKKADV_TRIP_DISABLE              0xC
-#define MAX77621_CKKADV_TRIP_75mV_PER_US          0x0
-#define MAX77621_CKKADV_TRIP_150mV_PER_US         0x4
-#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8
+#define MAX77621_CKKADV_TRIP_75mV_PER_US          (0  << 2)
+#define MAX77621_CKKADV_TRIP_150mV_PER_US         (1u << 2)
+#define MAX77621_CKKADV_TRIP_DISABLE              (3u << 2)
+#define MAX77621_CKKADV_TRIP_MASK                 (3u << 2)

-#define MAX77621_INDUCTOR_MIN_30_PER  0x0
-#define MAX77621_INDUCTOR_NOMINAL     0x1
-#define MAX77621_INDUCTOR_PLUS_30_PER 0x2
-#define MAX77621_INDUCTOR_PLUS_60_PER 0x3
+#define MAX77621_FT_ENABLE       BIT(4)
+#define MAX77621_DISCH_ENABLE    BIT(5)
+#define MAX77621_WDTMR_ENABLE    BIT(6)
+#define MAX77621_T_JUNCTION_120  BIT(7)

-int max77620_regulator_get_status(u32 id);
-int max77620_regulator_config_fps(u32 id);
-int max77620_regulator_set_voltage(u32 id, u32 mv);
-int max77620_regulator_enable(u32 id, int enable);
-int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags);
+#define MAX77621_CPU_CTRL1_POR_DEFAULT  (MAX77621_RAMP_50mV_PER_US)
+#define MAX77621_CPU_CTRL1_HOS_DEFAULT  (MAX77621_AD_ENABLE               | \
+										 MAX77621_NFSR_ENABLE             | \
+										 MAX77621_SNS_ENABLE              | \
+										 MAX77621_RAMP_12mV_PER_US)
+#define MAX77621_CPU_CTRL2_POR_DEFAULT  (MAX77621_T_JUNCTION_120          | \
+										 MAX77621_FT_ENABLE               | \
+										 MAX77621_CKKADV_TRIP_DISABLE     | \
+										 MAX77621_INDUCTOR_NOMINAL)
+#define MAX77621_CPU_CTRL2_HOS_DEFAULT  (MAX77621_T_JUNCTION_120          | \
+										 MAX77621_WDTMR_ENABLE            | \
+										 MAX77621_CKKADV_TRIP_75mV_PER_US | \
+										 MAX77621_INDUCTOR_NOMINAL)
+
+#define MAX77621_CTRL_HOS_CFG 0
+#define MAX77621_CTRL_POR_CFG 1
+
+int  max77620_regulator_get_status(u32 id);
+int  max77620_regulator_config_fps(u32 id);
+int  max7762x_regulator_set_voltage(u32 id, u32 uv);
+int  max7762x_regulator_enable(u32 id, bool enable);
+void max77620_config_gpio(u32 id, bool enable);
 void max77620_config_default();
 void max77620_low_battery_monitor_config(bool enable);

+void max77621_config_default(u32 id, bool por);
+
 #endif
--- a/bdk/power/max77812.h
+++ b/bdk/power/max77812.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MAX77812_H_
+#define _MAX77812_H_
+
+#define MAX77812_PHASE31_CPU_I2C_ADDR  0x31 // High power GPU. 2 Outputs: 3-phase M1 + 1-phase M4.
+#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // Low  power GPU. 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
+
+#define MAX77812_REG_RSET			0x00
+#define MAX77812_REG_INT_SRC		0x01
+#define MAX77812_REG_INT_SRC_M		0x02
+#define MAX77812_REG_TOPSYS_INT		0x03
+#define MAX77812_REG_TOPSYS_INT_M	0x04
+#define MAX77812_REG_TOPSYS_STAT	0x05
+#define MAX77812_REG_EN_CTRL		0x06
+#define  MAX77812_EN_CTRL_ENABLE      1
+#define  MAX77812_EN_CTRL_EN_M1_SHIFT 0
+#define  MAX77812_EN_CTRL_EN_M1_MASK  (1 << MAX77812_EN_CTRL_EN_M1_SHIFT)
+#define  MAX77812_EN_CTRL_EN_M2_SHIFT 2
+#define  MAX77812_EN_CTRL_EN_M2_MASK  (1 << MAX77812_EN_CTRL_EN_M2_SHIFT)
+#define  MAX77812_EN_CTRL_EN_M3_SHIFT 4
+#define  MAX77812_EN_CTRL_EN_M3_MASK  (1 << MAX77812_EN_CTRL_EN_M3_SHIFT)
+#define  MAX77812_EN_CTRL_EN_M4_SHIFT 6
+#define  MAX77812_EN_CTRL_EN_M4_MASK  (1 << MAX77812_EN_CTRL_EN_M4_SHIFT)
+#define MAX77812_REG_STUP_DLY2		0x07
+#define MAX77812_REG_STUP_DLY3		0x08
+#define MAX77812_REG_STUP_DLY4		0x09
+#define MAX77812_REG_SHDN_DLY1		0x0A
+#define MAX77812_REG_SHDN_DLY2		0x0B
+#define MAX77812_REG_SHDN_DLY3		0x0C
+#define MAX77812_REG_SHDN_DLY4		0x0D
+#define MAX77812_REG_WDTRSTB_DEB	0x0E
+#define MAX77812_REG_GPI_FUNC		0x0F
+#define MAX77812_REG_GPI_DEB1		0x10
+#define MAX77812_REG_GPI_DEB2		0x11
+#define MAX77812_REG_GPI_PD_CTRL	0x12
+#define MAX77812_REG_PROT_CFG		0x13
+#define MAX77812_REG_VERSION		0x14
+#define MAX77812_REG_I2C_CFG		0x15
+#define MAX77812_REG_BUCK_INT		0x20
+#define MAX77812_REG_BUCK_INT_M		0x21
+#define MAX77812_REG_BUCK_STAT		0x22
+#define MAX77812_REG_M1_VOUT		0x23 // GPU.
+#define MAX77812_REG_M2_VOUT		0x24
+#define MAX77812_REG_M3_VOUT		0x25 // DRAM on PHASE211.
+#define MAX77812_REG_M4_VOUT		0x26 // CPU.
+#define MAX77812_REG_M1_VOUT_D		0x27
+#define MAX77812_REG_M2_VOUT_D		0x28
+#define MAX77812_REG_M3_VOUT_D		0x29
+#define MAX77812_REG_M4_VOUT_D		0x2A
+#define MAX77812_REG_M1_VOUT_S		0x2B
+#define MAX77812_REG_M2_VOUT_S		0x2C
+#define MAX77812_REG_M3_VOUT_S		0x2D
+#define MAX77812_REG_M4_VOUT_S		0x2E
+#define MAX77812_REG_M1_CFG			0x2F // HOS: M1_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_M2_CFG			0x30 // HOS: M2_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_M3_CFG			0x31 // HOS: M3_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_M4_CFG			0x32 // HOS: M4_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_GLB_CFG1		0x33 // HOS: B_SD_SR/B_SS_SR - 5mV/us.
+#define MAX77812_REG_GLB_CFG2		0x34 // HOS: B_RD_SR/B_RU_SR - 5mV/us
+#define MAX77812_REG_GLB_CFG3		0x35
+
+/*! Protected area and settings only for MAX77812_ES2_VERSION */
+#define MAX77812_REG_GLB_CFG4		0x36 // QS: 0xBB.
+#define MAX77812_REG_GLB_CFG5		0x37 // QS: 0x39. ES2: Set to 0x3E.
+#define MAX77812_REG_GLB_CFG6		0x38 // QS: 0x88. ES2: Set to 0x90.
+#define MAX77812_REG_GLB_CFG7		0x39 // QS: 0x04.
+#define MAX77812_REG_GLB_CFG8		0x3A // QS: 0x3A. ES2: Set to 0x3A.
+
+#define MAX77812_REG_PROT_ACCESS	0xFD // 0x00: Lock, 0x5A: Unlock.
+#define MAX77812_REG_UNKNOWN		0xFE
+
+#define MAX77812_REG_EN_CTRL_MASK(n)		BIT(n)
+#define MAX77812_START_SLEW_RATE_MASK		0x07
+#define MAX77812_SHDN_SLEW_RATE_MASK		0x70
+#define MAX77812_RAMPUP_SLEW_RATE_MASK		0x07
+#define MAX77812_RAMPDOWN_SLEW_RATE_MASK	0x70
+#define MAX77812_SLEW_RATE_SHIFT			4
+
+#define MAX77812_OP_ACTIVE_DISCHARGE_MASK	BIT(7)
+#define MAX77812_PEAK_CURRENT_LMT_MASK		0x70
+#define MAX77812_SWITCH_FREQ_MASK			0x0C
+#define MAX77812_FORCED_PWM_MASK			BIT(1)
+#define MAX77812_SLEW_RATE_CNTRL_MASK		BIT(0)
+#define MAX77812_START_SHD_DELAY_MASK		0x1F
+#define MAX77812_VERSION_MASK				0x07
+#define MAX77812_ES2_VERSION				0x04
+#define MAX77812_QS_VERSION					0x05
+
+#define MAX77812_BUCK_VOLT_MASK				0xFF
+
+#endif
--- a/bdk/power/regulator_5v.c
+++ b/bdk/power/regulator_5v.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 CTCaer
+ * Copyright (c) 2019-2023 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -14,63 +14,90 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

+#include <soc/fuse.h>
 #include <soc/gpio.h>
+#include <soc/hw_init.h>
 #include <soc/pinmux.h>
 #include <soc/pmc.h>
 #include <soc/t210.h>
 #include <utils/types.h>

 static u8 reg_5v_dev = 0;
+static bool usb_src = false;

-void regulator_enable_5v(u8 dev)
+void regulator_5v_enable(u8 dev)
 {
+	bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
+
 	// The power supply selection from battery or USB is automatic.
 	if (!reg_5v_dev)
 	{
-		// Fan and Rail power from internal 5V regulator (battery).
+		// Fan and Rail power from battery 5V regulator EN.
 		PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = 1;
-		gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_GPIO);
-		gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_ENABLE);
-		gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH);
+		gpio_direction_output(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH);

-		// Fan and Rail power from USB 5V VDD.
-		PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1;
-		gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_GPIO);
-		gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_ENABLE);
-		gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_HIGH);
+		// Only Icosa has USB 5V VBUS rails.
+		if (tegra_t210)
+		{
+			// Fan and Rail power from USB 5V VBUS EN.
+			PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1;
+			gpio_direction_output(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
+		}

-		// Make sure GPIO power is enabled.
-		PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN;
-		// Override power detect for GPIO AO IO rails.
-		PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN;
+		// Make sure GPIO IO power is enabled.
+		PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO;
+		(void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write.
+
+		// Inform GPIO IO pads that we switched to 1.8V.
+		PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_33V_GPIO;
+		(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
+
+		usb_src = false;
 	}
 	reg_5v_dev |= dev;
 }

-void regulator_disable_5v(u8 dev)
+void regulator_5v_disable(u8 dev)
 {
+	bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
+
 	reg_5v_dev &= ~dev;

 	if (!reg_5v_dev)
 	{
-		// Rail power from internal 5V regulator (battery).
+		// Rail power from battery 5V regulator.
 		gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_LOW);
-		gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_DISABLE);
-		gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_SPIO);
-		PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = PINMUX_PARKED | PINMUX_INPUT_ENABLE;

-		// Rail power from USB 5V VDD.
-		gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
-		gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
-		gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_SPIO);
-		PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_PARKED | PINMUX_INPUT_ENABLE;
+		// Only Icosa has USB 5V VBUS rails.
+		if (tegra_t210)
+		{
+			// Rail power from USB 5V VBUS.
+			gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
+			usb_src = false;

-		// GPIO AO IO rails.
-		PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_GPIO_IO_EN;
+		}
 	}
 }

-bool regulator_get_5v_dev_enabled(u8 dev)
+bool regulator_5v_get_dev_enabled(u8 dev)
 {
 	return (reg_5v_dev & dev);
 }
+
+void regulator_5v_usb_src_enable(bool enable)
+{
+	// Only for Icosa.
+	if (hw_get_chip_id() != GP_HIDREV_MAJOR_T210)
+		return;
+
+	if (enable && !usb_src)
+	{
+		gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_HIGH);
+		usb_src = true;
+	}
+	else if (!enable && usb_src)
+	{
+		gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
+		usb_src = false;
+	}
+}
--- a/bdk/power/regulator_5v.h
+++ b/bdk/power/regulator_5v.h
@@ -21,14 +21,15 @@

 enum
 {
-	REGULATOR_5V_FAN  = (1 << 0),
-	REGULATOR_5V_JC_R = (1 << 1),
-	REGULATOR_5V_JC_L = (1 << 2),
+	REGULATOR_5V_FAN  = BIT(0),
+	REGULATOR_5V_JC_R = BIT(1),
+	REGULATOR_5V_JC_L = BIT(2),
 	REGULATOR_5V_ALL  = 0xFF
 };

-void regulator_enable_5v(u8 dev);
-void regulator_disable_5v(u8 dev);
-bool regulator_get_5v_dev_enabled(u8 dev);
+void regulator_5v_enable(u8 dev);
+void regulator_5v_disable(u8 dev);
+bool regulator_5v_get_dev_enabled(u8 dev);
+void regulator_5v_usb_src_enable(bool enable);

 #endif
--- a/bdk/rtc/max77620-rtc.c
+++ b/bdk/rtc/max77620-rtc.c
@@ -1,7 +1,7 @@
 /*
 * PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
 *
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2025 CTCaer
 * Copyright (c) 2019 shchmue
 *
 * This program is free software; you can redistribute it and/or modify it
@@ -19,7 +19,17 @@

 #include <rtc/max77620-rtc.h>
 #include <soc/i2c.h>
-#include <utils/util.h>
+#include <soc/pmc.h>
+#include <soc/timer.h>
+#include <soc/t210.h>
+
+bool auto_dst     = false;
+int  epoch_offset = 0;
+
+void max77620_rtc_prep_read()
+{
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
+}

 void max77620_rtc_get_time(rtc_time_t *time)
 {
@@ -30,20 +40,24 @@ void max77620_rtc_get_time(rtc_time_t *time)

 	// Get control reg config.
 	val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_CONTROL_REG);
-	// TODO: Check for binary format also?
+	// TODO: Make also sure it's binary format?

 	// Get time.
-	time->sec  = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_SEC_REG) & 0x7F;
-	time->min  = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MIN_REG) & 0x7F;
-	u8 hour = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG);
+	time->sec  = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_SEC_REG)  & 0x7F;
+	time->min  = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MIN_REG)  & 0x7F;
+	u8 hour    = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG) & 0x1F;
 	time->hour = hour & 0x1F;

-	if (!(val & MAX77620_RTC_24H) && (hour & MAX77620_RTC_HOUR_PM_MASK))
-		time->hour = (time->hour & 0xF) + 12;
+	if (!(val & MAX77620_RTC_24H))
+	{
+		time->hour = hour & 0xF;
+		if (hour & MAX77620_RTC_HOUR_PM_MASK)
+			time->hour += 12;
+	}

 	// Get day of week. 1: Monday to 7: Sunday.
 	time->weekday = 0;
-	val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_WEEKDAY_REG);
+	val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_WEEKDAY_REG) & 0x7F;
 	for (int i = 0; i < 8; i++)
 	{
 		time->weekday++;
@@ -53,8 +67,9 @@ void max77620_rtc_get_time(rtc_time_t *time)
 	}

 	// Get date.
-	time->day  = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DATE_REG) & 0x1f;
+	time->day   = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DAY_REG) & 0x1F;
 	time->month = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MONTH_REG) & 0xF) - 1;
+	time->month++; // Normally minus 1, but everything else expects 1 as January.
 	time->year  = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_YEAR_REG) & 0x7F) + 2000;
 }

@@ -64,6 +79,7 @@ void max77620_rtc_stop_alarm()

 	// Update RTC regs from RTC clock.
 	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
+	msleep(16);

 	// Stop alarm for both ALARM1 and ALARM2. Horizon uses ALARM2.
 	for (int i = 0; i < (MAX77620_RTC_NR_TIME_REGS * 2); i++)
@@ -82,9 +98,9 @@ void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time)
 	u32 tmp, edays, year, month, day;

 	// Set time.
-	time->sec = epoch % 60;
+	time->sec  = epoch % 60;
 	epoch /= 60;
-	time->min = epoch % 60;
+	time->min  = epoch % 60;
 	epoch /= 60;
 	time->hour = epoch % 24;
 	epoch /= 24;
@@ -99,14 +115,14 @@ void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time)
 	day = edays - month * 30 - month * 601 / 1000;

 	// Month/Year offset.
-	if(month < 14)
+	if (month < 14)
 	{
 		year -= 4716;
 		month--;
 	}
 	else
 	{
-		year -= 4715;
+		year  -= 4715;
 		month -= 13;
 	}

@@ -116,7 +132,7 @@ void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time)
 	time->day = day;

 	// Set weekday.
-	time->weekday = 0; //! TODO.
+	time->weekday = (day + 4) % 7;
 }

 u32 max77620_rtc_date_to_epoch(const rtc_time_t *time)
@@ -129,13 +145,13 @@ u32 max77620_rtc_date_to_epoch(const rtc_time_t *time)
 	month = time->month;

 	// Month/Year offset.
-	if(month < 3)
+	if (month < 3)
 	{
 		month += 12;
 		year--;
 	}

-	epoch = (365 * year) + (year >> 2) - (year / 100) + (year / 400); // Years to days.
+	epoch  = (365 * year) + (year >> 2) - (year / 100) + (year / 400); // Years to days.

 	epoch += (30 * month) + (3 * (month + 1) / 5) + time->day; // Months to days.
 	epoch -= 719561; // Epoch time is 1/1/1970.
@@ -145,3 +161,71 @@ u32 max77620_rtc_date_to_epoch(const rtc_time_t *time)

 	return epoch;
 }
+
+void max77620_rtc_get_time_adjusted(rtc_time_t *time)
+{
+	max77620_rtc_get_time(time);
+	if (epoch_offset)
+	{
+		u32 epoch = (u32)((s64)max77620_rtc_date_to_epoch(time) + epoch_offset);
+
+		// Adjust for DST between 28 march and 28 october. Good enough to cover all years as week info is not valid.
+		u16 md = (time->month << 8) | time->day;
+		if (auto_dst && md >= 0x31C && md < 0xA1C)
+			epoch += 3600;
+
+		max77620_rtc_epoch_to_date(epoch, time);
+	}
+}
+
+void max77620_rtc_set_auto_dst(bool enable)
+{
+	auto_dst = enable;
+}
+
+void max77620_rtc_set_epoch_offset(int offset)
+{
+	epoch_offset = offset;
+}
+
+void max77620_rtc_set_reboot_reason(rtc_reboot_reason_t *rr)
+{
+	max77620_rtc_stop_alarm();
+
+	// Set reboot reason.
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_YEAR_REG, rr->enc.val1);
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_YEAR_REG, rr->enc.val2);
+
+	// Set reboot reason magic.
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG, RTC_REBOOT_REASON_MAGIC);
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG, RTC_REBOOT_REASON_MAGIC);
+
+	// Update RTC clock from RTC regs.
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE);
+	msleep(16);
+}
+
+bool max77620_rtc_get_reboot_reason(rtc_reboot_reason_t *rr)
+{
+	u8 magic[2];
+
+	// Get reboot reason magic.
+	magic[0] = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG);
+	magic[1] = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG);
+
+	// Magic must be correct and match on both registers.
+	if (magic[0] != RTC_REBOOT_REASON_MAGIC || magic[0] != magic[1])
+		return false;
+
+	// Reboot reason setter is expected to have updated the actual regs already.
+	rr->enc.val1 = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_YEAR_REG);
+	rr->enc.val2 = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_YEAR_REG);
+
+	// Clear magic and update actual regs.
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG, 0);
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG, 0);
+	i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE);
+
+	// Return reboot reason. False if [config] was selected.
+	return true;
+}
--- a/bdk/rtc/max77620-rtc.h
+++ b/bdk/rtc/max77620-rtc.h
@@ -1,7 +1,7 @@
 /*
 * PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
 *
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2022 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -25,23 +25,28 @@

 #define MAX77620_RTC_NR_TIME_REGS   7

+#define MAX77620_RTC_RTCINT_REG     0x00
+#define MAX77620_RTC_RTCINTM_REG    0x01
 #define MAX77620_RTC_CONTROLM_REG   0x02
 #define MAX77620_RTC_CONTROL_REG    0x03
-#define  MAX77620_RTC_BIN_FORMAT (1 << 0)
-#define  MAX77620_RTC_24H        (1 << 1)
+#define  MAX77620_RTC_BIN_FORMAT    BIT(0)
+#define  MAX77620_RTC_24H           BIT(1)

 #define MAX77620_RTC_UPDATE0_REG    0x04
-#define  MAX77620_RTC_WRITE_UPDATE  (1 << 0)
-#define  MAX77620_RTC_READ_UPDATE   (1 << 4)
+#define  MAX77620_RTC_WRITE_UPDATE  BIT(0)
+#define  MAX77620_RTC_READ_UPDATE   BIT(4)
+
+#define MAX77620_RTC_UPDATE1_REG    0x05
+#define MAX77620_RTC_RTCSMPL_REG    0x06

 #define MAX77620_RTC_SEC_REG        0x07
 #define MAX77620_RTC_MIN_REG        0x08
 #define MAX77620_RTC_HOUR_REG       0x09
-#define  MAX77620_RTC_HOUR_PM_MASK  (1 << 6)
+#define  MAX77620_RTC_HOUR_PM_MASK  BIT(6)
 #define MAX77620_RTC_WEEKDAY_REG    0x0A
 #define MAX77620_RTC_MONTH_REG      0x0B
 #define MAX77620_RTC_YEAR_REG       0x0C
-#define MAX77620_RTC_DATE_REG       0x0D
+#define MAX77620_RTC_DAY_REG        0x0D

 #define MAX77620_ALARM1_SEC_REG     0x0E
 #define MAX77620_ALARM1_MIN_REG     0x0F
@@ -57,7 +62,7 @@
 #define MAX77620_ALARM2_MONTH_REG   0x19
 #define MAX77620_ALARM2_YEAR_REG    0x1A
 #define MAX77620_ALARM2_DATE_REG    0x1B
-#define  MAX77620_RTC_ALARM_EN_MASK	(1 << 7)
+#define  MAX77620_RTC_ALARM_EN_MASK	BIT(7)

 typedef struct _rtc_time_t {
 	u8  weekday;
@@ -69,9 +74,48 @@ typedef struct _rtc_time_t {
 	u16 year;
 } rtc_time_t;

+#define RTC_REBOOT_REASON_MAGIC 0x77 // 7-bit reg.
+
+enum {
+	REBOOT_REASON_NOP   = 0, // Use [config].
+	REBOOT_REASON_SELF  = 1, // Use autoboot_idx/autoboot_list.
+	REBOOT_REASON_MENU  = 2, // Force menu.
+	REBOOT_REASON_UMS   = 3, // Force selected UMS partition.
+	REBOOT_REASON_REC   = 4, // Set PMC_SCRATCH0_MODE_RECOVERY and reboot to self.
+	REBOOT_REASON_PANIC = 5  // Inform bootloader that panic occured if T210B01.
+};
+
+typedef struct _rtc_rr_decoded_t
+{
+	u16 reason:4;
+	u16 autoboot_idx:4;
+	u16 autoboot_list:1;
+	u16 ums_idx:3;
+} rtc_rr_decoded_t;
+
+typedef struct _rtc_rr_encoded_t
+{
+	u16 val1:6; // 6-bit reg.
+	u16 val2:6; // 6-bit reg.
+} rtc_rr_encoded_t;
+
+typedef struct _rtc_reboot_reason_t
+{
+	union {
+		rtc_rr_decoded_t dec;
+		rtc_rr_encoded_t enc;
+	};
+} rtc_reboot_reason_t;
+
+void max77620_rtc_prep_read();
 void max77620_rtc_get_time(rtc_time_t *time);
+void max77620_rtc_get_time_adjusted(rtc_time_t *time);
+void max77620_rtc_set_epoch_offset(int offset);
+void max77620_rtc_set_auto_dst(bool enable);
 void max77620_rtc_stop_alarm();
 void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time);
-u32 max77620_rtc_date_to_epoch(const rtc_time_t *time);
+u32  max77620_rtc_date_to_epoch(const rtc_time_t *time);
+void max77620_rtc_set_reboot_reason(rtc_reboot_reason_t *rr);
+bool max77620_rtc_get_reboot_reason(rtc_reboot_reason_t *rr);

 #endif /* _MFD_MAX77620_RTC_H_ */
--- a/bdk/sec/se.c
+++ b/bdk/sec/se.c
--- a/bdk/sec/se.h
+++ b/bdk/sec/se.h
@@ -1,37 +1,55 @@
 /*
-* Copyright (c) 2018 naehrwert
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms and conditions of the GNU General Public License,
-* version 2, as published by the Free Software Foundation.
-*
-* This program is distributed in the hope it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-* more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2019-2026 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */

 #ifndef _SE_H_
 #define _SE_H_

+#include "se_t210.h"
 #include <utils/types.h>

 void se_rsa_acc_ctrl(u32 rs, u32 flags);
 void se_key_acc_ctrl(u32 ks, u32 flags);
 u32  se_key_acc_ctrl_get(u32 ks);
-void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize);
-void se_aes_key_set(u32 ks, void *key, u32 size);
+
+/*! AES Key Management Functions */
+void se_aes_key_set(u32 ks, const void *key, u32 size);
+void se_aes_iv_set(u32 ks, const void *iv, u32 size);
+void se_aes_key_get(u32 ks, void *key, u32 size);
 void se_aes_key_clear(u32 ks);
-int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input);
-int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
-int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src);
-int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr);
-int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 total_size, u32 sha_cfg, bool is_oneshot);
-int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size);
-int se_calc_sha256_finalize(void *hash, u32 *msg_left);
-int se_gen_prng128(void *dst);
+void se_aes_iv_clear(u32 ks);
+int  se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *seed);
+void se_aes_ctx_get_keys(u8 *buf, u8 *keys, u32 keysize);
+/*! Encryption Functions */
+int  se_aes_crypt_ecb(u32 ks, int enc, void *dst, const void *src, u32 size);
+int  se_aes_crypt_cbc(u32 ks, int enc, void *dst, const void *src, u32 size);
+int  se_aes_crypt_ofb(u32 ks, void *dst, const void *src, u32 size);
+int  se_aes_crypt_ctr(u32 ks, void *dst, const void *src, u32 size, void *ctr);
+int  se_aes_crypt_xts_sec(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, void *dst, void *src, u32 secsize);
+int  se_aes_crypt_xts_sec_nx(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, u8 *tweak, bool regen_tweak, u32 tweak_exp, void *dst, void *src, u32 sec_size);
+int  se_aes_crypt_xts(u32 tweak_ks, u32 crypt_ks, int enc, u64 sec, void *dst, void *src, u32 secsize, u32 num_secs);
+/*! Hashing Functions */
+int  se_sha_hash_256_async(void *hash, const void *src, u32 size);
+int  se_sha_hash_256_oneshot(void *hash, const void *src, u32 size);
+int  se_sha_hash_256_partial_start(void *hash, const void *src, u32 size, bool is_oneshot);
+int  se_sha_hash_256_partial_update(void *hash, const void *src, u32 size, bool is_oneshot);
+int  se_sha_hash_256_partial_end(void *hash, u64 total_size, const void *src, u32 src_size, bool is_oneshot);
+int  se_sha_hash_256_finalize(void *hash);
+int  se_aes_hash_cmac(u32 ks, void *hash, const void *src, u32 size);
+/*! Random Functions */
+int  se_rng_pseudo(void *dst, u32 size);

 #endif
--- a/bdk/sec/se_t210.h
+++ b/bdk/sec/se_t210.h
@@ -1,391 +1,331 @@
 /*
-* Driver for Tegra Security Engine
-*
-* Copyright (c) 2011-2013, NVIDIA Corporation. All Rights Reserved.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-* more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-*/
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2026 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */

-#ifndef _CRYPTO_TEGRA_SE_H
-#define _CRYPTO_TEGRA_SE_H
+#ifndef _SE_T210_H
+#define _SE_T210_H

 #include <utils/types.h>

-#define TEGRA_SE_CRA_PRIORITY	300
-#define TEGRA_SE_COMPOSITE_PRIORITY 400
-#define TEGRA_SE_CRYPTO_QUEUE_LENGTH 50
-#define SE_MAX_SRC_SG_COUNT		50
-#define SE_MAX_DST_SG_COUNT		50
+#define SE_CRYPTO_QUEUE_LENGTH 50
+#define SE_MAX_SRC_SG_COUNT    50
+#define SE_MAX_DST_SG_COUNT    50

-#define TEGRA_SE_KEYSLOT_COUNT		16
-#define SE_MAX_LAST_BLOCK_SIZE	0xFFFFF
+#define SE_AES_KEYSLOT_COUNT   16
+#define SE_RSA_KEYSLOT_COUNT   2
+
+#define SE_AES_BLOCK_SIZE   16
+#define SE_AES_IV_SIZE      16
+#define SE_AES_MIN_KEY_SIZE 16
+#define SE_AES_MAX_KEY_SIZE 32
+#define SE_KEY_128_SIZE     16
+#define SE_KEY_192_SIZE     24
+#define SE_KEY_256_SIZE     32
+#define SE_SHA_192_SIZE     24
+#define SE_SHA_256_SIZE     32
+#define SE_SHA_384_SIZE     48
+#define SE_SHA_512_SIZE     64
+#define SE_RNG_BLOCK_SIZE   16
+#define SE_RNG_IV_SIZE      16
+#define SE_RNG_DT_SIZE      16
+#define SE_RNG_KEY_SIZE     16
+#define SE_RNG_SEED_SIZE (SE_RNG_IV_SIZE + SE_RNG_KEY_SIZE + SE_RNG_DT_SIZE)
+
+#define SE_AES_CMAC_DIGEST_SIZE 16
+#define SE_RSA512_DIGEST_SIZE   64
+#define SE_RSA1024_DIGEST_SIZE  128
+#define SE_RSA1536_DIGEST_SIZE  192
+#define SE_RSA2048_DIGEST_SIZE  256
+
+#define SE_SHA2_MIN_BLOCK_SIZE 64
+#define SE_SHA2_MAX_BLOCK_SIZE 128
+
+#define SE_LL_MAX_SIZE ALIGN_DOWN(0xFFFFFF, SE_SHA2_MAX_BLOCK_SIZE)
+
+#define  DECRYPT   0
+#define  ENCRYPT   1

 /* SE register definitions */
-#define SE_SECURITY_0 0x000
-#define SE_KEY_SCHED_READ_SHIFT 3
+#define SE_SE_SECURITY_REG 0x000
+#define  SE_HARD_SETTING   BIT(0)
+#define  SE_ENG_DIS        BIT(1)
+#define  SE_PERKEY_SETTING BIT(2)
+#define  SE_SOFT_SETTING   BIT(16)

-#define SE_TZRAM_SECURITY_0 0x004
+#define SE_TZRAM_SECURITY_REG 0x004
+#define  SE_TZRAM_HARD_SETTING BIT(0)
+#define  SE_TZRAM_ENG_DIS      BIT(1)

-#define SE_CONFIG_REG_OFFSET		0x014
-#define SE_CONFIG_ENC_ALG_SHIFT		12
-#define SE_CONFIG_DEC_ALG_SHIFT		8
-#define ALG_AES_ENC		1
-#define ALG_RNG			2
-#define ALG_SHA			3
-#define ALG_RSA			4
-#define ALG_NOP			0
-#define ALG_AES_DEC		1
-#define SE_CONFIG_ENC_ALG(x)		(x << SE_CONFIG_ENC_ALG_SHIFT)
-#define SE_CONFIG_DEC_ALG(x)		(x << SE_CONFIG_DEC_ALG_SHIFT)
-#define SE_CONFIG_DST_SHIFT			2
-#define DST_MEMORY		0
-#define DST_HASHREG		1
-#define DST_KEYTAB		2
-#define DST_SRK			3
-#define DST_RSAREG		4
-#define SE_CONFIG_DST(x)			(x << SE_CONFIG_DST_SHIFT)
-#define SE_CONFIG_ENC_MODE_SHIFT	24
-#define SE_CONFIG_DEC_MODE_SHIFT	16
-#define MODE_KEY128		0
-#define MODE_KEY192		1
-#define MODE_KEY256		2
-#define MODE_SHA1		0
-#define MODE_SHA224		4
-#define MODE_SHA256		5
-#define MODE_SHA384		6
-#define MODE_SHA512		7
-#define SE_CONFIG_ENC_MODE(x)		(x << SE_CONFIG_ENC_MODE_SHIFT)
-#define SE_CONFIG_DEC_MODE(x)		(x << SE_CONFIG_DEC_MODE_SHIFT)
+#define SE_OPERATION_REG 0x008
+#define  SE_OP_ABORT       0
+#define  SE_OP_START       1
+#define  SE_OP_RESTART_OUT 2
+#define  SE_OP_CTX_SAVE    3
+#define  SE_OP_RESTART_IN  4

-#define SE_RNG_CONFIG_REG_OFFSET		0x340
-#define RNG_MODE_SHIFT	0
-#define RNG_MODE_NORMAL	0
-#define RNG_MODE_FORCE_INSTANTION	1
-#define RNG_MODE_FORCE_RESEED		2
-#define SE_RNG_CONFIG_MODE(x)		(x << RNG_MODE_SHIFT)
-#define RNG_SRC_SHIFT	2
-#define RNG_SRC_NONE	0
-#define RNG_SRC_ENTROPY	1
-#define RNG_SRC_LFSR	2
-#define SE_RNG_CONFIG_SRC(x)		(x << RNG_SRC_SHIFT)
+#define SE_INT_ENABLE_REG	0x00C
+#define SE_INT_STATUS_REG	0x010
+#define  SE_INT_IN_LL_BUF_RD  BIT(0)
+#define  SE_INT_IN_DONE       BIT(1)
+#define  SE_INT_OUT_LL_BUF_WR BIT(2)
+#define  SE_INT_OUT_DONE      BIT(3)
+#define  SE_INT_OP_DONE       BIT(4)
+#define  SE_INT_RESEED_NEEDED BIT(5)
+#define  SE_INT_ERR_STAT      BIT(16)

-#define SE_RNG_SRC_CONFIG_REG_OFFSET	0x344
-#define RNG_SRC_RO_ENT_SHIFT	1
-#define RNG_SRC_RO_ENT_ENABLE	1
-#define RNG_SRC_RO_ENT_DISABLE	0
-#define SE_RNG_SRC_CONFIG_ENT_SRC(x)	(x << RNG_SRC_RO_ENT_SHIFT)
-#define RNG_SRC_RO_ENT_LOCK_SHIFT	 0
-#define RNG_SRC_RO_ENT_LOCK_ENABLE	 1
-#define RNG_SRC_RO_ENT_LOCK_DISABLE 0
-#define SE_RNG_SRC_CONFIG_ENT_SRC_LOCK(x) (x << RNG_SRC_RO_ENT_LOCK_SHIFT)
+#define SE_CONFIG_REG 0x014
+#define  DST_MEMORY      0
+#define  DST_HASHREG     1
+#define  DST_KEYTABLE    2
+#define  DST_SRK         3
+#define  DST_RSAREG      4
+#define  SE_CONFIG_DST(x)      ((x) << 2)
+#define  ALG_NOP         0
+#define  ALG_AES_DEC     1
+#define  SE_CONFIG_DEC_ALG(x)  ((x) << 8)
+#define  ALG_NOP         0
+#define  ALG_AES_ENC     1
+#define  ALG_RNG         2
+#define  ALG_SHA         3
+#define  ALG_RSA         4
+#define  SE_CONFIG_ENC_ALG(x)  ((x) << 12)
+#define  MODE_KEY128     0
+#define  MODE_KEY192     1
+#define  MODE_KEY256     2
+#define  MODE_SHA1       0
+#define  MODE_SHA224     4
+#define  MODE_SHA256     5
+#define  MODE_SHA384     6
+#define  MODE_SHA512     7
+#define  SE_CONFIG_DEC_MODE(x) ((x) << 16)
+#define  SE_CONFIG_ENC_MODE(x) ((x) << 24)

-#define SE_RNG_RESEED_INTERVAL_REG_OFFSET		0x348
+#define SE_IN_LL_ADDR_REG        0x018
+#define SE_IN_CUR_BYTE_ADDR_REG  0x01C
+#define SE_IN_CUR_LL_ID_REG      0x020
+#define SE_OUT_LL_ADDR_REG       0x024
+#define SE_OUT_CUR_BYTE_ADDR_REG 0x028
+#define SE_OUT_CUR_LL_ID_REG     0x02C

-#define SE_KEYTABLE_REG_OFFSET		0x31c
-#define SE_KEYTABLE_SLOT_SHIFT		4
-#define SE_KEYTABLE_SLOT(x)			(x << SE_KEYTABLE_SLOT_SHIFT)
-#define SE_KEYTABLE_QUAD_SHIFT		2
-#define QUAD_KEYS_128	0
-#define QUAD_KEYS_192	1
-#define QUAD_KEYS_256	1
-#define QUAD_ORG_IV		2
-#define QUAD_UPDTD_IV	3
-#define SE_KEYTABLE_QUAD(x)			(x << SE_KEYTABLE_QUAD_SHIFT)
-#define SE_KEYTABLE_OP_TYPE_SHIFT	9
-#define OP_READ			0
-#define OP_WRITE		1
-#define SE_KEYTABLE_OP_TYPE(x)		(x << SE_KEYTABLE_OP_TYPE_SHIFT)
-#define SE_KEYTABLE_TABLE_SEL_SHIFT		8
-#define TABLE_KEYIV		0
-#define TABLE_SCHEDULE	1
-#define SE_KEYTABLE_TABLE_SEL(x)	(x << SE_KEYTABLE_TABLE_SEL_SHIFT)
-#define SE_KEYTABLE_PKT_SHIFT		0
-#define SE_KEYTABLE_PKT(x)			(x << SE_KEYTABLE_PKT_SHIFT)
+#define SE_HASH_RESULT_REG 0x030
+#define  SE_HASH_RESULT_REG_COUNT 16

-#define SE_OP_DONE_SHIFT	4
-#define OP_DONE	1
-#define SE_OP_DONE(x, y)	((x) && (y << SE_OP_DONE_SHIFT))
+#define SE_CONTEXT_SAVE_CONFIG_REG 0x070
+#define  KEYS_0_3        0
+#define  KEYS_4_7        1
+#define  ORIGINAL_IV     2
+#define  UPDATED_IV      3
+#define  SE_CONTEXT_AES_WORD_QUAD(x)    ((x) << 0)
+#define  SE_CONTEXT_AES_KEY_INDEX(x)    ((x) << 8)
+#define  KEYS_0_3        0
+#define  KEYS_4_7        1
+#define  KEYS_8_11       2
+#define  KEYS_12_15      3
+#define  SE_CONTEXT_RSA_WORD_QUAD(x)    ((x) << 12)
+#define  SLOT0_EXPONENT  0
+#define  SLOT0_MODULUS   1
+#define  SLOT1_EXPONENT  2
+#define  SLOT1_MODULUS   3
+#define  SE_CONTEXT_RSA_KEY_INDEX(x)    ((x) << 16)
+#define  STICKY_0_3      0
+#define  STICKY_4_7      1
+#define  SE_CONTEXT_STICKY_WORD_QUAD(x) ((x) << 24)
+#define  STICKY_BITS     0
+#define  RSA_KEYTABLE    1
+#define  AES_KEYTABLE    2
+#define  MEM             4
+#define  SRK             6
+#define SE_CONTEXT_SRC(x)               ((x) << 29)

-#define SE_CRYPTO_LAST_BLOCK	0x080
+#define SE_CTX_SAVE_AUTO_T210B01_REG 0x074
+#define  SE_CTX_SAVE_AUTO_ENABLE		BIT(0)
+#define  SE_CTX_SAVE_AUTO_LOCK          BIT(8)
+#define  SE_CTX_SAVE_AUTO_CURR_CNT_MASK (0x3FF << 16)

-#define SE_CRYPTO_REG_OFFSET		0x304
-#define SE_CRYPTO_HASH_SHIFT		0
-#define HASH_DISABLE	0
-#define HASH_ENABLE		1
-#define SE_CRYPTO_HASH(x)			(x << SE_CRYPTO_HASH_SHIFT)
-#define SE_CRYPTO_XOR_POS_SHIFT		1
-#define XOR_BYPASS		0
-#define XOR_TOP			2
-#define XOR_BOTTOM		3
-#define SE_CRYPTO_XOR_POS(x)		(x << SE_CRYPTO_XOR_POS_SHIFT)
-#define SE_CRYPTO_INPUT_SEL_SHIFT	3
-#define INPUT_AHB		0
-#define INPUT_RANDOM	1
-#define INPUT_AESOUT	2
-#define INPUT_LNR_CTR	3
-#define SE_CRYPTO_INPUT_SEL(x)		(x << SE_CRYPTO_INPUT_SEL_SHIFT)
-#define SE_CRYPTO_VCTRAM_SEL_SHIFT	5
-#define VCTRAM_AHB		0
-#define VCTRAM_AESOUT	2
-#define VCTRAM_PREVAHB	3
-#define SE_CRYPTO_VCTRAM_SEL(x)		(x << SE_CRYPTO_VCTRAM_SEL_SHIFT)
-#define SE_CRYPTO_IV_SEL_SHIFT		7
-#define IV_ORIGINAL		0
-#define IV_UPDATED		1
-#define SE_CRYPTO_IV_SEL(x)			(x << SE_CRYPTO_IV_SEL_SHIFT)
-#define SE_CRYPTO_CORE_SEL_SHIFT	8
-#define CORE_DECRYPT	0
-#define CORE_ENCRYPT	1
-#define SE_CRYPTO_CORE_SEL(x)		(x << SE_CRYPTO_CORE_SEL_SHIFT)
-#define SE_CRYPTO_CTR_VAL_SHIFT		11
-#define SE_CRYPTO_CTR_VAL(x)		(x << SE_CRYPTO_CTR_VAL_SHIFT)
-#define SE_CRYPTO_KEY_INDEX_SHIFT	24
-#define SE_CRYPTO_KEY_INDEX(x)		(x << SE_CRYPTO_KEY_INDEX_SHIFT)
-#define SE_CRYPTO_CTR_CNTN_SHIFT	11
-#define SE_CRYPTO_CTR_CNTN(x)		(x << SE_CRYPTO_CTR_CNTN_SHIFT)
+#define SE_CRYPTO_LAST_BLOCK 0x080

-#define SE_CRYPTO_CTR_REG_COUNT		4
-#define SE_CRYPTO_CTR_REG_OFFSET	0x308
-
-#define SE_OPERATION_REG_OFFSET		0x008
-#define SE_OPERATION_SHIFT			0
-#define OP_ABORT		0
-#define OP_START		1
-#define OP_RESTART		2
-#define OP_CTX_SAVE		3
-#define OP_RESTART_IN	4
-#define SE_OPERATION(x)				(x << SE_OPERATION_SHIFT)
-
-#define SE_CONTEXT_SAVE_CONFIG_REG_OFFSET		0x070
-#define SE_CONTEXT_SAVE_WORD_QUAD_SHIFT		0
-#define KEYS_0_3		0
-#define KEYS_4_7		1
-#define ORIG_IV		2
-#define UPD_IV		3
-#define SE_CONTEXT_SAVE_WORD_QUAD(x)	(x << SE_CONTEXT_SAVE_WORD_QUAD_SHIFT)
-
-#define SE_CONTEXT_SAVE_KEY_INDEX_SHIFT		8
-#define SE_CONTEXT_SAVE_KEY_INDEX(x)	(x << SE_CONTEXT_SAVE_KEY_INDEX_SHIFT)
-
-#define SE_CONTEXT_SAVAE_STICKY_WORD_QUAD_SHIFT	24
-#define STICKY_0_3		0
-#define STICKY_4_7		1
-#define SE_CONTEXT_SAVE_STICKY_WORD_QUAD(x)		\
-		(x << SE_CONTEXT_SAVAE_STICKY_WORD_QUAD_SHIFT)
-
-#define SE_CONTEXT_SAVE_SRC_SHIFT		29
-#define STICKY_BITS		0
-#define KEYTABLE		2
-#define MEM		4
-#define SRK		6
-
-#define RSA_KEYTABLE	1
-#define AES_KEYTABLE	2
-#define SE_CONTEXT_SAVE_SRC(x)		(x << SE_CONTEXT_SAVE_SRC_SHIFT)
-
-#define SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT	16
-#define SE_CONTEXT_SAVE_RSA_KEY_INDEX(x)		\
-		(x << SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT)
-
-#define SE_CONTEXT_RSA_WORD_QUAD_SHIFT	12
-#define SE_CONTEXT_RSA_WORD_QUAD(x)		\
-		(x << SE_CONTEXT_RSA_WORD_QUAD_SHIFT)
-
-#define SE_INT_ENABLE_REG_OFFSET	0x00c
-#define SE_INT_STATUS_REG_OFFSET	0x010
-#define INT_DISABLE		0
-#define INT_ENABLE		1
-#define INT_UNSET		0
-#define INT_SET			1
-#define SE_INT_OP_DONE_SHIFT		4
-#define SE_INT_OP_DONE(x)			(x << SE_INT_OP_DONE_SHIFT)
-#define SE_INT_ERROR_SHIFT		16
-#define SE_INT_ERROR(x)			(x << SE_INT_ERROR_SHIFT)
-
-#define SE_STATUS_0 0x800
-#define SE_STATUS_0_STATE_WAIT_IN 3
-
-#define SE_ERR_STATUS_0			0x804
-#define SE_ERR_STATUS_0_SE_NS_ACCESS_CLEAR 0
-
-#define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET	0X330
-#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT		0
-#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x)		\
-		(x << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT)
-
-#define SE_KEY_INDEX_SHIFT		8
-#define SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(x)	(x << SE_KEY_INDEX_SHIFT)
-
-#define SE_IN_LL_ADDR_REG_OFFSET	0x018
-#define SE_OUT_LL_ADDR_REG_OFFSET	0x024
-
-#define SE_KEYTABLE_DATA0_REG_OFFSET	0x320
-#define SE_KEYTABLE_REG_MAX_DATA		16
-
-#define SE_BLOCK_COUNT_REG_OFFSET	0x318
-
-#define SE_SPARE_0_REG_OFFSET		0x80c
-
-#define SE_SHA_CONFIG_REG_OFFSET	0x200
+#define SE_SHA_CONFIG_REG 0x200
 #define  SHA_CONTINUE  0
 #define  SHA_INIT_HASH 1

-#define SE_SHA_MSG_LENGTH_0_REG_OFFSET	0x204
-#define SE_SHA_MSG_LENGTH_1_REG_OFFSET	0x208
-#define SE_SHA_MSG_LENGTH_2_REG_OFFSET	0x20C
-#define SE_SHA_MSG_LENGTH_3_REG_OFFSET	0x210
-#define SE_SHA_MSG_LEFT_0_REG_OFFSET	0x214
-#define SE_SHA_MSG_LEFT_1_REG_OFFSET	0x218
-#define SE_SHA_MSG_LEFT_2_REG_OFFSET	0x21C
-#define SE_SHA_MSG_LEFT_3_REG_OFFSET	0x220
+#define SE_SHA_MSG_LENGTH_0_REG 0x204
+#define SE_SHA_MSG_LENGTH_1_REG 0x208
+#define SE_SHA_MSG_LENGTH_2_REG 0x20C
+#define SE_SHA_MSG_LENGTH_3_REG 0x210
+#define SE_SHA_MSG_LEFT_0_REG   0x214
+#define SE_SHA_MSG_LEFT_1_REG   0x218
+#define SE_SHA_MSG_LEFT_2_REG   0x21C
+#define SE_SHA_MSG_LEFT_3_REG   0x220

-#define SE_HASH_RESULT_REG_COUNT	16
-#define SE_HASH_RESULT_REG_OFFSET	0x030
-#define TEGRA_SE_KEY_256_SIZE		32
-#define TEGRA_SE_KEY_192_SIZE		24
-#define TEGRA_SE_KEY_128_SIZE		16
-#define TEGRA_SE_AES_BLOCK_SIZE		16
-#define TEGRA_SE_AES_MIN_KEY_SIZE	16
-#define TEGRA_SE_AES_MAX_KEY_SIZE	32
-#define TEGRA_SE_AES_IV_SIZE		16
-#define TEGRA_SE_RNG_IV_SIZE		16
-#define TEGRA_SE_RNG_DT_SIZE		16
-#define TEGRA_SE_RNG_KEY_SIZE		16
-#define TEGRA_SE_RNG_SEED_SIZE		(TEGRA_SE_RNG_IV_SIZE + \
-						TEGRA_SE_RNG_KEY_SIZE + \
-						TEGRA_SE_RNG_DT_SIZE)
+#define SE_CRYPTO_SECURITY_PERKEY_REG 0x280
+#define  SE_KEY_LOCK_FLAG   0x80
+#define SE_CRYPTO_KEYTABLE_ACCESS_REG 0x284
+#define  SE_CRYPTO_KEYTABLE_ACCESS_REG_COUNT 16
+#define  SE_KEY_TBL_DIS_KEYREAD_FLAG    BIT(0)
+#define  SE_KEY_TBL_DIS_KEYUPDATE_FLAG  BIT(1)
+#define  SE_KEY_TBL_DIS_OIVREAD_FLAG    BIT(2)
+#define  SE_KEY_TBL_DIS_OIVUPDATE_FLAG  BIT(3)
+#define  SE_KEY_TBL_DIS_UIVREAD_FLAG    BIT(4)
+#define  SE_KEY_TBL_DIS_UIVUPDATE_FLAG  BIT(5)
+#define  SE_KEY_TBL_DIS_KEYUSE_FLAG     BIT(6)
+#define  SE_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F

-#define TEGRA_SE_AES_CMAC_DIGEST_SIZE	16
-#define TEGRA_SE_RSA512_DIGEST_SIZE	    64
-#define TEGRA_SE_RSA1024_DIGEST_SIZE	128
-#define TEGRA_SE_RSA1536_DIGEST_SIZE	192
-#define TEGRA_SE_RSA2048_DIGEST_SIZE	256
+#define SE_CRYPTO_CONFIG_REG 0x304
+#define  HASH_DISABLE   0
+#define  HASH_ENABLE    1
+#define  SE_CRYPTO_HASH(x)          ((x) << 0)
+#define  XOR_BYPASS     0
+#define  XOR_TOP        2
+#define  XOR_BOTTOM     3
+#define  SE_CRYPTO_XOR_POS(x)       ((x) << 1)
+#define  INPUT_MEMORY   0
+#define  INPUT_RANDOM   1
+#define  INPUT_AESOUT   2
+#define  INPUT_LNR_CTR  3
+#define  SE_CRYPTO_INPUT_SEL(x)     ((x) << 3)
+#define  VCTRAM_MEM     0
+#define  VCTRAM_AESOUT  2
+#define  VCTRAM_PREVMEM 3
+#define  SE_CRYPTO_VCTRAM_SEL(x)    ((x) << 5)
+#define  IV_ORIGINAL    0
+#define  IV_UPDATED     1
+#define  SE_CRYPTO_IV_SEL(x)        ((x) << 7)
+#define  CORE_DECRYPT   0
+#define  CORE_ENCRYPT   1
+#define  SE_CRYPTO_CORE_SEL(x)      ((x) << 8)
+#define  SE_CRYPTO_KEYSCH_BYPASS BIT(10)
+#define  SE_CRYPTO_CTR_CNTN(x)      ((x) << 11)
+#define  SE_CRYPTO_KEY_INDEX(x)     ((x) << 24)
+#define  MEMIF_AHB      0
+#define  MEMIF_MCCIF    1
+#define  SE_CRYPTO_MEMIF(x)         ((x) << 31)

-#define SE_KEY_TABLE_ACCESS_LOCK_OFFSET	0x280
-#define SE_KEY_TBL_DIS_KEY_LOCK_FLAG 0x80
+#define SE_CRYPTO_LINEAR_CTR_REG 0x308
+#define  SE_CRYPTO_LINEAR_CTR_REG_COUNT 4

-#define SE_KEY_TABLE_ACCESS_REG_OFFSET	0x284
-#define SE_KEY_TBL_DIS_KEYREAD_FLAG    (1 << 0)
-#define SE_KEY_TBL_DIS_KEYUPDATE_FLAG  (1 << 1)
-#define SE_KEY_TBL_DIS_OIVREAD_FLAG    (1 << 2)
-#define SE_KEY_TBL_DIS_OIVUPDATE_FLAG  (1 << 3)
-#define SE_KEY_TBL_DIS_UIVREAD_FLAG    (1 << 4)
-#define SE_KEY_TBL_DIS_UIVUPDATE_FLAG  (1 << 5)
-#define SE_KEY_TBL_DIS_KEYUSE_FLAG     (1 << 6)
-#define SE_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
+#define SE_CRYPTO_LAST_BLOCK_REG 0x318

-#define SE_KEY_READ_DISABLE_SHIFT		0
-#define SE_KEY_UPDATE_DISABLE_SHIFT		1
+#define SE_CRYPTO_KEYTABLE_ADDR_REG 0x31C
+#define  SE_KEYTABLE_PKT(x)         ((x) << 0)
+#define  KEYS_0_3        0
+#define  KEYS_4_7        1
+#define  ORIGINAL_IV     2
+#define  UPDATED_IV      3
+#define  SE_KEYTABLE_QUAD(x)        ((x) << 2)
+#define  SE_KEYTABLE_SLOT(x)        ((x) << 4)

-#define SE_CONTEXT_BUFER_SIZE	1072
-#define SE_CONTEXT_DRBG_BUFER_SIZE	2112
+#define SE_CRYPTO_KEYTABLE_DATA_REG 0x320

-#define SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET	0
-#define SE_CONTEXT_SAVE_RANDOM_DATA_SIZE	16
-#define SE_CONTEXT_SAVE_STICKY_BITS_OFFSET	\
-	(SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET + SE_CONTEXT_SAVE_RANDOM_DATA_SIZE)
-#define SE_CONTEXT_SAVE_STICKY_BITS_SIZE	16
+#define SE_CRYPTO_KEYTABLE_DST_REG 0x330
+#define  KEYS_0_3        0
+#define  KEYS_4_7        1
+#define  ORIGINAL_IV     2
+#define  UPDATED_IV      3
+#define  SE_KEYTABLE_DST_WORD_QUAD(x) ((x) << 0)
+#define  SE_KEYTABLE_DST_KEY_INDEX(x) ((x) << 8)

-#define SE_CONTEXT_SAVE_KEYS_OFFSET	(SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
-					SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
-#define SE11_CONTEXT_SAVE_KEYS_OFFSET	(SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
-					SE_CONTEXT_SAVE_STICKY_BITS_SIZE + \
-					SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
+#define SE_RNG_CONFIG_REG 0x340
+#define  MODE_NORMAL 0
+#define  MODE_FORCE_INSTANTION 1
+#define  MODE_FORCE_RESEED     2
+#define  SE_RNG_CONFIG_MODE(x)        ((x) << 0)
+#define  SRC_NONE        0
+#define  SRC_ENTROPY     1
+#define  SRC_LFSR        2
+#define  SE_RNG_CONFIG_SRC(x)         ((x) << 2)

-#define SE_CONTEXT_SAVE_KEY_LENGTH	512
-#define SE_CONTEXT_ORIGINAL_IV_OFFSET	(SE_CONTEXT_SAVE_KEYS_OFFSET + \
-			SE_CONTEXT_SAVE_KEY_LENGTH)
-#define SE11_CONTEXT_ORIGINAL_IV_OFFSET	(SE11_CONTEXT_SAVE_KEYS_OFFSET + \
-			SE_CONTEXT_SAVE_KEY_LENGTH)
+#define SE_RNG_SRC_CONFIG_REG	0x344
+#define  RO_ENTR_LOCK_DISABLE  0
+#define  RO_ENTR_LOCK_ENABLE   1
+#define  SE_RNG_SRC_CONFIG_ENTR_SRC_LOCK(x) ((x) << 0)
+#define  RO_ENTR_DISABLE       0
+#define  RO_ENTR_ENABLE        1
+#define  SE_RNG_SRC_CONFIG_ENTR_SRC(x)      ((x) << 1)
+#define  RO_HW_DIS_CYA_DISABLE 0
+#define  RO_HW_DIS_CYA_ENABLE  1
+#define  SE_RNG_SRC_CONFIG_HW_DIS_CYA(x)    ((x) << 2)
+#define  SE_RNG_SRC_CONFIG_ENTR_SUBSMPL(x)  ((x) << 4)
+#define  SE_RNG_SRC_CONFIG_ENTR_DATA_FLUSH  BIT(8)

-#define SE_CONTEXT_ORIGINAL_IV_LENGTH	256
+#define SE_RNG_RESEED_INTERVAL_REG 0x348

-#define SE_CONTEXT_UPDATED_IV_OFFSET	(SE_CONTEXT_ORIGINAL_IV_OFFSET + \
-			SE_CONTEXT_ORIGINAL_IV_LENGTH)
-#define SE11_CONTEXT_UPDATED_IV_OFFSET	(SE11_CONTEXT_ORIGINAL_IV_OFFSET + \
-			SE_CONTEXT_ORIGINAL_IV_LENGTH)
+#define SE_RSA_CONFIG 0x400
+#define  RSA_KEY_SLOT_ONE 0
+#define  RSA_KEY_SLOT_TW0 1
+#define  RSA_KEY_SLOT(x)            ((x) << 24)

-#define SE_CONTEXT_UPDATED_IV_LENGTH	256
+#define SE_RSA_KEY_SIZE_REG 0x404
+#define  RSA_KEY_WIDTH_512  0
+#define  RSA_KEY_WIDTH_1024 1
+#define  RSA_KEY_WIDTH_1536 2
+#define  RSA_KEY_WIDTH_2048 3

-#define SE_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET (SE_CONTEXT_UPDATED_IV_OFFSET + \
-					SE_CONTEXT_UPDATED_IV_LENGTH)
-#define SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET \
-					(SE11_CONTEXT_UPDATED_IV_OFFSET + \
-					SE_CONTEXT_UPDATED_IV_LENGTH)
+#define SE_RSA_EXP_SIZE_REG 0x408

-#define SE_CONTEXT_SAVE_RSA_KEYS_OFFSET	SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET
+#define SE_RSA_SECURITY_PERKEY_REG 0x40C
+#define  SE_RSA_KEY_LOCK_FLAG               0x80
+#define SE_RSA_KEYTABLE_ACCESS_REG 0x410
+#define  SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG    BIT(0)
+#define  SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG  BIT(1)
+#define  SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG     BIT(2)
+#define  SE_RSA_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
+#define  SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG      (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG)
+#define  SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_USE_FLAG  (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG | SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG)

-#define SE_CONTEXT_SAVE_RSA_KEY_LENGTH	1024
+#define SE_RSA_KEYTABLE_ADDR_REG 0x420
+#define  SE_RSA_KEYTABLE_PKT(x)        ((x) << 0)
+#define  RSA_KEY_TYPE_EXP       0
+#define  RSA_KEY_TYPE_MOD       1
+#define  SE_RSA_KEYTABLE_TYPE(x)       ((x) << 6)
+#define  RSA_KEY_NUM(x)                ((x) << 7)
+#define  RSA_KEY_INPUT_MODE_REG 0
+#define  RSA_KEY_INPUT_MODE_DMA 1
+#define  SE_RSA_KEYTABLE_INPUT_MODE(x) ((x) << 8)
+#define  RSA_KEY_READ           0
+#define  RSA_KEY_WRITE          1
+#define  SE_RSA_KEY_OP(x)              ((x) << 10)

-#define SE_CONTEXT_SAVE_RSA_KNOWN_PATTERN_OFFSET	\
-	(SE_CONTEXT_SAVE_RSA_KEYS_OFFSET + SE_CONTEXT_SAVE_RSA_KEY_LENGTH)
+#define SE_RSA_KEYTABLE_DATA_REG 0x424

-#define SE_CONTEXT_KNOWN_PATTERN_SIZE	16
+#define SE_RSA_OUTPUT_REG 0x428
+#define  SE_RSA_OUTPUT_REG_COUNT 64

-#define TEGRA_SE_RSA_KEYSLOT_COUNT		2
+#define SE_STATUS_REG 0x800
+#define  SE_STATUS_STATE_IDLE     0
+#define  SE_STATUS_STATE_BUSY     1
+#define  SE_STATUS_STATE_WAIT_OUT 2
+#define  SE_STATUS_STATE_WAIT_IN  3
+#define  SE_STATUS_STATE_MASK     3
+#define  SE_STATUS_MEM_IF_IDLE    (0 << 2)
+#define  SE_STATUS_MEM_IF_BUSY    BIT(2)

-#define SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET	0x40C
-#define SE_RSA_KEY_TBL_DIS_KEY_LOCK_FLAG    0x80
+#define SE_ERR_STATUS_REG 0x804
+#define  SE_ERR_STATUS_SE_NS_ACCESS    BIT(0)
+#define  SE_ERR_STATUS_BUSY_REG_WR     BIT(1)
+#define  SE_ERR_STATUS_DST             BIT(2)
+#define  SE_ERR_STATUS_SRK_USAGE_LIMIT BIT(3)
+#define  SE_ERR_STATUS_TZRAM_NS_ACCESS BIT(24)
+#define  SE_ERR_STATUS_TZRAM_ADDRESS   BIT(25)

-#define SE_RSA_KEYTABLE_ACCESS_REG_OFFSET	0x410
-#define SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG         (1 << 0)
-#define SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG       (1 << 1)
-#define SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG)
-#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG          (1 << 2)
-#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT    (1 << 2)
-#define SE_RSA_KEY_TBL_DIS_KEY_ALL_COMMON_FLAG  7
-#define SE_RSA_KEY_TBL_DIS_KEY_ALL_FLAG        0x7F
+#define SE_MISC_REG 0x808
+#define  SE_ENTROPY_NEXT_192BIT BIT(0)
+#define  SE_ENTROPY_VN_BYPASS   BIT(1)
+#define  SE_CLK_OVR_ON          BIT(2)

-#define SE_RSA_KEYTABLE_ADDR	0x420
-#define SE_RSA_KEYTABLE_DATA	0x424
-#define SE_RSA_OUTPUT 0x428
+#define SE_SPARE_REG 0x80C
+#define  SE_INPUT_NONCE_LE BIT(0)

-#define RSA_KEY_READ	0
-#define RSA_KEY_WRITE	1
-#define SE_RSA_KEY_OP_SHIFT	10
-#define SE_RSA_KEY_OP(x)	(x << SE_RSA_KEY_OP_SHIFT)
-
-#define RSA_KEY_INPUT_MODE_REG	0
-#define RSA_KEY_INPUT_MODE_DMA	1
-#define RSA_KEY_INPUT_MODE_SHIFT	8
-#define RSA_KEY_INPUT_MODE(x)	(x << RSA_KEY_INPUT_MODE_SHIFT)
-
-#define RSA_KEY_SLOT_ONE	0
-#define RSA_KEY_SLOT_TW0	1
-#define RSA_KEY_NUM_SHIFT	7
-#define RSA_KEY_NUM(x)	(x << RSA_KEY_NUM_SHIFT)
-
-#define RSA_KEY_TYPE_EXP	0
-#define RSA_KEY_TYPE_MOD	1
-#define RSA_KEY_TYPE_SHIFT	6
-#define RSA_KEY_TYPE(x)	(x << RSA_KEY_TYPE_SHIFT)
-
-#define SE_RSA_KEY_SIZE_REG_OFFSET	0x404
-#define SE_RSA_EXP_SIZE_REG_OFFSET	0x408
-
-#define RSA_KEY_SLOT_SHIFT	24
-#define RSA_KEY_SLOT(x)	(x << RSA_KEY_SLOT_SHIFT)
-#define SE_RSA_CONFIG	0x400
-
-#define RSA_KEY_PKT_WORD_ADDR_SHIFT	0
-#define RSA_KEY_PKT_WORD_ADDR(x)	(x << RSA_KEY_PKT_WORD_ADDR_SHIFT)
-
-#define RSA_KEY_WORD_ADDR_SHIFT	0
-#define RSA_KEY_WORD_ADDR(x)	(x << RSA_KEY_WORD_ADDR_SHIFT)
-
-#define SE_RSA_KEYTABLE_PKT_SHIFT	0
-#define SE_RSA_KEYTABLE_PKT(x)	(x << SE_RSA_KEYTABLE_PKT_SHIFT)
-
-#endif /* _CRYPTO_TEGRA_SE_H */
+#endif
--- a/bdk/sec/tsec.c
+++ b/bdk/sec/tsec.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2019 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 * Copyright (c) 2018 balika011
 *
 * This program is free software; you can redistribute it and/or modify it
@@ -20,20 +20,23 @@

 #include "tsec.h"
 #include "tsec_t210.h"
+#include <memory_map.h>
+#include <mem/heap.h>
+#include <mem/mc.h>
+#include <mem/smmu.h>
 #include <sec/se_t210.h>
 #include <soc/bpmp.h>
 #include <soc/clock.h>
 #include <soc/kfuse.h>
+#include <soc/pmc.h>
 #include <soc/t210.h>
-#include <mem/heap.h>
-#include <mem/mc.h>
-#include <mem/smmu.h>
-#include <utils/util.h>
+#include <soc/timer.h>

 // #include <gfx_utils.h>

 #define PKG11_MAGIC 0x31314B50
-#define KB_TSEC_FW_EMU_COMPAT 6 // KB ID for HOS 6.2.0.
+
+#define TSEC_HOS_KB_620 6

 static int _tsec_dma_wait_idle()
 {
@@ -41,9 +44,9 @@ static int _tsec_dma_wait_idle()

 	while (!(TSEC(TSEC_DMATRFCMD) & TSEC_DMATRFCMD_IDLE))
 		if (get_tmr_ms() > timeout)
-			return 0;
+			return 1;

-	return 1;
+	return 0;
 }

 static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offset)
@@ -55,142 +58,157 @@ static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offse
 	else
 		cmd = TSEC_DMATRFCMD_IMEM;      // DMA IMEM (Instruction memmory)

-	TSEC(TSEC_DMATRFMOFFS) = i_offset;
+	TSEC(TSEC_DMATRFMOFFS)  = i_offset;
 	TSEC(TSEC_DMATRFFBOFFS) = pa_offset;
-	TSEC(TSEC_DMATRFCMD) = cmd;
+	TSEC(TSEC_DMATRFCMD)    = cmd;

 	return _tsec_dma_wait_idle();
 }

-int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
+int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
 {
 	int res = 0;
 	u8 *fwbuf = NULL;
-	u32 *pdir, *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec;
+	u32 type = tsec_ctxt->type;
+	u32 *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec;
 	u32 *pkg11_magic_off;
+	void *ptb;

 	bpmp_mmu_disable();
-	bpmp_clk_rate_set(BPMP_CLK_NORMAL);
+	bpmp_clk_rate_relaxed(true);

 	// Enable clocks.
-	clock_enable_host1x();
-	usleep(2);
 	clock_enable_tsec();
 	clock_enable_sor_safe();
 	clock_enable_sor0();
 	clock_enable_sor1();
 	clock_enable_kfuse();
-
 	kfuse_wait_ready();

+	// Disable AHB aperture.
+	mc_disable_ahb_redirect();
+
+	if (type == TSEC_FW_TYPE_NEW)
+	{
+		// Disable all CCPLEX core rails.
+		pmc_domain_pwrgate_set(POWER_RAIL_CE0, DISABLE);
+		pmc_domain_pwrgate_set(POWER_RAIL_CE1, DISABLE);
+		pmc_domain_pwrgate_set(POWER_RAIL_CE2, DISABLE);
+		pmc_domain_pwrgate_set(POWER_RAIL_CE3, DISABLE);
+
+		// Enable AHB aperture and set it to full mmio.
+		mc_enable_ahb_redirect(0);
+	}
+
 	// Configure Falcon.
 	TSEC(TSEC_DMACTL) = 0;
 	TSEC(TSEC_IRQMSET) =
 		TSEC_IRQMSET_EXT(0xFF) |
-		TSEC_IRQMSET_WDTMR |
-		TSEC_IRQMSET_HALT |
-		TSEC_IRQMSET_EXTERR |
-		TSEC_IRQMSET_SWGEN0 |
+		TSEC_IRQMSET_WDTMR     |
+		TSEC_IRQMSET_HALT      |
+		TSEC_IRQMSET_EXTERR    |
+		TSEC_IRQMSET_SWGEN0    |
 		TSEC_IRQMSET_SWGEN1;
 	TSEC(TSEC_IRQDEST) =
 		TSEC_IRQDEST_EXT(0xFF) |
-		TSEC_IRQDEST_HALT |
-		TSEC_IRQDEST_EXTERR |
-		TSEC_IRQDEST_SWGEN0 |
+		TSEC_IRQDEST_HALT      |
+		TSEC_IRQDEST_EXTERR    |
+		TSEC_IRQDEST_SWGEN0    |
 		TSEC_IRQDEST_SWGEN1;
 	TSEC(TSEC_ITFEN) = TSEC_ITFEN_CTXEN | TSEC_ITFEN_MTHDEN;
-	if (!_tsec_dma_wait_idle())
+	if (_tsec_dma_wait_idle())
 	{
 		res = -1;
 		goto out;
 	}

 	// Load firmware or emulate memio environment for newer TSEC fw.
-	if (kb == KB_TSEC_FW_EMU_COMPAT)
+	if (type == TSEC_FW_TYPE_EMU)
 		TSEC(TSEC_DMATRFBASE) = (u32)tsec_ctxt->fw >> 8;
 	else
 	{
-		fwbuf = (u8 *)malloc(0x4000);
+		fwbuf = (u8 *)malloc(SZ_16K);
 		u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf, 0x100);
 		memcpy(fwbuf_aligned, tsec_ctxt->fw, tsec_ctxt->size);
+
 		TSEC(TSEC_DMATRFBASE) = (u32)fwbuf_aligned >> 8;
 	}

 	for (u32 addr = 0; addr < tsec_ctxt->size; addr += 0x100)
 	{
-		if (!_tsec_dma_pa_to_internal_100(false, addr, addr))
+		if (_tsec_dma_pa_to_internal_100(false, addr, addr))
 		{
 			res = -2;
 			goto out_free;
 		}
 	}

-	if (kb == KB_TSEC_FW_EMU_COMPAT)
+	if (type == TSEC_FW_TYPE_EMU)
 	{
 		// Init SMMU translation for TSEC.
-		pdir = smmu_init_for_tsec();
-		smmu_init(tsec_ctxt->secmon_base);
-		// Enable SMMU
-		if (!smmu_is_used())
-			smmu_enable();
+		ptb = smmu_domain_init(MC_SMMU_TSEC_ASID, 1);
+		smmu_init();
+
+		// Enable SMMU.
+		smmu_enable();

 		// Clock reset controller.
-		car = page_alloc(1);
-		memcpy(car, (void *)CLOCK_BASE, 0x1000);
-		car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = 2;
-		smmu_map(pdir, CLOCK_BASE, (u32)car, 1, _WRITABLE | _READABLE | _NONSECURE);
+		car = smmu_page_zalloc(1);
+		memcpy(car, (void *)CLOCK_BASE, SZ_PAGE);
+		car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = CLK_SRC_DIV(2);
+		smmu_map(ptb, CLOCK_BASE, (u32)car, 1, SMMU_WRITE | SMMU_READ | SMMU_NS);

 		// Fuse driver.
-		fuse = page_alloc(1);
-		memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, 0x400);
+		fuse = smmu_page_zalloc(1);
+		memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, SZ_1K);
 		fuse[0x82C / 4] = 0;
-		fuse[0x9E0 / 4] = (1 << (kb + 2)) - 1;
-		fuse[0x9E4 / 4] = (1 << (kb + 2)) - 1;
-		smmu_map(pdir, (FUSE_BASE - 0x800), (u32)fuse, 1, _READABLE | _NONSECURE);
+		fuse[0x9E0 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1;
+		fuse[0x9E4 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1;
+		smmu_map(ptb, (FUSE_BASE - 0x800), (u32)fuse, 1, SMMU_READ | SMMU_NS);

 		// Power management controller.
-		pmc = page_alloc(1);
-		smmu_map(pdir, RTC_BASE, (u32)pmc, 1, _READABLE | _NONSECURE);
+		pmc = smmu_page_zalloc(1);
+		smmu_map(ptb, RTC_BASE, (u32)pmc, 1, SMMU_READ | SMMU_NS);

 		// Flow control.
-		flowctrl = page_alloc(1);
-		smmu_map(pdir, FLOW_CTLR_BASE, (u32)flowctrl, 1, _WRITABLE | _NONSECURE);
+		flowctrl = smmu_page_zalloc(1);
+		smmu_map(ptb, FLOW_CTLR_BASE, (u32)flowctrl, 1, SMMU_WRITE | SMMU_NS);

 		// Security engine.
-		se = page_alloc(1);
-		memcpy(se, (void *)SE_BASE, 0x1000);
-		smmu_map(pdir, SE_BASE, (u32)se, 1, _READABLE | _WRITABLE | _NONSECURE);
+		se = smmu_page_zalloc(1);
+		memcpy(se, (void *)SE_BASE, SZ_PAGE);
+		smmu_map(ptb, SE_BASE, (u32)se, 1, SMMU_READ | SMMU_WRITE | SMMU_NS);

 		// Memory controller.
-		mc = page_alloc(1);
-		memcpy(mc, (void *)MC_BASE, 0x1000);
+		mc = smmu_page_zalloc(1);
+		memcpy(mc, (void *)MC_BASE, SZ_PAGE);
 		mc[MC_IRAM_BOM / 4] = 0;
-		mc[MC_IRAM_TOM / 4] = 0x80000000;
-		smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE);
+		mc[MC_IRAM_TOM / 4] = DRAM_START;
+		smmu_map(ptb, MC_BASE, (u32)mc, 1, SMMU_READ | SMMU_NS);

 		// IRAM
-		iram = page_alloc(0x30);
+		iram = smmu_page_zalloc(0x30);
 		memcpy(iram, tsec_ctxt->pkg1, 0x30000);
 		// PKG1.1 magic offset.
-		pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / 4));
-		smmu_map(pdir, 0x40010000, (u32)iram, 0x30, _READABLE | _WRITABLE | _NONSECURE);
+		pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / sizeof(u32)));
+		smmu_map(ptb, 0x40010000, (u32)iram, 0x30, SMMU_READ | SMMU_WRITE | SMMU_NS);

 		// Exception vectors
-		evec = page_alloc(1);
-		smmu_map(pdir, EXCP_VEC_BASE, (u32)evec, 1, _READABLE | _WRITABLE | _NONSECURE);
+		evec = smmu_page_zalloc(1);
+		smmu_map(ptb, EXCP_VEC_BASE, (u32)evec, 1, SMMU_READ | SMMU_WRITE | SMMU_NS);
 	}

 	// Execute firmware.
 	HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA;
-	TSEC(TSEC_STATUS) = 0;
-	TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
-	TSEC(TSEC_BOOTVEC) = 0;
-	TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU;
+	TSEC(TSEC_MAILBOX1) = 0;
+	TSEC(TSEC_MAILBOX0) = 1; // Set HOS key version.
+	TSEC(TSEC_BOOTVEC)  = 0;
+	TSEC(TSEC_CPUCTL)   = TSEC_CPUCTL_STARTCPU;

-	if (kb == KB_TSEC_FW_EMU_COMPAT)
+	if (type == TSEC_FW_TYPE_EMU)
 	{
-		u32 start = get_tmr_us();
-		u32 k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
+		u32 k = se[SE_CRYPTO_KEYTABLE_DATA_REG / 4];
+		u32 timeout = get_tmr_us() + 125000;
 		u32 key[16] = {0};
 		u32 kidx = 0;

@@ -198,21 +216,21 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 		{
 			smmu_flush_all();

-			if (k != se[SE_KEYTABLE_DATA0_REG_OFFSET / 4])
+			if (k != se[SE_CRYPTO_KEYTABLE_DATA_REG / 4])
 			{
-				k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
+				k = se[SE_CRYPTO_KEYTABLE_DATA_REG / 4];
 				key[kidx++] = k;
 			}

 			// Failsafe.
-			if ((u32)get_tmr_us() - start > 125000)
+			if ((u32)get_tmr_us() > timeout)
 				break;
 		}

 		if (kidx != 8)
 		{
 			res = -6;
-			smmu_deinit_for_tsec();
+			smmu_domain_deinit(MC_SMMU_TSEC_ASID, 1);

 			goto out_free;
 		}
@@ -223,12 +241,12 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 		memcpy(tsec_keys, &key, 0x20);
 		memcpy(tsec_ctxt->pkg1, iram, 0x30000);

-		smmu_deinit_for_tsec();
+		smmu_domain_deinit(MC_SMMU_TSEC_ASID, 1);

 		// for (int i = 0; i < kidx; i++)
 		// 	gfx_printf("key %08X\n", key[i]);

-		// gfx_printf("cpuctl (%08X) mbox (%08X)\n", TSEC(TSEC_CPUCTL), TSEC(TSEC_STATUS));
+		// gfx_printf("cpuctl (%08X) mbox (%08X)\n", TSEC(TSEC_CPUCTL), TSEC(TSEC_MAILBOX1));

 		// u32 errst = MC(MC_ERR_STATUS);
 		// gfx_printf(" MC %08X %08X %08X\n", MC(MC_INTSTATUS), errst, MC(MC_ERR_ADR));
@@ -239,19 +257,23 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 	}
 	else
 	{
-		if (!_tsec_dma_wait_idle())
+		if (_tsec_dma_wait_idle())
 		{
 			res = -3;
 			goto out_free;
 		}
+
 		u32 timeout = get_tmr_ms() + 2000;
-		while (!TSEC(TSEC_STATUS))
+		while (!TSEC(TSEC_MAILBOX1))
+		{
 			if (get_tmr_ms() > timeout)
 			{
 				res = -4;
 				goto out_free;
 			}
-		if (TSEC(TSEC_STATUS) != 0xB0B0B0B0)
+		}
+
+		if (TSEC(TSEC_MAILBOX1) != 0xB0B0B0B0)
 		{
 			res = -5;
 			goto out_free;
@@ -260,23 +282,22 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
 		// Fetch result.
 		HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0;
 		u32 buf[4];
-		buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB);
-		buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
-		buf[2] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB);
-		buf[3] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB);
-		SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0;
-		SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB) = 0;
-		SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0;
-		SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0;
+		buf[0] = SOR1(SOR_DP_HDCP_BKSV_LSB);
+		buf[1] = SOR1(SOR_TMDS_HDCP_BKSV_LSB);
+		buf[2] = SOR1(SOR_TMDS_HDCP_CN_MSB);
+		buf[3] = SOR1(SOR_TMDS_HDCP_CN_LSB);
+		SOR1(SOR_DP_HDCP_BKSV_LSB)   = 0;
+		SOR1(SOR_TMDS_HDCP_BKSV_LSB) = 0;
+		SOR1(SOR_TMDS_HDCP_CN_MSB)   = 0;
+		SOR1(SOR_TMDS_HDCP_CN_LSB)   = 0;

-		memcpy(tsec_keys, &buf, 0x10);
+		memcpy(tsec_keys, &buf, SE_KEY_128_SIZE);
 	}

-out_free:;
+out_free:
 	free(fwbuf);

-out:;
-
+out:
 	// Disable clocks.
 	clock_disable_kfuse();
 	clock_disable_sor1();
@@ -284,7 +305,10 @@ out:;
 	clock_disable_sor_safe();
 	clock_disable_tsec();
 	bpmp_mmu_enable();
-	bpmp_clk_rate_set(BPMP_CLK_DEFAULT_BOOST);
+	bpmp_clk_rate_relaxed(false);
+
+	// Re-enable AHB aperture.
+	mc_enable_ahb_redirect(1);

 	return res;
 }
--- a/bdk/sec/tsec.h
+++ b/bdk/sec/tsec.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
-* Copyright (c) 2018 CTCaer
+* Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -20,15 +20,23 @@

 #include <utils/types.h>

+enum tsec_fw_type
+{
+	// Retail Hovi Keygen.
+	TSEC_FW_TYPE_OLD = 0, // 1.0.0 - 6.1.0.
+	TSEC_FW_TYPE_EMU = 1, // 6.2.0 emulated environment.
+	TSEC_FW_TYPE_NEW = 2, // 7.0.0+.
+};
+
 typedef struct _tsec_ctxt_t
 {
 	void *fw;
 	u32 size;
+	u32 type;
 	void *pkg1;
 	u32 pkg11_off;
-	u32 secmon_base;
 } tsec_ctxt_t;

-int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt);
+int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt);

 #endif
--- a/bdk/sec/tsec_t210.h
+++ b/bdk/sec/tsec_t210.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2018 CTCaer
+* Copyright (c) 2018-2023 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -17,33 +17,33 @@
 #ifndef _TSEC_T210_H_
 #define _TSEC_T210_H_

-#define TSEC_BOOTKEYVER    0x1040
-#define TSEC_STATUS        0x1044
+#define TSEC_MAILBOX0      0x1040
+#define TSEC_MAILBOX1      0x1044
 #define TSEC_ITFEN         0x1048
-#define  TSEC_ITFEN_CTXEN         (1 << 0)
-#define  TSEC_ITFEN_MTHDEN        (1 << 1)
+#define  TSEC_ITFEN_CTXEN         BIT(0)
+#define  TSEC_ITFEN_MTHDEN        BIT(1)
 #define TSEC_IRQMSET       0x1010
-#define  TSEC_IRQMSET_WDTMR       (1 << 1)
-#define  TSEC_IRQMSET_HALT        (1 << 4)
-#define  TSEC_IRQMSET_EXTERR      (1 << 5)
-#define  TSEC_IRQMSET_SWGEN0      (1 << 6)
-#define  TSEC_IRQMSET_SWGEN1      (1 << 7)
+#define  TSEC_IRQMSET_WDTMR       BIT(1)
+#define  TSEC_IRQMSET_HALT        BIT(4)
+#define  TSEC_IRQMSET_EXTERR      BIT(5)
+#define  TSEC_IRQMSET_SWGEN0      BIT(6)
+#define  TSEC_IRQMSET_SWGEN1      BIT(7)
 #define  TSEC_IRQMSET_EXT(val)    (((val) & 0xFF) << 8)
 #define TSEC_IRQDEST       0x101C
-#define  TSEC_IRQDEST_HALT        (1 << 4)
-#define  TSEC_IRQDEST_EXTERR      (1 << 5)
-#define  TSEC_IRQDEST_SWGEN0      (1 << 6)
-#define  TSEC_IRQDEST_SWGEN1      (1 << 7)
+#define  TSEC_IRQDEST_HALT        BIT(4)
+#define  TSEC_IRQDEST_EXTERR      BIT(5)
+#define  TSEC_IRQDEST_SWGEN0      BIT(6)
+#define  TSEC_IRQDEST_SWGEN1      BIT(7)
 #define  TSEC_IRQDEST_EXT(val)    (((val) & 0xFF) << 8)
 #define TSEC_CPUCTL       0x1100
-#define  TSEC_CPUCTL_STARTCPU     (1 << 1)
+#define  TSEC_CPUCTL_STARTCPU     BIT(1)
 #define TSEC_BOOTVEC      0x1104
 #define TSEC_DMACTL       0x110C
 #define TSEC_DMATRFBASE   0x1110
 #define TSEC_DMATRFMOFFS  0x1114
 #define TSEC_DMATRFCMD    0x1118
-#define  TSEC_DMATRFCMD_IDLE      (1 << 1)
-#define  TSEC_DMATRFCMD_IMEM      (1 << 4)
+#define  TSEC_DMATRFCMD_IDLE      BIT(1)
+#define  TSEC_DMATRFCMD_IMEM      BIT(4)
 #define  TSEC_DMATRFCMD_SIZE_256B (6 << 8)
 #define TSEC_DMATRFFBOFFS 0x111C

--- a/bdk/soc/actmon.c
+++ b/bdk/soc/actmon.c
@@ -0,0 +1,172 @@
+/*
+ * Activity Monitor driver for Tegra X1
+ *
+ * Copyright (c) 2021 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "actmon.h"
+#include "clock.h"
+#include "t210.h"
+
+/* Global registers */
+#define ACTMON_GLB_STATUS          0x0
+#define  ACTMON_MCCPU_MON_ACT      BIT(8)
+#define  ACTMON_MCALL_MON_ACT      BIT(9)
+#define  ACTMON_CPU_FREQ_MON_ACT   BIT(10)
+#define  ACTMON_APB_MON_ACT        BIT(12)
+#define  ACTMON_AHB_MON_ACT        BIT(13)
+#define  ACTMON_BPMP_MON_ACT       BIT(14)
+#define  ACTMON_CPU_MON_ACT        BIT(15)
+#define  ACTMON_MCCPU_INTR         BIT(25)
+#define  ACTMON_MCALL_INTR         BIT(26)
+#define  ACTMON_CPU_FREQ_INTR      BIT(27)
+#define  ACTMON_APB_INTR           BIT(28)
+#define  ACTMON_AHB_INTR           BIT(29)
+#define  ACTMON_BPMP_INTR          BIT(30)
+#define  ACTMON_CPU_INTR           BIT(31)
+#define ACTMON_GLB_PERIOD_CTRL     0x4
+#define  ACTMON_GLB_PERIOD_USEC    BIT(8)
+#define  ACTMON_GLB_PERIOD_SAMPLE(n) (((n) - 1) & 0xFF)
+
+/* Device Registers */
+#define ACTMON_DEV_BASE            ACTMON_BASE + 0x80
+#define  ACTMON_DEV_SIZE           0x40
+/* CTRL */
+#define  ACTMON_DEV_CTRL_K_VAL(k)                       (((k) & 7) << 10)
+#define  ACTMON_DEV_CTRL_ENB_PERIODIC                   BIT(18)
+#define  ACTMON_DEV_CTRL_AT_END_EN                      BIT(19)
+#define  ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN             BIT(20)
+#define  ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN             BIT(21)
+#define  ACTMON_DEV_CTRL_WHEN_OVERFLOW_EN               BIT(22)
+#define  ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM(n) (((n) & 7) << 23)
+#define  ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM(n) (((n) & 7) << 26)
+#define  ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN     BIT(29)
+#define  ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN     BIT(30)
+#define  ACTMON_DEV_CTRL_ENB                            BIT(31)
+/* INTR_STATUS */
+#define  ACTMON_DEV_ISTS_AVG_ABOVE_WMARK   BIT(24)
+#define  ACTMON_DEV_ISTS_AVG_BELOW_WMARK   BIT(25)
+#define  ACTMON_DEV_ISTS_WHEN_OVERFLOW     BIT(26)
+#define  ACTMON_DEV_ISTS_AT_END            BIT(29)
+#define  ACTMON_DEV_ISTS_CONSECUTIVE_LOWER BIT(30)
+#define  ACTMON_DEV_ISTS_CONSECUTIVE_UPPER BIT(31)
+
+/* Histogram Registers */
+#define ACTMON_HISTOGRAM_CONFIG    0x300
+#define  ACTMON_HIST_CFG_ACTIVE                   BIT(0)
+#define  ACTMON_HIST_CFG_LINEAR_MODE              BIT(1)
+#define  ACTMON_HIST_CFG_NO_UNDERFLOW_BUCKET      BIT(2)
+#define  ACTMON_HIST_CFG_STALL_ON_SINGLE_SATURATE BIT(3)
+#define  ACTMON_HIST_CFG_SHIFT(s)                 (((s) & 0x1F) << 4)
+#define  ACTMON_HIST_CFG_SOURCE(s)                (((s) & 0xF) << 12)
+#define ACTMON_HISTOGRAM_CTRL      0x304
+#define  ACTMON_HIST_CTRL_CLEAR_ALL               BIT(0)
+#define ACTMON_HISTOGRAM_DATA_BASE 0x380
+#define  ACTMON_HISTOGRAM_DATA_NUM 32
+
+#define ACTMON_FREQ      19200000
+#define ACTMON_PERIOD_MS 20
+#define DEV_COUNT_WEIGHT 5
+
+typedef struct _actmon_dev_reg_t
+{
+	vu32 ctrl;
+	vu32 upper_wnark;
+	vu32 lower_wmark;
+	vu32 init_avg;
+	vu32 avg_upper_wmark;
+	vu32 avg_lower_wmark;
+	vu32 count_weight;
+	vu32 count;
+	vu32 avg_count;
+	vu32 intr_status;
+	vu32 ctrl2;
+	vu32 rsvd[5];
+} actmon_dev_reg_t;
+
+void actmon_hist_enable(actmon_hist_src_t src)
+{
+	ACTMON(ACTMON_HISTOGRAM_CONFIG) = ACTMON_HIST_CFG_SOURCE(src) | ACTMON_HIST_CFG_ACTIVE;
+	ACTMON(ACTMON_HISTOGRAM_CTRL) = ACTMON_HIST_CTRL_CLEAR_ALL;
+}
+
+void actmon_hist_disable()
+{
+	ACTMON(ACTMON_HISTOGRAM_CONFIG) = 0;
+}
+
+void actmon_hist_get(u32 *histogram)
+{
+	if (histogram)
+	{
+		for (u32 i = 0; i < ACTMON_HISTOGRAM_DATA_NUM; i++)
+			histogram[i] = ACTMON(ACTMON_HISTOGRAM_DATA_BASE + i * sizeof(u32));
+	}
+}
+
+void actmon_dev_enable(actmon_dev_t dev)
+{
+	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
+
+	regs->init_avg = ACTMON_FREQ * ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT / 100;
+	regs->count_weight = DEV_COUNT_WEIGHT;
+
+	regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(7); // 128 samples average.
+}
+
+void actmon_dev_disable(actmon_dev_t dev)
+{
+	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
+
+	regs->ctrl = 0;
+}
+
+u32 actmon_dev_get_load(actmon_dev_t dev)
+{
+	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
+
+	// Get load-based sampling. 1 decimal point precision.
+	u32 load = regs->count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT));
+
+	return load;
+}
+
+u32 actmon_dev_get_load_avg(actmon_dev_t dev)
+{
+	actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
+
+	// Get load-based sampling. 1 decimal point precision.
+	u32 avg_load = regs->avg_count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT));
+
+	return avg_load;
+}
+
+void atmon_dev_all_disable()
+{
+	// TODO: do a global reset?
+}
+
+void actmon_init()
+{
+	clock_enable_actmon();
+
+	// Set period.
+	ACTMON(ACTMON_GLB_PERIOD_CTRL) = ACTMON_GLB_PERIOD_SAMPLE(ACTMON_PERIOD_MS);
+}
+
+void actmon_end()
+{
+	clock_disable_actmon();
+}
--- a/bdk/soc/actmon.h
+++ b/bdk/soc/actmon.h
@@ -0,0 +1,62 @@
+/*
+ * Activity Monitor driver for Tegra X1
+ *
+ * Copyright (c) 2021 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ACTMON_H_
+#define __ACTMON_H_
+
+#include <utils/types.h>
+
+typedef enum _actmon_dev_t
+{
+	ACTMON_DEV_CPU,
+	ACTMON_DEV_BPMP,
+	ACTMON_DEV_AHB,
+	ACTMON_DEV_APB,
+	ACTMON_DEV_CPU_FREQ,
+	ACTMON_DEV_MC_ALL,
+	ACTMON_DEV_MC_CPU,
+
+	ACTMON_DEV_NUM,
+} actmon_dev_t;
+
+typedef enum _actmon_hist_src_t
+{
+	ACTMON_HIST_SRC_NONE     = 0,
+	ACTMON_HIST_SRC_AHB      = 1,
+	ACTMON_HIST_SRC_APB      = 2,
+	ACTMON_HIST_SRC_BPMP     = 3,
+	ACTMON_HIST_SRC_CPU      = 4,
+	ACTMON_HIST_SRC_MC_ALL   = 5,
+	ACTMON_HIST_SRC_MC_CPU   = 6,
+	ACTMON_HIST_SRC_CPU_FREQ = 7,
+	ACTMON_HIST_SRC_NA       = 8,
+	ACTMON_HIST_SRC_APB_MMIO = 9,
+} actmon_hist_src_t;
+
+void actmon_hist_enable(actmon_hist_src_t src);
+void actmon_hist_disable();
+void actmon_hist_get(u32 *histogram);
+void actmon_dev_enable(actmon_dev_t dev);
+void actmon_dev_disable(actmon_dev_t dev);
+u32  actmon_dev_get_load(actmon_dev_t dev);
+u32  actmon_dev_get_load_avg(actmon_dev_t dev);
+void atmon_dev_all_disable();
+void actmon_init();
+void actmon_end();
+
+#endif
--- a/bdk/soc/bpmp.c
+++ b/bdk/soc/bpmp.c
@@ -1,7 +1,7 @@
 /*
 * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
 *
- * Copyright (c) 2019-2020 CTCaer
+ * Copyright (c) 2019-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -18,45 +18,45 @@

 #include <soc/bpmp.h>
 #include <soc/clock.h>
+#include <soc/timer.h>
 #include <soc/t210.h>
 #include <memory_map.h>
-#include <utils/util.h>

 #define BPMP_MMU_CACHE_LINE_SIZE        0x20

 #define BPMP_CACHE_CONFIG               0x0
-#define  CFG_ENABLE_CACHE               (1 << 0)
-#define  CFG_ENABLE_SKEW_ASSOC          (1 << 1)
-#define  CFG_DISABLE_RANDOM_ALLOC       (1 << 2)
-#define  CFG_FORCE_WRITE_THROUGH        (1 << 3)
-#define  CFG_NEVER_ALLOCATE             (1 << 6)
-#define  CFG_ENABLE_INTERRUPT           (1 << 7)
-#define  CFG_MMU_TAG_MODE(x)            (x << 8)
+#define  CFG_ENABLE_CACHE               BIT(0)
+#define  CFG_ENABLE_SKEW_ASSOC          BIT(1)
+#define  CFG_DISABLE_RANDOM_ALLOC       BIT(2)
+#define  CFG_FORCE_WRITE_THROUGH        BIT(3)
+#define  CFG_NEVER_ALLOCATE             BIT(6)
+#define  CFG_ENABLE_INTERRUPT           BIT(7)
+#define  CFG_MMU_TAG_MODE(x)            ((x) << 8)
 #define   TAG_MODE_PARALLEL             0
 #define   TAG_MODE_TAG_FIRST            1
 #define   TAG_MODE_MMU_FIRST            2
-#define  CFG_DISABLE_WRITE_BUFFER       (1 << 10)
-#define  CFG_DISABLE_READ_BUFFER        (1 << 11)
-#define  CFG_ENABLE_HANG_DETECT         (1 << 12)
-#define  CFG_FULL_LINE_DIRTY            (1 << 13)
-#define  CFG_TAG_CHK_ABRT_ON_ERR        (1 << 14)
-#define  CFG_TAG_CHK_CLR_ERR            (1 << 15)
-#define  CFG_DISABLE_SAMELINE           (1 << 16)
-#define  CFG_OBS_BUS_EN                 (1 << 31)
+#define  CFG_DISABLE_WRITE_BUFFER       BIT(10)
+#define  CFG_DISABLE_READ_BUFFER        BIT(11)
+#define  CFG_ENABLE_HANG_DETECT         BIT(12)
+#define  CFG_FULL_LINE_DIRTY            BIT(13)
+#define  CFG_TAG_CHK_ABRT_ON_ERR        BIT(14)
+#define  CFG_TAG_CHK_CLR_ERR            BIT(15)
+#define  CFG_DISABLE_SAMELINE           BIT(16)
+#define  CFG_OBS_BUS_EN                 BIT(31)

 #define BPMP_CACHE_LOCK                 0x4
-#define  LOCK_LINE(x)                   (1 << x)
+#define  LOCK_LINE(x)                   BIT((x))

 #define BPMP_CACHE_SIZE                 0xC
 #define BPMP_CACHE_LFSR                 0x10

 #define BPMP_CACHE_TAG_STATUS           0x14
-#define  TAG_STATUS_TAG_CHECK_ERROR     (1 << 0)
+#define  TAG_STATUS_TAG_CHECK_ERROR     BIT(0)
 #define  TAG_STATUS_CONFLICT_ADDR_MASK  0xFFFFFFE0

 #define BPMP_CACHE_CLKEN_OVERRIDE       0x18
-#define  CLKEN_OVERRIDE_WR_MCCIF_CLKEN  (1 << 0)
-#define  CLKEN_OVERRIDE_RD_MCCIF_CLKEN  (1 << 1)
+#define  CLKEN_OVERRIDE_WR_MCCIF_CLKEN  BIT(0)
+#define  CLKEN_OVERRIDE_RD_MCCIF_CLKEN  BIT(1)

 #define BPMP_CACHE_MAINT_ADDR           0x20
 #define BPMP_CACHE_MAINT_DATA           0x24
@@ -68,8 +68,8 @@
 #define BPMP_CACHE_INT_CLEAR            0x44
 #define BPMP_CACHE_INT_RAW_EVENT        0x48
 #define BPMP_CACHE_INT_STATUS           0x4C
-#define  INT_MAINT_DONE                 (1 << 0)
-#define  INT_MAINT_ERROR                (1 << 1)
+#define  INT_MAINT_DONE                 BIT(0)
+#define  INT_MAINT_ERROR                BIT(1)

 #define BPMP_CACHE_RB_CFG               0x80
 #define BPMP_CACHE_WB_CFG               0x84
@@ -78,12 +78,12 @@
 #define BPMP_CACHE_MMU_SHADOW_COPY_MASK 0xA4

 #define BPMP_CACHE_MMU_CFG              0xAC
-#define  MMU_CFG_BLOCK_MAIN_ENTRY_WR    (1 << 0)
-#define  MMU_CFG_SEQ_EN                 (1 << 1)
-#define  MMU_CFG_TLB_EN                 (1 << 2)
-#define  MMU_CFG_SEG_CHECK_ALL_ENTRIES  (1 << 3)
-#define  MMU_CFG_ABORT_STORE_LAST       (1 << 4)
-#define  MMU_CFG_CLR_ABORT              (1 << 5)
+#define  MMU_CFG_BLOCK_MAIN_ENTRY_WR    BIT(0)
+#define  MMU_CFG_SEQ_EN                 BIT(1)
+#define  MMU_CFG_TLB_EN                 BIT(2)
+#define  MMU_CFG_SEG_CHECK_ALL_ENTRIES  BIT(3)
+#define  MMU_CFG_ABORT_STORE_LAST       BIT(4)
+#define  MMU_CFG_CLR_ABORT              BIT(5)

 #define BPMP_CACHE_MMU_CMD              0xB0
 #define  MMU_CMD_NOP                    0
@@ -98,27 +98,27 @@
 #define  ABORT_STAT_UNIT_TLB            3
 #define  ABORT_STAT_UNIT_SEG            4
 #define  ABORT_STAT_UNIT_FALLBACK       5
-#define  ABORT_STAT_OVERLAP             (1 << 3)
+#define  ABORT_STAT_OVERLAP             BIT(3)
 #define  ABORT_STAT_ENTRY               (0x1F << 4)
 #define  ABORT_STAT_TYPE_MASK           (3 << 16)
 #define  ABORT_STAT_TYPE_EXE            (0 << 16)
 #define  ABORT_STAT_TYPE_RD             (1 << 16)
 #define  ABORT_STAT_TYPE_WR             (2 << 16)
 #define  ABORT_STAT_SIZE                (3 << 18)
-#define  ABORT_STAT_SEQ                 (1 << 20)
-#define  ABORT_STAT_PROT                (1 << 21)
+#define  ABORT_STAT_SEQ                 BIT(20)
+#define  ABORT_STAT_PROT                BIT(21)

 #define BPMP_CACHE_MMU_ABORT_ADDR       0xB8
 #define BPMP_CACHE_MMU_ACTIVE_ENTRIES   0xBC

 #define BPMP_MMU_SHADOW_ENTRY_BASE      (BPMP_CACHE_BASE + 0x400)
 #define BPMP_MMU_MAIN_ENTRY_BASE        (BPMP_CACHE_BASE + 0x800)
-#define  MMU_EN_CACHED                  (1 << 0)
-#define  MMU_EN_EXEC                    (1 << 1)
-#define  MMU_EN_READ                    (1 << 2)
-#define  MMU_EN_WRITE                   (1 << 3)
+#define  MMU_EN_CACHED                  BIT(0)
+#define  MMU_EN_EXEC                    BIT(1)
+#define  MMU_EN_READ                    BIT(2)
+#define  MMU_EN_WRITE                   BIT(3)

-bpmp_mmu_entry_t mmu_entries[] =
+static const bpmp_mmu_entry_t mmu_entries[] =
 {
 	{ DRAM_START, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
 	{ IRAM_BASE,  0x4003FFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
@@ -134,13 +134,13 @@ void bpmp_mmu_maintenance(u32 op, bool force)
 	// This is a blocking operation.
 	BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op;

-	while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_MAINT_DONE))
+	while (!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_MAINT_DONE))
 		;

 	BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT);
 }

-void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
+void bpmp_mmu_set_entry(int idx, const bpmp_mmu_entry_t *entry, bool apply)
 {
 	if (idx > 31)
 		return;
@@ -150,10 +150,10 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
 	if (entry->enable)
 	{
 		mmu_entry->start_addr = ALIGN(entry->start_addr, BPMP_MMU_CACHE_LINE_SIZE);
-		mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE);
-		mmu_entry->attr = entry->attr;
+		mmu_entry->end_addr   = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE);
+		mmu_entry->attr       = entry->attr;

-		BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= (1 << idx);
+		BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= BIT(idx);

 		if (apply)
 			BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
@@ -166,13 +166,13 @@ void bpmp_mmu_enable()
 		return;

 	// Init BPMP MMU.
-	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT;
+	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD)            = MMU_CMD_INIT;
 	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_FALLBACK_ENTRY) = MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC; // RWX for non-defined regions.
-	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST;
+	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG)            = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST;

 	// Init BPMP MMU entries.
 	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0;
-	for (u32 idx = 0; idx < (sizeof(mmu_entries) / sizeof(bpmp_mmu_entry_t)); idx++)
+	for (u32 idx = 0; idx < ARRAY_SIZE(mmu_entries); idx++)
 		bpmp_mmu_set_entry(idx, &mmu_entries[idx], false);

 	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
@@ -200,36 +200,73 @@ void bpmp_mmu_disable()
 	BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0;
 }

+
+/*
+ * CLK_RST_CONTROLLER_SCLK_BURST_POLICY:
+ * 0 = CLKM
+ * 1 = PLLC_OUT1
+ * 2 = PLLC4_OUT3
+ * 3 = PLLP_OUT0
+ * 4 = PLLP_OUT2
+ * 5 = PLLC4_OUT1
+ * 6 = CLK_S
+ * 7 = PLLC4_OUT2
+ */
+
+bpmp_freq_t bpmp_fid_current = BPMP_CLK_NORMAL;
+
+void bpmp_clk_rate_relaxed(bool enable)
+{
+	// This is a glitch-free way to reduce the SCLK timings.
+	if (enable)
+	{
+		// Restore to PLLP source during PLLC configuration.
+		CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT.
+		(void)CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY);
+		usleep(100); // Wait a bit for clock source change.
+		CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // S1:H1:P3.
+		(void)CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE);
+	}
+	else if (bpmp_fid_current)
+	{
+		// Restore to PLLC_OUT1.
+		CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // S1:H1:P4.
+		CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 and CLKM for idle.
+		(void)CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY);
+		usleep(100); // Wait a bit for clock source change.
+	}
+}
+
 // APB clock affects RTC, PWM, MEMFETCH, APE, USB, SOR PWM,
 // I2C host, DC/DSI/DISP. UART gives extra stress.
 // 92: 100% success ratio. 93-94: 595-602MHz has 99% success ratio. 95: 608MHz less.
-const u8 pll_divn[] = {
+// APB clock max is supposed to be 204 MHz though.
+static const u8 pll_divn[] = {
 	0,   // BPMP_CLK_NORMAL:      408MHz  0% - 136MHz APB.
 	85,  // BPMP_CLK_HIGH_BOOST:  544MHz 33% - 136MHz APB.
+	88,  // BPMP_CLK_HIGH2_BOOST: 563MHz 38% - 141MHz APB.
 	90,  // BPMP_CLK_SUPER_BOOST: 576MHz 41% - 144MHz APB.
-	92   // BPMP_CLK_HYPER_BOOST: 589MHz 44% - 147MHz APB.
+	92,  // BPMP_CLK_HYPER_BOOST: 589MHz 44% - 147MHz APB.
 	// Do not use for public releases!
 	//95   // BPMP_CLK_DEV_BOOST: 608MHz 49% - 152MHz APB.
 };

-bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;
-
 void bpmp_clk_rate_get()
 {
 	bool clk_src_is_pllp = ((CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) >> 4) & 7) == 3;

 	if (clk_src_is_pllp)
-		bpmp_clock_set = BPMP_CLK_NORMAL;
+		bpmp_fid_current = BPMP_CLK_NORMAL;
 	else
 	{
-		bpmp_clock_set = BPMP_CLK_HIGH_BOOST;
+		bpmp_fid_current = BPMP_CLK_HIGH_BOOST;

 		u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
 		for (u32 i = 1; i < sizeof(pll_divn); i++)
 		{
 			if (pll_divn[i] == pll_divn_curr)
 			{
-				bpmp_clock_set = i;
+				bpmp_fid_current = i;
 				break;
 			}
 		}
@@ -238,38 +275,37 @@ void bpmp_clk_rate_get()

 void bpmp_clk_rate_set(bpmp_freq_t fid)
 {
-	if (fid > (BPMP_CLK_MAX - 1))
-		fid = BPMP_CLK_MAX - 1;
+	if (fid >= BPMP_CLK_NUM)
+		fid = BPMP_CLK_NUM - 1;

-	if (bpmp_clock_set == fid)
+	if (bpmp_fid_current == fid)
 		return;

+	bpmp_fid_current = fid;
+
+	// Use default SCLK / HCLK / PCLK clocks.
+	bpmp_clk_rate_relaxed(true);
+
 	if (fid)
 	{
-		if (bpmp_clock_set)
-		{
-			// Restore to PLLP source during PLLC4 configuration.
-			CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT.
-			msleep(1); // Wait a bit for clock source change.
-		}
-
 		// Configure and enable PLLC.
 		clock_enable_pllc(pll_divn[fid]);

-		// Set SCLK / HCLK / PCLK.
-		CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
-		CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 for active and CLKM for idle.
+		// Set new source and SCLK / HCLK / PCLK dividers.
+		bpmp_clk_rate_relaxed(false);
 	}
 	else
 	{
-		CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT for active and CLKM for idle.
-		msleep(1); // Wait a bit for clock source change.
-		CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
-
 		// Disable PLLC to save power.
 		clock_disable_pllc();
 	}
-	bpmp_clock_set = fid;
+}
+
+// State is reset to RUN on any clock or source set via SW.
+void bpmp_state_set(bpmp_state_t state)
+{
+	u32 cfg = CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & ~0xF0000000u;
+	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = cfg | (state << 28u);
 }

 // The following functions halt BPMP to reduce power while sleeping.
@@ -281,10 +317,10 @@ void bpmp_usleep(u32 us)
 	// Each iteration takes 1us.
 	while (us)
 	{
-		delay = (us > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : us;
+		delay = (us > HALT_MAX_CNT) ? HALT_MAX_CNT : us;
 		us -= delay;

-		FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_USEC | delay;
+		FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_USEC | delay;
 	}
 }

@@ -295,14 +331,14 @@ void bpmp_msleep(u32 ms)
 	// Iteration time is variable. ~200 - 1000us.
 	while (ms)
 	{
-		delay = (ms > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : ms;
+		delay = (ms > HALT_MAX_CNT) ? HALT_MAX_CNT : ms;
 		ms -= delay;

-		FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_MSEC | delay;
+		FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_MSEC | delay;
 	}
 }

 void bpmp_halt()
 {
-	FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_JTAG;
+	FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_JTAG;
 }
--- a/bdk/soc/bpmp.h
+++ b/bdk/soc/bpmp.h
@@ -1,7 +1,7 @@
 /*
 * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
 *
- * Copyright (c) 2019-2020 CTCaer
+ * Copyright (c) 2019-2025 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -47,20 +47,40 @@ typedef enum
 {
 	BPMP_CLK_NORMAL,      // 408MHz  0% - 136MHz APB.
 	BPMP_CLK_HIGH_BOOST,  // 544MHz 33% - 136MHz APB.
+	BPMP_CLK_HIGH2_BOOST, // 563MHz 38% - 141MHz APB.
 	BPMP_CLK_SUPER_BOOST, // 576MHz 41% - 144MHz APB.
 	BPMP_CLK_HYPER_BOOST, // 589MHz 44% - 147MHz APB.
 	//BPMP_CLK_DEV_BOOST, // 608MHz 49% - 152MHz APB.
-	BPMP_CLK_MAX
+	BPMP_CLK_NUM
 } bpmp_freq_t;

-#define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_HYPER_BOOST
+typedef enum
+{
+	BPMP_STATE_STANDBY = 0, // 32KHz.
+	BPMP_STATE_IDLE    = 1,
+	BPMP_STATE_RUN     = 2,
+
+	BPMP_STATE_IRQ     = BIT(2),
+	BPMP_STATE_FIQ     = BIT(3),
+} bpmp_state_t;
+
+#define BPMP_CLK_BIN0_BOOST    BPMP_CLK_HYPER_BOOST
+#define BPMP_CLK_BIN1_BOOST    BPMP_CLK_SUPER_BOOST
+#define BPMP_CLK_BIN2_BOOST    BPMP_CLK_HIGH2_BOOST
+#define BPMP_CLK_BIN3_BOOST    BPMP_CLK_HIGH_BOOST
+
+#define BPMP_CLK_LOWEST_BOOST  BPMP_CLK_BIN3_BOOST
+#define BPMP_CLK_LOWER_BOOST   BPMP_CLK_BIN1_BOOST
+#define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_BIN0_BOOST

 void bpmp_mmu_maintenance(u32 op, bool force);
-void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
+void bpmp_mmu_set_entry(int idx, const bpmp_mmu_entry_t *entry, bool apply);
 void bpmp_mmu_enable();
 void bpmp_mmu_disable();
+void bpmp_clk_rate_relaxed(bool enable);
 void bpmp_clk_rate_get();
 void bpmp_clk_rate_set(bpmp_freq_t fid);
+void bpmp_state_set(bpmp_state_t state);
 void bpmp_usleep(u32 us);
 void bpmp_msleep(u32 ms);
 void bpmp_halt();
--- a/Show More
+++ b/Show More