Bump hekate to v5.3.2

Additionally, screenshots are allowed only every 2s instead per second.

Makefile

@@ -16,11 +16,14 @@ TARGET := hekate
 BUILDDIR := build
 OUTPUTDIR := output
 SOURCEDIR = bootloader
+BDKDIR := bdk
+BDKINC := -I./$(BDKDIR)
 VPATH = $(dir ./$(SOURCEDIR)/) $(dir $(wildcard ./$(SOURCEDIR)/*/)) $(dir $(wildcard ./$(SOURCEDIR)/*/*/))
+VPATH += $(dir $(wildcard ./$(BDKDIR)/)) $(dir $(wildcard ./$(BDKDIR)/*/)) $(dir $(wildcard ./$(BDKDIR)/*/*/))
 
 # Main and graphics.
 OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \
-	start.o \
+	start.o exception_handlers.o \
 	main.o heap.o \
 	gfx.o tui.o \
 	fe_emmc_tools.o fe_info.o fe_tools.o \
@@ -28,9 +31,10 @@ OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \
 
 # Hardware.
 OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
-	bpmp.o clock.o cluster.o di.o gpio.o i2c.o mc.o sdram.o pinmux.o se.o smmu.o tsec.o uart.o \
+	bpmp.o ccplex.o clock.o di.o gpio.o i2c.o irq.o mc.o sdram.o \
+	pinmux.o pmc.o se.o smmu.o tsec.o uart.o \
 	fuse.o kfuse.o minerva.o \
-	sdmmc.o sdmmc_driver.o emummc.o nx_emmc.o \
+	sdmmc.o sdmmc_driver.o emummc.o nx_emmc.o nx_sd.o \
 	bq24193.o max17050.o max7762x.o max77620-rtc.o \
 	hw_init.o \
 )
@@ -53,12 +57,15 @@ OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
 	elfload.o elfreloc_arm.o \
 )
 
+GFX_INC   := '"../$(SOURCEDIR)/gfx/gfx.h"'
+FFCFG_INC := '"../$(SOURCEDIR)/libs/fatfs/ffconf.h"'
+
 ################################################################################
 
 CUSTOMDEFINES := -DIPL_LOAD_ADDR=$(IPL_LOAD_ADDR) -DBL_MAGIC=$(IPL_MAGIC)
 CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_RESERVED=$(BLVERSION_RSVD)
 CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_RESERVED=$(NYXVERSION_RSVD)
-#CUSTOMDEFINES += -DMENU_LOGO_ENABLE
+CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC)
 
 # 0: UART_A, 1: UART_B.
 #CUSTOMDEFINES += -DDEBUG_UART_PORT=0
@@ -66,7 +73,7 @@ CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINO
 #CUSTOMDEFINES += -DDEBUG
 
 ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-CFLAGS = $(ARCH) -O2 -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 -Wall $(CUSTOMDEFINES)
+CFLAGS = $(ARCH) -O2 -g -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 -Wall $(CUSTOMDEFINES)
 LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections -Xlinker --defsym=IPL_LOAD_ADDR=$(IPL_LOAD_ADDR)
 
 MODULEDIRS := $(wildcard modules/*)
@@ -77,11 +84,14 @@ NYXDIR := $(wildcard nyx)
 .PHONY: all clean $(MODULEDIRS) $(NYXDIR)
 
 all: $(TARGET).bin
-	@echo -n "Payload size is "
+	@printf ICTC49 >> $(OUTPUTDIR)/$(TARGET).bin
+	@echo "--------------------------------------"
+	@echo -n "Payload size: "
 	$(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET).bin))
-	@echo $(BIN_SIZE)
-	@echo "Max size is     126296 Bytes."
+	@echo $(BIN_SIZE)" Bytes"
+	@echo "Payload Max:  126296 Bytes"
 	@if [ ${BIN_SIZE} -gt 126296 ]; then echo "\e[1;33mPayload size exceeds limit!\e[0m"; fi
+	@echo "--------------------------------------"
 
 clean:
 	@rm -rf $(OBJS)
@@ -89,23 +99,25 @@ clean:
 	@rm -rf $(OUTPUTDIR)
 
 $(MODULEDIRS):
-	$(MAKE) -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)
 
 $(NYXDIR):
-	$(MAKE) -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)
+	@$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS)
 
 $(TARGET).bin: $(BUILDDIR)/$(TARGET)/$(TARGET).elf $(MODULEDIRS) $(NYXDIR)
 	$(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$@
-	@printf ICTC49 >> $(OUTPUTDIR)/$@
 
 $(BUILDDIR)/$(TARGET)/$(TARGET).elf: $(OBJS)
-	$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@
+	@$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@
+	@echo "hekate was built with the following flags:\nCFLAGS:  "$(CFLAGS)"\nLDFLAGS: "$(LDFLAGS)
 
 $(BUILDDIR)/$(TARGET)/%.o: %.c
-	$(CC) $(CFLAGS) -c $< -o $@
+	@echo Building $@
+	@$(CC) $(CFLAGS) $(BDKINC) -c $< -o $@
 
 $(BUILDDIR)/$(TARGET)/%.o: %.S
-	$(CC) $(CFLAGS) -c $< -o $@
+	@echo Building $@
+	@$(CC) $(CFLAGS) -c $< -o $@
 
 $(OBJS): $(BUILDDIR)/$(TARGET)
 

README.md

@@ -1,9 +1,9 @@
-# hekate - CTCaer mod
+# hekate - Nyx
 
 ![Image of Hekate](https://user-images.githubusercontent.com/3665130/60391760-bc1e8c00-9afe-11e9-8b7a-b065873081b2.png)
 
 
-Custom Nintendo Switch bootloader, firmware patcher, and more.
+Custom Graphical Nintendo Switch bootloader, firmware patcher, tools, and many more.
 
 
 ## Bootloader folders and files
@@ -30,7 +30,7 @@ Custom Nintendo Switch bootloader, firmware patcher, and more.
 | bootloader/screenshots/  | Folder where Nyx screenshots are saved                                |
 | bootloader/payloads/     | For payloads. 'Payloads...' menu. Autoboot only supported by including them into an ini. All CFW bootloaders, tools, Linux payloads are supported. |
 | bootloader/libtools/     | Future reserved                                                       |
-| sept                     | Sept folder. This must be always get updated via the Atmosphère release zip. Needed for tools and booting HOS on 7.0.0 and up. Unused for booting HOS if `fss0=` key is defined. |
+| sept                     | Sept folder. This must always get updated via the Atmosphère release zip. Needed for tools and booting HOS on 7.0.0 and up. Unused for booting HOS if `fss0=` key is defined. |
 
 **Note**: Sept files for booting 7.0.0 and up are expected at /sept folder at root of sd card.
 
@@ -53,14 +53,24 @@ You can find a template [Here](./res/hekate_ipl_template.ini)
 | autoboot=0         | 0: Disable, #: Boot entry number to auto boot.             |
 | autoboot_list=0    | 0: Read `autoboot` boot entry from hekate_ipl.ini, 1: Read from ini folder (ini files are ASCII ordered). |
 | bootwait=3         | 0: Disable (It also disables bootlogo. Having **VOL-** pressed since injection goes to menu.), #: Time to wait for **VOL-** to enter menu. |
-| verification=2     | 0: Disable Backup/Restore verification, 1: Sparse (block based, fast and not 100% reliable), 2: Full (sha256 based, slow and 100% reliable). |
 | autohosoff=1       | 0: Disable, 1: If woke up from HOS via an RTC alarm, shows logo, then powers off completely, 2: No logo, immediately powers off.|
 | autonogc=1         | 0: Disable, 1: Automatically applies nogc patch if unburnt fuses found and a >= 4.0.0 HOS is booted. |
 | updater2p=0        | 0: Disable, 1: Force updates (if needed) the reboot2payload binary to be hekate. |
 | backlight=100      | Screen backlight level. 0-255.                             |
 
 
-### Possible boot entry key/value combinations:
+### Nyx Global Configuration keys/values for (nyx.ini):
+
+| Config option      | Description                                                |
+| ------------------ | ---------------------------------------------------------- |
+| themecolor=167     | Sets Nyx color of text highlights.                         |
+| timeoff=100        | Sets time offset in HEX. Must be in HOS epoch format       |
+| homescreen=0       | Sets home screen. 0: Home menu, 1: All configs (merges Launch and More configs), 2: Launch, 3: More Configs. |
+| verification=1     | 0: Disable Backup/Restore verification, 1: Sparse (block based, fast and mostly reliable), 2: Full (sha256 based, slow and 100% reliable). |
+| umsemmcrw=1        | 1: eMMC/emuMMC UMS will be mounted as writable by default. |
+
+
+### Boot entry key/value combinations:
 
 | Config option          | Description                                                |
 | ---------------------- | ---------------------------------------------------------- |
@@ -75,15 +85,26 @@ You can find a template [Here](./res/hekate_ipl_template.ini)
 | fullsvcperm=1          | Disables SVC verification (full services permission)       |
 | debugmode=1            | Enables Debug mode. Obsolete when used with exosphere as secmon. |
 | atmosphere=1           | Enables Atmosphère patching.                               |
-| nouserexceptions=1     | Disables usermode exception handlers when paired with Exosphère. |
-| userpmu=1              | Allows user access to PMU when paired with Exosphère.      |
-| emummc_force_disable=1 | Disabled emuMMC if it's enabled.                           |
-| stock=1                | Disables unneeded kernel patching when running stock or semi-stock. `If emuMMC is enabled, emummc_force_disabled=1` is required to run completely stock. |
+| emupath={SD folder}    | Forces emuMMC to use the selected one. (=emuMMC/RAW1, =emuMMC/SD00, etc). emuMMC must be created by hekate because it uses the raw_based/file_based files. |
+| emummcforce=1          | Forces the use of emuMMC. If emummc.ini is disabled or not found, then it causes an error. |
+| emummc_force_disable=1 | Disables emuMMC, if it's enabled.                           |
+| stock=1                | Disables unneeded kernel patching when running stock or semi-stock. `If emuMMC is enabled, emummc_force_disabled=1` is required. emuMMC is not supported on stock. If additional KIPs are needed other than OFW's, you can define them with `kip1` key. No kip should be used that relies on Atmosphère patching, because it will hang. If `NOGC` is needed, use `kip1patch=nogc`. |
 | id=idname              | Identifies boot entry for forced boot via id. Max 7 chars. |
 | payload={SD path}      | Payload launching. Tools, Linux, CFW bootloaders, etc.     |
 | logopath={SD path}     | If no logopath, `bootloader/bootlogo.bmp` will be used if exists. If logopath exists, it will load the specified bitmap. |
 | icon={SD path}         | Force Nyx to use the icon defined here. If this is not found, it will check for a bmp named as the boot entry ([Test 2] -> `bootloader/res/Test 2.bmp`). Otherwise default will be used. |
 
+
+### Boot entry key/value Exosphère combinations:
+
+| Config option          | Description                                                |
+| ---------------------- | ---------------------------------------------------------- |
+| nouserexceptions=1     | Disables usermode exception handlers when paired with Exosphère. |
+| userpmu=1              | Enables user access to PMU when paired with Exosphère.     |
+| cal0blank=1            | Overrides Exosphère config `blank_prodinfo_{sys/emu}mmc`. If that key doesn't exist, `exosphere.ini` will be used. |
+| cal0writesys=1         | Overrides Exosphère config `allow_writing_to_cal_sysmmc`. If that key doesn't exist, `exosphere.ini` will be used. |
+
+
 **Note1**: When using the wildcard (`/*`) with `kip1` you can still use the normal `kip1` after that to load extra single kips.
 
 **Note2**: When using FSS0 it parses exosphere, warmboot and all core kips. You can override the first 2 by using `secmon`/`warmboot` after defining `fss0`.
@@ -97,32 +118,37 @@ This is in case the kips are incompatible between them. If compatible, you can o
 
 hekate has a boot storage in the binary that helps it configure it outside of BPMP enviroment:
 
-| Offset / Name        | Description                                                       |
-| -------------------- | ----------------------------------------------------------------- |
-| '0x94' boot_cfg      | bit0: Force AutoBoot, bit1: Show launch log, bit2: Boot from ID, bit7: sept run. |
-| '0x95' autoboot      | If `Force AutoBoot`: 0: Force go to menu, else boot that entry.   |
-| '0x96' autoboot_list | If `Force AutoBoot` and `autoboot` then it boots from ini folder. |
-| '0x97' extra_cfg     | bit7: Force Nyx to run `Dump pkg1/2`.                             |
-| '0x98' id[8]         | When Boot from ID is set, it will search all inis automatically and find the boot entry with that id and boot it. Must be NULL terminated. |
-| '0x98' xt_str[128]   | Depends on the set cfg bits.                                      |
+| Offset / Name           | Description                                                       |
+| ----------------------- | ----------------------------------------------------------------- |
+| '0x94' boot_cfg         | bit0: `Force AutoBoot`, bit1: `Show launch log`, bit2: `Boot from ID`, bit3: `Boot to emuMMC`, bit6: `Boot to UMS`, bit7: `sept run`. |
+| '0x95' autoboot         | If `Force AutoBoot`: 0: Force go to menu, else boot that entry.   |
+| '0x96' autoboot_list    | If `Force AutoBoot` and `autoboot` then it boots from ini folder. |
+| '0x97' extra_cfg        | bit7: Force Nyx to run `Dump pkg1/2`.                             |
+| '0x98' xt_str[128]      | Depends on the set cfg bits.                                      |
+| '0x98' ums[1]           | When `Boot to UMS` is set, it will launch the selected UMS. 0: SD, 1: eMMC BOOT0, 2: eMMC BOOT1, 3: eMMC GPP, 4: emuMMC BOOT0, 5: emuMMC BOOT1, 6: emuMMC GPP,  |
+| '0x98' id[8]            | When `Boot from ID` is set, it will search all inis automatically and find the boot entry with that id and boot it. Must be NULL terminated. |
+| '0xA0' emummc_path[120] | When `Boot to emuMMC` is set, it will override the current emuMMC (boot entry or emummc.ini). Must be NULL terminated. |
 
 
 If the main .ini is not found, it is created on the first hekate boot.
 
 
 ```
-hekate     (C) 2018 naehrwert, st4rk
-CTCaer mod (C) 2018 CTCaer.
+hekate  (c) 2018,      naehrwert, st4rk.
+        (c) 2018-2020, CTCaer.
+
+Nyx GUI (c) 2019-2020, CTCaer.
 
 Thanks to: derrek, nedwill, plutoo, shuffle2, smea, thexyz, yellows8.
 Greetings to: fincs, hexkyz, SciresM, Shiny Quagsire, WinterMute.
 
 Open source and free packages used:
- - FatFs R0.13a, Copyright (C) 2017, ChaN
- - bcl-1.2.0, Copyright (C) 2003-2006, Marcus Geelnard
+ - FatFs R0.13a, Copyright (c) 2017, ChaN
+ - bcl-1.2.0, Copyright (c) 2003-2006, Marcus Geelnard
  - Atmosphère (Exosphere types/panic, prc id kernel patches),
-   Copyright (C) 2018-2019, Atmosphère-NX
- - elfload, Copyright (C) 2014 Owen Shepherd, Copyright (C) 2018 M4xw
+   Copyright (c) 2018-2019, Atmosphère-NX
+ - elfload, Copyright (c) 2014 Owen Shepherd, Copyright (c) 2018 M4xw
+ - Littlev Graphics Library, Copyright (c) 2016 Gabor Kiss-Vamosi
 
                          ___
                       .-'   `'.

Versions.inc

@@ -1,11 +1,11 @@
 # IPL Version.
 BLVERSION_MAJOR := 5
-BLVERSION_MINOR := 1
-BLVERSION_HOTFX := 4
+BLVERSION_MINOR := 3
+BLVERSION_HOTFX := 2
 BLVERSION_RSVD := 0
 
 # Nyx Version.
 NYXVERSION_MAJOR := 0
-NYXVERSION_MINOR := 8
-NYXVERSION_HOTFX := 7
+NYXVERSION_MINOR := 9
+NYXVERSION_HOTFX := 3
 NYXVERSION_RSVD := 0

bdk/exception_handlers.S

@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Armv7tdmi Status register.
+ *
+ * bit0: Mode 0.
+ * bit1: Mode 1.
+ * bit2: Mode 2.
+ * bit3: Mode 3.
+ * bit4: Mode 4.
+ * bit5: Thumb state.
+ * bit6: FIQ disable.
+ * bit7: IRQ disable.
+ * bit8-27: Reserved.
+ * bit28: Overflow condition.
+ * bit29: Carry/Borrow/Extend condition.
+ * bit30: Zero condition.
+ * bit31: Negative/Less than condition.
+ *
+ * M[4:0] | Mode | Visible Thumb-state registers             | Visible ARM-state registers
+ * 10000  | USER | r0–r7, SP,     LR,     PC, CPSR           | r0–r14,                   PC, CPSR
+ * 10001  | FIQ  | r0–r7, SP_fiq, LR_fiq, PC, CPSR, SPSR_fiq | r0–r7,  r8_fiq–r14_fiq,   PC, CPSR, SPSR_fiq
+ * 10010  | IRQ  | r0–r7, SP_irq, LR_irq, PC, CPSR, SPSR_irq | r0–r12, r13_irq, r14_irq, PC, CPSR, SPSR_irq
+ * 10011  | SVC  | r0–r7, SP_svc, LR_svc, PC, CPSR, SPSR_svc | r0–r12, r13_svc, r14_svc, PC, CPSR, SPSR_svc
+ * 10111  | ABRT | r0–r7, SP_abt, LR_abt, PC, CPSR, SPSR_abt | r0–r12, r13_abt, r14_abt, PC, CPSR, SPSR_abt
+ * 11011  | UNDF | r0–r7, SP_und, LR_und, PC, CPSR, SPSR_und | r0–r12, r13_und, r14_und, PC, CPSR, SPSR_und
+ * 11111  | SYS  | r0–r7, SP,     LR,     PC, CPSR           | r0–r14,                   PC, CPSR
+ */
+
+#define EXCP_EN_ADDR   0x4003FFFC
+#define EXCP_TYPE_ADDR 0x4003FFF8
+#define EXCP_LR_ADDR   0x4003FFF4
+
+#define EXCP_VEC_BASE  0x6000F000
+#define EVP_COP_RESET_VECTOR          0x200
+#define EVP_COP_UNDEF_VECTOR          0x204
+#define EVP_COP_SWI_VECTOR            0x208
+#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
+#define EVP_COP_DATA_ABORT_VECTOR     0x210
+#define EVP_COP_RSVD_VECTOR           0x214
+#define EVP_COP_IRQ_VECTOR            0x218
+#define EVP_COP_FIQ_VECTOR            0x21C
+
+#define MODE_USR  0x10
+#define MODE_FIQ  0x11
+#define MODE_IRQ  0x12
+#define MODE_SVC  0x13
+#define MODE_ABT  0x17
+#define MODE_UDF  0x1B
+#define MODE_SYS  0x1F
+#define MODE_MASK 0x1F
+
+#define FIQ 0x40
+#define IRQ 0x80
+
+.section .text._irq_setup
+.arm
+
+.extern ipl_main
+.type ipl_main, %function
+
+.extern svc_handler
+.type svc_handler, %function
+
+.extern irq_handler
+.type irq_handler, %function
+
+.extern fiq_setup
+.type fiq_setup, %function
+
+.extern fiq_handler
+.type fiq_handler, %function
+
+.globl _irq_setup
+.type _irq_setup, %function
+_irq_setup:
+	MRS R0, CPSR
+	BIC R0, R0, #MODE_MASK              /* Clear mode bits */
+	ORR R0, R0, #(MODE_SVC | IRQ | FIQ) /* SUPERVISOR mode, IRQ/FIQ disabled */
+	MSR CPSR, R0
+
+	/* Setup IRQ stack pointer */
+	MSR CPSR, #(MODE_IRQ | IRQ | FIQ) /* IRQ mode, IRQ/FIQ disabled */
+	LDR SP, =0x40040000
+
+	/* Setup SYS stack pointer */
+	MSR CPSR, #(MODE_SYS | IRQ | FIQ) /* SYSTEM mode, IRQ/FIQ disabled */
+	LDR SP, =0x4003FF00               /* Will be changed later to DRAM */
+
+	MOV LR, PC
+	BL setup_vectors
+	/*BL fiq_setup*/
+
+	/* Enable interrupts */
+	BL irq_enable_cpu_irq_exceptions
+
+	B ipl_main
+	B .
+
+_reset:
+	LDR R0, =EXCP_EN_ADDR
+	LDR R1, =0x30505645 /* EVP0 */
+	STR R1, [R0]        /* EVP0 in EXCP_EN_ADDR */
+	LDR R0, =EXCP_LR_ADDR
+	MOV R1, LR
+	STR R1, [R0]        /* Save LR in EXCP_LR_ADDR */
+	LDR R0, =__bss_start
+	EOR R1, R1, R1
+	LDR R2, =__bss_end
+	SUB R2, R2, R0
+	BL memset
+	B _irq_setup
+
+_reset_handler:
+	LDR R0, =EXCP_TYPE_ADDR
+	LDR R1, =0x545352   /* RST */
+	STR R1, [R0]        /* RST in EXCP_TYPE_ADDR */
+	B _reset
+
+_undefined_handler:
+	LDR R0, =EXCP_TYPE_ADDR
+	LDR R1, =0x464455   /* UDF */
+	STR R1, [R0]        /* UDF in EXCP_TYPE_ADDR */
+	B _reset
+
+_prefetch_abort_handler:
+	LDR R0, =EXCP_TYPE_ADDR
+	LDR R1, =0x54424150 /* PABT */
+	STR R1, [R0]        /* PABT in EXCP_TYPE_ADDR */
+	B _reset
+
+_data_abort_handler:
+	LDR R0, =EXCP_TYPE_ADDR
+	LDR R1, =0x54424144 /* DABT */
+	STR R1, [R0]        /* DABT in EXCP_TYPE_ADDR */
+	B _reset
+
+.globl irq_enable_cpu_irq_exceptions
+.type irq_enable_cpu_irq_exceptions, %function
+irq_enable_cpu_irq_exceptions:
+	MRS R12, CPSR
+	BIC R12, R12, #(IRQ | FIQ) /* IRQ/FIQ enabled */
+	MSR CPSR, R12
+	BX LR
+
+.globl irq_disable_cpu_irq_exceptions
+.type irq_disable_cpu_irq_exceptions, %function
+irq_disable_cpu_irq_exceptions:
+	MRS R12, CPSR
+	ORR R12, R12, #(IRQ | FIQ) /* IRQ/FIQ disabled */
+	MSR CPSR, R12
+	BX LR
+
+_irq_handler:
+	MOV R13, R0    /* Save R0 in R13_IRQ */
+	SUB R0, LR, #4 /* Put return address in R0_SYS */
+	MOV LR, R1     /* Save R1 in R14_IRQ (LR) */
+	MRS R1, SPSR   /* Put the SPSR in R1_SYS */
+
+	MSR CPSR_c, #(MODE_SYS | IRQ)  /* SYSTEM mode, IRQ disabled */
+	STMFD SP!, {R0, R1}            /* SPSR and PC */
+	STMFD SP!, {R2-R3, R12, LR}    /* AAPCS-clobbered registers */
+	MOV R0, SP                     /* Make SP_SYS visible to IRQ mode */
+	SUB SP, SP, #8                 /* Make room for stacking R0 and R1 */
+
+	MSR CPSR_c, #(MODE_IRQ | IRQ) /* IRQ mode, IRQ disabled */
+	STMFD R0!, {R13, R14}         /* Finish saving the context (R0, R1) */
+
+	MSR CPSR_c, #(MODE_SYS | IRQ) /* SYSTEM mode, IRQ disabled */
+	LDR R12, =irq_handler
+	MOV LR, PC                    /* Copy the return address to link register */
+	BX R12                        /* Call the C IRQ handler (ARM/THUMB) */
+
+	MSR CPSR_c, #(MODE_SYS | IRQ | FIQ) /* SYSTEM mode, IRQ/FIQ disabled */
+	MOV R0, SP                          /* Make SP_SYS visible to IRQ mode */
+	ADD SP, SP, #32                     /* Fake unstacking 8 registers from SP_SYS */
+
+	MSR CPSR_c, #(MODE_IRQ | IRQ | FIQ) /* IRQ mode, IRQ/FIQ disabled */
+	MOV SP, R0                          /* Copy SP_SYS to SP_IRQ */
+	LDR R0, [SP, #28]                   /* Load the saved SPSR from the stack */
+	MSR SPSR_cxsf, R0                   /* Copy it into SPSR_IRQ */
+
+	LDMFD SP, {R0-R3, R12, LR}^ /* Unstack all saved USER/SYSTEM registers */
+	NOP                         /* Cant access barked registers immediately */
+	LDR LR, [SP, #24]           /* Load return address from the SYS stack */
+	MOVS PC, LR                 /* Return restoring CPSR from SPSR */
+
+_fiq_handler:
+	BL fiq_handler
+
+setup_vectors:
+	/* Setup vectors */
+	LDR R0, =EXCP_VEC_BASE
+
+	LDR R1, =_reset_handler
+	STR R1, [R0, #EVP_COP_RESET_VECTOR]
+
+	LDR R1, =_undefined_handler
+	STR R1, [R0, #EVP_COP_UNDEF_VECTOR]
+
+	LDR R1, =_reset_handler
+	STR R1, [R0, #EVP_COP_SWI_VECTOR]
+
+	LDR R1, =_prefetch_abort_handler
+	STR R1, [R0, #EVP_COP_PREFETCH_ABORT_VECTOR]
+
+	LDR R1, =_data_abort_handler
+	STR R1, [R0, #EVP_COP_DATA_ABORT_VECTOR]
+
+	LDR R1, =_reset_handler
+	STR R1, [R0, #EVP_COP_RSVD_VECTOR]
+
+	LDR R1, =_irq_handler
+	STR R1, [R0, #EVP_COP_IRQ_VECTOR]
+
+	LDR R1, =_fiq_handler
+	STR R1, [R0, #EVP_COP_FIQ_VECTOR]
+
+	BX LR

bdk/fatfs_cfg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,11 +14,11 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef _CLUSTER_H_
-#define _CLUSTER_H_
+#ifndef _FATFS_CFG_H_
+#define _FATFS_CFG_H_
 
-#include "../utils/types.h"
-
-void cluster_boot_cpu0(u32 entry);
+#ifdef FFCFG_INC
+#include FFCFG_INC
+#endif
 
 #endif

bdk/gfx/di.c

@@ -0,0 +1,446 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "di.h"
+#include <power/max77620.h>
+#include <power/max7762x.h>
+#include <soc/clock.h>
+#include <soc/gpio.h>
+#include <soc/i2c.h>
+#include <soc/pinmux.h>
+#include <soc/pmc.h>
+#include <soc/t210.h>
+#include <utils/util.h>
+
+#include "di.inl"
+
+extern volatile nyx_storage_t *nyx_str;
+
+static u32 _display_id = 0;
+
+void display_end();
+
+static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
+{
+	u32 end = get_tmr_us() + timeout;
+	while (get_tmr_us() < end && DSI(off) & mask)
+		;
+	usleep(5);
+}
+
+static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait)
+{
+	DSI(_DSIREG(DSI_WR_DATA)) = (param << 8) | cmd;
+	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+
+	if (wait)
+		usleep(wait);
+}
+
+void display_init()
+{
+	// Check if display is already initialized.
+	if (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) & 0x18000000)
+		display_end();
+
+	// Power on.
+	max77620_regulator_set_volt_and_flags(REGULATOR_LDO0, 1200000, MAX77620_POWER_MODE_NORMAL); // Configure to 1.2V.
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL);
+
+	// Enable Display Interface specific clocks.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL);
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
+
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP);
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10;    // Set PLLP_OUT and div 6 (68MHz).
+
+	// Disable deep power down.
+	PMC(APBDEV_PMC_IO_DPD_REQ)  = 0x40000000;
+	PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
+
+	// Config LCD and Backlight pins.
+	PINMUX_AUX(PINMUX_AUX_NFC_EN)     &= ~PINMUX_TRISTATE; // PULL_DOWN
+	PINMUX_AUX(PINMUX_AUX_NFC_INT)    &= ~PINMUX_TRISTATE; // PULL_DOWN
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_EN)  &= ~PINMUX_TRISTATE; // PULL_DOWN
+	PINMUX_AUX(PINMUX_AUX_LCD_RST)    &= ~PINMUX_TRISTATE; // PULL_DOWN
+
+	// Set Backlight +-5V pins mode and direction
+	gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO);
+	gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE);
+
+	// Enable Backlight power.
+	gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // Backlight +5V enable.
+	usleep(10000);
+	gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // Backlight -5V enable.
+	usleep(10000);
+
+	// Configure Backlight pins (PWM, EN, RST).
+	gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO);
+	gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
+	gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Enable Backlight EN.
+
+	// Power up supply regulator for display interface.
+	MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0;
+
+	// Set DISP1 clock source and parent clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT.
+	u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 96 MHz.
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
+	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;    // PLLD_SETUP.
+	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2D0AAA; // PLLD_ENABLE_CLK.
+
+	// Setup display communication interfaces.
+	exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94);
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config, 61);
+	usleep(10000);
+
+	// Enable Backlight Reset.
+	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH);
+	usleep(60000);
+
+	// Setups DSI packet configuration and request display id.
+	DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
+	_display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 3, 0);
+	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
+
+	_display_dsi_send_cmd(MIPI_DSI_DCS_READ, MIPI_DCS_GET_DISPLAY_ID, 0);
+	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
+
+	DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
+	_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
+
+	usleep(5000);
+
+	// MIPI_DCS_GET_DISPLAY_ID reply is a long read, size 3 u32.
+	for (u32 i = 0; i < 3; i++)
+		_display_id = DSI(_DSIREG(DSI_RD_DATA)); // Skip ack and msg type info and get the payload (display id).
+
+	// Save raw Display ID to Nyx storage.
+	nyx_str->info.disp_id = _display_id;
+
+	// Decode Display ID.
+	_display_id = ((_display_id >> 8) & 0xFF00) | (_display_id & 0xFF);
+
+	if ((_display_id & 0xFF) == PANEL_JDI_XXX062M)
+		_display_id = PANEL_JDI_XXX062M;
+
+	// Initialize display panel.
+	switch (_display_id)
+	{
+	case PANEL_JDI_XXX062M:
+		exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43);
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
+		break;
+	case PANEL_INL_P062CCA_AZ1:
+	case PANEL_AUO_A062TAN01:
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000);
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x439;          // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9;     // Enable extension cmd. (Pass: FF 83 94).
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x739;          // MIPI_DSI_DCS_LONG_WRITE: 7 bytes.
+		if (_display_id == PANEL_INL_P062CCA_AZ1)
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
+		else
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x143209;       // (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32).
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+		break;
+	case PANEL_INL_2J055IA_27A:
+	case PANEL_AUO_A055TAN01:
+	default: // Allow spare part displays to work.
+		_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 120000);
+		break;
+	}
+
+	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000);
+
+	// Configure PLLD for DISP1.
+	plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 460.8 MHz.
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div;
+	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20;
+	CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN.
+
+	// Finalize DSI configuration.
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 21);
+	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; // PCD1 | div3.
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10);
+	usleep(10000);
+
+	// Calibrate display communication pads.
+	exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 6);
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config, 4);
+	exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 16);
+	usleep(10000);
+
+	// Enable video display controller.
+	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113);
+}
+
+void display_backlight_pwm_init()
+{
+	clock_enable_pwm();
+
+	PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; // Enable PWM and set it to 25KHz PFM.
+
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC) | 1; // PWM clock source.
+	gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
+}
+
+void display_backlight(bool enable)
+{
+	gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO.
+}
+
+void display_backlight_brightness(u32 brightness, u32 step_delay)
+{
+	u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF;
+	if (brightness == old_value)
+		return;
+
+	if (brightness > 255)
+		brightness = 255;
+
+	if (old_value < brightness)
+	{
+		for (u32 i = old_value; i < brightness + 1; i++)
+		{
+			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
+			usleep(step_delay);
+		}
+	}
+	else
+	{
+		for (u32 i = old_value; i > brightness; i--)
+		{
+			PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
+			usleep(step_delay);
+		}
+	}
+	if (!brightness)
+		PWM(PWM_CONTROLLER_PWM_CSR_0) = 0;
+}
+
+void display_end()
+{
+	display_backlight_brightness(0, 1000);
+
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE;
+	DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
+
+	DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet.
+
+	// De-initialize video controller.
+	exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17);
+	exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16);
+	usleep(10000);
+
+	// De-initialize display panel.
+	switch (_display_id)
+	{
+	case PANEL_JDI_XXX062M:
+		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22);
+		break;
+	case PANEL_AUO_A062TAN01:
+		exec_cfg((u32 *)DSI_BASE, _display_deinit_config_auo, 37);
+		break;
+	case PANEL_INL_2J055IA_27A:
+	case PANEL_AUO_A055TAN01:
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x439; // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9; // Enable extension cmd. (Pass: FF 83 94).
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+		// Set Power.
+		DSI(_DSIREG(DSI_WR_DATA)) = 0xB39; // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
+		if (_display_id == PANEL_INL_2J055IA_27A)
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // Set Power control. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40).
+		else
+			DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
+		// Set Power control. (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x71143209;
+		DSI(_DSIREG(DSI_WR_DATA)) = 0x114D31; // Set Power control. (Unknown).
+		DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+		usleep(5000);
+		break;
+	case PANEL_INL_P062CCA_AZ1:
+	default:
+		break;
+	}
+
+	_display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_ENTER_SLEEP_MODE, 50000);
+
+	// Disable display and backlight pins.
+	gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
+	usleep(10000);
+
+	gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable.
+	usleep(10000);
+
+	gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable.
+	usleep(10000);
+
+	// Disable Display Interface specific clocks.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
+
+	// Power down pads.
+	DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
+	DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
+
+	// Switch to automatic function mode.
+	gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
+
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
+	PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC)| 1;
+}
+
+void display_color_screen(u32 color)
+{
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8);
+
+	// Configure display to show single color.
+	DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
+	DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
+	DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
+	DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
+	usleep(35000);
+
+	display_backlight(true);
+}
+
+u32 *display_init_framebuffer_pitch()
+{
+	// Sanitize framebuffer area.
+	memset((u32 *)IPL_FB_ADDRESS, 0, 0x3C0000);
+
+	// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32);
+	usleep(35000);
+
+	return (u32 *)IPL_FB_ADDRESS;
+}
+
+u32 *display_init_framebuffer_pitch_inv()
+{
+	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch_inv, 34);
+
+	usleep(35000);
+
+	return (u32 *)NYX_FB_ADDRESS;
+}
+
+u32 *display_init_framebuffer_block()
+{
+	// This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 34);
+
+	usleep(35000);
+
+	return (u32 *)NYX_FB_ADDRESS;
+}
+
+u32 *display_init_framebuffer_log()
+{
+	// This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
+	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_log, 20);
+
+	return (u32 *)LOG_FB_ADDRESS;
+}
+
+void display_activate_console()
+{
+	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
+	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD.
+	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+
+	for (u32 i = 0xFF80; i < 0x10000; i++)
+	{
+		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+		usleep(1000);
+	}
+
+	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+}
+
+void display_deactivate_console()
+{
+	DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window C.
+
+	for (u32 i = 0xFFFF; i > 0xFF7F; i--)
+	{
+		DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+		DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+		usleep(500);
+	}
+
+	DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0;
+	DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; // Disable window DD.
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ;
+}
+
+void display_init_cursor(void *crs_fb, u32 size)
+{
+	// Setup cursor.
+	DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10);
+	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) =
+		CURSOR_BLEND_R8G8B8A8 | CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF;
+
+	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) |= CURSOR_ENABLE;
+
+	// Arm and activate changes.
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
+}
+
+void display_set_pos_cursor(u32 x, u32 y)
+{
+	DISPLAY_A(_DIREG(DC_DISP_CURSOR_POSITION)) = x | (y << 16);
+
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
+}
+
+void display_deinit_cursor()
+{
+	DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = 0;
+	DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) &= ~CURSOR_ENABLE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ;
+}

bdk/gfx/di.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2018-2019 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,12 +18,27 @@
 #ifndef _DI_H_
 #define _DI_H_
 
-#include "../../common/memory_map.h"
-#include "../utils/types.h"
+#include <memory_map.h>
+#include <utils/types.h>
 
 /*! Display registers. */
 #define _DIREG(reg) ((reg) * 4)
 
+// Display controller scratch registers.
+#define DC_D_WINBUF_DD_SCRATCH_REGISTER_0 0xED
+#define DC_D_WINBUF_DD_SCRATCH_REGISTER_1 0xEE
+#define DC_T_WINBUF_TD_SCRATCH_REGISTER_0 0x16D
+#define DC_T_WINBUF_TD_SCRATCH_REGISTER_1 0x16E
+#define DC_COM_SCRATCH_REGISTER_A 0x325
+#define DC_COM_SCRATCH_REGISTER_B 0x326
+#define DC_A_WINBUF_AD_SCRATCH_REGISTER_0 0xBED
+#define DC_A_WINBUF_AD_SCRATCH_REGISTER_1 0xBEE
+#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0 0xDED
+#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1 0xDEE
+#define DC_C_WINBUF_CD_SCRATCH_REGISTER_0 0xFED
+#define DC_C_WINBUF_CD_SCRATCH_REGISTER_1 0xFEE
+
+// DC_CMD non-shadowed command/sync registers.
 #define DC_CMD_GENERAL_INCR_SYNCPT 0x00
 
 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
@@ -50,6 +65,7 @@
 #define  PM0_ENABLE (1 << 16)
 #define  PM1_ENABLE (1 << 18)
 
+#define DC_CMD_INT_STATUS 0x37
 #define DC_CMD_INT_MASK 0x38
 #define DC_CMD_INT_ENABLE 0x39
 
@@ -62,11 +78,13 @@
 #define  WIN_A_ACT_REQ   (1 <<  1)
 #define  WIN_B_ACT_REQ   (1 <<  2)
 #define  WIN_C_ACT_REQ   (1 <<  3)
+#define  WIN_D_ACT_REQ   (1 <<  4)
 #define  CURSOR_ACT_REQ  (1 <<  7)
 #define  GENERAL_UPDATE  (1 <<  8)
 #define  WIN_A_UPDATE    (1 <<  9)
 #define  WIN_B_UPDATE    (1 << 10)
 #define  WIN_C_UPDATE    (1 << 11)
+#define  WIN_D_UPDATE    (1 << 12)
 #define  CURSOR_UPDATE   (1 << 15)
 #define  NC_HOST_TRIG    (1 << 24)
 
@@ -74,15 +92,38 @@
 #define  WINDOW_A_SELECT (1 << 4)
 #define  WINDOW_B_SELECT (1 << 5)
 #define  WINDOW_C_SELECT (1 << 6)
+#define  WINDOW_D_SELECT (1 << 7)
 
 #define DC_CMD_REG_ACT_CONTROL 0x043
 
+// DC_D_WIN_DD window D instance of DC_WIN
+#define DC_D_WIN_DD_WIN_OPTIONS 0x80
+#define DC_D_WIN_DD_COLOR_DEPTH 0x83
+#define DC_D_WIN_DD_POSITION    0x84
+#define DC_D_WIN_DD_SIZE        0x85
+#define DC_D_WIN_DD_LINE_STRIDE 0x8A
+#define DC_D_WIN_DD_BLEND_LAYER_CONTROL 0x96
+#define DC_D_WIN_DD_BLEND_MATCH_SELECT  0x97
+#define DC_D_WIN_DD_BLEND_ALPHA_1BIT    0x99
+
+// DC_D_WINBUF_DD window D instance of DC_WINBUF
+#define DC_D_WINBUF_DD_START_ADDR    0xC0
+#define DC_D_WINBUF_DD_ADDR_H_OFFSET 0xC6
+#define DC_D_WINBUF_DD_ADDR_V_OFFSET 0xC8
+#define DC_D_WINBUF_DD_START_ADDR_HI 0xCD
+#define DC_D_WINBUF_DD_MEMFETCH_CONTROL 0xEB
+
+// DC_T_WIN_TD macro for using DD defines.
+#define _DC_T(reg) ((reg) + 0x80)
+
+// DC_COM non-shadowed registers.
 #define DC_COM_CRC_CONTROL 0x300
 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
 
 #define DC_COM_DSC_TOP_CTL 0x33E
 
+// DC_DISP shadowed registers.
 #define DC_DISP_DISP_WIN_OPTIONS 0x402
 #define  HDMI_ENABLE     (1 << 30)
 #define  DSI_ENABLE      (1 << 29)
@@ -161,6 +202,32 @@
 #define  DE_CONTROL_EARLY        (3 << 2)
 #define  DE_CONTROL_ACTIVE_BLANK (4 << 2)
 
+// Cursor configuration registers.
+#define DC_DISP_CURSOR_FOREGROUND    0x43C
+#define DC_DISP_CURSOR_BACKGROUND    0x43D
+#define  CURSOR_COLOR(r,g,b) (((r) & 0xFF) | (((g) & 0xFF) << 8) | (((b) & 0xFF) << 16))
+
+#define DC_DISP_CURSOR_START_ADDR    0x43E
+#define  CURSOR_CLIPPING(w) ((w) << 28)
+#define   CURSOR_CLIP_WIN_A 1
+#define   CURSOR_CLIP_WIN_B 2
+#define   CURSOR_CLIP_WIN_C 3
+#define  CURSOR_SIZE_32  (0 << 24)
+#define  CURSOR_SIZE_64  (1 << 24)
+#define  CURSOR_SIZE_128 (2 << 24)
+#define  CURSOR_SIZE_256 (3 << 24)
+#define DC_DISP_CURSOR_POSITION      0x440
+#define DC_DISP_CURSOR_START_ADDR_HI 0x4EC
+#define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1
+#define  CURSOR_BLEND_2BIT     (0 << 24)
+#define  CURSOR_BLEND_R8G8B8A8 (1 << 24)
+#define  CURSOR_BLEND_SRC_FACTOR(n) ((n) << 8)
+#define  CURSOR_BLEND_DST_FACTOR(n) ((n) << 16)
+#define   CURSOR_BLEND_ZRO 0
+#define   CURSOR_BLEND_K1  1
+#define   CURSOR_BLEND_NK1 2
+// End of cursor cfg regs.
+
 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
 #define DC_DISP_SD_BL_PARAMETERS 0x4D7
 #define DC_DISP_SD_BL_CONTROL 0x4DC
@@ -187,6 +254,13 @@
 #define  CSC_ENABLE   (1 << 18)
 #define  WIN_ENABLE   (1 << 30)
 
+#define DC_WIN_BUFFER_CONTROL 0x702
+#define  BUFFER_CONTROL_HOST  0
+#define  BUFFER_CONTROL_VI    1
+#define  BUFFER_CONTROL_EPP   2
+#define  BUFFER_CONTROL_MPEGE 3
+#define  BUFFER_CONTROL_SB2D  4
+
 #define DC_WIN_COLOR_DEPTH 0x703
 #define  WIN_COLOR_DEPTH_P1             0x0
 #define  WIN_COLOR_DEPTH_P2             0x1
@@ -211,8 +285,9 @@
 #define  WIN_COLOR_DEPTH_YCbCr422RA     0x18
 #define  WIN_COLOR_DEPTH_YUV422RA       0x19
 
-#define DC_WIN_BUFFER_CONTROL 0x702
 #define DC_WIN_POSITION 0x704
+#define  H_POSITION(x) (((x) & 0xFfff) <<  0)
+#define  V_POSITION(x) (((x) & 0x1fff) << 16)
 
 #define DC_WIN_SIZE 0x705
 #define  H_SIZE(x) (((x) & 0x1fff) <<  0)
@@ -234,6 +309,42 @@
 #define  UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
 #define DC_WIN_DV_CONTROL 0x70E
 
+#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716
+#define  WIN_K1(x) (((x) & 0xff) << 8)
+#define  WIN_K2(x) (((x) & 0xff) << 16)
+#define  WIN_BLEND_ENABLE (0 << 24)
+#define  WIN_BLEND_BYPASS (1 << 24)
+
+#define DC_WINBUF_BLEND_MATCH_SELECT 0x717
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ZERO             (0 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ONE              (1 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1               (2 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_DST     (3 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (4 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC     (5 << 0)
+
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ZERO             (0 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ONE              (1 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1               (2 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K2               (3 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1_TIMES_DST     (4 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (5 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC (6 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1           (7 << 4)
+
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_ZERO             (0 << 8)
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K1               (1 << 8)
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2               (2 << 8)
+
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO             (0 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ONE              (1 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_NEG_K1_TIMES_SRC (2 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2               (3 << 12)
+
+#define DC_WINBUF_BLEND_ALPHA_1BIT 0x719
+#define  WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xff) << 0)
+#define  WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xff) << 8)
+
 /*! The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
 #define DC_WINBUF_START_ADDR 0x800
 #define DC_WINBUF_ADDR_H_OFFSET 0x806
@@ -336,6 +447,7 @@
 
 #define DSI_PAD_CONTROL_CD 0x4C
 #define DSI_VIDEO_MODE_CONTROL 0x4E
+#define  DSI_CMD_PKT_VID_ENABLE 1
 
 #define DSI_PAD_CONTROL_1 0x4F
 #define DSI_PAD_CONTROL_2 0x50
@@ -349,7 +461,65 @@
 #define DSI_PAD_CONTROL_4 0x52
 #define DSI_INIT_SEQ_DATA_15 0x5F
 
-#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60
+/*! MIPI registers. */
+#define MIPI_CAL_MIPI_CAL_CTRL          (0x00 / 0x4)
+#define MIPI_CAL_CIL_MIPI_CAL_STATUS    (0x08 / 0x4)
+#define MIPI_CAL_CILA_MIPI_CAL_CONFIG   (0x14 / 0x4)
+#define MIPI_CAL_CILB_MIPI_CAL_CONFIG   (0x18 / 0x4)
+#define MIPI_CAL_CILC_MIPI_CAL_CONFIG   (0x1C / 0x4)
+#define MIPI_CAL_CILD_MIPI_CAL_CONFIG   (0x20 / 0x4)
+#define MIPI_CAL_CILE_MIPI_CAL_CONFIG   (0x24 / 0x4)
+#define MIPI_CAL_CILF_MIPI_CAL_CONFIG   (0x28 / 0x4)
+#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG   (0x38 / 0x4)
+#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG   (0x3C / 0x4)
+#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG   (0x40 / 0x4)
+#define MIPI_CAL_DSID_MIPI_CAL_CONFIG   (0x44 / 0x4)
+#define MIPI_CAL_MIPI_BIAS_PAD_CFG0     (0x58 / 0x4)
+#define MIPI_CAL_MIPI_BIAS_PAD_CFG1     (0x5C / 0x4)
+#define MIPI_CAL_MIPI_BIAS_PAD_CFG2     (0x60 / 0x4)
+#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x64 / 0x4)
+#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x68 / 0x4)
+#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x70 / 0x4)
+#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4)
+
+/*! MIPI CMDs. */
+#define MIPI_DSI_DCS_SHORT_WRITE 0x05
+#define MIPI_DSI_DCS_READ 0x06
+#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15
+#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
+#define MIPI_DSI_DCS_LONG_WRITE 0x39
+
+/*! MIPI DCS CMDs. */
+#define MIPI_DCS_GET_DISPLAY_ID   0x04
+#define MIPI_DCS_ENTER_SLEEP_MODE 0x10
+#define MIPI_DCS_EXIT_SLEEP_MODE  0x11
+#define MIPI_DCS_SET_DISPLAY_ON   0x29
+
+/* Switch Panels:
+ *
+ * 6.2 panels":
+ * [10] 81 [26]: JDI LPM062M326A
+ * [10] 96 [09]: JDI LAM062M109A
+ * [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
+ * [20] 95 [0F]: InnoLux P062CCA-AZ2
+ * [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
+ * [30] XX [0F]: AUO A062TAN02 (59.06A33.002) [UNCONFIRMED ID]
+ *
+ * 5.5" panels:
+ * [20] 94 [10]: InnoLux 2J055IA-27A (Rev B1)
+ * [30] XX [10]: AUO A055TAN01 (59.05A30.001) [UNCONFIRMED ID]
+ */
+
+enum
+{
+	PANEL_JDI_XXX062M     = 0x10,
+	PANEL_JDI_LAM062M109A = 0x0910,
+	PANEL_JDI_LPM062M326A = 0x2610,
+	PANEL_INL_P062CCA_AZ1 = 0x0F20,
+	PANEL_AUO_A062TAN01   = 0x0F30,
+	PANEL_INL_2J055IA_27A = 0x1020,
+	PANEL_AUO_A055TAN01   = 0x1030
+};
 
 void display_init();
 void display_backlight_pwm_init();
@@ -363,6 +533,14 @@ void display_backlight(bool enable);
 void display_backlight_brightness(u32 brightness, u32 step_delay);
 
 /*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
-u32 *display_init_framebuffer();
+u32 *display_init_framebuffer_pitch();
+u32 *display_init_framebuffer_pitch_inv();
+u32 *display_init_framebuffer_block();
+u32 *display_init_framebuffer_log();
+void display_activate_console();
+void display_deactivate_console();
+void display_init_cursor(void *crs_fb, u32 size);
+void display_set_pos_cursor(u32 x, u32 y);
+void display_deinit_cursor();
 
 #endif

bdk/gfx/di.inl

@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
-* Copyright (c) 2018 CTCaer
+* Copyright (c) 2018-2019 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -15,16 +15,8 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
-//Clock config.
-static const cfg_op_t _display_config_1[4] = {
-	{0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1
-	{0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE
-	{0x36, 0x20},       //CLK_RST_CONTROLLER_PLLD_MISC1
-	{0x37, 0x2D0AAA}    //CLK_RST_CONTROLLER_PLLD_MISC
-};
-
 //Display A config.
-static const cfg_op_t _display_config_2[94] = {
+static const cfg_op_t _display_dc_setup_win_config[94] = {
 	{DC_CMD_STATE_ACCESS, 0},
 	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
 	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
@@ -128,7 +120,7 @@ static const cfg_op_t _display_config_2[94] = {
 };
 
 //DSI Init config.
-static const cfg_op_t _display_config_3[61] = { 
+static const cfg_op_t _display_dsi_init_config[61] = {
 	{DSI_WR_DATA, 0},
 	{DSI_INT_ENABLE, 0},
 	{DSI_INT_STATUS, 0},
@@ -192,14 +184,14 @@ static const cfg_op_t _display_config_3[61] = {
 	{DSI_INIT_SEQ_CONTROL, 0}
 };
 
-//DSI config (if ver == 0x10).
-static const cfg_op_t _display_config_4[43] = {
-	{DSI_WR_DATA, 0x439},
-	{DSI_WR_DATA, 0x9483FFB9},
+//DSI panel config.
+static const cfg_op_t _display_init_config_jdi[43] = {
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0xBD15},
+	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x1939},
+	{DSI_WR_DATA, 0x1939},     // MIPI_DSI_DCS_LONG_WRITE: 25 bytes.
 	{DSI_WR_DATA, 0xAAAAAAD8},
 	{DSI_WR_DATA, 0xAAAAAAEB},
 	{DSI_WR_DATA, 0xAAEBAAAA},
@@ -208,9 +200,9 @@ static const cfg_op_t _display_config_4[43] = {
 	{DSI_WR_DATA, 0xAAEBAAAA},
 	{DSI_WR_DATA, 0xAA},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x1BD15},
+	{DSI_WR_DATA, 0x01BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x1BD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x2739},
+	{DSI_WR_DATA, 0x2739},     // MIPI_DSI_DCS_LONG_WRITE: 39 bytes.
 	{DSI_WR_DATA, 0xFFFFFFD8},
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFFFF},
@@ -222,25 +214,25 @@ static const cfg_op_t _display_config_4[43] = {
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFF},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x2BD15},
+	{DSI_WR_DATA, 0x02BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x2BD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0xF39},
+	{DSI_WR_DATA, 0xF39},      // MIPI_DSI_DCS_LONG_WRITE: 15 bytes.
 	{DSI_WR_DATA, 0xFFFFFFD8},
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFFFF},
 	{DSI_WR_DATA, 0xFFFFFF},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0xBD15},
+	{DSI_WR_DATA, 0x00BD15},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x0BD.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x6D915},
+	{DSI_WR_DATA, 0x06D915},   // MIPI_DSI_DCS_SHORT_WRITE_PARAM: 0x6D9.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x439},
-	{DSI_WR_DATA, 0xB9},
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST}
 };
 
-//DSI config.
-static const cfg_op_t _display_config_5[21] = {
+//DSI packet config.
+static const cfg_op_t _display_dsi_packet_config[21] = {
 	{DSI_PAD_CONTROL_1, 0},
 	{DSI_PHY_TIMING_0, 0x6070601},
 	{DSI_PHY_TIMING_1, 0x40A0E05},
@@ -264,15 +256,8 @@ static const cfg_op_t _display_config_5[21] = {
 	{DSI_HOST_CONTROL, 0},
 };
 
-//Clock config.
-static const cfg_op_t _display_config_6[3] = {
-	{0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE
-	{0x36, 0x20},       //CLK_RST_CONTROLLER_PLLD_MISC1
-	{0x37, 0x2DFC00}    //CLK_RST_CONTROLLER_PLLD_MISC
-};
-
-//DSI config.
-static const cfg_op_t _display_config_7[10] = {
+//DSI mode config.
+static const cfg_op_t _display_dsi_mode_config[10] = {
 	{DSI_TRIGGER, 0},
 	{DSI_CONTROL, 0},
 	{DSI_SOL_DELAY, 6},
@@ -286,17 +271,17 @@ static const cfg_op_t _display_config_7[10] = {
 };
 
 //MIPI CAL config.
-static const cfg_op_t _display_config_8[6] = {
-	{0x18, 0},          // MIPI_CAL_MIPI_BIAS_PAD_CFG2
-	{0x02, 0xF3F10000}, // MIPI_CAL_CIL_MIPI_CAL_STATUS
-	{0x16, 0},          // MIPI_CAL_MIPI_BIAS_PAD_CFG0
-	{0x18, 0},          // MIPI_CAL_MIPI_BIAS_PAD_CFG2
-	{0x18, 0x10010},    // MIPI_CAL_MIPI_BIAS_PAD_CFG2
-	{0x17, 0x300}       // MIPI_CAL_MIPI_BIAS_PAD_CFG1
+static const cfg_op_t _display_mipi_pad_cal_config[6] = {
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0},
+	{MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000},
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG0,  0},
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0},
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG2,  0x10010},
+	{MIPI_CAL_MIPI_BIAS_PAD_CFG1,  0x300}
 };
 
 //DSI config.
-static const cfg_op_t _display_config_9[4] = {
+static const cfg_op_t _display_dsi_pad_cal_config[4] = {
 	{DSI_PAD_CONTROL_1, 0},
 	{DSI_PAD_CONTROL_2, 0},
 	{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
@@ -304,27 +289,27 @@ static const cfg_op_t _display_config_9[4] = {
 };
 
 //MIPI CAL config.
-static const cfg_op_t _display_config_10[16] = {
-	{0x0E, 0x200200}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG
-	{0x0F, 0x200200}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG
-	{0x19, 0x200002}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2
-	{0x1A, 0x200002}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2
-	{0x05, 0},        // MIPI_CAL_CILA_MIPI_CAL_CONFIG
-	{0x06, 0},        // MIPI_CAL_CILB_MIPI_CAL_CONFIG
-	{0x07, 0},        // MIPI_CAL_CILC_MIPI_CAL_CONFIG
-	{0x08, 0},        // MIPI_CAL_CILD_MIPI_CAL_CONFIG
-	{0x09, 0},        // MIPI_CAL_CILE_MIPI_CAL_CONFIG
-	{0x0A, 0},        // MIPI_CAL_CILF_MIPI_CAL_CONFIG
-	{0x10, 0},        // MIPI_CAL_DSIC_MIPI_CAL_CONFIG
-	{0x11, 0},        // MIPI_CAL_DSID_MIPI_CAL_CONFIG
-	{0x1A, 0},        // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2
-	{0x1C, 0},        // MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2
-	{0x1D, 0},        // MIPI_CAL_DSID_MIPI_CAL_CONFIG_2
-	{0, 0x2A000001}   // MIPI_CAL_DSIA_MIPI_CAL_CONFIG
+static const cfg_op_t _display_mipi_apply_dsi_cal_config[16] = {
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG,   0x200200},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG,   0x200200},
+	{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002},
+	{MIPI_CAL_CILA_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILB_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILC_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILD_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILE_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_CILF_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_DSIC_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_DSID_MIPI_CAL_CONFIG,   0},
+	{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0},
+	{MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0},
+	{MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0},
+	{MIPI_CAL_MIPI_CAL_CTRL,          0x2A000001}
 };
 
 //Display A config.
-static const cfg_op_t _display_config_11[113] = {
+static const cfg_op_t _display_video_disp_controller_enable_config[113] = {
 	{DC_CMD_STATE_ACCESS, 0},
 	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
@@ -449,7 +434,7 @@ static const cfg_op_t _display_config_11[113] = {
 };
 
 ////Display A config.
-static const cfg_op_t _display_config_12[17] = {
+static const cfg_op_t _display_video_disp_controller_disable_config[17] = {
 	{DC_DISP_FRONT_PORCH, 0xA0088},
 	{DC_CMD_INT_MASK, 0},
 	{DC_CMD_STATE_ACCESS, 0},
@@ -470,7 +455,7 @@ static const cfg_op_t _display_config_12[17] = {
 };
 
 //DSI config.
-static const cfg_op_t _display_config_13[16] = {
+static const cfg_op_t _display_dsi_timing_deinit_config[16] = {
 	{DSI_POWER_CONTROL, 0},
 	{DSI_PAD_CONTROL_1, 0},
 	{DSI_PHY_TIMING_0, 0x6070601},
@@ -490,11 +475,11 @@ static const cfg_op_t _display_config_13[16] = {
 };
 
 //DSI config (if ver == 0x10).
-static const cfg_op_t _display_config_14[22] = {
-	{DSI_WR_DATA, 0x439},
-	{DSI_WR_DATA, 0x9483FFB9},
+static const cfg_op_t _display_deinit_config_jdi[22] = {
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x2139},
+	{DSI_WR_DATA, 0x2139},     // MIPI_DSI_DCS_LONG_WRITE: 33 bytes.
 	{DSI_WR_DATA, 0x191919D5},
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19191919},
@@ -505,95 +490,207 @@ static const cfg_op_t _display_config_14[22] = {
 	{DSI_WR_DATA, 0x19191919},
 	{DSI_WR_DATA, 0x19},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0xB39},
-	{DSI_WR_DATA, 0x4F0F41B1},
+	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
+	{DSI_WR_DATA, 0x4F0F41B1}, // Set Power control.
 	{DSI_WR_DATA, 0xF179A433},
-	{DSI_WR_DATA, 0x2D81},
+	{DSI_WR_DATA, 0x002D81},
 	{DSI_TRIGGER, DSI_TRIGGER_HOST},
-	{DSI_WR_DATA, 0x439},
-	{DSI_WR_DATA, 0xB9},
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
 	{DSI_TRIGGER, DSI_TRIGGER_HOST}
 };
 
+static const cfg_op_t _display_deinit_config_auo[37] = {
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x9483FFB9}, // Enable extension cmd. (Pass: FF 83 94).
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
+	{DSI_WR_DATA, 0x191919D5},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2C39},     // MIPI_DSI_DCS_LONG_WRITE: 44 bytes.
+	{DSI_WR_DATA, 0x191919D6},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xB39},      // MIPI_DSI_DCS_LONG_WRITE: 11 bytes.
+	{DSI_WR_DATA, 0x711148B1}, // Set Power control. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40).
+	// Set Power control. (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/32, Enter standby / PON / VCOMG).
+	{DSI_WR_DATA, 0x71143209},
+	{DSI_WR_DATA, 0x114D31},   // Set Power control. (Unknown).
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x439},      // MIPI_DSI_DCS_LONG_WRITE: 4 bytes.
+	{DSI_WR_DATA, 0x000000B9}, // Disable extension cmd.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST}
+};
+
+static const cfg_op_t _display_init_config_invert[3] = {
+	{DSI_WR_DATA, 0x239},
+	{DSI_WR_DATA, 0x02C1}, // INV_EN.
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+};
+
 //Display A config.
 static const cfg_op_t cfg_display_one_color[8] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display.
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} // Continuous display.
 };
 
-//Display A config.
-static const cfg_op_t cfg_display_framebuffer[32] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
+//Display A config linear pitch.
+static const cfg_op_t cfg_display_framebuffer_pitch[32] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
-	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
 	{DC_WIN_WIN_OPTIONS, 0},
 	{DC_WIN_WIN_OPTIONS, 0},
 	{DC_WIN_POSITION, 0}, //(0,0)
 	{DC_WIN_H_INITIAL_DDA, 0},
 	{DC_WIN_V_INITIAL_DDA, 0},
-	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes.
-	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
-	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels.
-	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
-	{DC_WIN_BUFFER_CONTROL, 0},
-	{DC_WINBUF_SURFACE_KIND, 0}, //Regular surface.
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)},
+	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
+	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, PITCH},
+	{DC_WINBUF_START_ADDR, IPL_FB_ADDRESS}, // Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0},
+	{DC_WINBUF_ADDR_V_OFFSET, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_WIN_OPTIONS, WIN_ENABLE}, // Enable window AD.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
+};
+
+//Display A config linear pitch inverse + Win D support.
+static const cfg_op_t cfg_display_framebuffer_pitch_inv[34] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)},
+	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
+	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, PITCH},
 	{DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address.
-	{DC_WINBUF_ADDR_H_OFFSET, 0}, //Linear: 0x383FFC, Block: 0x3813FC
-	{DC_WINBUF_ADDR_V_OFFSET, 1279}, //Linear: 1279, Block: 0
+	{DC_WINBUF_ADDR_H_OFFSET, 0}, // Linear: 0x383FFC, Block: 0x3813FC.
+	{DC_WINBUF_ADDR_V_OFFSET, 1279}, // Linear: 1279, Block: 0.
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
 	{DC_WIN_WIN_OPTIONS, WIN_ENABLE | V_DIRECTION}, // Enable window AD.
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display.
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update.
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
 };
 
-static const cfg_op_t cfg_display_framebuffer2[32] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
+//Display A config block linear.
+static const cfg_op_t cfg_display_framebuffer_block[34] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
-	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8.
 	{DC_WIN_WIN_OPTIONS, 0},
 	{DC_WIN_WIN_OPTIONS, 0},
 	{DC_WIN_POSITION, 0}, //(0,0)
 	{DC_WIN_H_INITIAL_DDA, 0},
 	{DC_WIN_V_INITIAL_DDA, 0},
-	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes.
-	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
-	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels.
-	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
-	{DC_WIN_BUFFER_CONTROL, 0},
-	{DC_WINBUF_SURFACE_KIND, BLOCK_HEIGHT(4) | BLOCK}, //Regular surface.
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)},
+	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
+	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, BLOCK_HEIGHT(4) | BLOCK},
 	{DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address.
-	{DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, //Linear: 0x383FFC, Block: 0x3813FC
-	{DC_WINBUF_ADDR_V_OFFSET, 0}, //Linear: 1279, Block: 0
+	{DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, // Linear: 0x383FFC, Block: 0x3813FC.
+	{DC_WINBUF_ADDR_V_OFFSET, 0}, // Linear: 1279, Block: 0.
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
 	{DC_WIN_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
-	{DC_WIN_WIN_OPTIONS, WIN_ENABLE | SCAN_COLUMN | H_DIRECTION}, //Enable window AD. | SCAN_COLUMN | H_DIRECTION
-	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display.
-	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update.
-	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request.
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
+	{DC_WIN_WIN_OPTIONS, WIN_ENABLE | SCAN_COLUMN | H_DIRECTION}, // Enable window AD. | SCAN_COLUMN | H_DIRECTION.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}
+};
+
+//Display D config.
+static const cfg_op_t cfg_display_framebuffer_log[20] = {
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8},
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(656 * 4)},
+	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x.
+	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(656)},
+	{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(656 * 2) | LINE_STRIDE(656 * 4)}, //656*2x656*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST},
+	{DC_WINBUF_SURFACE_KIND, PITCH},
+	{DC_WINBUF_START_ADDR, LOG_FB_ADDRESS}, // Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0},
+	{DC_WINBUF_ADDR_V_OFFSET, 0},
+	{DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_ENABLE | WIN_K1(200)},
+	{DC_WINBUF_BLEND_MATCH_SELECT, WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 | WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1},
+	{DC_WIN_WIN_OPTIONS, 0}, // Enable window DD.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_D_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_D_ACT_REQ}
 };

bdk/gfx_utils.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 CTCaer
+ * Copyright (c) 2020 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,6 +14,11 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "../utils/types.h"
+#ifndef _GFX_UTILS_H_
+#define _GFX_UTILS_H_
 
-char *dirlist(const char *directory, const char *pattern, bool includeHiddenFiles);
+#ifdef GFX_INC
+#include GFX_INC
+#endif
+
+#endif

bdk/ianos/elfload/elfload.h

@@ -22,10 +22,10 @@
 #include "elfarch.h"
 #include "elf.h"
 
-#include "../../utils/types.h"
+#include <utils/types.h>
 
 #ifdef DEBUG
-#include "../../gfx/gfx.h"
+#include <gfx_utils.h>
 #define EL_DEBUG(format, ...) \
 	gfx_printf(format __VA_OPT__(, ) __VA_ARGS__)
 #else

bdk/ianos/ianos.c

@@ -18,29 +18,27 @@
 #include <string.h>
 
 #include "ianos.h"
-#include "../utils/types.h"
-#include "../libs/elfload/elfload.h"
-#include "../../common/common_module.h"
-#include "../mem/heap.h"
-#include "../gfx/gfx.h"
+#include "elfload/elfload.h"
+#include <module.h>
+#include <mem/heap.h>
+#include <storage/nx_sd.h>
+#include <utils/types.h>
+
+#include <gfx_utils.h>
 
 #define IRAM_LIB_ADDR 0x4002B000
 #define DRAM_LIB_ADDR 0xE0000000
 
 extern heap_t _heap;
 
-extern void *sd_file_read(const char *path, u32 *fsize);
-extern bool sd_mount();
-extern void sd_unmount();
-
 void *elfBuf = NULL;
 void *fileBuf = NULL;
 
 static void _ianos_call_ep(moduleEntrypoint_t entrypoint, void *moduleConfig)
 {
 	bdkParams_t bdkParameters = (bdkParams_t)malloc(sizeof(struct _bdkParams_t));
-	bdkParameters->gfxCon = &gfx_con;
-	bdkParameters->gfxCtx = &gfx_ctxt;
+	bdkParameters->gfxCon = (void *)&gfx_con;
+	bdkParameters->gfxCtx = (void *)&gfx_ctxt;
 	bdkParameters->memcpy = (memcpy_t)&memcpy;
 	bdkParameters->memset = (memset_t)&memset;
 	bdkParameters->sharedHeap = &_heap;
@@ -66,26 +64,20 @@ static bool _ianos_read_cb(el_ctx *ctx, void *dest, size_t numberBytes, size_t o
 }
 
 //TODO: Support shared libraries.
-uintptr_t ianos_loader(bool sdmount, char *path, elfType_t type, void *moduleConfig)
+uintptr_t ianos_loader(char *path, elfType_t type, void *moduleConfig)
 {
+	el_ctx ctx;
 	uintptr_t epaddr = 0;
 
-	if (sdmount)
-	{
-		if (!sd_mount())
-			goto elfLoadFinalOut;
-	}
+	if (!sd_mount())
+		goto elfLoadFinalOut;
 
+	// Read library.
 	fileBuf = sd_file_read(path, NULL);
 
-	if (sdmount)
-		sd_unmount();
-
 	if (!fileBuf)
 		goto elfLoadFinalOut;
 
-
-	el_ctx ctx;
 	ctx.pread = _ianos_read_cb;
 
 	if (el_init(&ctx))
@@ -97,7 +89,6 @@ uintptr_t ianos_loader(bool sdmount, char *path, elfType_t type, void *moduleCon
 	case EXEC_ELF:
 	case AR64_ELF:
 		elfBuf = (void *)DRAM_LIB_ADDR;
-		sd_unmount();
 		break;
 	default:
 		elfBuf = malloc(ctx.memsz); // Aligned to 0x10 by default.
@@ -126,6 +117,5 @@ elfFreeOut:
 	fileBuf = NULL;
 
 elfLoadFinalOut:
-
 	return epaddr;
 }

bdk/ianos/ianos.h

@@ -18,7 +18,7 @@
 #ifndef IANOS_H
 #define IANOS_H
 
-#include "../utils/types.h"
+#include <utils/types.h>
 
 typedef enum
 {
@@ -29,6 +29,6 @@ typedef enum
 	KEEP_IN_RAM = (1 << 31)  // Shared library mask.
 } elfType_t;
 
-uintptr_t ianos_loader(bool sdmount, char *path, elfType_t type, void* config);
+uintptr_t ianos_loader(char *path, elfType_t type, void* config);
 
 #endif

bdk/input/als.c

@@ -17,11 +17,11 @@
  */
 
 #include "als.h"
-#include "../power/max77620.h"
-#include "../soc/clock.h"
-#include "../soc/i2c.h"
-#include "../soc/pinmux.h"
-#include "../utils/util.h"
+#include <power/max77620.h>
+#include <soc/clock.h>
+#include <soc/i2c.h>
+#include <soc/pinmux.h>
+#include <utils/util.h>
 
 #define HOS_GAIN  BH1730_GAIN_64X
 #define HOS_ITIME 38
@@ -102,7 +102,8 @@ u8 als_init(als_table_t *als_val)
 	i2c_init(I2C_2);
 
 	max77620_regulator_set_volt_and_flags(REGULATOR_LDO6, 2900000, MAX77620_POWER_MODE_NORMAL);
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2, 0xD8 | MAX77620_LDO_CFG2_ADE_MASK);
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2,
+		 (MAX77620_POWER_MODE_NORMAL << MAX77620_LDO_POWER_MODE_SHIFT | (3 << 3) | MAX77620_LDO_CFG2_ADE_ENABLE));
 
 	u8 id = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(0x12));
 	i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_SPEC(BH1730_SPECCMD_RESET), 0);

bdk/input/als.h

@@ -19,7 +19,7 @@
 #ifndef __ALS_H_
 #define __ALS_H_
 
-#include "../utils/types.h"
+#include <utils/types.h>
 
 #define BH1730_I2C_ADDR 0x29
 

bdk/input/joycon.c

@@ -0,0 +1,872 @@
+/*
+ * Joy-Con UART driver for Nintendo Switch
+ *
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "joycon.h"
+#include <gfx_utils.h>
+#include <power/max17050.h>
+#include <power/regulator_5v.h>
+#include <soc/bpmp.h>
+#include <soc/clock.h>
+#include <soc/gpio.h>
+#include <soc/pinmux.h>
+#include <soc/uart.h>
+#include <soc/t210.h>
+#include <utils/util.h>
+
+// For disabling driver when logging is enabled.
+#include <libs/lv_conf.h>
+
+#define JC_WIRED_CMD        0x91
+#define JC_WIRED_HID        0x92
+#define JC_WIRED_INIT_REPLY 0x94
+#define JC_INIT_HANDSHAKE   0xA5
+
+#define JC_WIRED_CMD_MAC 0x01
+#define JC_WIRED_CMD_10  0x10
+
+#define JC_HID_OUTPUT_RPT 0x01
+#define JC_HID_RUMBLE_RPT 0x10
+
+#define JC_HID_INPUT_RPT  0x30
+#define JC_HID_SUBMCD_RPT 0x21
+
+#define JC_HID_SUBCMD_HCI_STATE  0x06
+#define  HCI_STATE_SLEEP     0x00
+#define  HCI_STATE_RECONNECT 0x01
+#define  HCI_STATE_PAIR      0x02
+#define  HCI_STATE_HOME      0x04
+#define JC_HID_SUBCMD_SPI_READ   0x10
+#define  SPI_READ_OFFSET     0x20
+#define JC_HID_SUBCMD_RUMBLE_CTL 0x48
+#define JC_HID_SUBCMD_SND_RUMBLE 0xFF
+
+#define JC_BTN_MASK_L 0xFF2900 // 0xFFE900: with charge status.
+#define JC_BTN_MASK_R 0x76FF
+
+#define JC_ID_L 1
+#define JC_ID_R 2
+
+enum
+{
+	JC_BATT_EMTPY = 0,
+	JC_BATT_CRIT  = 2,
+	JC_BATT_LOW   = 4,
+	JC_BATT_MID   = 6,
+	JC_BATT_FULL  = 8
+};
+
+static const u8 init_jc[] = {
+	0xA1, 0xA2, 0xA3, 0xA4
+};
+
+static const u8 init_handshake[] = {
+	0x19, 0x01, 0x03, 0x07, 0x00,      // Uart header.
+	JC_INIT_HANDSHAKE, 0x02,           // Wired cmd and wired subcmd.
+	0x01, 0x7E, 0x00, 0x00, 0x00       // Wired subcmd data.
+};
+
+static const u8 init_get_info[]  = {
+	0x19, 0x01, 0x03, 0x07, 0x00,      // Uart header.
+	JC_WIRED_CMD, JC_WIRED_CMD_MAC,    // Wired cmd and subcmd.
+	0x00, 0x00, 0x00, 0x00, 0x24       // Wired subcmd data.
+};
+
+static const u8 init_finilize[]  = {
+	0x19, 0x01, 0x03, 0x07, 0x00,      // Uart header.
+	JC_WIRED_CMD, JC_WIRED_CMD_10,     // Wired cmd and subcmd.
+	0x00, 0x00, 0x00, 0x00, 0x3D       // Wired subcmd data.
+};
+
+static const u8 nx_pad_status[]  = {
+	0x19, 0x01, 0x03, 0x08, 0x00,      // Uart header.
+	JC_WIRED_HID, 0x00,                // Wired cmd and hid cmd.
+	0x01, 0x00, 0x00, 0x69, 0x2D, 0x1F // hid data.
+};
+
+typedef struct _jc_uart_hdr_t
+{
+	u8 magic[3];
+	u8 total_size_lsb;
+	u8 total_size_msb;
+} jc_uart_hdr_t;
+
+typedef struct _jc_wired_hdr_t
+{
+	jc_uart_hdr_t uart_hdr;
+	u8 cmd;
+	u8 data[5];
+	u8 crc;
+	u8 payload[];
+} jc_wired_hdr_t;
+
+typedef struct _jc_hid_out_rpt_t
+{
+	u8 cmd;
+	u8 pkt_id;
+	u8 rumble[8];
+	u8 subcmd;
+	u8 subcmd_data[];
+} jc_hid_out_rpt_t;
+
+typedef struct _jc_hid_out_spi_read_t
+{
+	u32 addr;
+	u8  size;
+} jc_hid_out_spi_read_t;
+
+typedef struct _jc_hid_in_rpt_t
+{
+	u8 cmd;
+	u8 pkt_id;
+	u8 conn_info:4;
+	u8 batt_info:4;
+	u8 btn_right;
+	u8 btn_shared;
+	u8 btn_left;
+	u8 stick_h_left;
+	u8 stick_m_left;
+	u8 stick_v_left;
+	u8 stick_h_right;
+	u8 stick_m_right;
+	u8 stick_v_right;
+	u8 vib_decider;
+	u8 submcd_ack;
+	u8 subcmd;
+	u8 subcmd_data[];
+} jc_hid_in_rpt_t;
+
+typedef struct _jc_hid_in_spi_read_t
+{
+	u32 addr;
+	u8  size;
+	u8  data[];
+} jc_hid_in_spi_read_t;
+
+typedef struct _jc_hid_in_pair_data_t
+{
+	u8  magic;
+	u8  size;
+	u16 checksum;
+	u8  mac[6];
+	u8  ltk[16];
+	u8  pad0[10];
+	u8  bt_caps; // bit3: Secure conn supported host, bit5: Paired to TBFC supported host, bit6: iTBFC page supported
+	u8  pad1;
+} jc_hid_in_pair_data_t;
+
+typedef struct _joycon_ctxt_t
+{
+	u8 buf[0x100]; //FIXME: If heap is used, dumping breaks.
+	u8 uart;
+	u8 type;
+	u8 mac[6];
+	u32 hw_init_done;
+	u32 last_received_time;
+	u32 last_status_req_time;
+	u8 rumble_sent;
+	u8 connected;
+} joycon_ctxt_t;
+
+static joycon_ctxt_t jc_l;
+static joycon_ctxt_t jc_r;
+
+static bool jc_init_done = false;
+static u32 hid_pkt_inc = 0;
+
+static jc_gamepad_rpt_t jc_gamepad;
+
+void jc_power_supply(u8 uart, bool enable);
+
+void joycon_send_raw(u8 uart_port, const u8 *buf, u16 size)
+{
+	uart_send(uart_port, buf, size);
+	uart_wait_idle(uart_port, UART_TX_IDLE);
+}
+
+static u16 jc_packet_add_uart_hdr(jc_wired_hdr_t *out, u8 wired_cmd, u8 *data, u16 size)
+{
+	out->uart_hdr.magic[0] = 0x19;
+	out->uart_hdr.magic[1] = 0x01;
+	out->uart_hdr.magic[2] = 0x3;
+
+	out->uart_hdr.total_size_lsb = sizeof(jc_wired_hdr_t) - sizeof(jc_uart_hdr_t);
+	out->uart_hdr.total_size_msb = 0;
+	out->cmd = wired_cmd;
+
+	if (data)
+		memcpy(out->data, data, size);
+
+	out->crc = 0; // wired crc8ccit can be skipped.
+
+	return sizeof(jc_wired_hdr_t);
+}
+
+static u16 jc_hid_output_rpt_craft(jc_wired_hdr_t *rpt, u8 *payload, u16 size)
+{
+	u16 pkt_size = jc_packet_add_uart_hdr(rpt, JC_WIRED_HID, NULL, 0);
+	pkt_size += size;
+
+	rpt->uart_hdr.total_size_lsb += size;
+	rpt->data[0] = size >> 8;
+	rpt->data[1] = size & 0xFF;
+
+	if (payload)
+		memcpy(rpt->payload, payload, size);
+
+	return pkt_size;
+}
+
+void jc_send_hid_output_rpt(u8 uart, u8 *payload, u16 size)
+{
+	u8 rpt[0x50];
+	memset(rpt, 0, sizeof(rpt));
+
+	u32 rpt_size = jc_hid_output_rpt_craft((jc_wired_hdr_t *)rpt, payload, size);
+
+	joycon_send_raw(uart, rpt, rpt_size);
+}
+
+static u8 jc_hid_pkt_id_incr()
+{
+	u8 curr_id = hid_pkt_inc;
+	hid_pkt_inc++;
+
+	return (curr_id & 0xF);
+}
+
+void jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size)
+{
+	u8 temp[0x30];
+	u8 rumble_neutral[8] = {0x00, 0x01, 0x40, 0x40, 0x00, 0x01, 0x40, 0x40};
+	u8 rumble_init[8]    = {0xc2, 0xc8, 0x03, 0x72, 0xc2, 0xc8, 0x03, 0x72};
+
+	memset(temp, 0, sizeof(temp));
+
+	jc_hid_out_rpt_t *hid_pkt = (jc_hid_out_rpt_t *)temp;
+
+	memcpy(hid_pkt->rumble, rumble_neutral, sizeof(rumble_neutral));
+
+	if (subcmd == JC_HID_SUBCMD_SND_RUMBLE)
+	{
+		bool send_r_rumble = jc_r.connected && !jc_r.rumble_sent;
+		bool send_l_rumble = jc_l.connected && !jc_l.rumble_sent;
+
+		// Enable rumble.
+		hid_pkt->cmd = JC_HID_OUTPUT_RPT;
+		hid_pkt->pkt_id = jc_hid_pkt_id_incr();
+		hid_pkt->subcmd = JC_HID_SUBCMD_RUMBLE_CTL;
+		hid_pkt->subcmd_data[0] = 1;
+		if (send_r_rumble)
+			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10);
+		if (send_l_rumble)
+			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10);
+
+		// Send rumble.
+		hid_pkt->cmd = JC_HID_RUMBLE_RPT;
+		hid_pkt->pkt_id = jc_hid_pkt_id_incr();
+		memcpy(hid_pkt->rumble, rumble_init, sizeof(rumble_init));
+		if (send_r_rumble)
+			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 10);
+		if (send_l_rumble)
+			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 10);
+
+		msleep(15);
+
+		// Disable rumble.
+		hid_pkt->cmd = JC_HID_OUTPUT_RPT;
+		hid_pkt->pkt_id = jc_hid_pkt_id_incr();
+		hid_pkt->subcmd = JC_HID_SUBCMD_RUMBLE_CTL;
+		hid_pkt->subcmd_data[0] = 0;
+		memcpy(hid_pkt->rumble, rumble_neutral, sizeof(rumble_neutral));
+		if (send_r_rumble)
+			jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10);
+		if (send_l_rumble)
+			jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10);
+	}
+	else
+	{
+		hid_pkt->cmd = JC_HID_OUTPUT_RPT;
+		hid_pkt->pkt_id = jc_hid_pkt_id_incr();
+		hid_pkt->subcmd = subcmd;
+		if (data)
+			memcpy(hid_pkt->subcmd_data, data, size);
+
+		u8 pkt_size = sizeof(jc_hid_out_rpt_t) + size;
+
+		jc_send_hid_output_rpt(uart, (u8 *)hid_pkt, pkt_size);
+	}
+}
+
+static void jc_charging_decider(u8 batt, u8 uart)
+{
+	u32 system_batt_enough = max17050_get_cached_batt_volt() > 4000;
+
+	// Power supply control based on battery levels and charging.
+	if ((batt >> 1 << 1) < JC_BATT_LOW) // Level without checking charging.
+		jc_power_supply(uart, true);
+	else if (batt > (system_batt_enough ? JC_BATT_FULL : JC_BATT_MID)) // Addresses the charging bit.
+		jc_power_supply(uart, false);
+}
+
+static void jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size)
+{
+	u32 btn_tmp;
+	jc_hid_in_rpt_t *hid_pkt = (jc_hid_in_rpt_t *)packet;
+
+	switch (hid_pkt->cmd)
+	{
+	case JC_HID_INPUT_RPT:
+		btn_tmp = hid_pkt->btn_right | hid_pkt->btn_shared << 8 | hid_pkt->btn_left << 16;
+
+		if (jc->type & JC_ID_L)
+		{
+			jc_gamepad.buttons &= ~JC_BTN_MASK_L;
+			jc_gamepad.buttons |= (btn_tmp & JC_BTN_MASK_L);
+
+			jc_gamepad.lstick_x = hid_pkt->stick_h_left | ((hid_pkt->stick_m_left & 0xF) << 8);
+			jc_gamepad.lstick_y = (hid_pkt->stick_m_left >> 4) | (hid_pkt->stick_v_left << 4);
+
+			jc_gamepad.batt_info_l = hid_pkt->batt_info;
+		}
+		else if (jc->type & JC_ID_R)
+		{
+			jc_gamepad.buttons &= ~JC_BTN_MASK_R;
+			jc_gamepad.buttons |= (btn_tmp & JC_BTN_MASK_R);
+
+			jc_gamepad.rstick_x = hid_pkt->stick_h_right | ((hid_pkt->stick_m_right & 0xF) << 8);
+			jc_gamepad.rstick_y = (hid_pkt->stick_m_right >> 4) | (hid_pkt->stick_v_right << 4);
+
+			jc_gamepad.batt_info_r = hid_pkt->batt_info;
+		}
+
+		jc_gamepad.conn_l = jc_l.connected;
+		jc_gamepad.conn_r = jc_r.connected;
+
+		jc_charging_decider(hid_pkt->batt_info, jc->uart);
+		break;
+	case JC_HID_SUBMCD_RPT:
+		if (hid_pkt->subcmd == JC_HID_SUBCMD_SPI_READ)
+		{
+			jc_bt_conn_t *bt_conn;
+
+			if (jc->type & JC_ID_L)
+				bt_conn = &jc_gamepad.bt_conn_l;
+			else
+				bt_conn = &jc_gamepad.bt_conn_r;
+
+			jc_hid_in_spi_read_t  *spi_info = (jc_hid_in_spi_read_t *)hid_pkt->subcmd_data;
+			jc_hid_in_pair_data_t *pair_data = (jc_hid_in_pair_data_t *)spi_info->data;
+
+			// Check if we reply is pairing info.
+			if (spi_info->size == 0x1A && pair_data->magic == 0x95 && pair_data->size == 0x22)
+			{
+				bt_conn->type = jc->type;
+
+				memcpy(bt_conn->mac, jc->mac, 6);
+				memcpy(bt_conn->host_mac, pair_data->mac, 6);
+				for (u32 i = 16; i > 0; i--)
+					bt_conn->ltk[16 - i] = pair_data->ltk[i - 1];
+			}
+		}
+		break;
+	default:
+		break;
+	}
+	jc->last_received_time = get_tmr_ms();
+}
+
+static void jc_parse_wired_init(joycon_ctxt_t *jc, const u8* data, u32 size)
+{
+	switch (data[0])
+	{
+	case JC_WIRED_CMD_MAC:
+		for (int i = 12; i > 6; i--)
+			jc->mac[12 - i] = data[i];
+		jc->type = data[6];
+		jc->connected = true;
+	default:
+		break;
+	}
+}
+
+static void jc_uart_pkt_parse(joycon_ctxt_t *jc, const u8* packet, size_t size)
+{
+	jc_wired_hdr_t *pkt = (jc_wired_hdr_t *)packet;
+	switch (pkt->cmd)
+	{
+	case JC_WIRED_HID:
+		jc_parse_wired_hid(jc, pkt->payload, (pkt->data[0] << 8) | pkt->data[1]);
+		break;
+	case JC_WIRED_INIT_REPLY:
+		jc_parse_wired_init(jc, pkt->data, size - sizeof(jc_uart_hdr_t) - 1);
+		break;
+	default:
+		break;
+	}
+}
+
+static void jc_rcv_pkt(joycon_ctxt_t *jc)
+{
+	if (gpio_read(GPIO_PORT_E, GPIO_PIN_6) && jc->uart == UART_C)
+		return;
+	else if (gpio_read(GPIO_PORT_H, GPIO_PIN_6) && jc->uart == UART_B)
+		return;
+
+	// Check if device stopped sending data.
+	u32 uart_irq = uart_get_IIR(jc->uart);
+	if ((uart_irq & 0x8) != 0x8)
+		return;
+
+	u32 len = uart_recv(jc->uart, (u8 *)jc->buf, 0x100);
+
+	// Check valid size and uart reply magic.
+	if (len > 7 && !memcmp(jc->buf, "\x19\x81\x03", 3))
+	{
+		jc_wired_hdr_t *pkt = (jc_wired_hdr_t *)(jc->buf);
+
+		jc_uart_pkt_parse(jc, jc->buf, pkt->uart_hdr.total_size_lsb + sizeof(jc_uart_hdr_t));
+	}
+}
+
+static bool jc_send_init_rumble(joycon_ctxt_t *jc)
+{
+	// Send init rumble or request nx pad status report.
+	if ((jc_r.connected && !jc_r.rumble_sent) || (jc_l.connected && !jc_l.rumble_sent))
+	{
+		gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
+		gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
+
+		jc_send_hid_cmd(jc->uart, JC_HID_SUBCMD_SND_RUMBLE, NULL, 0);
+
+		if (jc_l.connected)
+			jc_l.rumble_sent = true;
+		if (jc_r.connected)
+			jc_r.rumble_sent = true;
+
+		if (jc->uart != UART_B)
+			gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
+		else
+			gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
+
+		return 1;
+	}
+
+	return 0;
+}
+
+static void jc_req_nx_pad_status(joycon_ctxt_t *jc)
+{
+	bool sent_rumble = jc_send_init_rumble(jc);
+
+	if (sent_rumble)
+		return;
+
+	if (jc->last_status_req_time > get_tmr_ms() || !jc->connected)
+		return;
+
+	// Turn off Joy-Con detect.
+	if (jc->uart == UART_B)
+		gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
+	else
+		gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
+
+	joycon_send_raw(jc->uart, nx_pad_status, sizeof(nx_pad_status));
+
+	// Turn Joy-Con detect on.
+	if (jc->uart == UART_B)
+		gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
+	else
+		gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
+
+	jc->last_status_req_time = get_tmr_ms() + 15;
+}
+
+static bool _jc_validate_pairing_info(u8 *buf, bool *is_hos)
+{
+	u8 crc = 0;
+	for (u32 i = 0; i < 0x22; i++)
+		crc += buf[4 + i];
+
+	crc += 0x68; // Host is Switch.
+
+	if ((crc ^ 0x55) == buf[2])
+		*is_hos = true;
+
+	crc -= 0x68;
+	crc += 0x08; // Host is PC.
+
+	if (*is_hos || (crc ^ 0x55) == buf[2])
+		return true;
+
+	return false;
+}
+
+jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos)
+{
+	u8 retries;
+	jc_bt_conn_t *bt_conn;
+
+	bt_conn = &jc_gamepad.bt_conn_l;
+	memset(bt_conn->host_mac, 0, 6);
+	memset(bt_conn->ltk, 0, 16);
+
+	bt_conn = &jc_gamepad.bt_conn_r;
+	memset(bt_conn->host_mac, 0, 6);
+	memset(bt_conn->ltk, 0, 16);
+
+	while (jc_l.last_status_req_time > get_tmr_ms())
+	{
+		jc_rcv_pkt(&jc_r);
+		jc_rcv_pkt(&jc_l);
+	}
+
+	jc_hid_in_spi_read_t subcmd_data_l;
+	subcmd_data_l.addr = 0x2000;
+	subcmd_data_l.size = 0x1A;
+
+	jc_hid_in_spi_read_t subcmd_data_r;
+	subcmd_data_r.addr = 0x2000;
+	subcmd_data_r.size = 0x1A;
+
+	// Turn off Joy-Con detect.
+	gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
+	gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
+
+	bool jc_r_found = jc_r.connected ? false : true;
+	bool jc_l_found = jc_l.connected ? false : true;
+
+	u32 total_retries = 10;
+retry:
+	retries = 10;
+	while (retries)
+	{
+		u32 time_now = get_tmr_ms();
+		if ((!jc_l_found && jc_l.last_status_req_time < time_now) || (!jc_r_found && jc_r.last_status_req_time < time_now))
+		{
+			if (!jc_l_found)
+			{
+				jc_send_hid_cmd(jc_l.uart, JC_HID_SUBCMD_SPI_READ, (u8 *)&subcmd_data_l, 5);
+				jc_l.last_status_req_time = get_tmr_ms() + 15;
+			}
+
+			if (!jc_r_found)
+			{
+				jc_send_hid_cmd(jc_r.uart, JC_HID_SUBCMD_SPI_READ, (u8 *)&subcmd_data_r, 5);
+				jc_r.last_status_req_time = get_tmr_ms() + 15;
+			}
+
+			retries--;
+		}
+
+		if (!jc_l_found)
+		{
+			memset(jc_l.buf, 0, 0x100);
+			jc_rcv_pkt(&jc_l);
+
+			bool is_hos = false;
+			if (_jc_validate_pairing_info(&jc_l.buf[SPI_READ_OFFSET], &is_hos))
+			{
+				bool is_active = jc_l.buf[SPI_READ_OFFSET] == 0x95;
+
+				if (!is_active)
+					subcmd_data_l.addr += 0x26; // Get next slot.
+				else
+					jc_l_found = true; // Entry is active.
+
+				if (jc_l_found && is_hos)
+					*is_l_hos = true;
+			}
+		}
+
+		if (!jc_r_found)
+		{
+			memset(jc_r.buf, 0, 0x100);
+			jc_rcv_pkt(&jc_r);
+
+			bool is_hos = false;
+			if (_jc_validate_pairing_info(&jc_r.buf[SPI_READ_OFFSET], &is_hos))
+			{
+				bool is_active = jc_r.buf[SPI_READ_OFFSET] == 0x95;
+
+				if (!is_active)
+					subcmd_data_r.addr += 0x26; // Get next slot.
+				else
+					jc_r_found = true; // Entry is active.
+
+				if (jc_r_found && is_hos)
+					*is_r_hos = true;
+			}
+		}
+
+		if (jc_l_found && jc_r_found)
+			break;
+	}
+
+	if (!jc_l_found || !jc_r_found)
+	{
+		if (total_retries)
+		{
+			total_retries--;
+			goto retry;
+		}
+
+		if (!jc_l_found)
+		{
+			bt_conn = &jc_gamepad.bt_conn_l;
+			memset(bt_conn->host_mac, 0, 6);
+			memset(bt_conn->ltk, 0, 16);
+		}
+
+		if (!jc_r_found)
+		{
+			bt_conn = &jc_gamepad.bt_conn_r;
+			memset(bt_conn->host_mac, 0, 6);
+			memset(bt_conn->ltk, 0, 16);
+		}
+	}
+
+	// Turn Joy-Con detect on.
+	gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
+	gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
+
+	return &jc_gamepad;
+}
+
+void jc_deinit()
+{
+	gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
+	gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
+
+	u8 data = HCI_STATE_SLEEP;
+
+	if (jc_r.connected)
+	{
+		jc_send_hid_cmd(UART_B, JC_HID_SUBCMD_HCI_STATE, &data, 1);
+		jc_rcv_pkt(&jc_r);
+	}
+	if (jc_l.connected)
+	{
+		jc_send_hid_cmd(UART_C, JC_HID_SUBCMD_HCI_STATE, &data, 1);
+		jc_rcv_pkt(&jc_l);
+	}
+
+	jc_power_supply(UART_B, false);
+	jc_power_supply(UART_C, false);
+}
+
+static void jc_init_conn(joycon_ctxt_t *jc)
+{
+	if (((u32)get_tmr_ms() - jc->last_received_time) > 1000)
+	{
+		jc_power_supply(jc->uart, true);
+
+		// Turn off Joy-Con detect.
+		if (jc->uart == UART_B)
+		{
+			jc_gamepad.buttons &= ~JC_BTN_MASK_R;
+			jc_gamepad.conn_r = false;
+			gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
+		}
+		else
+		{
+			jc_gamepad.buttons &= ~JC_BTN_MASK_L;
+			jc_gamepad.conn_l = false;
+			gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
+		}
+
+		uart_init(jc->uart, 1000000);
+		uart_invert(jc->uart, true, UART_INVERT_TXD);
+		uart_set_IIR(jc->uart);
+
+		joycon_send_raw(jc->uart, init_jc, 4);
+		joycon_send_raw(jc->uart, init_handshake, sizeof(init_handshake));
+
+		msleep(5);
+		jc_rcv_pkt(jc);
+
+		joycon_send_raw(jc->uart, init_get_info, sizeof(init_get_info));
+		msleep(5);
+		jc_rcv_pkt(jc);
+
+		joycon_send_raw(jc->uart, init_finilize, sizeof(init_finilize));
+		msleep(5);
+		jc_rcv_pkt(jc);
+
+		// Turn Joy-Con detect on.
+		if (jc->uart == UART_B)
+			gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
+		else
+			gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
+
+		jc->last_received_time = get_tmr_ms();
+
+		if (jc->connected)
+			jc_power_supply(jc->uart, false);
+	}
+}
+
+static void jc_conn_check()
+{
+	// Check if a Joy-Con was disconnected.
+	if (gpio_read(GPIO_PORT_E, GPIO_PIN_6))
+	{
+		jc_power_supply(UART_C, false);
+
+		hid_pkt_inc = 0;
+
+		jc_l.connected = false;
+		jc_l.rumble_sent = false;
+
+		jc_gamepad.buttons &= ~JC_BTN_MASK_L;
+		jc_gamepad.conn_l = false;
+
+		jc_gamepad.batt_info_l = 0;
+		jc_gamepad.bt_conn_l.type = 0;
+	}
+
+	if (gpio_read(GPIO_PORT_H, GPIO_PIN_6))
+	{
+		jc_power_supply(UART_B, false);
+
+		hid_pkt_inc = 0;
+
+		jc_r.connected = false;
+		jc_r.rumble_sent = false;
+
+		jc_gamepad.buttons &= ~JC_BTN_MASK_R;
+		jc_gamepad.conn_r = false;
+
+		jc_gamepad.batt_info_r = 0;
+		jc_gamepad.bt_conn_r.type = 0;
+	}
+}
+
+void jc_power_supply(u8 uart, bool enable)
+{
+	if (enable)
+	{
+		if (regulator_get_5v_dev_enabled(1 << uart))
+			return;
+
+		regulator_enable_5v(1 << uart);
+
+		if (jc_init_done)
+		{
+			if (uart == UART_C)
+				gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_HIGH);
+			else
+				gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_HIGH);
+			return;
+		}
+
+		if (uart == UART_C)
+		{
+			// Joy-Con(L) Charge Detect.
+			PINMUX_AUX(PINMUX_AUX_SPDIF_IN) = PINMUX_PULL_DOWN | 1;
+			gpio_config(GPIO_PORT_CC, GPIO_PIN_3, GPIO_MODE_GPIO);
+			gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_3, GPIO_OUTPUT_ENABLE);
+			gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_HIGH);
+		}
+		else
+		{
+			// Joy-Con(R) Charge Detect.
+			PINMUX_AUX(PINMUX_AUX_GPIO_PK3) = PINMUX_DRIVE_4X | PINMUX_PULL_DOWN | 2;
+			gpio_config(GPIO_PORT_K, GPIO_PIN_3, GPIO_MODE_GPIO);
+			gpio_output_enable(GPIO_PORT_K, GPIO_PIN_3, GPIO_OUTPUT_ENABLE);
+			gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_HIGH);
+		}
+	}
+	else
+	{
+		if (!regulator_get_5v_dev_enabled(1 << uart))
+			return;
+
+		regulator_disable_5v(1 << uart);
+
+		if (uart == UART_C)
+			gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_LOW);
+		else
+			gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_LOW);
+	}
+}
+
+void jc_init_hw()
+{
+	jc_l.uart = UART_C;
+	jc_r.uart = UART_B;
+
+#if (LV_LOG_PRINTF != 1)
+	jc_power_supply(UART_C, true);
+	jc_power_supply(UART_B, true);
+
+	// Joy-Con (R) IsAttached.
+	PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
+	gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
+
+	// Joy-Con (L) IsAttached.
+	PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
+	gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
+
+	// Configure pinmuxing for UART B and C.
+	pinmux_config_uart(UART_B);
+	pinmux_config_uart(UART_C);
+
+	// Ease the stress to APB.
+	bpmp_clk_rate_set(BPMP_CLK_NORMAL);
+
+	// Enable UART B and C clocks.
+	clock_enable_uart(UART_B);
+	clock_enable_uart(UART_C);
+
+	// Restore OC.
+	bpmp_clk_rate_set(BPMP_CLK_DEFAULT_BOOST);
+
+	// Turn Joy-Con detect on.
+	gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
+	gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
+
+	jc_init_done = true;
+#endif
+}
+
+jc_gamepad_rpt_t *joycon_poll()
+{
+	if (!jc_init_done)
+		return NULL;
+
+	if (!gpio_read(GPIO_PORT_H, GPIO_PIN_6))
+		jc_init_conn(&jc_r);
+	if (!gpio_read(GPIO_PORT_E, GPIO_PIN_6))
+		jc_init_conn(&jc_l);
+
+	if (!gpio_read(GPIO_PORT_H, GPIO_PIN_6))
+		jc_req_nx_pad_status(&jc_r);
+	if (!gpio_read(GPIO_PORT_E, GPIO_PIN_6))
+		jc_req_nx_pad_status(&jc_l);
+
+	if (!gpio_read(GPIO_PORT_H, GPIO_PIN_6))
+		jc_rcv_pkt(&jc_r);
+	if (!gpio_read(GPIO_PORT_E, GPIO_PIN_6))
+		jc_rcv_pkt(&jc_l);
+
+	jc_conn_check();
+
+	return &jc_gamepad;
+}

bdk/input/joycon.h

@@ -0,0 +1,98 @@
+/*
+ * Ambient light sensor driver for Nintendo Switch's Rohm BH1730
+ *
+ * Copyright (c) 2018 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __JOYCON_H_
+#define __JOYCON_H_
+
+#include <utils/types.h>
+
+#define JC_BTNS_DIRECTION_PAD 0xF0000
+#define JC_BTNS_PREV_NEXT     0x800080
+#define JC_BTNS_ENTER         0x400008
+#define JC_BTNS_ESC           0x4
+
+#define JC_BTNS_ALL (JC_BTNS_PREV_NEXT | JC_BTNS_ENTER | JC_BTNS_DIRECTION_PAD | JC_BTNS_ESC)
+
+typedef struct _jc_bt_conn_t
+{
+	u8 type;
+	u8 mac[6];
+	u8 host_mac[6];
+	u8 ltk[16];
+} jc_bt_conn_t;
+
+typedef struct _jc_gamepad_rpt_t
+{
+	union
+	{
+		struct
+		{
+			// Joy-Con (R).
+			u32 y:1;
+			u32 x:1;
+			u32 b:1;
+			u32 a:1;
+			u32 sr_r:1;
+			u32 sl_r:1;
+			u32 r:1;
+			u32 zr:1;
+
+			// Shared
+			u32 minus:1;
+			u32 plus:1;
+			u32 r3:1;
+			u32 l3:1;
+			u32 home:1;
+			u32 cap:1;
+			u32 pad:1;
+			u32 wired:1;
+
+			// Joy-Con (L).
+			u32 down:1;
+			u32 up:1;
+			u32 right:1;
+			u32 left:1;
+			u32 sr_l:1;
+			u32 sl_l:1;
+			u32 l:1;
+			u32 zl:1;
+		};
+		u32 buttons;
+	};
+
+	u16 lstick_x;
+	u16 lstick_y;
+	u16 rstick_x;
+	u16 rstick_y;
+	bool center_stick_l;
+	bool center_stick_r;
+	bool conn_l;
+	bool conn_r;
+	u8 batt_info_l;
+	u8 batt_info_r;
+	jc_bt_conn_t bt_conn_l;
+	jc_bt_conn_t bt_conn_r;
+} jc_gamepad_rpt_t;
+
+void jc_power_supply(u8 uart, bool enable);
+void jc_init_hw();
+void jc_deinit();
+jc_gamepad_rpt_t *joycon_poll();
+jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos);
+
+#endif

bdk/input/touch.c

@@ -19,19 +19,19 @@
 
 #include <string.h>
 
-#include "../soc/clock.h"
-#include "../soc/i2c.h"
-#include "../soc/pinmux.h"
-#include "../power/max7762x.h"
-#include "../power/max77620.h"
-#include "../soc/gpio.h"
-#include "../soc/t210.h"
-#include "../utils/btn.h"
-#include "../utils/util.h"
+#include <soc/clock.h>
+#include <soc/i2c.h>
+#include <soc/pinmux.h>
+#include <power/max7762x.h>
+#include <power/max77620.h>
+#include <soc/gpio.h>
+#include <soc/t210.h>
+#include <utils/btn.h>
+#include <utils/util.h>
 #include "touch.h"
 
 
-#include "../gfx/gfx.h"
+#include <gfx_utils.h>
 #define DPRINTF(...) gfx_printf(__VA_ARGS__)
 
 static int touch_command(u8 cmd, u8 *buf, u8 size)
@@ -276,6 +276,29 @@ int touch_panel_ito_test(u8 *err)
 	return res;
 }
 
+int touch_get_fb_info(u8 *buf)
+{
+	u8 tmp[5];
+
+	u8 cmd[3] = { STMFTS_RW_FRAMEBUFFER_REG, 0, 0 };
+	int res = 0;
+
+
+	for (u32 i = 0; i < 0x10000; i+=4)
+	{
+		if (!res)
+		{
+			cmd[1] = (i >> 8) & 0xFF;
+			cmd[2] = i & 0xFF;
+			memset(tmp, 0xCC, 5);
+			res = touch_read_reg(cmd, 3, tmp, 5);
+			memcpy(&buf[i], tmp + 1, 4);
+		}
+	}
+
+	return res;
+}
+
 int touch_sense_enable()
 {
 	// Enable auto tuning calibration and multi-touch sensing.
@@ -338,7 +361,7 @@ int touch_power_on()
 	// Enables LDO6 for touchscreen VDD/AVDD supply
 	max77620_regulator_set_volt_and_flags(REGULATOR_LDO6, 2900000, MAX77620_POWER_MODE_NORMAL);
 	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_LDO6_CFG2,
-		MAX77620_LDO_CFG2_ADE_ENABLE | (3 << 3) | (MAX77620_POWER_MODE_NORMAL << MAX77620_LDO_POWER_MODE_SHIFT));
+		 (MAX77620_POWER_MODE_NORMAL << MAX77620_LDO_POWER_MODE_SHIFT | (3 << 3) | MAX77620_LDO_CFG2_ADE_ENABLE));
 
 	// Configure touchscreen GPIO.
 	PINMUX_AUX(PINMUX_AUX_DAP4_SCLK) = PINMUX_PULL_DOWN | 1;

bdk/input/touch.h

@@ -20,7 +20,7 @@
 #ifndef __TOUCH_H_
 #define __TOUCH_H_
 
-#include "../utils/types.h"
+#include <utils/types.h>
 
 #define STMFTS_I2C_ADDR 0x49
 

bdk/libs/compr/blz.h

@@ -17,7 +17,7 @@
 #ifndef _BLZ_H_
 #define _BLZ_H_
 
-#include "../../utils/types.h"
+#include <utils/types.h>
 
 typedef struct _blz_footer
 {

bdk/libs/compr/lz.c

@@ -125,7 +125,7 @@ static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf )
 *  insize  - Number of input bytes.
 *************************************************************************/
 
-void LZ_Uncompress( const unsigned char *in, unsigned char *out,
+unsigned int LZ_Uncompress( const unsigned char *in, unsigned char *out,
     unsigned int insize )
 {
     unsigned char marker, symbol;
@@ -134,7 +134,7 @@ void LZ_Uncompress( const unsigned char *in, unsigned char *out,
     /* Do we have anything to uncompress? */
     if( insize < 1 )
     {
-        return;
+        return 0;
     }
 
     /* Get marker symbol from input stream */
@@ -176,4 +176,6 @@ void LZ_Uncompress( const unsigned char *in, unsigned char *out,
         }
     }
     while( inpos < insize );
+
+    return outpos;
 }

bdk/libs/compr/lz.h

@@ -41,7 +41,7 @@ extern "C" {
 * Function prototypes
 *************************************************************************/
 
-void LZ_Uncompress( const unsigned char *in, unsigned char *out,
+unsigned int LZ_Uncompress( const unsigned char *in, unsigned char *out,
                     unsigned int insize );
 
 

bdk/libs/fatfs/diskio.h

@@ -9,7 +9,7 @@
 extern "C" {
 #endif
 
-#include "../../utils/types.h"
+#include <utils/types.h>
 
 /* Status of Disk Functions */
 typedef BYTE	DSTATUS;
@@ -23,6 +23,13 @@ typedef enum {
 	RES_PARERR		/* 4: Invalid Parameter */
 } DRESULT;
 
+typedef enum {
+	DRIVE_SD   = 0,
+	DRIVE_RAM  = 1,
+	DRIVE_EMMC = 2,
+	DRIVE_BIS  = 3
+} DDRIVE;
+
 
 /*---------------------------------------*/
 /* Prototypes for disk control functions */
@@ -33,6 +40,7 @@ DSTATUS disk_status (BYTE pdrv);
 DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
 DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
 DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+DRESULT disk_set_info (BYTE pdrv, BYTE cmd, void *buff);
 
 
 /* Disk Status Bits (DSTATUS) */
@@ -47,6 +55,7 @@ DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
 /* Generic command (Used by FatFs) */
 #define CTRL_SYNC			0	/* Complete pending write process (needed at FF_FS_READONLY == 0) */
 #define GET_SECTOR_COUNT	1	/* Get media size (needed at FF_USE_MKFS == 1) */
+#define SET_SECTOR_COUNT	1	/* Set media size (needed at FF_USE_MKFS == 1) */
 #define GET_SECTOR_SIZE		2	/* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
 #define GET_BLOCK_SIZE		3	/* Get erase block size (needed at FF_USE_MKFS == 1) */
 #define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */

bdk/libs/fatfs/ff.c

@@ -38,7 +38,7 @@
 
 #include "ff.h"			/* Declarations of FatFs API */
 #include "diskio.h"		/* Declarations of device I/O functions */
-#include "../../gfx/gfx.h"
+#include <gfx_utils.h>
 
 #define EFSPRINTF(text, ...) print_error(); gfx_printf("%k"text"%k\n", 0xFFFFFF00, 0xFFFFFFFF);
 //#define EFSPRINTF(...)
@@ -3906,11 +3906,11 @@ FRESULT f_read (
 
 
 
-#ifdef FF_FASTFS
+#if FF_FASTFS && FF_USE_FASTSEEK
 /*-----------------------------------------------------------------------*/
 /* Fast Read Aligned Sized File Without a Cache                         */
 /*-----------------------------------------------------------------------*/
-#if FF_USE_FASTSEEK
+
 FRESULT f_read_fast (
 	FIL* fp,			/* Pointer to the file object */
 	const void* buff,	/* Pointer to the data to be written */
@@ -3988,7 +3988,6 @@ FRESULT f_read_fast (
 	LEAVE_FF(fs, FR_OK);
 }
 #endif
-#endif
 
 
 
@@ -4132,11 +4131,11 @@ FRESULT f_write (
 
 
 
-#ifdef FF_FASTFS
+#if FF_FASTFS && FF_USE_FASTSEEK
 /*-----------------------------------------------------------------------*/
 /* Fast Write Aligned Sized File Without a Cache                         */
 /*-----------------------------------------------------------------------*/
-#if FF_USE_FASTSEEK
+
 FRESULT f_write_fast (
 	FIL* fp,			/* Pointer to the file object */
 	const void* buff,	/* Pointer to the data to be written */
@@ -4219,7 +4218,6 @@ FRESULT f_write_fast (
 	LEAVE_FF(fs, FR_OK);
 }
 #endif
-#endif
 
 
 
@@ -4680,8 +4678,7 @@ FRESULT f_lseek (
 
 
 
-#ifdef FF_FASTFS
-#if FF_USE_FASTSEEK
+#if FF_FASTFS && FF_USE_FASTSEEK
 /*-----------------------------------------------------------------------*/
 /* Seek File Read/Write Pointer                                          */
 /*-----------------------------------------------------------------------*/
@@ -4708,7 +4705,6 @@ DWORD *f_expand_cltbl (
 	return fp->cltbl;
 }
 #endif
-#endif
 
 
 
@@ -5842,7 +5838,7 @@ FRESULT f_mkfs (
 	UINT len			/* Size of working buffer [byte] */
 )
 {
-	const UINT n_fats = 1;		/* Number of FATs for FAT/FAT32 volume (1 or 2) */
+	const UINT n_fats = 2;		/* Number of FATs for FAT/FAT32 volume (1 or 2) */
 	const UINT n_rootdir = 512;	/* Number of root directory entries for FAT volume */
 	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT volume (4Ks unit) */
 	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (128Ks unit) */
@@ -5906,7 +5902,7 @@ FRESULT f_mkfs (
 	} else {
 		/* Create a single-partition in this function */
 		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
-		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+		b_vol = (opt & FM_SFD) ? 0 : 32768;		/* Volume start sector. Align to 16MB */
 		if (sz_vol < b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);
 		sz_vol -= b_vol;						/* Volume size */
 	}
@@ -6130,6 +6126,9 @@ FRESULT f_mkfs (
 			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
 				sz_rsv += n; b_fat += n;
 			} else {					/* FAT: Expand FAT size */
+				if (n % n_fats) {	/* Adjust fractional error if needed */
+					n--; sz_rsv++; b_fat++;
+				}
 				sz_fat += n / n_fats;
 			}
 
@@ -6193,13 +6192,13 @@ FRESULT f_mkfs (
 			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
 			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
 			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
-			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+			mem_cpy(buf + BS_VolLab32, "SWITCH SD  " "FAT32   ", 19);	/* Volume label, FAT signature */
 		} else {
 			st_dword(buf + BS_VolID, GET_FATTIME());	/* VSN */
 			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
 			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
 			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
-			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+			mem_cpy(buf + BS_VolLab, "SWITCH SD  " "FAT     ", 19);	/* Volume label, FAT signature */
 		}
 		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
 		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Write it to the VBR sector */

bdk/libs/fatfs/ff.h

@@ -26,8 +26,8 @@
 extern "C" {
 #endif
 
-#include "../../utils/types.h"	/* Basic integer types */
-#include "ffconf.h"		/* FatFs configuration options */
+#include <utils/types.h>	/* Basic integer types */
+#include <fatfs_cfg.h>	/* FatFs configuration options */
 
 #if FF_DEFINED != FFCONF_DEF
 #error Wrong configuration file (ffconf.h).
@@ -246,7 +246,7 @@ typedef enum {
 	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
 	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
 	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > FF_FS_LOCK */
-#ifdef FF_FASTFS
+#if FF_FASTFS
 	FR_INVALID_PARAMETER,	/* (19) Given parameter is invalid */
 	FR_CLTBL_NO_INIT	    /* (20) The cluster table for fast seek/read/write was not created */
 #else
@@ -263,10 +263,8 @@ FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a f
 FRESULT f_close (FIL* fp);											/* Close an open file object */
 FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
 FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
-#ifdef FF_FASTFS
 FRESULT f_read_fast (FIL* fp, const void* buff, UINT btr);			/* Fast read data from the file */
 FRESULT f_write_fast (FIL* fp, const void* buff, UINT btw);         /* Fast write data to the file */
-#endif
 FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
 FRESULT f_truncate (FIL* fp);										/* Truncate the file */
 FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
@@ -288,9 +286,7 @@ FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get numbe
 FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
 FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
 FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
-#ifdef FF_FASTFS
 DWORD  *f_expand_cltbl (FIL* fp, UINT tblsz, FSIZE_t ofs);			/* Expand file and populate cluster table */
-#endif
 FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt);					/* Allocate a contiguous block to the file */
 FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
 FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
@@ -380,8 +376,11 @@ int ff_del_syncobj (FF_SYNC_t sobj);	/* Delete a sync object */
 #define	AM_RDO	0x01	/* Read only */
 #define	AM_HID	0x02	/* Hidden */
 #define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume */
 #define AM_DIR	0x10	/* Directory */
 #define AM_ARC	0x20	/* Archive */
+#define AM_DEV	0x40	/* Device */
+#define AM_RVD	0x80	/* Reserved */
 
 
 #ifdef __cplusplus

bdk/libs/lv_conf.h

@@ -17,8 +17,8 @@
 #ifndef LV_CONF_H
 #define LV_CONF_H
 
-#include "../utils/types.h"
-#include "../../../common/memory_map.h"
+#include <utils/types.h>
+#include <memory_map.h>
 /*===================
    Dynamic memory
  *===================*/
@@ -32,7 +32,7 @@
 #  define LV_MEM_ADR          NYX_LV_MEM_ADR /*Set an address for memory pool instead of allocation it as an array. Can be in external SRAM too.*/
 #  define LV_MEM_AUTO_DEFRAG  1              /*Automatically defrag on free*/
 #else       /*LV_MEM_CUSTOM*/
-#  define LV_MEM_CUSTOM_INCLUDE "../../../mem/heap.h"   /*Header for the dynamic memory function*/
+#  define LV_MEM_CUSTOM_INCLUDE <mem/heap.h> /*Header for the dynamic memory function*/
 #  define LV_MEM_CUSTOM_ALLOC   malloc       /*Wrapper to malloc*/
 #  define LV_MEM_CUSTOM_FREE    free         /*Wrapper to free*/
 #endif     /*LV_MEM_CUSTOM*/
@@ -149,7 +149,7 @@
 /*HAL settings*/
 #define LV_TICK_CUSTOM               1                       /*1: use a custom tick source (removing the need to manually update the tick with `lv_tick_inc`) */
 #if LV_TICK_CUSTOM == 1
-#define LV_TICK_CUSTOM_INCLUDE       "../../../utils/util.h" /*Header for the sys time function*/
+#define LV_TICK_CUSTOM_INCLUDE       <utils/util.h>          /*Header for the sys time function*/
 #define LV_TICK_CUSTOM_SYS_TIME_EXPR (get_tmr_ms())          /*Expression evaluating to current systime in ms*/
 #endif     /*LV_TICK_CUSTOM*/
 
@@ -163,7 +163,7 @@
  * LV_LOG_LEVEL_WARN        Log if something unwanted happened but didn't caused problem
  * LV_LOG_LEVEL_ERROR       Only critical issue, when the system may fail
  */
-#  define LV_LOG_LEVEL    LV_LOG_LEVEL_ERROR
+#  define LV_LOG_LEVEL    LV_LOG_LEVEL_WARN
 /* 1: Print the log with 'printf'; 0: user need to register a callback*/
 #  define LV_LOG_PRINTF   1
 #endif  /*USE_LV_LOG*/

bdk/libs/lvgl/lv_core/lv_indev.c

@@ -357,7 +357,10 @@ static void indev_pointer_proc(lv_indev_t * i, lv_indev_data_t * data)
     if(i->cursor != NULL &&
             (i->proc.last_point.x != data->point.x ||
              i->proc.last_point.y != data->point.y)) {
-        lv_obj_set_pos(i->cursor, data->point.x, data->point.y);
+        /*Use cursor's center as pointer*/
+        uint32_t off_x = lv_obj_get_width(i->cursor) >> 1;
+        uint32_t off_y = lv_obj_get_height(i->cursor) >> 1;
+        lv_obj_set_pos(i->cursor, data->point.x - off_x, data->point.y - off_y);
     }
 
     i->proc.act_point.x = data->point.x;

bdk/libs/lvgl/lv_fonts/hekate_symbol_120.c

@@ -16,7 +16,7 @@
 
 #include "../lv_misc/lv_font.h"
 
-#include "../../../../../common/memory_map.h"
+#include <memory_map.h>
 
 #if USE_HEKATE_SYMBOL_120 != 0	/*Can be enabled in lv_conf.h*/
 

bdk/libs/lvgl/lv_fonts/hekate_symbol_20.c

@@ -16,7 +16,7 @@
 
 #include "../lv_misc/lv_font.h"
 
-#include "../../../../../common/memory_map.h"
+#include <memory_map.h>
 
 #if USE_HEKATE_SYMBOL_20 != 0	/*Can be enabled in lv_conf.h*/
 

bdk/libs/lvgl/lv_fonts/hekate_symbol_30.c

@@ -16,7 +16,7 @@
 
 #include "../lv_misc/lv_font.h"
 
-#include "../../../../../common/memory_map.h"
+#include <memory_map.h>
 
 #if USE_HEKATE_SYMBOL_30 != 0	/*Can be enabled in lv_conf.h*/
 

bdk/libs/lvgl/lv_fonts/interui_20.c

@@ -16,7 +16,7 @@
 
 #include "../lv_misc/lv_font.h"
 
-#include "../../../../../common/memory_map.h"
+#include <memory_map.h>
 
 #if USE_INTERUI_20 != 0	/*Can be enabled in lv_conf.h*/
 

bdk/libs/lvgl/lv_fonts/interui_30.c

@@ -16,7 +16,7 @@
 
 #include "../lv_misc/lv_font.h"
 
-#include "../../../../../common/memory_map.h"
+#include <memory_map.h>
 
 #if USE_INTERUI_30 != 0	/*Can be enabled in lv_conf.h*/
 

bdk/libs/lvgl/lv_fonts/ubuntu_mono.c

@@ -16,7 +16,7 @@
 
 #include "../lv_misc/lv_font.h"
 
-#include "../../../../../common/memory_map.h"
+#include <memory_map.h>
 
 #if USE_UBUNTU_MONO != 0	/*Can be enabled in lv_conf.h*/
 

bdk/libs/lvgl/lv_hal/lv_hal_indev.h

@@ -17,7 +17,7 @@ extern "C" {
  *********************/
 #include <stdint.h>
 #include "lv_hal.h"
-#include "../../../utils/types.h"
+#include <utils/types.h>
 #include "../lv_misc/lv_area.h"
 #include "../lv_core/lv_obj.h"
 

bdk/libs/lvgl/lv_misc/lv_area.h

@@ -15,7 +15,7 @@ extern "C" {
  *      INCLUDES
  *********************/
 #include <string.h>
-#include "../../../utils/types.h"
+#include <utils/types.h>
 
 /*********************
  *      DEFINES

bdk/libs/lvgl/lv_misc/lv_circ.h

@@ -16,7 +16,7 @@ extern "C" {
  *********************/
 #include <stddef.h>
 #include "lv_area.h"
-#include "../../../utils/types.h"
+#include <utils/types.h>
 
 /*********************
  *      DEFINES

bdk/libs/lvgl/lv_misc/lv_color.c

@@ -1,3 +1,19 @@
+/*
+ * Copyright (c) 2019-2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
 /**
  * @file lv_color.c
  *
@@ -12,6 +28,8 @@
  *      DEFINES
  *********************/
 
+#define HUE_DEGREE 512
+
 /**********************
  *      TYPEDEFS
  **********************/
@@ -43,57 +61,68 @@
  * @param v value [0..100]
  * @return the given RGB color in RGB (with LV_COLOR_DEPTH depth)
  */
-lv_color_t lv_color_hsv_to_rgb(uint16_t h, uint8_t s, uint8_t v)
+lv_color_t lv_color_hsv_to_rgb(uint16_t hue, uint8_t sat, uint8_t val)
 {
-    if(s == 0)
-        return LV_COLOR_MAKE(v, v, v);
-
-    h = (uint32_t)((uint32_t)h * 255) / 360;
-    s = (uint16_t)((uint16_t)s * 255) / 100;
-    v = (uint16_t)((uint16_t)v * 255) / 100;
-
     uint8_t r, g, b;
 
-    uint8_t region, remainder, p, q, t;
+    uint32_t h = (hue * 360 * HUE_DEGREE -1) / 360;
+    uint32_t s = sat * 255 / 100;
+    uint32_t v = val * 255 / 100;
+    uint32_t p = (256 * v - s * v) / 256;
+    uint32_t region = h / (60 * 512);
+    
+    if(sat == 0)
+        return LV_COLOR_MAKE(v, v, v);
 
-    region = h / 43;
-    remainder = (h - (region * 43)) * 6;
+    if (region & 1)
+    {
+        uint32_t q = (256 * 60 * HUE_DEGREE * v - h * s * v + 60 * HUE_DEGREE * s * v * region) /
+            (256 * 60 * HUE_DEGREE);
 
-    p = (v * (255 - s)) >> 8;
-    q = (v * (255 - ((s * remainder) >> 8))) >> 8;
-    t = (v * (255 - ((s * (255 - remainder)) >> 8))) >> 8;
-
-    switch(region) {
-        case 0:
-            r = v;
-            g = t;
-            b = p;
-            break;
+        switch (region)
+        {
         case 1:
             r = q;
             g = v;
             b = p;
             break;
+        case 3:
+            r = p;
+            g = q;
+            b = v;
+            break;
+        case 5:
+        default:
+            r = v;
+            g = p;
+            b = q;
+            break;
+        }
+    }
+    else
+    {
+        uint32_t t = (256 * 60 * HUE_DEGREE * v + h * s * v - 60 * HUE_DEGREE * s * v * (region + 1)) /
+            (256 * 60 * HUE_DEGREE);
+
+        switch (region)
+        {
+        case 0:
+            r = v;
+            g = t;
+            b = p;
+            break;
         case 2:
             r = p;
             g = v;
             b = t;
             break;
-        case 3:
-            r = p;
-            g = q;
-            b = v;
-            break;
         case 4:
+        default:
             r = t;
             g = p;
             b = v;
             break;
-        default:
-            r = v;
-            g = p;
-            b = q;
-            break;
+        }
     }
 
     return LV_COLOR_MAKE(r, g, b);

bdk/libs/lvgl/lv_misc/lv_color.h

@@ -432,7 +432,7 @@ static inline uint8_t lv_color_brightness(lv_color_t color)
  * @param v value [0..100]
  * @return the given RGB color in RGB (with LV_COLOR_DEPTH depth)
  */
-lv_color_t lv_color_hsv_to_rgb(uint16_t h, uint8_t s, uint8_t v);
+lv_color_t lv_color_hsv_to_rgb(uint16_t hue, uint8_t sat, uint8_t val);
 
 /**
  * Convert an RGB color to HSV