v2.1 (and like always, transfer unmerged PRs)

ipl/hos.c

@@ -378,13 +378,8 @@ int hos_launch(ini_sec_t *cfg)
 	memset(&ctxt, 0, sizeof(launch_ctxt_t));
 	list_init(&ctxt.kip1_list);
 
-	gfx_clear(&gfx_ctxt, 0xFF1B1B1B);
-	gfx_con_setpos(&gfx_con, 0, 0);
-
 	if (cfg && !_config(&ctxt, cfg))
 		return 0;
-        
-	gfx_printf(&gfx_con, "Initializing...\n\n");
 
 	//Read package1 and the correct keyblob.
 	if (!_read_emmc_pkg1(&ctxt))
@@ -502,7 +497,7 @@ int hos_launch(ini_sec_t *cfg)
 			break;
 	}
 
-	//Clear 'BootConfig' for retail systems.
+	//Clear 'BootConfig'.
 	memset((void *)0x4003D000, 0, 0x3000);
 
 	//pkg2_decrypt((void *)0xA9800000);

ipl/main.c

@@ -1025,7 +1025,7 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
 	if(isSmallSdCard)
 	{
 		f_unlink(partialIdxFilename);
-		gfx_printf(&gfx_con, "%k\n\nYou can now join the files\nand get the complete raw eMMC dump.", 0xFFCCCCCC);
+		gfx_printf(&gfx_con, "%k%K\n\nYou can now join the files\nand get the complete raw eMMC dump.", 0xFFCCCCCC, 0xFF1B1B1B);
 	}
 	gfx_puts(&gfx_con, "\n\n");
 
@@ -1127,10 +1127,10 @@ static void dump_emmc_selected(dumpType_t dumpType)
 	}
 
 	gfx_putc(&gfx_con, '\n');
-	gfx_printf(&gfx_con, "Time taken: %d seconds.\n", (get_tmr() - timer) / 1000000);
+	gfx_printf(&gfx_con, "%kTime taken: %d seconds.%k\n", 0xFF00FF96, (get_tmr() - timer) / 1000000, 0xFFCCCCCC);
 	sdmmc_storage_end(&storage);
 	if (res)
-		gfx_printf(&gfx_con, "\n%kFinished and verified!%k\nPress any key.\n",0xFF00FF96, 0xFFCCCCCC);
+		gfx_puts(&gfx_con, "\nFinished and verified!\nPress any key.\n");
 
 out:;
 	btn_wait();
@@ -1430,7 +1430,7 @@ ment_t ment_top[] = {
 };
 menu_t menu_top = {
 	ment_top,
-	"hekate - ipl (CTCaer mod v2.2)", 0, 0
+	"hekate - ipl (CTCaer mod v2.1)", 0, 0
 };
 
 extern void pivot_stack(u32 stack_top);

ipl/pkg1.c

@@ -90,7 +90,7 @@ PATCHSET_DEF(_kernel_4_patchset,
 );
 
 PATCHSET_DEF(_kernel_5_patchset,
-	{ 0x45E6C, _NOP() },         // Disable SVC verifications
+	{ 0xFFFFFFFF, 0xFFFFFFFF },  // TODO: MISSING
 	{ 0x5513C, _MOVZX(8, 1, 0) } // Enable Debug Patch
 );
 

ipl/sd.h

@@ -86,7 +86,6 @@
 #define UHS_SDR50_BUS_SPEED		2
 #define UHS_SDR104_BUS_SPEED	3
 #define UHS_DDR50_BUS_SPEED		4
-#define HS400_BUS_SPEED 		5
 
 /*
 * SD_SWITCH mode
@@ -103,6 +102,6 @@
 * SD_SWITCH access modes
 */
 #define SD_SWITCH_ACCESS_DEF	0
-#define SD_SWITCH_ACCESS_HS		1
+#define SD_SWITCH_ACCESS_HS	1
 
 #endif /* LINUX_MMC_SD_H */

ipl/sdmmc_driver.c

@@ -204,34 +204,32 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
 	case 1:
 	case 5:
 	case 6:
-		sdmmc->regs->hostctl  &= 0xFB; //Should this be 0xFFFB (~4) ?
+		sdmmc->regs->hostctl &= 0xFB;
-		sdmmc->regs->hostctl2 &= SDHCI_CTRL_VDD_330;
+		sdmmc->regs->hostctl2 &= 0xFFF7;
 		break;
 	case 2:
 	case 7:
-		sdmmc->regs->hostctl  |= 4;
+		sdmmc->regs->hostctl |= 4;
-		sdmmc->regs->hostctl2 &= SDHCI_CTRL_VDD_330;
+		sdmmc->regs->hostctl2 &= 0xFFF7;
 		break;
 	case 3:
 	case 11:
 	case 13:
 	case 14:
-		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED;
+		sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & 0xFFF8) | 3;
-		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
+		sdmmc->regs->hostctl2 |= 8;
 		break;
 	case 4:
-		 //Non standard
+		sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & 0xFFF8) | 5;
-		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | HS400_BUS_SPEED;
+		sdmmc->regs->hostctl2 |= 8;
-		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
 		break;
 	case 8:
-		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR12_BUS_SPEED;
+		sdmmc->regs->hostctl2 = sdmmc->regs->hostctl2 & 0xFFF8;
-		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
+		sdmmc->regs->hostctl2 |= 8;
 		break;
 	case 10:
-		//T210 Errata for SDR50, the host must be set to SDR104.
+		sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & 0xFFF8) | 2;
-		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED;
+		sdmmc->regs->hostctl2 |= 8;
-		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
 		break;
 	}
 
@@ -553,16 +551,16 @@ int sdmmc_config_tuning(sdmmc_t *sdmmc, u32 type, u32 cmd)
 	sdmmc->regs->field_1C0 = (sdmmc->regs->field_1C0 & 0xFFFF1FFF) | flag;
 	sdmmc->regs->field_1C0 = (sdmmc->regs->field_1C0 & 0xFFFFE03F) | 0x40;
 	sdmmc->regs->field_1C0 |= 0x20000;
-	sdmmc->regs->hostctl2  |= SDHCI_CTRL_EXEC_TUNING;
+	sdmmc->regs->hostctl2 |= 0x40;
 
 	for (u32 i = 0; i < max; i++)
 	{
 		_sdmmc_config_tuning_once(sdmmc, cmd);
-		if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING))
+		if (!(sdmmc->regs->hostctl2 & 0x40))
 			break;
 	}
 
-	if (sdmmc->regs->hostctl2 & SDHCI_CTRL_TUNED_CLK)
+	if (sdmmc->regs->hostctl2 & 0x80)
 		return 1;
 	return 0;
 }
@@ -579,14 +577,14 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
 			return 0;
 	}
 
-	sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_PRESET_VAL_EN;
+	sdmmc->regs->hostctl2 &= 0x7FFF;
-	sdmmc->regs->clkcon   &= ~TEGRA_MMC_CLKCON_CLKGEN_SELECT;
+	sdmmc->regs->clkcon &= ~TEGRA_MMC_CLKCON_CLKGEN_SELECT;
-	sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN;
+	sdmmc->regs->hostctl2 |= 0x1000;
 
 	if (!(sdmmc->regs->capareg & 0x10000000))
 		return 0;
 
-	sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN;
+	sdmmc->regs->hostctl2 |= 0x2000;
 	sdmmc->regs->hostctl &= 0xE7;
 	sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 0xE;
 
@@ -1078,7 +1076,7 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
 	_sdmmc_get_clkcon(sdmmc);
 	sleep(5000);
 	
-	if (sdmmc->regs->hostctl2 & SDHCI_CTRL_VDD_180)
+	if (sdmmc->regs->hostctl2 & 8)
 	{
 		sdmmc->regs->clkcon |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 		_sdmmc_get_clkcon(sdmmc);

ipl/sdmmc_driver.h

@@ -45,28 +45,9 @@
 #define SDMMC_RSP_TYPE_5 5
 
 /*! SDMMC mask interrupt status. */
-#define SDMMC_MASKINT_MASKED   0
+#define SDMMC_MASKINT_MASKED 0
 #define SDMMC_MASKINT_NOERROR -1
-#define SDMMC_MASKINT_ERROR   -2
+#define SDMMC_MASKINT_ERROR -2
-
-/*! SDMMC host control 2 */
-#define SDHCI_CTRL_UHS_MASK			0xFFF8
-#define SDHCI_CTRL_VDD_330			0xFFF7
-#define SDHCI_CTRL_VDD_180			8
-#define SDHCI_CTRL_EXEC_TUNING		0x40
-#define SDHCI_CTRL_TUNED_CLK		0x80
-#define SDHCI_HOST_VERSION_4_EN		0x1000
-#define SDHCI_ADDRESSING_64BIT_EN	0x2000
-#define SDHCI_CTRL_PRESET_VAL_EN	0x8000
-
-/*! SD bus speeds. */
-#define UHS_SDR12_BUS_SPEED		0
-#define HIGH_SPEED_BUS_SPEED	1
-#define UHS_SDR25_BUS_SPEED		1
-#define UHS_SDR50_BUS_SPEED		2
-#define UHS_SDR104_BUS_SPEED	3
-#define UHS_DDR50_BUS_SPEED		4
-#define HS400_BUS_SPEED 		5
 
 /*! Helper for SWITCH command argument. */
 #define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))

ipl/tui.c

@@ -27,7 +27,7 @@ void tui_pbar(gfx_con_t *con, int x, int y, u32 val, u32 fgcol, u32 bgcol)
 
 	gfx_con_setpos(con, x, y);
 
-	gfx_printf(con, "%k[%3d%%]%k", fgcol, val, 0xFFCCCCCC);
+	gfx_printf(con, "%k[%3d%%]%k", fgcol, val, bgcol);
 
 	x += 7 * con->fntsz;