v2.1 (and like always, transfer unmerged PRs)

So, it's time to move 1.0.0 secmon.
If we want to continue having a full featured bootloader, this change is a must.

It will move the secmon to 0x4002B000 + 0x20 (to keep the values addresses aligned).
It fixes relocator patch.

So now the payload size limit is 160KB - .bss (~158KB).

Makefile

@@ -44,7 +44,7 @@ OBJS = $(addprefix $(BUILD)/, \
 OBJS += $(addprefix $(BUILD)/, diskio.o ff.o ffunicode.o)
 
 ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-CFLAGS = $(ARCH) -Os -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11# -Wall
+CFLAGS = $(ARCH) -O2 -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11# -Wall
 LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections
 
 .PHONY: all clean

README.md

@@ -4,13 +4,49 @@
 
 Nintendo Switch bootloader, firmware patcher, and more.
 
+
 ## ipl config
 
 The ipl can be configured via 'hekate_ipl.ini' (if it is present on the SD card). Each ini section represents a boot entry, except for the special section 'config' that controls the global configuration.
 
-Possible key/value combinations:
+### Possible key/value combinations:
 
- - warmboot={SD path}
- - secmon={SD path}
- - kernel={SD path}
- - kip1={SD path}
+| Config option      | Description                                                |
+| ------------------ | ---------------------------------------------------------- |
+| warmboot={SD path} | Replaces the warmboot binary                               |
+| secmon={SD path}   | Replaces the security monitor binary                       |
+| kernel={SD path}   | Replaces the kernel binary                                 |
+| kip1={SD path}     | Replaces/Adds kernel initial process. Multiple can be set. |
+| fullsvcperm=1      | Disables SVC verification                                  |
+| debugmode=1        | Enables Debug mode                                         |
+
+
+
+```
+hekate (C) 2018 naehrwert, st4rk.
+
+Thanks to: derrek, nedwill, plutoo, shuffle2, smea, thexyz, yellows8.
+Greetings to: fincs, hexkyz, SciresM, Shiny Quagsire, WinterMute.
+
+Open source and free packages used:
+ - FatFs R0.13a, Copyright (C) 2017, ChaN
+ - bcl-1.2.0,    Copyright (C) 2003-2006, Marcus Geelnard
+
+                         ___
+                      .-'   `'.
+                     /         \
+                     |         ;
+                     |         |           ___.--,
+            _.._     |0) = (0) |    _.---'`__.-( (_.
+     __.--'`_.. '.__.\    '--. \_.-' ,.--'`     `""`
+    ( ,.--'`   ',__ /./;   ;, '.__.'`    __
+    _`) )  .---.__.' / |   |\   \__..--""  """--.,_
+   `---' .'.''-._.-'`_./  /\ '.  \ _.--''````'''--._`-.__.'
+         | |  .' _.-' |  |  \  \  '.               `----`
+          \ \/ .'     \  \   '. '-._)
+           \/ /        \  \    `=.__`'-.
+           / /\         `) )    / / `"".`\
+     , _.-'.'\ \        / /    ( (     / /
+      `--'`   ) )    .-'.'      '.'.  | (
+             (/`    ( (`          ) )  '-;   [switchbrew]
+```

ipl/di.c

@@ -87,31 +87,31 @@ void display_init()
 
 	sleep(60000);
 
-	DSI(_DSIREG(DSI_DSI_BTA_TIMING)) = 0x50204;
-	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x337;
-	DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2;
-	_display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3);
+	DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
+	DSI(_DSIREG(DSI_WR_DATA)) = 0x337;
+	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
 
-	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x406;
-	DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2;
-	_display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3);
+	DSI(_DSIREG(DSI_WR_DATA)) = 0x406;
+	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
+	_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
 
-	DSI(_DSIREG(DSI_HOST_DSI_CONTROL)) = 0x200B;
-	_display_dsi_wait(150000, _DSIREG(DSI_HOST_DSI_CONTROL), 8);
+	DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
+	_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
 
 	sleep(5000);
 
-	_display_ver = DSI(_DSIREG(DSI_DSI_RD_DATA));
+	_display_ver = DSI(_DSIREG(DSI_RD_DATA));
 	if (_display_ver == 0x10)
 		exec_cfg((u32 *)DSI_BASE, _display_config_4, 43);
 
-	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1105;
-	DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2;
+	DSI(_DSIREG(DSI_WR_DATA)) = 0x1105;
+	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
 
 	sleep(180000);
 
-	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2905;
-	DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2;
+	DSI(_DSIREG(DSI_WR_DATA)) = 0x2905;
+	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
 
 	sleep(20000);
 
@@ -134,15 +134,15 @@ void display_init()
 void display_end()
 {
 	GPIO_6(0x24) &= 0xFFFFFFFE;
-	DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 1;
-	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2805;
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1;
+	DSI(_DSIREG(DSI_WR_DATA)) = 0x2805;
 
 	u32 end = HOST1X(0x30A4) + 5;
 	while (HOST1X(0x30A4) < end)
 		;
 
-	DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = 5;
-	DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 0;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
+	DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
 
 	exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17);
 	exec_cfg((u32 *)DSI_BASE, _display_config_13, 16);
@@ -152,8 +152,8 @@ void display_end()
 	if (_display_ver == 0x10)
 		exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
 
-	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1005;
-	DSI(_DSIREG(DSI_DSI_TRIGGER)) = 2;
+	DSI(_DSIREG(DSI_WR_DATA)) = 0x1005;
+	DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
 
 	sleep(50000);
 
@@ -175,8 +175,8 @@ void display_end()
 	CLOCK(0x300) = 0x18000000;
 	CLOCK(0x324) = 0x18000000;
 
-	DSI(_DSIREG(DSI_PAD_CONTROL)) = 0x10F010F;
-	DSI(_DSIREG(DSI_DSI_POWER_CONTROL)) = 0;
+	DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
+	DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
 
 	GPIO_6(0x04) &= 0xFFFFFFFE;
 
@@ -193,7 +193,7 @@ void display_color_screen(u32 color)
 	DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
 	DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
 	DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
-	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | 1;
+	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | GENERAL_ACT_REQ;
 
 	sleep(35000);
 

ipl/di.h

@@ -21,44 +21,319 @@
 
 /*! Display registers. */
 #define _DIREG(reg) ((reg) * 4)
+
+#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
+
+#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
+#define  SYNCPT_CNTRL_NO_STALL   (1 << 8)
+#define  SYNCPT_CNTRL_SOFT_RESET (1 << 0)
+
+#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
+#define  SYNCPT_VSYNC_ENABLE (1 << 8)
+
+#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
+
 #define DC_CMD_DISPLAY_COMMAND 0x32
+#define  DISP_CTRL_MODE_STOP       (0 << 5)
+#define  DISP_CTRL_MODE_C_DISPLAY  (1 << 5)
+#define  DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
+#define  DISP_CTRL_MODE_MASK       (3 << 5)
+
+#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
+#define  PW0_ENABLE (1 <<  0)
+#define  PW1_ENABLE (1 <<  2)
+#define  PW2_ENABLE (1 <<  4)
+#define  PW3_ENABLE (1 <<  6)
+#define  PW4_ENABLE (1 <<  8)
+#define  PM0_ENABLE (1 << 16)
+#define  PM1_ENABLE (1 << 18)
+
+#define DC_CMD_INT_MASK 0x38
+#define DC_CMD_INT_ENABLE 0x39
+
 #define DC_CMD_STATE_ACCESS 0x40
+#define  READ_MUX  (1 << 0)
+#define  WRITE_MUX (1 << 2)
+
 #define DC_CMD_STATE_CONTROL 0x41
+#define  GENERAL_ACT_REQ (1 <<  0)
+#define  WIN_A_ACT_REQ   (1 <<  1)
+#define  WIN_B_ACT_REQ   (1 <<  2)
+#define  WIN_C_ACT_REQ   (1 <<  3)
+#define  CURSOR_ACT_REQ  (1 <<  7)
+#define  GENERAL_UPDATE  (1 <<  8)
+#define  WIN_A_UPDATE    (1 <<  9)
+#define  WIN_B_UPDATE    (1 << 10)
+#define  WIN_C_UPDATE    (1 << 11)
+#define  CURSOR_UPDATE   (1 << 15)
+#define  NC_HOST_TRIG    (1 << 24)
+
 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
+#define  WINDOW_A_SELECT (1 << 4)
+#define  WINDOW_B_SELECT (1 << 5)
+#define  WINDOW_C_SELECT (1 << 6)
+
+#define DC_CMD_REG_ACT_CONTROL 0x043
+
+#define DC_COM_CRC_CONTROL 0x300
+#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
+#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
+
 #define DC_DISP_DISP_WIN_OPTIONS 0x402
+#define  HDMI_ENABLE     (1 << 30)
+#define  DSI_ENABLE      (1 << 29)
+#define  SOR1_TIMING_CYA (1 << 27)
+#define  SOR1_ENABLE     (1 << 26)
+#define  SOR_ENABLE      (1 << 25)
+#define  CURSOR_ENABLE   (1 << 16)
+
+#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
+#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
+#define DC_DISP_DISP_TIMING_OPTIONS 0x405
+#define DC_DISP_REF_TO_SYNC 0x406
+#define DC_DISP_SYNC_WIDTH 0x407
+#define DC_DISP_BACK_PORCH 0x408
+#define DC_DISP_ACTIVE 0x409
+#define DC_DISP_FRONT_PORCH 0x40A
+
 #define DC_DISP_DISP_CLOCK_CONTROL 0x42E
+#define  PIXEL_CLK_DIVIDER_PCD1  (0 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD2  (2 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD3  (3 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD4  (4 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD6  (5 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD8  (6 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD9  (7 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
+#define  PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
+#define  SHIFT_CLK_DIVIDER(x)    ((x) & 0xff)
+
+#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
+#define  DISP_DATA_FORMAT_DF1P1C    (0 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
+#define  DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
+#define  DISP_DATA_FORMAT_DF2S      (4 << 0)
+#define  DISP_DATA_FORMAT_DF3S      (5 << 0)
+#define  DISP_DATA_FORMAT_DFSPI     (6 << 0)
+#define  DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
+#define  DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
+#define  DISP_ALIGNMENT_MSB         (0 << 8)
+#define  DISP_ALIGNMENT_LSB         (1 << 8)
+#define  DISP_ORDER_RED_BLUE        (0 << 9)
+#define  DISP_ORDER_BLUE_RED        (1 << 9)
+
+#define DC_DISP_DISP_COLOR_CONTROL 0x430
+#define  DITHER_CONTROL_MASK    (3 << 8)
+#define  DITHER_CONTROL_DISABLE (0 << 8)
+#define  DITHER_CONTROL_ORDERED (2 << 8)
+#define  DITHER_CONTROL_ERRDIFF (3 << 8)
+#define  BASE_COLOR_SIZE_MASK   (0xf << 0)
+#define  BASE_COLOR_SIZE_666    (0 << 0)
+#define  BASE_COLOR_SIZE_111    (1 << 0)
+#define  BASE_COLOR_SIZE_222    (2 << 0)
+#define  BASE_COLOR_SIZE_333    (3 << 0)
+#define  BASE_COLOR_SIZE_444    (4 << 0)
+#define  BASE_COLOR_SIZE_555    (5 << 0)
+#define  BASE_COLOR_SIZE_565    (6 << 0)
+#define  BASE_COLOR_SIZE_332    (7 << 0)
+#define  BASE_COLOR_SIZE_888    (8 << 0)
+
+#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
+#define  SC1_H_QUALIFIER_NONE	(1 << 16)
+#define  SC0_H_QUALIFIER_NONE	(1 <<  0)
+
+#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
+#define  DE_SELECT_ACTIVE_BLANK  (0 << 0)
+#define  DE_SELECT_ACTIVE        (1 << 0)
+#define  DE_SELECT_ACTIVE_IS     (2 << 0)
+#define  DE_CONTROL_ONECLK       (0 << 2)
+#define  DE_CONTROL_NORMAL       (1 << 2)
+#define  DE_CONTROL_EARLY_EXT    (2 << 2)
+#define  DE_CONTROL_EARLY        (3 << 2)
+#define  DE_CONTROL_ACTIVE_BLANK (4 << 2)
+
+#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
+
+#define DC_WIN_CSC_YOF 0x611
+#define DC_WIN_CSC_KYRGB 0x612
+#define DC_WIN_CSC_KUR 0x613
+#define DC_WIN_CSC_KVR 0x614
+#define DC_WIN_CSC_KUG 0x615
+#define DC_WIN_CSC_KVG 0x616
+#define DC_WIN_CSC_KUB 0x617
+#define DC_WIN_CSC_KVB 0x618
 #define DC_WIN_AD_WIN_OPTIONS 0xB80
 #define DC_WIN_BD_WIN_OPTIONS 0xD80
 #define DC_WIN_CD_WIN_OPTIONS 0xF80
 
 //The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER).
-#define DC_X_WIN_XD_WIN_OPTIONS 0x700
-#define DC_X_WIN_XD_COLOR_DEPTH 0x703
-#define DC_X_WIN_XD_POSITION 0x704
-#define DC_X_WIN_XD_SIZE 0x705
-#define DC_X_WIN_XD_PRESCALED_SIZE 0x706
-#define DC_X_WIN_XD_H_INITIAL_DDA 0x707
-#define DC_X_WIN_XD_V_INITIAL_DDA 0x708
-#define DC_X_WIN_XD_DDA_INCREMENT 0x709
-#define DC_X_WIN_XD_LINE_STRIDE 0x70A
+#define DC_WIN_WIN_OPTIONS 0x700
+#define  H_DIRECTION  (1 <<  0)
+#define  V_DIRECTION  (1 <<  2)
+#define  COLOR_EXPAND (1 <<  6)
+#define  CSC_ENABLE   (1 << 18)
+#define  WIN_ENABLE   (1 << 30)
+
+#define DC_WIN_COLOR_DEPTH 0x703
+#define  WIN_COLOR_DEPTH_P1             0x0
+#define  WIN_COLOR_DEPTH_P2             0x1
+#define  WIN_COLOR_DEPTH_P4             0x2
+#define  WIN_COLOR_DEPTH_P8             0x3
+#define  WIN_COLOR_DEPTH_B4G4R4A4       0x4
+#define  WIN_COLOR_DEPTH_B5G5R5A        0x5
+#define  WIN_COLOR_DEPTH_B5G6R5         0x6
+#define  WIN_COLOR_DEPTH_AB5G5R5        0x7
+#define  WIN_COLOR_DEPTH_B8G8R8A8       0xC
+#define  WIN_COLOR_DEPTH_R8G8B8A8       0xD
+#define  WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE
+#define  WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF
+#define  WIN_COLOR_DEPTH_YCbCr422       0x10
+#define  WIN_COLOR_DEPTH_YUV422         0x11
+#define  WIN_COLOR_DEPTH_YCbCr420P      0x12
+#define  WIN_COLOR_DEPTH_YUV420P        0x13
+#define  WIN_COLOR_DEPTH_YCbCr422P      0x14
+#define  WIN_COLOR_DEPTH_YUV422P        0x15
+#define  WIN_COLOR_DEPTH_YCbCr422R      0x16
+#define  WIN_COLOR_DEPTH_YUV422R        0x17
+#define  WIN_COLOR_DEPTH_YCbCr422RA     0x18
+#define  WIN_COLOR_DEPTH_YUV422RA       0x19
+
+#define DC_WIN_BUFFER_CONTROL 0x702
+#define DC_WIN_POSITION 0x704
+
+#define DC_WIN_SIZE 0x705
+#define  H_SIZE(x) (((x) & 0x1fff) <<  0)
+#define  V_SIZE(x) (((x) & 0x1fff) << 16)
+
+#define DC_WIN_PRESCALED_SIZE 0x706
+#define  H_PRESCALED_SIZE(x) (((x) & 0x7fff) <<  0)
+#define  V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
+
+#define DC_WIN_H_INITIAL_DDA 0x707
+#define DC_WIN_V_INITIAL_DDA 0x708
+
+#define DC_WIN_DDA_INC 0x709
+#define  H_DDA_INC(x) (((x) & 0xffff) <<  0)
+#define  V_DDA_INC(x) (((x) & 0xffff) << 16)
+
+#define DC_WIN_LINE_STRIDE 0x70A
+#define DC_WIN_DV_CONTROL 0x70E
 
 //The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER).
-#define DC_X_WINBUF_XD_START_ADDR 0x800
-#define DC_X_WINBUF_XD_ADDR_H_OFFSET 0x806
-#define DC_X_WINBUF_XD_ADDR_V_OFFSET 0x808
-#define DC_X_WINBUF_XD_SURFACE_KIND 0x80B
+#define DC_WINBUF_START_ADDR 0x800
+#define DC_WINBUF_ADDR_H_OFFSET 0x806
+#define DC_WINBUF_ADDR_V_OFFSET 0x808
+#define DC_WINBUF_SURFACE_KIND 0x80B
 
 /*! Display serial interface registers. */
 #define _DSIREG(reg) ((reg) * 4)
-#define DSI_DSI_RD_DATA 0x9
-#define DSI_DSI_WR_DATA 0xA
-#define DSI_DSI_POWER_CONTROL 0xB
-#define DSI_HOST_DSI_CONTROL 0xF
-#define DSI_DSI_TRIGGER 0x13
-#define DSI_DSI_BTA_TIMING 0x3F
-#define DSI_PAD_CONTROL 0x4B
-#define DSI_DSI_VID_MODE_CONTROL 0x4E
+
+#define DSI_RD_DATA 0x9
+#define DSI_WR_DATA 0xA
+
+#define DSI_POWER_CONTROL 0xB
+#define  DSI_POWER_CONTROL_ENABLE 1
+
+#define DSI_INT_ENABLE 0xC
+#define DSI_INT_STATUS 0xD
+#define DSI_INT_MASK 0xE
+
+#define DSI_HOST_CONTROL 0xF
+#define  DSI_HOST_CONTROL_FIFO_RESET   (1 << 21)
+#define  DSI_HOST_CONTROL_CRC_RESET    (1 << 20)
+#define  DSI_HOST_CONTROL_TX_TRIG_SOL  (0 << 12)
+#define  DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
+#define  DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
+#define  DSI_HOST_CONTROL_RAW          (1 << 6)
+#define  DSI_HOST_CONTROL_HS           (1 << 5)
+#define  DSI_HOST_CONTROL_FIFO_SEL     (1 << 4)
+#define  DSI_HOST_CONTROL_IMM_BTA      (1 << 3)
+#define  DSI_HOST_CONTROL_PKT_BTA      (1 << 2)
+#define  DSI_HOST_CONTROL_CS           (1 << 1)
+#define  DSI_HOST_CONTROL_ECC          (1 << 0)
+
+#define DSI_CONTROL 0x10
+#define  DSI_CONTROL_HS_CLK_CTRL  (1 << 20)
+#define  DSI_CONTROL_CHANNEL(c)   (((c) & 0x3) << 16)
+#define  DSI_CONTROL_FORMAT(f)    (((f) & 0x3) << 12)
+#define  DSI_CONTROL_TX_TRIG(x)   (((x) & 0x3) <<  8)
+#define  DSI_CONTROL_LANES(n)     (((n) & 0x3) <<  4)
+#define  DSI_CONTROL_DCS_ENABLE   (1 << 3)
+#define  DSI_CONTROL_SOURCE(s)    (((s) & 0x1) <<  2)
+#define  DSI_CONTROL_VIDEO_ENABLE (1 << 1)
+#define  DSI_CONTROL_HOST_ENABLE  (1 << 0)
+
+#define DSI_SOL_DELAY 0x11
+#define DSI_MAX_THRESHOLD 0x12
+
+#define DSI_TRIGGER 0x13
+#define  DSI_TRIGGER_HOST  (1 << 1)
+#define  DSI_TRIGGER_VIDEO (1 << 0)
+
+#define DSI_TX_CRC 0x14
+#define DSI_STATUS 0x15
+#define DSI_INIT_SEQ_CONTROL 0x1A
+#define DSI_INIT_SEQ_DATA_0 0x1B
+#define DSI_INIT_SEQ_DATA_1 0x1C
+#define DSI_INIT_SEQ_DATA_2 0x1D
+#define DSI_INIT_SEQ_DATA_3 0x1E
+#define DSI_PKT_SEQ_0_LO 0x23
+#define DSI_PKT_SEQ_0_HI 0x24
+#define DSI_PKT_SEQ_1_LO 0x25
+#define DSI_PKT_SEQ_1_HI 0x26
+#define DSI_PKT_SEQ_2_LO 0x27
+#define DSI_PKT_SEQ_2_HI 0x28
+#define DSI_PKT_SEQ_3_LO 0x29
+#define DSI_PKT_SEQ_3_HI 0x2A
+#define DSI_PKT_SEQ_4_LO 0x2B
+#define DSI_PKT_SEQ_4_HI 0x2C
+#define DSI_PKT_SEQ_5_LO 0x2D
+#define DSI_PKT_SEQ_5_HI 0x2E
+#define DSI_DCS_CMDS 0x33
+#define DSI_PKT_LEN_0_1 0x34
+#define DSI_PKT_LEN_2_3 0x35
+#define DSI_PKT_LEN_4_5 0x36
+#define DSI_PKT_LEN_6_7 0x37
+#define DSI_PHY_TIMING_0 0x3C
+#define DSI_PHY_TIMING_1 0x3D
+#define DSI_PHY_TIMING_2 0x3E
+#define DSI_BTA_TIMING 0x3F
+
+#define DSI_TIMEOUT_0 0x44
+#define  DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
+#define  DSI_TIMEOUT_HTX(x) (((x) & 0xffff) <<  0)
+
+#define DSI_TIMEOUT_1 0x45
+#define  DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
+#define  DSI_TIMEOUT_TA(x) (((x) & 0xffff) <<  0)
+
+#define DSI_TO_TALLY 0x46
+
+#define DSI_PAD_CONTROL_0 0x4B
+#define  DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
+#define  DSI_PAD_CONTROL_VS1_PULLDN(x)  (((x) & 0xf) << 16)
+#define  DSI_PAD_CONTROL_VS1_PDIO_CLK   (1 <<  8)
+#define  DSI_PAD_CONTROL_VS1_PDIO(x)    (((x) & 0xf) <<  0)
+
+#define DSI_PAD_CONTROL_CD 0x4c
+#define DSI_VIDEO_MODE_CONTROL 0x4E
+
+#define DSI_PAD_CONTROL_1 0x4F
+#define DSI_PAD_CONTROL_2 0x50
+
+#define DSI_PAD_CONTROL_3 0x51
+#define  DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
+#define  DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
+#define  DSI_PAD_PREEMP_PD(x)     (((x) & 0x3) << 4)
+#define  DSI_PAD_PREEMP_PU(x)     (((x) & 0x3) << 0)
+
+#define DSI_PAD_CONTROL_4 0x52
 
 void display_init();
 void display_end();

ipl/di.inl

@@ -18,263 +18,269 @@
 static const cfg_op_t _display_config_1[4] = {
 	{0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1
 	{0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE
-	{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
-	{0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC
+	{0x36, 0x20},       //CLK_RST_CONTROLLER_PLLD_MISC1
+	{0x37, 0x2D0AAA}    //CLK_RST_CONTROLLER_PLLD_MISC
 };
 
 //Display A config.
 static const cfg_op_t _display_config_2[94] = {
-	{0x40, 0},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{0x43, 0x54},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{0x42, 0x10},
-	{0x42, 0x20},
-	{0x42, 0x40},
-	{0x480, 0},
-	{0x403, 0},
-	{0x404, 0},
-	{0x36, 0x50155},
-	{1, 0x100},
-	{0x28, 0x109},
-	{DC_CMD_STATE_CONTROL, 0xF00},
-	{DC_CMD_STATE_CONTROL, 0xF},
-	{0x40, 0},
-	{0x42, 0x10},
-	{0x700, 0},
-	{0x42, 0x10},
-	{0x70E, 0},
-	{0x700, 0},
-	{0x42, 0x10},
-	{0x42, 0x10},
-	{0x611, 0xF0},
-	{0x612, 0x12A},
-	{0x613, 0},
-	{0x614, 0x198},
-	{0x615, 0x39B},
-	{0x616, 0x32F},
-	{0x617, 0x204},
-	{0x618, 0},
-	{0x42, 0x20},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x70E, 0},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x42, 0x20},
-	{0x611, 0xF0},
-	{0x612, 0x12A},
-	{0x613, 0},
-	{0x614, 0x198},
-	{0x615, 0x39B},
-	{0x616, 0x32F},
-	{0x617, 0x204},
-	{0x618, 0},
-	{0x42, 0x40},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x70E, 0},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x42, 0x40},
-	{0x611, 0xF0},
-	{0x612, 0x12A},
-	{0x613, 0},
-	{0x614, 0x198},
-	{0x615, 0x39B},
-	{0x616, 0x32F},
-	{0x617, 0x204},
-	{0x618, 0},
-	{0x42, 0x10},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x700, 0},
-	{0x430, 8},
-	{0x42F, 0},
-	{0x307, 0x1000000},
-	{0x309, 0},
+	{DC_CMD_STATE_ACCESS, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_REG_ACT_CONTROL, 0x54},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_DISP_DC_MCCIF_FIFOCTRL, 0},
+	{DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
+	{DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
+	{DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
+	{DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
+	{DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
+	{DC_CMD_STATE_ACCESS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_DV_CONTROL, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	/* Setup default YUV colorspace conversion coefficients */
+	{DC_WIN_CSC_YOF,   0xF0},
+	{DC_WIN_CSC_KYRGB, 0x12A},
+	{DC_WIN_CSC_KUR,   0},
+	{DC_WIN_CSC_KVR,   0x198},
+	{DC_WIN_CSC_KUG,   0x39B},
+	{DC_WIN_CSC_KVG,   0x32F},
+	{DC_WIN_CSC_KUB,   0x204},
+	{DC_WIN_CSC_KVB,   0},
+	/* End of color coefficients */
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_DV_CONTROL, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	/* Setup default YUV colorspace conversion coefficients */
+	{DC_WIN_CSC_YOF,   0xF0},
+	{DC_WIN_CSC_KYRGB, 0x12A},
+	{DC_WIN_CSC_KUR,   0},
+	{DC_WIN_CSC_KVR,   0x198},
+	{DC_WIN_CSC_KUG,   0x39B},
+	{DC_WIN_CSC_KVG,   0x32F},
+	{DC_WIN_CSC_KUB,   0x204},
+	{DC_WIN_CSC_KVB,   0},
+	/* End of color coefficients */
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_DV_CONTROL, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	/* Setup default YUV colorspace conversion coefficients */
+	{DC_WIN_CSC_YOF,   0xF0},
+	{DC_WIN_CSC_KYRGB, 0x12A},
+	{DC_WIN_CSC_KUR,   0},
+	{DC_WIN_CSC_KVR,   0x198},
+	{DC_WIN_CSC_KUG,   0x39B},
+	{DC_WIN_CSC_KVG,   0x32F},
+	{DC_WIN_CSC_KUB,   0x204},
+	{DC_WIN_CSC_KVB,   0},
+	/* End of color coefficients */
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
+	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
+	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
+	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
 	{0x4E4, 0},
-	{0x300, 0},
-	{DC_CMD_STATE_CONTROL, 0xF00},
-	{DC_CMD_STATE_CONTROL, 0xF},
-	{0x42, 0x10},
+	{DC_COM_CRC_CONTROL, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{0x716, 0x10000FF},
-	{0x42, 0x20},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
 	{0x716, 0x10000FF},
-	{0x42, 0x40},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
 	{0x716, 0x10000FF},
-	{0x31, 0},
-	{0x42, 0x10},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x700, 0},
-	{0x402, 0},
-	{0x32, 0},
-	{DC_CMD_STATE_CONTROL, 0xF00},
-	{DC_CMD_STATE_CONTROL, 0xF}
+	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_COMMAND, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
 };
 
-//DSI config.
+//DSI Init config.
 static const cfg_op_t _display_config_3[60] = { 
-	{0xA, 0},
-	{0xC, 0},
-	{0xD, 0},
-	{0xE, 0},
-	{0x1B, 0},
-	{0x1C, 0},
-	{0x1D, 0},
-	{0x1E, 0},
-	{0x33, 0},
-	{0x23, 0},
-	{0x25, 0},
-	{0x27, 0},
-	{0x29, 0},
-	{0x2B, 0},
-	{0x2D, 0},
-	{0x24, 0},
-	{0x26, 0},
-	{0x28, 0},
-	{0x2A, 0},
-	{0x2C, 0},
-	{0x2E, 0},
-	{0x10, 0},
-	{0x4C, 0},
-	{0x11, 0x18},
-	{0x12, 0x1E0},
-	{0x13, 0},
-	{0x1A, 0},
-	{0x34, 0},
-	{0x35, 0},
-	{0x36, 0},
-	{0x37, 0},
-	{0x4F, 0},
-	{0x3C, 0x6070601},
-	{0x3D, 0x40A0E05},
-	{0x3E, 0x30109},
-	{0x3F, 0x190A14},
-	{0x44, 0x2000FFFF},
-	{0x45, 0x7652000},
-	{0x46, 0},
-	{0x4B, 0},
-	{DSI_DSI_POWER_CONTROL, 1},
-	{DSI_DSI_POWER_CONTROL, 1},
-	{DSI_DSI_POWER_CONTROL, 0},
-	{DSI_DSI_POWER_CONTROL, 0},
-	{0x4F, 0},
-	{0x3C, 0x6070601},
-	{0x3D, 0x40A0E05},
-	{0x3E, 0x30118},
-	{0x3F, 0x190A14},
-	{0x44, 0x2000FFFF},
-	{0x45, 0x13432000},
-	{0x46, 0},
-	{0xF, 0x102003},
-	{0x10, 0x31},
-	{DSI_DSI_POWER_CONTROL, 1},
-	{DSI_DSI_POWER_CONTROL, 1},
-	{0x12, 0x40},
-	{0x13, 0},
-	{0x14, 0},
-	{0x1A, 0}
+	{DSI_WR_DATA, 0},
+	{DSI_INT_ENABLE, 0},
+	{DSI_INT_STATUS, 0},
+	{DSI_INT_MASK, 0},
+	{DSI_INIT_SEQ_DATA_0, 0},
+	{DSI_INIT_SEQ_DATA_1, 0},
+	{DSI_INIT_SEQ_DATA_2, 0},
+	{DSI_INIT_SEQ_DATA_3, 0},
+	{DSI_DCS_CMDS, 0},
+	{DSI_PKT_SEQ_0_LO, 0},
+	{DSI_PKT_SEQ_1_LO, 0},
+	{DSI_PKT_SEQ_2_LO, 0},
+	{DSI_PKT_SEQ_3_LO, 0},
+	{DSI_PKT_SEQ_4_LO, 0},
+	{DSI_PKT_SEQ_5_LO, 0},
+	{DSI_PKT_SEQ_0_HI, 0},
+	{DSI_PKT_SEQ_1_HI, 0},
+	{DSI_PKT_SEQ_2_HI, 0},
+	{DSI_PKT_SEQ_3_HI, 0},
+	{DSI_PKT_SEQ_4_HI, 0},
+	{DSI_PKT_SEQ_5_HI, 0},
+	{DSI_CONTROL, 0},
+	{DSI_PAD_CONTROL_CD, 0},
+	{DSI_SOL_DELAY, 0x18},
+	{DSI_MAX_THRESHOLD, 0x1E0},
+	{DSI_TRIGGER, 0},
+	{DSI_INIT_SEQ_CONTROL, 0},
+	{DSI_PKT_LEN_0_1, 0},
+	{DSI_PKT_LEN_2_3, 0},
+	{DSI_PKT_LEN_4_5, 0},
+	{DSI_PKT_LEN_6_7, 0},
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PHY_TIMING_0, 0x6070601},
+	{DSI_PHY_TIMING_1, 0x40A0E05},
+	{DSI_PHY_TIMING_2, 0x30109},
+	{DSI_BTA_TIMING, 0x190A14},
+	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
+	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
+	{DSI_TO_TALLY, 0},
+	{DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_POWER_CONTROL, 0},
+	{DSI_POWER_CONTROL, 0},
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PHY_TIMING_0, 0x6070601},
+	{DSI_PHY_TIMING_1, 0x40A0E05},
+	{DSI_PHY_TIMING_2, 0x30118},
+	{DSI_BTA_TIMING, 0x190A14},
+	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
+	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
+	{DSI_TO_TALLY, 0},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+	{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_MAX_THRESHOLD, 0x40},
+	{DSI_TRIGGER, 0},
+	{DSI_TX_CRC, 0},
+	{DSI_INIT_SEQ_CONTROL, 0}
 };
 
 //DSI config (if ver == 0x10).
 static const cfg_op_t _display_config_4[43] = {
-	{DSI_DSI_WR_DATA, 0x439},
-	{DSI_DSI_WR_DATA, 0x9483FFB9},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0xBD15},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x1939},
-	{DSI_DSI_WR_DATA, 0xAAAAAAD8},
-	{DSI_DSI_WR_DATA, 0xAAAAAAEB},
-	{DSI_DSI_WR_DATA, 0xAAEBAAAA},
-	{DSI_DSI_WR_DATA, 0xAAAAAAAA},
-	{DSI_DSI_WR_DATA, 0xAAAAAAEB},
-	{DSI_DSI_WR_DATA, 0xAAEBAAAA},
-	{DSI_DSI_WR_DATA, 0xAA},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x1BD15},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x2739},
-	{DSI_DSI_WR_DATA, 0xFFFFFFD8},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFF},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x2BD15},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0xF39},
-	{DSI_DSI_WR_DATA, 0xFFFFFFD8},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFFFF},
-	{DSI_DSI_WR_DATA, 0xFFFFFF},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0xBD15},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x6D915},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x439},
-	{DSI_DSI_WR_DATA, 0xB9},
-	{DSI_DSI_TRIGGER, 2}
+	{DSI_WR_DATA, 0x439},
+	{DSI_WR_DATA, 0x9483FFB9},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xBD15},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x1939},
+	{DSI_WR_DATA, 0xAAAAAAD8},
+	{DSI_WR_DATA, 0xAAAAAAEB},
+	{DSI_WR_DATA, 0xAAEBAAAA},
+	{DSI_WR_DATA, 0xAAAAAAAA},
+	{DSI_WR_DATA, 0xAAAAAAEB},
+	{DSI_WR_DATA, 0xAAEBAAAA},
+	{DSI_WR_DATA, 0xAA},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x1BD15},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2739},
+	{DSI_WR_DATA, 0xFFFFFFD8},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFF},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2BD15},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xF39},
+	{DSI_WR_DATA, 0xFFFFFFD8},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFFFF},
+	{DSI_WR_DATA, 0xFFFFFF},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xBD15},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x6D915},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x439},
+	{DSI_WR_DATA, 0xB9},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST}
 };
 
 //DSI config.
 static const cfg_op_t _display_config_5[21] = {
-	{0x4F, 0},
-	{0x3C, 0x6070601},
-	{0x3D, 0x40A0E05},
-	{0x3E, 0x30172},
-	{0x3F, 0x190A14},
-	{0x44, 0x20000A40},
-	{0x45, 0x5A2F2000},
-	{0x46, 0},
-	{0x23, 0x40000208},
-	{0x27, 0x40000308},
-	{0x2B, 0x40000308},
-	{0x25, 0x40000308},
-	{0x29, 0x3F3B2B08},
-	{0x2A, 0x2CC},
-	{0x2D, 0x3F3B2B08},
-	{0x2E, 0x2CC},
-	{0x34, 0xCE0000},
-	{0x35, 0x87001A2},
-	{0x36, 0x190},
-	{0x37, 0x190},
-	{0xF, 0},
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PHY_TIMING_0, 0x6070601},
+	{DSI_PHY_TIMING_1, 0x40A0E05},
+	{DSI_PHY_TIMING_2, 0x30172},
+	{DSI_BTA_TIMING, 0x190A14},
+	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
+	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
+	{DSI_TO_TALLY, 0},
+	{DSI_PKT_SEQ_0_LO, 0x40000208},
+	{DSI_PKT_SEQ_2_LO, 0x40000308},
+	{DSI_PKT_SEQ_4_LO, 0x40000308},
+	{DSI_PKT_SEQ_1_LO, 0x40000308},
+	{DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
+	{DSI_PKT_SEQ_3_HI, 0x2CC},
+	{DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
+	{DSI_PKT_SEQ_5_HI, 0x2CC},
+	{DSI_PKT_LEN_0_1, 0xCE0000},
+	{DSI_PKT_LEN_2_3, 0x87001A2},
+	{DSI_PKT_LEN_4_5, 0x190},
+	{DSI_PKT_LEN_6_7, 0x190},
+	{DSI_HOST_CONTROL, 0},
 };
 
 //Clock config.
 static const cfg_op_t _display_config_6[3] = {
 	{0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE
-	{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
-	{0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC
+	{0x36, 0x20},       //CLK_RST_CONTROLLER_PLLD_MISC1
+	{0x37, 0x2DFC00}    //CLK_RST_CONTROLLER_PLLD_MISC
 };
 
 //DSI config.
 static const cfg_op_t _display_config_7[10] = {
-	{0x13, 0},
-	{0x10, 0},
-	{0x11, 6},
-	{0x12, 0x1E0},
-	{DSI_DSI_POWER_CONTROL, 1},
-	{0x10, 0x103032},
-	{0xF, 0x33},
-	{0x10, 0x103032},
-	{0xF, 3},
-	{0xF, 0x23}
+	{DSI_TRIGGER, 0},
+	{DSI_CONTROL, 0},
+	{DSI_SOL_DELAY, 6},
+	{DSI_MAX_THRESHOLD, 0x1E0},
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+	{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
 };
 
 //MIPI CAL config.
@@ -289,10 +295,10 @@ static const cfg_op_t _display_config_8[6] = {
 
 //DSI config.
 static const cfg_op_t _display_config_9[4] = {
-	{0x4F, 0},
-	{0x50, 0},
-	{0x51, 0x3333},
-	{0x52, 0}
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PAD_CONTROL_2, 0},
+	{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
+	{DSI_PAD_CONTROL_4, 0}
 };
 
 //MIPI CAL config.
@@ -317,232 +323,240 @@ static const cfg_op_t _display_config_10[16] = {
 
 //Display A config.
 static const cfg_op_t _display_config_11[113] = {
-	{0x40, 0},
-	{0x42, 0x10},
-	{0x700, 0},
-	{0x42, 0x10},
-	{0x70E, 0},
-	{0x700, 0},
-	{0x42, 0x10},
-	{0x42, 0x10},
-	{0x611, 0xF0},
-	{0x612, 0x12A},
-	{0x613, 0},
-	{0x614, 0x198},
-	{0x615, 0x39B},
-	{0x616, 0x32F},
-	{0x617, 0x204},
-	{0x618, 0},
-	{0x42, 0x20},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x70E, 0},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x42, 0x20},
-	{0x611, 0xF0},
-	{0x612, 0x12A},
-	{0x613, 0},
-	{0x614, 0x198},
-	{0x615, 0x39B},
-	{0x616, 0x32F},
-	{0x617, 0x204},
-	{0x618, 0},
-	{0x42, 0x40},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x70E, 0},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x42, 0x40},
-	{0x611, 0xF0},
-	{0x612, 0x12A},
-	{0x613, 0},
-	{0x614, 0x198},
-	{0x615, 0x39B},
-	{0x616, 0x32F},
-	{0x617, 0x204},
-	{0x618, 0},
-	{0x42, 0x10},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x700, 0},
-	{0x430, 8},
-	{0x42F, 0},
-	{0x307, 0x1000000},
-	{0x309, 0},
+	{DC_CMD_STATE_ACCESS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_DV_CONTROL, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	/* Setup default YUV colorspace conversion coefficients */
+	{DC_WIN_CSC_YOF,   0xF0},
+	{DC_WIN_CSC_KYRGB, 0x12A},
+	{DC_WIN_CSC_KUR,   0},
+	{DC_WIN_CSC_KVR,   0x198},
+	{DC_WIN_CSC_KUG,   0x39B},
+	{DC_WIN_CSC_KVG,   0x32F},
+	{DC_WIN_CSC_KUB,   0x204},
+	{DC_WIN_CSC_KVB,   0},
+	/* End of color coefficients */
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_DV_CONTROL, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	/* Setup default YUV colorspace conversion coefficients */
+	{DC_WIN_CSC_YOF,   0xF0},
+	{DC_WIN_CSC_KYRGB, 0x12A},
+	{DC_WIN_CSC_KUR,   0},
+	{DC_WIN_CSC_KVR,   0x198},
+	{DC_WIN_CSC_KUG,   0x39B},
+	{DC_WIN_CSC_KVG,   0x32F},
+	{DC_WIN_CSC_KUB,   0x204},
+	{DC_WIN_CSC_KVB,   0},
+	/* End of color coefficients */
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_DV_CONTROL, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	/* Setup default YUV colorspace conversion coefficients */
+	{DC_WIN_CSC_YOF,   0xF0},
+	{DC_WIN_CSC_KYRGB, 0x12A},
+	{DC_WIN_CSC_KUR,   0},
+	{DC_WIN_CSC_KVR,   0x198},
+	{DC_WIN_CSC_KUG,   0x39B},
+	{DC_WIN_CSC_KVG,   0x32F},
+	{DC_WIN_CSC_KUB,   0x204},
+	{DC_WIN_CSC_KVB,   0},
+	/* End of color coefficients */
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
+	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
+	{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
+	{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
 	{0x4E4, 0},
-	{0x300, 0},
-	{DC_CMD_STATE_CONTROL, 0xF00},
-	{DC_CMD_STATE_CONTROL, 0xF},
-	{0x42, 0x10},
+	{DC_COM_CRC_CONTROL, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
 	{0x716, 0x10000FF},
-	{0x42, 0x20},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
 	{0x716, 0x10000FF},
-	{0x42, 0x40},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
 	{0x716, 0x10000FF},
-	{0x31, 0},
-	{0x42, 0x10},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x700, 0},
-	{0x402, 0},
-	{0x32, 0},
-	{DC_CMD_STATE_CONTROL, 0xF00},
-	{DC_CMD_STATE_CONTROL, 0xF},
-	{0x40, 0},
-	{0x405, 0},
-	{0x406, 0x10000},
-	{0x407, 0x10048},
-	{0x408, 0x90048},
-	{0x409, 0x50002D0},
-	{0x40A, 0xA0088},
-	{0x431, 0x10001},
-	{0x303, 0},
-	{0x432, 5},
-	{0x42F, 0},
-	{0x42E, 0},
-	{0x31, 0},
-	{0x42, 0x10},
-	{0x700, 0},
-	{0x42, 0x20},
-	{0x700, 0},
-	{0x42, 0x40},
-	{0x700, 0},
-	{0x402, 0},
-	{0x32, 0x20},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{0x40, 5},
-	{0x40A, 0xA0088},
-	{0x40, 0},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{0, 0x301},
-	{0, 0x301},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{0x40, 0},
-	{0x42E, 4},
-	{0x430, 8},
-	{0x31, 0}
+	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_COMMAND, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
+	{DC_CMD_STATE_ACCESS, 0},
+	/* Set Display timings */
+	{DC_DISP_DISP_TIMING_OPTIONS, 0},
+	{DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
+	{DC_DISP_SYNC_WIDTH,  0x10048},
+	{DC_DISP_BACK_PORCH,  0x90048},
+	{DC_DISP_ACTIVE,      0x50002D0},
+	{DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd.
+	/* End of Display timings */
+	{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
+	{DC_COM_PIN_OUTPUT_ENABLE(1), 0},
+	{DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
+	{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
+	{DC_DISP_DISP_CLOCK_CONTROL, 0},
+	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
+	{DC_DISP_FRONT_PORCH, 0xA0088},
+	{DC_CMD_STATE_ACCESS, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
+	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_STATE_ACCESS, 0},
+	{DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
+	{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
+	{DC_CMD_DISPLAY_COMMAND_OPTION0, 0}
 };
 
 ////Display A config.
 static const cfg_op_t _display_config_12[17] = {
-	{0x40A, 0xA0088},
-	{0x38, 0},
-	{0x40, 0},
-	{0x39, 0},
-	{0x28, 0},
-	{0x32, 0},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{0, 0x301},
-	{0, 0x301},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1},
-	{0x36, 0},
-	{DC_CMD_STATE_CONTROL, 0x100},
-	{DC_CMD_STATE_CONTROL, 1}
+	{DC_DISP_FRONT_PORCH, 0xA0088},
+	{DC_CMD_INT_MASK, 0},
+	{DC_CMD_STATE_ACCESS, 0},
+	{DC_CMD_INT_ENABLE, 0},
+	{DC_CMD_CONT_SYNCPT_VSYNC, 0},
+	{DC_CMD_DISPLAY_COMMAND, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
+	{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
+	{DC_CMD_DISPLAY_POWER_CONTROL, 0},
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
 };
 
 //DSI config.
 static const cfg_op_t _display_config_13[16] = {
-	{DSI_DSI_POWER_CONTROL, 0},
-	{0x4F, 0},
-	{0x3C, 0x6070601},
-	{0x3D, 0x40A0E05},
-	{0x3E, 0x30109},
-	{0x3F, 0x190A14},
-	{0x44, 0x2000FFFF},
-	{0x45, 0x7652000},
-	{0x46, 0},
-	{0xF, 0x102003},
-	{0x10, 0x31},
-	{DSI_DSI_POWER_CONTROL, 1},
-	{0x12, 0x40},
-	{0x13, 0},
-	{0x14, 0},
-	{0x1A, 0}
+	{DSI_POWER_CONTROL, 0},
+	{DSI_PAD_CONTROL_1, 0},
+	{DSI_PHY_TIMING_0, 0x6070601},
+	{DSI_PHY_TIMING_1, 0x40A0E05},
+	{DSI_PHY_TIMING_2, 0x30109},
+	{DSI_BTA_TIMING, 0x190A14},
+	{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
+	{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
+	{DSI_TO_TALLY, 0},
+	{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
+	{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
+	{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
+	{DSI_MAX_THRESHOLD, 0x40},
+	{DSI_TRIGGER, 0},
+	{DSI_TX_CRC, 0},
+	{DSI_INIT_SEQ_CONTROL, 0}
 };
 
 //DSI config (if ver == 0x10).
 static const cfg_op_t _display_config_14[22] = {
-	{DSI_DSI_WR_DATA, 0x439},
-	{DSI_DSI_WR_DATA, 0x9483FFB9},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x2139},
-	{DSI_DSI_WR_DATA, 0x191919D5},
-	{DSI_DSI_WR_DATA, 0x19191919},
-	{DSI_DSI_WR_DATA, 0x19191919},
-	{DSI_DSI_WR_DATA, 0x19191919},
-	{DSI_DSI_WR_DATA, 0x19191919},
-	{DSI_DSI_WR_DATA, 0x19191919},
-	{DSI_DSI_WR_DATA, 0x19191919},
-	{DSI_DSI_WR_DATA, 0x19191919},
-	{DSI_DSI_WR_DATA, 0x19},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0xB39},
-	{DSI_DSI_WR_DATA, 0x4F0F41B1},
-	{DSI_DSI_WR_DATA, 0xF179A433},
-	{DSI_DSI_WR_DATA, 0x2D81},
-	{DSI_DSI_TRIGGER, 2},
-	{DSI_DSI_WR_DATA, 0x439},
-	{DSI_DSI_WR_DATA, 0xB9},
-	{DSI_DSI_TRIGGER, 2}
+	{DSI_WR_DATA, 0x439},
+	{DSI_WR_DATA, 0x9483FFB9},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x2139},
+	{DSI_WR_DATA, 0x191919D5},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19191919},
+	{DSI_WR_DATA, 0x19},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0xB39},
+	{DSI_WR_DATA, 0x4F0F41B1},
+	{DSI_WR_DATA, 0xF179A433},
+	{DSI_WR_DATA, 0x2D81},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST},
+	{DSI_WR_DATA, 0x439},
+	{DSI_WR_DATA, 0xB9},
+	{DSI_TRIGGER, DSI_TRIGGER_HOST}
 };
 
 //Display A config.
 static const cfg_op_t cfg_display_one_color[8] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A.
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B.
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C.
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE
-	{DC_CMD_DISPLAY_COMMAND, 0x20} //DISPLAY_CTRL_MODE: continuous display.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display.
 };
 
 //Display A config.
 static const cfg_op_t cfg_display_framebuffer[32] = {
-	{DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C.
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B.
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A.
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE
-	{DC_X_WIN_XD_COLOR_DEPTH, 0xD}, //T_A8B8G8R8
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_X_WIN_XD_POSITION, 0}, //(0,0)
-	{DC_X_WIN_XD_H_INITIAL_DDA, 0},
-	{DC_X_WIN_XD_V_INITIAL_DDA, 0},
-	{DC_X_WIN_XD_PRESCALED_SIZE, 0x5000B40}, //Pre-scaled size: 1280x2880 bytes (= 0x500 vertical lines x 0xB40 bytes).
-	{DC_X_WIN_XD_DDA_INCREMENT, 0x10001000},
-	{DC_X_WIN_XD_SIZE, 0x50002D0}, //Window size: 1280x720 (= 0x500 vertical lines x 0x2D0 horizontal pixels).
-	{DC_X_WIN_XD_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
-	{0x702, 0},
-	{DC_X_WINBUF_XD_SURFACE_KIND, 0}, //Regular surface.
-	{DC_X_WINBUF_XD_START_ADDR, 0xC0000000}, //Framebuffer address.
-	{DC_X_WINBUF_XD_ADDR_H_OFFSET, 0},
-	{DC_X_WINBUF_XD_ADDR_V_OFFSET, 0},
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE
-	{DC_X_WIN_XD_WIN_OPTIONS, 0},
-	{DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE
-	{DC_X_WIN_XD_WIN_OPTIONS, 0x40000000}, //Enable window AD.
-	{DC_CMD_DISPLAY_COMMAND, 0x20}, //DISPLAY_CTRL_MODE: continuous display.
-	{DC_CMD_STATE_CONTROL, 0x300}, //General update; window A update.
-	{DC_CMD_STATE_CONTROL, 3} //General activation request; window A activation request.
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_R8G8B8A8}, //T_A8B8G8R8
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_WIN_POSITION, 0}, //(0,0)
+	{DC_WIN_H_INITIAL_DDA, 0},
+	{DC_WIN_V_INITIAL_DDA, 0},
+	{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes.
+	{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
+	{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels.
+	{DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
+	{DC_WIN_BUFFER_CONTROL, 0},
+	{DC_WINBUF_SURFACE_KIND, 0}, //Regular surface.
+	{DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address.
+	{DC_WINBUF_ADDR_H_OFFSET, 0},
+	{DC_WINBUF_ADDR_V_OFFSET, 0},
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_WIN_WIN_OPTIONS, 0},
+	{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
+	{DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD.
+	{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display.
+	{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update.
+	{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request.
 };

ipl/ff.c

@@ -26,7 +26,7 @@
 #include "gfx.h"
 extern gfx_ctxt_t gfx_ctxt;
 extern gfx_con_t gfx_con;
-#define EFSPRINTF(text, ...) gfx_printf(&gfx_con, "\n\n\n%k[FatFS] "text"%k\n", 0xFF00FFFF, 0xFFFFFFFF)
+#define EFSPRINTF(text, ...) gfx_printf(&gfx_con, "\n\n\n%k[FatFS] Error: "text"%k\n", 0xFF00FFFF, 0xFFFFFFFF)
 //#define EFSPRINTF(...)
 
 /*--------------------------------------------------------------------------
@@ -3259,7 +3259,7 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 		stat = disk_status(fs->pdrv);
 		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
 			if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
-				EFSPRINTF("Error: Write protected!");
+				EFSPRINTF("Write protected!");
 				return FR_WRITE_PROTECTED;
 			}
 			return FR_OK;				/* The filesystem object is valid */
@@ -3273,11 +3273,11 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 	fs->pdrv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
 	stat = disk_initialize(fs->pdrv);	/* Initialize the physical drive */
 	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
-		EFSPRINTF("Error: Medium not ready or hard error!");
+		EFSPRINTF("Medium not ready or hard error!");
 		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
 	}
 	if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
-		EFSPRINTF("Error: Write protected!");
+		EFSPRINTF("Write protected!");
 		return FR_WRITE_PROTECTED;
 	}
 #if FF_MAX_SS != FF_MIN_SS				/* Get sector size (multiple sector size cfg only) */
@@ -3301,11 +3301,11 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
 	}
 	if (fmt == 4) {
-		EFSPRINTF("Error: Disk I/O error - Could not load boot record!");
+		EFSPRINTF("Disk I/O error - Could not load boot record!");
 		return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
 	}
 	if (fmt >= 2) {
-		EFSPRINTF("Error: No FAT/FAT32/exFAT filesystem found!");
+		EFSPRINTF("No FAT/FAT32/exFAT filesystem found!");
 		return FR_NO_FILESYSTEM;	/* No FAT volume is found */
 	}
 
@@ -3316,21 +3316,24 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 		QWORD maxlba;
 
 		for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ;	/* Check zero filler */
-		if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+		if (i < BPB_ZeroedEx + 53) {
+			EFSPRINTF("exFAT - Zero filler check failed!");
+			return FR_NO_FILESYSTEM;
+		}
 
 		if (ld_word(fs->win + BPB_FSVerEx) != 0x100) {
-			EFSPRINTF("Error: exFAT - Version check failed!");
+			EFSPRINTF("exFAT - Version check failed!");
 			return FR_NO_FILESYSTEM;	/* Check exFAT version (must be version 1.0) */
 		}
 
 		if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) {	/* (BPB_BytsPerSecEx must be equal to the physical sector size) */
-			EFSPRINTF("Error: exFAT - Bytes per sector does not match physical sector size!");
+			EFSPRINTF("exFAT - Bytes per sector does not match physical sector size!");
 			return FR_NO_FILESYSTEM;
 		}
 
 		maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect;	/* Last LBA + 1 of the volume */
 		if (maxlba >= 0x100000000) {
-			EFSPRINTF("Error: exFAT - Cannot handle volume LBA with 32-bit LBA!");
+			EFSPRINTF("exFAT - Cannot handle volume LBA with 32-bit LBA!");
 			return FR_NO_FILESYSTEM;	/* (It cannot be handled in 32-bit LBA) */
 		}
 
@@ -3338,19 +3341,19 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 
 		fs->n_fats = fs->win[BPB_NumFATsEx];			/* Number of FATs */
 		if (fs->n_fats != 1) {
-			EFSPRINTF("Error: exFAT - Multiple or no file allocation tables found!");
+			EFSPRINTF("exFAT - Multiple or no file allocation tables found!");
 			return FR_NO_FILESYSTEM;	/* (Supports only 1 FAT) */
 		}
 
 		fs->csize = 1 << fs->win[BPB_SecPerClusEx];		/* Cluster size */
 		if (fs->csize == 0)	{
-			EFSPRINTF("Error: exFAT - Cluster size is not between 1KB - 32KB!");
+			EFSPRINTF("exFAT - Cluster size is not between 1KB - 32KB!");
 			return FR_NO_FILESYSTEM;	/* (Must be 1..32768) */
 		}
 
 		nclst = ld_dword(fs->win + BPB_NumClusEx);		/* Number of clusters */
 		if (nclst > MAX_EXFAT) {
-			EFSPRINTF("Error: exFAT - Total clusters exceed allowed!");
+			EFSPRINTF("exFAT - Total clusters exceed allowed!");
 			return FR_NO_FILESYSTEM;	/* (Too many clusters) */
 		}
 		fs->n_fatent = nclst + 2;
@@ -3360,20 +3363,23 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 		fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
 		fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
 		if (maxlba < (QWORD)fs->database + nclst * fs->csize) {
-			EFSPRINTF("Error: exFAT - Volume size is lower than required!");
+			EFSPRINTF("exFAT - Volume size is lower than required!");
 			return FR_NO_FILESYSTEM;	/* (Volume size must not be smaller than the size required) */
 		}
 		fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
 
 		/* Check if bitmap location is in assumption (at the first cluster) */
 		if (move_window(fs, clst2sect(fs, fs->dirbase)) != FR_OK) {
-			EFSPRINTF("Error: exFAT - Bitmap location not at first cluster!");
+			EFSPRINTF("exFAT - Bitmap location not at first cluster!");
 			return FR_DISK_ERR;
 		}
 		for (i = 0; i < SS(fs); i += SZDIRE) {
 			if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break;	/* 81 entry with cluster #2? */
 		}
-		if (i == SS(fs)) return FR_NO_FILESYSTEM;
+		if (i == SS(fs)) {
+			EFSPRINTF("exFAT - Bitmap allocation is missing!");
+			return FR_NO_FILESYSTEM;
+		}
 #if !FF_FS_READONLY
 		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
 #endif
@@ -3382,7 +3388,7 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 #endif	/* FF_FS_EXFAT */
 	{
 		if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) {
-			EFSPRINTF("Error: FAT - Bytes per sector does not match physical sector size!");
+			EFSPRINTF("FAT - Bytes per sector does not match physical sector size!");
 			return FR_NO_FILESYSTEM;	/* (BPB_BytsPerSec must be equal to the physical sector size) */
 		}
 
@@ -3392,20 +3398,20 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 
 		fs->n_fats = fs->win[BPB_NumFATs];				/* Number of FATs */
 		if (fs->n_fats != 1 && fs->n_fats != 2) {
-			EFSPRINTF("Error: FAT - No or more than 2 file allocation tables found!");
+			EFSPRINTF("FAT - No or more than 2 file allocation tables found!");
 			return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
 		}
 		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
 
 		fs->csize = fs->win[BPB_SecPerClus];			/* Cluster size */
 		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) {
-			EFSPRINTF("Error: FAT - Cluster size is not a power of 2!");
+			EFSPRINTF("FAT - Cluster size is not a power of 2!");
 			return FR_NO_FILESYSTEM;	/* (Must be power of 2) */
 		}
 
 		fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
 		if (fs->n_rootdir % (SS(fs) / SZDIRE)) {
-			EFSPRINTF("Error: FAT - Root directory entries are not sector aligned!");
+			EFSPRINTF("FAT - Root directory entries are not sector aligned!");
 			return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
 		}
 
@@ -3414,19 +3420,19 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 
 		nrsv = ld_word(fs->win + BPB_RsvdSecCnt);		/* Number of reserved sectors */
 		if (nrsv == 0) {
-			EFSPRINTF("Error: FAT - Zero reserved sectors!");
+			EFSPRINTF("FAT - Zero reserved sectors!");
 			return FR_NO_FILESYSTEM;			/* (Must not be 0) */
 		}
 
 		/* Determine the FAT sub type */
 		sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE);	/* RSV + FAT + DIR */
 		if (tsect < sysect) {
-			EFSPRINTF("Error: FAT - Invalid volume size!");
+			EFSPRINTF("FAT - Invalid volume size!");
 			return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
 		}
 		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
 		if (nclst == 0) {
-			EFSPRINTF("Error: FAT - Invalid volume size!");
+			EFSPRINTF("FAT - Invalid volume size!");
 			return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
 		}
 		fmt = 0;
@@ -3434,7 +3440,7 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
 		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
 		if (fmt == 0) {
-			EFSPRINTF("Error: FAT - Not compatible FAT12/16/32 filesystem!");
+			EFSPRINTF("FAT - Not compatible FAT12/16/32 filesystem!");
 			return FR_NO_FILESYSTEM;
 		}
 
@@ -3445,18 +3451,18 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 		fs->database = bsect + sysect;					/* Data start sector */
 		if (fmt == FS_FAT32) {
 			if (ld_word(fs->win + BPB_FSVer32) != 0) {
-				EFSPRINTF("Error: FAT32 - Not a 0.0 revision!");
+				EFSPRINTF("FAT32 - Not a 0.0 revision!");
 				return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0) */
 			}
 			if (fs->n_rootdir != 0) {
-				EFSPRINTF("Error: FAT32 - Root entry sector is not 0!");
+				EFSPRINTF("FAT32 - Root entry sector is not 0!");
 				return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
 			}
 			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
 			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
 		} else {
 			if (fs->n_rootdir == 0)	{
-				EFSPRINTF("Error: FAT - Root entry sector is 0!");
+				EFSPRINTF("FAT - Root entry sector is 0!");
 				return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must not be 0) */
 			}
 			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
@@ -3464,7 +3470,7 @@ FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
 				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
 		}
 		if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) {
-			EFSPRINTF("Error: FAT - FAT size is not the required size!");
+			EFSPRINTF("FAT - FAT size is not the required size!");
 			return FR_NO_FILESYSTEM;	/* (BPB_FATSz must not be less than the size needed) */
 		}
 
@@ -3578,7 +3584,7 @@ FRESULT f_mount (
 	/* Get logical drive number */
 	vol = get_ldnumber(&rp);
 	if (vol < 0) {
-		EFSPRINTF("Error: Invalid drive!");
+		EFSPRINTF("Invalid drive!");
 		return FR_INVALID_DRIVE;
 	}
 	cfs = FatFs[vol];					/* Pointer to fs object */
@@ -3822,11 +3828,11 @@ FRESULT f_read (
 	*br = 0;	/* Clear read byte counter */
 	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
-		EFSPRINTF("Error: File object Validation!");
+		EFSPRINTF("File object Validation!");
 		LEAVE_FF(fs, res);	/* Check validity */
 	}
 	if (!(fp->flag & FA_READ)) {
-		EFSPRINTF("Error: Access denied!");
+		EFSPRINTF("Access denied!");
 		LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
 	}
 	remain = fp->obj.objsize - fp->fptr;
@@ -3850,18 +3856,18 @@ FRESULT f_read (
 					}
 				}
 				if (clst < 2) {
-					EFSPRINTF("Error: Cluster status check or Internal error!");
+					EFSPRINTF("Cluster status check or Internal error!");
 					ABORT(fs, FR_INT_ERR);
 				}
 				if (clst == 0xFFFFFFFF) {
-					EFSPRINTF("Error: Disk error (cluster hard error)!");
+					EFSPRINTF("Disk error (cluster hard error)!");
 					ABORT(fs, FR_DISK_ERR);
 				}
 				fp->clust = clst;				/* Update current cluster */
 			}
 			sect = clst2sect(fs, fp->clust);	/* Get current sector */
 			if (sect == 0) {
-				EFSPRINTF("Error: Get current sector error!");
+				EFSPRINTF("Get current sector error!");
 				ABORT(fs, FR_INT_ERR);
 			}
 			sect += csect;
@@ -3871,7 +3877,7 @@ FRESULT f_read (
 					cc = fs->csize - csect;
 				}
 				if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) {
-					EFSPRINTF("Error: Read - Low level disk I/O!");
+					EFSPRINTF("Read - Low level disk I/O!");
 					ABORT(fs, FR_DISK_ERR);
 				}
 #if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2		/* Replace one of the read sectors with cached data if it contains a dirty sector */
@@ -3893,14 +3899,14 @@ FRESULT f_read (
 #if !FF_FS_READONLY
 				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
 					if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) {
-						EFSPRINTF("Error: Write-back dirty sector cache!");
+						EFSPRINTF("Write-back dirty sector cache!");
 						ABORT(fs, FR_DISK_ERR);
 					}
 					fp->flag &= (BYTE)~FA_DIRTY;
 				}
 #endif
 				if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) {
-					EFSPRINTF("Error: Read - Low level disk I/O!\n(fill sector cache)");
+					EFSPRINTF("Read - Low level disk I/O!\n(fill sector cache)");
 					ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
 				}
 			}
@@ -3945,11 +3951,11 @@ FRESULT f_write (
 	*bw = 0;	/* Clear write byte counter */
 	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
 	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
-		EFSPRINTF("Error: File object Validation!");
+		EFSPRINTF("File object Validation!");
 		LEAVE_FF(fs, res);	/* Check validity */
 	}
 	if (!(fp->flag & FA_WRITE)) {
-		EFSPRINTF("Error: Access denied!");
+		EFSPRINTF("Access denied!");
 		LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
 	}
 
@@ -3979,15 +3985,15 @@ FRESULT f_write (
 					}
 				}
 				if (clst == 0) {
-					EFSPRINTF("Error: Could not allocate a new cluster\n(disk full or low level disk I/O error)!");
+					EFSPRINTF("Could not allocate a new cluster\n(disk full or low level disk I/O error)!");
 					break;		/* Could not allocate a new cluster (disk full) */
 				}
 				if (clst == 1) {
-					EFSPRINTF("Error: Cluster status check or Internal error!");
+					EFSPRINTF("Cluster status check or Internal error!");
 					ABORT(fs, FR_INT_ERR);
 				}
 				if (clst == 0xFFFFFFFF) {
-					EFSPRINTF("Error: Disk error (cluster hard error)!");
+					EFSPRINTF("Disk error (cluster hard error)!");
 					ABORT(fs, FR_DISK_ERR);
 				}
 				fp->clust = clst;			/* Update current cluster */
@@ -3998,7 +4004,7 @@ FRESULT f_write (
 #else
 			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
 				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) {
-					EFSPRINTF("Error: Write-back sector cache!");
+					EFSPRINTF("Write-back sector cache!");
 					ABORT(fs, FR_DISK_ERR);
 				}
 				fp->flag &= (BYTE)~FA_DIRTY;
@@ -4006,7 +4012,7 @@ FRESULT f_write (
 #endif
 			sect = clst2sect(fs, fp->clust);	/* Get current sector */
 			if (sect == 0) {
-				EFSPRINTF("Error: Get current sector error!");
+				EFSPRINTF("Get current sector error!");
 				ABORT(fs, FR_INT_ERR);
 			}
 			sect += csect;
@@ -4016,7 +4022,7 @@ FRESULT f_write (
 					cc = fs->csize - csect;
 				}
 				if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) {
-					EFSPRINTF("Error: Write - Low level disk I/O!");
+					EFSPRINTF("Write - Low level disk I/O!");
 					ABORT(fs, FR_DISK_ERR);
 				}
 #if FF_FS_MINIMIZE <= 2
@@ -4044,7 +4050,7 @@ FRESULT f_write (
 			if (fp->sect != sect && 		/* Fill sector cache with file data */
 				fp->fptr < fp->obj.objsize &&
 				disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) {
-					EFSPRINTF("Error: Read - Low level disk I/O!\n(Could not fill sector cache with file data)");
+					EFSPRINTF("Read - Low level disk I/O!\n(Could not fill sector cache with file data)");
 					ABORT(fs, FR_DISK_ERR);
 			}
 #endif

ipl/gfx.c

@@ -299,7 +299,7 @@ void gfx_hexdump(gfx_con_t *con, u32 base, const u8 *buf, u32 len)
 				for(u32 j = 0; j < 0x10; j++)
 				{
 					u8 c = buf[i - 0x10 + j];
-					if(c >= 32 && c < 128)
+					if(c >= 32 && c <= 126)
 						gfx_putc(con, c);
 					else
 						gfx_putc(con, '.');
@@ -309,6 +309,27 @@ void gfx_hexdump(gfx_con_t *con, u32 base, const u8 *buf, u32 len)
 			gfx_printf(con, "%08x: ", base + i);
 		}
 		gfx_printf(con, "%02x ", buf[i]);
+		if (i == len - 1)
+		{
+			int ln = len % 0x10 != 0;
+			u32 k = 0x10 - 1;
+			if (ln)
+			{
+				k = len & 0xF - 1;
+				for (u32 j = 0; j < 0x10 - k; j++)
+					gfx_puts(con, "   ");
+			}
+			gfx_puts(con, "| ");
+			for(u32 j = 0; j < (ln ? k : k + 1); j++)
+			{
+				u8 c = buf[i - k + j];
+				if(c >= 32 && c <= 126)
+					gfx_putc(con, c);
+				else
+					gfx_putc(con, '.');
+			}
+			gfx_putc(con, '\n');
+		}
 	}
 	gfx_putc(con, '\n');
 	gfx_con_setfontsz(con, prevFontSize);

ipl/hos.c

@@ -35,8 +35,8 @@
 #include "gfx.h"
 extern gfx_ctxt_t gfx_ctxt;
 extern gfx_con_t gfx_con;
-#define DPRINTF(...) gfx_printf(&gfx_con, __VA_ARGS__)
-//#define DPRINTF(...)
+//#define DPRINTF(...) gfx_printf(&gfx_con, __VA_ARGS__)
+#define DPRINTF(...)
 
 enum KB_FIRMWARE_VERSION {
 	KB_FIRMWARE_VERSION_100_200 = 0,
@@ -190,6 +190,9 @@ typedef struct _launch_ctxt_t
 	void *kernel;
 	u32 kernel_size;
 	link_t kip1_list;
+
+	u8 *svcperm;
+	u8 *debugmode;
 } launch_ctxt_t;
 
 typedef struct _merge_kip_t
@@ -213,10 +216,10 @@ static int _read_emmc_pkg1(launch_ctxt_t *ctxt)
 	ctxt->pkg1_id = pkg1_identify(ctxt->pkg1);
 	if (!ctxt->pkg1_id)
 	{
-		DPRINTF("%kCould not identify package1,\nversion (= '%s').%k\n", 0xFF0000FF, (char *)ctxt->pkg1 + 0x10, 0xFFFFFFFF);
+		gfx_printf(&gfx_con, "%kCould not identify package1,\nVersion (= '%s').%k\n", 0xFF0000FF, (char *)ctxt->pkg1 + 0x10, 0xFFFFFFFF);
 		goto out;
 	}
-	DPRINTF("Identified package1 ('%s'),\nkeyblob version %d\n", (char *)(ctxt->pkg1 + 0x10), ctxt->pkg1_id->kb);
+	gfx_printf(&gfx_con, "Identified package1 ('%s'),\nKeyblob version %d\n\n", (char *)(ctxt->pkg1 + 0x10), ctxt->pkg1_id->kb);
 
 	//Read the correct keyblob.
 	ctxt->keyblob = (u8 *)malloc(NX_EMMC_BLOCKSIZE);
@@ -241,7 +244,7 @@ static int _read_emmc_pkg2(launch_ctxt_t *ctxt)
 	//Parse eMMC GPT.
 	LIST_INIT(gpt);
 	nx_emmc_gpt_parse(&gpt, &storage);
-DPRINTF("parsed GPT\n");
+	DPRINTF("Parsed GPT\n");
 	//Find package2 partition.
 	emmc_part_t *pkg2_part = nx_emmc_part_find(&gpt, "BCPKG2-1-Normal-Main");
 	if (!pkg2_part)
@@ -254,10 +257,10 @@ DPRINTF("parsed GPT\n");
 	u32 *hdr = (u32 *)(tmp + 0x100);
 	u32 pkg2_size = hdr[0] ^ hdr[2] ^ hdr[3];
 	free(tmp);
-DPRINTF("pkg2 size on emmc is %08X\n", pkg2_size);
+	DPRINTF("pkg2 size on emmc is %08X\n", pkg2_size);
 	//Read in package2.
 	u32 pkg2_size_aligned = ALIGN(pkg2_size, NX_EMMC_BLOCKSIZE);
-DPRINTF("pkg2 size aligned is %08X\n", pkg2_size_aligned);
+	DPRINTF("pkg2 size aligned is %08X\n", pkg2_size_aligned);
 	ctxt->pkg2 = malloc(pkg2_size_aligned);
 	ctxt->pkg2_size = pkg2_size;
 	nx_emmc_part_read(&storage, pkg2_part, 0x4000 / NX_EMMC_BLOCKSIZE, 
@@ -315,12 +318,32 @@ static int _config_kip1(launch_ctxt_t *ctxt, const char *value)
 	merge_kip_t *mkip1 = (merge_kip_t *)malloc(sizeof(merge_kip_t));
 	mkip1->kip1 = malloc(f_size(&fp));
 	f_read(&fp, mkip1->kip1, f_size(&fp), NULL);
-DPRINTF("loaded kip from SD (size %08X)\n", f_size(&fp));
+	DPRINTF("Loaded kip1 from SD (size %08X)\n", f_size(&fp));
 	f_close(&fp);
 	list_append(&ctxt->kip1_list, &mkip1->link);
 	return 1;
 }
 
+static int _config_svcperm(launch_ctxt_t *ctxt, const char *value)
+{
+	if (*(u8 *)value == '1')
+	{
+		DPRINTF("Disabled SVC verification\n");
+		ctxt->svcperm = malloc(1);
+	}
+		
+	return 1;
+}
+
+static int _config_debugmode(launch_ctxt_t *ctxt, const char *value)
+{
+	if (*(u8 *)value == '1')
+	{
+		DPRINTF("Enabled Debug mode\n");
+		ctxt->debugmode = malloc(1);
+	}
+}
+
 typedef struct _cfg_handler_t
 {
 	const char *key;
@@ -332,6 +355,8 @@ static const cfg_handler_t _config_handlers[] = {
 	{ "secmon", _config_secmon },
 	{ "kernel", _config_kernel },
 	{ "kip1", _config_kip1 },
+	{ "fullsvcperm", _config_svcperm },
+	{ "debugmode", _config_debugmode },
 	{ NULL, NULL },
 };
 
@@ -347,6 +372,8 @@ static int _config(launch_ctxt_t *ctxt, ini_sec_t *cfg)
 
 int hos_launch(ini_sec_t *cfg)
 {
+	int bootStatePackage2;
+	int bootStateContinue;
 	launch_ctxt_t ctxt;
 	memset(&ctxt, 0, sizeof(launch_ctxt_t));
 	list_init(&ctxt.kip1_list);
@@ -358,14 +385,10 @@ int hos_launch(ini_sec_t *cfg)
 	if (!_read_emmc_pkg1(&ctxt))
 		return 0;
 
-	//XXX: remove this once we support 3+.
-	//if (ctxt.pkg1_id->kb > 0)
-	//	return 0;
-
-DPRINTF("loaded pkg1 and keyblob\n");
+	gfx_printf(&gfx_con, "Loaded package1 and keyblob\n");
 	//Generate keys.
 	keygen(ctxt.keyblob, ctxt.pkg1_id->kb, (u8 *)ctxt.pkg1 + ctxt.pkg1_id->tsec_off);
-DPRINTF("generated keys\n");
+	DPRINTF("Generated keys\n");
 	//Decrypt and unpack package1 if we require parts of it.
 	if (!ctxt.warmboot || !ctxt.secmon)
 	{
@@ -373,7 +396,7 @@ DPRINTF("generated keys\n");
 		pkg1_unpack((void *)0x8000D000, (void *)ctxt.pkg1_id->secmon_base, ctxt.pkg1_id, ctxt.pkg1);
 		//gfx_hexdump(&gfx_con, 0x8000D000, (void *)0x8000D000, 0x100);
 		//gfx_hexdump(&gfx_con, ctxt.pkg1_id->secmon_base, (void *)ctxt.pkg1_id->secmon_base, 0x100);
-DPRINTF("decrypted and unpacked pkg1\n");
+		gfx_printf(&gfx_con, "Decrypted and unpacked package1\n");
 	}
 	//Replace 'warmboot.bin' if requested.
 	if (ctxt.warmboot)
@@ -388,67 +411,89 @@ DPRINTF("decrypted and unpacked pkg1\n");
 	{
 		//Else we patch it to allow for an unsigned package2.
 		patch_t *secmon_patchset = ctxt.pkg1_id->secmon_patchset;
+		//In case a kernel patch option is set. Allows to disable Svc Verififcation or/and enable Debug mode
+		patch_t *kernel_patchset = ctxt.pkg1_id->kernel_patchset;
 		
-		if (secmon_patchset != NULL) {
-			for (u32 i = 0; secmon_patchset[i].off != 0xFFFFFFFF; i++)
-				*(vu32 *)(ctxt.pkg1_id->secmon_base + secmon_patchset[i].off) = secmon_patchset[i].val;
+		if (secmon_patchset != NULL || (kernel_patchset != NULL && (ctxt.svcperm || ctxt.debugmode))) {
+			if (secmon_patchset != NULL)
+			{
+				gfx_printf(&gfx_con, "%kPatching Security Monitor%k\n", 0xFF00BAFF, 0xFFCCCCCC);
+				for (u32 i = 0; secmon_patchset[i].off != 0xFFFFFFFF; i++)
+					*(vu32 *)(ctxt.pkg1_id->secmon_base + secmon_patchset[i].off) = secmon_patchset[i].val;
+			}
 
-			DPRINTF("loaded warmboot.bin and secmon\n");
+			gfx_printf(&gfx_con, "Loaded warmboot.bin and secmon\n");
 			
 			//Read package2.
 			if (!_read_emmc_pkg2(&ctxt))
 				return 0;
 
-			DPRINTF("read pkg2\n");
+			gfx_printf(&gfx_con, "Read package2\n");
 			//Decrypt package2 and parse KIP1 blobs in INI1 section.
 			pkg2_hdr_t *pkg2_hdr = pkg2_decrypt(ctxt.pkg2);
 
 			LIST_INIT(kip1_info);
 			pkg2_parse_kips(&kip1_info, pkg2_hdr);
 
-			DPRINTF("parsed ini1\n");
+			gfx_printf(&gfx_con, "Parsed ini1\n");
 			
 			//Use the kernel included in package2 in case we didn't load one already.
 			if (!ctxt.kernel)
 			{
 				ctxt.kernel = pkg2_hdr->data;
 				ctxt.kernel_size = pkg2_hdr->sec_size[PKG2_SEC_KERNEL];
+
+				if (kernel_patchset != NULL && (ctxt.svcperm || ctxt.debugmode))
+				{
+					gfx_printf(&gfx_con, "%kPatching kernel%k\n", 0xFF00BAFF, 0xFFCCCCCC);
+					if (ctxt.svcperm && kernel_patchset[0].off != 0xFFFFFFFF)
+						*(vu32 *)(ctxt.kernel + kernel_patchset[0].off) = kernel_patchset[0].val;
+					if (ctxt.debugmode && kernel_patchset[1].off != 0xFFFFFFFF)
+						*(vu32 *)(ctxt.kernel + kernel_patchset[1].off) = kernel_patchset[1].val;
+				}
 			}
 
 			//Merge extra KIP1s into loaded ones.
+			gfx_printf(&gfx_con, "%kPatching kernel initial processes%k\n", 0xFF00BAFF, 0xFFCCCCCC);
 			LIST_FOREACH_ENTRY(merge_kip_t, mki, &ctxt.kip1_list, link)
 				pkg2_merge_kip(&kip1_info, (pkg2_kip1_t *)mki->kip1);
 
 			//Rebuild and encrypt package2.
 			pkg2_build_encrypt((void *)0xA9800000, ctxt.kernel, ctxt.kernel_size, &kip1_info);
-			DPRINTF("rebuilt pkg2\n");
+			gfx_printf(&gfx_con, "Rebuilt and loaded package2\n");
 		} else {
 			//Read package2.
 			if (!_read_emmc_pkg2(&ctxt))
 				return 0;
 
-			DPRINTF("read pkg2\n");
+			gfx_printf(&gfx_con, "Loaded package2\n");
 			memcpy((void *)0xA9800000, ctxt.pkg2, ctxt.pkg2_size);
 		}
 	}
+    // Unmount SD Card
+	f_mount(NULL, "", 1);
+
+	gfx_printf(&gfx_con, "\n%kBooting...%k\n", 0xFF00FF96, 0xFFCCCCCC);
 
 	se_aes_key_clear(0x8);
 	se_aes_key_clear(0xB);
-	
+
 	switch (ctxt.pkg1_id->kb) {
 		case KB_FIRMWARE_VERSION_100_200:
 		case KB_FIRMWARE_VERSION_300:
 		case KB_FIRMWARE_VERSION_301:
 			se_key_acc_ctrl(0xC, 0xFF);
 			se_key_acc_ctrl(0xD, 0xFF);
+			bootStatePackage2 = 2;
+			bootStateContinue = 3;
 			break;
 		default:
 		case KB_FIRMWARE_VERSION_400:
 		case KB_FIRMWARE_VERSION_500:
 			se_key_acc_ctrl(0xC, 0xFF);
-			//se_key_acc_ctrl(0xD, 0xFF);
-			//se_key_acc_ctrl(0xE, 0xFF);
 			se_key_acc_ctrl(0xF, 0xFF);
+			bootStatePackage2 = 3;
+			bootStateContinue = 4;
 			break;
 	}
 
@@ -466,7 +511,7 @@ DPRINTF("decrypted and unpacked pkg1\n");
 	vu32 *mb_in = (vu32 *)0x40002EF8;
 	vu32 *mb_out = (vu32 *)0x40002EFC;
 
-	*mb_in = 0;
+	*mb_in = bootStatePackage2;
 	*mb_out = 0;
 
 	//Wait for secmon to get ready.
@@ -475,14 +520,8 @@ DPRINTF("decrypted and unpacked pkg1\n");
 		sleep(1);
 
 	//Signal 'BootConfig'.
-	*mb_in = 1;
-	sleep(100);
-
-	//Signal package2 available.
-	*mb_in = 2;
-	sleep(100);
-	*mb_in = 3;
-	sleep(100);
+	//*mb_in = 1;
+	//sleep(100);
 
 	/*PMC(0x4) = 0x7FFFF3;
 	PMC(0x2C4) = 0xFFFFFFFF;
@@ -497,8 +536,7 @@ DPRINTF("decrypted and unpacked pkg1\n");
 	//display_end();
 
 	//Signal to continue boot.
-	*mb_in = 4;
-	sleep(100);
+	*mb_in = bootStateContinue;
 
 	//Halt ourselves in waitevent state.
 	while (1)

ipl/main.c

@@ -38,6 +38,7 @@
 #include "gpio.h"
 #include "sdmmc.h"
 #include "ff.h"
+#include "ctc_logo2.h"
 #include "tui.h"
 #include "heap.h"
 #include "list.h"
@@ -47,6 +48,7 @@
 #include "hos.h"
 #include "pkg1.h"
 #include "mmc.h"
+#include "lz.h"
 
 //TODO: ugly.
 gfx_ctxt_t gfx_ctxt;
@@ -61,6 +63,7 @@ sdmmc_t sd_sdmmc;
 sdmmc_storage_t sd_storage;
 FATFS sd_fs;
 int sd_mounted;
+u8 *Kc_HEKATE_LOGO;
 
 int sd_mount()
 {
@@ -649,12 +652,14 @@ out:;
 void reboot_normal()
 {
 	sd_unmount();
+	free(Kc_HEKATE_LOGO);
 	panic(0x21); //Bypass fuse programming in package1.
 }
 
 void reboot_rcm()
 {
 	sd_unmount();
+	free(Kc_HEKATE_LOGO);
 	PMC(APBDEV_PMC_SCRATCH0) = 2; //Reboot into rcm.
 	PMC(0) |= 0x10;
 	while (1)
@@ -664,10 +669,90 @@ void reboot_rcm()
 void power_off()
 {
 	sd_unmount();
+	free(Kc_HEKATE_LOGO);
 	//TODO: we should probably make sure all regulators are powered off properly.
 	i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
 }
 
+int dump_emmc_verify(sdmmc_storage_t *storage, u32 lba_curr, char* outFilename, u32 NUM_SECTORS_PER_ITER, emmc_part_t *part)
+{
+	FIL fp;
+	u32 prevPct = 200;
+
+	if (f_open(&fp, outFilename, FA_READ) == FR_OK)
+	{
+		u8 *bufEm = (u8 *)malloc(NX_EMMC_BLOCKSIZE * NUM_SECTORS_PER_ITER);
+		u8 *bufSd = (u8 *)malloc(NX_EMMC_BLOCKSIZE * NUM_SECTORS_PER_ITER);
+
+		u32 totalSectorsVer = (u32)(f_size(&fp) >> 9);
+		u32 lbaCurrVer = lba_curr - totalSectorsVer;
+
+		u32 pct = (u64)((u64)(lbaCurrVer - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start);
+		tui_pbar(&gfx_con, 0, gfx_con.y, pct, 0xFF00FF96, 0xFF005515);
+
+		while (totalSectorsVer > 0)
+		{
+			u32 num = MIN(totalSectorsVer, NUM_SECTORS_PER_ITER);
+
+			if(!sdmmc_storage_read(storage, lbaCurrVer, num, bufEm))
+			{
+				gfx_con_setfontsz(&gfx_con, 16);
+				EPRINTFARGS("\nFailed to read %d blocks @ LBA %08X\nfrom eMMC. Aborting..\n",
+				num, lbaCurrVer);
+
+				free(bufEm);
+				free(bufSd);
+				f_close(&fp);
+				return 1;
+			}
+			if (!(f_read(&fp, bufSd, num, NULL) == FR_OK))
+			{
+				gfx_con_setfontsz(&gfx_con, 16);
+				EPRINTFARGS("\nFailed to read %d blocks from sd card.\nVerification failed..\n", num);
+
+				free(bufEm);
+				free(bufSd);
+				f_close(&fp);
+				return 1;
+			}
+
+			if(!memcmp(bufEm, bufSd, num << 9))
+			{
+				gfx_con_setfontsz(&gfx_con, 16);
+				EPRINTFARGS("\nVerification failed.\nVerification failed..\n", num);
+
+				free(bufEm);
+				free(bufSd);
+				f_close(&fp);
+				return 1;
+			}
+
+			pct = (u64)((u64)(lbaCurrVer - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start);
+			if (pct != prevPct)
+			{
+				tui_pbar(&gfx_con, 0, gfx_con.y, pct, 0xFF00FF96, 0xFF005515);
+				prevPct = pct;
+			}
+
+			lbaCurrVer += num;
+			totalSectorsVer -= num;
+		}
+		free(bufEm);
+		free(bufSd);
+		f_close(&fp);
+
+		tui_pbar(&gfx_con, 0, gfx_con.y, pct, 0xFFCCCCCC, 0xFF555555);
+
+		return 0;
+	}
+	else
+	{
+		gfx_con_setfontsz(&gfx_con, 16);
+		EPRINTF("\nFile not found or could not be loaded.\nVerification failed..\n");
+		return 1;
+	}
+}
+
 int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
 {
 	static const u32 FAT32_FILESIZE_LIMIT = 0xFFFFFFFF;
@@ -807,6 +892,15 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
 			memset(&fp, 0, sizeof(fp));
 			currPartIdx++;
 
+			// Verify part
+			if (dump_emmc_verify(storage, lba_curr, outFilename, NUM_SECTORS_PER_ITER, part))
+			{
+				EPRINTF("\nPress any key and try again.\n");
+
+				free(buf);
+				return 0;
+			}
+
 			if (numSplitParts >= 10 && currPartIdx < 10)
 			{
 				outFilename[sdPathLen] = '0';
@@ -894,7 +988,7 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
 		u32 pct = (u64)((u64)(lba_curr - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start);
 		if (pct != prevPct)
 		{
-			tui_pbar(&gfx_con, 0, gfx_con.y, pct);
+			tui_pbar(&gfx_con, 0, gfx_con.y, pct, 0xFFCCCCCC, 0xFF555555);
 			prevPct = pct;
 		}
 
@@ -909,17 +1003,29 @@ int dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part)
 			bytesWritten = 0;
 		}
 	}
-	tui_pbar(&gfx_con, 0, gfx_con.y, 100);
+	tui_pbar(&gfx_con, 0, gfx_con.y, 100, 0xFFCCCCCC, 0xFF555555);
 
-out:;
+	// Dumping process ended successfully
 	free(buf);
 	f_close(&fp);
+
+	// Verify last part or single file dump
+	if (dump_emmc_verify(storage, lba_curr, outFilename, NUM_SECTORS_PER_ITER, part))
+	{
+		EPRINTF("\nPress any key and try again.\n");
+
+		free(buf);
+		return 0;
+	}
+	else
+		tui_pbar(&gfx_con, 0, gfx_con.y, 100, 0xFF00FF96, 0xFF005515);
+
 	gfx_con_setfontsz(&gfx_con, 16);
 	// Remove partial dump index file if no fatal errors occurred.
 	if(isSmallSdCard)
 	{
 		f_unlink(partialIdxFilename);
-		gfx_printf(&gfx_con, "\n\nYou can now join the files\nand get the complete raw eMMC dump.");
+		gfx_printf(&gfx_con, "%k%K\n\nYou can now join the files\nand get the complete raw eMMC dump.", 0xFFCCCCCC, 0xFF1B1B1B);
 	}
 	gfx_puts(&gfx_con, "\n\n");
 
@@ -1024,7 +1130,7 @@ static void dump_emmc_selected(dumpType_t dumpType)
 	gfx_printf(&gfx_con, "%kTime taken: %d seconds.%k\n", 0xFF00FF96, (get_tmr() - timer) / 1000000, 0xFFCCCCCC);
 	sdmmc_storage_end(&storage);
 	if (res)
-		gfx_puts(&gfx_con, "\nDone. Press any key.\n");
+		gfx_puts(&gfx_con, "\nFinished and verified!\nPress any key.\n");
 
 out:;
 	btn_wait();
@@ -1166,8 +1272,13 @@ void launch_firmware()
 		gfx_printf(&gfx_con, "Using default launch configuration...\n");
 	}
 
+	free(Kc_HEKATE_LOGO);
 	if (!hos_launch(cfg_sec))
+	{
+		Kc_HEKATE_LOGO = (u8 *)malloc(36864);
+		LZ_Uncompress(Kc_HEKATE_LOGOlz, Kc_HEKATE_LOGO, SZ_HEKATE_LOGOLZ);
 		EPRINTF("Failed to launch firmware.");
+	}
 
 	//TODO: free ini.
 
@@ -1209,12 +1320,12 @@ void about()
 {
 	gfx_con_setfontsz(&gfx_con, 8);
 	static const char octopus[] =
-	"hekate (c) 2018 naehrwert, st4rk\n\n"
+	"hekate (C) 2018 naehrwert, st4rk\n\n"
 	"Thanks to: %kderrek, nedwill, plutoo, shuffle2, smea, thexyz, yellows8%k\n\n"
 	"Greetings to: fincs, hexkyz, SciresM, Shiny Quagsire, WinterMute\n\n"
 	"Open source and free packages used:\n"
-	" - FatFs R0.13a (Copyright (C) 2017, ChaN)\n"
-	" - bcl-1.2.0 (Copyright (c) 2003-2006 Marcus Geelnard)\n\n"
+	" - FatFs R0.13a, (Copyright (C) 2017, ChaN)\n"
+	" - bcl-1.2.0,    (Copyright (C) 2003-2006, Marcus Geelnard)\n\n"
 	"                         %k___\n"
 	"                      .-'   `'.\n"
 	"                     /         \\\n"
@@ -1319,7 +1430,7 @@ ment_t ment_top[] = {
 };
 menu_t menu_top = {
 	ment_top,
-	"hekate - ipl (CTCaer mod v2.0)", 0, 0
+	"hekate - ipl (CTCaer mod v2.1)", 0, 0
 };
 
 extern void pivot_stack(u32 stack_top);
@@ -1342,6 +1453,8 @@ void ipl_main()
 	u32 *fb = display_init_framebuffer();
 	gfx_init_ctxt(&gfx_ctxt, fb, 720, 1280, 768);
 	gfx_clear(&gfx_ctxt, 0xFF1B1B1B);
+	Kc_HEKATE_LOGO = (u8 *)malloc(36864);
+	LZ_Uncompress(Kc_HEKATE_LOGOlz, Kc_HEKATE_LOGO, SZ_HEKATE_LOGOLZ);
 	gfx_con_init(&gfx_con, &gfx_ctxt);
 
 	while (1)

ipl/pkg1.c

@@ -24,9 +24,12 @@
 #define _BL(a, o) 0x94000000 | (((o) - (a)) >> 2) & 0x3FFFFFF
 #define _NOP() 0xD503201F
 
+//#define SM_100_ADR 0x40014020
+#define SM_100_ADR 0x4002B020
+
 PATCHSET_DEF(_secmon_1_patchset,
-	//Patch the relocator to be able to run from 0x4002D000.
-	//{ 0x1E0, _ADRP(0, 0x7C013000 - 0x4002D000) }
+	//Patch the relocator to be able to run from SM_100_ADR.
+	{ 0x1E0, _ADRP(0, 0x7C013000 - (SM_100_ADR - 0x40)) },
 	//Patch package2 decryption and signature/hash checks.
 	{ 0x9F0 + 0xADC, _NOP() }, //Header signature.
 	{ 0x9F0 + 0xB8C, _NOP() }, //Version.
@@ -48,15 +51,15 @@ PATCHSET_DEF(_secmon_3_patchset,
 	{ 0xAC8 + 0xADC, _NOP() }  //Sections SHA2.
 );
 
-PATCHSET_DEF(_secmon_5_patchset,
+PATCHSET_DEF(_secmon_4_patchset,
 	//Patch package2 decryption and signature/hash checks.
 	{ 0x1218 + 0x6E68, _NOP() }, //Header signature.
 	{ 0x1218 + 0x6E74, _NOP() }, //Version.
 	{ 0x1218 + 0x6FE4, _NOP() }, //Sections SHA2.
-	{ 0x1218 + 0x2DC, _NOP() }   //Unknown.
+	{ 0x1218 + 0x2DC,  _NOP() }  //Unknown.
 );
 
-PATCHSET_DEF(_secmon_6_patchset,
+PATCHSET_DEF(_secmon_5_patchset,
 	//Patch package2 decryption and signature/hash checks.
 	{ 0x12b0 + 0x4d0, _NOP() },
 	{ 0x12b0 + 0x4dc, _NOP() },
@@ -65,6 +68,32 @@ PATCHSET_DEF(_secmon_6_patchset,
 	//{ 0x12b0 + 0xa18 , _NOP() } // BootConfig Retail Check
 );
 
+// Include kernel patches here, so we can utilize pkg1 id
+PATCHSET_DEF(_kernel_1_patchset,
+	{ 0x3764C, _NOP() },         // Disable SVC verifications
+	{ 0x44074, _MOVZX(8, 1, 0) } // Enable Debug Patch
+);
+
+PATCHSET_DEF(_kernel_2_patchset,
+	{ 0x54834, _NOP() },         // Disable SVC verifications
+	{ 0x6086C, _MOVZX(8, 1, 0) } // Enable Debug Patch
+);
+
+PATCHSET_DEF(_kernel_3_patchset,
+	{ 0x3BD24, _NOP() },         // Disable SVC verifications
+	{ 0x483FC, _MOVZX(8, 1, 0) } // Enable Debug Patch
+);
+
+PATCHSET_DEF(_kernel_4_patchset,
+	{ 0x41EB4, _NOP() },         // Disable SVC verifications
+	{ 0x4EBFC, _MOVZX(8, 1, 0) } // Enable Debug Patch
+);
+
+PATCHSET_DEF(_kernel_5_patchset,
+	{ 0xFFFFFFFF, 0xFFFFFFFF },  // TODO: MISSING
+	{ 0x5513C, _MOVZX(8, 1, 0) } // Enable Debug Patch
+);
+
 /*
 * package1.1 header: <wb, ldr, sm>
 * package1.1 layout:
@@ -77,12 +106,12 @@ PATCHSET_DEF(_secmon_6_patchset,
 */
 
 static const pkg1_id_t _pkg1_ids[] = {
-	{ "20161121183008", 0, 0x1900, 0x3FE0, { 2, 1, 0 }, 0x40014020, _secmon_1_patchset }, //1.0.0
-	{ "20170210155124", 0, 0x1900, 0x3FE0, { 0, 1, 2 }, 0x4002D000, _secmon_2_patchset }, //2.0.0
-	{ "20170519101410", 1, 0x1A00, 0x3FE0, { 0, 1, 2 }, 0x4002D000, _secmon_3_patchset }, //3.0.0
-	{ "20170710161758", 2, 0x1A00, 0x3FE0, { 0, 1, 2 }, 0x4002D000, _secmon_3_patchset }, //3.0.1
-	{ "20170921172629", 3, 0x1800, 0x3FE0, { 1, 2, 0 }, 0x4002B000, _secmon_5_patchset }, //4.0.0
-	{ "20180220163747", 4, 0x1900, 0x3FE0, { 1, 2, 0 }, 0x4002B000, _secmon_6_patchset }, //5.0.0
+	{ "20161121183008", 0, 0x1900, 0x3FE0, { 2, 1, 0 }, SM_100_ADR, _secmon_1_patchset, _kernel_1_patchset }, //1.0.0 (Patched relocator)
+	{ "20170210155124", 0, 0x1900, 0x3FE0, { 0, 1, 2 }, 0x4002D000, _secmon_2_patchset, _kernel_2_patchset }, //2.0.0 - 2.3.0
+	{ "20170519101410", 1, 0x1A00, 0x3FE0, { 0, 1, 2 }, 0x4002D000, _secmon_3_patchset, _kernel_3_patchset }, //3.0.0
+	{ "20170710161758", 2, 0x1A00, 0x3FE0, { 0, 1, 2 }, 0x4002D000, _secmon_3_patchset, _kernel_3_patchset }, //3.0.1 - 3.0.2
+	{ "20170921172629", 3, 0x1800, 0x3FE0, { 1, 2, 0 }, 0x4002B000, _secmon_4_patchset, _kernel_4_patchset }, //4.0.0 - 4.1.0
+	{ "20180220163747", 4, 0x1900, 0x3FE0, { 1, 2, 0 }, 0x4002B000, _secmon_5_patchset, _kernel_5_patchset }, //5.0.0 - 5.0.2
 	{ NULL, 0, 0, 0, 0 } //End.
 };
 

ipl/pkg1.h

@@ -40,6 +40,7 @@ typedef struct _pkg1_id_t
 	u32 sec_map[3];
 	u32 secmon_base;
 	patch_t *secmon_patchset;
+	patch_t *kernel_patchset;
 } pkg1_id_t;
 
 typedef struct _pk11_hdr_t

ipl/sdram_param_t210_lp0.h

@@ -262,7 +262,7 @@ struct sdram_params {
 	/* Specifies the value for EMC_PUTERM_WIDTH */
 	u32 EmcPutermWidth;
 	/* Specifies the value for EMC_PUTERM_ADJ */
-	u32 EmcPutermAdj;
+	////u32 EmcPutermAdj;
 
 	/* Specifies the value for EMC_QRST */
 	u32 EmcQRst;
@@ -647,7 +647,7 @@ struct sdram_params {
 	u32 EmcAcpdControl;
 
 	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
-	u32 EmcSwizzleRank0ByteCfg;
+	////u32 EmcSwizzleRank0ByteCfg;
 	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
 	u32 EmcSwizzleRank0Byte0;
 	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
@@ -657,7 +657,7 @@ struct sdram_params {
 	/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
 	u32 EmcSwizzleRank0Byte3;
 	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
-	u32 EmcSwizzleRank1ByteCfg;
+	////u32 EmcSwizzleRank1ByteCfg;
 	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
 	u32 EmcSwizzleRank1Byte0;
 	/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */

ipl/tui.c

@@ -16,9 +16,10 @@
 
 #include "tui.h"
 #include "btn.h"
-#include "ctc_logo2.h"
 
-void tui_pbar(gfx_con_t *con, int x, int y, u32 val)
+extern u8 *Kc_HEKATE_LOGO;
+
+void tui_pbar(gfx_con_t *con, int x, int y, u32 val, u32 fgcol, u32 bgcol)
 {
 	u32 cx, cy;
 
@@ -26,14 +27,14 @@ void tui_pbar(gfx_con_t *con, int x, int y, u32 val)
 
 	gfx_con_setpos(con, x, y);
 
-	gfx_printf(con, "[%3d%%]", val);
+	gfx_printf(con, "%k[%3d%%]%k", fgcol, val, bgcol);
 
 	x += 7 * con->fntsz;
 	
 	for (int i = 0; i < con->fontmult * 6; i++)
 	{
-		gfx_line(con->gfx_ctxt, x, y + i + 1, x + 3 * val, y + i + 1, 0xFFCCCCCC);
-		gfx_line(con->gfx_ctxt, x + 3 * val, y + i + 1, x + 3 * 100, y + i + 1, 0xFF555555);
+		gfx_line(con->gfx_ctxt, x, y + i + 1, x + 3 * val, y + i + 1, fgcol);
+		gfx_line(con->gfx_ctxt, x + 3 * val, y + i + 1, x + 3 * 100, y + i + 1, bgcol);
 	}
 
 	gfx_con_setpos(con, cx, cy);

ipl/tui.h

@@ -57,7 +57,7 @@ typedef struct _menu_t
 #define MDEF_CAPTION(caption, color) { MENT_CAPTION, caption, color }
 #define MDEF_CHGLINE() {MENT_CHGLINE}
 
-void tui_pbar(gfx_con_t *con, int x, int y, u32 val);
+void tui_pbar(gfx_con_t *con, int x, int y, u32 val, u32 fgcol, u32 bgcol);
 void *tui_do_menu(gfx_con_t *con, menu_t *menu);
 
 #endif