OmniNX/hekate-pro
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v6.5.2
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659 Commits

Author SHA1 Message Date
NaGa
45318f691f . 2026-03-28 01:42:43 +01:00
CTCaer
a60510f7de bdk: mc: add offset to arc aperture 
And increase it back to 4KB for TSEC only, since the firmware actually checks for it.
 2026-03-27 20:44:29 +01:00
CTCaer
1561af252f bdk: sdmmc: parse bkops info 2026-03-27 20:44:15 +01:00
CTCaer
f6cecdc783 bdk: memory map: define max use from sdram params 2026-03-27 20:44:15 +01:00
CTCaer
387b5b07ed bdk: sdmmc: rename bkops define 
And remove dead code.
 2026-03-27 20:44:15 +01:00
CTCaer
e7deafd6a1 bdk: smmu: reset heap on disable 
And rename domain init/deinit
 2026-03-27 20:42:31 +01:00
CTCaer
3e6df2459d bdk: sdram: add missing T210 1GB density timings 2026-03-27 20:42:31 +01:00
CTCaer
7ca071a67c bdk: lvgl: add creme accent support 2026-03-27 20:42:31 +01:00
CTCaer
07408305f5 bdk: lvgl: correct slider knob signal coordinates 
It should always point to the middle of the knob and not be variable with offset.
 2026-03-27 20:42:31 +01:00
CTCaer
64a5d48ab5 touch: increase max allowed touched area 2026-03-27 20:42:31 +01:00
CTCaer
a02624cd39 bdk: mc: reduce ahb aperture by 4KB 
The state machine automatically uses TOM + 4KB as real top address.
This can cause issues with HW that accesses that low RAM range,
since once the request enters ARC can't be redirected to MC and can hang.
 2026-03-27 20:42:31 +01:00
CTCaer
88ba35b73f bdk: mc: always enable ahb redirection 2026-03-27 20:42:31 +01:00
CTCaer
f975364a8e bdk: touch: add clone support 
From LCD on OLED sku.
 2026-03-27 20:42:31 +01:00
CTCaer
72623d5a80 bdk: ini: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
12d970fa64 bdk: pmc: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
9bca3c0253 bdk: kfuse: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
fcbae9d581 bdk: clock: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
a8325f4ec4 bdk: tsec: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
0e49d62bed bdk: se: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
1101db8f19 bdk: power: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
45446486f2 bdk: dram: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
10fceea4be bdk: touch: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
f26e9f0504 bdk: i2c: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
58064bda34 bdk: vic: expose idle wait 2026-03-27 20:08:45 +01:00
CTCaer
1319984285 bdk: touch: check event count for wait event 
And increase checks during autotune execution.
 2026-03-27 20:08:45 +01:00
CTCaer
8881faa91b bdk: touch: simplify input reporting 
Additionally, touch polling now returns 1 for no event result.
 2026-03-27 20:08:45 +01:00
CTCaer
0e64b9384f bdk: touch: switch to custom chip info cmd 
And also check if chip id is correct on init.
 2026-03-27 20:08:45 +01:00
CTCaer
e3fba92e00 bdk: touch: use packet i2c for all transfers 
The repeating byte doesn't exist in i2c packet mode.
Additionally, adjust split transfers to one.
 2026-03-27 20:08:45 +01:00
CTCaer
2a7e148011 bdk: touch: refactor 
And also use packet mode for big tx/rx combo i2c trasnfers.
 2026-03-27 20:08:45 +01:00
CTCaer
476c070cf4 bdk: i2c: optimize packet mode functions 
- Allow xfer packet to send up to 20 bytes before receiving
- Remove interrupt use since it's only polling
- Check proper status for TX finish.
 2026-03-27 20:08:45 +01:00
CTCaer
8f6dce1368 bdk: i2c: refactor 2026-03-27 20:08:45 +01:00
CTCaer
10c2d3d379 bdk: clk: add missing macro 2026-03-27 20:08:45 +01:00
CTCaer
e2ff75291b bdk: touch: refactor/improve 
- Remove useless poll wait
- Use more defines
- Deduplicate code
- Add more checks
- Add switch sense mode
 2026-03-27 20:08:45 +01:00
CTCaer
45a08c058f bdk: clk: reduce i2c freq input to save power 2026-03-27 20:08:45 +01:00
CTCaer
7a37ddc45e bdk: vic: add hw version that this driver aims for 
Also TRM lies about best cache width, like always.
The higher the faster. The lower the simpler alignment.
A balanced one is used by default.
 2026-03-27 20:08:45 +01:00
CTCaer
de3a74d351 bdk: bm92t: do not parse non fixed pdos 2026-03-27 20:08:45 +01:00
CTCaer
eb62a31a1a bdk: sdmmc: remove dependency to ram for init 2026-03-27 20:08:45 +01:00
CTCaer
bf5372628a bdk: mem: rename sdmmc dma buffer 2026-03-27 20:05:57 +01:00
CTCaer
aba56fd173 bdk: move exception type base away from IRQ stack 
Allow a more heavy stack usage by IRQ handlers.
 2026-03-27 20:05:57 +01:00
CTCaer
618e3007b5 bdk: lvgl: complete black theme 
This has the side-effect to make any theme color component from 0x0B to 0xC7 work.
 2026-03-27 19:38:45 +01:00
CTCaer
378d38b850 bdk: add missing header guards 2026-03-27 19:38:45 +01:00
CTCaer
f155346238 bdk: ianos: restructure for future expansion 2026-03-27 19:38:08 +01:00
CTCaer
b3c95990ed bdk: pmc: refactor register defines and structs 2026-03-27 19:36:58 +01:00
CTCaer
b86701823c bdk: pinmux: always detach I2C4 pins from I2C3 pm 
Generally I2C3 communication can work via I2C3 or I2C4 pins.
Defaults are fine as long as one of the pin groups are floating or grounded or
both share I2C traces.

In NX boards I2C4 SDA is used for GC and connected to 1V8.
So if a GC is slotted, I2C3 works, if not, no communication is possible.

This config was done previously inside I2C3 consumer driver (touchscreen).
Now it's moved inside pinmux_config_i2c.
 2026-03-27 19:36:58 +01:00
CTCaer
315457651c bdk: joycon: make init stricter but relax timings 
Additionally, if both Joy-Con are found, try to send rumble simultaneously.
 2026-03-27 10:02:21 +01:00
CTCaer
aecd657358 bdk: display: reduce display off waiting time 
And align oled panel inside vblank.
Assumes display deinit happens before the rest of deinit.
 2026-03-27 10:02:21 +01:00
CTCaer
925b6e22bb bdk: se: add T210 SHA256 silicon errata WAR 
Apparently, some T210 silicon have an undocumented errata where the MSG_LEFT2/3
registers are not ignored as they should.
When they have random data in POR they cause a hang as long as the message and
SHA calculation speed. So always clear them.
Additionally, clear MSG_LENGTH2/3 registers too even though they do not matter.
 2026-03-27 10:02:21 +01:00
CTCaer
5a35a61753 bdk: se: adjust T210 silicon errata coherency WAR 
Add a 15us worst case scenario delay after OP done for T210.
Practically, because of 1600 MHz RAM, less than 1us delay is needed.
(204 MHz: 15us, 408 MHz: 5us, etc).
 2026-03-27 10:02:21 +01:00
CTCaer
e649d1df8e bdk: se: correct result for < block size aes 2026-03-27 10:02:21 +01:00
CTCaer
4daa02fe85 bdk: hwinit: remove coreboot support 
Everything external is finally updated and beyond parity with old things that needed it.
 2026-03-27 10:00:26 +01:00