OmniNX/hekate-pro
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Author SHA1 Message Date
CTCaer
ffc0aa2c3d bdk: fuse: return array size with fuse_read_array 2026-03-27 09:57:23 +01:00
CTCaer
bb20eabea2 nyx: parted: remove invisible btns in eMMC mode 2026-03-27 09:57:23 +01:00
CTCaer
330b463110 nyx: add a small stall in lvgl loop 
EMC CC should not run in less than 20us.
 2026-03-27 09:56:31 +01:00
CTCaer
4af99c9f78 hos/l4t: deduplicate sc7exit-b01 load 
And remove obsolete MWS (L4T one deprecated it 3 years ago).
 2026-03-27 09:56:31 +01:00
CTCaer
4c2f8f14dc hos: reflect minerva changes 2026-03-27 09:55:59 +01:00
CTCaer
fd8c2ef56d lp0 cfg: use a more appropriate entry name 2026-03-27 09:55:12 +01:00
CTCaer
6b66b7f079 minerva: update tov1.6_T210/v0.1_T21X 
T21X v0.1:
- Add IRB/no table support
T210 v1.6/Common:
- Add a proper table for 8GB T210 config instead of editing a 4GB one
- Increase timeout to 2ms
- Generally improve checks and guard against unknown SoCs/SKUs
- Remove the long ago obsolete OVERCLOCK_FREQ/OVERCLOCK_VOLTAGE ifdefs
 2026-03-27 09:55:12 +01:00
CTCaer
76922b7b87 bdk: minerva: add IRB support 
Aka no table support.
 2026-03-27 09:55:12 +01:00
CTCaer
2bc4000acc hekate: gfx: correct a very very very old typo 2026-03-27 09:55:12 +01:00
CTCaer
892dba3a71 hekate: exo: simplify fatal screen to save space 
And remove an obsolete message.
 2026-03-27 09:55:12 +01:00
CTCaer
851bf05841 hekate: remove precise free clusters calc in TUI 2026-03-27 09:55:12 +01:00
CTCaer
03cb1aac29 bdk: clock: update some defines 2026-03-27 09:54:06 +01:00
CTCaer
61cb77a016 bdk: sdmmc: add defines for max block number 2026-03-27 09:54:06 +01:00
CTCaer
facd5c9ae9 Bump hekate to v6.4.2 and Nyx to v1.8.2 2026-03-27 09:53:33 +01:00
CTCaer
5c04530bfc nyx: options: add month/date checks for roller 
Now the roller will return back automatically if day can't be set for selected month.
Additionally, fix the check when saving.
 2026-03-27 09:53:33 +01:00
CTCaer
ef5033fb0e nyx: info: add wafer graph with die x/y placement 2026-03-27 09:53:33 +01:00
CTCaer
952a7e8aa2 nyx: info: streamline hw info from fuses 
- Compact and group relevant values together
- Use actual value name instead of register name where possible
- Fix LOT code masking
- Fully parse and show LOT code (it's the same marking on die)
- Correct X coordinate parsing (9bit 2s complement)
- Add product code
 2026-03-27 09:53:33 +01:00
CTCaer
4430833d28 hekate: write rsvd cfg to update.bin if different 2026-03-27 09:53:33 +01:00
CTCaer
3af536f954 nyx: do init always with lowest clock boost 2026-03-27 09:52:34 +01:00
CTCaer
5bc98c4b19 nyx: fix bt pairing dumping 2026-03-27 09:52:34 +01:00
CTCaer
2b353c1336 nyx: info: add forced 8GB ram info 2026-03-27 09:52:34 +01:00
CTCaer
32c374aff5 hekate: show errors before parsing R2C 2026-03-27 09:52:34 +01:00
CTCaer
1af22f6c45 hekate: add force 8GB ram config mode 2026-03-27 09:52:34 +01:00
CTCaer
4b796ab63f loader/hekate/nyx: utilize the new rsvd cfg 2026-03-27 09:52:34 +01:00
CTCaer
8d525a3c50 bdk: add reserved cfg to ipl meta and nyx storage 2026-03-27 09:51:47 +01:00
CTCaer
ef0ab0b0f1 bdk: sdmmc: correct drive ohms comment 2026-03-27 09:51:47 +01:00
CTCaer
7b7906efc2 bdk: clock: add i2c to the errata affected list 2026-03-27 09:51:47 +01:00
CTCaer
e29d139946 bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2026-03-27 09:51:47 +01:00
CTCaer
cfcbb62768 hekate/nyx: use minerva storage and panel id 2026-03-27 09:51:47 +01:00
CTCaer
b862311c0c bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2026-03-27 09:51:46 +01:00
CTCaer
11b49e3bbc bdk: nyx: rename disp_id to panel_id 2026-03-27 09:51:46 +01:00
CTCaer
ac245a0b6f bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2026-03-27 09:51:46 +01:00
CTCaer
c0300b1cee bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2026-03-27 09:51:46 +01:00
CTCaer
1eaa801d6a bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2026-03-27 09:51:46 +01:00
CTCaer
25359b23b9 bdk: clock: add sdmmc1 to the errata affected list 2026-03-27 09:51:46 +01:00
CTCaer
db08514ff0 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2026-03-27 09:51:46 +01:00
CTCaer
877e2c7c2e bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2026-03-27 09:51:46 +01:00
CTCaer
fa2d7854d3 bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2026-03-27 09:51:46 +01:00
CTCaer
ac0d98ad29 bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2026-03-27 09:51:46 +01:00
CTCaer
9b216efddf Bump hekate to v6.4.1 and Nyx to v1.8.1 2026-03-27 09:49:29 +01:00
CTCaer
911b170b4d nyx: info: add hos version for 22 fuses burnt 2026-03-27 09:49:29 +01:00
CTCaer
c026b1db3d hos: fix 21.0.0 nogc FS patch and refactor patches 
The NOGC sdmmc memio patch was incorrectly changing the register that keeps the value for HOS 21.0.0.
Refactored all patches to stop patching the whole op and just change the value from 0x200 to 0x400.
 2026-03-27 09:49:29 +01:00
CTCaer
dc1ad1a5a7 Bump hekate to v6.4.0 and Nyx to v1.8.0 2026-03-27 09:49:29 +01:00
CTCaer
36aa1b21ad nyx: parted: do not allow FULL on upgraded eMMC 
It's not allowed on creation anyway because of unknown HOS USER size factors
 2026-03-27 09:49:29 +01:00
CTCaer
10521a32d3 hos: add 21.0.0 support 2026-03-27 09:48:54 +01:00
CTCaer
82a97aae53 nyx: extend bpmpclock 
Add 2 more slower modes.
 2026-03-27 09:48:54 +01:00
CTCaer
a365af0492 bdk: bpmp: add binX clock defines 2026-03-27 09:48:54 +01:00
CTCaer
28dce16877 bdk: fuse: add sense function 2026-03-27 09:48:54 +01:00
CTCaer
f541f14699 bdk: fuse: add extra info on regs 2026-03-27 09:48:54 +01:00
CTCaer
518cfd401a bdk: fuse: correct masking on array read cmd 2026-03-27 09:48:54 +01:00