OmniNX/hekate-pro
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1,918 Commits 3 Branches 63 Tags
ef0ab0b0f10f341ec2d6bc00f02f61e047dfee7a
Commit Graph
573 Commits
Author SHA1 Message Date
CTCaer ef0ab0b0f1 bdk: sdmmc: correct drive ohms comment 2026-03-27 09:51:47 +01:00
CTCaer 7b7906efc2 bdk: clock: add i2c to the errata affected list 2026-03-27 09:51:47 +01:00
CTCaer e29d139946 bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2026-03-27 09:51:47 +01:00
CTCaer b862311c0c bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2026-03-27 09:51:46 +01:00
CTCaer 11b49e3bbc bdk: nyx: rename disp_id to panel_id 2026-03-27 09:51:46 +01:00
CTCaer ac245a0b6f bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2026-03-27 09:51:46 +01:00
CTCaer c0300b1cee bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2026-03-27 09:51:46 +01:00
CTCaer 1eaa801d6a bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2026-03-27 09:51:46 +01:00
CTCaer 25359b23b9 bdk: clock: add sdmmc1 to the errata affected list 2026-03-27 09:51:46 +01:00
CTCaer db08514ff0 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2026-03-27 09:51:46 +01:00
CTCaer 877e2c7c2e bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2026-03-27 09:51:46 +01:00
CTCaer fa2d7854d3 bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2026-03-27 09:51:46 +01:00
CTCaer ac0d98ad29 bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2026-03-27 09:51:46 +01:00
CTCaer a365af0492 bdk: bpmp: add binX clock defines 2026-03-27 09:48:54 +01:00
CTCaer 28dce16877 bdk: fuse: add sense function 2026-03-27 09:48:54 +01:00
CTCaer f541f14699 bdk: fuse: add extra info on regs 2026-03-27 09:48:54 +01:00
CTCaer 518cfd401a bdk: fuse: correct masking on array read cmd 2026-03-27 09:48:54 +01:00
CTCaer 44dd00c29a bdk: t210: add mc channel macros 2026-03-27 09:48:54 +01:00
CTCaer 0fa5db1d74 bdk: emc/mc: don't use [io]_rsvd naming for unused regs 2026-03-27 09:48:53 +01:00
CTCaer 76d5cf591f bdk: lvgl: make sure task has a task to call 2026-03-27 09:48:53 +01:00
CTCaer 67157b1867 bdk: ini: switch back to ASCII ordering 
For combining multiple inis.
 2026-03-27 09:44:07 +01:00
CTCaer af72bb5b94 bdk: dirlist: use flags instead of arguments 
A new flag was also added that forces an ASCII ordering instead of Alphabetical one.
 2026-03-27 09:44:07 +01:00
CTCaer e19cf3038b bdk: minerva: allow sdmmc la to be skipped on L4T 2026-03-27 09:44:07 +01:00
CTCaer b52f5edce6 bdk: hwinit: refactor MBIST WAR & add description 
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
 2026-03-27 09:44:07 +01:00
CTCaer 393d135105 bdk: hwinit: fix RAM_SVOP_PDP try no 2 
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
 2026-03-27 09:44:07 +01:00
CTCaer 6cc3aee389 bdk: storage: small mmc refactoring 
- Correct some Response Type names
- And use _def for mmc defines similarly to sd_def
 2026-03-27 09:44:07 +01:00
CTCaer 030576ff3f bdk: mc: carveouts are not set by cfg so fix them 
For HOS <= 3.0.2 the carveouts are set by bootloader and sdram config actually does not set them.
So add which need different value from reset and also make sure that data is flushed for WPR config.
 2026-03-27 09:44:07 +01:00
CTCaer 44e4c0ab21 bdk: make use of new MC/EMC defines 2026-03-27 09:44:07 +01:00
CTCaer f45adfd92f bdk: rework MC/EMC register defines from scratch 
And add register structs also.
 2026-03-27 09:44:06 +01:00
CTCaer 2fda4115aa bdk: add some t210 and fuses defines 
PGUP tag register can be used to identify which cpu we are running on.
 2026-03-27 09:44:06 +01:00
CTCaer d289224653 bdk: clock: simplify logic 
Simplify logic for clock enable and sdmmc clock management
 2026-03-27 09:44:06 +01:00
CTCaer 0647fd06d8 bdk: clock: remove non existent module ids 
And add comments to special handling ones
 2026-03-27 09:44:06 +01:00
CTCaer d33ded5f6d bdk: pmc: rename pmc_enable_partition 2026-03-27 09:44:06 +01:00
CTCaer b70932cfaa bdk: clock: wait for PLLD to lock when set 2026-03-27 09:44:06 +01:00
CTCaer c83bd247dd bdk: add tegra BCT/BIT headers for T210/T210B01 2026-03-27 09:42:41 +01:00
CTCaer 3874b025a9 bdk: rtc: add auto dst support and fix an off-by-one 2026-03-27 09:41:57 +01:00
CTCaer 26d8faa502 bdk: lvgl: set long press to 5s 2026-03-27 09:07:45 +01:00
CTCaer e66ab207d9 bdk: fatfs: optimize format and fix PrFILE2 SAFE 
The FAT tables are now always aligned 1MB which can increase the FAT traversing
speed. Additionally, always aligning the FAT tables to minimum 16KB fixes a case
where PrFILE2 SAFE could be disabled because of unaligned FAT.
 2026-03-27 09:07:45 +01:00
CTCaer baea3b0265 bdk: use f_unmount instead of null f_mount 2026-03-27 09:07:45 +01:00
CTCaer 380c1dc9b2 bdk: refactor several comments and defines 2026-03-27 09:05:58 +01:00
CTCaer 1ee9a9cd64 bdk: update memory map to increase ramdisk size 
From 1040 to 1280MB.
 2026-03-27 09:05:58 +01:00
CTCaer 528e1fb0a4 bdk: usb: revamp hid logic 
- Add support for GET REPORT. Allows OS to get a single input report.
- Add support for SET_IDLE. Allows OS to control when to send input reports

The SET IDLE and the underlying logic change fixes several things:
- The old issue of congestion in some systems.
- The new bug that would not allow setup packets to be received because mode
 was set to only send when there are changes.
- Now this starts properly as the old code but allows to be changed by OS on
 demand, while continuing servicing setup packets.
 2026-03-27 09:05:58 +01:00
CTCaer 077986cb47 bdk: usb: small refactor 2026-03-27 09:05:58 +01:00
CTCaer ec84a58dcc bdk: usb: remove unused endpoint from hid 2026-03-27 09:05:58 +01:00
CTCaer 51c1e31134 bdk: max17050: add version check 2026-03-27 09:05:58 +01:00
CTCaer 95af92d912 bdk: bq24193: add version check 2026-03-27 09:05:58 +01:00
CTCaer a028568349 bdk: bm92t: add version check 2026-03-27 09:05:58 +01:00
CTCaer fbaa88cc31 bdk: smmu: add smmu disable 2026-03-27 09:05:58 +01:00
CTCaer 1e870bcef4 bdk: display: update comments 
And also set WinD reg updating to HSYNC
 2026-03-27 09:05:58 +01:00
CTCaer 2d91e9b549 bdk: clock: refactor common PLL defines 2026-03-27 09:05:58 +01:00