OmniNX/hekate-pro
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Author SHA1 Message Date
CTCaer ef0ab0b0f1 bdk: sdmmc: correct drive ohms comment 2026-03-27 09:51:47 +01:00
CTCaer 7b7906efc2 bdk: clock: add i2c to the errata affected list 2026-03-27 09:51:47 +01:00
CTCaer e29d139946 bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2026-03-27 09:51:47 +01:00
CTCaer cfcbb62768 hekate/nyx: use minerva storage and panel id 2026-03-27 09:51:47 +01:00
CTCaer b862311c0c bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2026-03-27 09:51:46 +01:00
CTCaer 11b49e3bbc bdk: nyx: rename disp_id to panel_id 2026-03-27 09:51:46 +01:00
CTCaer ac245a0b6f bdk: minerva: remove dependency to Nyx storage 
minerva_str_t must be used now and passed directly to minerva_init.
 2026-03-27 09:51:46 +01:00
CTCaer c0300b1cee bdk: display: remove dependency to Nyx storage 
display_get_verbose_panel_id should now be used to get the full panel id.
 2026-03-27 09:51:46 +01:00
CTCaer 1eaa801d6a bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2026-03-27 09:51:46 +01:00
CTCaer 25359b23b9 bdk: clock: add sdmmc1 to the errata affected list 2026-03-27 09:51:46 +01:00
CTCaer db08514ff0 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2026-03-27 09:51:46 +01:00
CTCaer 877e2c7c2e bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2026-03-27 09:51:46 +01:00
CTCaer fa2d7854d3 bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2026-03-27 09:51:46 +01:00
CTCaer ac0d98ad29 bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2026-03-27 09:51:46 +01:00
CTCaer 9b216efddf Bump hekate to v6.4.1 and Nyx to v1.8.1 2026-03-27 09:49:29 +01:00
CTCaer 911b170b4d nyx: info: add hos version for 22 fuses burnt 2026-03-27 09:49:29 +01:00
CTCaer c026b1db3d hos: fix 21.0.0 nogc FS patch and refactor patches 
The NOGC sdmmc memio patch was incorrectly changing the register that keeps the value for HOS 21.0.0.
Refactored all patches to stop patching the whole op and just change the value from 0x200 to 0x400.
 2026-03-27 09:49:29 +01:00
CTCaer dc1ad1a5a7 Bump hekate to v6.4.0 and Nyx to v1.8.0 2026-03-27 09:49:29 +01:00
CTCaer 36aa1b21ad nyx: parted: do not allow FULL on upgraded eMMC 
It's not allowed on creation anyway because of unknown HOS USER size factors
 2026-03-27 09:49:29 +01:00
CTCaer 10521a32d3 hos: add 21.0.0 support 2026-03-27 09:48:54 +01:00
CTCaer 82a97aae53 nyx: extend bpmpclock 
Add 2 more slower modes.
 2026-03-27 09:48:54 +01:00
CTCaer a365af0492 bdk: bpmp: add binX clock defines 2026-03-27 09:48:54 +01:00
CTCaer 28dce16877 bdk: fuse: add sense function 2026-03-27 09:48:54 +01:00
CTCaer f541f14699 bdk: fuse: add extra info on regs 2026-03-27 09:48:54 +01:00
CTCaer 518cfd401a bdk: fuse: correct masking on array read cmd 2026-03-27 09:48:54 +01:00
CTCaer 44dd00c29a bdk: t210: add mc channel macros 2026-03-27 09:48:54 +01:00
CTCaer 0fa5db1d74 bdk: emc/mc: don't use [io]_rsvd naming for unused regs 2026-03-27 09:48:53 +01:00
CTCaer 76d5cf591f bdk: lvgl: make sure task has a task to call 2026-03-27 09:48:53 +01:00
CTCaer daf832971e nyx: part: extend Fix Hybrid MBR/GPT functionality 
- Allow invalid/out-of-bounds and empty partitions to be removed from GPT
- Add fix for wrong emuMMC offset because of older bugged Android Dynamic scheme
 2026-03-27 09:48:53 +01:00
CTCaer 3c260b1918 nyx: info: update SD errors after a bench session 2026-03-27 09:48:07 +01:00
CTCaer 6b4b20e0ac nyx: info: say when sbk fuses can't be read 
Additionally, swap the IDDQ real with raw values.
 2026-03-27 09:48:07 +01:00
CTCaer 0468877136 nyx: fix a mem leak on closing emummc change win 2026-03-27 09:48:07 +01:00
CTCaer fba05d4e7a nyx: part: add support for max 24GB resized emuMMC 
If a partition is added manually, 28GB is the max allowed to be created.
 2026-03-27 09:46:51 +01:00
CTCaer b70fcb77e2 Update template with ;/# and newline info 2026-03-27 09:44:58 +01:00
CTCaer 5437f9ce2c nyx: backup/restore UX improvements 
- Fix the verification % and bar if restored backup is smaller than partition
- Use orange bar for restoring when writing to eMMC/emuMMC.
- Fix bar color on restoring after verification
- Allow verification to be aborted for all parts in partial mode (FAT32 or small card)
 2026-03-27 09:44:58 +01:00
CTCaer 87e3ddadf7 nyx: part mgr: remove gpt 126 entries check 
It's done before to validate GPT anyway
 2026-03-27 09:44:58 +01:00
CTCaer 8b7777f25b minerva: update to v1.5 
- "Perf" hack removal (match L4T mini Minerva)
 It's not a performance hack, it just kills low power modes.
 If wanted in L4T, use HP Mode in `ram_oc_opt`.
- Simplify of burst regs config
- Refactor of several bit defines and variables
 2026-03-27 09:44:07 +01:00
CTCaer b0ec8a1e64 l4t: add some missing carveout configs 
Mostly relevant for CARVEOUT_NVDEC_TSEC_ENABLE.
 2026-03-27 09:44:07 +01:00
CTCaer 67157b1867 bdk: ini: switch back to ASCII ordering 
For combining multiple inis.
 2026-03-27 09:44:07 +01:00
CTCaer 23ac454b1d hekate: use the new dirlist 2026-03-27 09:44:07 +01:00
CTCaer af72bb5b94 bdk: dirlist: use flags instead of arguments 
A new flag was also added that forces an ASCII ordering instead of Alphabetical one.
 2026-03-27 09:44:07 +01:00
CTCaer e19cf3038b bdk: minerva: allow sdmmc la to be skipped on L4T 2026-03-27 09:44:07 +01:00
CTCaer b52f5edce6 bdk: hwinit: refactor MBIST WAR & add description 
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
 2026-03-27 09:44:07 +01:00
CTCaer 393d135105 bdk: hwinit: fix RAM_SVOP_PDP try no 2 
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
 2026-03-27 09:44:07 +01:00
CTCaer 6cc3aee389 bdk: storage: small mmc refactoring 
- Correct some Response Type names
- And use _def for mmc defines similarly to sd_def
 2026-03-27 09:44:07 +01:00
CTCaer 7b4b26bb38 hos: use the renamed mc carveout function 2026-03-27 09:44:07 +01:00
CTCaer 030576ff3f bdk: mc: carveouts are not set by cfg so fix them 
For HOS <= 3.0.2 the carveouts are set by bootloader and sdram config actually does not set them.
So add which need different value from reset and also make sure that data is flushed for WPR config.
 2026-03-27 09:44:07 +01:00
CTCaer 44e4c0ab21 bdk: make use of new MC/EMC defines 2026-03-27 09:44:07 +01:00
CTCaer f45adfd92f bdk: rework MC/EMC register defines from scratch 
And add register structs also.
 2026-03-27 09:44:06 +01:00
CTCaer 2fda4115aa bdk: add some t210 and fuses defines 
PGUP tag register can be used to identify which cpu we are running on.
 2026-03-27 09:44:06 +01:00