OmniNX/hekate-pro
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2,045 Commits 3 Branches 63 Tags
1101db8f193d92f0a93c212eba49762cfe047639
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187 Commits

Author SHA1 Message Date
CTCaer
f26e9f0504 bdk: i2c: homogenize return values 2026-03-27 20:16:31 +01:00
CTCaer
476c070cf4 bdk: i2c: optimize packet mode functions 
- Allow xfer packet to send up to 20 bytes before receiving
- Remove interrupt use since it's only polling
- Check proper status for TX finish.
 2026-03-27 20:08:45 +01:00
CTCaer
8f6dce1368 bdk: i2c: refactor 2026-03-27 20:08:45 +01:00
CTCaer
10c2d3d379 bdk: clk: add missing macro 2026-03-27 20:08:45 +01:00
CTCaer
45a08c058f bdk: clk: reduce i2c freq input to save power 2026-03-27 20:08:45 +01:00
CTCaer
aba56fd173 bdk: move exception type base away from IRQ stack 
Allow a more heavy stack usage by IRQ handlers.
 2026-03-27 20:05:57 +01:00
CTCaer
378d38b850 bdk: add missing header guards 2026-03-27 19:38:45 +01:00
CTCaer
b3c95990ed bdk: pmc: refactor register defines and structs 2026-03-27 19:36:58 +01:00
CTCaer
b86701823c bdk: pinmux: always detach I2C4 pins from I2C3 pm 
Generally I2C3 communication can work via I2C3 or I2C4 pins.
Defaults are fine as long as one of the pin groups are floating or grounded or
both share I2C traces.

In NX boards I2C4 SDA is used for GC and connected to 1V8.
So if a GC is slotted, I2C3 works, if not, no communication is possible.

This config was done previously inside I2C3 consumer driver (touchscreen).
Now it's moved inside pinmux_config_i2c.
 2026-03-27 19:36:58 +01:00
CTCaer
aecd657358 bdk: display: reduce display off waiting time 
And align oled panel inside vblank.
Assumes display deinit happens before the rest of deinit.
 2026-03-27 10:02:21 +01:00
CTCaer
4daa02fe85 bdk: hwinit: remove coreboot support 
Everything external is finally updated and beyond parity with old things that needed it.
 2026-03-27 10:00:26 +01:00
CTCaer
2004b38f41 bdk: ccplex: do not disable mselect on cpu pwrgate 2026-03-27 09:57:59 +01:00
CTCaer
46fa18be89 bdk: display: simplify macros 
Expand register index in parent macro and remove _DI/_DSIREG macros.
 2026-03-27 09:57:59 +01:00
CTCaer
c17881f2c3 bdk: display: use spare reg to store dcs bl duty 
And also remove backlight pwm restoring from coreboot hw deinit path.
 2026-03-27 09:57:59 +01:00
CTCaer
ffc0aa2c3d bdk: fuse: return array size with fuse_read_array 2026-03-27 09:57:23 +01:00
CTCaer
03cb1aac29 bdk: clock: update some defines 2026-03-27 09:54:06 +01:00
CTCaer
7b7906efc2 bdk: clock: add i2c to the errata affected list 2026-03-27 09:51:47 +01:00
CTCaer
e29d139946 bdk: fuse: allow overriding dram id fuses 
This should be set before running sdram init.
fuse_read_dramid(true) will still return the real id.
 2026-03-27 09:51:47 +01:00
CTCaer
b862311c0c bdl: minerva: add deinit function 
Removes dependency to Nyx storage for hw init too.
 2026-03-27 09:51:46 +01:00
CTCaer
1eaa801d6a bdk: bpmp: add write commits 
And deduplicate bpmp_clk_rate_relaxed in bpmp_clk_rate_set.
 2026-03-27 09:51:46 +01:00
CTCaer
25359b23b9 bdk: clock: add sdmmc1 to the errata affected list 2026-03-27 09:51:46 +01:00
CTCaer
db08514ff0 bdk: clock: allow pll lock wait to timeout 
Also enable PLLC4 p/f lock and reduce time waiting before disabling.
 2026-03-27 09:51:46 +01:00
CTCaer
877e2c7c2e bdk: clock: improve PLLC init 
- Use 6 as divm and div1 for OUT1 to avoid having very high frequency on OUT0
 There seems to be an undocumented silicon errata where PLLC OUT0 produces EMI
 to input mux logic in modules, even when not using it.
- Always check if PLL is enabled and disable first in order to avoid a silicon
 errata with hybrid PLLs
- Fix PLLC_FLL_LD_MEM value
 2026-03-27 09:51:46 +01:00
CTCaer
fa2d7854d3 bdk: clock: streamline sdmmc func naming 
Additionally, restored the pclock variable because of _clock_sdmmc_config_clock_host store order.
 2026-03-27 09:51:46 +01:00
CTCaer
ac0d98ad29 bdk: clock: use SET/CLR registers for all modules 
This is not mandatory but removes unnecessary load-mask/or-stores.

On the other hand, due to an undocumented T210 silicon errata,
these are mandatory for SDMMC modules.
This is because a fraction of T210 chips can glitch out and cause SoC hang.
T210B01 is not affected.
 2026-03-27 09:51:46 +01:00
CTCaer
a365af0492 bdk: bpmp: add binX clock defines 2026-03-27 09:48:54 +01:00
CTCaer
28dce16877 bdk: fuse: add sense function 2026-03-27 09:48:54 +01:00
CTCaer
f541f14699 bdk: fuse: add extra info on regs 2026-03-27 09:48:54 +01:00
CTCaer
518cfd401a bdk: fuse: correct masking on array read cmd 2026-03-27 09:48:54 +01:00
CTCaer
44dd00c29a bdk: t210: add mc channel macros 2026-03-27 09:48:54 +01:00
CTCaer
b52f5edce6 bdk: hwinit: refactor MBIST WAR & add description 
The biggest take here is that the split approach of having it in Bootrom and
Bootloader is that it's only for boot. Any later powerdown must rerun the WAR
for that particular power domain.
 2026-03-27 09:44:07 +01:00
CTCaer
393d135105 bdk: hwinit: fix RAM_SVOP_PDP try no 2 
Previously the correct reg name was used but register address was not fixed.
So finally fix it.
 2026-03-27 09:44:07 +01:00
CTCaer
2fda4115aa bdk: add some t210 and fuses defines 
PGUP tag register can be used to identify which cpu we are running on.
 2026-03-27 09:44:06 +01:00
CTCaer
d289224653 bdk: clock: simplify logic 
Simplify logic for clock enable and sdmmc clock management
 2026-03-27 09:44:06 +01:00
CTCaer
0647fd06d8 bdk: clock: remove non existent module ids 
And add comments to special handling ones
 2026-03-27 09:44:06 +01:00
CTCaer
d33ded5f6d bdk: pmc: rename pmc_enable_partition 2026-03-27 09:44:06 +01:00
CTCaer
b70932cfaa bdk: clock: wait for PLLD to lock when set 2026-03-27 09:44:06 +01:00
CTCaer
380c1dc9b2 bdk: refactor several comments and defines 2026-03-27 09:05:58 +01:00
CTCaer
2d91e9b549 bdk: clock: refactor common PLL defines 2026-03-27 09:05:58 +01:00
CTCaer
3c6bb75267 bdk: small refactoring 2025-05-13 16:17:31 +02:00
CTCaer
14413ae6bd bdk: timer: restore rtc timer spinlock 2024-10-10 18:22:03 +03:00
CTCaer
edf00d8e51 bdk: bpmp: add state set function 
Some states are controlled via software. So add a function for that.
 2024-10-04 21:54:58 +03:00
CTCaer
1a98e3a702 bdk: irq: disable irq if handler error 2024-10-04 21:53:17 +03:00
CTCaer
8bf3bee08b bdk: uart: fix fifo clear 
- Do not clear fifo for everything if not needed
- Correct fifo clear checks
 2024-10-04 21:52:24 +03:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
e47b6ec19b bdk: hwinit: display changes 
Do not display ldo0 if enabled here as it's not needed.
Make sure PLLP_OUTB is properly reset in case of coming out of warmboot.
 2024-07-02 17:59:14 +03:00
CTCaer
acb3997a7d bdk: hwinit: reorder no io power 
And make sure sdmmc iopower is not enabled after vdd disable.
 2024-07-02 17:56:20 +03:00
CTCaer
054c68f251 bdk: hwinit: power on all relevant rails 
Since that doesn't happen via sdram init anymore, do it in hwinit.
It only matters if we came out of warmboot.
 2024-06-08 12:21:15 +03:00
CTCaer
85eb5489fe bdk: pmc: rename io/det power defines 2024-06-08 12:16:07 +03:00
CTCaer
8b4f776c9d bdk: fan: rename functions and add set from temp 
- Rename functions to proper style (drivername_)
- Add fan_set_from_temp for managing the fan with passed SoC temperature.
 2024-06-07 17:14:05 +03:00