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loader: fix latency and related timings

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This commit is contained in:
hanabbi
2023-09-06 20:02:39 +09:00
parent e7ac97d436
commit ada4c184b5
3 changed files with 21 additions and 21 deletions
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11
Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
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@@ -30,9 +30,6 @@ namespace ams::ldr::oc {
// Preset Six // Preset Six
const std::array<u32, 5> tREFpb_values = {488, 976, 1952, 3256, 9999}; const std::array<u32, 5> tREFpb_values = {488, 976, 1952, 3256, 9999};
// Preset Seven
const std::array<u32, 6> tWL_values = {14, 12, 10, 8, 6, 4};
const u32 TIMING_PRESET_ONE = C.ramTimingPresetOne; const u32 TIMING_PRESET_ONE = C.ramTimingPresetOne;
const u32 TIMING_PRESET_TWO = C.ramTimingPresetTwo; const u32 TIMING_PRESET_TWO = C.ramTimingPresetTwo;
const u32 TIMING_PRESET_THREE = C.ramTimingPresetThree; const u32 TIMING_PRESET_THREE = C.ramTimingPresetThree;
@@ -141,9 +138,9 @@ namespace ams::ldr::oc {
const double tCK_avg = 1000'000. / C.eristaEmcMaxClock; const double tCK_avg = 1000'000. / C.eristaEmcMaxClock;
// Write Latency // Write Latency
const u32 WL = 18 - 2*TIMING_PRESET_SEVEN; //? const u32 WL = 14 - 2*TIMING_PRESET_SEVEN;
// Read Latency // Read Latency
const u32 RL = 40 - 4*TIMING_PRESET_SEVEN; //? const u32 RL = 32 - 4*TIMING_PRESET_SEVEN;
// minimum number of cycles from any read command to any write command, irrespective of bank // minimum number of cycles from any read command to any write command, irrespective of bank
const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6; const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6;
@@ -175,9 +172,9 @@ namespace ams::ldr::oc {
// tCK_avg (average clock period) in ns // tCK_avg (average clock period) in ns
const double tCK_avg = 1000'000. / C.marikoEmcMaxClock; const double tCK_avg = 1000'000. / C.marikoEmcMaxClock;
// Write Latency // Write Latency
const u32 WL = 18 - 2*TIMING_PRESET_SEVEN; //? const u32 WL = 14 - 2*TIMING_PRESET_SEVEN;
// Read Latency // Read Latency
const u32 RL = 40 - 4*TIMING_PRESET_SEVEN; //? const u32 RL = 32 - 4*TIMING_PRESET_SEVEN;
// minimum number of cycles from any read command to any write command, irrespective of bank // minimum number of cycles from any read command to any write command, irrespective of bank
const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)); const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST));

14
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
View File

@@ -153,10 +153,10 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb)); WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb));
WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS)); WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS));
WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb)); WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb));
WRITE_PARAM_ALL_REG(table, emc_r2w, R2W + 8); WRITE_PARAM_ALL_REG(table, emc_r2w, R2W);
WRITE_PARAM_ALL_REG(table, emc_w2r, W2R - 6); WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP)); WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP));
WRITE_PARAM_ALL_REG(table, emc_w2p, WTP - 7); WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
WRITE_PARAM_ALL_REG(table, emc_trtm, RTM); WRITE_PARAM_ALL_REG(table, emc_trtm, RTM);
WRITE_PARAM_ALL_REG(table, emc_twtm, WTM); WRITE_PARAM_ALL_REG(table, emc_twtm, WTM);
WRITE_PARAM_ALL_REG(table, emc_tratm, RATM); WRITE_PARAM_ALL_REG(table, emc_tratm, RATM);
@@ -211,10 +211,10 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_faw, CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_faw, CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rrd, CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rrd, CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rap2pre, CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV)) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rap2pre, CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV))
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_wap2pre, CEIL((WTP-7) / MC_ARB_DIV)) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_wap2pre, CEIL((WTP) / MC_ARB_DIV))
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2r, CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2r, CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W+8) / MC_ARB_DIV) - 1 + MC_ARB_SFA) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R-6) / MC_ARB_DIV) - 1 + MC_ARB_SFA) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rfcpb, CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV)) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rfcpb, CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV))
u32 DA_TURNS = 0; u32 DA_TURNS = 0;
@@ -286,7 +286,7 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
table->dram_timings.t_rp = tRPpb; table->dram_timings.t_rp = tRPpb;
table->dram_timings.t_rfc = tRFCab; table->dram_timings.t_rfc = tRFCab;
table->dram_timings.rl = RL; //table->dram_timings.rl = 32;
table->emc_cfg_2 = 0x0011083d; table->emc_cfg_2 = 0x0011083d;
} }

17
pages/src/main.ts
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@@ -468,13 +468,16 @@ var AdvTable: Array<AdvEntry> = [
4, 4,
["WARNING: Unstable timings can corrupt your nand", ["WARNING: Unstable timings can corrupt your nand",
"Latency decrement for both AUTO_ADJ and CUSTOM_ADJ", "Latency decrement for both AUTO_ADJ and CUSTOM_ADJ",
"Values are : WL - RL", "This preset decreases Write/Read related delays. Values are Write - Read",
"<b>0</b> : 2131Mhz Latency bracket for AUTO_ADJ, Do Not Adjust for CUST_ADJ", "<b>0</b> : 0 - 0, Do Not Adjust for CUST_ADJ",
"<b>1</b> : 1862Mhz Latency", "<b>1</b> : '-2' - '-4'",
"<b>2</b> : 1600Mhz Latency", "<b>2</b> : '-4' - '-8'",
"<b>3</b> : 1331Mhz Latency",], "<b>3</b> : '-6' - '-12'",
1, "<b>4</b> : '-8' - '-16'",
[0,3], "<b>5</b> : '-10' - '-20'",
"<b>6</b> : '-12' - '-24'",],
0,
[0,6],
1, 1,
) )
]; ];