diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp index d9604328..bd49bfb2 100644 --- a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp +++ b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp @@ -30,9 +30,6 @@ namespace ams::ldr::oc { // Preset Six const std::array tREFpb_values = {488, 976, 1952, 3256, 9999}; - // Preset Seven - const std::array tWL_values = {14, 12, 10, 8, 6, 4}; - const u32 TIMING_PRESET_ONE = C.ramTimingPresetOne; const u32 TIMING_PRESET_TWO = C.ramTimingPresetTwo; const u32 TIMING_PRESET_THREE = C.ramTimingPresetThree; @@ -141,9 +138,9 @@ namespace ams::ldr::oc { const double tCK_avg = 1000'000. / C.eristaEmcMaxClock; // Write Latency - const u32 WL = 18 - 2*TIMING_PRESET_SEVEN; //? + const u32 WL = 14 - 2*TIMING_PRESET_SEVEN; // Read Latency - const u32 RL = 40 - 4*TIMING_PRESET_SEVEN; //? + const u32 RL = 32 - 4*TIMING_PRESET_SEVEN; // minimum number of cycles from any read command to any write command, irrespective of bank const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6; @@ -175,9 +172,9 @@ namespace ams::ldr::oc { // tCK_avg (average clock period) in ns const double tCK_avg = 1000'000. / C.marikoEmcMaxClock; // Write Latency - const u32 WL = 18 - 2*TIMING_PRESET_SEVEN; //? + const u32 WL = 14 - 2*TIMING_PRESET_SEVEN; // Read Latency - const u32 RL = 40 - 4*TIMING_PRESET_SEVEN; //? + const u32 RL = 32 - 4*TIMING_PRESET_SEVEN; // minimum number of cycles from any read command to any write command, irrespective of bank const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)); diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp index c417974b..142bca7b 100644 --- a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp +++ b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp @@ -153,10 +153,10 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) { WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb)); WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS)); WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb)); - WRITE_PARAM_ALL_REG(table, emc_r2w, R2W + 8); - WRITE_PARAM_ALL_REG(table, emc_w2r, W2R - 6); + WRITE_PARAM_ALL_REG(table, emc_r2w, R2W); + WRITE_PARAM_ALL_REG(table, emc_w2r, W2R); WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP)); - WRITE_PARAM_ALL_REG(table, emc_w2p, WTP - 7); + WRITE_PARAM_ALL_REG(table, emc_w2p, WTP); WRITE_PARAM_ALL_REG(table, emc_trtm, RTM); WRITE_PARAM_ALL_REG(table, emc_twtm, WTM); WRITE_PARAM_ALL_REG(table, emc_tratm, RATM); @@ -211,10 +211,10 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) { WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_faw, CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rrd, CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rap2pre, CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV)) - WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_wap2pre, CEIL((WTP-7) / MC_ARB_DIV)) + WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_wap2pre, CEIL((WTP) / MC_ARB_DIV)) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2r, CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA) - WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W+8) / MC_ARB_DIV) - 1 + MC_ARB_SFA) - WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R-6) / MC_ARB_DIV) - 1 + MC_ARB_SFA) + WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W) / MC_ARB_DIV) - 1 + MC_ARB_SFA) + WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R) / MC_ARB_DIV) - 1 + MC_ARB_SFA) WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rfcpb, CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV)) u32 DA_TURNS = 0; @@ -286,7 +286,7 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) { table->dram_timings.t_rp = tRPpb; table->dram_timings.t_rfc = tRFCab; - table->dram_timings.rl = RL; + //table->dram_timings.rl = 32; table->emc_cfg_2 = 0x0011083d; } diff --git a/pages/src/main.ts b/pages/src/main.ts index 659834b2..6bdf89c5 100644 --- a/pages/src/main.ts +++ b/pages/src/main.ts @@ -468,13 +468,16 @@ var AdvTable: Array = [ 4, ["WARNING: Unstable timings can corrupt your nand", "Latency decrement for both AUTO_ADJ and CUSTOM_ADJ", - "Values are : WL - RL", - "0 : 2131Mhz Latency bracket for AUTO_ADJ, Do Not Adjust for CUST_ADJ", - "1 : 1862Mhz Latency", - "2 : 1600Mhz Latency", - "3 : 1331Mhz Latency",], - 1, - [0,3], + "This preset decreases Write/Read related delays. Values are Write - Read", + "0 : 0 - 0, Do Not Adjust for CUST_ADJ", + "1 : '-2' - '-4'", + "2 : '-4' - '-8'", + "3 : '-6' - '-12'", + "4 : '-8' - '-16'", + "5 : '-10' - '-20'", + "6 : '-12' - '-24'",], + 0, + [0,6], 1, ) ];