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Adding auto_adj for mariko, timing fix for erista, added mariko dvb to customize.cpp

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Lightos1
2025-10-01 15:31:08 +02:00
parent acf45ffa5e
commit a6422e0b1f
5 changed files with 492 additions and 761 deletions
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8
Source/Atmosphere/stratosphere/loader/source/oc/customize.cpp
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@@ -85,7 +85,7 @@ volatile CustomizeTable C = {
* Not enabled by default.
* This will not work without sys-clk-OC.
*/
.marikoEmcVddqVolt = 0,
.marikoEmcVddqVolt = 600000,
.marikoCpuUV = 0,
@@ -105,6 +105,8 @@ volatile CustomizeTable C = {
.commonGpuVoltOffset = 0,
.marikoEmcDvbShift = 0,
.t1_tRCD = 0,
.t2_tRP = 0,
.t3_tRAS = 0,
@@ -114,7 +116,7 @@ volatile CustomizeTable C = {
.t7_tWTR = 0,
.t8_tREFI = 0,
.mem_burst_latency = 2,
.mem_burst_latency = 0,
// NOTE: These tables should NOT BE USED and are only here as placeholders. Always try and find your own optimal tables.
// Ensure the voltages actually increase or stay the sameot
@@ -386,7 +388,7 @@ volatile CustomizeTable C = {
{ 768000, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
{ 844800, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
{ 921600, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
{ 998400, { }, { 1316991, 8144, -940, 808, -21583, 226 } }, // UNSAFE
{ 998400, { }, { 1316991, 8144, -940, 808, -21583, 226 } }, // POTENTIALLY UNSAFE
{ 1075200, { }, { 1358882, 8144, -940, 808, -21583, 226 } }, // UNSAFE
// { 1152000, { }, { 1400773, 8144, -940, 808, -21583, 226 } }, // DANGEROUS
// { 1228800, { }, { 1440773, 8144, -940, 808, -21583, 226 } }, // DANGEROUS

10
Source/Atmosphere/stratosphere/loader/source/oc/customize.hpp
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@@ -30,12 +30,7 @@
#include "mtc_timing_table.hpp"
enum MtcConfig: u32 {
AUTO_ADJ_ALL = 0,
CUSTOM_ADJ_ALL = 1,
NO_ADJ_ALL = 2,
CUSTOMIZED_ALL = 4,
AUTO_ADJ = 5,
AUTO_ADJ = 0,
};
using CustomizeCpuDvfsTable = pcv::cvb_entry_t[pcv::DvfsTableEntryLimit];
@@ -49,8 +44,7 @@
typedef struct CustomizeTable {
u8 cust[4] = {'C', 'U', 'S', 'T'};
u32 custRev = CUST_REV;
u32 mtcConfErista = AUTO_ADJ;
u32 mtcConfMariko = AUTO_ADJ_ALL; // TODO: Fix mariko and merge into mtcConf
u32 mtcConf = AUTO_ADJ;
u32 commonCpuBoostClock;
u32 commonEmcMemVolt;
u32 eristaCpuMaxVolt;

132
Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
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@@ -58,6 +58,12 @@
// const u32 TIMING_PRESET_SIX = C.ramTimingPresetSix;
// const u32 TIMING_PRESET_SEVEN = C.ramTimingPresetSeven;
// Write Latency
const u32 WL = 14 + C.mem_burst_latency;
// Read Latency
const u32 RL = 32 - C.mem_burst_latency;
// Burst Length
const u32 BL = 16;
@@ -79,21 +85,9 @@
// tRC (ACTIVATE-ACTIVATE command period same bank) in ns
const u32 tRC = tRPpb + tRAS;
const u32 tPPD = 4;
const u32 tRTW = !C.t6_tRTW ? 10 : tWTR_values[C.t6_tRTW-1];
// DQS output access time from CK_t/CK_c
const double tDQSCK_min = 1.5; // TODO: Fix/remove for mariko if needed
// DQS output access time from CK_t/CK_c
const double tDQSCK_max = 3.5; // TODO: Fix/remove for mariko if needed
// Write preamble (tCK)
const double tWPRE = 1.8; // TODO: Fix/remove for mariko if needed
// Read postamble (tCK)
const double tRPST = 0.4; // TODO: Fix/remove for mariko if needed
// WRITE command to first DQS transition(max) (tCK)
const double tDQSS_max = 1.25; // TODO: Fix/remove for mariko if needed
// DQ-to-DQS offset(max) (ns)
const double tDQS2DQ_max = 0.8; // TODO: Fix/remove for mariko if needed
// DQS_t, DQS_c to DQ skew total, per group, per access (DBI Disabled)
const double tDQSQ = 0.18; // TODO: Fix/remove for mariko if needed
// Write-to-Read delay
const u32 tWTR = !C.t7_tWTR ? 10 : tWTR_values[C.t7_tWTR-1];
@@ -104,9 +98,6 @@
// write recovery time
const u32 tWR = !TIMING_PRESET_THREE ? 18 : tWR_values[TIMING_PRESET_THREE-1];
// Read to refresh delay
const u32 tR2REF = tRTP + tRPpb;
// tRCD (RAS-CAS delay) in ns
const u32 tRCD = !C.t1_tRCD ? 18 : tRCD_values[C.t1_tRCD-1];
@@ -115,124 +106,35 @@
// tREFpb (average refresh interval per bank) in ns for 8Gb density
const u32 tREFpb = !C.t8_tREFI ? 488 : tREFpb_values[C.t8_tREFI-1];
// tREFab (average refresh interval all 8 banks) in ns for 8Gb density
// const u32 tREFab = tREFpb * 8;
// tPDEX2WR, tPDEX2RD (timing delay from exiting powerdown mode to a write/read command) in ns
// const u32 tPDEX2 = 10;
// Exit power-down to next valid command delay
const double tXP = 10;
// Delay from valid command to CKE input LOW in ns
const double tCMDCKE = 1.75; // TODO: Fix/remove for mariko if needed
// tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
// Valid clock and CS requirement after CKE input LOW after MRW command
const u32 tMRWCKEL = 14; // TODO: Fix/remove for mariko if needed
// Valid CS requirement after CKE input LOW
const double tCKELCS = 5; // TODO: Fix/remove for mariko if needed
// Valid CS requirement before CKE input HIGH
const double tCSCKEH = 1.75; // TODO: Fix/remove for mariko if needed
const double tXP = 7.5;
// tXSR (SELF REFRESH exit to next valid command delay) in ns
const double tXSR = tRFCab + 7.5;
// tCKE (minimum pulse width(HIGH and LOW pulse width)) in ns
const double tCKE = 7.5; // TODO: Fix/remove for mariko if needed
// Minimum self refresh time (entry to exit)
const u32 tSR = 15;
// tFAW (Four-bank Activate Window) in ns
const u32 tFAW = 40;// !TIMING_PRESET_TWO ? 40 : tFAW_values[TIMING_PRESET_TWO-1]; TOGO
// Valid Clock requirement before CKE Input HIGH in ns
const double tCKCKEH = 1.75; // TODO: Fix/remove for mariko if needed
// #_of_rows per die for 8Gb density
const u32 numOfRows = 131072;
// p78 The first valid data is available RL × t CK + t DQSCK + t DQSQ
//const u32 QUSE = RL + CEIL(tDQSCK_min/tCK_avg + tDQSQ);
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
// emc_clk_period = dram_clk / 2;
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
const u32 REFBW = MIN((u32)65536, REFRESH+64);
namespace pcv::erista {
// tCK_avg (average clock period) in ns
const double tCK_avg = 1000'000. / C.eristaEmcMaxClock;
// Write Latency
const u32 WL = 14 + C.mem_burst_latency;
// Read Latency
const u32 RL = 32 - C.mem_burst_latency;
// minimum number of cycles from any read command to any write command, irrespective of bank
// const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6;
// Delay Time From WRITE-to-READ
// const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg) - 6;
// write-to-precharge time for commands to the same bank in cycles
// const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
// #_of_rows per die for 16Gb density
const u32 numOfRows = 131072;
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
// emc_clk_period = dram_clk / 2;
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.eristaEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
const u32 REFBW = MIN((u32)65536, REFRESH+64);
// Write With Auto Precharge to to Power-Down Entry
// const u32 WTPDEN = WTP + 1 + CEIL(tDQSS_max/tCK_avg) + CEIL(tDQS2DQ_max/tCK_avg) + 6;
// Additional time after t XP hasexpired until the MRR commandmay be issued
// const double tMRRI = tRCD + 3 * tCK_avg;
// tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
// const double tPDEX2MRR = tXP + tMRRI;
}
namespace pcv::mariko {
// tCK_avg (average clock period) in ns
const double tCK_avg = 1000'000. / C.marikoEmcMaxClock;
// Write Latency
const u32 WL = 14 + C.mem_burst_latency;
// Read Latency
const u32 RL = 32 - C.mem_burst_latency;
// minimum number of cycles from any read command to any write command, irrespective of bank
const u32 R2W = WL + BL/2 + 1 + CEIL(tRTW/tCK_avg);
// Delay Time From WRITE-to-READ
const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg);
// write-to-precharge time for commands to the same bank in cycles
const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg);
// Read-To-MRW delay
const u32 RTM = RL + BL/2 + CEIL(tDQSCK_max/tCK_avg) + FLOOR(tRPST) + CEIL(7.5/tCK_avg);
// Write-To-MRW/MRR delay
const u32 WTM = WL + 1 + BL/2 + CEIL(7.5/tCK_avg);
// Read With AP-To-MRW/MRR delay
const u32 RATM = RTM + CEIL(tRTP/tCK_avg) - 8;
// Write With AP-To-MRW/MRR delay
const u32 WATM = WTM + CEIL(tWR/tCK_avg);
// #_of_rows per die for 8Gb density
const u32 numOfRows = 65536;
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
// emc_clk_period = dram_clk / 2;
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
const u32 REFBW = MIN((u32)65536, REFRESH+64);
// Write With Auto Precharge to to Power-Down Entry
const u32 WTPDEN = WTP + 1 + CEIL(tDQSS_max/tCK_avg) + CEIL(tDQS2DQ_max/tCK_avg) + 6;
// Additional time after t XP hasexpired until the MRR commandmay be issued
const double tMRRI = tRCD + 3 * tCK_avg;
// tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
const double tPDEX2MRR = tXP + tMRRI;
}
}

13
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp
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@@ -160,7 +160,7 @@
}
void MemMtcTableAutoAdjust(EristaMtcTable *table) {
if (C.mtcConfErista != AUTO_ADJ)
if (C.mtcConf != AUTO_ADJ)
return;
#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \
@@ -190,6 +190,11 @@
WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW));
WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab));
WRITE_PARAM_ALL_REG(table, emc_trefbw, REFBW);
WRITE_PARAM_ALL_REG(table, emc_tcke, 0x68);
// WRITE_PARAM_ALL_REG(table, emc_r2w, R2W);
// WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
// WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
#define WRITE_PARAM_BURST_MC_REG(TABLE, PARAM, VALUE) TABLE->burst_mc_regs.PARAM = VALUE;
@@ -203,10 +208,10 @@
table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
//table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
//table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
// table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
// table->burst_mc_regs.mc_emem_arb_timing_ccdmw = CEIL(tCCDMW / MC_ARB_DIV) -1 + MC_ARB_SFA;
}

1090
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
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