Lazy timing fix, clean up later
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@@ -42,7 +42,7 @@ namespace ams::ldr::oc {
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const u32 BL = 16;
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/* Base latency for read and write (tWRL). */
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const u32 RL = C.mem_burst_read_latency;
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const u32 RL = C.mem_burst_read_latency - 4; /* (This is a lazy fix for now) */
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const u32 WL = C.mem_burst_write_latency;
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/* Switch uses RL_DBI, todo: get rid of non DBI_RL. */
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