Lazy timing fix, clean up later

This commit is contained in:
Lightos1
2026-01-21 22:45:47 +01:00
parent 2856f6f778
commit 9723fdc2e0

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@@ -42,7 +42,7 @@ namespace ams::ldr::oc {
const u32 BL = 16;
/* Base latency for read and write (tWRL). */
const u32 RL = C.mem_burst_read_latency;
const u32 RL = C.mem_burst_read_latency - 4; /* (This is a lazy fix for now) */
const u32 WL = C.mem_burst_write_latency;
/* Switch uses RL_DBI, todo: get rid of non DBI_RL. */