chore: merge hoc monitor and remove unnessesary files
This commit is contained in:
6
.gitmodules
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6
.gitmodules
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@@ -0,0 +1,6 @@
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||||
[submodule "Source/Horizon-OC-Monitor/lib/Atmosphere-libs"]
|
||||
path = Source/Horizon-OC-Monitor/lib/Atmosphere-libs
|
||||
url = https://github.com/Atmosphere-NX/Atmosphere-libs
|
||||
[submodule "Source/Horizon-OC-Monitor/lib/libultrahand"]
|
||||
path = Source/Horizon-OC-Monitor/lib/libultrahand
|
||||
url = https://github.com/ppkantorski/libultrahand
|
||||
10
Source/Horizon-OC-Monitor/.gitignore
vendored
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10
Source/Horizon-OC-Monitor/.gitignore
vendored
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||||
|
||||
build/
|
||||
|
||||
*.ovl
|
||||
|
||||
*.elf
|
||||
|
||||
*.nacp
|
||||
|
||||
*.nro
|
||||
6
Source/Horizon-OC-Monitor/.gitmodules
vendored
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6
Source/Horizon-OC-Monitor/.gitmodules
vendored
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@@ -0,0 +1,6 @@
|
||||
[submodule "lib/Atmosphere-libs"]
|
||||
path = lib/Atmosphere-libs
|
||||
url = https://github.com/Atmosphere-NX/Atmosphere-libs
|
||||
[submodule "lib/libultrahand"]
|
||||
path = lib/libultrahand
|
||||
url = https://github.com/ppkantorski/libultrahand
|
||||
339
Source/Horizon-OC-Monitor/LICENSE
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339
Source/Horizon-OC-Monitor/LICENSE
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@@ -0,0 +1,339 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 2, June 1991
|
||||
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Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
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242
Source/Horizon-OC-Monitor/Makefile
Normal file
242
Source/Horizon-OC-Monitor/Makefile
Normal file
@@ -0,0 +1,242 @@
|
||||
#---------------------------------------------------------------------------------
|
||||
.SUFFIXES:
|
||||
#---------------------------------------------------------------------------------
|
||||
|
||||
ifeq ($(strip $(DEVKITPRO)),)
|
||||
$(error "Please set DEVKITPRO in your environment. export DEVKITPRO=<path to>/devkitpro")
|
||||
endif
|
||||
|
||||
TOPDIR ?= $(CURDIR)
|
||||
include $(DEVKITPRO)/libnx/switch_rules
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# TARGET is the name of the output
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
#---------------------------------------------------------------------------------
|
||||
APP_TITLE := Status Monitor
|
||||
APP_VERSION := 1.3.2+r3
|
||||
TARGET := $(notdir $(CURDIR))
|
||||
BUILD := build
|
||||
SOURCES := source
|
||||
INCLUDES := include lib/Atmosphere-libs/libstratosphere/source/dmnt lib/Atmosphere-libs/libstratosphere/source
|
||||
NO_ICON := 1
|
||||
#ROMFS := romfs
|
||||
|
||||
# This location should reflect where you place the libultrahand directory (lib can vary between projects).
|
||||
include ${TOPDIR}/lib/libultrahand/ultrahand.mk
|
||||
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# options for code generation
|
||||
#---------------------------------------------------------------------------------
|
||||
ARCH := -march=armv8-a+simd+crc+crypto -mtune=cortex-a57 -mtp=soft -fPIE
|
||||
|
||||
CFLAGS := -g -Wall -Wno-address-of-packed-member -O3 -ffunction-sections -ffast-math -flto -fomit-frame-pointer \
|
||||
-fuse-linker-plugin -finline-small-functions \
|
||||
-fno-strict-aliasing -frename-registers -falign-functions=16 \
|
||||
$(ARCH) $(DEFINES)
|
||||
|
||||
# For compiling Ultrahand Overlay only
|
||||
IS_STATUS_MONITOR_DIRECTIVE := 1
|
||||
CFLAGS += -DIS_STATUS_MONITOR_DIRECTIVE=$(IS_STATUS_MONITOR_DIRECTIVE)
|
||||
|
||||
# Enable appearance overriding
|
||||
UI_OVERRIDE_PATH := /config/status-monitor/
|
||||
CFLAGS += -DUI_OVERRIDE_PATH="\"$(UI_OVERRIDE_PATH)\""
|
||||
|
||||
|
||||
CFLAGS += $(INCLUDE) -D__SWITCH__ -DAPP_VERSION="\"$(APP_VERSION)\""
|
||||
|
||||
CXXFLAGS := $(CFLAGS) -std=c++26 -Wno-dangling-else -fno-unwind-tables -fno-asynchronous-unwind-tables
|
||||
|
||||
ASFLAGS := -g $(ARCH)
|
||||
LDFLAGS = -specs=$(DEVKITPRO)/libnx/switch.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
|
||||
|
||||
LIBS := -lnx
|
||||
|
||||
CXXFLAGS += -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti
|
||||
LDFLAGS += -Wl,--gc-sections -Wl,--as-needed
|
||||
|
||||
|
||||
# For Ensuring Parallel LTRANS Jobs w/ GCC, make -j6
|
||||
CXXFLAGS += -flto -fuse-linker-plugin -flto=6
|
||||
LDFLAGS += -flto=6
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# list of directories containing libraries, this must be the top level containing
|
||||
# include and lib
|
||||
#---------------------------------------------------------------------------------
|
||||
LIBDIRS := $(PORTLIBS) $(LIBNX)
|
||||
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# no real need to edit anything past this point unless you need to add additional
|
||||
# rules for different file extensions
|
||||
#---------------------------------------------------------------------------------
|
||||
ifneq ($(BUILD),$(notdir $(CURDIR)))
|
||||
#---------------------------------------------------------------------------------
|
||||
|
||||
export OUTPUT := $(CURDIR)/$(TARGET)
|
||||
export TOPDIR := $(CURDIR)
|
||||
|
||||
export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
|
||||
$(foreach dir,$(DATA),$(CURDIR)/$(dir))
|
||||
|
||||
export DEPSDIR := $(CURDIR)/$(BUILD)
|
||||
|
||||
CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
|
||||
CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
|
||||
SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
|
||||
BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*)))
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# use CXX for linking C++ projects, CC for standard C
|
||||
#---------------------------------------------------------------------------------
|
||||
ifeq ($(strip $(CPPFILES)),)
|
||||
#---------------------------------------------------------------------------------
|
||||
export LD := $(CC)
|
||||
#---------------------------------------------------------------------------------
|
||||
else
|
||||
#---------------------------------------------------------------------------------
|
||||
export LD := $(CXX)
|
||||
#---------------------------------------------------------------------------------
|
||||
endif
|
||||
#---------------------------------------------------------------------------------
|
||||
|
||||
export OFILES_BIN := $(addsuffix .o,$(BINFILES))
|
||||
export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
|
||||
export OFILES := $(OFILES_BIN) $(OFILES_SRC)
|
||||
export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES)))
|
||||
|
||||
export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
|
||||
$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
|
||||
-I$(CURDIR)/$(BUILD)
|
||||
|
||||
export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib)
|
||||
|
||||
ifeq ($(strip $(CONFIG_JSON)),)
|
||||
jsons := $(wildcard *.json)
|
||||
ifneq (,$(findstring $(TARGET).json,$(jsons)))
|
||||
export APP_JSON := $(TOPDIR)/$(TARGET).json
|
||||
else
|
||||
ifneq (,$(findstring config.json,$(jsons)))
|
||||
export APP_JSON := $(TOPDIR)/config.json
|
||||
endif
|
||||
endif
|
||||
else
|
||||
export APP_JSON := $(TOPDIR)/$(CONFIG_JSON)
|
||||
endif
|
||||
|
||||
ifeq ($(strip $(ICON)),)
|
||||
icons := $(wildcard *.jpg)
|
||||
ifneq (,$(findstring $(TARGET).jpg,$(icons)))
|
||||
export APP_ICON := $(TOPDIR)/$(TARGET).jpg
|
||||
else
|
||||
ifneq (,$(findstring icon.jpg,$(icons)))
|
||||
export APP_ICON := $(TOPDIR)/icon.jpg
|
||||
endif
|
||||
endif
|
||||
else
|
||||
export APP_ICON := $(TOPDIR)/$(ICON)
|
||||
endif
|
||||
|
||||
ifeq ($(strip $(NO_ICON)),)
|
||||
export NROFLAGS += --icon=$(APP_ICON)
|
||||
endif
|
||||
|
||||
ifeq ($(strip $(NO_NACP)),)
|
||||
export NROFLAGS += --nacp=$(CURDIR)/$(TARGET).nacp
|
||||
endif
|
||||
|
||||
ifneq ($(APP_TITLEID),)
|
||||
export NACPFLAGS += --titleid=$(APP_TITLEID)
|
||||
endif
|
||||
|
||||
ifneq ($(ROMFS),)
|
||||
export NROFLAGS += --romfsdir=$(CURDIR)/$(ROMFS)
|
||||
endif
|
||||
|
||||
.PHONY: $(BUILD) clean all
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
all: $(BUILD)
|
||||
|
||||
|
||||
$(BUILD):
|
||||
@[ -d $@ ] || mkdir -p $@
|
||||
@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
|
||||
@rm -rf out/
|
||||
@mkdir -p out/switch/.overlays/
|
||||
@cp -a $(CURDIR)/config out/
|
||||
@cp $(CURDIR)/$(TARGET).ovl out/switch/.overlays/$(TARGET).ovl
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
clean:
|
||||
@echo "Cleanning ... $(TARGET)"
|
||||
@rm -fr $(BUILD) $(TARGET).ovl $(TARGET).nro $(TARGET).nacp $(TARGET).elf
|
||||
@rm -rf out/
|
||||
@rm -f $(TARGET).zip
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
dist: all
|
||||
@echo making dist ...
|
||||
@rm -f $(TARGET).zip
|
||||
@cd out; zip -r ../$(TARGET).zip ./*; cd ../
|
||||
#---------------------------------------------------------------------------------
|
||||
else
|
||||
.PHONY: all
|
||||
|
||||
DEPENDS := $(OFILES:.o=.d)
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# main targets
|
||||
#---------------------------------------------------------------------------------
|
||||
all : $(OUTPUT).ovl
|
||||
|
||||
$(OUTPUT).ovl : $(OUTPUT).elf $(OUTPUT).nacp
|
||||
@elf2nro $< $@ $(NROFLAGS)
|
||||
@echo "built ... $(notdir $(OUTPUT).ovl)"
|
||||
@printf 'ULTR' >> $@
|
||||
@printf "Ultrahand signature has been added.\n"
|
||||
|
||||
$(OUTPUT).elf : $(OFILES)
|
||||
|
||||
$(OFILES_SRC) : $(HFILES_BIN)
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# you need a rule like this for each extension you use as binary data
|
||||
#---------------------------------------------------------------------------------
|
||||
%.bin.o %_bin.h : %.bin
|
||||
#---------------------------------------------------------------------------------
|
||||
@echo $(notdir $<)
|
||||
@$(bin2o)
|
||||
|
||||
-include $(DEPENDS)
|
||||
|
||||
#---------------------------------------------------------------------------------------
|
||||
endif
|
||||
#---------------------------------------------------------------------------------------
|
||||
62
Source/Horizon-OC-Monitor/README.md
Normal file
62
Source/Horizon-OC-Monitor/README.md
Normal file
@@ -0,0 +1,62 @@
|
||||
# Status Monitor Overlay
|
||||
Monitor Your hardware in real time!
|
||||
|
||||
This is an overlay homebrew dedicated to Nintendo Switch.
|
||||
You need to have installed Tesla environment to use it.
|
||||
|
||||
Tool contains five menus to choose, each one is explained [here](/docs/modes.md).<br>
|
||||
Overlay supports customizations through config file, more [here](/docs/config.md).
|
||||
|
||||
If it's not working in dock, you need to first start Status Monitor, then put Nintendo Switch to dock.
|
||||
|
||||
# What is currently supported:
|
||||
- CPU Usage for each core (Cores `#0`-`#2` are used by apps/games, Core `#3` is used by OS, background processes and also Tesla overlays)
|
||||
- GPU Load
|
||||
- CPU, GPU & RAM target frequencies (also real frequencies + RAM Load if [sys-clk 2.0.0_rc4+](https://github.com/retronx-team/sys-clk/releases) is installed, use only official RetroNX release for reliable results)
|
||||
- Used RAM categorized to: (not supported by FWs <5.0.0)
|
||||
- Total
|
||||
- Application
|
||||
- Applet
|
||||
- System
|
||||
- System Unsafe
|
||||
- SoC, PCB & Skin temperatures (Skin temperature not supported by FWs <5.0.0)
|
||||
- Fan Rotation Level
|
||||
- PFPS, FPS, resolutions, game read speed (shows only if [my fork of SaltyNX](https://github.com/masagrator/SaltyNX/releases) is installed)
|
||||
- Battery temperature, raw charge, age, average voltage, average current flow and average power flow
|
||||
- Charger type, max voltage, and max current
|
||||
- DSP usage (only for FW older than 17.0.0)
|
||||
- NVDEC, NVENC and NVJPG clock rates
|
||||
- Network type + Wi-fi password
|
||||
|
||||
# Requirements:
|
||||
- Ultrahand Overlay or Tesla Menu (version >=1.2.3)
|
||||
|
||||
How to setup everything: [HERE](https://gist.github.com/masagrator/65fcbd5ad09243399268d145aaab899b)
|
||||
|
||||
---
|
||||
|
||||
# Thanks to:
|
||||
- RetroNX channel for helping with coding stuff
|
||||
- SunTheCourier for sys-clk-Overlay from which I learned how to make my own Tesla homebrew
|
||||
- Herbaciarz for providing screenshots from HDMI Grabber
|
||||
- KazushiMe for writing code to read registers from max17050 chip
|
||||
- CTCaer for Hekate from which I took max17050.h and calculation formulas for reading battery stats from max17050 chip
|
||||
- ChanseyIsTheBest for testing Game Resolutions menu
|
||||
|
||||
# FAQ:
|
||||
Q: This homebrew has any impact on games?
|
||||
|
||||
A: Negligible, you won't see any difference. Almost everything is done on Core `#3`, other cores usage is below 0.001%.
|
||||
|
||||
# Troubleshooting:
|
||||
|
||||
Q: When opening Full or Mini mode, overlay is showing that Core #3 usage is at 100% while everything else is showing 0, eventually leading to crash. Why this happens?
|
||||
|
||||
A: There are few possible explanations:
|
||||
1. You're using nifm services connection test patches (in short `nifm ctest patches`) that are included in various packs. Those patches allow to connect to network that has no internet connection. But they cause nifm to randomly rampage when connected to network. Find any folder in `atmosphere/exefs_patches` that has in folder name `nifm`, `nfim` and/or `ctest`, delete this folder and restart Switch (if you are using `sys-patch`, turn off `nifm` patching). If you must use it, only solution is to use this overlay only in airplane mode.
|
||||
2. You're using some untested custom sysmodule that has no proper thread sleeping implemented. Find out in atmosphere/contents any sysmodule that you don't need, delete it and restart Switch.
|
||||
3. Your Switch is using sigpatches, is not a primary device, is using linked account, and is connected to network. Delete sigpatches, change your Switch to primary device, unlink account, or disable Wi-Fi.
|
||||
|
||||
Q: When opening Status Monitor overlays stop responding, or something that I am trying to open while Status Monitor is opened is freezing (f.e. Album or HB Menu). How to fix this?
|
||||
|
||||
A: Issue comes from too much sysmodules accessing sdcard at once. You must limit amount of sysmodules that have such access (you can free one session by disabling logs in SaltyNX-Tool).
|
||||
@@ -0,0 +1,127 @@
|
||||
[status-monitor]
|
||||
battery_avg_iir_filter=false
|
||||
battery_time_left_refreshrate=60
|
||||
average_gpu_load=false
|
||||
use_old_fps_average=false
|
||||
|
||||
[full]
|
||||
refresh_rate=1
|
||||
layer_width_align=left
|
||||
show_real_freqs=true
|
||||
show_deltas=true
|
||||
show_target_freqs=true
|
||||
show_fps=true
|
||||
show_res=true
|
||||
show_read_speed=true
|
||||
use_dynamic_colors=true
|
||||
disable_screenshots=false
|
||||
separator_color=#888F
|
||||
cat_color_1=#8FFF
|
||||
cat_color_2=#8CFF
|
||||
text_color=#FFFF
|
||||
|
||||
[mini]
|
||||
refresh_rate=1
|
||||
handheld_font_size=15
|
||||
docked_font_size=15
|
||||
spacing=8
|
||||
real_freqs=true
|
||||
real_volts=true
|
||||
show_full_cpu=false
|
||||
show_full_res=true
|
||||
show_fan_percentage=true
|
||||
show_soc_voltage=false
|
||||
use_dynamic_colors=true
|
||||
show_vddq=false
|
||||
show_vdd2=true
|
||||
decimal_vdd2=false
|
||||
show_dtc=true
|
||||
use_dtc_symbol=true
|
||||
dtc_format=%m-%d-%Y%H:%M:%S
|
||||
show=DTC+BAT+CPU+GPU+RAM+TMP+FPS+RES
|
||||
replace_MB_with_RAM_load=true
|
||||
show_RAM_load_CPU_GPU=false
|
||||
invert_battery_display=true
|
||||
disable_screenshots=false
|
||||
sleep_exit=false
|
||||
frame_offset_x=10
|
||||
frame_offset_y=10
|
||||
frame_padding=10
|
||||
background_color=#0009
|
||||
focus_background_color=#000F
|
||||
separator_color=#888F
|
||||
cat_color=#2DFF
|
||||
text_color=#FFFF
|
||||
|
||||
[micro]
|
||||
refresh_rate=1
|
||||
layer_height_align=top
|
||||
handheld_font_size=15
|
||||
docked_font_size=15
|
||||
text_align=center
|
||||
real_freqs=true
|
||||
real_volts=true
|
||||
show_full_cpu=false
|
||||
show_full_res=false
|
||||
show_soc_voltage=true
|
||||
use_dynamic_colors=true
|
||||
show_vddq=false
|
||||
show_vdd2=true
|
||||
decimal_vdd2=false
|
||||
show_dtc=true
|
||||
use_dtc_symbol=true
|
||||
dtc_format=%H:%M:%S
|
||||
show=FPS+CPU+GPU+RAM+SOC+BAT+DTC
|
||||
replace_GB_with_RAM_load=true
|
||||
invert_battery_display=false
|
||||
disable_screenshots=false
|
||||
sleep_exit=false
|
||||
background_color=#0009
|
||||
separator_color=#888F
|
||||
cat_color=#2DFF
|
||||
text_color=#FFFF
|
||||
|
||||
[fps-counter]
|
||||
refresh_rate=30
|
||||
handheld_font_size=40
|
||||
docked_font_size=40
|
||||
use_integer_counter=false
|
||||
disable_screenshots=false
|
||||
frame_offset_x=10
|
||||
frame_offset_y=10
|
||||
frame_padding=10
|
||||
background_color=#0009
|
||||
focus_background_color=#000F
|
||||
text_color=#8CFF
|
||||
|
||||
[fps-graph]
|
||||
refresh_rate=30
|
||||
show_info=false
|
||||
use_dynamic_colors=true
|
||||
disable_screenshots=false
|
||||
frame_offset_x=10
|
||||
frame_offset_y=10
|
||||
frame_padding=10
|
||||
background_color=#0009
|
||||
focus_background_color=#000F
|
||||
fps_counter_color=#888C
|
||||
border_color=#2DFF
|
||||
dashed_line_color=#8888
|
||||
main_line_color=#FFFF
|
||||
rounded_line_color=#F0FF
|
||||
perfect_line_color=#0C0F
|
||||
max_fps_text_color=#FFFF
|
||||
min_fps_text_color=#FFFF
|
||||
text_color=#FFFF
|
||||
cat_color=#0F0F
|
||||
|
||||
[game_resolutions]
|
||||
refresh_rate=10
|
||||
disable_screenshots=false
|
||||
frame_offset_x=10
|
||||
frame_offset_y=10
|
||||
frame_padding=10
|
||||
background_color=#0009
|
||||
focus_background_color=#000F
|
||||
cat_color=#8FFF
|
||||
text_color=#FFFF
|
||||
103
Source/Horizon-OC-Monitor/docs/config.md
Normal file
103
Source/Horizon-OC-Monitor/docs/config.md
Normal file
@@ -0,0 +1,103 @@
|
||||
# Configuration file
|
||||
|
||||
Configuration file is in `sdmc:/config/status-monitor/`. By default it's named `config.ini.template`. To be detected by overlay it must be renamed to `config.ini`.
|
||||
|
||||
---
|
||||
|
||||
Explanation of what each setting does.<br>
|
||||
Colors are provided in RGBA4444 format, which means that each character represents different channel: red, green, blue, alpha.
|
||||
|
||||
> [status-monitor]
|
||||
|
||||
| Key | Explanation | Possible values | Default Value |
|
||||
|-----|-------------|-----------------|---------------|
|
||||
| `key_combo` | Buttons combination that allows exiting Full, Mini, Micro, FPS Graph and FPS Counter modes; max 4 buttons, otherwise next buttons will be ignored. Combine different buttons with `+` | `A`, `B`, `X`, `Y`, `L`, `R`, `ZL`, `ZR`, `PLUS`, `MINUS`, `DUP`, `DDOWN`, `DLEFT`, `DRIGHT`, `SL`, `SR`, `LSTICK`, `RSTICK`, `UP`, `DOWN`, `LEFT`, `RIGHT` | `L+DDOWN+RSTICK` |
|
||||
| `battery_avg_iir_filter` | Read voltage + current averages directly from fuel gauge, that uses infinite impulse response filter | `true`, `false` | `false` |
|
||||
| `battery_time_left_refreshrate` | How many seconds must pass to refresh Battery Remaining Time | from `1` to `60` | `60` |
|
||||
| `average_gpu_load` | Average 5 last GPU load readings. Because GPU load by design shows only load for last 1/60s, this option allows for more accurate gpu load readings at the cost of slight bump in CPU Core #3 usage (from 2 to 4 percentage points depending on CPU clock). | `true`, `false` | `false` |
|
||||
| `font_cache` | Allow caching generated glyphs for better performance. Cache is cleaned up when moving between modes. | `true`, `false` | `true` |
|
||||
|
||||
|
||||
> [full]
|
||||
|
||||
| Key | Explanation | Possible values | Default Value |
|
||||
|-----|-------------|-----------------|---------------|
|
||||
| `refresh_rate` | How often per second this mode should be refreshed. Higher value means higher CPU Core #3 usage, that's why it is recommended to stay at 1. | From `1` to `60` | `1` |
|
||||
| `layer_width_align` | On which side of the screen X axis you want this mode | `left`, `right` | `left` |
|
||||
| `show_real_freqs` | This works only if you have sys-clk 2.0.0_rc4+ installed. Show real frequencies for CPU, GPU and RAM | `false`, `true` | `true` |
|
||||
| `show_deltas` | This works only if you have sys-clk 2.0.0_rc4+ installed. Show difference for CPU, GPU and RAM between target frequencies and real frequencies. They are not showed if both keys `show_real_freqs` and `show_target_freqs` are set to `false` | `false`, `true` | `true` |
|
||||
| `show_target_freqs` | Show target frequencies for CPU, GPU and RAM | `false`, `true` | `true` |
|
||||
| `show_fps` | Show game's FPS and PFPS | `false`, `true` | `true` |
|
||||
| `show_res` | Show game's 2 best candidates for internal resolution, it won't show when game is not using NVN | `false`, `true` | `true` |
|
||||
| `show_read_speed` | Show game's read speed per second | `false`, `true` | `true` |
|
||||
|
||||
> [mini]
|
||||
|
||||
| Key | Explanation | Possible values | Default Value |
|
||||
|-----|-------------|-----------------|---------------|
|
||||
| `refresh_rate` | How often per second this mode should be refreshed. Higher value means higher CPU Core #3 usage, that's why it is recommended to stay at 1. | From `1` to `60` | `1` |
|
||||
| `layer_width_align` | On which side of the screen X axis you want this mode | `left`, `center`, `right` | `left` |
|
||||
| `layer_height_align` | On which side of the screen Y axis you want this mode | `top`, `center`, `bottom` | `top` |
|
||||
| `handheld_font_size` | How big should be rendered text in handheld mode | From `8` to `22` | `15` |
|
||||
| `docked_font_size` | How big should be rendered text in docked mode | From `8` to `22` | `15` |
|
||||
| `real_freqs` | This works only if you have sys-clk 2.0.0_rc4+ installed. It shows real frequencies for CPU, GPU and RAM instead of target frequencies | `true`, `false` | `false` |
|
||||
| `show` | Which data should be rendered. Connect different stats with `+` in any order. | `CPU`, `GPU`, `RAM`, `TEMP`, `FAN`, `DRAW`, `FPS`, `RES`, `READ` | `CPU+GPU+RAM+TEMP+FAN+DRAW+FPS+RES+READ` |
|
||||
| `replace_MB_with_RAM_load` | This works only if you have sys-clk 2.0.0_rc4+ installed. Instead of RAM total usage it shows RAM load. | `true`, `false` | `true` |
|
||||
| `background_color` | Background color in RGBA4444 format | From `#0000` to `#FFFF` | `#1117` |
|
||||
| `cat_color` | Category text color (left side) in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
| `text_color` | Stats text color (right side) in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
|
||||
> [micro]
|
||||
|
||||
| Key | Explanation | Possible values | Default Value |
|
||||
|-----|-------------|-----------------|---------------|
|
||||
| `refresh_rate` | How often per second this mode should be refreshed. Higher value means higher CPU Core #3 usage, that's why it is recommended to stay at 1. | From `1` to `60` | `1` |
|
||||
| `layer_height_align` | On which side of the screen Y axis you want this mode | `top`, `bottom` | `top` |
|
||||
| `handheld_font_size` | How big should be rendered text in handheld mode | From `8` to `18` | `18` |
|
||||
| `docked_font_size` | How big should be rendered text in docked mode | From `8` to `18` | `18` |
|
||||
| `text_align` | How shown text should be aligned | `left`, `center`, `right`| `center` |
|
||||
| `real_freqs` | This works only if you have sys-clk 2.0.0_rc4+ installed. It shows real frequencies for CPU, GPU and RAM instead of target frequencies | `true`, `false` | `false` |
|
||||
| `show` | Which data should be rendered. Connect different stats with `+` in any order. | `CPU`, `GPU`, `RAM`, `BRD`, `FAN`, `FPS` | `CPU+GPU+RAM+BRD+FAN+FPS` |
|
||||
| `replace_GB_with_RAM_load` | This works only if you have sys-clk 2.0.0_rc4+ installed. Instead of RAM total usage it shows RAM load. | `true`, `false` | `true` |
|
||||
| `background_color` | Background color in RGBA4444 format | From `#0000` to `#FFFF` | `#1117` |
|
||||
| `cat_color` | Category text color (left side) in RGBA4444 format | From `#0000` to `#FFFF` | `#FCCF` |
|
||||
| `text_color` | Stats text color (right side) in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
|
||||
|
||||
> [fps-counter]
|
||||
|
||||
| Key | Explanation | Possible values | Default Value |
|
||||
|-----|-------------|-----------------|---------------|
|
||||
| `layer_width_align` | On which side of the screen X axis you want this mode | `left`, `center`, `right` | `left` |
|
||||
| `layer_height_align` | On which side of the screen Y axis you want this mode | `top`, `center`, `bottom` | `top` |
|
||||
| `handheld_font_size` | How big should be rendered text in handheld mode | From `8` to `150` | `40` |
|
||||
| `docked_font_size` | How big should be rendered text in docked mode | From `8` to `150` | `40` |
|
||||
| `background_color` | Background color in RGBA4444 format | From `#0000` to `#FFFF` | `#1117` |
|
||||
| `text_color` | Text color in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
|
||||
> [fps-graph]
|
||||
|
||||
| Key | Explanation | Possible values | Default Value |
|
||||
|-----|-------------|-----------------|---------------|
|
||||
| `layer_width_align` | On which side of the screen X axis you want this mode | `left`, `center`, `right` | `left` |
|
||||
| `layer_height_align` | On which side of the screen Y axis you want this mode | `top`, `center`, `bottom` | `top` |
|
||||
| `max_fps_text_color` | Text color of "60" in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
| `min_fps_text_color` | Text color of "0" in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
| `background_color` | Background color in RGBA4444 format | From `#0000` to `#FFFF` | `#1117` |
|
||||
| `fps_counter_color` | Text color of average FPS printed behind graph in RGBA4444 format | From `#0000` to `#FFFF` | `#4444` |
|
||||
| `border_color` | Color of rectangle in RGBA4444 format | From `#0000` to `#FFFF` | `#F77F` |
|
||||
| `dashed_line_color` | Color of dashed line at the center of rectangle in RGBA4444 format | From `#0000` to `#FFFF` | `#8888` |
|
||||
| `main_line_color` | Color of line representing FPS value on graph in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
| `rounded_line_color` | Color of line representing FPS value on graph if it's divisble by 10 in RGBA4444 format | From `#0000` to `#FFFF` | `#F0FF` |
|
||||
| `perfect_line_color` | Color of line representing FPS value on graph if it's divisble by 30 in RGBA4444 format | From `#0000` to `#FFFF` | `#0C0F` |
|
||||
|
||||
> [game_resolutions]
|
||||
|
||||
| Key | Explanation | Possible values | Default Value |
|
||||
|-----|-------------|-----------------|---------------|
|
||||
| `refresh_rate` | How often per second this mode should be refreshed. Higher value means higher CPU Core #3 usage, that's why it is recommended to stay at 1. | From `1` to `60` | `10` |
|
||||
| `layer_width_align` | On which side of the screen X axis you want this mode | `left`, `center`, `right` | `left` |
|
||||
| `layer_height_align` | On which side of the screen Y axis you want this mode | `top`, `center`, `bottom` | `top` |
|
||||
| `background_color` | Background color in RGBA4444 format | From `#0000` to `#FFFF` | `#1117` |
|
||||
| `cat_color` | Category text color (left side) in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
| `text_color` | Stats text color (right side) in RGBA4444 format | From `#0000` to `#FFFF` | `#FFFF` |
|
||||
252
Source/Horizon-OC-Monitor/docs/modes.md
Normal file
252
Source/Horizon-OC-Monitor/docs/modes.md
Normal file
@@ -0,0 +1,252 @@
|
||||
# Modes
|
||||
|
||||
Status Monitor Overlay from 1.0.0 release contains five modes to choose from Main Menu.<br>
|
||||
For additional functions you need to install:
|
||||
- [SaltyNX](https://github.com/masagrator/SaltyNX/releases)
|
||||
- [sys-clk 2.0.0_rc4+](https://github.com/retronx-team/sys-clk/releases) (using closed source forks of sys-clk can result in retrieving wrong real clockrates and ram load)
|
||||
|
||||
# Full
|
||||
|
||||
This mode you can know from older releases of Status Monitor. It contains all informations properly described and supported with high precision.
|
||||
|
||||
- CPU Usage
|
||||
- Real Frequency: `%.1f` = Real clockrate of all CPU cores in MHz (This shows only when sys-clk 2.0.0_4c+ is installed)
|
||||
- Target Frequency: `%.1f` = Target clockrate of all CPU cores in MHz
|
||||
- Core #0-#3: `%.2f` = Load of CPU Cores calculated from IdleTickCount to percent value
|
||||
|
||||
- GPU Usage
|
||||
- Real Frequency: `%.1f` = Real clockrate of GPU in MHz (This shows only when sys-clk 2.0.0_rc4+ is installed)
|
||||
- Target Frequency: `%.1f` = Target clockrate of GPU in MHz
|
||||
- Load: `%.1f` = GPU Load provided by PMU in percent
|
||||
|
||||
- RAM Usage
|
||||
- Real Frequency: `%.1f` = Real clockrate of EMC in MHz (This shows only when sys-clk 2.0.0_rc4+ is installed)
|
||||
- Target Frequency: `%.1f` = Target clockrate of EMC in MHz
|
||||
- Load: `%.1f` (CPU `%.1f` | GPU `%.1f`) = RAM Load in % (Which part of that are CPU and GPU (with other hardware, but their impact on GPU readings is negligible))
|
||||
- `%s`: `%.2f`/`%.2f` = %s memory used/%s memory available in MB (not working with FW <5.0.0)
|
||||
|
||||
- Board
|
||||
- Battery Power Flow: `%+.2f`[h:mm] = How much power in watts is discharged from or charged to the battery [time left before shutdown]
|
||||
- Temperatures: SoC: `%.1f` / PCB: `%.1f` / Skin: `%.1f` = SoC / PCB / Skin temperature in Celsius degrees (Explanation provided at the end of file)
|
||||
- Fan Rotation Level: `%.1f` = Fan rotation level in percent
|
||||
|
||||
|
||||
```Optional (shows only when SaltyNX is installed and game is running)```
|
||||
|
||||
| Category | Format | Explanation |
|
||||
|----------|-------------------|--------------------------------------------------------------------------|
|
||||
| PFPS | %u | Pushed Frames Per Second - how many frames were displayed in last second |
|
||||
| FPS | %.2f | Frames Per Second - value calculated by averaging frametime |
|
||||
| Resolutions | %dx%d \|\| %dx%d | Two the most promising candidates for internal game resolution `(^1)` |
|
||||
| Read speed | %.2f MiB/s | Show game read speed in the last second |
|
||||
|
||||
- ^1 - read more informations in explanation for "Game Resolutions" menu
|
||||
|
||||
# Mini
|
||||
|
||||
Contains most of supported informations with lower precision. You can use touch screen to change its position temporarily.
|
||||
|
||||
| Category | Format | Explanation |
|
||||
|----------|---------------------------------------------------|---------------------------------------------------------------------------|
|
||||
| CPU | [%.0f,%.0f,%.0f,%.0f]@%.1f | Core #0 usage, Core #1 usage, Core #2 usage, Core #3 usage@CPU Target/Real frequency`(^1)` |
|
||||
| GPU | %.1f@%.1f | Load@GPU Target/Real Frequency`(^1)` |
|
||||
| RAM | %.0f/%.0f@%.1f<br>`or`<br>%.1f(%.1f \| %.1f)@%.1f | Total RAM used/Total RAM available in MB@EMC Target/Real frequency `or` RAM load (CPU \| GPU)@EMC Target frequency `(^1)` |
|
||||
| TEMP | %2.1f/%2.1f/%2.1f | SoC temperature/PCB temperature/Skin temperature `(^2)` |
|
||||
| FAN | %2.1f | Fan rotation level |
|
||||
| DRAW | %+.2f[h:mm] | How much power in watts is discharged from or charged to the battery [Time left before shutdown] |
|
||||
| RES | %dx%d \|\| %dx%d | Two the most promising candidates for internal game resolution `(^3)` |
|
||||
| READ | %.2f MiB/s | Show game read speed in the last second |
|
||||
|
||||
- ^1 - Real Frequency + RAM Load available only with sys-clk 2.0.0_rc4+
|
||||
- ^2 - Explanation provided at the end of file
|
||||
- ^3 - read more informations in explanation for "Game Resolutions" menu
|
||||
|
||||
```Optional```
|
||||
|
||||
> shows only when SaltyNX is installed and game is running
|
||||
>
|
||||
| Category | Format | Explanation |
|
||||
|----------|-------------------|--------------------------------------------------------------------------|
|
||||
| FPS | %.2f | Frames Per Second |
|
||||
|
||||
# Micro
|
||||
|
||||
Contains most of supported informations with lower precision in one line.
|
||||
|
||||
| Category | Format | Explanation |
|
||||
|----------|------------------------------------------------------------|---------------------------------------------------------------------------|
|
||||
| CPU | [%.0f,%.0f,%.0f,%.0f]%s%.1f | [Core #0 usage, Core #1 usage, Core #2 usage, Core #3 usage] `(^1)` CPU Target/Real Frequency `(^3)` |
|
||||
| GPU | %.1f%s%.1f | Load (^1) GPU Target/Real Frequency |
|
||||
| RAM | %.1f/%.1f%s%.1f `or` %.1f%s%.1f | Total RAM used/Total RAM available in GB `(^1)` EMC Target frequency `or` RAM Load in % `(^1)` EMC Target frequency |
|
||||
| BRD | %2.1f/%2.1f/%2.1f@+.1f[h:mm] | SoC temperature/PCB temperature/Skin temperature(^2)/Battery Power Flow[Time left before shutdown] |
|
||||
| FAN | %2.1f | Fan rotation level |
|
||||
|
||||
- ^1 - by default it's `@`, but if you have sys-clk 2.0.0_rc4+ installed, this changes depending on difference between real clocks and targeted clocks. <br>
|
||||
- `△` - real clocks are higher by at least 20 MHz than expected
|
||||
- `▽` - real clocks are lower by at least 20 MHz than expected
|
||||
- `≠` - real clocks are lower by at least 50 MHz than expected (If this shows constantly for longer than few seconds, this is a sign of throttling, usually caused by bad overclocking configuration)
|
||||
- ^2 - Explanation provided at the end of file
|
||||
- ^3 - Real frequencies + RAM Load available only with sys-clk 2.0.0_rc4+
|
||||
|
||||
```Optional```
|
||||
|
||||
> shows only when SaltyNX is installed and game is running
|
||||
|
||||
| Category | Format | Explanation |
|
||||
|----------|--------------------|--------------------------------------------------------------------------|
|
||||
| FPS | %.1f | Frames Per Second |
|
||||
|
||||
|
||||
# FPS
|
||||
|
||||
> Counter
|
||||
|
||||
It shows only FPS value in 31Hz + vsync signal. <br>
|
||||
If game is not launched, it will show always `n/d` aka `no data`.<br>
|
||||
|
||||
Mode available only with SaltyNX installed. You can use touch screen to change its position temporarily.
|
||||
|
||||
> Graph
|
||||
|
||||
It shows average FPS graph in 31Hz + vsync signal. In background of graph you can see rendered actual average FPS.<br>
|
||||
If game is not launched, graph will be empty.<br>
|
||||
If game is not rendering any new frame, graph is not updated.
|
||||
|
||||
If line is within rounding error of graph line, it's colored. Average FPS must be between -0.05 and +0.04 of graph line target FPS. So for 30 FPS it's between 29.95 - 30.04 FPS. For 43 FPS it's 42.95 - 43.04 FPS.
|
||||
If it's in display refresh rate or half of it rounding error range, it's green. Any other FPS graph target is purple.
|
||||
|
||||
Colors can be changed in config file.
|
||||
|
||||
Mode available only with SaltyNX installed. You can use touch screen to change its position temporarily.
|
||||
|
||||
# Other
|
||||
|
||||
> Battery
|
||||
|
||||
- Battery Actual Capacity: `%d` = Battery Designed Capacity multiplied by Battery Age in mAh
|
||||
- Battery Designed Capacity: `%d` = Battery capacity targeted by manufacturer in mAh
|
||||
- Battery Temperature: `%.1f` = Battery temperature in Celsius
|
||||
- Battery Raw Charge: `%.1f` = Raw battery charged capacity in percent
|
||||
- Battery Age: `%.1f` = How much of designed capacity was charged last time battery was charged completely in percent
|
||||
- Battery Voltage: `%.0f` = Battery average voltage in mV (time period: 5s, or with `battery_avg_iir_filter` enabled: 45s)
|
||||
- Battery Current Flow: `%+.0f` = Battery average current flow in mA (time period: 5s, or with `battery_avg_iir_filter` enabled: 11.25s)
|
||||
- Battery Power Flow: `%+.3f` = Battery average power flow in W calculated from Battery Voltage and Battery Current Flow
|
||||
- Battery Remaining Time: h:mm - How much time is left before shutdown
|
||||
|
||||
Shows only if charger is connected:
|
||||
| Category | Format | Explanation |
|
||||
|---------------------------|--------------|----------------------------------------------------------------------------------|
|
||||
| Charger Type | %u | Connected charger type, more in Battery.hpp "BatteryChargeInfoFieldsChargerType" |
|
||||
| Charger Max Voltage | %u | Charger and external device voltage limit in mV |
|
||||
| Charger Max Current | %u | Charger and external device current limit in mA |
|
||||
|
||||
> Miscellaneous
|
||||
|
||||
| Category | Format | Explanation |
|
||||
|------------------------|-------------------|----------------------------------------------------------------------------------|
|
||||
| DSP Usage | %u | In percent (not available on 17.0.0+) |
|
||||
| NVDEC | %.2f | Target frequency in MHz (shows 0 if chip is not active) |
|
||||
| NVENC | %.2f | Target frequency in MHz (shows 0 if chip is not active) |
|
||||
| NVJPG | %.2f | Target frequency in MHz (shows 0 if chip is not active) |
|
||||
| Network Type | %s | It shows if Switch is connected to internet, and if it's using Ethernet or Wi-Fi |
|
||||
|
||||
If Network Type is "Wi-Fi", you can press Y to show password. Since max password length is 64 characters, it may show in up to 3 lines.
|
||||
|
||||
> Game Resolutions
|
||||
|
||||
For this mode to show and work properly you must have SaltyNX 0.9.0+ installed. You can use touch screen to change its position temporarily.
|
||||
|
||||
When game runs, this menu shows what resolutions and how many times they were passed to GPU via two functions:
|
||||
- __Depth__ shows info from depth texture passed to `nvnCommandBufferSetRenderTargets`
|
||||
- __Viewport__ shows info from arguments passed to:
|
||||
- for NVN: `nvnCommandBufferSetViewport`, `nvnCommandBufferSetViewports`, `nvnCommandBufferSetScissor` and `nvnCommandBufferSetScissors`
|
||||
- for EGL: `glViewport`, `glViewportArrayv`, `glViewportIndexedf`, `glViewportIndexedfv` and all their variations
|
||||
- for Vulkan: `vkCmdSetViewport` and `vkCmdSetViewportWithCount`
|
||||
|
||||
This menu shows first 8 resolutions passed to those functions in last frame rendering loop, sorted in descending order of calls number.<br>
|
||||
Its main purpose is to catch game rendering resolution, but user must deduce which ones are correct.<br>
|
||||
I have limited catched resolutions only to ones that have ratio higher than 0.6 and lower than 1.8. Such low value comes from the fact that some games are rendering at width lower than height (f.e. 480x720). There is also a limit where it won't accept resolutions which height is lower than 160 px or higher than 1440 px.<br>
|
||||
|
||||
Remember that resolutions you can see in this mode may be used in different ways - for example Tokyo Xanadu Ex+ max dynamic resolution in handheld will show 1280x736, but it's not that game will squeeze this into 720p screen, it's just removing those additional 16 pixels from showing on screen.
|
||||
|
||||
Those commands are used by all 3D games using NVN, EGL and Vulkan APIs (that's why it may not work with games using 2D engines).<br>
|
||||
This mode is not 100% fullproof, so it can show that nothing is catched or it won't catch what is used for 3D rendering (if this happens for some 3D game, please report an issue).
|
||||
|
||||
By default refresh rate of this menu is 10 FPS. You can change that in config.ini, more in config.md<br>
|
||||
Exiting is done by using the same combo buttons used in other main modes.
|
||||
|
||||
Games that don't mesh well with RES category in `Mini` and Resolution in `Full` modes while showing properly rendering resolutions in this menu:
|
||||
- `Kirby and The Forgotten Land`: dynamic resolution has much less calls than other resolutions, it shows up correctly only when it's max dynamic resolution set. It shows up always first in Depth category of Game Resolutions menu.
|
||||
- `Darksiders 2`: Dynamic resolution is randomly showing up, fighting for attention with native resolution call. In Game Resolutions menu it shows up either at 2nd or 3rd place of Viewport.
|
||||
|
||||
# Additional info
|
||||
|
||||
> How Battery Remaining Time is calculated
|
||||
|
||||
It is calculated from the last 3 minutes of power draw readings. In the first minute of running any mode, it is updated every 0.5s, after one minute it's updated every minute. When exiting the currently used mode, calculations are reset. When connecting or disconnecting the charger, calculations are reset. When Battery Power Draw is positive instead of negative, time is shown as [-:--] and calculations are reset.
|
||||
|
||||
> What is Skin temperature ($\mathbf{T}skin$)?
|
||||
|
||||
This is temperature calculated from SoC and PCB temperatures that is mainly used to prevent Switch from overheating. Reading it is not supported on FWs <5.0.0.
|
||||
|
||||
Explanation provided by CTCaer
|
||||
>Temperature ($\mathbf{T}skin$) calculation.
|
||||
>
|
||||
>
|
||||
>Console and Handheld:
|
||||
>
|
||||
>$\mathbf{T}soc >= 84°C$ - Immediate sleep. No questions asked.
|
||||
>
|
||||
>$\mathbf{T}pcb >= 84°C$ - Immediate sleep. No questions asked.
|
||||
>
|
||||
>
|
||||
>Console only:
|
||||
>
|
||||
>$\mathbf{T}skin < 63°C$ - Clears both timers.
|
||||
>
|
||||
>$\mathbf{T}skin >= 63°C$ - Immediate sleep. No questions asked.
|
||||
>
|
||||
>
|
||||
>Handheld only:
|
||||
>
|
||||
>$\mathbf{T}skin < 58°C$ - Clears both timers.
|
||||
>
|
||||
>$58°C <= \mathbf{T}skin < 61°C$ - Starts 60s timer and clears 10s timer.
|
||||
>
|
||||
>$61°C <= \mathbf{T}skin < 63°C$ - Starts 10s timer.
|
||||
>
|
||||
>$\mathbf{T}skin >= 63°C$ - Immediate sleep. No questions asked.
|
||||
>
|
||||
>
|
||||
>The two timers are separate. If 61°C is reached, the 10s timer is immediatly started.
|
||||
>
|
||||
>If a timer ends and the temperature is not dropped, goes into sleep.
|
||||
>
|
||||
>
|
||||
>tskin is the specific calculation below:
|
||||
```
|
||||
soc_adj = (temps.iir_filter_gain_soc * (temps.soc - temps.soc_adj_prev)) + temps.soc_adj_prev;
|
||||
pcb_adj = (temps.iir_filter_gain_pcb * (temps.pcb - temps.pcb_adj_prev)) + temps.pcb_adj_prev;
|
||||
temps.soc_adj_prev = soc_adj;
|
||||
temps.pcb_adj_prev = pcb_adj;
|
||||
|
||||
if (soc_adj >= 38000)
|
||||
{
|
||||
if (temps.handheld)
|
||||
soc_adj = (temps.tskin_soc_coeff_handheld[0] * soc_adj) + (1000 * temps.tskin_soc_coeff_handheld[1]);
|
||||
else
|
||||
soc_adj = (temps.tskin_soc_coeff_console[0] * soc_adj) + (1000 * temps.tskin_soc_coeff_console[1]);
|
||||
soc_adj = (soc_adj / 10000) + 500;
|
||||
}
|
||||
|
||||
if (pcb_adj >= 38000)
|
||||
{
|
||||
if (temps.handheld)
|
||||
pcb_adj = (temps.tskin_pcb_coeff_handheld[0] * pcb_adj) + (1000 * temps.tskin_pcb_coeff_handheld[1]);
|
||||
else
|
||||
pcb_adj = (temps.tskin_pcb_coeff_console[0] * soc_adj) + (1000 * temps.tskin_pcb_coeff_console[1]);
|
||||
pcb_adj = (pcb_adj / 10000) + 500;
|
||||
}
|
||||
|
||||
skin_adj = MAX(soc_adj, pcb_adj); //tskin
|
||||
```
|
||||
81
Source/Horizon-OC-Monitor/include/Battery.hpp
Normal file
81
Source/Horizon-OC-Monitor/include/Battery.hpp
Normal file
@@ -0,0 +1,81 @@
|
||||
///* Notes VoltageAvg
|
||||
//
|
||||
// Vavg time = 175.8ms x 2^(6+VOLT), default: VOLT = 2 (Vavg time = 45s)
|
||||
//
|
||||
///End of Notes
|
||||
|
||||
typedef enum {
|
||||
NoHub = BIT(0), //If hub is disconnected
|
||||
Rail = BIT(8), //At least one Joy-con is charging from rail
|
||||
SPDSRC = BIT(12), //OTG
|
||||
ACC = BIT(16) //Accessory
|
||||
} BatteryChargeInfoFieldsFlags;
|
||||
|
||||
typedef enum {
|
||||
NewPDO = 1, //Received new Power Data Object
|
||||
NoPD = 2, //No Power Delivery source is detected
|
||||
AcceptedRDO = 3 //Received and accepted Request Data Object
|
||||
} BatteryChargeInfoFieldsPDControllerState; //BM92T series
|
||||
|
||||
typedef enum {
|
||||
None = 0,
|
||||
PD = 1,
|
||||
TypeC_1500mA = 2,
|
||||
TypeC_3000mA = 3,
|
||||
DCP = 4,
|
||||
CDP = 5,
|
||||
SDP = 6,
|
||||
Apple_500mA = 7,
|
||||
Apple_1000mA = 8,
|
||||
Apple_2000mA = 9
|
||||
} BatteryChargeInfoFieldsChargerType;
|
||||
|
||||
typedef enum {
|
||||
Sink = 1,
|
||||
Source = 2
|
||||
} BatteryChargeInfoFieldsPowerRole;
|
||||
|
||||
typedef struct {
|
||||
int32_t InputCurrentLimit; //Input (Sink) current limit in mA
|
||||
int32_t VBUSCurrentLimit; //Output (Source/VBUS/OTG) current limit in mA
|
||||
int32_t ChargeCurrentLimit; //Battery charging current limit in mA (512mA when Docked, 768mA when BatteryTemperature < 17.0 C)
|
||||
int32_t ChargeVoltageLimit; //Battery charging voltage limit in mV (3952mV when BatteryTemperature >= 51.0 C)
|
||||
int32_t unk_x10; //Possibly an emum, getting the same value as PowerRole in all tested cases
|
||||
int32_t unk_x14; //Possibly flags
|
||||
BatteryChargeInfoFieldsPDControllerState PDControllerState; //Power Delivery Controller State
|
||||
int32_t BatteryTemperature; //Battery temperature in milli C
|
||||
int32_t RawBatteryCharge; //Raw battery charged capacity per cent-mille (i.e. 100% = 100000 pcm)
|
||||
int32_t VoltageAvg; //Voltage avg in mV (more in Notes)
|
||||
int32_t BatteryAge; //Battery age (capacity full / capacity design) per cent-mille (i.e. 100% = 100000 pcm)
|
||||
BatteryChargeInfoFieldsPowerRole PowerRole;
|
||||
BatteryChargeInfoFieldsChargerType ChargerType;
|
||||
int32_t ChargerVoltageLimit; //Charger and external device voltage limit in mV
|
||||
int32_t ChargerCurrentLimit; //Charger and external device current limit in mA
|
||||
BatteryChargeInfoFieldsFlags Flags; //Unknown flags
|
||||
char reserved[0x14]; //17.0.0+ data
|
||||
} BatteryChargeInfoFields;
|
||||
|
||||
typedef struct {
|
||||
int32_t InputCurrentLimit; //Input (Sink) current limit in mA
|
||||
int32_t VBUSCurrentLimit; //Output (Source/VBUS/OTG) current limit in mA
|
||||
int32_t ChargeCurrentLimit; //Battery charging current limit in mA (512mA when Docked, 768mA when BatteryTemperature < 17.0 C)
|
||||
int32_t ChargeVoltageLimit; //Battery charging voltage limit in mV (3952mV when BatteryTemperature >= 51.0 C)
|
||||
int32_t unk_x10; //Possibly an emum, getting the same value as PowerRole in all tested cases
|
||||
int32_t unk_x14; //Possibly flags
|
||||
BatteryChargeInfoFieldsPDControllerState PDControllerState; //Power Delivery Controller State
|
||||
int32_t BatteryTemperature; //Battery temperature in milli C
|
||||
int32_t RawBatteryCharge; //Raw battery charged capacity per cent-mille (i.e. 100% = 100000 pcm)
|
||||
int32_t VoltageAvg; //Voltage avg in mV (more in Notes)
|
||||
int32_t BatteryAge; //Battery age (capacity full / capacity design) per cent-mille (i.e. 100% = 100000 pcm)
|
||||
char reserved[4]; //17.0.0+ data
|
||||
BatteryChargeInfoFieldsPowerRole PowerRole;
|
||||
BatteryChargeInfoFieldsChargerType ChargerType;
|
||||
int32_t ChargerVoltageLimit; //Charger and external device voltage limit in mV
|
||||
int32_t ChargerCurrentLimit; //Charger and external device current limit in mA
|
||||
BatteryChargeInfoFieldsFlags Flags; //Unknown flags
|
||||
char reserved2[0x10]; //17.0.0+ data
|
||||
} BatteryChargeInfoFields17;
|
||||
|
||||
Result psmGetBatteryChargeInfoFields(Service* psmService, BatteryChargeInfoFields *out) {
|
||||
return serviceDispatchOut(psmService, 17, *out);
|
||||
}
|
||||
41
Source/Horizon-OC-Monitor/include/Misc.hpp
Normal file
41
Source/Horizon-OC-Monitor/include/Misc.hpp
Normal file
@@ -0,0 +1,41 @@
|
||||
typedef struct {
|
||||
u8 ssid_len; ///< NifmSfWirelessSettingData::ssid_len
|
||||
char ssid[0x21]; ///< NifmSfWirelessSettingData::ssid
|
||||
u8 unk_x22; ///< NifmSfWirelessSettingData::unk_x21
|
||||
u8 pad; ///< Padding
|
||||
u32 unk_x24; ///< NifmSfWirelessSettingData::unk_x22
|
||||
u32 unk_x28; ///< NifmSfWirelessSettingData::unk_x23
|
||||
u8 passphrase_len; ///< Passphrase length
|
||||
u8 passphrase[0x41]; ///< NifmSfWirelessSettingData::passphrase
|
||||
u8 pad2[0x2]; ///< Padding
|
||||
} NifmWirelessSettingData_new;
|
||||
|
||||
/// NetworkProfileData. Converted from/to \ref NifmSfNetworkProfileData.
|
||||
typedef struct {
|
||||
Uuid uuid; ///< NifmSfNetworkProfileData::uuid
|
||||
char network_name[0x40]; ///< NifmSfNetworkProfileData::network_name
|
||||
u32 unk_x50; ///< NifmSfNetworkProfileData::unk_x112
|
||||
u32 unk_x54; ///< NifmSfNetworkProfileData::unk_x113
|
||||
u8 unk_x58; ///< NifmSfNetworkProfileData::unk_x114
|
||||
u8 unk_x59; ///< NifmSfNetworkProfileData::unk_x115
|
||||
u8 pad[2]; ///< Padding
|
||||
NifmWirelessSettingData_new wireless_setting_data; ///< \ref NifmWirelessSettingData
|
||||
NifmIpSettingData ip_setting_data; ///< \ref NifmIpSettingData
|
||||
} NifmNetworkProfileData_new;
|
||||
|
||||
Result getNvChannelClockRate(NvChannel *channel, u32 module_id, u32 *clock_rate) {
|
||||
struct nvhost_clk_rate_args {
|
||||
uint32_t rate;
|
||||
uint32_t moduleid;
|
||||
} args = {
|
||||
.rate = 0,
|
||||
.moduleid = module_id,
|
||||
};
|
||||
|
||||
const u32 id = hosversionBefore(8,0,0) ? _NV_IOWR(0, 0x14, args) : _NV_IOWR(0, 0x23, args);
|
||||
Result rc = nvIoctl(channel->fd, id, &args);
|
||||
if (R_SUCCEEDED(rc) && clock_rate)
|
||||
*clock_rate = args.rate;
|
||||
|
||||
return rc;
|
||||
}
|
||||
231
Source/Horizon-OC-Monitor/include/SaltyNX.h
Normal file
231
Source/Horizon-OC-Monitor/include/SaltyNX.h
Normal file
@@ -0,0 +1,231 @@
|
||||
#pragma once
|
||||
#include "ipc.h"
|
||||
|
||||
Handle saltysd_orig;
|
||||
|
||||
Result SaltySD_Connect() {
|
||||
for (int i = 0; i < 200; i++) {
|
||||
if (!svcConnectToNamedPort(&saltysd_orig, "SaltySD"))
|
||||
return 0;
|
||||
svcSleepThread(1000*1000);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
Result SaltySD_Term()
|
||||
{
|
||||
Result ret;
|
||||
IpcCommand c;
|
||||
|
||||
ipcInitialize(&c);
|
||||
ipcSendPid(&c);
|
||||
|
||||
struct input
|
||||
{
|
||||
u64 magic;
|
||||
u64 cmd_id;
|
||||
u64 zero;
|
||||
u64 reserved[2];
|
||||
} *raw;
|
||||
|
||||
raw = (input*)ipcPrepareHeader(&c, sizeof(*raw));
|
||||
|
||||
raw->magic = SFCI_MAGIC;
|
||||
raw->cmd_id = 0;
|
||||
raw->zero = 0;
|
||||
|
||||
ret = ipcDispatch(saltysd_orig);
|
||||
|
||||
if (R_SUCCEEDED(ret))
|
||||
{
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct output {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
} *resp = (output*)r.Raw;
|
||||
|
||||
ret = resp->result;
|
||||
}
|
||||
|
||||
// Session terminated works too.
|
||||
svcCloseHandle(saltysd_orig);
|
||||
if (ret == 0xf601) return 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Result SaltySD_CheckIfSharedMemoryAvailable(ptrdiff_t *offset, u64 size)
|
||||
{
|
||||
Result ret = 0;
|
||||
|
||||
// Send a command
|
||||
IpcCommand c;
|
||||
ipcInitialize(&c);
|
||||
ipcSendPid(&c);
|
||||
|
||||
struct input {
|
||||
u64 magic;
|
||||
u64 cmd_id;
|
||||
u64 size;
|
||||
u32 reserved[2];
|
||||
} *raw;
|
||||
|
||||
raw = (input*)ipcPrepareHeader(&c, sizeof(*raw));
|
||||
|
||||
raw->magic = SFCI_MAGIC;
|
||||
raw->cmd_id = 6;
|
||||
raw->size = size;
|
||||
|
||||
ret = ipcDispatch(saltysd_orig);
|
||||
|
||||
if (R_SUCCEEDED(ret)) {
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct output {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
u64 offset;
|
||||
} *resp = (output*)r.Raw;
|
||||
|
||||
ret = resp->result;
|
||||
|
||||
if (!ret)
|
||||
{
|
||||
*offset = resp->offset;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Result SaltySD_GetSharedMemoryHandle(Handle *retrieve)
|
||||
{
|
||||
Result ret = 0;
|
||||
|
||||
// Send a command
|
||||
IpcCommand c;
|
||||
ipcInitialize(&c);
|
||||
ipcSendPid(&c);
|
||||
|
||||
struct input {
|
||||
u64 magic;
|
||||
u64 cmd_id;
|
||||
u32 reserved[4];
|
||||
} *raw;
|
||||
|
||||
raw = (input*)ipcPrepareHeader(&c, sizeof(*raw));
|
||||
|
||||
raw->magic = SFCI_MAGIC;
|
||||
raw->cmd_id = 7;
|
||||
|
||||
ret = ipcDispatch(saltysd_orig);
|
||||
|
||||
if (R_SUCCEEDED(ret)) {
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct output {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
u64 reserved[2];
|
||||
} *resp = (output*)r.Raw;
|
||||
|
||||
ret = resp->result;
|
||||
|
||||
if (!ret)
|
||||
{
|
||||
*retrieve = r.Handles[0];
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Result SaltySD_GetDisplayRefreshRate(uint8_t* refreshRate)
|
||||
{
|
||||
Result ret = 0;
|
||||
|
||||
// Send a command
|
||||
IpcCommand c;
|
||||
ipcInitialize(&c);
|
||||
ipcSendPid(&c);
|
||||
|
||||
struct input {
|
||||
u64 magic;
|
||||
u64 cmd_id;
|
||||
u64 zero;
|
||||
u64 reserved;
|
||||
} *raw;
|
||||
|
||||
raw = (input*)ipcPrepareHeader(&c, sizeof(*raw));
|
||||
|
||||
raw->magic = SFCI_MAGIC;
|
||||
raw->cmd_id = 10;
|
||||
raw->zero = 0;
|
||||
|
||||
ret = ipcDispatch(saltysd_orig);
|
||||
|
||||
if (R_SUCCEEDED(ret)) {
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct output {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
u64 refreshRate;
|
||||
u64 reserved;
|
||||
} *resp = (output*)r.Raw;
|
||||
|
||||
ret = resp->result;
|
||||
|
||||
if (!ret)
|
||||
{
|
||||
*refreshRate = (uint8_t)(resp->refreshRate);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Result SaltySD_SetDisplayRefreshRate(uint8_t refreshRate)
|
||||
{
|
||||
Result ret = 0;
|
||||
|
||||
// Send a command
|
||||
IpcCommand c;
|
||||
ipcInitialize(&c);
|
||||
ipcSendPid(&c);
|
||||
|
||||
struct input {
|
||||
u64 magic;
|
||||
u64 cmd_id;
|
||||
u64 refreshRate;
|
||||
u64 reserved;
|
||||
} *raw;
|
||||
|
||||
raw = (input*)ipcPrepareHeader(&c, sizeof(*raw));
|
||||
|
||||
raw->magic = SFCI_MAGIC;
|
||||
raw->cmd_id = 11;
|
||||
raw->refreshRate = refreshRate;
|
||||
|
||||
ret = ipcDispatch(saltysd_orig);
|
||||
|
||||
if (R_SUCCEEDED(ret)) {
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct output {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
u64 reserved[2];
|
||||
} *resp = (output*)r.Raw;
|
||||
|
||||
ret = resp->result;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
19
Source/Horizon-OC-Monitor/include/audsnoop.h
Normal file
19
Source/Horizon-OC-Monitor/include/audsnoop.h
Normal file
@@ -0,0 +1,19 @@
|
||||
#pragma once
|
||||
|
||||
#include <switch.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
Result audsnoopInitialize(void);
|
||||
void audsnoopExit(void);
|
||||
|
||||
Result audsnoopEnableDspUsageMeasurement(void);
|
||||
Result audsnoopDisableDspUsageMeasurement(void);
|
||||
|
||||
Result audsnoopGetDspUsage(u32 *usage);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
77
Source/Horizon-OC-Monitor/include/i2c.h
Normal file
77
Source/Horizon-OC-Monitor/include/i2c.h
Normal file
@@ -0,0 +1,77 @@
|
||||
#pragma once
|
||||
|
||||
Result I2cReadRegHandler16(u8 reg, I2cDevice dev, u16 *out)
|
||||
{
|
||||
struct readReg {
|
||||
u8 send;
|
||||
u8 sendLength;
|
||||
u8 sendData;
|
||||
u8 receive;
|
||||
u8 receiveLength;
|
||||
};
|
||||
|
||||
I2cSession _session;
|
||||
|
||||
Result res = i2cOpenSession(&_session, dev);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
u16 val;
|
||||
|
||||
struct readReg readRegister = {
|
||||
.send = 0 | (I2cTransactionOption_Start << 6),
|
||||
.sendLength = sizeof(reg),
|
||||
.sendData = reg,
|
||||
.receive = 1 | (I2cTransactionOption_All << 6),
|
||||
.receiveLength = sizeof(val),
|
||||
};
|
||||
|
||||
res = i2csessionExecuteCommandList(&_session, &val, sizeof(val), &readRegister, sizeof(readRegister));
|
||||
if (res)
|
||||
{
|
||||
i2csessionClose(&_session);
|
||||
return res;
|
||||
}
|
||||
|
||||
*out = val;
|
||||
i2csessionClose(&_session);
|
||||
return 0;
|
||||
}
|
||||
|
||||
Result I2cReadRegHandler8(u8 reg, I2cDevice dev, u8 *out)
|
||||
{
|
||||
struct readReg {
|
||||
u8 send;
|
||||
u8 sendLength;
|
||||
u8 sendData;
|
||||
u8 receive;
|
||||
u8 receiveLength;
|
||||
};
|
||||
|
||||
I2cSession _session;
|
||||
|
||||
Result res = i2cOpenSession(&_session, dev);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
u8 val;
|
||||
|
||||
struct readReg readRegister = {
|
||||
.send = 0 | (I2cTransactionOption_Start << 6),
|
||||
.sendLength = sizeof(reg),
|
||||
.sendData = reg,
|
||||
.receive = 1 | (I2cTransactionOption_All << 6),
|
||||
.receiveLength = sizeof(val),
|
||||
};
|
||||
|
||||
res = i2csessionExecuteCommandList(&_session, &val, sizeof(val), &readRegister, sizeof(readRegister));
|
||||
if (res)
|
||||
{
|
||||
i2csessionClose(&_session);
|
||||
return res;
|
||||
}
|
||||
|
||||
*out = val;
|
||||
i2csessionClose(&_session);
|
||||
return 0;
|
||||
}
|
||||
755
Source/Horizon-OC-Monitor/include/ipc.h
Normal file
755
Source/Horizon-OC-Monitor/include/ipc.h
Normal file
@@ -0,0 +1,755 @@
|
||||
/**
|
||||
* @file ipc.h
|
||||
* @brief Inter-process communication handling
|
||||
* @author plutoo
|
||||
* @copyright libnx Authors
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
/// IPC input header magic
|
||||
#define SFCI_MAGIC 0x49434653
|
||||
/// IPC output header magic
|
||||
#define SFCO_MAGIC 0x4f434653
|
||||
|
||||
/// IPC invalid object ID
|
||||
#define IPC_INVALID_OBJECT_ID UINT32_MAX
|
||||
|
||||
///@name IPC request building
|
||||
///@{
|
||||
|
||||
/// IPC command (request) structure.
|
||||
#define IPC_MAX_BUFFERS 8
|
||||
#define IPC_MAX_OBJECTS 8
|
||||
|
||||
typedef enum {
|
||||
BufferType_Normal=0, ///< Regular buffer.
|
||||
BufferType_Type1=1, ///< Allows ProcessMemory and shared TransferMemory.
|
||||
BufferType_Invalid=2,
|
||||
BufferType_Type3=3 ///< Same as Type1 except remote process is not allowed to use device-mapping.
|
||||
} BufferType;
|
||||
|
||||
typedef enum {
|
||||
BufferDirection_Send=0,
|
||||
BufferDirection_Recv=1,
|
||||
BufferDirection_Exch=2,
|
||||
} BufferDirection;
|
||||
|
||||
typedef enum {
|
||||
IpcCommandType_Invalid = 0,
|
||||
IpcCommandType_LegacyRequest = 1,
|
||||
IpcCommandType_Close = 2,
|
||||
IpcCommandType_LegacyControl = 3,
|
||||
IpcCommandType_Request = 4,
|
||||
IpcCommandType_Control = 5,
|
||||
IpcCommandType_RequestWithContext = 6,
|
||||
IpcCommandType_ControlWithContext = 7,
|
||||
} IpcCommandType;
|
||||
|
||||
typedef enum {
|
||||
DomainMessageType_Invalid = 0,
|
||||
DomainMessageType_SendMessage = 1,
|
||||
DomainMessageType_Close = 2,
|
||||
} DomainMessageType;
|
||||
|
||||
/// IPC domain message header.
|
||||
typedef struct {
|
||||
u8 Type;
|
||||
u8 NumObjectIds;
|
||||
u16 Length;
|
||||
u32 ThisObjectId;
|
||||
u32 Pad[2];
|
||||
} DomainMessageHeader;
|
||||
|
||||
/// IPC domain response header.
|
||||
typedef struct {
|
||||
u32 NumObjectIds;
|
||||
u32 Pad[3];
|
||||
} DomainResponseHeader;
|
||||
|
||||
|
||||
typedef struct {
|
||||
size_t NumSend; // A
|
||||
size_t NumRecv; // B
|
||||
size_t NumExch; // W
|
||||
const void* Buffers[IPC_MAX_BUFFERS];
|
||||
size_t BufferSizes[IPC_MAX_BUFFERS];
|
||||
BufferType BufferTypes[IPC_MAX_BUFFERS];
|
||||
|
||||
size_t NumStaticIn; // X
|
||||
size_t NumStaticOut; // C
|
||||
const void* Statics[IPC_MAX_BUFFERS];
|
||||
size_t StaticSizes[IPC_MAX_BUFFERS];
|
||||
u8 StaticIndices[IPC_MAX_BUFFERS];
|
||||
|
||||
bool SendPid;
|
||||
size_t NumHandlesCopy;
|
||||
size_t NumHandlesMove;
|
||||
Handle Handles[IPC_MAX_OBJECTS];
|
||||
|
||||
size_t NumObjectIds;
|
||||
u32 ObjectIds[IPC_MAX_OBJECTS];
|
||||
} IpcCommand;
|
||||
|
||||
/**
|
||||
* @brief Initializes an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
*/
|
||||
static inline void ipcInitialize(IpcCommand* cmd) {
|
||||
*cmd = (IpcCommand){};
|
||||
}
|
||||
|
||||
/// IPC buffer descriptor.
|
||||
typedef struct {
|
||||
u32 Size; ///< Size of the buffer.
|
||||
u32 Addr; ///< Lower 32-bits of the address of the buffer
|
||||
u32 Packed; ///< Packed data (including higher bits of the address)
|
||||
} IpcBufferDescriptor;
|
||||
|
||||
/// IPC static send-buffer descriptor.
|
||||
typedef struct {
|
||||
u32 Packed; ///< Packed data (including higher bits of the address)
|
||||
u32 Addr; ///< Lower 32-bits of the address
|
||||
} IpcStaticSendDescriptor;
|
||||
|
||||
/// IPC static receive-buffer descriptor.
|
||||
typedef struct {
|
||||
u32 Addr; ///< Lower 32-bits of the address of the buffer
|
||||
u32 Packed; ///< Packed data (including higher bits of the address)
|
||||
} IpcStaticRecvDescriptor;
|
||||
|
||||
/**
|
||||
* @brief Adds a buffer to an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param buffer Address of the buffer.
|
||||
* @param size Size of the buffer.
|
||||
* @param type Buffer type.
|
||||
*/
|
||||
static inline void ipcAddSendBuffer(IpcCommand* cmd, const void* buffer, size_t size, BufferType type) {
|
||||
const size_t off = cmd->NumSend;
|
||||
cmd->Buffers[off] = buffer;
|
||||
cmd->BufferSizes[off] = size;
|
||||
cmd->BufferTypes[off] = type;
|
||||
cmd->NumSend++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds a receive-buffer to an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param buffer Address of the buffer.
|
||||
* @param size Size of the buffer.
|
||||
* @param type Buffer type.
|
||||
*/
|
||||
static inline void ipcAddRecvBuffer(IpcCommand* cmd, void* buffer, size_t size, BufferType type) {
|
||||
const size_t off = cmd->NumSend + cmd->NumRecv;
|
||||
cmd->Buffers[off] = buffer;
|
||||
cmd->BufferSizes[off] = size;
|
||||
cmd->BufferTypes[off] = type;
|
||||
cmd->NumRecv++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds an exchange-buffer to an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param buffer Address of the buffer.
|
||||
* @param size Size of the buffer.
|
||||
* @param type Buffer type.
|
||||
*/
|
||||
static inline void ipcAddExchBuffer(IpcCommand* cmd, void* buffer, size_t size, BufferType type) {
|
||||
const size_t off = cmd->NumSend + cmd->NumRecv + cmd->NumExch;
|
||||
cmd->Buffers[off] = buffer;
|
||||
cmd->BufferSizes[off] = size;
|
||||
cmd->BufferTypes[off] = type;
|
||||
cmd->NumExch++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds a static-buffer to an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param buffer Address of the buffer.
|
||||
* @param size Size of the buffer.
|
||||
* @param index Index of buffer.
|
||||
*/
|
||||
static inline void ipcAddSendStatic(IpcCommand* cmd, const void* buffer, size_t size, u8 index) {
|
||||
const size_t off = cmd->NumStaticIn;
|
||||
cmd->Statics[off] = buffer;
|
||||
cmd->StaticSizes[off] = size;
|
||||
cmd->StaticIndices[off] = index;
|
||||
cmd->NumStaticIn++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds a static-receive-buffer to an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param buffer Address of the buffer.
|
||||
* @param size Size of the buffer.
|
||||
* @param index Index of buffer.
|
||||
*/
|
||||
static inline void ipcAddRecvStatic(IpcCommand* cmd, void* buffer, size_t size, u8 index) {
|
||||
const size_t off = cmd->NumStaticIn + cmd->NumStaticOut;
|
||||
cmd->Statics[off] = buffer;
|
||||
cmd->StaticSizes[off] = size;
|
||||
cmd->StaticIndices[off] = index;
|
||||
cmd->NumStaticOut++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds a smart-buffer (buffer + static-buffer pair) to an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param pointer_buffer_size Pointer buffer size.
|
||||
* @param buffer Address of the buffer.
|
||||
* @param size Size of the buffer.
|
||||
* @param index Index of buffer.
|
||||
*/
|
||||
static inline void ipcAddSendSmart(IpcCommand* cmd, size_t pointer_buffer_size, const void* buffer, size_t size, u8 index) {
|
||||
if (pointer_buffer_size != 0 && size <= pointer_buffer_size) {
|
||||
ipcAddSendBuffer(cmd, NULL, 0, BufferType_Normal);
|
||||
ipcAddSendStatic(cmd, buffer, size, index);
|
||||
} else {
|
||||
ipcAddSendBuffer(cmd, buffer, size, BufferType_Normal);
|
||||
ipcAddSendStatic(cmd, NULL, 0, index);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds a smart-receive-buffer (buffer + static-receive-buffer pair) to an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param pointer_buffer_size Pointer buffer size.
|
||||
* @param buffer Address of the buffer.
|
||||
* @param size Size of the buffer.
|
||||
* @param index Index of buffer.
|
||||
*/
|
||||
static inline void ipcAddRecvSmart(IpcCommand* cmd, size_t pointer_buffer_size, void* buffer, size_t size, u8 index) {
|
||||
if (pointer_buffer_size != 0 && size <= pointer_buffer_size) {
|
||||
ipcAddRecvBuffer(cmd, NULL, 0, BufferType_Normal);
|
||||
ipcAddRecvStatic(cmd, buffer, size, index);
|
||||
} else {
|
||||
ipcAddRecvBuffer(cmd, buffer, size, BufferType_Normal);
|
||||
ipcAddRecvStatic(cmd, NULL, 0, index);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Tags an IPC command structure to send the PID.
|
||||
* @param cmd IPC command structure.
|
||||
*/
|
||||
static inline void ipcSendPid(IpcCommand* cmd) {
|
||||
cmd->SendPid = true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds a copy-handle to be sent through an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param h Handle to send.
|
||||
* @remark The receiving process gets a copy of the handle.
|
||||
*/
|
||||
static inline void ipcSendHandleCopy(IpcCommand* cmd, Handle h) {
|
||||
cmd->Handles[cmd->NumHandlesCopy++] = h;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds a move-handle to be sent through an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param h Handle to send.
|
||||
* @remark The sending process loses ownership of the handle, which is transferred to the receiving process.
|
||||
*/
|
||||
static inline void ipcSendHandleMove(IpcCommand* cmd, Handle h) {
|
||||
cmd->Handles[cmd->NumHandlesCopy + cmd->NumHandlesMove++] = h;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Prepares the header of an IPC command structure.
|
||||
* @param cmd IPC command structure.
|
||||
* @param sizeof_raw Size in bytes of the raw data structure to embed inside the IPC request
|
||||
* @return Pointer to the raw embedded data structure in the request, ready to be filled out.
|
||||
*/
|
||||
static inline void* ipcPrepareHeader(IpcCommand* cmd, size_t sizeof_raw) {
|
||||
u32* buf = (u32*)armGetTls();
|
||||
size_t i;
|
||||
*buf++ = IpcCommandType_Request | (cmd->NumStaticIn << 16) | (cmd->NumSend << 20) | (cmd->NumRecv << 24) | (cmd->NumExch << 28);
|
||||
|
||||
u32* fill_in_size_later = buf;
|
||||
|
||||
if (cmd->NumStaticOut > 0) {
|
||||
*buf = (cmd->NumStaticOut + 2) << 10;
|
||||
}
|
||||
else {
|
||||
*buf = 0;
|
||||
}
|
||||
|
||||
if (cmd->SendPid || cmd->NumHandlesCopy > 0 || cmd->NumHandlesMove > 0) {
|
||||
*buf++ |= 0x80000000;
|
||||
*buf++ = (!!cmd->SendPid) | (cmd->NumHandlesCopy << 1) | (cmd->NumHandlesMove << 5);
|
||||
|
||||
if (cmd->SendPid)
|
||||
buf += 2;
|
||||
|
||||
for (i=0; i<(cmd->NumHandlesCopy + cmd->NumHandlesMove); i++)
|
||||
*buf++ = cmd->Handles[i];
|
||||
}
|
||||
else {
|
||||
buf++;
|
||||
}
|
||||
|
||||
for (i=0; i<cmd->NumStaticIn; i++, buf+=2) {
|
||||
IpcStaticSendDescriptor* desc = (IpcStaticSendDescriptor*) buf;
|
||||
|
||||
const uintptr_t ptr = (uintptr_t) cmd->Statics[i];
|
||||
desc->Addr = ptr;
|
||||
desc->Packed = cmd->StaticIndices[i] | (cmd->StaticSizes[i] << 16) |
|
||||
(((ptr >> 32) & 15) << 12) | (((ptr >> 36) & 15) << 6);
|
||||
}
|
||||
|
||||
for (i=0; i<(cmd->NumSend + cmd->NumRecv + cmd->NumExch); i++, buf+=3) {
|
||||
IpcBufferDescriptor* desc = (IpcBufferDescriptor*) buf;
|
||||
desc->Size = cmd->BufferSizes[i];
|
||||
|
||||
const uintptr_t ptr = (uintptr_t) cmd->Buffers[i];
|
||||
desc->Addr = ptr;
|
||||
desc->Packed = cmd->BufferTypes[i] |
|
||||
(((ptr >> 32) & 15) << 28) | ((ptr >> 36) << 2);
|
||||
}
|
||||
|
||||
const u32 padding = ((16 - (((uintptr_t) buf) & 15)) & 15) / 4;
|
||||
u32* raw = (u32*) (buf + padding);
|
||||
|
||||
size_t raw_size = (sizeof_raw/4) + 4;
|
||||
buf += raw_size;
|
||||
|
||||
u16* buf_u16 = (u16*) buf;
|
||||
|
||||
for (i=0; i<cmd->NumStaticOut; i++) {
|
||||
const size_t off = cmd->NumStaticIn + i;
|
||||
const size_t sz = (uintptr_t) cmd->StaticSizes[off];
|
||||
|
||||
buf_u16[i] = (sz > 0xFFFF) ? 0 : sz;
|
||||
}
|
||||
|
||||
const size_t u16s_size = ((2*cmd->NumStaticOut) + 3)/4;
|
||||
buf += u16s_size;
|
||||
raw_size += u16s_size;
|
||||
|
||||
*fill_in_size_later |= raw_size;
|
||||
|
||||
for (i=0; i<cmd->NumStaticOut; i++, buf+=2) {
|
||||
IpcStaticRecvDescriptor* desc = (IpcStaticRecvDescriptor*) buf;
|
||||
const size_t off = cmd->NumStaticIn + i;
|
||||
|
||||
const uintptr_t ptr = (uintptr_t) cmd->Statics[off];
|
||||
desc->Addr = ptr;
|
||||
desc->Packed = (ptr >> 32) | (cmd->StaticSizes[off] << 16);
|
||||
}
|
||||
|
||||
return (void*) raw;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Dispatches an IPC request.
|
||||
* @param session IPC session handle.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcDispatch(Handle session) {
|
||||
return svcSendSyncRequest(session);
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
///@name IPC response parsing
|
||||
///@{
|
||||
|
||||
/// IPC parsed command (response) structure.
|
||||
typedef struct {
|
||||
IpcCommandType CommandType; ///< Type of the command
|
||||
|
||||
bool HasPid; ///< true if the 'Pid' field is filled out.
|
||||
u64 Pid; ///< PID included in the response (only if HasPid is true)
|
||||
|
||||
size_t NumHandles; ///< Number of handles copied.
|
||||
Handle Handles[IPC_MAX_OBJECTS]; ///< Handles.
|
||||
bool WasHandleCopied[IPC_MAX_OBJECTS]; ///< true if the handle was moved, false if it was copied.
|
||||
|
||||
bool IsDomainRequest; ///< true if the the message is a Domain message.
|
||||
DomainMessageType InMessageType; ///< Type of the domain message.
|
||||
u32 InMessageLength; ///< Size of rawdata (for domain messages).
|
||||
u32 InThisObjectId; ///< Object ID to call the command on (for domain messages).
|
||||
size_t InNumObjectIds; ///< Number of object IDs (for domain messages).
|
||||
u32 InObjectIds[IPC_MAX_OBJECTS]; ///< Object IDs (for domain messages).
|
||||
|
||||
bool IsDomainResponse; ///< true if the the message is a Domain response.
|
||||
size_t OutNumObjectIds; ///< Number of object IDs (for domain responses).
|
||||
u32 OutObjectIds[IPC_MAX_OBJECTS]; ///< Object IDs (for domain responses).
|
||||
|
||||
size_t NumBuffers; ///< Number of buffers in the response.
|
||||
void* Buffers[IPC_MAX_BUFFERS]; ///< Pointers to the buffers.
|
||||
size_t BufferSizes[IPC_MAX_BUFFERS]; ///< Sizes of the buffers.
|
||||
BufferType BufferTypes[IPC_MAX_BUFFERS]; ///< Types of the buffers.
|
||||
BufferDirection BufferDirections[IPC_MAX_BUFFERS]; ///< Direction of each buffer.
|
||||
|
||||
size_t NumStatics; ///< Number of statics in the response.
|
||||
void* Statics[IPC_MAX_BUFFERS]; ///< Pointers to the statics.
|
||||
size_t StaticSizes[IPC_MAX_BUFFERS]; ///< Sizes of the statics.
|
||||
u8 StaticIndices[IPC_MAX_BUFFERS]; ///< Indices of the statics.
|
||||
|
||||
size_t NumStaticsOut; ///< Number of output statics available in the response.
|
||||
|
||||
void* Raw; ///< Pointer to the raw embedded data structure in the response.
|
||||
void* RawWithoutPadding; ///< Pointer to the raw embedded data structure, without padding.
|
||||
size_t RawSize; ///< Size of the raw embedded data.
|
||||
} IpcParsedCommand;
|
||||
|
||||
/**
|
||||
* @brief Parse an IPC command response into an IPC parsed command structure.
|
||||
* @param r IPC parsed command structure to fill in.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcParse(IpcParsedCommand* r) {
|
||||
u32* buf = (u32*)armGetTls();
|
||||
u32 ctrl0 = *buf++;
|
||||
u32 ctrl1 = *buf++;
|
||||
size_t i;
|
||||
|
||||
r->IsDomainRequest = false;
|
||||
r->IsDomainResponse = false;
|
||||
|
||||
r->CommandType = (IpcCommandType) (ctrl0 & 0xffff);
|
||||
r->HasPid = false;
|
||||
r->RawSize = (ctrl1 & 0x1ff) * 4;
|
||||
r->NumHandles = 0;
|
||||
|
||||
r->NumStaticsOut = (ctrl1 >> 10) & 15;
|
||||
if (r->NumStaticsOut >> 1) r->NumStaticsOut--; // Value 2 -> Single descriptor
|
||||
if (r->NumStaticsOut >> 1) r->NumStaticsOut--; // Value 3+ -> (Value - 2) descriptors
|
||||
|
||||
if (ctrl1 & 0x80000000) {
|
||||
u32 ctrl2 = *buf++;
|
||||
|
||||
if (ctrl2 & 1) {
|
||||
r->HasPid = true;
|
||||
r->Pid = *buf++;
|
||||
r->Pid |= ((u64)(*buf++)) << 32;
|
||||
}
|
||||
|
||||
const size_t num_handles_copy = ((ctrl2 >> 1) & 15);
|
||||
const size_t num_handles_move = ((ctrl2 >> 5) & 15);
|
||||
|
||||
size_t num_handles = num_handles_copy + num_handles_move;
|
||||
u32* buf_after_handles = buf + num_handles;
|
||||
|
||||
if (num_handles > IPC_MAX_OBJECTS)
|
||||
num_handles = IPC_MAX_OBJECTS;
|
||||
|
||||
for (i=0; i<num_handles; i++)
|
||||
{
|
||||
r->Handles[i] = *(buf+i);
|
||||
r->WasHandleCopied[i] = (i < num_handles_copy);
|
||||
}
|
||||
|
||||
r->NumHandles = num_handles;
|
||||
buf = buf_after_handles;
|
||||
}
|
||||
|
||||
size_t num_statics = (ctrl0 >> 16) & 15;
|
||||
u32* buf_after_statics = buf + num_statics*2;
|
||||
|
||||
if (num_statics > IPC_MAX_BUFFERS)
|
||||
num_statics = IPC_MAX_BUFFERS;
|
||||
|
||||
for (i=0; i<num_statics; i++, buf+=2) {
|
||||
IpcStaticSendDescriptor* desc = (IpcStaticSendDescriptor*) buf;
|
||||
const u64 packed = (u64) desc->Packed;
|
||||
|
||||
r->Statics[i] = (void*) (desc->Addr | (((packed >> 12) & 15) << 32) | (((packed >> 6) & 15) << 36));
|
||||
r->StaticSizes[i] = packed >> 16;
|
||||
r->StaticIndices[i] = packed & 63;
|
||||
}
|
||||
|
||||
r->NumStatics = num_statics;
|
||||
buf = buf_after_statics;
|
||||
|
||||
const size_t num_bufs_send = (ctrl0 >> 20) & 15;
|
||||
const size_t num_bufs_recv = (ctrl0 >> 24) & 15;
|
||||
const size_t num_bufs_exch = (ctrl0 >> 28) & 15;
|
||||
|
||||
size_t num_bufs = num_bufs_send + num_bufs_recv + num_bufs_exch;
|
||||
r->Raw = (void*)(((uintptr_t)(buf + num_bufs*3) + 15) &~ 15);
|
||||
r->RawWithoutPadding = (void*)((uintptr_t)(buf + num_bufs*3));
|
||||
|
||||
if (num_bufs > IPC_MAX_BUFFERS)
|
||||
num_bufs = IPC_MAX_BUFFERS;
|
||||
|
||||
for (i=0; i<num_bufs; i++, buf+=3) {
|
||||
IpcBufferDescriptor* desc = (IpcBufferDescriptor*) buf;
|
||||
u64 packed = (u64) desc->Packed;
|
||||
|
||||
r->Buffers[i] = (void*) (desc->Addr | ((packed >> 28) << 32) | (((packed >> 2) & 15) << 36));
|
||||
r->BufferSizes[i] = desc->Size;
|
||||
r->BufferTypes[i] = (BufferType) (packed & 3);
|
||||
|
||||
if (i < num_bufs_send)
|
||||
r->BufferDirections[i] = BufferDirection_Send;
|
||||
else if (i < (num_bufs_send + num_bufs_recv))
|
||||
r->BufferDirections[i] = BufferDirection_Recv;
|
||||
else
|
||||
r->BufferDirections[i] = BufferDirection_Exch;
|
||||
}
|
||||
|
||||
r->NumBuffers = num_bufs;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Queries the size of an IPC pointer buffer.
|
||||
* @param session IPC session handle.
|
||||
* @param size Output variable in which to store the size.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcQueryPointerBufferSize(Handle session, size_t *size) {
|
||||
u32* buf = (u32*)armGetTls();
|
||||
|
||||
buf[0] = IpcCommandType_Control;
|
||||
buf[1] = 8;
|
||||
buf[2] = 0;
|
||||
buf[3] = 0;
|
||||
buf[4] = SFCI_MAGIC;
|
||||
buf[5] = 0;
|
||||
buf[6] = 3;
|
||||
buf[7] = 0;
|
||||
|
||||
Result rc = ipcDispatch(session);
|
||||
|
||||
if (R_SUCCEEDED(rc)) {
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct ipcQueryPointerBufferSizeResponse {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
u32 size;
|
||||
} *raw = (struct ipcQueryPointerBufferSizeResponse*)r.Raw;
|
||||
|
||||
rc = raw->result;
|
||||
|
||||
if (R_SUCCEEDED(rc)) {
|
||||
*size = raw->size & 0xffff;
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Closes the IPC session with proper clean up.
|
||||
* @param session IPC session handle.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcCloseSession(Handle session) {
|
||||
u32* buf = (u32*)armGetTls();
|
||||
buf[0] = IpcCommandType_Close;
|
||||
buf[1] = 0;
|
||||
return ipcDispatch(session);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clones an IPC session.
|
||||
* @param session IPC session handle.
|
||||
* @param unk Unknown.
|
||||
* @param new_session_out Output cloned IPC session handle.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcCloneSession(Handle session, u32 unk, Handle* new_session_out) {
|
||||
u32* buf = (u32*)armGetTls();
|
||||
|
||||
buf[0] = IpcCommandType_Control;
|
||||
buf[1] = 9;
|
||||
buf[2] = 0;
|
||||
buf[3] = 0;
|
||||
buf[4] = SFCI_MAGIC;
|
||||
buf[5] = 0;
|
||||
buf[6] = 4;
|
||||
buf[7] = 0;
|
||||
buf[8] = unk;
|
||||
|
||||
Result rc = ipcDispatch(session);
|
||||
|
||||
if (R_SUCCEEDED(rc)) {
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct ipcCloneSessionResponse {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
} *raw = (struct ipcCloneSessionResponse*)r.Raw;
|
||||
|
||||
rc = raw->result;
|
||||
|
||||
if (R_SUCCEEDED(rc) && new_session_out) {
|
||||
*new_session_out = r.Handles[0];
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
///@name IPC domain handling
|
||||
///@{
|
||||
|
||||
/**
|
||||
* @brief Converts an IPC session handle into a domain.
|
||||
* @param session IPC session handle.
|
||||
* @param object_id_out Output variable in which to store the object ID.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcConvertSessionToDomain(Handle session, u32* object_id_out) {
|
||||
u32* buf = (u32*)armGetTls();
|
||||
|
||||
buf[0] = IpcCommandType_Control;
|
||||
buf[1] = 8;
|
||||
buf[4] = SFCI_MAGIC;
|
||||
buf[5] = 0;
|
||||
buf[6] = 0;
|
||||
buf[7] = 0;
|
||||
|
||||
Result rc = ipcDispatch(session);
|
||||
|
||||
if (R_SUCCEEDED(rc)) {
|
||||
IpcParsedCommand r;
|
||||
ipcParse(&r);
|
||||
|
||||
struct ipcConvertSessionToDomainResponse {
|
||||
u64 magic;
|
||||
u64 result;
|
||||
u32 object_id;
|
||||
} *raw = (struct ipcConvertSessionToDomainResponse*)r.Raw;
|
||||
|
||||
rc = raw->result;
|
||||
|
||||
if (R_SUCCEEDED(rc)) {
|
||||
*object_id_out = raw->object_id;
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Adds an object ID to be sent through an IPC domain command structure.
|
||||
* @param cmd IPC domain command structure.
|
||||
* @param object_id Object ID to send.
|
||||
*/
|
||||
static inline void ipcSendObjectId(IpcCommand* cmd, u32 object_id) {
|
||||
cmd->ObjectIds[cmd->NumObjectIds++] = object_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Prepares the header of an IPC command structure (domain version).
|
||||
* @param cmd IPC command structure.
|
||||
* @param sizeof_raw Size in bytes of the raw data structure to embed inside the IPC request
|
||||
* @param object_id Domain object ID.
|
||||
* @return Pointer to the raw embedded data structure in the request, ready to be filled out.
|
||||
*/
|
||||
static inline void* ipcPrepareHeaderForDomain(IpcCommand* cmd, size_t sizeof_raw, u32 object_id) {
|
||||
void* raw = ipcPrepareHeader(cmd, sizeof_raw + sizeof(DomainMessageHeader) + cmd->NumObjectIds*sizeof(u32));
|
||||
DomainMessageHeader* hdr = (DomainMessageHeader*) raw;
|
||||
u32 *object_ids = (u32*)(((uintptr_t) raw) + sizeof(DomainMessageHeader) + sizeof_raw);
|
||||
|
||||
hdr->Type = DomainMessageType_SendMessage;
|
||||
hdr->NumObjectIds = (u8)cmd->NumObjectIds;
|
||||
hdr->Length = sizeof_raw;
|
||||
hdr->ThisObjectId = object_id;
|
||||
hdr->Pad[0] = hdr->Pad[1] = 0;
|
||||
|
||||
for(size_t i = 0; i < cmd->NumObjectIds; i++)
|
||||
object_ids[i] = cmd->ObjectIds[i];
|
||||
return (void*)(((uintptr_t) raw) + sizeof(DomainMessageHeader));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Parse an IPC command request into an IPC parsed command structure (domain version).
|
||||
* @param r IPC parsed command structure to fill in.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcParseDomainRequest(IpcParsedCommand* r) {
|
||||
Result rc = ipcParse(r);
|
||||
DomainMessageHeader *hdr;
|
||||
u32 *object_ids;
|
||||
if(R_FAILED(rc))
|
||||
return rc;
|
||||
|
||||
hdr = (DomainMessageHeader*) r->Raw;
|
||||
object_ids = (u32*)(((uintptr_t) hdr) + sizeof(DomainMessageHeader) + hdr->Length);
|
||||
r->Raw = (void*)(((uintptr_t) r->Raw) + sizeof(DomainMessageHeader));
|
||||
|
||||
r->IsDomainRequest = true;
|
||||
r->InMessageType = (DomainMessageType)(hdr->Type);
|
||||
switch (r->InMessageType) {
|
||||
case DomainMessageType_SendMessage:
|
||||
case DomainMessageType_Close:
|
||||
break;
|
||||
default:
|
||||
return MAKERESULT(Module_Libnx, LibnxError_DomainMessageUnknownType);
|
||||
}
|
||||
|
||||
r->InThisObjectId = hdr->ThisObjectId;
|
||||
r->InNumObjectIds = hdr->NumObjectIds > 8 ? 8 : hdr->NumObjectIds;
|
||||
if ((uintptr_t)object_ids + sizeof(u32) * r->InNumObjectIds - (uintptr_t)armGetTls() >= 0x100) {
|
||||
return MAKERESULT(Module_Libnx, LibnxError_DomainMessageTooManyObjectIds);
|
||||
}
|
||||
for(size_t i = 0; i < r->InNumObjectIds; i++)
|
||||
r->InObjectIds[i] = object_ids[i];
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Parse an IPC command response into an IPC parsed command structure (domain version).
|
||||
* @param r IPC parsed command structure to fill in.
|
||||
* @param sizeof_raw Size in bytes of the raw data structure.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcParseDomainResponse(IpcParsedCommand* r, size_t sizeof_raw) {
|
||||
Result rc = ipcParse(r);
|
||||
DomainResponseHeader *hdr;
|
||||
u32 *object_ids;
|
||||
if(R_FAILED(rc))
|
||||
return rc;
|
||||
|
||||
hdr = (DomainResponseHeader*) r->Raw;
|
||||
r->Raw = (void*)(((uintptr_t) r->Raw) + sizeof(DomainResponseHeader));
|
||||
object_ids = (u32*)(((uintptr_t) r->Raw) + sizeof_raw);//Official sw doesn't align this.
|
||||
|
||||
r->IsDomainResponse = true;
|
||||
|
||||
r->OutNumObjectIds = hdr->NumObjectIds > 8 ? 8 : hdr->NumObjectIds;
|
||||
if ((uintptr_t)object_ids + sizeof(u32) * r->OutNumObjectIds - (uintptr_t)armGetTls() >= 0x100) {
|
||||
return MAKERESULT(Module_Libnx, LibnxError_DomainMessageTooManyObjectIds);
|
||||
}
|
||||
for(size_t i = 0; i < r->OutNumObjectIds; i++)
|
||||
r->OutObjectIds[i] = object_ids[i];
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Closes a domain object by ID.
|
||||
* @param session IPC session handle.
|
||||
* @param object_id ID of the object to close.
|
||||
* @return Result code.
|
||||
*/
|
||||
static inline Result ipcCloseObjectById(Handle session, u32 object_id) {
|
||||
IpcCommand c;
|
||||
DomainMessageHeader* hdr;
|
||||
|
||||
ipcInitialize(&c);
|
||||
hdr = (DomainMessageHeader*)ipcPrepareHeader(&c, sizeof(DomainMessageHeader));
|
||||
|
||||
hdr->Type = DomainMessageType_Close;
|
||||
hdr->NumObjectIds = 0;
|
||||
hdr->Length = 0;
|
||||
hdr->ThisObjectId = object_id;
|
||||
hdr->Pad[0] = hdr->Pad[1] = 0;
|
||||
|
||||
return ipcDispatch(session); // this command has no associated response
|
||||
}
|
||||
|
||||
///@}
|
||||
165
Source/Horizon-OC-Monitor/include/max17050.h
Normal file
165
Source/Horizon-OC-Monitor/include/max17050.h
Normal file
@@ -0,0 +1,165 @@
|
||||
/*
|
||||
* Fuel gauge driver for Nintendo Switch's Maxim 17050
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics
|
||||
* MyungJoo Ham <myungjoo.ham@samsung.com>
|
||||
* Copyright (c) 2018-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Modified by: MasaGratoR
|
||||
*/
|
||||
|
||||
#ifndef __MAX17050_H_
|
||||
#define __MAX17050_H_
|
||||
|
||||
//#include <utils/types.h>
|
||||
#include "i2c.h"
|
||||
|
||||
/* Board default values */
|
||||
#define MAX17050_BOARD_CGAIN 2 /* Actual: 1.99993 */
|
||||
#define MAX17050_BOARD_SNS_RESISTOR_UOHM 5000 /* 0.005 Ohm */
|
||||
|
||||
//#define MAX17050_STATUS_BattAbsent BIT(3)
|
||||
|
||||
/* Consider RepCap which is less then 10 units below FullCAP full */
|
||||
/*
|
||||
#define MAX17050_FULL_THRESHOLD 10
|
||||
|
||||
#define MAX17050_CHARACTERIZATION_DATA_SIZE 48
|
||||
|
||||
#define MAXIM17050_I2C_ADDR 0x36
|
||||
*/
|
||||
|
||||
#define MAX17050_WAIT_NS 1000000000
|
||||
|
||||
constexpr float max17050SenseResistor = MAX17050_BOARD_SNS_RESISTOR_UOHM / 1000; // in uOhm
|
||||
constexpr float max17050CGain = 1.99993;
|
||||
|
||||
|
||||
enum MAX17050_reg {
|
||||
MAX17050_STATUS = 0x00,
|
||||
MAX17050_VALRT_Th = 0x01,
|
||||
MAX17050_TALRT_Th = 0x02,
|
||||
MAX17050_SALRT_Th = 0x03,
|
||||
MAX17050_AtRate = 0x04,
|
||||
MAX17050_RepCap = 0x05,
|
||||
MAX17050_RepSOC = 0x06,
|
||||
MAX17050_Age = 0x07,
|
||||
MAX17050_TEMP = 0x08,
|
||||
MAX17050_VCELL = 0x09,
|
||||
MAX17050_Current = 0x0A,
|
||||
MAX17050_AvgCurrent = 0x0B,
|
||||
|
||||
MAX17050_SOC = 0x0D,
|
||||
MAX17050_AvSOC = 0x0E,
|
||||
MAX17050_RemCap = 0x0F,
|
||||
MAX17050_FullCAP = 0x10,
|
||||
MAX17050_TTE = 0x11,
|
||||
MAX17050_QRTbl00 = 0x12,
|
||||
MAX17050_FullSOCThr = 0x13,
|
||||
MAX17050_RSLOW = 0x14,
|
||||
|
||||
MAX17050_AvgTA = 0x16,
|
||||
MAX17050_Cycles = 0x17,
|
||||
MAX17050_DesignCap = 0x18,
|
||||
MAX17050_AvgVCELL = 0x19,
|
||||
MAX17050_MinMaxTemp = 0x1A,
|
||||
MAX17050_MinMaxVolt = 0x1B,
|
||||
MAX17050_MinMaxCurr = 0x1C,
|
||||
MAX17050_CONFIG = 0x1D,
|
||||
MAX17050_ICHGTerm = 0x1E,
|
||||
MAX17050_AvCap = 0x1F,
|
||||
MAX17050_ManName = 0x20,
|
||||
MAX17050_DevName = 0x21,
|
||||
MAX17050_QRTbl10 = 0x22,
|
||||
MAX17050_FullCAPNom = 0x23,
|
||||
MAX17050_TempNom = 0x24,
|
||||
MAX17050_TempLim = 0x25,
|
||||
MAX17050_TempHot = 0x26,
|
||||
MAX17050_AIN = 0x27,
|
||||
MAX17050_LearnCFG = 0x28,
|
||||
MAX17050_FilterCFG = 0x29,
|
||||
MAX17050_RelaxCFG = 0x2A,
|
||||
MAX17050_MiscCFG = 0x2B,
|
||||
MAX17050_TGAIN = 0x2C,
|
||||
MAX17050_TOFF = 0x2D,
|
||||
MAX17050_CGAIN = 0x2E,
|
||||
MAX17050_COFF = 0x2F,
|
||||
|
||||
MAX17050_QRTbl20 = 0x32,
|
||||
MAX17050_SOC_empty = 0x33,
|
||||
MAX17050_T_empty = 0x34,
|
||||
MAX17050_FullCAP0 = 0x35,
|
||||
MAX17050_LAvg_empty = 0x36,
|
||||
MAX17050_FCTC = 0x37,
|
||||
MAX17050_RCOMP0 = 0x38,
|
||||
MAX17050_TempCo = 0x39,
|
||||
MAX17050_V_empty = 0x3A,
|
||||
MAX17050_K_empty0 = 0x3B,
|
||||
MAX17050_TaskPeriod = 0x3C,
|
||||
MAX17050_FSTAT = 0x3D,
|
||||
MAX17050_TIMER = 0x3E,
|
||||
MAX17050_SHDNTIMER = 0x3F,
|
||||
|
||||
MAX17050_QRTbl30 = 0x42,
|
||||
|
||||
MAX17050_dQacc = 0x45,
|
||||
MAX17050_dPacc = 0x46,
|
||||
|
||||
MAX17050_VFSOC0 = 0x48,
|
||||
|
||||
Max17050_QH0 = 0x4C,
|
||||
MAX17050_QH = 0x4D,
|
||||
MAX17050_QL = 0x4E,
|
||||
|
||||
MAX17050_MinVolt = 0x50, // Custom ID. Not to be sent to i2c.
|
||||
MAX17050_MaxVolt = 0x51, // Custom ID. Not to be sent to i2c.
|
||||
|
||||
MAX17050_VFSOC0Enable = 0x60,
|
||||
MAX17050_MODELEnable1 = 0x62,
|
||||
MAX17050_MODELEnable2 = 0x63,
|
||||
|
||||
MAX17050_MODELChrTbl = 0x80,
|
||||
|
||||
MAX17050_OCV = 0xEE,
|
||||
|
||||
MAX17050_OCVInternal = 0xFB,
|
||||
|
||||
MAX17050_VFSOC = 0xFF,
|
||||
};
|
||||
|
||||
/*
|
||||
int max17050_get_property(enum MAX17050_reg reg, int *value);
|
||||
int max17050_fix_configuration();
|
||||
u32 max17050_get_cached_batt_volt();
|
||||
*/
|
||||
#endif /* __MAX17050_H_ */
|
||||
|
||||
Result Max17050ReadReg(u8 reg, u16 *out)
|
||||
{
|
||||
u16 data = 0;
|
||||
Result res = I2cReadRegHandler16(reg, I2cDevice_Max17050, &data);
|
||||
|
||||
if (R_FAILED(res))
|
||||
{
|
||||
return res;
|
||||
}
|
||||
|
||||
*out = data;
|
||||
return res;
|
||||
}
|
||||
41
Source/Horizon-OC-Monitor/include/pcv_types.h
Normal file
41
Source/Horizon-OC-Monitor/include/pcv_types.h
Normal file
@@ -0,0 +1,41 @@
|
||||
typedef enum {
|
||||
PcvPowerDomain_Max77620_Sd0 = 0,
|
||||
PcvPowerDomain_Max77620_Sd1 = 1,
|
||||
PcvPowerDomain_Max77620_Sd2 = 2,
|
||||
PcvPowerDomain_Max77620_Sd3 = 3,
|
||||
PcvPowerDomain_Max77620_Ldo0 = 4,
|
||||
PcvPowerDomain_Max77620_Ldo1 = 5,
|
||||
PcvPowerDomain_Max77620_Ldo2 = 6,
|
||||
PcvPowerDomain_Max77620_Ldo3 = 7,
|
||||
PcvPowerDomain_Max77620_Ldo4 = 8,
|
||||
PcvPowerDomain_Max77620_Ldo5 = 9,
|
||||
PcvPowerDomain_Max77620_Ldo6 = 10,
|
||||
PcvPowerDomain_Max77620_Ldo7 = 11,
|
||||
PcvPowerDomain_Max77620_Ldo8 = 12,
|
||||
PcvPowerDomain_Max77621_Cpu = 13,
|
||||
PcvPowerDomain_Max77621_Gpu = 14,
|
||||
PcvPowerDomain_Max77812_Cpu = 15,
|
||||
PcvPowerDomain_Max77812_Gpu = 16,
|
||||
PcvPowerDomain_Max77812_Dram = 17,
|
||||
} PowerDomain;
|
||||
|
||||
typedef enum {
|
||||
PcvPowerDomainId_Max77620_Sd0 = 0x3A000080,
|
||||
PcvPowerDomainId_Max77620_Sd1 = 0x3A000081,
|
||||
PcvPowerDomainId_Max77620_Sd2 = 0x3A000082,
|
||||
PcvPowerDomainId_Max77620_Sd3 = 0x3A000083,
|
||||
PcvPowerDomainId_Max77620_Ldo0 = 0x3A0000A0,
|
||||
PcvPowerDomainId_Max77620_Ldo1 = 0x3A0000A1,
|
||||
PcvPowerDomainId_Max77620_Ldo2 = 0x3A0000A2,
|
||||
PcvPowerDomainId_Max77620_Ldo3 = 0x3A0000A3,
|
||||
PcvPowerDomainId_Max77620_Ldo4 = 0x3A0000A4,
|
||||
PcvPowerDomainId_Max77620_Ldo5 = 0x3A0000A5,
|
||||
PcvPowerDomainId_Max77620_Ldo6 = 0x3A0000A6,
|
||||
PcvPowerDomainId_Max77620_Ldo7 = 0x3A0000A7,
|
||||
PcvPowerDomainId_Max77620_Ldo8 = 0x3A0000A8,
|
||||
PcvPowerDomainId_Max77621_Cpu = 0x3A000003,
|
||||
PcvPowerDomainId_Max77621_Gpu = 0x3A000004,
|
||||
PcvPowerDomainId_Max77812_Cpu = 0x3A000003,
|
||||
PcvPowerDomainId_Max77812_Gpu = 0x3A000004,
|
||||
PcvPowerDomainId_Max77812_Dram = 0x3A000005,
|
||||
} PowerDomainId;
|
||||
22
Source/Horizon-OC-Monitor/include/pwm.h
Normal file
22
Source/Horizon-OC-Monitor/include/pwm.h
Normal file
@@ -0,0 +1,22 @@
|
||||
#pragma once
|
||||
|
||||
#include <switch.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
Service s;
|
||||
} PwmChannelSession;
|
||||
|
||||
Result pwmInitialize(void);
|
||||
void pwmExit(void);
|
||||
Service* pwmGetServiceSession(void);
|
||||
Result pwmOpenSession2(PwmChannelSession *out, u32 device_code);
|
||||
Result pwmChannelSessionGetDutyCycle(PwmChannelSession *c, double* out);
|
||||
void pwmChannelSessionClose(PwmChannelSession *c);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
19
Source/Horizon-OC-Monitor/include/rgltr.h
Normal file
19
Source/Horizon-OC-Monitor/include/rgltr.h
Normal file
@@ -0,0 +1,19 @@
|
||||
#pragma once
|
||||
#include <switch.h>
|
||||
#include "pcv_types.h"
|
||||
|
||||
typedef struct {
|
||||
Service s;
|
||||
} RgltrSession;
|
||||
|
||||
Result rgltrInitialize(void);
|
||||
|
||||
void rgltrExit(void);
|
||||
|
||||
Service* rgltrGetServiceSession(void);
|
||||
|
||||
Result rgltrOpenSession(RgltrSession* session_out, PowerDomainId module_id);
|
||||
void rgltrCloseSession(RgltrSession* session);
|
||||
Result rgltrGetVoltage(RgltrSession* session, u32 *out_volt);
|
||||
Result rgltrGetPowerModuleNumLimit(u32 *out);
|
||||
Result rgltrGetVoltageEnabled(RgltrSession* session, u32 *out);
|
||||
29
Source/Horizon-OC-Monitor/include/rgltr_services.h
Normal file
29
Source/Horizon-OC-Monitor/include/rgltr_services.h
Normal file
@@ -0,0 +1,29 @@
|
||||
// rgltr_services.h
|
||||
// ========
|
||||
// Minimal header declarations for rgltr‐related functionality.
|
||||
// Any file that wants to call rgltrOpenSession(), rgltrGetVoltage(), etc. should
|
||||
// simply do `#include "infonx.h"` (NOT infonx.cpp).
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <switch.h> // for Service, Result, hosversionBefore(), smGetService(), serviceClose(), etc.
|
||||
#include "rgltr.h" // for RgltrSession, PowerDomainId, etc.
|
||||
|
||||
// Global service handle for "rgltr". Defined in infonx.cpp.
|
||||
extern Service g_rgltrSrv;
|
||||
|
||||
// Open/close the "rgltr" service. You must call rgltrInitialize() (once) before using
|
||||
// rgltrOpenSession() & friends. Call rgltrExit() when your app is shutting down.
|
||||
Result rgltrInitialize(void);
|
||||
void rgltrExit(void);
|
||||
|
||||
// Open a regulator session for the given PowerDomainId (e.g. CPU, GPU, DRAM).
|
||||
// On success, (*session_out).s will contain a valid Service handle.
|
||||
Result rgltrOpenSession(RgltrSession* session_out, PowerDomainId module_id);
|
||||
|
||||
// Query the current voltage (in microvolts, µV) from a previously opened session.
|
||||
// Writes the result into *out_volt.
|
||||
Result rgltrGetVoltage(RgltrSession* session, u32* out_volt);
|
||||
|
||||
// Close a previously opened regulator session.
|
||||
void rgltrCloseSession(RgltrSession* session);
|
||||
126
Source/Horizon-OC-Monitor/include/sysclk/board.h
Normal file
126
Source/Horizon-OC-Monitor/include/sysclk/board.h
Normal file
@@ -0,0 +1,126 @@
|
||||
/*
|
||||
* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
* wrote this file. As long as you retain this notice you can do whatever you
|
||||
* want with this stuff. If you meet any of us some day, and you think this
|
||||
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SysClkSocType_Erista = 0,
|
||||
SysClkSocType_Mariko,
|
||||
SysClkSocType_EnumMax
|
||||
} SysClkSocType;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SysClkProfile_Handheld = 0,
|
||||
SysClkProfile_HandheldCharging,
|
||||
SysClkProfile_HandheldChargingUSB,
|
||||
SysClkProfile_HandheldChargingOfficial,
|
||||
SysClkProfile_Docked,
|
||||
SysClkProfile_EnumMax
|
||||
} SysClkProfile;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SysClkModule_CPU = 0,
|
||||
SysClkModule_GPU,
|
||||
SysClkModule_MEM,
|
||||
SysClkModule_EnumMax
|
||||
} SysClkModule;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SysClkThermalSensor_SOC = 0,
|
||||
SysClkThermalSensor_PCB,
|
||||
SysClkThermalSensor_Skin,
|
||||
SysClkThermalSensor_EnumMax
|
||||
} SysClkThermalSensor;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SysClkPowerSensor_Now = 0,
|
||||
SysClkPowerSensor_Avg,
|
||||
SysClkPowerSensor_EnumMax
|
||||
} SysClkPowerSensor;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SysClkRamLoad_All = 0,
|
||||
SysClkRamLoad_Cpu,
|
||||
SysClkRamLoad_EnumMax
|
||||
} SysClkRamLoad;
|
||||
|
||||
#define SYSCLK_ENUM_VALID(n, v) ((v) < n##_EnumMax)
|
||||
|
||||
static inline const char* sysclkFormatModule(SysClkModule module, bool pretty)
|
||||
{
|
||||
switch(module)
|
||||
{
|
||||
case SysClkModule_CPU:
|
||||
return pretty ? "CPU" : "cpu";
|
||||
case SysClkModule_GPU:
|
||||
return pretty ? "GPU" : "gpu";
|
||||
case SysClkModule_MEM:
|
||||
return pretty ? "Memory" : "mem";
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static inline const char* sysclkFormatThermalSensor(SysClkThermalSensor thermSensor, bool pretty)
|
||||
{
|
||||
switch(thermSensor)
|
||||
{
|
||||
case SysClkThermalSensor_SOC:
|
||||
return pretty ? "SOC" : "soc";
|
||||
case SysClkThermalSensor_PCB:
|
||||
return pretty ? "PCB" : "pcb";
|
||||
case SysClkThermalSensor_Skin:
|
||||
return pretty ? "Skin" : "skin";
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static inline const char* sysclkFormatPowerSensor(SysClkPowerSensor powSensor, bool pretty)
|
||||
{
|
||||
switch(powSensor)
|
||||
{
|
||||
case SysClkPowerSensor_Now:
|
||||
return pretty ? "Now" : "now";
|
||||
case SysClkPowerSensor_Avg:
|
||||
return pretty ? "Avg" : "avg";
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static inline const char* sysclkFormatProfile(SysClkProfile profile, bool pretty)
|
||||
{
|
||||
switch(profile)
|
||||
{
|
||||
case SysClkProfile_Docked:
|
||||
return pretty ? "Docked" : "docked";
|
||||
case SysClkProfile_Handheld:
|
||||
return pretty ? "Handheld" : "handheld";
|
||||
case SysClkProfile_HandheldCharging:
|
||||
return pretty ? "Charging" : "handheld_charging";
|
||||
case SysClkProfile_HandheldChargingUSB:
|
||||
return pretty ? "USB Charger" : "handheld_charging_usb";
|
||||
case SysClkProfile_HandheldChargingOfficial:
|
||||
return pretty ? "Official Charger" : "handheld_charging_official";
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
38
Source/Horizon-OC-Monitor/include/sysclk/client/ipc.h
Normal file
38
Source/Horizon-OC-Monitor/include/sysclk/client/ipc.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
* wrote this file. As long as you retain this notice you can do whatever you
|
||||
* want with this stuff. If you meet any of us some day, and you think this
|
||||
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "types.h"
|
||||
#include "../config.h"
|
||||
#include "../board.h"
|
||||
#include "../ipc.h"
|
||||
|
||||
bool sysclkIpcRunning();
|
||||
Result sysclkIpcInitialize(void);
|
||||
void sysclkIpcExit(void);
|
||||
|
||||
Result sysclkIpcGetAPIVersion(u32* out_ver);
|
||||
Result sysclkIpcGetVersionString(char* out, size_t len);
|
||||
Result sysclkIpcGetCurrentContext(SysClkContext* out_context);
|
||||
Result sysclkIpcGetProfileCount(u64 tid, u8* out_count);
|
||||
Result sysclkIpcSetEnabled(bool enabled);
|
||||
Result sysclkIpcExitCmd();
|
||||
Result sysclkIpcSetOverride(SysClkModule module, u32 hz);
|
||||
Result sysclkIpcGetProfiles(u64 tid, SysClkTitleProfileList* out_profiles);
|
||||
Result sysclkIpcSetProfiles(u64 tid, SysClkTitleProfileList* profiles);
|
||||
Result sysclkIpcGetConfigValues(SysClkConfigValueList* out_configValues);
|
||||
Result sysclkIpcSetConfigValues(SysClkConfigValueList* configValues);
|
||||
Result sysclkIpcGetFreqList(SysClkModule module, u32* list, u32 maxCount, u32* outCount);
|
||||
|
||||
static inline Result sysclkIpcRemoveOverride(SysClkModule module)
|
||||
{
|
||||
return sysclkIpcSetOverride(module, 0);
|
||||
}
|
||||
29
Source/Horizon-OC-Monitor/include/sysclk/client/types.h
Normal file
29
Source/Horizon-OC-Monitor/include/sysclk/client/types.h
Normal file
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
* wrote this file. As long as you retain this notice you can do whatever you
|
||||
* want with this stuff. If you meet any of us some day, and you think this
|
||||
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __SWITCH__
|
||||
|
||||
#include <switch/types.h>
|
||||
#include <switch/result.h>
|
||||
|
||||
#else
|
||||
|
||||
#define R_FAILED(res) ((res) != 0)
|
||||
#define R_SUCCEEDED(res) ((res) == 0)
|
||||
|
||||
typedef std::uint32_t Result;
|
||||
typedef std::uint32_t u32;
|
||||
typedef std::int32_t s32;
|
||||
typedef std::uint64_t u64;
|
||||
typedef std::uint8_t u8;
|
||||
|
||||
#endif
|
||||
51
Source/Horizon-OC-Monitor/include/sysclk/clock_manager.h
Normal file
51
Source/Horizon-OC-Monitor/include/sysclk/clock_manager.h
Normal file
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
* wrote this file. As long as you retain this notice you can do whatever you
|
||||
* want with this stuff. If you meet any of us some day, and you think this
|
||||
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "board.h"
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t enabled;
|
||||
uint64_t applicationId;
|
||||
SysClkProfile profile;
|
||||
uint32_t freqs[SysClkModule_EnumMax];
|
||||
uint32_t realFreqs[SysClkModule_EnumMax];
|
||||
uint32_t overrideFreqs[SysClkModule_EnumMax];
|
||||
uint32_t temps[SysClkThermalSensor_EnumMax];
|
||||
int32_t power[SysClkPowerSensor_EnumMax];
|
||||
uint32_t ramLoad[SysClkRamLoad_EnumMax];
|
||||
uint32_t realVolts[4];
|
||||
uint32_t perfConfId;
|
||||
SysClkProfile realProfile;
|
||||
int32_t reserved[5];
|
||||
uint32_t reserved2;
|
||||
} SysClkContext;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wdeprecated-enum-enum-conversion"
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
uint32_t mhz[SysClkProfile_EnumMax * SysClkModule_EnumMax];
|
||||
uint32_t mhzMap[SysClkProfile_EnumMax][SysClkModule_EnumMax];
|
||||
};
|
||||
} SysClkTitleProfileList;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#define SYSCLK_FREQ_LIST_MAX 32
|
||||
78
Source/Horizon-OC-Monitor/include/sysclk/config.h
Normal file
78
Source/Horizon-OC-Monitor/include/sysclk/config.h
Normal file
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
* wrote this file. As long as you retain this notice you can do whatever you
|
||||
* want with this stuff. If you meet any of us some day, and you think this
|
||||
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
typedef enum {
|
||||
SysClkConfigValue_PollingIntervalMs = 0,
|
||||
SysClkConfigValue_TempLogIntervalMs,
|
||||
SysClkConfigValue_FreqLogIntervalMs,
|
||||
SysClkConfigValue_PowerLogIntervalMs,
|
||||
SysClkConfigValue_CsvWriteIntervalMs,
|
||||
SysClkConfigValue_EnumMax,
|
||||
} SysClkConfigValue;
|
||||
|
||||
typedef struct {
|
||||
uint64_t values[SysClkConfigValue_EnumMax];
|
||||
} SysClkConfigValueList;
|
||||
|
||||
static inline const char* sysclkFormatConfigValue(SysClkConfigValue val, bool pretty)
|
||||
{
|
||||
switch(val)
|
||||
{
|
||||
case SysClkConfigValue_PollingIntervalMs:
|
||||
return pretty ? "Polling Interval (ms)" : "poll_interval_ms";
|
||||
case SysClkConfigValue_TempLogIntervalMs:
|
||||
return pretty ? "Temperature logging interval (ms)" : "temp_log_interval_ms";
|
||||
case SysClkConfigValue_FreqLogIntervalMs:
|
||||
return pretty ? "Frequency logging interval (ms)" : "freq_log_interval_ms";
|
||||
case SysClkConfigValue_PowerLogIntervalMs:
|
||||
return pretty ? "Power logging interval (ms)" : "power_log_interval_ms";
|
||||
case SysClkConfigValue_CsvWriteIntervalMs:
|
||||
return pretty ? "CSV write interval (ms)" : "csv_write_interval_ms";
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint64_t sysclkDefaultConfigValue(SysClkConfigValue val)
|
||||
{
|
||||
switch(val)
|
||||
{
|
||||
case SysClkConfigValue_PollingIntervalMs:
|
||||
return 300ULL;
|
||||
case SysClkConfigValue_TempLogIntervalMs:
|
||||
case SysClkConfigValue_FreqLogIntervalMs:
|
||||
case SysClkConfigValue_PowerLogIntervalMs:
|
||||
case SysClkConfigValue_CsvWriteIntervalMs:
|
||||
return 0ULL;
|
||||
default:
|
||||
return 0ULL;
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint64_t sysclkValidConfigValue(SysClkConfigValue val, uint64_t input)
|
||||
{
|
||||
switch(val)
|
||||
{
|
||||
case SysClkConfigValue_PollingIntervalMs:
|
||||
return input > 0;
|
||||
case SysClkConfigValue_TempLogIntervalMs:
|
||||
case SysClkConfigValue_FreqLogIntervalMs:
|
||||
case SysClkConfigValue_PowerLogIntervalMs:
|
||||
case SysClkConfigValue_CsvWriteIntervalMs:
|
||||
return input >= 0;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
53
Source/Horizon-OC-Monitor/include/sysclk/ipc.h
Normal file
53
Source/Horizon-OC-Monitor/include/sysclk/ipc.h
Normal file
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
* wrote this file. As long as you retain this notice you can do whatever you
|
||||
* want with this stuff. If you meet any of us some day, and you think this
|
||||
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "board.h"
|
||||
#include "clock_manager.h"
|
||||
|
||||
#define SYSCLK_IPC_API_VERSION 4
|
||||
#define SYSCLK_IPC_SERVICE_NAME "sys:clk"
|
||||
|
||||
enum SysClkIpcCmd
|
||||
{
|
||||
SysClkIpcCmd_GetApiVersion = 0,
|
||||
SysClkIpcCmd_GetVersionString = 1,
|
||||
SysClkIpcCmd_GetCurrentContext = 2,
|
||||
SysClkIpcCmd_Exit = 3,
|
||||
SysClkIpcCmd_GetProfileCount = 4,
|
||||
SysClkIpcCmd_GetProfiles = 5,
|
||||
SysClkIpcCmd_SetProfiles = 6,
|
||||
SysClkIpcCmd_SetEnabled = 7,
|
||||
SysClkIpcCmd_SetOverride = 8,
|
||||
SysClkIpcCmd_GetConfigValues = 9,
|
||||
SysClkIpcCmd_SetConfigValues = 10,
|
||||
SysClkIpcCmd_GetFreqList = 11,
|
||||
};
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint64_t tid;
|
||||
SysClkTitleProfileList profiles;
|
||||
} SysClkIpc_SetProfiles_Args;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
SysClkModule module;
|
||||
uint32_t hz;
|
||||
} SysClkIpc_SetOverride_Args;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
SysClkModule module;
|
||||
uint32_t maxCount;
|
||||
} SysClkIpc_GetFreqList_Args;
|
||||
103
Source/Horizon-OC-Monitor/include/tmp451.h
Normal file
103
Source/Horizon-OC-Monitor/include/tmp451.h
Normal file
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* SOC/PCB Temperature driver for Nintendo Switch's TI TMP451
|
||||
*
|
||||
* Copyright (c) 2018 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Modified by: MasaGratoR
|
||||
*/
|
||||
|
||||
#ifndef __TMP451_H_
|
||||
#define __TMP451_H_
|
||||
|
||||
//#include <utils/types.h>
|
||||
#include "i2c.h"
|
||||
|
||||
//#define TMP451_I2C_ADDR 0x4C
|
||||
|
||||
#define TMP451_PCB_TEMP_REG 0x00
|
||||
#define TMP451_SOC_TEMP_REG 0x01
|
||||
|
||||
/*
|
||||
#define TMP451_CONFIG_REG 0x09
|
||||
#define TMP451_CNV_RATE_REG 0x0A
|
||||
*/
|
||||
|
||||
#define TMP451_SOC_TEMP_DEC_REG 0x10
|
||||
#define TMP451_PCB_TEMP_DEC_REG 0x15
|
||||
|
||||
/*
|
||||
#define TMP451_SOC_TMP_OFH_REG 0x11
|
||||
#define TMP451_SOC_TMP_OFL_REG 0x12
|
||||
*/
|
||||
|
||||
// If input is false, the return value is packed. MSByte is the integer in oC
|
||||
// and the LSByte is the decimal point truncated to 2 decimal places.
|
||||
// Otherwise it's an integer oC.
|
||||
/*
|
||||
u16 tmp451_get_soc_temp(bool integer);
|
||||
u16 tmp451_get_pcb_temp(bool integer);
|
||||
void tmp451_init();
|
||||
void tmp451_end();
|
||||
*/
|
||||
|
||||
Result Tmp451ReadReg(u8 reg, u8 *out)
|
||||
{
|
||||
u8 data = 0;
|
||||
Result res = I2cReadRegHandler8(reg, I2cDevice_Tmp451, &data);
|
||||
|
||||
if (R_FAILED(res))
|
||||
{
|
||||
return res;
|
||||
}
|
||||
|
||||
*out = data;
|
||||
return res;
|
||||
}
|
||||
|
||||
Result Tmp451GetSocTemp(float* temperature) {
|
||||
u8 integer = 0;
|
||||
u8 decimals = 0;
|
||||
|
||||
Result rc = Tmp451ReadReg(TMP451_SOC_TEMP_REG, &integer);
|
||||
if (R_FAILED(rc))
|
||||
return rc;
|
||||
rc = Tmp451ReadReg(TMP451_SOC_TEMP_DEC_REG, &decimals);
|
||||
if (R_FAILED(rc))
|
||||
return rc;
|
||||
|
||||
decimals = ((u16)(decimals >> 4) * 625) / 100;
|
||||
*temperature = (float)(integer) + ((float)(decimals) / 100);
|
||||
return rc;
|
||||
}
|
||||
|
||||
Result Tmp451GetPcbTemp(float* temperature) {
|
||||
u8 integer = 0;
|
||||
u8 decimals = 0;
|
||||
|
||||
Result rc = Tmp451ReadReg(TMP451_PCB_TEMP_REG, &integer);
|
||||
if (R_FAILED(rc))
|
||||
return rc;
|
||||
rc = Tmp451ReadReg(TMP451_PCB_TEMP_DEC_REG, &decimals);
|
||||
if (R_FAILED(rc))
|
||||
return rc;
|
||||
|
||||
decimals = ((u16)(decimals >> 4) * 625) / 100;
|
||||
*temperature = (float)(integer) + ((float)(decimals) / 100);
|
||||
return rc;
|
||||
}
|
||||
|
||||
#endif /* __TMP451_H_ */
|
||||
189
Source/Horizon-OC-Monitor/lang/de.json
Normal file
189
Source/Horizon-OC-Monitor/lang/de.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Modi",
|
||||
"Modes Configure": "Modi Konfigurieren",
|
||||
"Full": "Voll",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Mikro",
|
||||
"FPS Graph": "FPS-Diagramm",
|
||||
"FPS Counter": "FPS-Zähler",
|
||||
"Game Resolutions": "Spielauflösungen",
|
||||
"Other": "Sonstiges",
|
||||
"Battery/Charger": "Akku/Ladegerät",
|
||||
"Miscellaneous": "Verschiedenes",
|
||||
"CPU Usage": "CPU-Auslastung",
|
||||
"GPU Usage": "GPU-Auslastung",
|
||||
"RAM Usage": "RAM-Auslastung",
|
||||
"Target Frequency": "Ziel-Frequenz",
|
||||
"Real Frequency": "Aktuelle Frequenz",
|
||||
"Core 0 ": "Kern 0 ",
|
||||
"Core 1 ": "Kern 1 ",
|
||||
"Core 2 ": "Kern 2 ",
|
||||
"Core 3 ": "Kern 3 ",
|
||||
"Load": "Auslastung",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Gesamt\nAnwendung\nApplet\nSystem\nSystem (unsicher)",
|
||||
"Board": "Board",
|
||||
"Battery Power Flow": "Akkuleistungsfluss",
|
||||
"\nTemperatures": "\nTemperaturen",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Lüfterdrehzahl",
|
||||
"Game": "Spiel",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Auflösungen ",
|
||||
"Read Speed ": "Lesegeschwindigkeit ",
|
||||
"Press ": "Drücke ",
|
||||
" to Exit": " zum Beenden",
|
||||
"Depth": "Tiefe",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Spiel läuft nicht\noder ist inkompatibel.",
|
||||
"Battery Stats": "Akkustatistiken",
|
||||
"Actual Capacity": "Aktuelle Kapazität",
|
||||
"Designed Capacity": "Nennkapazität",
|
||||
"Temperature": "Temperatur",
|
||||
"Raw Charge": "Rohladung",
|
||||
"Age": "Alter",
|
||||
"Voltage": "Spannung",
|
||||
"Current Flow": "Stromfluss",
|
||||
"Power Flow": "Leistungsfluss",
|
||||
"Remaining Time": "Verbleibende Zeit",
|
||||
"Charger Stats": "Ladegerät-Statistiken",
|
||||
"Input Current Limit": "Eingangsstrombegrenzung",
|
||||
"VBUS Current Limit": "VBUS-Strombegrenzung",
|
||||
"Voltage Limit": "Spannungsbegrenzung",
|
||||
"Current Limit": "Strombegrenzung",
|
||||
"Type": "Typ",
|
||||
"Max Voltage": "Max. Spannung",
|
||||
"Max Current": "Max. Strom",
|
||||
"Multimedia Clock Rates": "Multimedia-Taktraten",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Netzwerk",
|
||||
"Type: Wi-Fi": "Typ: Wi-Fi",
|
||||
"Press Y to show password": "Drücke Y, um Passwort anzuzeigen",
|
||||
"Type: Ethernet": "Typ: Ethernet",
|
||||
"Type: Not connected": "Typ: Nicht verbunden",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Elemente Nach unten Nach oben",
|
||||
"Transparent": "Transparent",
|
||||
"Opaque": "Undurchsichtig",
|
||||
"Alpha": "Alpha",
|
||||
"Pretty": "Hübsch",
|
||||
"Compact": "Kompakt",
|
||||
"FileSafe": "Dateisicher",
|
||||
"Day+Time": "Tag+Uhrzeit",
|
||||
"Date+Time(s)": "Datum+Uhrzeit(s)",
|
||||
"Date+Time AM/PM": "Datum+Uhrzeit AM/PM",
|
||||
"Date+Time(s) AM/PM": "Datum+Uhrzeit(s) AM/PM",
|
||||
"Date+Time EU": "Datum+Uhrzeit EU",
|
||||
"Date+Time EU AM/PM": "Datum+Uhrzeit EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Datum+Uhrzeit(s) EU AM/PM",
|
||||
"Date+Time ISO": "Datum+Uhrzeit ISO",
|
||||
"Time 24h": "Uhrzeit 24h",
|
||||
"Time AM/PM": "Uhrzeit AM/PM",
|
||||
"Time(s) 24h": "Uhrzeit(s) 24h",
|
||||
"Time(s) AM/PM": "Uhrzeit(s) AM/PM",
|
||||
"Date US": "Datum US",
|
||||
"Date EU": "Datum EU",
|
||||
"Date ISO": "Datum ISO",
|
||||
"Date Short": "Datum kurz",
|
||||
"DTC Format": "DTC-Format",
|
||||
"Toggles": "Schalter",
|
||||
"Info": "Info anzeigen",
|
||||
"Disable Screenshots": "Bildschirmfotos deaktivieren",
|
||||
"Real Freqs": "Aktuelle Frequenzen",
|
||||
"Deltas": "Deltas",
|
||||
"Target Freqs": "Ziel-Frequenzen",
|
||||
"FPS": "FPS",
|
||||
"RES": "AUFL",
|
||||
"Read Speed": "Lesegeschwindigkeit",
|
||||
"Real Frequencies": "Aktuelle Frequenzen",
|
||||
"Real Voltages": "Aktuelle Spannungen",
|
||||
"Full CPU": "Volle CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Volle Auflösung",
|
||||
"SOC Voltage": "SOC-Spannung",
|
||||
"RAM Load CPU/GPU": "RAM-Last CPU/GPU",
|
||||
"Use DTC Symbol": "DTC-Symbol verwenden",
|
||||
"Use Dynamic Colors": "Dynamische Farben verwenden",
|
||||
"Sleep Exit": "Beenden aus Ruhezustand",
|
||||
"Configuration": "Konfiguration",
|
||||
"Refresh Rate": "Bildwiederholrate",
|
||||
"Frame Padding": "Rahmenabstand",
|
||||
" Font Size": " Schriftgröße",
|
||||
"Font Sizes": "Schriftgrößen",
|
||||
"Handheld Font Size": "Handheld-Schriftgröße",
|
||||
"Docked Font Size": "Docked-Schriftgröße",
|
||||
"Black": "Schwarz",
|
||||
"Dark Gray": "Dunkelgrau",
|
||||
"Gray": "Grau",
|
||||
"Light Gray": "Hellgrau",
|
||||
"Silver": "Silber",
|
||||
"White": "Weiß",
|
||||
"Dark Red": "Dunkelrot",
|
||||
"Red": "Rot",
|
||||
"Light Red": "Hellrot",
|
||||
"Pink": "Pink",
|
||||
"Dark Green": "Dunkelgrün",
|
||||
"Green": "Grün",
|
||||
"Lime Green": "Limette",
|
||||
"Light Green": "Hellgrün",
|
||||
"Dark Blue": "Dunkelblau",
|
||||
"Blue": "Blau",
|
||||
"Light Blue": "Hellblau",
|
||||
"Sky Blue": "Himmelblau",
|
||||
"Dark Purple": "Dunkellila",
|
||||
"Purple": "Lila",
|
||||
"Light Purple": "Helllila",
|
||||
"Violet": "Violett",
|
||||
"Orange": "Orange",
|
||||
"Yellow": "Gelb",
|
||||
"Light Yellow": "Hellgelb",
|
||||
"Teal": "Petrol",
|
||||
"Cyan": "Cyan",
|
||||
"Light Cyan": "Hellcyan",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Knallpink",
|
||||
"Brown": "Braun",
|
||||
"Light Brown": "Hellbraun",
|
||||
"Colors": "Farben",
|
||||
"Background Color": "Hintergrundfarbe",
|
||||
"Background Alpha": "Hintergrund-Alpha",
|
||||
"Focus Color": "Fokusfarbe",
|
||||
"Focus Alpha": "Fokus-Alpha",
|
||||
"Text Color": "Textfarbe",
|
||||
"Border": "Rahmen",
|
||||
"Dashed Line": "Gestrichelte Linie",
|
||||
"Max FPS Text": "Max-FPS-Text",
|
||||
"Min FPS Text": "Min-FPS-Text",
|
||||
"Main Line": "Hauptlinie",
|
||||
"Rounded Line": "Abgerundete Linie",
|
||||
"Perfect Line": "Perfekte Linie",
|
||||
" Color": " Farbe",
|
||||
" Alpha": " Alpha",
|
||||
"Category Color": "Kategoriefarbe",
|
||||
"Category Color 1": "Kategoriefarbe 1",
|
||||
"Category Color 2": "Kategoriefarbe 2",
|
||||
"Separator Color": "Trennlinienfarbe",
|
||||
"Elements": "Elemente",
|
||||
"Text Alignment": "Textausrichtung",
|
||||
"Vertical Position": "Vertikale Position",
|
||||
"Horizontal Position": "Horizontale Position",
|
||||
"Left": "Links",
|
||||
"Right": "Rechts",
|
||||
"Top": "Oben",
|
||||
"Center": "Mitte",
|
||||
"Bottom": "Unten",
|
||||
"FPS Counter Color": "FPS-Zähler-Farbe",
|
||||
"FPS Counter Alpha": "FPS-Zähler-Alpha",
|
||||
"Border Color": "Rahmenfarbe",
|
||||
"Dashed Line Color": "Gestrichelte-Linie-Farbe",
|
||||
"Dashed Line Alpha": "Gestrichelte-Linie-Alpha",
|
||||
"Max FPS Text Color": "Max-FPS-Textfarbe",
|
||||
"Min FPS Text Color": "Min-FPS-Textfarbe",
|
||||
"Main Line Color": "Hauptlinienfarbe",
|
||||
"Rounded Line Color": "Abgerundete-Linienfarbe",
|
||||
"Perfect Line Color": "Perfekte-Linienfarbe"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/en.json
Normal file
189
Source/Horizon-OC-Monitor/lang/en.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Modes",
|
||||
"Modes Configure": "Modes Configure",
|
||||
"Full": "Full",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Micro",
|
||||
"FPS Graph": "FPS Graph",
|
||||
"FPS Counter": "FPS Counter",
|
||||
"Game Resolutions": "Game Resolutions",
|
||||
"Other": "Other",
|
||||
"Battery/Charger": "Battery/Charger",
|
||||
"Miscellaneous": "Miscellaneous",
|
||||
"CPU Usage": "CPU Usage",
|
||||
"GPU Usage": "GPU Usage",
|
||||
"RAM Usage": "RAM Usage",
|
||||
"Target Frequency": "Target Frequency",
|
||||
"Real Frequency": "Real Frequency",
|
||||
"Core 0 ": "Core 0 ",
|
||||
"Core 1 ": "Core 1 ",
|
||||
"Core 2 ": "Core 2 ",
|
||||
"Core 3 ": "Core 3 ",
|
||||
"Load": "Load",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Total\nApplication\nApplet\nSystem\nSystem Unsafe",
|
||||
"Board": "Board",
|
||||
"Battery Power Flow": "Battery Power Flow",
|
||||
"\nTemperatures": "\nTemperatures",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Fan Rotation Level",
|
||||
"Game": "Game",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Resolutions ",
|
||||
"Read Speed ": "Read speed ",
|
||||
"Press ": "Press ",
|
||||
" to Exit": " to Exit",
|
||||
"Depth": "Depth",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Game is not running\nor it's incompatible.",
|
||||
"Battery Stats": "Battery Stats",
|
||||
"Actual Capacity": "Actual Capacity",
|
||||
"Designed Capacity": "Designed Capacity",
|
||||
"Temperature": "Temperature",
|
||||
"Raw Charge": "Raw Charge",
|
||||
"Age": "Age",
|
||||
"Voltage": "Voltage",
|
||||
"Current Flow": "Current Flow",
|
||||
"Power Flow": "Power Flow",
|
||||
"Remaining Time": "Remaining Time",
|
||||
"Charger Stats": "Charger Stats",
|
||||
"Input Current Limit": "Input Current Limit",
|
||||
"VBUS Current Limit": "VBUS Current Limit",
|
||||
"Voltage Limit": "Voltage Limit",
|
||||
"Current Limit": "Current Limit",
|
||||
"Type": "Type",
|
||||
"Max Voltage": "Max Voltage",
|
||||
"Max Current": "Max Current",
|
||||
"Multimedia Clock Rates": "Multimedia Clock Rates",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Network",
|
||||
"Type: Wi-Fi": "Type: Wi-Fi",
|
||||
"Press Y to show password": "Press Y to show password",
|
||||
"Type: Ethernet": "Type: Ethernet",
|
||||
"Type: Not connected": "Tipo: Not connected",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Elements Move Down Move Up",
|
||||
"Transparent": "Transparent",
|
||||
"Opaque": "Opaque",
|
||||
"Alpha": "Alpha",
|
||||
"Pretty": "Pretty",
|
||||
"Compact": "Compact",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "Day+Time",
|
||||
"Date+Time(s)": "Date+Time(s)",
|
||||
"Date+Time AM/PM": "Date+Time AM/PM",
|
||||
"Date+Time(s) AM/PM": "Date+Time(s) AM/PM",
|
||||
"Date+Time EU": "Date+Time EU",
|
||||
"Date+Time EU AM/PM": "Date+Time EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Date+Time(s) EU AM/PM",
|
||||
"Date+Time ISO": "Date+Time ISO",
|
||||
"Time 24h": "Time 24h",
|
||||
"Time AM/PM": "Time AM/PM",
|
||||
"Time(s) 24h": "Time(s) 24h",
|
||||
"Time(s) AM/PM": "Time(s) AM/PM",
|
||||
"Date US": "Date US",
|
||||
"Date EU": "Date EU",
|
||||
"Date ISO": "Date ISO",
|
||||
"Date Short": "Date Short",
|
||||
"DTC Format": "DTC Format",
|
||||
"Toggles": "Toggles",
|
||||
"Info": "Show Info",
|
||||
"Disable Screenshots": "Disable Screenshots",
|
||||
"Real Freqs": "Real Freqs",
|
||||
"Deltas": "Deltas",
|
||||
"Target Freqs": "Target Freqs",
|
||||
"FPS": "FPS",
|
||||
"RES": "RES",
|
||||
"Read Speed": "Read Speed",
|
||||
"Real Frequencies": "Real Frequencies",
|
||||
"Real Voltages": "Real Voltages",
|
||||
"Full CPU": "Full CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Full Resolution",
|
||||
"SOC Voltage": "SOC Voltage",
|
||||
"RAM Load CPU/GPU": "RAM Load CPU/GPU",
|
||||
"Use DTC Symbol": "Use DTC Symbol",
|
||||
"Use Dynamic Colors": "Use Dynamic Colors",
|
||||
"Sleep Exit": "Sleep Exit",
|
||||
"Configuration": "Configuration",
|
||||
"Refresh Rate": "Refresh Rate",
|
||||
"Frame Padding": "Frame Padding",
|
||||
" Font Size": " Font Size",
|
||||
"Font Sizes": "Font Sizes",
|
||||
"Handheld Font Size": "Handheld Font Size",
|
||||
"Docked Font Size": "Docked Font Size",
|
||||
"Black": "Black",
|
||||
"Dark Gray": "Dark Gray",
|
||||
"Gray": "Gray",
|
||||
"Light Gray": "Light Gray",
|
||||
"Silver": "Silver",
|
||||
"White": "White",
|
||||
"Dark Red": "Dark Red",
|
||||
"Red": "Red",
|
||||
"Light Red": "Light Red",
|
||||
"Pink": "Pink",
|
||||
"Dark Green": "Dark Green",
|
||||
"Green": "Green",
|
||||
"Lime Green": "Lime Green",
|
||||
"Light Green": "Light Green",
|
||||
"Dark Blue": "Dark Blue",
|
||||
"Blue": "Blue",
|
||||
"Light Blue": "Light Blue",
|
||||
"Sky Blue": "Sky Blue",
|
||||
"Dark Purple": "Dark Purple",
|
||||
"Purple": "Purple",
|
||||
"Light Purple": "Light Purple",
|
||||
"Violet": "Violet",
|
||||
"Orange": "Orange",
|
||||
"Yellow": "Yellow",
|
||||
"Light Yellow": "Light Yellow",
|
||||
"Teal": "Teal",
|
||||
"Cyan": "Cyan",
|
||||
"Light Cyan": "Light Cyan",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Hot Pink",
|
||||
"Brown": "Brown",
|
||||
"Light Brown": "Light Brown",
|
||||
"Colors": "Colors",
|
||||
"Background Color": "Background Color",
|
||||
"Background Alpha": "Background Alpha",
|
||||
"Focus Color": "Focus Color",
|
||||
"Focus Alpha": "Focus Alpha",
|
||||
"Text Color": "Text Color",
|
||||
"Border": "Border",
|
||||
"Dashed Line": "Dashed Line",
|
||||
"Max FPS Text": "Max FPS Text",
|
||||
"Min FPS Text": "Min FPS Text",
|
||||
"Main Line": "Main Line",
|
||||
"Rounded Line": "Rounded Line",
|
||||
"Perfect Line": "Perfect Line",
|
||||
" Color": " Color",
|
||||
" Alpha": " Alpha",
|
||||
"Category Color": "Category Color",
|
||||
"Category Color 1": "Category Color 1",
|
||||
"Category Color 2": "Category Color 2",
|
||||
"Separator Color": "Separator Color",
|
||||
"Elements": "Elements",
|
||||
"Text Alignment": "Text Alignment",
|
||||
"Vertical Position": "Vertical Position",
|
||||
"Horizontal Position": "Horizontal Position",
|
||||
"Left": "Left",
|
||||
"Right": "Right",
|
||||
"Top": "Top",
|
||||
"Center": "Center",
|
||||
"Bottom": "Bottom",
|
||||
"FPS Counter Color":"FPS Counter Color",
|
||||
"FPS Counter Alpha":"FPS Counter Alpha",
|
||||
"Border Color":"Border Color",
|
||||
"Dashed Line Color":"Dashed Line Color",
|
||||
"Dashed Line Alpha":"Dashed Line Alpha",
|
||||
"Max FPS Text Color":"Max FPS Text Color",
|
||||
"Min FPS Text Color":"Min FPS Text Color",
|
||||
"Main Line Color":"Main Line Color",
|
||||
"Rounded Line Color":"Rounded Line Color",
|
||||
"Perfect Line Color":"Perfect Line Color"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/es.json
Normal file
189
Source/Horizon-OC-Monitor/lang/es.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Modos",
|
||||
"Modes Configure": "Modos Configurar",
|
||||
"Full": "Completo",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Micro",
|
||||
"FPS Graph": "Gráfico FPS",
|
||||
"FPS Counter": "Contador FPS",
|
||||
"Game Resolutions": "Resoluciones del juego",
|
||||
"Other": "Otros",
|
||||
"Battery/Charger": "Batería/Cargador",
|
||||
"Miscellaneous": "Varios",
|
||||
"CPU Usage": "Uso de CPU",
|
||||
"GPU Usage": "Uso de GPU",
|
||||
"RAM Usage": "Uso de RAM",
|
||||
"Target Frequency": "Frecuencia objetivo",
|
||||
"Real Frequency": "Frecuencia real",
|
||||
"Core 0 ": "Núcleo 0 ",
|
||||
"Core 1 ": "Núcleo 1 ",
|
||||
"Core 2 ": "Núcleo 2 ",
|
||||
"Core 3 ": "Núcleo 3 ",
|
||||
"Load": "Carga",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Total\nAplicación\nApplet\nSistema\nSistema (inseguro)",
|
||||
"Board": "Placa",
|
||||
"Battery Power Flow": "Flujo de energía de batería",
|
||||
"\nTemperatures": "\nTemperaturas",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Nivel de rotación del ventilador",
|
||||
"Game": "Juego",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Resoluciones ",
|
||||
"Read Speed ": "Velocidad de lectura ",
|
||||
"Press ": "Pulsa ",
|
||||
" to Exit": " para salir",
|
||||
"Depth": "Profundidad",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "El juego no está en ejecución\no es incompatible.",
|
||||
"Battery Stats": "Estadísticas de batería",
|
||||
"Actual Capacity": "Capacidad actual",
|
||||
"Designed Capacity": "Capacidad nominal",
|
||||
"Temperature": "Temperatura",
|
||||
"Raw Charge": "Carga bruta",
|
||||
"Age": "Edad",
|
||||
"Voltage": "Voltaje",
|
||||
"Current Flow": "Flujo de corriente",
|
||||
"Power Flow": "Flujo de potencia",
|
||||
"Remaining Time": "Tiempo restante",
|
||||
"Charger Stats": "Estadísticas del cargador",
|
||||
"Input Current Limit": "Límite de corriente de entrada",
|
||||
"VBUS Current Limit": "Límite de corriente VBUS",
|
||||
"Voltage Limit": "Límite de voltaje",
|
||||
"Current Limit": "Límite de corriente",
|
||||
"Type": "Tipo",
|
||||
"Max Voltage": "Voltaje máx.",
|
||||
"Max Current": "Corriente máx.",
|
||||
"Multimedia Clock Rates": "Frecuencias de reloj multimedia",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Red",
|
||||
"Type: Wi-Fi": "Tipo: Wi-Fi",
|
||||
"Press Y to show password": "Pulsa Y para mostrar contraseña",
|
||||
"Type: Ethernet": "Tipo: Ethernet",
|
||||
"Type: Not connected": "Tipo: No conectado",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Elementos Bajar Subir",
|
||||
"Transparent": "Transparente",
|
||||
"Opaque": "Opaco",
|
||||
"Alpha": "Alfa",
|
||||
"Pretty": "Bonito",
|
||||
"Compact": "Compacto",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "Día+Hora",
|
||||
"Date+Time(s)": "Fecha+Hora(s)",
|
||||
"Date+Time AM/PM": "Fecha+Hora AM/PM",
|
||||
"Date+Time(s) AM/PM": "Fecha+Hora(s) AM/PM",
|
||||
"Date+Time EU": "Fecha+Hora EU",
|
||||
"Date+Time EU AM/PM": "Fecha+Hora EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Fecha+Hora(s) EU AM/PM",
|
||||
"Date+Time ISO": "Fecha+Hora ISO",
|
||||
"Time 24h": "Hora 24h",
|
||||
"Time AM/PM": "Hora AM/PM",
|
||||
"Time(s) 24h": "Hora(s) 24h",
|
||||
"Time(s) AM/PM": "Hora(s) AM/PM",
|
||||
"Date US": "Fecha EE.UU.",
|
||||
"Date EU": "Fecha EU",
|
||||
"Date ISO": "Fecha ISO",
|
||||
"Date Short": "Fecha corta",
|
||||
"DTC Format": "Formato DTC",
|
||||
"Toggles": "Conmutadores",
|
||||
"Info": "Mostrar info",
|
||||
"Disable Screenshots": "Desactivar capturas",
|
||||
"Real Freqs": "Frecuencias reales",
|
||||
"Deltas": "Deltas",
|
||||
"Target Freqs": "Frecuencias objetivo",
|
||||
"FPS": "FPS",
|
||||
"RES": "RES",
|
||||
"Read Speed": "Velocidad de lectura",
|
||||
"Real Frequencies": "Frecuencias reales",
|
||||
"Real Voltages": "Voltajes reales",
|
||||
"Full CPU": "CPU completo",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Resolución completa",
|
||||
"SOC Voltage": "Voltaje SOC",
|
||||
"RAM Load CPU/GPU": "Carga RAM CPU/GPU",
|
||||
"Use DTC Symbol": "Usar símbolo DTC",
|
||||
"Use Dynamic Colors": "Usar colores dinámicos",
|
||||
"Sleep Exit": "Salir del reposo",
|
||||
"Configuration": "Configuración",
|
||||
"Refresh Rate": "Tasa de refresco",
|
||||
"Frame Padding": "Relleno de marco",
|
||||
" Font Size": " Tamaño de fuente",
|
||||
"Font Sizes": "Tamaños de fuente",
|
||||
"Handheld Font Size": "Tamaño fuente portátil",
|
||||
"Docked Font Size": "Tamaño fuente acoplado",
|
||||
"Black": "Negro",
|
||||
"Dark Gray": "Gris oscuro",
|
||||
"Gray": "Gris",
|
||||
"Light Gray": "Gris claro",
|
||||
"Silver": "Plata",
|
||||
"White": "Blanco",
|
||||
"Dark Red": "Rojo oscuro",
|
||||
"Red": "Rojo",
|
||||
"Light Red": "Rojo claro",
|
||||
"Pink": "Rosa",
|
||||
"Dark Green": "Verde oscuro",
|
||||
"Green": "Verde",
|
||||
"Lime Green": "Verde lima",
|
||||
"Light Green": "Verde claro",
|
||||
"Dark Blue": "Azul oscuro",
|
||||
"Blue": "Azul",
|
||||
"Light Blue": "Azul claro",
|
||||
"Sky Blue": "Azul cielo",
|
||||
"Dark Purple": "Púrpura oscuro",
|
||||
"Purple": "Púrpura",
|
||||
"Light Purple": "Púrpura claro",
|
||||
"Violet": "Violeta",
|
||||
"Orange": "Naranja",
|
||||
"Yellow": "Amarillo",
|
||||
"Light Yellow": "Amarillo claro",
|
||||
"Teal": "Verde azulado",
|
||||
"Cyan": "Cian",
|
||||
"Light Cyan": "Cian claro",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Rosa intenso",
|
||||
"Brown": "Marrón",
|
||||
"Light Brown": "Marrón claro",
|
||||
"Colors": "Colores",
|
||||
"Background Color": "Color de fondo",
|
||||
"Background Alpha": "Alfa de fondo",
|
||||
"Focus Color": "Color de foco",
|
||||
"Focus Alpha": "Alfa de foco",
|
||||
"Text Color": "Color de texto",
|
||||
"Border": "Borde",
|
||||
"Dashed Line": "Línea discontinua",
|
||||
"Max FPS Text": "Texto FPS máx.",
|
||||
"Min FPS Text": "Texto FPS mín.",
|
||||
"Main Line": "Línea principal",
|
||||
"Rounded Line": "Línea redondeada",
|
||||
"Perfect Line": "Línea perfecta",
|
||||
" Color": " Color",
|
||||
" Alpha": " Alfa",
|
||||
"Category Color": "Color de categoría",
|
||||
"Category Color 1": "Color categoría 1",
|
||||
"Category Color 2": "Color categoría 2",
|
||||
"Separator Color": "Color separador",
|
||||
"Elements": "Elementos",
|
||||
"Text Alignment": "Alineación de texto",
|
||||
"Vertical Position": "Posición vertical",
|
||||
"Horizontal Position": "Posición horizontal",
|
||||
"Left": "Izquierda",
|
||||
"Right": "Derecha",
|
||||
"Top": "Arriba",
|
||||
"Center": "Centro",
|
||||
"Bottom": "Abajo",
|
||||
"FPS Counter Color": "Color contador FPS",
|
||||
"FPS Counter Alpha": "Alfa contador FPS",
|
||||
"Border Color": "Color de borde",
|
||||
"Dashed Line Color": "Color línea discontinua",
|
||||
"Dashed Line Alpha": "Alfa línea discontinua",
|
||||
"Max FPS Text Color": "Color texto FPS máx.",
|
||||
"Min FPS Text Color": "Color texto FPS mín.",
|
||||
"Main Line Color": "Color línea principal",
|
||||
"Rounded Line Color": "Color línea redondeada",
|
||||
"Perfect Line Color": "Color línea perfecta"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/fr.json
Normal file
189
Source/Horizon-OC-Monitor/lang/fr.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Modes",
|
||||
"Modes Configure": "Modes Configurer",
|
||||
"Full": "Complet",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Micro",
|
||||
"FPS Graph": "Graphique FPS",
|
||||
"FPS Counter": "Compteur FPS",
|
||||
"Game Resolutions": "Résolutions du jeu",
|
||||
"Other": "Autres",
|
||||
"Battery/Charger": "Batterie/Chargeur",
|
||||
"Miscellaneous": "Divers",
|
||||
"CPU Usage": "Utilisation CPU",
|
||||
"GPU Usage": "Utilisation GPU",
|
||||
"RAM Usage": "Utilisation RAM",
|
||||
"Target Frequency": "Fréquence cible",
|
||||
"Real Frequency": "Fréquence réelle",
|
||||
"Core 0 ": "Cœur 0 ",
|
||||
"Core 1 ": "Cœur 1 ",
|
||||
"Core 2 ": "Cœur 2 ",
|
||||
"Core 3 ": "Cœur 3 ",
|
||||
"Load": "Charge",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Total\nApplication\nApplet\nSystème\nSystème non sécurisé",
|
||||
"Board": "Carte",
|
||||
"Battery Power Flow": "Flux de puissance batterie",
|
||||
"\nTemperatures": "\nTempératures",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Niveau de rotation ventilateur",
|
||||
"Game": "Jeu",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Résolutions ",
|
||||
"Read Speed ": "Vitesse de lecture ",
|
||||
"Press ": "Appuyez sur ",
|
||||
" to Exit": " pour quitter",
|
||||
"Depth": "Profondeur",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Le jeu ne fonctionne pas\nou est incompatible.",
|
||||
"Battery Stats": "Statistiques batterie",
|
||||
"Actual Capacity": "Capacité actuelle",
|
||||
"Designed Capacity": "Capacité nominale",
|
||||
"Temperature": "Température",
|
||||
"Raw Charge": "Charge brute",
|
||||
"Age": "Âge",
|
||||
"Voltage": "Tension",
|
||||
"Current Flow": "Flux de courant",
|
||||
"Power Flow": "Flux de puissance",
|
||||
"Remaining Time": "Temps restant",
|
||||
"Charger Stats": "Statistiques chargeur",
|
||||
"Input Current Limit": "Limite courant entrée",
|
||||
"VBUS Current Limit": "Limite courant VBUS",
|
||||
"Voltage Limit": "Limite tension",
|
||||
"Current Limit": "Limite courant",
|
||||
"Type": "Type",
|
||||
"Max Voltage": "Tension max",
|
||||
"Max Current": "Courant max",
|
||||
"Multimedia Clock Rates": "Fréquences horloge multimédia",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Réseau",
|
||||
"Type: Wi-Fi": "Type : Wi-Fi",
|
||||
"Press Y to show password": "Appuyez sur Y pour afficher le mot de passe",
|
||||
"Type: Ethernet": "Type : Ethernet",
|
||||
"Type: Not connected": "Type : Non connecté",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Éléments Descendre Monter",
|
||||
"Transparent": "Transparent",
|
||||
"Opaque": "Opaque",
|
||||
"Alpha": "Alpha",
|
||||
"Pretty": "Joli",
|
||||
"Compact": "Compact",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "Jour+Heure",
|
||||
"Date+Time(s)": "Date+Heure(s)",
|
||||
"Date+Time AM/PM": "Date+Heure AM/PM",
|
||||
"Date+Time(s) AM/PM": "Date+Heure(s) AM/PM",
|
||||
"Date+Time EU": "Date+Heure EU",
|
||||
"Date+Time EU AM/PM": "Date+Heure EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Date+Heure(s) EU AM/PM",
|
||||
"Date+Time ISO": "Date+Heure ISO",
|
||||
"Time 24h": "Heure 24h",
|
||||
"Time AM/PM": "Heure AM/PM",
|
||||
"Time(s) 24h": "Heure(s) 24h",
|
||||
"Time(s) AM/PM": "Heure(s) AM/PM",
|
||||
"Date US": "Date US",
|
||||
"Date EU": "Date EU",
|
||||
"Date ISO": "Date ISO",
|
||||
"Date Short": "Date courte",
|
||||
"DTC Format": "Format DTC",
|
||||
"Toggles": "Basculement",
|
||||
"Info": "Afficher infos",
|
||||
"Disable Screenshots": "Désactiver captures d'écran",
|
||||
"Real Freqs": "Fréquences réelles",
|
||||
"Deltas": "Deltas",
|
||||
"Target Freqs": "Fréquences cibles",
|
||||
"FPS": "FPS",
|
||||
"RES": "RÉS",
|
||||
"Read Speed": "Vitesse de lecture",
|
||||
"Real Frequencies": "Fréquences réelles",
|
||||
"Real Voltages": "Tensions réelles",
|
||||
"Full CPU": "CPU complet",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Résolution complète",
|
||||
"SOC Voltage": "Tension SOC",
|
||||
"RAM Load CPU/GPU": "Charge RAM CPU/GPU",
|
||||
"Use DTC Symbol": "Utiliser symbole DTC",
|
||||
"Use Dynamic Colors": "Utiliser couleurs dynamiques",
|
||||
"Sleep Exit": "Sortie veille",
|
||||
"Configuration": "Configuration",
|
||||
"Refresh Rate": "Taux de rafraîchissement",
|
||||
"Frame Padding": "Marge de cadre",
|
||||
" Font Size": " Taille police",
|
||||
"Font Sizes": "Tailles de police",
|
||||
"Handheld Font Size": "Taille police portable",
|
||||
"Docked Font Size": "Taille police dockée",
|
||||
"Black": "Noir",
|
||||
"Dark Gray": "Gris foncé",
|
||||
"Gray": "Gris",
|
||||
"Light Gray": "Gris clair",
|
||||
"Silver": "Argent",
|
||||
"White": "Blanc",
|
||||
"Dark Red": "Rouge foncé",
|
||||
"Red": "Rouge",
|
||||
"Light Red": "Rouge clair",
|
||||
"Pink": "Rose",
|
||||
"Dark Green": "Vert foncé",
|
||||
"Green": "Vert",
|
||||
"Lime Green": "Vert citron",
|
||||
"Light Green": "Vert clair",
|
||||
"Dark Blue": "Bleu foncé",
|
||||
"Blue": "Bleu",
|
||||
"Light Blue": "Bleu clair",
|
||||
"Sky Blue": "Bleu ciel",
|
||||
"Dark Purple": "Violet foncé",
|
||||
"Purple": "Violet",
|
||||
"Light Purple": "Violet clair",
|
||||
"Violet": "Violet",
|
||||
"Orange": "Orange",
|
||||
"Yellow": "Jaune",
|
||||
"Light Yellow": "Jaune clair",
|
||||
"Teal": "Sarcelle",
|
||||
"Cyan": "Cyan",
|
||||
"Light Cyan": "Cyan clair",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Rose vif",
|
||||
"Brown": "Marron",
|
||||
"Light Brown": "Marron clair",
|
||||
"Colors": "Couleurs",
|
||||
"Background Color": "Couleur d'arrière-plan",
|
||||
"Background Alpha": "Alpha d'arrière-plan",
|
||||
"Focus Color": "Couleur de focus",
|
||||
"Focus Alpha": "Alpha de focus",
|
||||
"Text Color": "Couleur du texte",
|
||||
"Border": "Bordure",
|
||||
"Dashed Line": "Ligne pointillée",
|
||||
"Max FPS Text": "Texte FPS max",
|
||||
"Min FPS Text": "Texte FPS min",
|
||||
"Main Line": "Ligne principale",
|
||||
"Rounded Line": "Ligne arrondie",
|
||||
"Perfect Line": "Ligne parfaite",
|
||||
" Color": " Couleur",
|
||||
" Alpha": " Alpha",
|
||||
"Category Color": "Couleur de catégorie",
|
||||
"Category Color 1": "Couleur catégorie 1",
|
||||
"Category Color 2": "Couleur catégorie 2",
|
||||
"Separator Color": "Couleur de séparateur",
|
||||
"Elements": "Éléments",
|
||||
"Text Alignment": "Alignement du texte",
|
||||
"Vertical Position": "Position verticale",
|
||||
"Horizontal Position": "Position horizontale",
|
||||
"Left": "Gauche",
|
||||
"Right": "Droite",
|
||||
"Top": "Haut",
|
||||
"Center": "Centre",
|
||||
"Bottom": "Bas",
|
||||
"FPS Counter Color": "Couleur compteur FPS",
|
||||
"FPS Counter Alpha": "Alpha compteur FPS",
|
||||
"Border Color": "Couleur de bordure",
|
||||
"Dashed Line Color": "Couleur ligne pointillée",
|
||||
"Dashed Line Alpha": "Alpha ligne pointillée",
|
||||
"Max FPS Text Color": "Couleur texte FPS max",
|
||||
"Min FPS Text Color": "Couleur texte FPS min",
|
||||
"Main Line Color": "Couleur ligne principale",
|
||||
"Rounded Line Color": "Couleur ligne arrondie",
|
||||
"Perfect Line Color": "Couleur ligne parfaite"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/it.json
Normal file
189
Source/Horizon-OC-Monitor/lang/it.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Modalità",
|
||||
"Modes Configure": "Modalità Configura",
|
||||
"Full": "Completo",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Micro",
|
||||
"FPS Graph": "Grafico FPS",
|
||||
"FPS Counter": "Contatore FPS",
|
||||
"Game Resolutions": "Risoluzioni di gioco",
|
||||
"Other": "Altro",
|
||||
"Battery/Charger": "Batteria/Caricatore",
|
||||
"Miscellaneous": "Varie",
|
||||
"CPU Usage": "Utilizzo CPU",
|
||||
"GPU Usage": "Utilizzo GPU",
|
||||
"RAM Usage": "Utilizzo RAM",
|
||||
"Target Frequency": "Frequenza target",
|
||||
"Real Frequency": "Frequenza reale",
|
||||
"Core 0 ": "Core 0 ",
|
||||
"Core 1 ": "Core 1 ",
|
||||
"Core 2 ": "Core 2 ",
|
||||
"Core 3 ": "Core 3 ",
|
||||
"Load": "Carico",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Totale\nApplicazione\nApplet\nSistema\nSistema non sicuro",
|
||||
"Board": "Scheda",
|
||||
"Battery Power Flow": "Flusso potenza batteria",
|
||||
"\nTemperatures": "\nTemperature",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Livello rotazione ventola",
|
||||
"Game": "Gioco",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Risoluzioni ",
|
||||
"Read Speed ": "Velocità di lettura ",
|
||||
"Press ": "Premi ",
|
||||
" to Exit": " per uscire",
|
||||
"Depth": "Profondità",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Il gioco non è in esecuzione\no è incompatibile.",
|
||||
"Battery Stats": "Statistiche batteria",
|
||||
"Actual Capacity": "Capacità attuale",
|
||||
"Designed Capacity": "Capacità nominale",
|
||||
"Temperature": "Temperatura",
|
||||
"Raw Charge": "Carica grezza",
|
||||
"Age": "Età",
|
||||
"Voltage": "Voltaggio",
|
||||
"Current Flow": "Flusso corrente",
|
||||
"Power Flow": "Flusso potenza",
|
||||
"Remaining Time": "Tempo rimanente",
|
||||
"Charger Stats": "Statistiche caricatore",
|
||||
"Input Current Limit": "Limite corrente ingresso",
|
||||
"VBUS Current Limit": "Limite corrente VBUS",
|
||||
"Voltage Limit": "Limite tensione",
|
||||
"Current Limit": "Limite corrente",
|
||||
"Type": "Tipo",
|
||||
"Max Voltage": "Tensione max",
|
||||
"Max Current": "Corrente max",
|
||||
"Multimedia Clock Rates": "Frequenze clock multimediali",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Rete",
|
||||
"Type: Wi-Fi": "Tipo: Wi-Fi",
|
||||
"Press Y to show password": "Premi Y per mostrare la password",
|
||||
"Type: Ethernet": "Tipo: Ethernet",
|
||||
"Type: Not connected": "Tipo: Non connesso",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Elementi Sposta giù Sposta su",
|
||||
"Transparent": "Trasparente",
|
||||
"Opaque": "Opaco",
|
||||
"Alpha": "Alfa",
|
||||
"Pretty": "Carino",
|
||||
"Compact": "Compatto",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "Giorno+Ora",
|
||||
"Date+Time(s)": "Data+Ora(s)",
|
||||
"Date+Time AM/PM": "Data+Ora AM/PM",
|
||||
"Date+Time(s) AM/PM": "Data+Ora(s) AM/PM",
|
||||
"Date+Time EU": "Data+Ora EU",
|
||||
"Date+Time EU AM/PM": "Data+Ora EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Data+Ora(s) EU AM/PM",
|
||||
"Date+Time ISO": "Data+Ora ISO",
|
||||
"Time 24h": "Ora 24h",
|
||||
"Time AM/PM": "Ora AM/PM",
|
||||
"Time(s) 24h": "Ora(s) 24h",
|
||||
"Time(s) AM/PM": "Ora(s) AM/PM",
|
||||
"Date US": "Data US",
|
||||
"Date EU": "Data EU",
|
||||
"Date ISO": "Data ISO",
|
||||
"Date Short": "Data breve",
|
||||
"DTC Format": "Formato DTC",
|
||||
"Toggles": "Interruttori",
|
||||
"Info": "Mostra info",
|
||||
"Disable Screenshots": "Disabilita screenshot",
|
||||
"Real Freqs": "Frequenze reali",
|
||||
"Deltas": "Delta",
|
||||
"Target Freqs": "Frequenze target",
|
||||
"FPS": "FPS",
|
||||
"RES": "RIS",
|
||||
"Read Speed": "Velocità di lettura",
|
||||
"Real Frequencies": "Frequenze reali",
|
||||
"Real Voltages": "Voltaggi reali",
|
||||
"Full CPU": "CPU completo",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Risoluzione completa",
|
||||
"SOC Voltage": "Voltaggio SOC",
|
||||
"RAM Load CPU/GPU": "Carico RAM CPU/GPU",
|
||||
"Use DTC Symbol": "Usa simbolo DTC",
|
||||
"Use Dynamic Colors": "Usa colori dinamici",
|
||||
"Sleep Exit": "Uscita standby",
|
||||
"Configuration": "Configurazione",
|
||||
"Refresh Rate": "Frequenza di aggiornamento",
|
||||
"Frame Padding": "Spaziatura cornice",
|
||||
" Font Size": " Dimensione font",
|
||||
"Font Sizes": "Dimensioni font",
|
||||
"Handheld Font Size": "Dimensione font portatile",
|
||||
"Docked Font Size": "Dimensione font docked",
|
||||
"Black": "Nero",
|
||||
"Dark Gray": "Grigio scuro",
|
||||
"Gray": "Grigio",
|
||||
"Light Gray": "Grigio chiaro",
|
||||
"Silver": "Argento",
|
||||
"White": "Bianco",
|
||||
"Dark Red": "Rosso scuro",
|
||||
"Red": "Rosso",
|
||||
"Light Red": "Rosso chiaro",
|
||||
"Pink": "Rosa",
|
||||
"Dark Green": "Verde scuro",
|
||||
"Green": "Verde",
|
||||
"Lime Green": "Verde lime",
|
||||
"Light Green": "Verde chiaro",
|
||||
"Dark Blue": "Blu scuro",
|
||||
"Blue": "Blu",
|
||||
"Light Blue": "Azzurro",
|
||||
"Sky Blue": "Azzurro cielo",
|
||||
"Dark Purple": "Viola scuro",
|
||||
"Purple": "Viola",
|
||||
"Light Purple": "Viola chiaro",
|
||||
"Violet": "Viola",
|
||||
"Orange": "Arancione",
|
||||
"Yellow": "Giallo",
|
||||
"Light Yellow": "Giallo chiaro",
|
||||
"Teal": "Verde acqua",
|
||||
"Cyan": "Ciano",
|
||||
"Light Cyan": "Ciano chiaro",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Rosa shocking",
|
||||
"Brown": "Marrone",
|
||||
"Light Brown": "Marrone chiaro",
|
||||
"Colors": "Colori",
|
||||
"Background Color": "Colore sfondo",
|
||||
"Background Alpha": "Alfa sfondo",
|
||||
"Focus Color": "Colore focus",
|
||||
"Focus Alpha": "Alfa focus",
|
||||
"Text Color": "Colore testo",
|
||||
"Border": "Bordo",
|
||||
"Dashed Line": "Linea tratteggiata",
|
||||
"Max FPS Text": "Testo FPS max",
|
||||
"Min FPS Text": "Testo FPS min",
|
||||
"Main Line": "Linea principale",
|
||||
"Rounded Line": "Linea arrotondata",
|
||||
"Perfect Line": "Linea perfetta",
|
||||
" Color": " Colore",
|
||||
" Alpha": " Alfa",
|
||||
"Category Color": "Colore categoria",
|
||||
"Category Color 1": "Colore categoria 1",
|
||||
"Category Color 2": "Colore categoria 2",
|
||||
"Separator Color": "Colore separatore",
|
||||
"Elements": "Elementi",
|
||||
"Text Alignment": "Allineamento testo",
|
||||
"Vertical Position": "Posizione verticale",
|
||||
"Horizontal Position": "Posizione orizzontale",
|
||||
"Left": "Sinistra",
|
||||
"Right": "Destra",
|
||||
"Top": "Sopra",
|
||||
"Center": "Centro",
|
||||
"Bottom": "Sotto",
|
||||
"FPS Counter Color": "Colore contatore FPS",
|
||||
"FPS Counter Alpha": "Alfa contatore FPS",
|
||||
"Border Color": "Colore bordo",
|
||||
"Dashed Line Color": "Colore linea tratteggiata",
|
||||
"Dashed Line Alpha": "Alfa linea tratteggiata",
|
||||
"Max FPS Text Color": "Colore testo FPS max",
|
||||
"Min FPS Text Color": "Colore testo FPS min",
|
||||
"Main Line Color": "Colore linea principale",
|
||||
"Rounded Line Color": "Colore linea arrotondata",
|
||||
"Perfect Line Color": "Colore linea perfetta"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/ja.json
Normal file
189
Source/Horizon-OC-Monitor/lang/ja.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "モード",
|
||||
"Modes Configure": "モード 設定",
|
||||
"Full": "フル",
|
||||
"Mini": "ミニ",
|
||||
"Micro": "マイクロ",
|
||||
"FPS Graph": "FPSグラフ",
|
||||
"FPS Counter": "FPSカウンター",
|
||||
"Game Resolutions": "ゲーム解像度",
|
||||
"Other": "その他",
|
||||
"Battery/Charger": "バッテリー/充電器",
|
||||
"Miscellaneous": "その他",
|
||||
"CPU Usage": "CPU使用率",
|
||||
"GPU Usage": "GPU使用率",
|
||||
"RAM Usage": "RAM使用率",
|
||||
"Target Frequency": "目標周波数",
|
||||
"Real Frequency": "実際の周波数",
|
||||
"Core 0 ": "コア 0 ",
|
||||
"Core 1 ": "コア 1 ",
|
||||
"Core 2 ": "コア 2 ",
|
||||
"Core 3 ": "コア 3 ",
|
||||
"Load": "負荷",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "合計\nアプリケーション\nアプレット\nシステム\nシステム(非安全)",
|
||||
"Board": "ボード",
|
||||
"Battery Power Flow": "バッテリー電力フロー",
|
||||
"\nTemperatures": "\n温度",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "ファン回転レベル",
|
||||
"Game": "ゲーム",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "解像度 ",
|
||||
"Read Speed ": "読み込み速度 ",
|
||||
"Press ": "押す ",
|
||||
" to Exit": " で終了",
|
||||
"Depth": "深度",
|
||||
"Viewport": "ビューポート",
|
||||
"Game is not running\nor it's incompatible.": "ゲームが実行されていない\nまたは非対応です。",
|
||||
"Battery Stats": "バッテリー統計",
|
||||
"Actual Capacity": "実際の容量",
|
||||
"Designed Capacity": "設計容量",
|
||||
"Temperature": "温度",
|
||||
"Raw Charge": "生充電量",
|
||||
"Age": "経年",
|
||||
"Voltage": "電圧",
|
||||
"Current Flow": "電流フロー",
|
||||
"Power Flow": "電力フロー",
|
||||
"Remaining Time": "残り時間",
|
||||
"Charger Stats": "充電器統計",
|
||||
"Input Current Limit": "入力電流制限",
|
||||
"VBUS Current Limit": "VBUS電流制限",
|
||||
"Voltage Limit": "電圧制限",
|
||||
"Current Limit": "電流制限",
|
||||
"Type": "タイプ",
|
||||
"Max Voltage": "最大電圧",
|
||||
"Max Current": "最大電流",
|
||||
"Multimedia Clock Rates": "マルチメディアクロックレート",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "ネットワーク",
|
||||
"Type: Wi-Fi": "タイプ: Wi-Fi",
|
||||
"Press Y to show password": "Yを押してパスワードを表示",
|
||||
"Type: Ethernet": "タイプ: Ethernet",
|
||||
"Type: Not connected": "タイプ: 未接続",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "要素 下へ 上へ",
|
||||
"Transparent": "透明",
|
||||
"Opaque": "不透明",
|
||||
"Alpha": "アルファ",
|
||||
"Pretty": "プリティ",
|
||||
"Compact": "コンパクト",
|
||||
"FileSafe": "ファイルセーフ",
|
||||
"Day+Time": "日+時間",
|
||||
"Date+Time(s)": "日付+時間(s)",
|
||||
"Date+Time AM/PM": "日付+時間 AM/PM",
|
||||
"Date+Time(s) AM/PM": "日付+時間(s) AM/PM",
|
||||
"Date+Time EU": "日付+時間 EU",
|
||||
"Date+Time EU AM/PM": "日付+時間 EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "日付+時間(s) EU AM/PM",
|
||||
"Date+Time ISO": "日付+時間 ISO",
|
||||
"Time 24h": "時間 24h",
|
||||
"Time AM/PM": "時間 AM/PM",
|
||||
"Time(s) 24h": "時間(s) 24h",
|
||||
"Time(s) AM/PM": "時間(s) AM/PM",
|
||||
"Date US": "日付 US",
|
||||
"Date EU": "日付 EU",
|
||||
"Date ISO": "日付 ISO",
|
||||
"Date Short": "短い日付",
|
||||
"DTC Format": "DTC形式",
|
||||
"Toggles": "トグル",
|
||||
"Info": "情報表示",
|
||||
"Disable Screenshots": "スクリーンショット無効",
|
||||
"Real Freqs": "実際の周波数",
|
||||
"Deltas": "デルタ",
|
||||
"Target Freqs": "目標周波数",
|
||||
"FPS": "FPS",
|
||||
"RES": "解像度",
|
||||
"Read Speed": "読み込み速度",
|
||||
"Real Frequencies": "実際の周波数",
|
||||
"Real Voltages": "実際の電圧",
|
||||
"Full CPU": "フルCPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "フル解像度",
|
||||
"SOC Voltage": "SOC電圧",
|
||||
"RAM Load CPU/GPU": "RAM負荷 CPU/GPU",
|
||||
"Use DTC Symbol": "DTCシンボル使用",
|
||||
"Use Dynamic Colors": "ダイナミックカラー使用",
|
||||
"Sleep Exit": "スリープ解除",
|
||||
"Configuration": "設定",
|
||||
"Refresh Rate": "リフレッシュレート",
|
||||
"Frame Padding": "フレームパディング",
|
||||
" Font Size": " フォントサイズ",
|
||||
"Font Sizes": "フォントサイズ",
|
||||
"Handheld Font Size": "携帯モードフォントサイズ",
|
||||
"Docked Font Size": "ドックモードフォントサイズ",
|
||||
"Black": "黒",
|
||||
"Dark Gray": "ダークグレー",
|
||||
"Gray": "グレー",
|
||||
"Light Gray": "ライトグレー",
|
||||
"Silver": "シルバー",
|
||||
"White": "白",
|
||||
"Dark Red": "ダークレッド",
|
||||
"Red": "赤",
|
||||
"Light Red": "ライト レッド",
|
||||
"Pink": "ピンク",
|
||||
"Dark Green": "ダークグリーン",
|
||||
"Green": "緑",
|
||||
"Lime Green": "ライムグリーン",
|
||||
"Light Green": "ライトグリーン",
|
||||
"Dark Blue": "ダークブルー",
|
||||
"Blue": "青",
|
||||
"Light Blue": "ライトブルー",
|
||||
"Sky Blue": "スカイブルー",
|
||||
"Dark Purple": "ダークパープル",
|
||||
"Purple": "パープル",
|
||||
"Light Purple": "ライトパープル",
|
||||
"Violet": "バイオレット",
|
||||
"Orange": "オレンジ",
|
||||
"Yellow": "黄",
|
||||
"Light Yellow": "ライトイエロー",
|
||||
"Teal": "ティール",
|
||||
"Cyan": "シアン",
|
||||
"Light Cyan": "ライトシアン",
|
||||
"Magenta": "マゼンタ",
|
||||
"Hot Pink": "ホットピンク",
|
||||
"Brown": "ブラウン",
|
||||
"Light Brown": "ライトブラウン",
|
||||
"Colors": "色",
|
||||
"Background Color": "背景色",
|
||||
"Background Alpha": "背景アルファ",
|
||||
"Focus Color": "フォーカス色",
|
||||
"Focus Alpha": "フォーカスアルファ",
|
||||
"Text Color": "文字色",
|
||||
"Border": "枠線",
|
||||
"Dashed Line": "破線",
|
||||
"Max FPS Text": "最大FPSテキスト",
|
||||
"Min FPS Text": "最小FPSテキスト",
|
||||
"Main Line": "主線",
|
||||
"Rounded Line": "丸角線",
|
||||
"Perfect Line": "完璧線",
|
||||
" Color": " 色",
|
||||
" Alpha": " アルファ",
|
||||
"Category Color": "カテゴリ色",
|
||||
"Category Color 1": "カテゴリ色 1",
|
||||
"Category Color 2": "カテゴリ色 2",
|
||||
"Separator Color": "セパレータ色",
|
||||
"Elements": "要素",
|
||||
"Text Alignment": "テキスト配置",
|
||||
"Vertical Position": "垂直位置",
|
||||
"Horizontal Position": "水平位置",
|
||||
"Left": "左",
|
||||
"Right": "右",
|
||||
"Top": "上",
|
||||
"Center": "中央",
|
||||
"Bottom": "下",
|
||||
"FPS Counter Color": "FPSカウンター色",
|
||||
"FPS Counter Alpha": "FPSカウンターアルファ",
|
||||
"Border Color": "枠線色",
|
||||
"Dashed Line Color": "破線色",
|
||||
"Dashed Line Alpha": "破線アルファ",
|
||||
"Max FPS Text Color": "最大FPSテキスト色",
|
||||
"Min FPS Text Color": "最小FPSテキスト色",
|
||||
"Main Line Color": "主線色",
|
||||
"Rounded Line Color": "丸角線色",
|
||||
"Perfect Line Color": "完璧線色"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/ko.json
Normal file
189
Source/Horizon-OC-Monitor/lang/ko.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "모드",
|
||||
"Modes Configure": "모드 설정",
|
||||
"Full": "전체",
|
||||
"Mini": "미니",
|
||||
"Micro": "마이크로",
|
||||
"FPS Graph": "FPS 그래프",
|
||||
"FPS Counter": "FPS 카운터",
|
||||
"Game Resolutions": "게임 해상도",
|
||||
"Other": "기타",
|
||||
"Battery/Charger": "배터리/충전기",
|
||||
"Miscellaneous": "기타",
|
||||
"CPU Usage": "CPU 사용량",
|
||||
"GPU Usage": "GPU 사용량",
|
||||
"RAM Usage": "RAM 사용량",
|
||||
"Target Frequency": "목표 주파수",
|
||||
"Real Frequency": "실제 주파수",
|
||||
"Core 0 ": "코어 0 ",
|
||||
"Core 1 ": "코어 1 ",
|
||||
"Core 2 ": "코어 2 ",
|
||||
"Core 3 ": "코어 3 ",
|
||||
"Load": "부하",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "합계\n앱\n애플릿\n시스템\n시스템(비안전)",
|
||||
"Board": "보드",
|
||||
"Battery Power Flow": "배터리 전력 흐름",
|
||||
"\nTemperatures": "\n온도",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "팬 회전 레벨",
|
||||
"Game": "게임",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "해상도 ",
|
||||
"Read Speed ": "읽기 속도 ",
|
||||
"Press ": "누르기 ",
|
||||
" to Exit": " 종료",
|
||||
"Depth": "깊이",
|
||||
"Viewport": "뷰포트",
|
||||
"Game is not running\nor it's incompatible.": "게임이 실행 중이 아니거나\n호환되지 않습니다.",
|
||||
"Battery Stats": "배터리 통계",
|
||||
"Actual Capacity": "실제 용량",
|
||||
"Designed Capacity": "설계 용량",
|
||||
"Temperature": "온도",
|
||||
"Raw Charge": "원시 충전량",
|
||||
"Age": "수명",
|
||||
"Voltage": "전압",
|
||||
"Current Flow": "전류 흐름",
|
||||
"Power Flow": "전력 흐름",
|
||||
"Remaining Time": "남은 시간",
|
||||
"Charger Stats": "충전기 통계",
|
||||
"Input Current Limit": "입력 전류 제한",
|
||||
"VBUS Current Limit": "VBUS 전류 제한",
|
||||
"Voltage Limit": "전압 제한",
|
||||
"Current Limit": "전류 제한",
|
||||
"Type": "유형",
|
||||
"Max Voltage": "최대 전압",
|
||||
"Max Current": "최대 전류",
|
||||
"Multimedia Clock Rates": "멀티미디어 클럭 속도",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "네트워크",
|
||||
"Type: Wi-Fi": "유형: Wi-Fi",
|
||||
"Press Y to show password": "Y를 눌러 비밀번호 표시",
|
||||
"Type: Ethernet": "유형: 이더넷",
|
||||
"Type: Not connected": "유형: 연결 안 됨",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "요소 아래로 위로",
|
||||
"Transparent": "투명",
|
||||
"Opaque": "불투명",
|
||||
"Alpha": "알파",
|
||||
"Pretty": "예쁨",
|
||||
"Compact": "컴팩트",
|
||||
"FileSafe": "파일세이프",
|
||||
"Day+Time": "일+시간",
|
||||
"Date+Time(s)": "날짜+시간(s)",
|
||||
"Date+Time AM/PM": "날짜+시간 AM/PM",
|
||||
"Date+Time(s) AM/PM": "날짜+시간(s) AM/PM",
|
||||
"Date+Time EU": "날짜+시간 EU",
|
||||
"Date+Time EU AM/PM": "날짜+시간 EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "날짜+시간(s) EU AM/PM",
|
||||
"Date+Time ISO": "날짜+시간 ISO",
|
||||
"Time 24h": "시간 24시",
|
||||
"Time AM/PM": "시간 AM/PM",
|
||||
"Time(s) 24h": "시간(s) 24시",
|
||||
"Time(s) AM/PM": "시간(s) AM/PM",
|
||||
"Date US": "날짜 US",
|
||||
"Date EU": "날짜 EU",
|
||||
"Date ISO": "날짜 ISO",
|
||||
"Date Short": "짧은 날짜",
|
||||
"DTC Format": "DTC 형식",
|
||||
"Toggles": "토글",
|
||||
"Info": "정보 표시",
|
||||
"Disable Screenshots": "스크린샷 비활성화",
|
||||
"Real Freqs": "실제 주파수",
|
||||
"Deltas": "델타",
|
||||
"Target Freqs": "목표 주파수",
|
||||
"FPS": "FPS",
|
||||
"RES": "해상도",
|
||||
"Read Speed": "읽기 속도",
|
||||
"Real Frequencies": "실제 주파수",
|
||||
"Real Voltages": "실제 전압",
|
||||
"Full CPU": "전체 CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "전체 해상도",
|
||||
"SOC Voltage": "SOC 전압",
|
||||
"RAM Load CPU/GPU": "RAM 부하 CPU/GPU",
|
||||
"Use DTC Symbol": "DTC 심볼 사용",
|
||||
"Use Dynamic Colors": "동적 색상 사용",
|
||||
"Sleep Exit": "절전 종료",
|
||||
"Configuration": "설정",
|
||||
"Refresh Rate": "리프레시 레이트",
|
||||
"Frame Padding": "프레임 패딩",
|
||||
" Font Size": " 글꼴 크기",
|
||||
"Font Sizes": "글꼴 크기",
|
||||
"Handheld Font Size": "핸드헬드 글꼴 크기",
|
||||
"Docked Font Size": "도킹 글꼴 크기",
|
||||
"Black": "검정",
|
||||
"Dark Gray": "짙은 회색",
|
||||
"Gray": "회색",
|
||||
"Light Gray": "밝은 회색",
|
||||
"Silver": "은색",
|
||||
"White": "흰색",
|
||||
"Dark Red": "짙은 빨강",
|
||||
"Red": "빨강",
|
||||
"Light Red": "밝은 빨강",
|
||||
"Pink": "분홍",
|
||||
"Dark Green": "짙은 초록",
|
||||
"Green": "초록",
|
||||
"Lime Green": "라임 그린",
|
||||
"Light Green": "밝은 초록",
|
||||
"Dark Blue": "짙은 파랑",
|
||||
"Blue": "파랑",
|
||||
"Light Blue": "밝은 파랑",
|
||||
"Sky Blue": "하늘색",
|
||||
"Dark Purple": "짙은 보라",
|
||||
"Purple": "보라",
|
||||
"Light Purple": "밝은 보라",
|
||||
"Violet": "바이올렛",
|
||||
"Orange": "주황",
|
||||
"Yellow": "노랑",
|
||||
"Light Yellow": "밝은 노랑",
|
||||
"Teal": "청록",
|
||||
"Cyan": "시안",
|
||||
"Light Cyan": "밝은 시안",
|
||||
"Magenta": "마젠타",
|
||||
"Hot Pink": "핫핑크",
|
||||
"Brown": "갈색",
|
||||
"Light Brown": "밝은 갈색",
|
||||
"Colors": "색상",
|
||||
"Background Color": "배경색",
|
||||
"Background Alpha": "배경 투명도",
|
||||
"Focus Color": "포커스 색상",
|
||||
"Focus Alpha": "포커스 투명도",
|
||||
"Text Color": "텍스트 색상",
|
||||
"Border": "테두리",
|
||||
"Dashed Line": "점선",
|
||||
"Max FPS Text": "최대 FPS 텍스트",
|
||||
"Min FPS Text": "최소 FPS 텍스트",
|
||||
"Main Line": "주선",
|
||||
"Rounded Line": "둥근 선",
|
||||
"Perfect Line": "완벽 선",
|
||||
" Color": " 색상",
|
||||
" Alpha": " 투명도",
|
||||
"Category Color": "카테고리 색상",
|
||||
"Category Color 1": "카테고리 색상 1",
|
||||
"Category Color 2": "카테고리 색상 2",
|
||||
"Separator Color": "구분선 색상",
|
||||
"Elements": "요소",
|
||||
"Text Alignment": "텍스트 정렬",
|
||||
"Vertical Position": "세로 위치",
|
||||
"Horizontal Position": "가로 위치",
|
||||
"Left": "왼쪽",
|
||||
"Right": "오른쪽",
|
||||
"Top": "위",
|
||||
"Center": "가운데",
|
||||
"Bottom": "아래",
|
||||
"FPS Counter Color": "FPS 카운터 색상",
|
||||
"FPS Counter Alpha": "FPS 카운터 투명도",
|
||||
"Border Color": "테두리 색상",
|
||||
"Dashed Line Color": "점선 색상",
|
||||
"Dashed Line Alpha": "점선 투명도",
|
||||
"Max FPS Text Color": "최대 FPS 텍스트 색상",
|
||||
"Min FPS Text Color": "최소 FPS 텍스트 색상",
|
||||
"Main Line Color": "주선 색상",
|
||||
"Rounded Line Color": "둥근 선 색상",
|
||||
"Perfect Line Color": "완벽 선 색상"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/nl.json
Normal file
189
Source/Horizon-OC-Monitor/lang/nl.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Modi",
|
||||
"Modes Configure": "Modi Configureren",
|
||||
"Full": "Volledig",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Micro",
|
||||
"FPS Graph": "FPS-grafiek",
|
||||
"FPS Counter": "FPS-teller",
|
||||
"Game Resolutions": "Spelresoluties",
|
||||
"Other": "Overig",
|
||||
"Battery/Charger": "Batterij/Oplader",
|
||||
"Miscellaneous": "Diversen",
|
||||
"CPU Usage": "CPU-gebruik",
|
||||
"GPU Usage": "GPU-gebruik",
|
||||
"RAM Usage": "RAM-gebruik",
|
||||
"Target Frequency": "Doelfrequentie",
|
||||
"Real Frequency": "Werkelijke frequentie",
|
||||
"Core 0 ": "Kern 0 ",
|
||||
"Core 1 ": "Kern 1 ",
|
||||
"Core 2 ": "Kern 2 ",
|
||||
"Core 3 ": "Kern 3 ",
|
||||
"Load": "Belasting",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Totaal\nApplicatie\nApplet\nSysteem\nSysteem onveilig",
|
||||
"Board": "Bord",
|
||||
"Battery Power Flow": "Batterijstroom",
|
||||
"\nTemperatures": "\nTemperaturen",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Ventilatorrotatieniveau",
|
||||
"Game": "Spel",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Resoluties ",
|
||||
"Read Speed ": "Leessnelheid ",
|
||||
"Press ": "Druk op ",
|
||||
" to Exit": " om af te sluiten",
|
||||
"Depth": "Diepte",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Spel draait niet\nof is incompatibel.",
|
||||
"Battery Stats": "Batterijstatistieken",
|
||||
"Actual Capacity": "Werkelijke capaciteit",
|
||||
"Designed Capacity": "Ontworpen capaciteit",
|
||||
"Temperature": "Temperatuur",
|
||||
"Raw Charge": "Ruwe lading",
|
||||
"Age": "Leeftijd",
|
||||
"Voltage": "Spanning",
|
||||
"Current Flow": "Stroomstroom",
|
||||
"Power Flow": "Stroomverbruik",
|
||||
"Remaining Time": "Resterende tijd",
|
||||
"Charger Stats": "Opladerstatistieken",
|
||||
"Input Current Limit": "Ingangsstroomlimiet",
|
||||
"VBUS Current Limit": "VBUS-stroomlimiet",
|
||||
"Voltage Limit": "Spanningslimiet",
|
||||
"Current Limit": "Stroomlimiet",
|
||||
"Type": "Type",
|
||||
"Max Voltage": "Max spanning",
|
||||
"Max Current": "Max stroom",
|
||||
"Multimedia Clock Rates": "Multimedia kloksnelheden",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Netwerk",
|
||||
"Type: Wi-Fi": "Type: Wi-Fi",
|
||||
"Press Y to show password": "Druk op Y om wachtwoord te tonen",
|
||||
"Type: Ethernet": "Type: Ethernet",
|
||||
"Type: Not connected": "Type: Niet verbonden",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Elementen Omlaag verplaatsen Omhoog verplaatsen",
|
||||
"Transparent": "Transparant",
|
||||
"Opaque": "Ondoorzichtig",
|
||||
"Alpha": "Alpha",
|
||||
"Pretty": "Mooi",
|
||||
"Compact": "Compact",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "Dag+Tijd",
|
||||
"Date+Time(s)": "Datum+Tijd(s)",
|
||||
"Date+Time AM/PM": "Datum+Tijd AM/PM",
|
||||
"Date+Time(s) AM/PM": "Datum+Tijd(s) AM/PM",
|
||||
"Date+Time EU": "Datum+Tijd EU",
|
||||
"Date+Time EU AM/PM": "Datum+Tijd EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Datum+Tijd(s) EU AM/PM",
|
||||
"Date+Time ISO": "Datum+Tijd ISO",
|
||||
"Time 24h": "Tijd 24u",
|
||||
"Time AM/PM": "Tijd AM/PM",
|
||||
"Time(s) 24h": "Tijd(s) 24u",
|
||||
"Time(s) AM/PM": "Tijd(s) AM/PM",
|
||||
"Date US": "Datum VS",
|
||||
"Date EU": "Datum EU",
|
||||
"Date ISO": "Datum ISO",
|
||||
"Date Short": "Datum kort",
|
||||
"DTC Format": "DTC-formaat",
|
||||
"Toggles": "Schakelaars",
|
||||
"Info": "Info tonen",
|
||||
"Disable Screenshots": "Schermafbeeldingen uitschakelen",
|
||||
"Real Freqs": "Werkelijke frequenties",
|
||||
"Deltas": "Delta's",
|
||||
"Target Freqs": "Doelfrequenties",
|
||||
"FPS": "FPS",
|
||||
"RES": "RES",
|
||||
"Read Speed": "Leessnelheid",
|
||||
"Real Frequencies": "Werkelijke frequenties",
|
||||
"Real Voltages": "Werkelijke spanningen",
|
||||
"Full CPU": "Volledige CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Volledige resolutie",
|
||||
"SOC Voltage": "SOC-spanning",
|
||||
"RAM Load CPU/GPU": "RAM-belasting CPU/GPU",
|
||||
"Use DTC Symbol": "DTC-symbool gebruiken",
|
||||
"Use Dynamic Colors": "Dynamische kleuren gebruiken",
|
||||
"Sleep Exit": "Slaap afsluiten",
|
||||
"Configuration": "Configuratie",
|
||||
"Refresh Rate": "Vernieuwingsfrequentie",
|
||||
"Frame Padding": "Frame opvulling",
|
||||
" Font Size": " Lettergrootte",
|
||||
"Font Sizes": "Lettergroottes",
|
||||
"Handheld Font Size": "Handheld lettergrootte",
|
||||
"Docked Font Size": "Docked lettergrootte",
|
||||
"Black": "Zwart",
|
||||
"Dark Gray": "Donkergrijs",
|
||||
"Gray": "Grijs",
|
||||
"Light Gray": "Lichtgrijs",
|
||||
"Silver": "Zilver",
|
||||
"White": "Wit",
|
||||
"Dark Red": "Donkerrood",
|
||||
"Red": "Rood",
|
||||
"Light Red": "Lichtrood",
|
||||
"Pink": "Roze",
|
||||
"Dark Green": "Donkergroen",
|
||||
"Green": "Groen",
|
||||
"Lime Green": "Limoengroen",
|
||||
"Light Green": "Lichtgroen",
|
||||
"Dark Blue": "Donkerblauw",
|
||||
"Blue": "Blauw",
|
||||
"Light Blue": "Lichtblauw",
|
||||
"Sky Blue": "Hemelsblauw",
|
||||
"Dark Purple": "Donkerpaars",
|
||||
"Purple": "Paars",
|
||||
"Light Purple": "Lichtpaars",
|
||||
"Violet": "Violet",
|
||||
"Orange": "Oranje",
|
||||
"Yellow": "Geel",
|
||||
"Light Yellow": "Lichtgeel",
|
||||
"Teal": "Teal",
|
||||
"Cyan": "Cyaan",
|
||||
"Light Cyan": "Lichtcyaan",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Felroze",
|
||||
"Brown": "Bruin",
|
||||
"Light Brown": "Lichtbruin",
|
||||
"Colors": "Kleuren",
|
||||
"Background Color": "Achtergrondkleur",
|
||||
"Background Alpha": "Achtergrond alpha",
|
||||
"Focus Color": "Focuskleur",
|
||||
"Focus Alpha": "Focus alpha",
|
||||
"Text Color": "Tekstkleur",
|
||||
"Border": "Rand",
|
||||
"Dashed Line": "Gestippelde lijn",
|
||||
"Max FPS Text": "Max FPS tekst",
|
||||
"Min FPS Text": "Min FPS tekst",
|
||||
"Main Line": "Hoofdlijn",
|
||||
"Rounded Line": "Afgeronde lijn",
|
||||
"Perfect Line": "Perfecte lijn",
|
||||
" Color": " Kleur",
|
||||
" Alpha": " Alpha",
|
||||
"Category Color": "Categoriekleur",
|
||||
"Category Color 1": "Categoriekleur 1",
|
||||
"Category Color 2": "Categoriekleur 2",
|
||||
"Separator Color": "Scheidingskleur",
|
||||
"Elements": "Elementen",
|
||||
"Text Alignment": "Tekstuitlijning",
|
||||
"Vertical Position": "Verticale positie",
|
||||
"Horizontal Position": "Horizontale positie",
|
||||
"Left": "Links",
|
||||
"Right": "Rechts",
|
||||
"Top": "Boven",
|
||||
"Center": "Midden",
|
||||
"Bottom": "Onder",
|
||||
"FPS Counter Color":"FPS-tellerkleur",
|
||||
"FPS Counter Alpha":"FPS-teller alpha",
|
||||
"Border Color":"Randkleur",
|
||||
"Dashed Line Color":"Gestippelde lijnkleur",
|
||||
"Dashed Line Alpha":"Gestippelde lijn alpha",
|
||||
"Max FPS Text Color":"Max FPS tekstkleur",
|
||||
"Min FPS Text Color":"Min FPS tekstkleur",
|
||||
"Main Line Color":"Hoofdlijnkleur",
|
||||
"Rounded Line Color":"Afgeronde lijnkleur",
|
||||
"Perfect Line Color":"Perfecte lijnkleur"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/pl.json
Normal file
189
Source/Horizon-OC-Monitor/lang/pl.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Tryby",
|
||||
"Modes Configure": "Tryby Konfiguruj",
|
||||
"Full": "Pełny",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Mikro",
|
||||
"FPS Graph": "Wykres FPS",
|
||||
"FPS Counter": "Licznik FPS",
|
||||
"Game Resolutions": "Rozdzielczości gry",
|
||||
"Other": "Inne",
|
||||
"Battery/Charger": "Bateria/Ładowarka",
|
||||
"Miscellaneous": "Różne",
|
||||
"CPU Usage": "Użycie CPU",
|
||||
"GPU Usage": "Użycie GPU",
|
||||
"RAM Usage": "Użycie RAM",
|
||||
"Target Frequency": "Częstotliwość docelowa",
|
||||
"Real Frequency": "Rzeczywista częstotliwość",
|
||||
"Core 0 ": "Rdzeń 0 ",
|
||||
"Core 1 ": "Rdzeń 1 ",
|
||||
"Core 2 ": "Rdzeń 2 ",
|
||||
"Core 3 ": "Rdzeń 3 ",
|
||||
"Load": "Obciążenie",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Razem\nAplikacja\nApplet\nSystem\nSystem (niebezpieczny)",
|
||||
"Board": "Płyta",
|
||||
"Battery Power Flow": "Przepływ mocy baterii",
|
||||
"\nTemperatures": "\nTemperatury",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Poziom obrotów wentylatora",
|
||||
"Game": "Gra",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Rozdzielczości ",
|
||||
"Read Speed ": "Prędkość odczytu ",
|
||||
"Press ": "Naciśnij ",
|
||||
" to Exit": " aby wyjść",
|
||||
"Depth": "Głębia",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Gra nie jest uruchomiona\nlub jest niekompatybilna.",
|
||||
"Battery Stats": "Statystyki baterii",
|
||||
"Actual Capacity": "Rzeczywista pojemność",
|
||||
"Designed Capacity": "Pojemność znamionowa",
|
||||
"Temperature": "Temperatura",
|
||||
"Raw Charge": "Surowy poziom naładowania",
|
||||
"Age": "Wiek",
|
||||
"Voltage": "Napięcie",
|
||||
"Current Flow": "Przepływ prądu",
|
||||
"Power Flow": "Przepływ mocy",
|
||||
"Remaining Time": "Pozostały czas",
|
||||
"Charger Stats": "Statystyki ładowarki",
|
||||
"Input Current Limit": "Limit prądu wejściowego",
|
||||
"VBUS Current Limit": "Limit prądu VBUS",
|
||||
"Voltage Limit": "Limit napięcia",
|
||||
"Current Limit": "Limit prądu",
|
||||
"Type": "Typ",
|
||||
"Max Voltage": "Maks. napięcie",
|
||||
"Max Current": "Maks. prąd",
|
||||
"Multimedia Clock Rates": "Taktowanie multimediów",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Sieć",
|
||||
"Type: Wi-Fi": "Typ: Wi-Fi",
|
||||
"Press Y to show password": "Naciśnij Y, aby pokazać hasło",
|
||||
"Type: Ethernet": "Typ: Ethernet",
|
||||
"Type: Not connected": "Typ: Nie połączono",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Elementy Przesuń w dół Przesuń w górę",
|
||||
"Transparent": "Przezroczysty",
|
||||
"Opaque": "Nieprzezroczysty",
|
||||
"Alpha": "Alfa",
|
||||
"Pretty": "Ładny",
|
||||
"Compact": "Kompaktowy",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "Dzień+Czas",
|
||||
"Date+Time(s)": "Data+Czas(s)",
|
||||
"Date+Time AM/PM": "Data+Czas AM/PM",
|
||||
"Date+Time(s) AM/PM": "Data+Czas(s) AM/PM",
|
||||
"Date+Time EU": "Data+Czas EU",
|
||||
"Date+Time EU AM/PM": "Data+Czas EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Data+Czas(s) EU AM/PM",
|
||||
"Date+Time ISO": "Data+Czas ISO",
|
||||
"Time 24h": "Czas 24h",
|
||||
"Time AM/PM": "Czas AM/PM",
|
||||
"Time(s) 24h": "Czas(s) 24h",
|
||||
"Time(s) AM/PM": "Czas(s) AM/PM",
|
||||
"Date US": "Data US",
|
||||
"Date EU": "Data EU",
|
||||
"Date ISO": "Data ISO",
|
||||
"Date Short": "Krótka data",
|
||||
"DTC Format": "Format DTC",
|
||||
"Toggles": "Przełączniki",
|
||||
"Info": "Pokaż informacje",
|
||||
"Disable Screenshots": "Wyłącz zrzuty ekranu",
|
||||
"Real Freqs": "Rzeczywiste częstotliwości",
|
||||
"Deltas": "Delty",
|
||||
"Target Freqs": "Docelowe częstotliwości",
|
||||
"FPS": "FPS",
|
||||
"RES": "ROZDZ.",
|
||||
"Read Speed": "Prędkość odczytu",
|
||||
"Real Frequencies": "Rzeczywiste częstotliwości",
|
||||
"Real Voltages": "Rzeczywiste napięcia",
|
||||
"Full CPU": "Pełny CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Pełna rozdzielczość",
|
||||
"SOC Voltage": "Napięcie SOC",
|
||||
"RAM Load CPU/GPU": "Obciążenie RAM CPU/GPU",
|
||||
"Use DTC Symbol": "Użyj symbolu DTC",
|
||||
"Use Dynamic Colors": "Użyj dynamicznych kolorów",
|
||||
"Sleep Exit": "Wyjście z uśpienia",
|
||||
"Configuration": "Konfiguracja",
|
||||
"Refresh Rate": "Częstotliwość odświeżania",
|
||||
"Frame Padding": "Wypełnienie ramki",
|
||||
" Font Size": " Rozmiar czcionki",
|
||||
"Font Sizes": "Rozmiary czcionki",
|
||||
"Handheld Font Size": "Rozmiar czcionki w trybie przenośnym",
|
||||
"Docked Font Size": "Rozmiar czcionki w trybie stacjonarnym",
|
||||
"Black": "Czarny",
|
||||
"Dark Gray": "Ciemnoszary",
|
||||
"Gray": "Szary",
|
||||
"Light Gray": "Jasnoszary",
|
||||
"Silver": "Srebrny",
|
||||
"White": "Biały",
|
||||
"Dark Red": "Ciemnoczerwony",
|
||||
"Red": "Czerwony",
|
||||
"Light Red": "Jasnoczerwony",
|
||||
"Pink": "Różowy",
|
||||
"Dark Green": "Ciemnozielony",
|
||||
"Green": "Zielony",
|
||||
"Lime Green": "Limonkowy",
|
||||
"Light Green": "Jasnozielony",
|
||||
"Dark Blue": "Ciemnoniebieski",
|
||||
"Blue": "Niebieski",
|
||||
"Light Blue": "Jasnoniebieski",
|
||||
"Sky Blue": "Błękitny",
|
||||
"Dark Purple": "Ciemnofioletowy",
|
||||
"Purple": "Fioletowy",
|
||||
"Light Purple": "Jasnofioletowy",
|
||||
"Violet": "Fiolet",
|
||||
"Orange": "Pomarańczowy",
|
||||
"Yellow": "Żółty",
|
||||
"Light Yellow": "Jasnożółty",
|
||||
"Teal": "Morski",
|
||||
"Cyan": "Cyjan",
|
||||
"Light Cyan": "Jasny cyjan",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Jaskrawo różowy",
|
||||
"Brown": "Brązowy",
|
||||
"Light Brown": "Jasnobrązowy",
|
||||
"Colors": "Kolory",
|
||||
"Background Color": "Kolor tła",
|
||||
"Background Alpha": "Przezroczystość tła",
|
||||
"Focus Color": "Kolor fokusu",
|
||||
"Focus Alpha": "Przezroczystość fokusu",
|
||||
"Text Color": "Kolor tekstu",
|
||||
"Border": "Obramowanie",
|
||||
"Dashed Line": "Linia przerywana",
|
||||
"Max FPS Text": "Tekst maks. FPS",
|
||||
"Min FPS Text": "Tekst min. FPS",
|
||||
"Main Line": "Główna linia",
|
||||
"Rounded Line": "Zaokrąglona linia",
|
||||
"Perfect Line": "Idealna linia",
|
||||
" Color": " Kolor",
|
||||
" Alpha": " Alfa",
|
||||
"Category Color": "Kolor kategorii",
|
||||
"Category Color 1": "Kolor kategorii 1",
|
||||
"Category Color 2": "Kolor kategorii 2",
|
||||
"Separator Color": "Kolor separatora",
|
||||
"Elements": "Elementy",
|
||||
"Text Alignment": "Wyrównanie tekstu",
|
||||
"Vertical Position": "Pozycja pionowa",
|
||||
"Horizontal Position": "Pozycja pozioma",
|
||||
"Left": "Lewo",
|
||||
"Right": "Prawo",
|
||||
"Top": "Góra",
|
||||
"Center": "Środek",
|
||||
"Bottom": "Dół",
|
||||
"FPS Counter Color": "Kolor licznika FPS",
|
||||
"FPS Counter Alpha": "Alfa licznika FPS",
|
||||
"Border Color": "Kolor obramowania",
|
||||
"Dashed Line Color": "Kolor linii przerywanej",
|
||||
"Dashed Line Alpha": "Alfa linii przerywanej",
|
||||
"Max FPS Text Color": "Kolor tekstu maks. FPS",
|
||||
"Min FPS Text Color": "Kolor tekstu min. FPS",
|
||||
"Main Line Color": "Kolor głównej linii",
|
||||
"Rounded Line Color": "Kolor zaokrąglonej linii",
|
||||
"Perfect Line Color": "Kolor idealnej linii"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/pt.json
Normal file
189
Source/Horizon-OC-Monitor/lang/pt.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Modos",
|
||||
"Modes Configure": "Modos Configurar",
|
||||
"Full": "Completo",
|
||||
"Mini": "Mini",
|
||||
"Micro": "Micro",
|
||||
"FPS Graph": "Gráfico FPS",
|
||||
"FPS Counter": "Contador FPS",
|
||||
"Game Resolutions": "Resoluções no Jogo",
|
||||
"Other": "Outros",
|
||||
"Battery/Charger": "Bateria/Carregador",
|
||||
"Miscellaneous": "Diversos",
|
||||
"CPU Usage": "Uso da CPU",
|
||||
"GPU Usage": "Uso da GPU",
|
||||
"RAM Usage": "Uso da RAM",
|
||||
"Target Frequency": "Frequência Alvo",
|
||||
"Real Frequency": "Frequência Real",
|
||||
"Core 0 ": "Núcleo 0 ",
|
||||
"Core 1 ": "Núcleo 1 ",
|
||||
"Core 2 ": "Núcleo 2 ",
|
||||
"Core 3 ": "Núcleo 3 ",
|
||||
"Load": "Carga",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Total\nAplicativo\nMiniAplicativo\nSistema\nSistema Inseguro",
|
||||
"Board": "Placa",
|
||||
"Battery Power Flow": "Fluxo de Energia",
|
||||
"\nTemperatures": "\nTemperaturas",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Rotação da Fan",
|
||||
"Game": "Jogo",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Resoluções ",
|
||||
"Read Speed ": "Velocidade de Leitura ",
|
||||
"Press ": "Pressione ",
|
||||
" to Exit": " para Sair",
|
||||
"Depth": "Profundidade",
|
||||
"Viewport": "Visualização",
|
||||
"Game is not running\nor it's incompatible.": "O jogo não está rodando\n ou não é compatível.",
|
||||
"Battery Stats": "Estatísticas da Bateria",
|
||||
"Actual Capacity": "Capacidade Atual",
|
||||
"Designed Capacity": "Capacidade Designada",
|
||||
"Temperature": "Temperatura",
|
||||
"Raw Charge": "Carga Bruta",
|
||||
"Age": "Idade",
|
||||
"Voltage": "Voltagem",
|
||||
"Current Flow": "Fluxo de Corrente",
|
||||
"Power Flow": "Fluxo de Potência",
|
||||
"Remaining Time": "Tempo Restante",
|
||||
"Charger Stats": "Estatísticas do Carregador",
|
||||
"Input Current Limit": "Limite Corrente Entrada",
|
||||
"VBUS Current Limit": "Limite Corrente VBUS",
|
||||
"Voltage Limit": "Limite de Voltagem",
|
||||
"Current Limit": "Limite Atual",
|
||||
"Type": "Tipo",
|
||||
"Max Voltage": "Voltagem Máxima",
|
||||
"Max Current": "Corrente Máxima",
|
||||
"Multimedia Clock Rates": "Frequências Multimídia",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Rede",
|
||||
"Type: Wi-Fi": "Tipo: Wi-Fi",
|
||||
"Press Y to show password": "Pressione Y para exibir a senha",
|
||||
"Type: Ethernet": "Tipo: Ethernet",
|
||||
"Type: Not connected": "Tipo: Não conectado",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Elementos Descer Subir",
|
||||
"Transparent": "Transparente",
|
||||
"Opaque": "Opaco",
|
||||
"Alpha": "Alfa",
|
||||
"Pretty": "Bonito",
|
||||
"Compact": "Compacto",
|
||||
"FileSafe": "Seguro",
|
||||
"Day+Time": "Dia+Hora",
|
||||
"Date+Time(s)": "Data+Hora(s)",
|
||||
"Date+Time AM/PM": "Data+Hora AM/PM",
|
||||
"Date+Time(s) AM/PM": "Data+Hora(s) AM/PM",
|
||||
"Date+Time EU": "Data+Hora EU",
|
||||
"Date+Time EU AM/PM": "Data+Hora EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Data+Hora(s) EU AM/PM",
|
||||
"Date+Time ISO": "Data+Hora ISO",
|
||||
"Time 24h": "Hora 24h",
|
||||
"Time AM/PM": "Hora AM/PM",
|
||||
"Time(s) 24h": "Hora(s) 24h",
|
||||
"Time(s) AM/PM": "Hora(s) AM/PM",
|
||||
"Date US": "Data US",
|
||||
"Date EU": "Data EU",
|
||||
"Date ISO": "Data ISO",
|
||||
"Date Short": "Data Abreviada",
|
||||
"DTC Format": "Formato DTC",
|
||||
"Toggles": "Alternar",
|
||||
"Info": "Informações",
|
||||
"Disable Screenshots": "Desativar Capturas",
|
||||
"Real Freqs": "Frequências Reais",
|
||||
"Deltas": "Deltas",
|
||||
"Target Freqs": "Frequências Alvo",
|
||||
"FPS": "FPS",
|
||||
"RES": "RES",
|
||||
"Read Speed": "Velocidade de Leitura",
|
||||
"Real Frequencies": "Frequências Reais",
|
||||
"Real Voltages": "Voltagens Reais",
|
||||
"Full CPU": "CPU Completa",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Resolução Completa",
|
||||
"SOC Voltage": "Voltagem do SOC",
|
||||
"RAM Load CPU/GPU": "Carga na CPU/GPU",
|
||||
"Use DTC Symbol": "Usar Símbolo DTC",
|
||||
"Use Dynamic Colors": "Usar Cores Dinâmicas",
|
||||
"Sleep Exit": "Sair do Repouso",
|
||||
"Configuration": "Configuração",
|
||||
"Refresh Rate": "Taxa de Atualização",
|
||||
"Frame Padding": "Preenc. de Quadro",
|
||||
" Font Size": " Tamanho da Fonte",
|
||||
"Font Sizes": "Tamanho das Fontes",
|
||||
"Handheld Font Size": "Modo Portátil",
|
||||
"Docked Font Size": "Modo Dock",
|
||||
"Black": "Preto",
|
||||
"Dark Gray": "Cinza Escuro",
|
||||
"Gray": "Cinza",
|
||||
"Light Gray": "Cinza Claro",
|
||||
"Silver": "Prata",
|
||||
"White": "Branco",
|
||||
"Dark Red": "Vermelho Escuro",
|
||||
"Red": "Vermelho",
|
||||
"Light Red": "LVermelho Claro",
|
||||
"Pink": "Rosa",
|
||||
"Dark Green": "Verde Escuro",
|
||||
"Green": "Verde",
|
||||
"Lime Green": "Verde Limão",
|
||||
"Light Green": "Verde Claro",
|
||||
"Dark Blue": "Azul Escuro",
|
||||
"Blue": "Azul",
|
||||
"Light Blue": "Azul Claro",
|
||||
"Sky Blue": "Azul Céu",
|
||||
"Dark Purple": "Roxo Escuro",
|
||||
"Purple": "Roxo",
|
||||
"Light Purple": "Roxo Claro",
|
||||
"Violet": "Violeta",
|
||||
"Orange": "Laranja",
|
||||
"Yellow": "Amarelo",
|
||||
"Light Yellow": "Amarelo Claro",
|
||||
"Teal": "Verde Azulado",
|
||||
"Cyan": "Ciano",
|
||||
"Light Cyan": "Ciano Claro",
|
||||
"Magenta": "Magenta",
|
||||
"Hot Pink": "Rosa Choque",
|
||||
"Brown": "Marrom",
|
||||
"Light Brown": "Marrom Claro",
|
||||
"Colors": "Cores",
|
||||
"Background Color": "Cor de Fundo",
|
||||
"Background Alpha": "Opacidade",
|
||||
"Focus Color": "Cor em Foco",
|
||||
"Focus Alpha": "Alfa em Foco",
|
||||
"Text Color": "Cor do Texto",
|
||||
"Border": "Borda",
|
||||
"Dashed Line": "Linha Tracejada",
|
||||
"Max FPS Text": "Texto Máx. FPS",
|
||||
"Min FPS Text": "Texto Min. FPS",
|
||||
"Main Line": "Linha Principal",
|
||||
"Rounded Line": "Linha Arredondada",
|
||||
"Perfect Line": "Linha Perfeita",
|
||||
" Color": " Cor",
|
||||
" Alpha": " Alfa",
|
||||
"Category Color": "Cor da Categoria",
|
||||
"Category Color 1": "Cor Categoria 1",
|
||||
"Category Color 2": "Cor Categoria 2",
|
||||
"Separator Color": "Cor do Separador",
|
||||
"Elements": "Elementos",
|
||||
"Text Alignment": "Alinhamento do Texto",
|
||||
"Vertical Position": "Posição Vertical",
|
||||
"Horizontal Position": "Posição Horizontal",
|
||||
"Left": "Esquerdo",
|
||||
"Right": "Direito",
|
||||
"Top": "Topo",
|
||||
"Center": "Centro",
|
||||
"Bottom": "Baixo",
|
||||
"FPS Counter Color":"Cor Contador FPS",
|
||||
"FPS Counter Alpha":"Opac. Contador FPS",
|
||||
"Border Color":"Cor da Borda",
|
||||
"Dashed Line Color":"Cor Linha Trac.",
|
||||
"Dashed Line Alpha":"Opac. Linha Trac.",
|
||||
"Max FPS Text Color":"Cor Texto FPS Máx.",
|
||||
"Min FPS Text Color":"Cor Texto FPS Min.",
|
||||
"Main Line Color":"Cor Linha Principal",
|
||||
"Rounded Line Color":"Cor Linha Arrend.",
|
||||
"Perfect Line Color":"Cor Linha Perfeita"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/ru.json
Normal file
189
Source/Horizon-OC-Monitor/lang/ru.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Режимы",
|
||||
"Modes Configure": "Режимы Настроить",
|
||||
"Full": "Полный",
|
||||
"Mini": "Мини",
|
||||
"Micro": "Микро",
|
||||
"FPS Graph": "График FPS",
|
||||
"FPS Counter": "Счётчик FPS",
|
||||
"Game Resolutions": "Разрешения игры",
|
||||
"Other": "Прочее",
|
||||
"Battery/Charger": "Аккумулятор/Зарядка",
|
||||
"Miscellaneous": "Разное",
|
||||
"CPU Usage": "Загрузка CPU",
|
||||
"GPU Usage": "Загрузка GPU",
|
||||
"RAM Usage": "Загрузка RAM",
|
||||
"Target Frequency": "Целевая частота",
|
||||
"Real Frequency": "Реальная частота",
|
||||
"Core 0 ": "Ядро 0 ",
|
||||
"Core 1 ": "Ядро 1 ",
|
||||
"Core 2 ": "Ядро 2 ",
|
||||
"Core 3 ": "Ядро 3 ",
|
||||
"Load": "Нагрузка",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Всего\nПриложение\nАпплет\nСистема\nСистема (небезопасно)",
|
||||
"Board": "Плата",
|
||||
"Battery Power Flow": "Поток энергии аккумулятора",
|
||||
"\nTemperatures": "\nТемпературы",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Уровень вращения вентилятора",
|
||||
"Game": "Игра",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Разрешения ",
|
||||
"Read Speed ": "Скорость чтения ",
|
||||
"Press ": "Нажмите ",
|
||||
" to Exit": " для выхода",
|
||||
"Depth": "Глубина",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Игра не запущена\nили несовместима.",
|
||||
"Battery Stats": "Статистика аккумулятора",
|
||||
"Actual Capacity": "Фактическая ёмкость",
|
||||
"Designed Capacity": "Номинальная ёмкость",
|
||||
"Temperature": "Температура",
|
||||
"Raw Charge": "Сырой заряд",
|
||||
"Age": "Возраст",
|
||||
"Voltage": "Напряжение",
|
||||
"Current Flow": "Ток",
|
||||
"Power Flow": "Мощность",
|
||||
"Remaining Time": "Оставшееся время",
|
||||
"Charger Stats": "Статистика зарядки",
|
||||
"Input Current Limit": "Лимит входного тока",
|
||||
"VBUS Current Limit": "Лимит тока VBUS",
|
||||
"Voltage Limit": "Лимит напряжения",
|
||||
"Current Limit": "Лимит тока",
|
||||
"Type": "Тип",
|
||||
"Max Voltage": "Макс. напряжение",
|
||||
"Max Current": "Макс. ток",
|
||||
"Multimedia Clock Rates": "Частоты мультимедиа",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Сеть",
|
||||
"Type: Wi-Fi": "Тип: Wi-Fi",
|
||||
"Press Y to show password": "Нажмите Y, чтобы показать пароль",
|
||||
"Type: Ethernet": "Тип: Ethernet",
|
||||
"Type: Not connected": "Тип: Не подключено",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Элементы Вниз Вверх",
|
||||
"Transparent": "Прозрачный",
|
||||
"Opaque": "Непрозрачный",
|
||||
"Alpha": "Альфа",
|
||||
"Pretty": "Красивый",
|
||||
"Compact": "Компактный",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "День+Время",
|
||||
"Date+Time(s)": "Дата+Время(с)",
|
||||
"Date+Time AM/PM": "Дата+Время AM/PM",
|
||||
"Date+Time(s) AM/PM": "Дата+Время(с) AM/PM",
|
||||
"Date+Time EU": "Дата+Время EU",
|
||||
"Date+Time EU AM/PM": "Дата+Время EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Дата+Время(с) EU AM/PM",
|
||||
"Date+Time ISO": "Дата+Время ISO",
|
||||
"Time 24h": "Время 24ч",
|
||||
"Time AM/PM": "Время AM/PM",
|
||||
"Time(s) 24h": "Время(с) 24ч",
|
||||
"Time(s) AM/PM": "Время(с) AM/PM",
|
||||
"Date US": "Дата US",
|
||||
"Date EU": "Дата EU",
|
||||
"Date ISO": "Дата ISO",
|
||||
"Date Short": "Краткая дата",
|
||||
"DTC Format": "Формат DTC",
|
||||
"Toggles": "Переключатели",
|
||||
"Info": "Показать информацию",
|
||||
"Disable Screenshots": "Отключить скриншоты",
|
||||
"Real Freqs": "Реальные частоты",
|
||||
"Deltas": "Дельты",
|
||||
"Target Freqs": "Целевые частоты",
|
||||
"FPS": "FPS",
|
||||
"RES": "РАЗР.",
|
||||
"Read Speed": "Скорость чтения",
|
||||
"Real Frequencies": "Реальные частоты",
|
||||
"Real Voltages": "Реальные напряжения",
|
||||
"Full CPU": "Полный CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Полное разрешение",
|
||||
"SOC Voltage": "Напряжение SOC",
|
||||
"RAM Load CPU/GPU": "Нагрузка RAM CPU/GPU",
|
||||
"Use DTC Symbol": "Использовать символ DTC",
|
||||
"Use Dynamic Colors": "Использовать динамические цвета",
|
||||
"Sleep Exit": "Выход из сна",
|
||||
"Configuration": "Конфигурация",
|
||||
"Refresh Rate": "Частота обновления",
|
||||
"Frame Padding": "Отступ кадра",
|
||||
" Font Size": " Размер шрифта",
|
||||
"Font Sizes": "Размеры шрифта",
|
||||
"Handheld Font Size": "Размер шрифта в портативном режиме",
|
||||
"Docked Font Size": "Размер шрифта в док-режиме",
|
||||
"Black": "Чёрный",
|
||||
"Dark Gray": "Тёмно-серый",
|
||||
"Gray": "Серый",
|
||||
"Light Gray": "Светло-серый",
|
||||
"Silver": "Серебряный",
|
||||
"White": "Белый",
|
||||
"Dark Red": "Тёмно-красный",
|
||||
"Red": "Красный",
|
||||
"Light Red": "Светло-красный",
|
||||
"Pink": "Розовый",
|
||||
"Dark Green": "Тёмно-зелёный",
|
||||
"Green": "Зелёный",
|
||||
"Lime Green": "Лаймовый",
|
||||
"Light Green": "Светло-зелёный",
|
||||
"Dark Blue": "Тёмно-синий",
|
||||
"Blue": "Синий",
|
||||
"Light Blue": "Светло-синий",
|
||||
"Sky Blue": "Небесно-голубой",
|
||||
"Dark Purple": "Тёмно-фиолетовый",
|
||||
"Purple": "Фиолетовый",
|
||||
"Light Purple": "Светло-фиолетовый",
|
||||
"Violet": "Фиолетовый",
|
||||
"Orange": "Оранжевый",
|
||||
"Yellow": "Жёлтый",
|
||||
"Light Yellow": "Светло-жёлтый",
|
||||
"Teal": "Бирюзовый",
|
||||
"Cyan": "Голубой",
|
||||
"Light Cyan": "Светло-голубой",
|
||||
"Magenta": "Пурпурный",
|
||||
"Hot Pink": "Ярко-розовый",
|
||||
"Brown": "Коричневый",
|
||||
"Light Brown": "Светло-коричневый",
|
||||
"Colors": "Цвета",
|
||||
"Background Color": "Цвет фона",
|
||||
"Background Alpha": "Прозрачность фона",
|
||||
"Focus Color": "Цвет фокуса",
|
||||
"Focus Alpha": "Прозрачность фокуса",
|
||||
"Text Color": "Цвет текста",
|
||||
"Border": "Граница",
|
||||
"Dashed Line": "Пунктирная линия",
|
||||
"Max FPS Text": "Текст макс. FPS",
|
||||
"Min FPS Text": "Текст мин. FPS",
|
||||
"Main Line": "Основная линия",
|
||||
"Rounded Line": "Скруглённая линия",
|
||||
"Perfect Line": "Идеальная линия",
|
||||
" Color": " Цвет",
|
||||
" Alpha": " Прозрачность",
|
||||
"Category Color": "Цвет категории",
|
||||
"Category Color 1": "Цвет категории 1",
|
||||
"Category Color 2": "Цвет категории 2",
|
||||
"Separator Color": "Цвет разделителя",
|
||||
"Elements": "Элементы",
|
||||
"Text Alignment": "Выравнивание текста",
|
||||
"Vertical Position": "Вертикальная позиция",
|
||||
"Horizontal Position": "Горизонтальная позиция",
|
||||
"Left": "Слева",
|
||||
"Right": "Справа",
|
||||
"Top": "Сверху",
|
||||
"Center": "По центру",
|
||||
"Bottom": "Снизу",
|
||||
"FPS Counter Color": "Цвет счётчика FPS",
|
||||
"FPS Counter Alpha": "Прозрачность счётчика FPS",
|
||||
"Border Color": "Цвет границы",
|
||||
"Dashed Line Color": "Цвет пунктирной линии",
|
||||
"Dashed Line Alpha": "Прозрачность пунктирной линии",
|
||||
"Max FPS Text Color": "Цвет текста макс. FPS",
|
||||
"Min FPS Text Color": "Цвет текста мин. FPS",
|
||||
"Main Line Color": "Цвет основной линии",
|
||||
"Rounded Line Color": "Цвет скруглённой линии",
|
||||
"Perfect Line Color": "Цвет идеальной линии"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/uk.json
Normal file
189
Source/Horizon-OC-Monitor/lang/uk.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "Режими",
|
||||
"Modes Configure": "Режими Налаштувати",
|
||||
"Full": "Повний",
|
||||
"Mini": "Міні",
|
||||
"Micro": "Мікро",
|
||||
"FPS Graph": "Графік FPS",
|
||||
"FPS Counter": "Лічильник FPS",
|
||||
"Game Resolutions": "Роздільна здатність гри",
|
||||
"Other": "Інше",
|
||||
"Battery/Charger": "Акумулятор/Зарядка",
|
||||
"Miscellaneous": "Різне",
|
||||
"CPU Usage": "Завантаження CPU",
|
||||
"GPU Usage": "Завантаження GPU",
|
||||
"RAM Usage": "Завантаження RAM",
|
||||
"Target Frequency": "Цільова частота",
|
||||
"Real Frequency": "Реальна частота",
|
||||
"Core 0 ": "Ядро 0 ",
|
||||
"Core 1 ": "Ядро 1 ",
|
||||
"Core 2 ": "Ядро 2 ",
|
||||
"Core 3 ": "Ядро 3 ",
|
||||
"Load": "Навантаження",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "Всього\nДодаток\nАплет\nСистема\nСистема (небезпечно)",
|
||||
"Board": "Плата",
|
||||
"Battery Power Flow": "Потік енергії акумулятора",
|
||||
"\nTemperatures": "\nТемператури",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "Рівень обертання вентилятора",
|
||||
"Game": "Гра",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "Роздільна здатність ",
|
||||
"Read Speed ": "Швидкість зчитування ",
|
||||
"Press ": "Натисніть ",
|
||||
" to Exit": " для виходу",
|
||||
"Depth": "Глибина",
|
||||
"Viewport": "Viewport",
|
||||
"Game is not running\nor it's incompatible.": "Гра не запущена\nабо несумісна.",
|
||||
"Battery Stats": "Статистика акумулятора",
|
||||
"Actual Capacity": "Фактична ємність",
|
||||
"Designed Capacity": "Номінальна ємність",
|
||||
"Temperature": "Температура",
|
||||
"Raw Charge": "Сирий заряд",
|
||||
"Age": "Вік",
|
||||
"Voltage": "Напруга",
|
||||
"Current Flow": "Струм",
|
||||
"Power Flow": "Потужність",
|
||||
"Remaining Time": "Залишковий час",
|
||||
"Charger Stats": "Статистика зарядки",
|
||||
"Input Current Limit": "Ліміт вхідного струму",
|
||||
"VBUS Current Limit": "Ліміт струму VBUS",
|
||||
"Voltage Limit": "Ліміт напруги",
|
||||
"Current Limit": "Ліміт струму",
|
||||
"Type": "Тип",
|
||||
"Max Voltage": "Макс. напруга",
|
||||
"Max Current": "Макс. струм",
|
||||
"Multimedia Clock Rates": "Частоти мультимедіа",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "Мережа",
|
||||
"Type: Wi-Fi": "Тип: Wi-Fi",
|
||||
"Press Y to show password": "Натисніть Y, щоб показати пароль",
|
||||
"Type: Ethernet": "Тип: Ethernet",
|
||||
"Type: Not connected": "Тип: Не підключено",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "Елементи Вниз Вгору",
|
||||
"Transparent": "Прозорий",
|
||||
"Opaque": "Непрозорий",
|
||||
"Alpha": "Альфа",
|
||||
"Pretty": "Красивий",
|
||||
"Compact": "Компактний",
|
||||
"FileSafe": "FileSafe",
|
||||
"Day+Time": "День+Час",
|
||||
"Date+Time(s)": "Дата+Час(с)",
|
||||
"Date+Time AM/PM": "Дата+Час AM/PM",
|
||||
"Date+Time(s) AM/PM": "Дата+Час(с) AM/PM",
|
||||
"Date+Time EU": "Дата+Час EU",
|
||||
"Date+Time EU AM/PM": "Дата+Час EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "Дата+Час(с) EU AM/PM",
|
||||
"Date+Time ISO": "Дата+Час ISO",
|
||||
"Time 24h": "Час 24год",
|
||||
"Time AM/PM": "Час AM/PM",
|
||||
"Time(s) 24h": "Час(с) 24год",
|
||||
"Time(s) AM/PM": "Час(с) AM/PM",
|
||||
"Date US": "Дата US",
|
||||
"Date EU": "Дата EU",
|
||||
"Date ISO": "Дата ISO",
|
||||
"Date Short": "Коротка дата",
|
||||
"DTC Format": "Формат DTC",
|
||||
"Toggles": "Перемикачі",
|
||||
"Info": "Показати інформацію",
|
||||
"Disable Screenshots": "Вимкнути знімки екрана",
|
||||
"Real Freqs": "Реальні частоти",
|
||||
"Deltas": "Дельти",
|
||||
"Target Freqs": "Цільові частоти",
|
||||
"FPS": "FPS",
|
||||
"RES": "РОЗД.",
|
||||
"Read Speed": "Швидкість зчитування",
|
||||
"Real Frequencies": "Реальні частоти",
|
||||
"Real Voltages": "Реальні напруги",
|
||||
"Full CPU": "Повний CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "Повна роздільна здатність",
|
||||
"SOC Voltage": "Напруга SOC",
|
||||
"RAM Load CPU/GPU": "Навантаження RAM CPU/GPU",
|
||||
"Use DTC Symbol": "Використовувати символ DTC",
|
||||
"Use Dynamic Colors": "Використовувати динамічні кольори",
|
||||
"Sleep Exit": "Вихід зі сну",
|
||||
"Configuration": "Конфігурація",
|
||||
"Refresh Rate": "Частота оновлення",
|
||||
"Frame Padding": "Відступ кадру",
|
||||
" Font Size": " Розмір шрифту",
|
||||
"Font Sizes": "Розміри шрифту",
|
||||
"Handheld Font Size": "Розмір шрифту в портативному режимі",
|
||||
"Docked Font Size": "Розмір шрифту в док-режимі",
|
||||
"Black": "Чорний",
|
||||
"Dark Gray": "Темно-сірий",
|
||||
"Gray": "Сірий",
|
||||
"Light Gray": "Світло-сірий",
|
||||
"Silver": "Сріблястий",
|
||||
"White": "Білий",
|
||||
"Dark Red": "Темно-червоний",
|
||||
"Red": "Червоний",
|
||||
"Light Red": "Світло-червоний",
|
||||
"Pink": "Рожевий",
|
||||
"Dark Green": "Темно-зелений",
|
||||
"Green": "Зелений",
|
||||
"Lime Green": "Лаймовий",
|
||||
"Light Green": "Світло-зелений",
|
||||
"Dark Blue": "Темно-синій",
|
||||
"Blue": "Синій",
|
||||
"Light Blue": "Світло-синій",
|
||||
"Sky Blue": "Небесно-блакитний",
|
||||
"Dark Purple": "Темно-фіолетовий",
|
||||
"Purple": "Фіолетовий",
|
||||
"Light Purple": "Світло-фіолетовий",
|
||||
"Violet": "Фіолетовий",
|
||||
"Orange": "Помаранчевий",
|
||||
"Yellow": "Жовтий",
|
||||
"Light Yellow": "Світло-жовтий",
|
||||
"Teal": "Бірюзовий",
|
||||
"Cyan": "Блакитний",
|
||||
"Light Cyan": "Світло-блакитний",
|
||||
"Magenta": "Пурпуровий",
|
||||
"Hot Pink": "Яскраво-рожевий",
|
||||
"Brown": "Коричневий",
|
||||
"Light Brown": "Світло-коричневий",
|
||||
"Colors": "Кольори",
|
||||
"Background Color": "Колір фону",
|
||||
"Background Alpha": "Прозорість фону",
|
||||
"Focus Color": "Колір фокусу",
|
||||
"Focus Alpha": "Прозорість фокусу",
|
||||
"Text Color": "Колір тексту",
|
||||
"Border": "Межа",
|
||||
"Dashed Line": "Пунктирна лінія",
|
||||
"Max FPS Text": "Текст макс. FPS",
|
||||
"Min FPS Text": "Текст мін. FPS",
|
||||
"Main Line": "Основна лінія",
|
||||
"Rounded Line": "Закруглена лінія",
|
||||
"Perfect Line": "Ідеальна лінія",
|
||||
" Color": " Колір",
|
||||
" Alpha": " Прозорість",
|
||||
"Category Color": "Колір категорії",
|
||||
"Category Color 1": "Колір категорії 1",
|
||||
"Category Color 2": "Колір категорії 2",
|
||||
"Separator Color": "Колір роздільника",
|
||||
"Elements": "Елементи",
|
||||
"Text Alignment": "Вирівнювання тексту",
|
||||
"Vertical Position": "Вертикальна позиція",
|
||||
"Horizontal Position": "Горизонтальна позиція",
|
||||
"Left": "Зліва",
|
||||
"Right": "Справа",
|
||||
"Top": "Зверху",
|
||||
"Center": "По центру",
|
||||
"Bottom": "Знизу",
|
||||
"FPS Counter Color": "Колір лічильника FPS",
|
||||
"FPS Counter Alpha": "Прозорість лічильника FPS",
|
||||
"Border Color": "Колір межі",
|
||||
"Dashed Line Color": "Колір пунктирної лінії",
|
||||
"Dashed Line Alpha": "Прозорість пунктирної лінії",
|
||||
"Max FPS Text Color": "Колір тексту макс. FPS",
|
||||
"Min FPS Text Color": "Колір тексту мін. FPS",
|
||||
"Main Line Color": "Колір основної лінії",
|
||||
"Rounded Line Color": "Колір закругленої лінії",
|
||||
"Perfect Line Color": "Колір ідеальної лінії"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/zh-cn.json
Normal file
189
Source/Horizon-OC-Monitor/lang/zh-cn.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "模式",
|
||||
"Modes Configure": "模式 配置",
|
||||
"Full": "完整",
|
||||
"Mini": "迷你",
|
||||
"Micro": "微型",
|
||||
"FPS Graph": "FPS 图表",
|
||||
"FPS Counter": "FPS 计数器",
|
||||
"Game Resolutions": "游戏分辨率",
|
||||
"Other": "其他",
|
||||
"Battery/Charger": "电池/充电器",
|
||||
"Miscellaneous": "杂项",
|
||||
"CPU Usage": "CPU 使用率",
|
||||
"GPU Usage": "GPU 使用率",
|
||||
"RAM Usage": "RAM 使用率",
|
||||
"Target Frequency": "目标频率",
|
||||
"Real Frequency": "实际频率",
|
||||
"Core 0 ": "核心 0 ",
|
||||
"Core 1 ": "核心 1 ",
|
||||
"Core 2 ": "核心 2 ",
|
||||
"Core 3 ": "核心 3 ",
|
||||
"Load": "负载",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "总计\n应用\n小程序\n系统\n系统(不安全)",
|
||||
"Board": "主板",
|
||||
"Battery Power Flow": "电池功率流",
|
||||
"\nTemperatures": "\n温度",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "风扇转速级别",
|
||||
"Game": "游戏",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "分辨率 ",
|
||||
"Read Speed ": "读取速度 ",
|
||||
"Press ": "按 ",
|
||||
" to Exit": " 退出",
|
||||
"Depth": "深度",
|
||||
"Viewport": "视口",
|
||||
"Game is not running\nor it's incompatible.": "游戏未运行\n或不兼容。",
|
||||
"Battery Stats": "电池统计",
|
||||
"Actual Capacity": "实际容量",
|
||||
"Designed Capacity": "设计容量",
|
||||
"Temperature": "温度",
|
||||
"Raw Charge": "原始电量",
|
||||
"Age": "寿命",
|
||||
"Voltage": "电压",
|
||||
"Current Flow": "电流",
|
||||
"Power Flow": "功率",
|
||||
"Remaining Time": "剩余时间",
|
||||
"Charger Stats": "充电器统计",
|
||||
"Input Current Limit": "输入电流限制",
|
||||
"VBUS Current Limit": "VBUS 电流限制",
|
||||
"Voltage Limit": "电压限制",
|
||||
"Current Limit": "电流限制",
|
||||
"Type": "类型",
|
||||
"Max Voltage": "最大电压",
|
||||
"Max Current": "最大电流",
|
||||
"Multimedia Clock Rates": "多媒体时钟频率",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "网络",
|
||||
"Type: Wi-Fi": "类型:Wi-Fi",
|
||||
"Press Y to show password": "按 Y 显示密码",
|
||||
"Type: Ethernet": "类型:以太网",
|
||||
"Type: Not connected": "类型:未连接",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "元素 下移 上移",
|
||||
"Transparent": "透明",
|
||||
"Opaque": "不透明",
|
||||
"Alpha": "透明度",
|
||||
"Pretty": "美观",
|
||||
"Compact": "紧凑",
|
||||
"FileSafe": "文件安全",
|
||||
"Day+Time": "日期+时间",
|
||||
"Date+Time(s)": "日期+时间(秒)",
|
||||
"Date+Time AM/PM": "日期+时间 AM/PM",
|
||||
"Date+Time(s) AM/PM": "日期+时间(秒) AM/PM",
|
||||
"Date+Time EU": "日期+时间 EU",
|
||||
"Date+Time EU AM/PM": "日期+时间 EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "日期+时间(秒) EU AM/PM",
|
||||
"Date+Time ISO": "日期+时间 ISO",
|
||||
"Time 24h": "时间 24时",
|
||||
"Time AM/PM": "时间 AM/PM",
|
||||
"Time(s) 24h": "时间(秒) 24时",
|
||||
"Time(s) AM/PM": "时间(秒) AM/PM",
|
||||
"Date US": "日期 US",
|
||||
"Date EU": "日期 EU",
|
||||
"Date ISO": "日期 ISO",
|
||||
"Date Short": "短日期",
|
||||
"DTC Format": "DTC 格式",
|
||||
"Toggles": "开关",
|
||||
"Info": "显示信息",
|
||||
"Disable Screenshots": "禁用截图",
|
||||
"Real Freqs": "实际频率",
|
||||
"Deltas": "差值",
|
||||
"Target Freqs": "目标频率",
|
||||
"FPS": "FPS",
|
||||
"RES": "分辨率",
|
||||
"Read Speed": "读取速度",
|
||||
"Real Frequencies": "实际频率",
|
||||
"Real Voltages": "实际电压",
|
||||
"Full CPU": "完整 CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "完整分辨率",
|
||||
"SOC Voltage": "SOC 电压",
|
||||
"RAM Load CPU/GPU": "RAM 负载 CPU/GPU",
|
||||
"Use DTC Symbol": "使用 DTC 符号",
|
||||
"Use Dynamic Colors": "使用动态颜色",
|
||||
"Sleep Exit": "退出睡眠",
|
||||
"Configuration": "配置",
|
||||
"Refresh Rate": "刷新率",
|
||||
"Frame Padding": "帧填充",
|
||||
" Font Size": " 字体大小",
|
||||
"Font Sizes": "字体大小",
|
||||
"Handheld Font Size": "手持模式字体大小",
|
||||
"Docked Font Size": "底座模式字体大小",
|
||||
"Black": "黑色",
|
||||
"Dark Gray": "深灰",
|
||||
"Gray": "灰色",
|
||||
"Light Gray": "浅灰",
|
||||
"Silver": "银色",
|
||||
"White": "白色",
|
||||
"Dark Red": "深红",
|
||||
"Red": "红色",
|
||||
"Light Red": "浅红",
|
||||
"Pink": "粉红",
|
||||
"Dark Green": "深绿",
|
||||
"Green": "绿色",
|
||||
"Lime Green": "酸橙绿",
|
||||
"Light Green": "浅绿",
|
||||
"Dark Blue": "深蓝",
|
||||
"Blue": "蓝色",
|
||||
"Light Blue": "浅蓝",
|
||||
"Sky Blue": "天蓝",
|
||||
"Dark Purple": "深紫",
|
||||
"Purple": "紫色",
|
||||
"Light Purple": "浅紫",
|
||||
"Violet": "紫罗兰",
|
||||
"Orange": "橙色",
|
||||
"Yellow": "黄色",
|
||||
"Light Yellow": "浅黄",
|
||||
"Teal": "蓝绿",
|
||||
"Cyan": "青色",
|
||||
"Light Cyan": "浅青",
|
||||
"Magenta": "品红",
|
||||
"Hot Pink": "艳粉",
|
||||
"Brown": "棕色",
|
||||
"Light Brown": "浅棕",
|
||||
"Colors": "颜色",
|
||||
"Background Color": "背景颜色",
|
||||
"Background Alpha": "背景透明度",
|
||||
"Focus Color": "焦点颜色",
|
||||
"Focus Alpha": "焦点透明度",
|
||||
"Text Color": "文字颜色",
|
||||
"Border": "边框",
|
||||
"Dashed Line": "虚线",
|
||||
"Max FPS Text": "最大 FPS 文字",
|
||||
"Min FPS Text": "最小 FPS 文字",
|
||||
"Main Line": "主线",
|
||||
"Rounded Line": "圆角线",
|
||||
"Perfect Line": "完美线",
|
||||
" Color": " 颜色",
|
||||
" Alpha": " 透明度",
|
||||
"Category Color": "分类颜色",
|
||||
"Category Color 1": "分类颜色 1",
|
||||
"Category Color 2": "分类颜色 2",
|
||||
"Separator Color": "分隔线颜色",
|
||||
"Elements": "元素",
|
||||
"Text Alignment": "文字对齐",
|
||||
"Vertical Position": "垂直位置",
|
||||
"Horizontal Position": "水平位置",
|
||||
"Left": "左",
|
||||
"Right": "右",
|
||||
"Top": "上",
|
||||
"Center": "中",
|
||||
"Bottom": "下",
|
||||
"FPS Counter Color": "FPS 计数器颜色",
|
||||
"FPS Counter Alpha": "FPS 计数器透明度",
|
||||
"Border Color": "边框颜色",
|
||||
"Dashed Line Color": "虚线颜色",
|
||||
"Dashed Line Alpha": "虚线透明度",
|
||||
"Max FPS Text Color": "最大 FPS 文字颜色",
|
||||
"Min FPS Text Color": "最小 FPS 文字颜色",
|
||||
"Main Line Color": "主线颜色",
|
||||
"Rounded Line Color": "圆角线颜色",
|
||||
"Perfect Line Color": "完美线颜色"
|
||||
}
|
||||
189
Source/Horizon-OC-Monitor/lang/zh-tw.json
Normal file
189
Source/Horizon-OC-Monitor/lang/zh-tw.json
Normal file
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"Status Monitor": "Status Monitor",
|
||||
"Modes": "模式",
|
||||
"Modes Configure": "模式 設定",
|
||||
"Full": "完整",
|
||||
"Mini": "迷你",
|
||||
"Micro": "微型",
|
||||
"FPS Graph": "FPS 圖表",
|
||||
"FPS Counter": "FPS 計數器",
|
||||
"Game Resolutions": "遊戲解析度",
|
||||
"Other": "其他",
|
||||
"Battery/Charger": "電池/充電器",
|
||||
"Miscellaneous": "雜項",
|
||||
"CPU Usage": "CPU 使用率",
|
||||
"GPU Usage": "GPU 使用率",
|
||||
"RAM Usage": "RAM 使用率",
|
||||
"Target Frequency": "目標頻率",
|
||||
"Real Frequency": "實際頻率",
|
||||
"Core 0 ": "核心 0 ",
|
||||
"Core 1 ": "核心 1 ",
|
||||
"Core 2 ": "核心 2 ",
|
||||
"Core 3 ": "核心 3 ",
|
||||
"Load": "負載",
|
||||
"Total\nApplication\nApplet\nSystem\nSystem Unsafe": "總計\n應用程式\n小程式\n系統\n系統(不安全)",
|
||||
"Board": "主機板",
|
||||
"Battery Power Flow": "電池功率流",
|
||||
"\nTemperatures": "\n溫度",
|
||||
"SoC\nPCB\nSkin": "SoC\nPCB\nSkin",
|
||||
"Fan Rotation Level": "風扇轉速等級",
|
||||
"Game": "遊戲",
|
||||
"PFPS ": "PFPS ",
|
||||
"FPS ": "FPS ",
|
||||
"Resolutions ": "解析度 ",
|
||||
"Read Speed ": "讀取速度 ",
|
||||
"Press ": "按 ",
|
||||
" to Exit": " 退出",
|
||||
"Depth": "深度",
|
||||
"Viewport": "視口",
|
||||
"Game is not running\nor it's incompatible.": "遊戲未執行\n或不相容。",
|
||||
"Battery Stats": "電池統計",
|
||||
"Actual Capacity": "實際容量",
|
||||
"Designed Capacity": "設計容量",
|
||||
"Temperature": "溫度",
|
||||
"Raw Charge": "原始電量",
|
||||
"Age": "壽命",
|
||||
"Voltage": "電壓",
|
||||
"Current Flow": "電流",
|
||||
"Power Flow": "功率",
|
||||
"Remaining Time": "剩餘時間",
|
||||
"Charger Stats": "充電器統計",
|
||||
"Input Current Limit": "輸入電流限制",
|
||||
"VBUS Current Limit": "VBUS 電流限制",
|
||||
"Voltage Limit": "電壓限制",
|
||||
"Current Limit": "電流限制",
|
||||
"Type": "類型",
|
||||
"Max Voltage": "最大電壓",
|
||||
"Max Current": "最大電流",
|
||||
"Multimedia Clock Rates": "多媒體時脈頻率",
|
||||
"NVDEC": "NVDEC",
|
||||
"NVENC": "NVENC",
|
||||
"NVJPG": "NVJPG",
|
||||
"Network": "網路",
|
||||
"Type: Wi-Fi": "類型:Wi-Fi",
|
||||
"Press Y to show password": "按 Y 顯示密碼",
|
||||
"Type: Ethernet": "類型:乙太網路",
|
||||
"Type: Not connected": "類型:未連線",
|
||||
"CPU\nGPU\nRAM\nSOC\nPCB\nSKN": "CPU\nGPU\nRAM\nSOC\nPCB\nSKN",
|
||||
"Elements Move Down Move Up": "元素 下移 上移",
|
||||
"Transparent": "透明",
|
||||
"Opaque": "不透明",
|
||||
"Alpha": "透明度",
|
||||
"Pretty": "美觀",
|
||||
"Compact": "緊湊",
|
||||
"FileSafe": "檔案安全",
|
||||
"Day+Time": "日期+時間",
|
||||
"Date+Time(s)": "日期+時間(秒)",
|
||||
"Date+Time AM/PM": "日期+時間 AM/PM",
|
||||
"Date+Time(s) AM/PM": "日期+時間(秒) AM/PM",
|
||||
"Date+Time EU": "日期+時間 EU",
|
||||
"Date+Time EU AM/PM": "日期+時間 EU AM/PM",
|
||||
"Date+Time(s) EU AM/PM": "日期+時間(秒) EU AM/PM",
|
||||
"Date+Time ISO": "日期+時間 ISO",
|
||||
"Time 24h": "時間 24時",
|
||||
"Time AM/PM": "時間 AM/PM",
|
||||
"Time(s) 24h": "時間(秒) 24時",
|
||||
"Time(s) AM/PM": "時間(秒) AM/PM",
|
||||
"Date US": "日期 US",
|
||||
"Date EU": "日期 EU",
|
||||
"Date ISO": "日期 ISO",
|
||||
"Date Short": "短日期",
|
||||
"DTC Format": "DTC 格式",
|
||||
"Toggles": "開關",
|
||||
"Info": "顯示資訊",
|
||||
"Disable Screenshots": "停用截圖",
|
||||
"Real Freqs": "實際頻率",
|
||||
"Deltas": "差值",
|
||||
"Target Freqs": "目標頻率",
|
||||
"FPS": "FPS",
|
||||
"RES": "解析度",
|
||||
"Read Speed": "讀取速度",
|
||||
"Real Frequencies": "實際頻率",
|
||||
"Real Voltages": "實際電壓",
|
||||
"Full CPU": "完整 CPU",
|
||||
"VDDQ": "VDDQ",
|
||||
"VDD2": "VDD2",
|
||||
"Full Resolution": "完整解析度",
|
||||
"SOC Voltage": "SOC 電壓",
|
||||
"RAM Load CPU/GPU": "RAM 負載 CPU/GPU",
|
||||
"Use DTC Symbol": "使用 DTC 符號",
|
||||
"Use Dynamic Colors": "使用動態顏色",
|
||||
"Sleep Exit": "退出睡眠",
|
||||
"Configuration": "設定",
|
||||
"Refresh Rate": "更新率",
|
||||
"Frame Padding": "畫面邊距",
|
||||
" Font Size": " 字型大小",
|
||||
"Font Sizes": "字型大小",
|
||||
"Handheld Font Size": "掌機模式字型大小",
|
||||
"Docked Font Size": "主機模式字型大小",
|
||||
"Black": "黑色",
|
||||
"Dark Gray": "深灰",
|
||||
"Gray": "灰色",
|
||||
"Light Gray": "淺灰",
|
||||
"Silver": "銀色",
|
||||
"White": "白色",
|
||||
"Dark Red": "深紅",
|
||||
"Red": "紅色",
|
||||
"Light Red": "淺紅",
|
||||
"Pink": "粉紅",
|
||||
"Dark Green": "深綠",
|
||||
"Green": "綠色",
|
||||
"Lime Green": "萊姆綠",
|
||||
"Light Green": "淺綠",
|
||||
"Dark Blue": "深藍",
|
||||
"Blue": "藍色",
|
||||
"Light Blue": "淺藍",
|
||||
"Sky Blue": "天空藍",
|
||||
"Dark Purple": "深紫",
|
||||
"Purple": "紫色",
|
||||
"Light Purple": "淺紫",
|
||||
"Violet": "紫羅蘭",
|
||||
"Orange": "橙色",
|
||||
"Yellow": "黃色",
|
||||
"Light Yellow": "淺黃",
|
||||
"Teal": "藍綠",
|
||||
"Cyan": "青色",
|
||||
"Light Cyan": "淺青",
|
||||
"Magenta": "洋紅",
|
||||
"Hot Pink": "熱粉",
|
||||
"Brown": "棕色",
|
||||
"Light Brown": "淺棕",
|
||||
"Colors": "顏色",
|
||||
"Background Color": "背景顏色",
|
||||
"Background Alpha": "背景透明度",
|
||||
"Focus Color": "焦點顏色",
|
||||
"Focus Alpha": "焦點透明度",
|
||||
"Text Color": "文字顏色",
|
||||
"Border": "邊框",
|
||||
"Dashed Line": "虛線",
|
||||
"Max FPS Text": "最大 FPS 文字",
|
||||
"Min FPS Text": "最小 FPS 文字",
|
||||
"Main Line": "主線",
|
||||
"Rounded Line": "圓角線",
|
||||
"Perfect Line": "完美線",
|
||||
" Color": " 顏色",
|
||||
" Alpha": " 透明度",
|
||||
"Category Color": "分類顏色",
|
||||
"Category Color 1": "分類顏色 1",
|
||||
"Category Color 2": "分類顏色 2",
|
||||
"Separator Color": "分隔線顏色",
|
||||
"Elements": "元素",
|
||||
"Text Alignment": "文字對齊",
|
||||
"Vertical Position": "垂直位置",
|
||||
"Horizontal Position": "水平位置",
|
||||
"Left": "左",
|
||||
"Right": "右",
|
||||
"Top": "上",
|
||||
"Center": "中",
|
||||
"Bottom": "下",
|
||||
"FPS Counter Color": "FPS 計數器顏色",
|
||||
"FPS Counter Alpha": "FPS 計數器透明度",
|
||||
"Border Color": "邊框顏色",
|
||||
"Dashed Line Color": "虛線顏色",
|
||||
"Dashed Line Alpha": "虛線透明度",
|
||||
"Max FPS Text Color": "最大 FPS 文字顏色",
|
||||
"Min FPS Text Color": "最小 FPS 文字顏色",
|
||||
"Main Line Color": "主線顏色",
|
||||
"Rounded Line Color": "圓角線顏色",
|
||||
"Perfect Line Color": "完美線顏色"
|
||||
}
|
||||
2577
Source/Horizon-OC-Monitor/source/Utils.hpp
Normal file
2577
Source/Horizon-OC-Monitor/source/Utils.hpp
Normal file
File diff suppressed because it is too large
Load Diff
35
Source/Horizon-OC-Monitor/source/audsnoop.c
Normal file
35
Source/Horizon-OC-Monitor/source/audsnoop.c
Normal file
@@ -0,0 +1,35 @@
|
||||
#define NX_SERVICE_ASSUME_NON_DOMAIN
|
||||
#include <switch.h>
|
||||
#include <service_guard.h>
|
||||
|
||||
static Service g_audsnoopSrv;
|
||||
|
||||
NX_GENERATE_SERVICE_GUARD(audsnoop);
|
||||
|
||||
Result _audsnoopInitialize(void) {
|
||||
return smGetService(&g_audsnoopSrv, "auddev");
|
||||
}
|
||||
|
||||
void _audsnoopCleanup(void) {
|
||||
serviceClose(&g_audsnoopSrv);
|
||||
}
|
||||
|
||||
Service* audsnoopGetServiceSession(void) {
|
||||
return &g_audsnoopSrv;
|
||||
}
|
||||
|
||||
Result audsnoopEnableDspUsageMeasurement(void) {
|
||||
return serviceDispatch(&g_audsnoopSrv, 0);
|
||||
}
|
||||
|
||||
Result audsnoopDisableDspUsageMeasurement(void) {
|
||||
return serviceDispatch(&g_audsnoopSrv, 1);
|
||||
}
|
||||
|
||||
Result audsnoopGetDspUsage(u32 *usage) {
|
||||
u32 tmp = 0;
|
||||
Result rc = serviceDispatchOut(&g_audsnoopSrv, 6, tmp);
|
||||
if (R_SUCCEEDED(rc) && usage)
|
||||
*usage = tmp;
|
||||
return rc;
|
||||
}
|
||||
1193
Source/Horizon-OC-Monitor/source/main.cpp
Normal file
1193
Source/Horizon-OC-Monitor/source/main.cpp
Normal file
File diff suppressed because it is too large
Load Diff
220
Source/Horizon-OC-Monitor/source/modes/Battery.hpp
Normal file
220
Source/Horizon-OC-Monitor/source/modes/Battery.hpp
Normal file
@@ -0,0 +1,220 @@
|
||||
class OtherMenu;
|
||||
|
||||
class BatteryOverlay : public tsl::Gui {
|
||||
private:
|
||||
// Separated value buffers
|
||||
char actualCapacity_c[32] = "";
|
||||
char designedCapacity_c[32] = "";
|
||||
char batteryTemp_c[32] = "";
|
||||
char rawCharge_c[32] = "";
|
||||
char batteryAge_c[32] = "";
|
||||
char voltageAvg_c[64] = "";
|
||||
char currentFlow_c[64] = "";
|
||||
char powerFlow_c[64] = "";
|
||||
char remainingTime_c[16] = "";
|
||||
char inputCurrentLimit_c[32] = "";
|
||||
char vbusCurrentLimit_c[32] = "";
|
||||
char chargeVoltageLimit_c[32] = "";
|
||||
char chargeCurrentLimit_c[32] = "";
|
||||
char chargerType_c[32] = "";
|
||||
char chargerMaxVoltage_c[32] = "";
|
||||
char chargerMaxCurrent_c[32] = "";
|
||||
|
||||
bool skipOnce = true;
|
||||
bool runOnce = true;
|
||||
bool isChargerConnected = false;
|
||||
FullSettings settings;
|
||||
public:
|
||||
BatteryOverlay() {
|
||||
GetConfigSettings(&settings);
|
||||
disableJumpTo = true;
|
||||
mutexInit(&mutex_BatteryChecker);
|
||||
StartBatteryThread();
|
||||
//tsl::elm::g_disableMenuCacheOnReturn.store(true, std::memory_order_release);
|
||||
}
|
||||
~BatteryOverlay() {
|
||||
CloseBatteryThread();
|
||||
fixForeground = true;
|
||||
}
|
||||
|
||||
virtual tsl::elm::Element* createUI() override {
|
||||
|
||||
auto* Status = new tsl::elm::CustomDrawer([this](tsl::gfx::Renderer *renderer, u16 x, u16 y, u16 w, u16 h) {
|
||||
static constexpr u16 Y_OFFSET = 40;
|
||||
static constexpr u16 X_OFFSET = 20;
|
||||
static const u16 LABEL_X = 20 + X_OFFSET;
|
||||
static const u16 VALUE_X = 240+ X_OFFSET;
|
||||
static const u16 START_Y = 155 + Y_OFFSET;
|
||||
static constexpr u16 LINE_HEIGHT = 18;
|
||||
static constexpr u8 FONT_SIZE = 18;
|
||||
static const tsl::Color LABEL_COLOR_1= settings.catColor1;
|
||||
static const tsl::Color LABEL_COLOR_2 = settings.catColor2;
|
||||
static const tsl::Color VALUE_COLOR = settings.textColor;
|
||||
|
||||
renderer->drawString("Battery Stats", false, LABEL_X, 120 + Y_OFFSET, 20, LABEL_COLOR_1);
|
||||
|
||||
u16 currentY = START_Y;
|
||||
|
||||
// Actual Capacity
|
||||
renderer->drawString("Actual Capacity", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(actualCapacity_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Designed Capacity
|
||||
renderer->drawString("Designed Capacity", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(designedCapacity_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Temperature
|
||||
renderer->drawString("Temperature", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(batteryTemp_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Raw Charge
|
||||
renderer->drawString("Raw Charge", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(rawCharge_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Age
|
||||
renderer->drawString("Age", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(batteryAge_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Voltage
|
||||
renderer->drawString("Voltage", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(voltageAvg_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Current Flow
|
||||
renderer->drawString("Current Flow", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(currentFlow_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Power Flow
|
||||
renderer->drawString("Power Flow", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(powerFlow_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Remaining Time
|
||||
renderer->drawString("Remaining Time", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(remainingTime_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Charger-specific fields (only shown when charger is connected)
|
||||
if (isChargerConnected) {
|
||||
currentY += 3*LINE_HEIGHT;
|
||||
renderer->drawString("Charger Stats", false, LABEL_X, currentY, 20, LABEL_COLOR_1);
|
||||
currentY += 2*LINE_HEIGHT;
|
||||
// Input Current Limit
|
||||
renderer->drawString("Input Current Limit", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(inputCurrentLimit_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// VBUS Current Limit
|
||||
renderer->drawString("VBUS Current Limit", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(vbusCurrentLimit_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Charge Voltage Limit
|
||||
renderer->drawString("Voltage Limit", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(chargeVoltageLimit_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Charge Current Limit
|
||||
renderer->drawString("Current Limit", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(chargeCurrentLimit_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Charger Type
|
||||
renderer->drawString("Type", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(chargerType_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Charger Max Voltage
|
||||
renderer->drawString("Max Voltage", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(chargerMaxVoltage_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
currentY += LINE_HEIGHT;
|
||||
|
||||
// Charger Max Current
|
||||
renderer->drawString("Max Current", false, LABEL_X, currentY, FONT_SIZE, LABEL_COLOR_2);
|
||||
renderer->drawString(chargerMaxCurrent_c, false, VALUE_X, currentY, FONT_SIZE, VALUE_COLOR);
|
||||
}
|
||||
});
|
||||
|
||||
//tsl::elm::g_disableMenuCacheOnReturn.store(true, std::memory_order_release);
|
||||
tsl::elm::HeaderOverlayFrame* rootFrame = new tsl::elm::HeaderOverlayFrame("Status Monitor", APP_VERSION, true);
|
||||
rootFrame->setContent(Status);
|
||||
|
||||
return rootFrame;
|
||||
}
|
||||
|
||||
virtual void update() override {
|
||||
mutexLock(&mutex_BatteryChecker);
|
||||
|
||||
char tempBatTimeEstimate[8] = "--:--";
|
||||
if (batTimeEstimate >= 0) {
|
||||
snprintf(tempBatTimeEstimate, sizeof(tempBatTimeEstimate), "%d:%02d", batTimeEstimate / 60, batTimeEstimate % 60);
|
||||
}
|
||||
|
||||
const BatteryChargeInfoFieldsChargerType ChargerConnected = hosversionAtLeast(17,0,0) ?
|
||||
((BatteryChargeInfoFields17*)&_batteryChargeInfoFields)->ChargerType :
|
||||
_batteryChargeInfoFields.ChargerType;
|
||||
const int32_t ChargerVoltageLimit = hosversionAtLeast(17,0,0) ?
|
||||
((BatteryChargeInfoFields17*)&_batteryChargeInfoFields)->ChargerVoltageLimit :
|
||||
_batteryChargeInfoFields.ChargerVoltageLimit;
|
||||
const int32_t ChargerCurrentLimit = hosversionAtLeast(17,0,0) ?
|
||||
((BatteryChargeInfoFields17*)&_batteryChargeInfoFields)->ChargerCurrentLimit :
|
||||
_batteryChargeInfoFields.ChargerCurrentLimit;
|
||||
|
||||
isChargerConnected = (ChargerConnected != 0);
|
||||
|
||||
// Format all values
|
||||
snprintf(actualCapacity_c, sizeof(actualCapacity_c), "%.0f mAh", actualFullBatCapacity);
|
||||
snprintf(designedCapacity_c, sizeof(designedCapacity_c), "%.0f mAh", designedFullBatCapacity);
|
||||
snprintf(batteryTemp_c, sizeof(batteryTemp_c), "%.1f\u00B0C", (float)_batteryChargeInfoFields.BatteryTemperature / 1000);
|
||||
snprintf(rawCharge_c, sizeof(rawCharge_c), "%.1f%%", (float)_batteryChargeInfoFields.RawBatteryCharge / 1000);
|
||||
snprintf(batteryAge_c, sizeof(batteryAge_c), "%.1f%%", (float)_batteryChargeInfoFields.BatteryAge / 1000);
|
||||
snprintf(voltageAvg_c, sizeof(voltageAvg_c), "%.0f mV (%ds)", batVoltageAvg, batteryFiltered ? 45 : 5);
|
||||
snprintf(currentFlow_c, sizeof(currentFlow_c), "%+.0f mA (%ss)", batCurrentAvg, batteryFiltered ? "11.25" : "5");
|
||||
snprintf(powerFlow_c, sizeof(powerFlow_c), "%+.3f W%s", PowerConsumption, batteryFiltered ? "" : " (5s)");
|
||||
snprintf(remainingTime_c, sizeof(remainingTime_c), "%s", tempBatTimeEstimate);
|
||||
|
||||
if (isChargerConnected) {
|
||||
snprintf(inputCurrentLimit_c, sizeof(inputCurrentLimit_c), "%d mA", _batteryChargeInfoFields.InputCurrentLimit);
|
||||
snprintf(vbusCurrentLimit_c, sizeof(vbusCurrentLimit_c), "%d mA", _batteryChargeInfoFields.VBUSCurrentLimit);
|
||||
snprintf(chargeVoltageLimit_c, sizeof(chargeVoltageLimit_c), "%d mV", _batteryChargeInfoFields.ChargeVoltageLimit);
|
||||
snprintf(chargeCurrentLimit_c, sizeof(chargeCurrentLimit_c), "%d mA", _batteryChargeInfoFields.ChargeCurrentLimit);
|
||||
snprintf(chargerType_c, sizeof(chargerType_c), "%u", ChargerConnected);
|
||||
snprintf(chargerMaxVoltage_c, sizeof(chargerMaxVoltage_c), "%u mV", ChargerVoltageLimit);
|
||||
snprintf(chargerMaxCurrent_c, sizeof(chargerMaxCurrent_c), "%u mA", ChargerCurrentLimit);
|
||||
}
|
||||
|
||||
mutexUnlock(&mutex_BatteryChecker);
|
||||
|
||||
if (!skipOnce) {
|
||||
if (runOnce) {
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
runOnce = false;
|
||||
}
|
||||
} else {
|
||||
skipOnce = false;
|
||||
}
|
||||
}
|
||||
|
||||
virtual bool handleInput(uint64_t keysDown, uint64_t keysHeld, touchPosition touchInput, JoystickPosition leftJoyStick, JoystickPosition rightJoyStick) override {
|
||||
if (keysDown & KEY_B) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerExitSound.store(true, std::memory_order_release);
|
||||
skipOnce = true;
|
||||
runOnce = true;
|
||||
lastSelectedItem = "Battery/Charger";
|
||||
lastMode = "";
|
||||
tsl::swapTo<OtherMenu>();
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
};
|
||||
2215
Source/Horizon-OC-Monitor/source/modes/Configurator.hpp
Normal file
2215
Source/Horizon-OC-Monitor/source/modes/Configurator.hpp
Normal file
File diff suppressed because it is too large
Load Diff
525
Source/Horizon-OC-Monitor/source/modes/FPS_Counter.hpp
Normal file
525
Source/Horizon-OC-Monitor/source/modes/FPS_Counter.hpp
Normal file
@@ -0,0 +1,525 @@
|
||||
class MainMenu;
|
||||
|
||||
class com_FPS : public tsl::Gui {
|
||||
private:
|
||||
char FPSavg_c[8];
|
||||
FpsCounterSettings settings;
|
||||
size_t fontsize = 0;
|
||||
ApmPerformanceMode performanceMode = ApmPerformanceMode_Invalid;
|
||||
bool skipOnce = true;
|
||||
bool runOnce = true;
|
||||
|
||||
// Repositioning variables
|
||||
int frameOffsetX = 0;
|
||||
int frameOffsetY = 0;
|
||||
bool isDragging = false;
|
||||
size_t framePadding = 10;
|
||||
static constexpr int screenWidth = 1280;
|
||||
static constexpr int screenHeight = 720;
|
||||
static constexpr int border = 8;
|
||||
|
||||
bool originalUseRightAlignment = ult::useRightAlignment;
|
||||
|
||||
struct ButtonState {
|
||||
std::atomic<bool> minusDragActive{false};
|
||||
std::atomic<bool> plusDragActive{false};
|
||||
} buttonState;
|
||||
|
||||
Thread touchPollThread;
|
||||
std::atomic<bool> touchPollRunning{false};
|
||||
|
||||
// Store actual rendered dimensions
|
||||
size_t actualTextWidth = 0;
|
||||
size_t actualTotalWidth = 0;
|
||||
size_t actualTotalHeight = 0;
|
||||
|
||||
public:
|
||||
com_FPS() {
|
||||
tsl::hlp::requestForeground(false);
|
||||
disableJumpTo = true;
|
||||
GetConfigSettings(&settings);
|
||||
apmGetPerformanceMode(&performanceMode);
|
||||
if (performanceMode == ApmPerformanceMode_Normal) {
|
||||
fontsize = settings.handheldFontSize;
|
||||
}
|
||||
else if (performanceMode == ApmPerformanceMode_Boost) {
|
||||
fontsize = settings.dockedFontSize;
|
||||
}
|
||||
|
||||
// Load saved frame offsets
|
||||
frameOffsetX = settings.frameOffsetX;
|
||||
frameOffsetY = settings.frameOffsetY;
|
||||
framePadding = settings.framePadding;
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
|
||||
FullMode = false;
|
||||
TeslaFPS = settings.refreshRate;
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().removeScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = true;
|
||||
StartFPSCounterThread();
|
||||
|
||||
// Start touch polling thread for instant response at low FPS
|
||||
touchPollRunning.store(true, std::memory_order_release);
|
||||
threadCreate(&touchPollThread, [](void* arg) -> void {
|
||||
com_FPS* overlay = static_cast<com_FPS*>(arg);
|
||||
|
||||
// Allow only Player 1 and handheld mode
|
||||
const HidNpadIdType id_list[2] = { HidNpadIdType_No1, HidNpadIdType_Handheld };
|
||||
|
||||
// Configure HID system to only listen to these IDs
|
||||
hidSetSupportedNpadIdType(id_list, 2);
|
||||
|
||||
// Configure input for up to 2 supported controllers (P1 + Handheld)
|
||||
padConfigureInput(2, HidNpadStyleSet_NpadStandard | HidNpadStyleTag_NpadSystemExt);
|
||||
|
||||
// Initialize separate pad states for both controllers
|
||||
PadState pad_p1;
|
||||
PadState pad_handheld;
|
||||
padInitialize(&pad_p1, HidNpadIdType_No1);
|
||||
padInitialize(&pad_handheld, HidNpadIdType_Handheld);
|
||||
|
||||
u64 minusHoldStart = 0;
|
||||
u64 plusHoldStart = 0;
|
||||
static constexpr u64 HOLD_THRESHOLD_NS = 500'000'000ULL;
|
||||
|
||||
HidTouchScreenState state = {0};
|
||||
bool inputDetected;
|
||||
|
||||
while (overlay->touchPollRunning.load(std::memory_order_acquire)) {
|
||||
// Only poll when rendering and not dragging
|
||||
{
|
||||
inputDetected = false;
|
||||
|
||||
// Check touch in bounds
|
||||
if (hidGetTouchScreenStates(&state, 1) && state.count > 0) {
|
||||
const int touchX = state.touches[0].x;
|
||||
const int touchY = state.touches[0].y;
|
||||
|
||||
// Use actual dimensions, fallback to estimate if not yet rendered
|
||||
size_t totalWidth = overlay->actualTotalWidth;
|
||||
size_t totalHeight = overlay->actualTotalHeight;
|
||||
|
||||
if (totalWidth == 0) {
|
||||
// Fallback calculation
|
||||
size_t approxFontSize = overlay->fontsize;
|
||||
if (approxFontSize == 0) approxFontSize = 50;
|
||||
const size_t textWidth = approxFontSize * 4;
|
||||
const size_t margin = (approxFontSize / 8);
|
||||
const size_t innerWidth = textWidth + margin;
|
||||
const size_t innerHeight = approxFontSize;
|
||||
totalWidth = innerWidth + (2 * border);
|
||||
totalHeight = innerHeight + (2 * border);
|
||||
}
|
||||
|
||||
// Apply frame offsets
|
||||
const int overlayX = overlay->frameOffsetX;
|
||||
const int overlayY = overlay->frameOffsetY;
|
||||
|
||||
// Touch padding
|
||||
const int touchPadding = 4;
|
||||
const int touchableX = overlayX - touchPadding;
|
||||
const int touchableY = overlayY - touchPadding;
|
||||
const int touchableWidth = totalWidth + (touchPadding * 2);
|
||||
const int touchableHeight = totalHeight + (touchPadding * 2);
|
||||
|
||||
// Check if touch is within bounds
|
||||
if (touchX >= touchableX && touchX <= touchableX + touchableWidth &&
|
||||
touchY >= touchableY && touchY <= touchableY + touchableHeight) {
|
||||
inputDetected = true;
|
||||
}
|
||||
}
|
||||
|
||||
// Poll buttons from both controllers
|
||||
padUpdate(&pad_p1);
|
||||
padUpdate(&pad_handheld);
|
||||
|
||||
// Combine input from both controllers
|
||||
const u64 keysHeld = padGetButtons(&pad_p1) | padGetButtons(&pad_handheld);
|
||||
const u64 now = armTicksToNs(armGetSystemTick());
|
||||
|
||||
// Track MINUS hold duration
|
||||
if ((keysHeld & KEY_MINUS) && !(keysHeld & ~KEY_MINUS & ALL_KEYS_MASK)) {
|
||||
if (minusHoldStart == 0) {
|
||||
minusHoldStart = now;
|
||||
}
|
||||
if (now - minusHoldStart >= HOLD_THRESHOLD_NS) {
|
||||
inputDetected = true;
|
||||
overlay->buttonState.minusDragActive.exchange(true, std::memory_order_acq_rel);
|
||||
}
|
||||
}
|
||||
|
||||
// Track PLUS hold duration
|
||||
else if ((keysHeld & KEY_PLUS) && !(keysHeld & ~KEY_PLUS & ALL_KEYS_MASK)) {
|
||||
if (plusHoldStart == 0) {
|
||||
plusHoldStart = now;
|
||||
}
|
||||
if (now - plusHoldStart >= HOLD_THRESHOLD_NS) {
|
||||
inputDetected = true;
|
||||
overlay->buttonState.plusDragActive.exchange(true, std::memory_order_acq_rel);
|
||||
}
|
||||
}
|
||||
|
||||
else {
|
||||
minusHoldStart = plusHoldStart = 0;
|
||||
overlay->buttonState.minusDragActive.exchange(false, std::memory_order_acq_rel);
|
||||
overlay->buttonState.plusDragActive.exchange(false, std::memory_order_acq_rel);
|
||||
}
|
||||
|
||||
// Disable rendering on any input, re-enable when no input
|
||||
static bool resetOnce = true;
|
||||
if (inputDetected) {
|
||||
if (resetOnce && isRendering) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
resetOnce = false;
|
||||
}
|
||||
} else {
|
||||
resetOnce = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
static auto lastUnderscanPixels = std::make_pair(0, 0);
|
||||
|
||||
if (lastUnderscanPixels != tsl::impl::currentUnderscanPixels) {
|
||||
for (int i = 0; i < 2; i++) {
|
||||
tsl::gfx::Renderer::get().updateLayerSize();
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(overlay->frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
}
|
||||
lastUnderscanPixels = tsl::impl::currentUnderscanPixels;
|
||||
}
|
||||
|
||||
svcSleepThread(16000000ULL*2); // 16ms polling
|
||||
}
|
||||
}, this, NULL, 0x1000, 0x2B, -2);
|
||||
threadStart(&touchPollThread);
|
||||
}
|
||||
|
||||
~com_FPS() {
|
||||
// Stop touch polling thread
|
||||
touchPollRunning.store(false, std::memory_order_release);
|
||||
threadWaitForExit(&touchPollThread);
|
||||
threadClose(&touchPollThread);
|
||||
|
||||
TeslaFPS = 60;
|
||||
EndFPSCounterThread();
|
||||
FullMode = true;
|
||||
fixForeground = true;
|
||||
ult::useRightAlignment = originalUseRightAlignment;
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().addScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = false;
|
||||
}
|
||||
|
||||
virtual tsl::elm::Element* createUI() override {
|
||||
|
||||
auto* Status = new tsl::elm::CustomDrawer([this](tsl::gfx::Renderer *renderer, u16 x, u16 y, u16 w, u16 h) {
|
||||
// Calculate text dimensions
|
||||
const auto [textWidth, textHeight] = renderer->getTextDimensions(
|
||||
(FPSavg != 254.0) ? FPSavg_c : "--", false, fontsize
|
||||
);
|
||||
|
||||
const size_t margin = (fontsize / 8);
|
||||
|
||||
// Inner rectangle dimensions (content area)
|
||||
const size_t innerWidth = textWidth + margin;
|
||||
const size_t innerHeight = textHeight;
|
||||
|
||||
// Total dimensions including border
|
||||
const size_t totalWidth = innerWidth + (2 * border);
|
||||
const size_t totalHeight = innerHeight + (2 * border);
|
||||
|
||||
// Store actual dimensions for input handling
|
||||
actualTextWidth = textWidth;
|
||||
actualTotalWidth = totalWidth;
|
||||
actualTotalHeight = totalHeight;
|
||||
|
||||
// Calculate position with frame offsets
|
||||
//int posX = frameOffsetX;
|
||||
//int posY = frameOffsetY;
|
||||
|
||||
int _frameOffsetX = ult::limitedMemory ? std::max(0, frameOffsetX - (1280-448)) : frameOffsetX;
|
||||
|
||||
// Clamp to screen bounds (accounting for total size including border)
|
||||
const int posX = std::max(int(framePadding), std::min(_frameOffsetX, static_cast<int>(screenWidth - totalWidth - framePadding)));
|
||||
const int posY = std::max(int(framePadding), std::min(frameOffsetY, static_cast<int>(screenHeight - totalHeight - framePadding)));
|
||||
|
||||
// Draw the rounded rectangle (background)
|
||||
const tsl::Color bgColor = !isDragging
|
||||
? settings.backgroundColor
|
||||
: settings.focusBackgroundColor;
|
||||
|
||||
renderer->drawRoundedRectSingleThreaded(
|
||||
posX,
|
||||
posY,
|
||||
totalWidth,
|
||||
totalHeight,
|
||||
16,
|
||||
aWithOpacity(bgColor)
|
||||
);
|
||||
|
||||
// Calculate centered text position within the bordered area
|
||||
const int textX = posX + border + (margin / 2);
|
||||
const int textY = posY + border + (fontsize - margin);
|
||||
|
||||
// Draw the text
|
||||
renderer->drawString(
|
||||
(FPSavg != 254.0) ? FPSavg_c : "--",
|
||||
false,
|
||||
textX,
|
||||
textY,
|
||||
fontsize,
|
||||
settings.textColor
|
||||
);
|
||||
});
|
||||
|
||||
tsl::elm::HeaderOverlayFrame* rootFrame = new tsl::elm::HeaderOverlayFrame("", "");
|
||||
rootFrame->setContent(Status);
|
||||
|
||||
return rootFrame;
|
||||
}
|
||||
|
||||
virtual void update() override {
|
||||
apmGetPerformanceMode(&performanceMode);
|
||||
if (performanceMode == ApmPerformanceMode_Normal) {
|
||||
fontsize = settings.handheldFontSize;
|
||||
}
|
||||
else if (performanceMode == ApmPerformanceMode_Boost) {
|
||||
fontsize = settings.dockedFontSize;
|
||||
}
|
||||
if (settings.useIntegerCounter) {
|
||||
snprintf(FPSavg_c, sizeof FPSavg_c, "%d", (int)round(useOldFPSavg ? FPSavg_old : FPSavg));
|
||||
} else {
|
||||
snprintf(FPSavg_c, sizeof FPSavg_c, "%2.1f", useOldFPSavg ? FPSavg_old : FPSavg);
|
||||
}
|
||||
|
||||
if (!skipOnce) {
|
||||
if (runOnce) {
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
runOnce = false;
|
||||
}
|
||||
} else {
|
||||
skipOnce = false;
|
||||
}
|
||||
}
|
||||
|
||||
virtual bool handleInput(u64 keysDown, u64 keysHeld, const HidTouchState &touchPos, HidAnalogStickState joyStickPosLeft, HidAnalogStickState joyStickPosRight) override {
|
||||
// Static variables to maintain drag state between function calls
|
||||
static bool oldTouchDetected = false;
|
||||
static bool oldMinusHeld = false;
|
||||
static bool oldPlusHeld = false;
|
||||
static HidTouchState initialTouchPos = {0};
|
||||
static int initialFrameOffsetX = 0;
|
||||
static int initialFrameOffsetY = 0;
|
||||
static constexpr int TOUCH_THRESHOLD = 8;
|
||||
static bool hasMoved = false;
|
||||
|
||||
// Touch detection
|
||||
const bool currentTouchDetected = (touchPos.x > 0 && touchPos.y > 0 &&
|
||||
touchPos.x < screenWidth && touchPos.y < screenHeight);
|
||||
|
||||
static bool clearOnRelease = false;
|
||||
|
||||
if (clearOnRelease && !isRendering) {
|
||||
clearOnRelease = false;
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
}
|
||||
|
||||
// Use actual dimensions from last render, fallback to estimate if not available
|
||||
size_t totalWidth = actualTotalWidth;
|
||||
size_t totalHeight = actualTotalHeight;
|
||||
|
||||
if (totalWidth == 0) {
|
||||
// Fallback calculation if not yet rendered
|
||||
const size_t textWidth = fontsize * 4;
|
||||
const size_t margin = (fontsize / 8);
|
||||
const size_t innerWidth = textWidth + margin;
|
||||
const size_t innerHeight = fontsize + (margin / 2);
|
||||
totalWidth = innerWidth + (2 * border);
|
||||
totalHeight = innerHeight + (2 * border);
|
||||
}
|
||||
|
||||
// Current overlay position
|
||||
const int overlayX = frameOffsetX;
|
||||
const int overlayY = frameOffsetY;
|
||||
|
||||
// Touch detection area (with padding for easier interaction)
|
||||
static constexpr int touchPadding = 4;
|
||||
const int touchableX = overlayX - touchPadding;
|
||||
const int touchableY = overlayY - touchPadding;
|
||||
const int touchableWidth = totalWidth + (touchPadding * 2);
|
||||
const int touchableHeight = totalHeight + (touchPadding * 2);
|
||||
|
||||
// Screen boundaries for clamping (accounting for total size)
|
||||
const int minX = framePadding;
|
||||
const int maxX = screenWidth - totalWidth - framePadding;
|
||||
const int minY = framePadding;
|
||||
const int maxY = screenHeight - totalHeight - framePadding;
|
||||
|
||||
const bool minusDragReady = buttonState.minusDragActive.load(std::memory_order_acquire);
|
||||
const bool plusDragReady = buttonState.plusDragActive.load(std::memory_order_acquire);
|
||||
|
||||
// Check button states
|
||||
const bool currentMinusHeld = (keysHeld & KEY_MINUS) && !(keysHeld & ~KEY_MINUS & ALL_KEYS_MASK) && minusDragReady;
|
||||
const bool currentPlusHeld = (keysHeld & KEY_PLUS) && !(keysHeld & ~KEY_PLUS & ALL_KEYS_MASK) && plusDragReady;
|
||||
|
||||
// Handle touch dragging
|
||||
if (currentTouchDetected && !isDragging) {
|
||||
const int touchX = touchPos.x;
|
||||
const int touchY = touchPos.y;
|
||||
|
||||
if (!oldTouchDetected) {
|
||||
// Touch just started - check if within overlay bounds
|
||||
if (touchX >= touchableX && touchX <= touchableX + touchableWidth &&
|
||||
touchY >= touchableY && touchY <= touchableY + touchableHeight) {
|
||||
|
||||
// Start touch dragging
|
||||
isDragging = true;
|
||||
triggerRumbleClick.store(true, std::memory_order_release);
|
||||
triggerOnSound.store(true, std::memory_order_release);
|
||||
hasMoved = false;
|
||||
initialTouchPos = touchPos;
|
||||
initialFrameOffsetX = frameOffsetX;
|
||||
initialFrameOffsetY = frameOffsetY;
|
||||
}
|
||||
}
|
||||
} else if (currentTouchDetected && isDragging && !currentMinusHeld && !currentPlusHeld) {
|
||||
// Continue touch dragging
|
||||
const int touchX = touchPos.x;
|
||||
const int touchY = touchPos.y;
|
||||
const int deltaX = touchX - initialTouchPos.x;
|
||||
const int deltaY = touchY - initialTouchPos.y;
|
||||
|
||||
// Check if we've moved enough to consider this a drag
|
||||
if (!hasMoved) {
|
||||
const int totalMovement = abs(deltaX) + abs(deltaY);
|
||||
if (totalMovement >= TOUCH_THRESHOLD) {
|
||||
hasMoved = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (hasMoved) {
|
||||
// Update frame offsets with boundary checking
|
||||
frameOffsetX = std::max(minX, std::min(maxX, initialFrameOffsetX + deltaX));
|
||||
frameOffsetY = std::max(minY, std::min(maxY, initialFrameOffsetY + deltaY));
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
}
|
||||
} else if (!currentTouchDetected && oldTouchDetected && isDragging && !currentMinusHeld && !currentPlusHeld) {
|
||||
// Touch just released
|
||||
if (hasMoved) {
|
||||
// Save position when touch drag ends
|
||||
auto iniData = ult::getParsedDataFromIniFile(configIniPath);
|
||||
iniData["fps-counter"]["frame_offset_x"] = std::to_string(frameOffsetX);
|
||||
iniData["fps-counter"]["frame_offset_y"] = std::to_string(frameOffsetY);
|
||||
ult::saveIniFileData(configIniPath, iniData);
|
||||
}
|
||||
|
||||
// Reset touch drag state
|
||||
isDragging = false;
|
||||
hasMoved = false;
|
||||
clearOnRelease = true;
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerOffSound.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
// Handle joystick dragging (MINUS + right joystick OR PLUS + left joystick)
|
||||
if ((currentMinusHeld || currentPlusHeld) && !isDragging) {
|
||||
// Start joystick dragging
|
||||
isDragging = true;
|
||||
triggerRumbleClick.store(true, std::memory_order_release);
|
||||
triggerOnSound.store(true, std::memory_order_release);
|
||||
} else if ((currentMinusHeld || currentPlusHeld) && isDragging) {
|
||||
// Continue joystick dragging
|
||||
static constexpr int JOYSTICK_DEADZONE = 20;
|
||||
|
||||
// Choose the appropriate joystick based on which button is held
|
||||
const HidAnalogStickState& activeJoystick = currentMinusHeld ? joyStickPosRight : joyStickPosLeft;
|
||||
|
||||
// Only move if joystick is outside deadzone
|
||||
if (abs(activeJoystick.x) > JOYSTICK_DEADZONE || abs(activeJoystick.y) > JOYSTICK_DEADZONE) {
|
||||
// Calculate joystick magnitude
|
||||
const float magnitude = sqrt((float)(activeJoystick.x * activeJoystick.x + activeJoystick.y * activeJoystick.y));
|
||||
const float normalizedMagnitude = magnitude / 32767.0f;
|
||||
|
||||
// Smooth curve for sensitivity
|
||||
static constexpr float baseSensitivity = 0.00008f;
|
||||
static constexpr float maxSensitivity = 0.0005f;
|
||||
|
||||
const float curveValue = pow(normalizedMagnitude, 8.0f);
|
||||
const float currentSensitivity = baseSensitivity + (maxSensitivity - baseSensitivity) * curveValue;
|
||||
|
||||
// Calculate movement delta with fractional accumulation
|
||||
static float accumulatedX = 0.0f;
|
||||
static float accumulatedY = 0.0f;
|
||||
|
||||
accumulatedX += (float)activeJoystick.x * currentSensitivity;
|
||||
accumulatedY += -(float)activeJoystick.y * currentSensitivity;
|
||||
|
||||
const int deltaX = (int)accumulatedX;
|
||||
const int deltaY = (int)accumulatedY;
|
||||
accumulatedX -= deltaX;
|
||||
accumulatedY -= deltaY;
|
||||
|
||||
// Update frame offsets with boundary checking
|
||||
frameOffsetX = std::max(minX, std::min(maxX, frameOffsetX + deltaX));
|
||||
frameOffsetY = std::max(minY, std::min(maxY, frameOffsetY + deltaY));
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
}
|
||||
} else if (((!currentMinusHeld && oldMinusHeld) || (!currentPlusHeld && oldPlusHeld)) && isDragging) {
|
||||
// Button just released - stop joystick dragging
|
||||
auto iniData = ult::getParsedDataFromIniFile(configIniPath);
|
||||
iniData["fps-counter"]["frame_offset_x"] = std::to_string(frameOffsetX);
|
||||
iniData["fps-counter"]["frame_offset_y"] = std::to_string(frameOffsetY);
|
||||
ult::saveIniFileData(configIniPath, iniData);
|
||||
isDragging = false;
|
||||
clearOnRelease = true;
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerOffSound.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
// Update state for next frame
|
||||
oldTouchDetected = currentTouchDetected;
|
||||
oldMinusHeld = currentMinusHeld;
|
||||
oldPlusHeld = currentPlusHeld;
|
||||
|
||||
// Handle existing key input logic (but don't interfere with dragging)
|
||||
if (!isDragging) {
|
||||
if (isKeyComboPressed(keysHeld, keysDown)) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
runOnce = true;
|
||||
skipOnce = true;
|
||||
TeslaFPS = 60;
|
||||
lastSelectedItem = "FPS Counter";
|
||||
lastMode = "";
|
||||
if (skipMain) {
|
||||
lastMode = "return";
|
||||
tsl::goBack();
|
||||
}
|
||||
else {
|
||||
tsl::setNextOverlay(filepath.c_str(), "--lastSelectedItem 'FPS Counter'");
|
||||
tsl::Overlay::get()->close();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// Return true if we handled the input (during dragging)
|
||||
return isDragging;
|
||||
}
|
||||
};
|
||||
726
Source/Horizon-OC-Monitor/source/modes/FPS_Graph.hpp
Normal file
726
Source/Horizon-OC-Monitor/source/modes/FPS_Graph.hpp
Normal file
@@ -0,0 +1,726 @@
|
||||
class MainMenu;
|
||||
|
||||
class com_FPSGraph : public tsl::Gui {
|
||||
private:
|
||||
uint8_t refreshRate = 0;
|
||||
char FPSavg_c[8];
|
||||
FpsGraphSettings settings;
|
||||
uint64_t systemtickfrequency_impl = systemtickfrequency;
|
||||
uint32_t cnt = 0;
|
||||
char CPU_Load_c[12] = " -";
|
||||
char GPU_Load_c[12] = " -";
|
||||
char RAM_Load_c[12] = " -";
|
||||
char SOC_TEMP_c[12] = " -";
|
||||
char PCB_TEMP_c[12] = " -";
|
||||
char SKIN_TEMP_c[12] = " -";
|
||||
bool skipOnce = true;
|
||||
bool runOnce = true;
|
||||
|
||||
// Repositioning variables (matching Mini)
|
||||
int frameOffsetX = 0;
|
||||
int frameOffsetY = 0;
|
||||
bool isDragging = false;
|
||||
size_t framePadding = 10;
|
||||
static constexpr int screenWidth = 1280;
|
||||
static constexpr int screenHeight = 720;
|
||||
static constexpr int border = 8;
|
||||
|
||||
bool originalUseRightAlignment = ult::useRightAlignment;
|
||||
|
||||
struct ButtonState {
|
||||
std::atomic<bool> minusDragActive{false};
|
||||
std::atomic<bool> plusDragActive{false};
|
||||
} buttonState;
|
||||
|
||||
Thread touchPollThread;
|
||||
std::atomic<bool> touchPollRunning{false};
|
||||
|
||||
// Store actual rendered dimensions (including border)
|
||||
size_t actualTotalWidth = 0;
|
||||
size_t actualTotalHeight = 0;
|
||||
|
||||
public:
|
||||
bool isStarted = false;
|
||||
com_FPSGraph() {
|
||||
tsl::hlp::requestForeground(false);
|
||||
disableJumpTo = true;
|
||||
GetConfigSettings(&settings);
|
||||
|
||||
if (R_SUCCEEDED(SaltySD_Connect())) {
|
||||
if (R_FAILED(SaltySD_GetDisplayRefreshRate(&refreshRate)))
|
||||
refreshRate = 0;
|
||||
svcSleepThread(100'000);
|
||||
SaltySD_Term();
|
||||
}
|
||||
|
||||
// Load saved frame offsets
|
||||
frameOffsetX = settings.frameOffsetX;
|
||||
frameOffsetY = settings.frameOffsetY;
|
||||
framePadding = settings.framePadding;
|
||||
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
|
||||
FullMode = false;
|
||||
TeslaFPS = settings.refreshRate;
|
||||
systemtickfrequency_impl /= settings.refreshRate;
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().removeScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = true;
|
||||
mutexInit(&mutex_Misc);
|
||||
StartInfoThread();
|
||||
StartFPSCounterThread();
|
||||
|
||||
// Start touch polling thread for instant response at low FPS
|
||||
touchPollRunning.store(true, std::memory_order_release);
|
||||
threadCreate(&touchPollThread, [](void* arg) -> void {
|
||||
com_FPSGraph* overlay = static_cast<com_FPSGraph*>(arg);
|
||||
|
||||
// Allow only Player 1 and handheld mode
|
||||
const HidNpadIdType id_list[2] = { HidNpadIdType_No1, HidNpadIdType_Handheld };
|
||||
|
||||
// Configure HID system to only listen to these IDs
|
||||
hidSetSupportedNpadIdType(id_list, 2);
|
||||
|
||||
// Configure input for up to 2 supported controllers (P1 + Handheld)
|
||||
padConfigureInput(2, HidNpadStyleSet_NpadStandard | HidNpadStyleTag_NpadSystemExt);
|
||||
|
||||
// Initialize separate pad states for both controllers
|
||||
PadState pad_p1;
|
||||
PadState pad_handheld;
|
||||
padInitialize(&pad_p1, HidNpadIdType_No1);
|
||||
padInitialize(&pad_handheld, HidNpadIdType_Handheld);
|
||||
|
||||
u64 minusHoldStart = 0;
|
||||
u64 plusHoldStart = 0;
|
||||
static constexpr u64 HOLD_THRESHOLD_NS = 500'000'000ULL;
|
||||
|
||||
HidTouchScreenState state = {0};
|
||||
bool inputDetected;
|
||||
|
||||
while (overlay->touchPollRunning.load(std::memory_order_acquire)) {
|
||||
// Only poll when rendering and not dragging
|
||||
{
|
||||
inputDetected = false;
|
||||
|
||||
// Check touch in bounds
|
||||
if (hidGetTouchScreenStates(&state, 1) && state.count > 0) {
|
||||
const int touchX = state.touches[0].x;
|
||||
const int touchY = state.touches[0].y;
|
||||
|
||||
// Use actual dimensions, fallback to estimate if not yet rendered
|
||||
size_t totalWidth = overlay->actualTotalWidth;
|
||||
size_t totalHeight = overlay->actualTotalHeight;
|
||||
|
||||
if (totalWidth == 0) {
|
||||
// Fallback calculation
|
||||
const s16 refresh_rate_offset = (overlay->refreshRate < 100) ? 21 : 28;
|
||||
const s16 info_width = overlay->settings.showInfo ? (6 + overlay->rectangle_width/2 - 4) : 0;
|
||||
const s16 content_width = overlay->rectangle_width + refresh_rate_offset + info_width;
|
||||
const s16 content_height = overlay->rectangle_height + 12;
|
||||
totalWidth = content_width + (2 * border);
|
||||
totalHeight = content_height + (2 * border);
|
||||
}
|
||||
|
||||
// Apply frame offsets (base position already includes border offset)
|
||||
const int overlayX = overlay->base_x + overlay->frameOffsetX - border;
|
||||
const int overlayY = overlay->base_y + overlay->frameOffsetY - border;
|
||||
|
||||
// Touch padding
|
||||
const int touchPadding = 4;
|
||||
const int touchableX = overlayX - touchPadding;
|
||||
const int touchableY = overlayY - touchPadding;
|
||||
const int touchableWidth = totalWidth + (touchPadding * 2);
|
||||
const int touchableHeight = totalHeight + (touchPadding * 2);
|
||||
|
||||
// Check if touch is within bounds
|
||||
if (touchX >= touchableX && touchX <= touchableX + touchableWidth &&
|
||||
touchY >= touchableY && touchY <= touchableY + touchableHeight) {
|
||||
inputDetected = true;
|
||||
}
|
||||
}
|
||||
|
||||
// Poll buttons from both controllers
|
||||
padUpdate(&pad_p1);
|
||||
padUpdate(&pad_handheld);
|
||||
|
||||
// Combine input from both controllers
|
||||
const u64 keysHeld = padGetButtons(&pad_p1) | padGetButtons(&pad_handheld);
|
||||
const u64 now = armTicksToNs(armGetSystemTick());
|
||||
|
||||
// Track MINUS hold duration
|
||||
if ((keysHeld & KEY_MINUS) && !(keysHeld & ~KEY_MINUS & ALL_KEYS_MASK)) {
|
||||
if (minusHoldStart == 0) {
|
||||
minusHoldStart = now;
|
||||
}
|
||||
if (now - minusHoldStart >= HOLD_THRESHOLD_NS) {
|
||||
inputDetected = true;
|
||||
overlay->buttonState.minusDragActive.exchange(true, std::memory_order_acq_rel);
|
||||
}
|
||||
}
|
||||
|
||||
// Track PLUS hold duration
|
||||
else if ((keysHeld & KEY_PLUS) && !(keysHeld & ~KEY_PLUS & ALL_KEYS_MASK)) {
|
||||
if (plusHoldStart == 0) {
|
||||
plusHoldStart = now;
|
||||
}
|
||||
if (now - plusHoldStart >= HOLD_THRESHOLD_NS) {
|
||||
inputDetected = true;
|
||||
overlay->buttonState.plusDragActive.exchange(true, std::memory_order_acq_rel);
|
||||
}
|
||||
}
|
||||
|
||||
else {
|
||||
minusHoldStart = plusHoldStart = 0;
|
||||
overlay->buttonState.minusDragActive.exchange(false, std::memory_order_acq_rel);
|
||||
overlay->buttonState.plusDragActive.exchange(false, std::memory_order_acq_rel);
|
||||
}
|
||||
|
||||
// Disable rendering on any input, re-enable when no input
|
||||
static bool resetOnce = true;
|
||||
if (inputDetected) {
|
||||
if (resetOnce && isRendering) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
resetOnce = false;
|
||||
}
|
||||
} else {
|
||||
resetOnce = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
static auto lastUnderscanPixels = std::make_pair(0, 0);
|
||||
|
||||
if (lastUnderscanPixels != tsl::impl::currentUnderscanPixels) {
|
||||
for (int i = 0; i < 2; i++) {
|
||||
tsl::gfx::Renderer::get().updateLayerSize();
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(overlay->frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
}
|
||||
lastUnderscanPixels = tsl::impl::currentUnderscanPixels;
|
||||
}
|
||||
|
||||
svcSleepThread(16000000ULL*2); // 16ms polling
|
||||
}
|
||||
}, this, NULL, 0x1000, 0x2B, -2);
|
||||
threadStart(&touchPollThread);
|
||||
}
|
||||
|
||||
~com_FPSGraph() {
|
||||
// Stop touch polling thread
|
||||
touchPollRunning.store(false, std::memory_order_release);
|
||||
threadWaitForExit(&touchPollThread);
|
||||
threadClose(&touchPollThread);
|
||||
|
||||
EndInfoThread();
|
||||
EndFPSCounterThread();
|
||||
FullMode = true;
|
||||
fixForeground = true;
|
||||
ult::useRightAlignment = originalUseRightAlignment;
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().addScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = false;
|
||||
}
|
||||
|
||||
struct stats {
|
||||
s16 value;
|
||||
bool zero_rounded;
|
||||
};
|
||||
|
||||
std::vector<stats> readings;
|
||||
|
||||
s16 base_y = 0;
|
||||
s16 base_x = 0;
|
||||
s16 rectangle_width = 180;
|
||||
s16 rectangle_height = 60;
|
||||
s16 rectangle_x = 15;
|
||||
s16 rectangle_y = 5;
|
||||
s16 rectangle_range_max = 60;
|
||||
s16 rectangle_range_min = 0;
|
||||
char legend_max[4] = "60";
|
||||
char legend_min[2] = "0";
|
||||
s32 range = std::abs(rectangle_range_max - rectangle_range_min) + 1;
|
||||
s16 x_end = rectangle_x + rectangle_width;
|
||||
s16 y_old = rectangle_y+rectangle_height;
|
||||
s16 y_30FPS = rectangle_y+(rectangle_height / 2);
|
||||
s16 y_60FPS = rectangle_y;
|
||||
bool isAbove = false;
|
||||
|
||||
virtual tsl::elm::Element* createUI() override {
|
||||
|
||||
auto* Status = new tsl::elm::CustomDrawer([this](tsl::gfx::Renderer *renderer, u16 x, u16 y, u16 w, u16 h) {
|
||||
|
||||
// Calculate content dimensions (what goes inside the border)
|
||||
const s16 refresh_rate_offset = (refreshRate < 100) ? 21 : 28;
|
||||
const s16 info_width = settings.showInfo ? (6 + rectangle_width/2 - 4) : 6;
|
||||
const s16 content_width = rectangle_width + refresh_rate_offset + info_width;
|
||||
const s16 content_height = rectangle_height + 12;
|
||||
|
||||
// Total dimensions including border
|
||||
const size_t totalWidth = content_width + (2 * border);
|
||||
const size_t totalHeight = content_height + (2 * border);
|
||||
|
||||
// Store actual dimensions for input handling
|
||||
actualTotalWidth = totalWidth;
|
||||
actualTotalHeight = totalHeight;
|
||||
|
||||
if (refreshRate && refreshRate < 240) {
|
||||
rectangle_height = refreshRate;
|
||||
rectangle_range_max = refreshRate;
|
||||
if (refreshRate < 100) {
|
||||
rectangle_x = 15;
|
||||
legend_max[0] = 0x30 + (refreshRate / 10);
|
||||
legend_max[1] = 0x30 + (refreshRate % 10);
|
||||
legend_max[2] = 0;
|
||||
}
|
||||
else {
|
||||
rectangle_x = 22;
|
||||
legend_max[0] = 0x30 + (refreshRate / 100);
|
||||
legend_max[1] = 0x30 + ((refreshRate / 10) % 10);
|
||||
legend_max[2] = 0x30 + (refreshRate % 10);
|
||||
}
|
||||
y_30FPS = rectangle_y+(rectangle_height / 2);
|
||||
range = std::abs(rectangle_range_max - rectangle_range_min) + 1;
|
||||
};
|
||||
|
||||
int _frameOffsetX = ult::limitedMemory ? std::max(0, frameOffsetX - (1280-448)) : frameOffsetX;
|
||||
|
||||
// Calculate position with frame offsets (for the rounded rect, which includes border)
|
||||
int posX = base_x + _frameOffsetX - border;
|
||||
int posY = base_y + frameOffsetY - border;
|
||||
|
||||
// Clamp to screen bounds (accounting for total size including border)
|
||||
posX = std::max(int(framePadding), std::min(posX, static_cast<int>(screenWidth - totalWidth - framePadding)));
|
||||
posY = std::max(int(framePadding), std::min(posY, static_cast<int>(screenHeight - totalHeight - framePadding)));
|
||||
|
||||
// Draw the rounded rectangle (background)
|
||||
const tsl::Color bgColor = !isDragging
|
||||
? settings.backgroundColor
|
||||
: settings.focusBackgroundColor;
|
||||
|
||||
renderer->drawRoundedRectSingleThreaded(
|
||||
posX,
|
||||
posY,
|
||||
totalWidth,
|
||||
totalHeight,
|
||||
16,
|
||||
aWithOpacity(bgColor)
|
||||
);
|
||||
|
||||
posX += 4;
|
||||
|
||||
// Content drawing position (inside the border)
|
||||
const int final_base_x = posX + border;
|
||||
const int final_base_y = posY + border;
|
||||
|
||||
const s16 size = (refreshRate > 60 || !refreshRate) ? 63 : (s32)(63.0/(60.0/refreshRate));
|
||||
const auto width = renderer->getTextDimensions(FPSavg_c, false, size).first;
|
||||
|
||||
const s16 pos_y = size + final_base_y + rectangle_y + ((rectangle_height - size) / 2);
|
||||
const s16 pos_x = final_base_x + rectangle_x + ((rectangle_width - width) / 2);
|
||||
|
||||
if (FPSavg != 254.0)
|
||||
renderer->drawString(FPSavg_c, false, pos_x, pos_y-5, size, settings.fpsColor);
|
||||
renderer->drawEmptyRect(final_base_x+(rectangle_x - 1)+2, final_base_y+(rectangle_y - 1), rectangle_width + 2, rectangle_height + 4, aWithOpacity(settings.borderColor));
|
||||
renderer->drawDashedLine(final_base_x+rectangle_x+2, final_base_y+y_30FPS, final_base_x+rectangle_x+rectangle_width, final_base_y+y_30FPS, 6, aWithOpacity(settings.dashedLineColor));
|
||||
renderer->drawString(&legend_max[0], false, final_base_x+(rectangle_x-((refreshRate < 100) ? 15 : 22)), final_base_y+(rectangle_y+7), 10, (settings.maxFPSTextColor));
|
||||
renderer->drawString(&legend_min[0], false, final_base_x+(rectangle_x-10), final_base_y+(rectangle_y+rectangle_height+3), 10, settings.minFPSTextColor);
|
||||
|
||||
size_t last_element = readings.size() - 1;
|
||||
|
||||
s16 offset = 0;
|
||||
if (refreshRate >= 100) offset = 7;
|
||||
|
||||
static s32 y_on_range;
|
||||
static tsl::Color color = {0};
|
||||
for (s16 x = x_end; x > static_cast<s16>(x_end-readings.size()); x--) {
|
||||
y_on_range = readings[last_element].value + std::abs(rectangle_range_min) + 1;
|
||||
if (y_on_range < 0) {
|
||||
y_on_range = 0;
|
||||
}
|
||||
else if (y_on_range > range) {
|
||||
isAbove = true;
|
||||
y_on_range = range;
|
||||
}
|
||||
|
||||
const s16 y = rectangle_y + static_cast<s16>(std::lround((float)rectangle_height * ((float)(range - y_on_range) / (float)range)));
|
||||
color = (settings.mainLineColor);
|
||||
if (y == y_old && !isAbove && readings[last_element].zero_rounded) {
|
||||
if ((y == y_30FPS || y == y_60FPS))
|
||||
color = (settings.perfectLineColor);
|
||||
else
|
||||
color = (settings.dashedLineColor);
|
||||
}
|
||||
|
||||
if (x == x_end) {
|
||||
y_old = y;
|
||||
}
|
||||
|
||||
renderer->drawLine(final_base_x+x+offset, final_base_y+y, final_base_x+x+offset, final_base_y+y_old, color);
|
||||
isAbove = false;
|
||||
y_old = y;
|
||||
last_element--;
|
||||
}
|
||||
|
||||
if (settings.showInfo) {
|
||||
const s16 info_x = final_base_x+rectangle_width+rectangle_x + 6 +8;
|
||||
const s16 info_y = final_base_y + 3;
|
||||
const s16 fontSize = 11;
|
||||
|
||||
// Get line height from font size (we'll use the actual rendered height)
|
||||
const auto testDimensions = renderer->getTextDimensions("A", false, fontSize);
|
||||
const s16 lineHeight = testDimensions.second;
|
||||
|
||||
// Starting Y position for first line
|
||||
const s16 startY = info_y + lineHeight;
|
||||
|
||||
// Value X position (offset from labels)
|
||||
const s16 value_x = info_x + 40;
|
||||
|
||||
static constexpr s16 SPACING = 1;
|
||||
|
||||
// Compute gradient colors for temperatures
|
||||
const tsl::Color socColor = settings.useDynamicColors ? tsl::GradientColor(SOC_temperatureF) : settings.textColor;
|
||||
const tsl::Color pcbColor = settings.useDynamicColors ? tsl::GradientColor(PCB_temperatureF) : settings.textColor;
|
||||
const tsl::Color skinColor = settings.useDynamicColors ? tsl::GradientColor(static_cast<float>(skin_temperaturemiliC) / 1000.0f) : settings.textColor;
|
||||
|
||||
// Draw each label and value pair on the same baseline
|
||||
// Line 0: CPU
|
||||
renderer->drawString("CPU", false, info_x, startY, fontSize, settings.catColor);
|
||||
renderer->drawString(CPU_Load_c, false, value_x, startY, fontSize, settings.textColor);
|
||||
|
||||
// Line 1: GPU
|
||||
renderer->drawString("GPU", false, info_x, startY + lineHeight+SPACING, fontSize, settings.catColor);
|
||||
renderer->drawString(GPU_Load_c, false, value_x, startY + lineHeight+SPACING, fontSize, settings.textColor);
|
||||
|
||||
// Line 2: RAM
|
||||
renderer->drawString("RAM", false, info_x, startY + lineHeight * 2+2*SPACING, fontSize, settings.catColor);
|
||||
renderer->drawString(RAM_Load_c, false, value_x, startY + lineHeight * 2+2*SPACING, fontSize, settings.textColor);
|
||||
|
||||
// Line 3: SOC (with gradient color)
|
||||
renderer->drawString("SOC", false, info_x, startY + lineHeight * 3+3*SPACING, fontSize, settings.catColor);
|
||||
renderer->drawString(SOC_TEMP_c, false, value_x, startY + lineHeight * 3+3*SPACING, fontSize, socColor);
|
||||
|
||||
// Line 4: PCB (with gradient color)
|
||||
renderer->drawString("PCB", false, info_x, startY + lineHeight * 4+4*SPACING, fontSize, settings.catColor);
|
||||
renderer->drawString(PCB_TEMP_c, false, value_x, startY + lineHeight * 4+4*SPACING, fontSize, pcbColor);
|
||||
|
||||
// Line 5: SKIN (with gradient color)
|
||||
renderer->drawString("Skin", false, info_x, startY + lineHeight * 5+5*SPACING, fontSize, settings.catColor);
|
||||
renderer->drawString(SKIN_TEMP_c, false, value_x, startY + lineHeight * 5+5*SPACING, fontSize, skinColor);
|
||||
}
|
||||
});
|
||||
|
||||
tsl::elm::HeaderOverlayFrame* rootFrame = new tsl::elm::HeaderOverlayFrame("", "");
|
||||
rootFrame->setContent(Status);
|
||||
|
||||
return rootFrame;
|
||||
}
|
||||
|
||||
virtual void update() override {
|
||||
cnt++;
|
||||
if (cnt >= TeslaFPS)
|
||||
cnt = 0;
|
||||
|
||||
///FPS
|
||||
stats temp = {0, false};
|
||||
static uint64_t lastFrame = 0;
|
||||
|
||||
snprintf(FPSavg_c, sizeof FPSavg_c, "%2.1f", FPSavg);
|
||||
const uint8_t SaltySharedDisplayRefreshRate = *(uint8_t*)((uintptr_t)shmemGetAddr(&_sharedmemory) + 1);
|
||||
if (SaltySharedDisplayRefreshRate)
|
||||
refreshRate = SaltySharedDisplayRefreshRate;
|
||||
else refreshRate = 60;
|
||||
if (FPSavg < 254) {
|
||||
snprintf(FPSavg_c, sizeof(FPSavg_c), "%.1f", useOldFPSavg ? FPSavg_old : FPSavg);
|
||||
|
||||
if (lastFrame == lastFrameNumber) return;
|
||||
else lastFrame = lastFrameNumber;
|
||||
if ((s16)(readings.size()) >= rectangle_width) {
|
||||
readings.erase(readings.begin());
|
||||
}
|
||||
const float whole = std::round(useOldFPSavg ? FPSavg_old : FPSavg);
|
||||
temp.value = static_cast<s16>(std::lround(useOldFPSavg ? FPSavg_old : FPSavg));
|
||||
if ((useOldFPSavg ? FPSavg_old : FPSavg) < whole+0.04 && (useOldFPSavg ? FPSavg_old : FPSavg) > whole-0.05) {
|
||||
temp.zero_rounded = true;
|
||||
}
|
||||
readings.push_back(temp);
|
||||
}
|
||||
else {
|
||||
if (readings.size()) {
|
||||
readings.clear();
|
||||
readings.shrink_to_fit();
|
||||
lastFrame = 0;
|
||||
}
|
||||
FPSavg_c[0] = 0;
|
||||
}
|
||||
|
||||
if (cnt)
|
||||
return;
|
||||
|
||||
mutexLock(&mutex_Misc);
|
||||
|
||||
// Format temperature strings separately for proper alignment
|
||||
snprintf(SOC_TEMP_c, sizeof SOC_TEMP_c, "%2.1f\u00B0C", SOC_temperatureF);
|
||||
snprintf(PCB_TEMP_c, sizeof PCB_TEMP_c, "%2.1f\u00B0C", PCB_temperatureF);
|
||||
snprintf(SKIN_TEMP_c, sizeof SKIN_TEMP_c, "%2d.%d\u00B0C",
|
||||
skin_temperaturemiliC / 1000, (skin_temperaturemiliC / 100) % 10);
|
||||
|
||||
// Atomically snapshot each idle tick once
|
||||
const uint64_t idle0 = idletick0.load(std::memory_order_acquire);
|
||||
const uint64_t idle1 = idletick1.load(std::memory_order_acquire);
|
||||
const uint64_t idle2 = idletick2.load(std::memory_order_acquire);
|
||||
const uint64_t idle3 = idletick3.load(std::memory_order_acquire);
|
||||
|
||||
// Clamp values to systemtickfrequency_impl (avoid div-by-zero / runaway)
|
||||
const uint64_t safe0 = std::min(idle0, systemtickfrequency_impl);
|
||||
const uint64_t safe1 = std::min(idle1, systemtickfrequency_impl);
|
||||
const uint64_t safe2 = std::min(idle2, systemtickfrequency_impl);
|
||||
const uint64_t safe3 = std::min(idle3, systemtickfrequency_impl);
|
||||
|
||||
// Compute per-core CPU usage
|
||||
const double cpu_usage0 = (1.0 - (static_cast<double>(safe0) / systemtickfrequency_impl)) * 100.0;
|
||||
const double cpu_usage1 = (1.0 - (static_cast<double>(safe1) / systemtickfrequency_impl)) * 100.0;
|
||||
const double cpu_usage2 = (1.0 - (static_cast<double>(safe2) / systemtickfrequency_impl)) * 100.0;
|
||||
const double cpu_usage3 = (1.0 - (static_cast<double>(safe3) / systemtickfrequency_impl)) * 100.0;
|
||||
|
||||
// Compute max core load (the highest usage)
|
||||
const double cpu_usageM = std::max({cpu_usage0, cpu_usage1, cpu_usage2, cpu_usage3});
|
||||
|
||||
// Format output strings
|
||||
snprintf(CPU_Load_c, sizeof(CPU_Load_c), "%.1f%%", cpu_usageM);
|
||||
snprintf(GPU_Load_c, sizeof(GPU_Load_c), "%d.%d%%", GPU_Load_u / 10, GPU_Load_u % 10);
|
||||
snprintf(RAM_Load_c, sizeof(RAM_Load_c), "%hu.%hhu%%",
|
||||
ramLoad[SysClkRamLoad_All] / 10,
|
||||
ramLoad[SysClkRamLoad_All] % 10);
|
||||
|
||||
mutexUnlock(&mutex_Misc);
|
||||
|
||||
if (!skipOnce) {
|
||||
if (runOnce) {
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
runOnce = false;
|
||||
}
|
||||
} else {
|
||||
skipOnce = false;
|
||||
}
|
||||
}
|
||||
|
||||
virtual bool handleInput(u64 keysDown, u64 keysHeld, const HidTouchState &touchPos, HidAnalogStickState joyStickPosLeft, HidAnalogStickState joyStickPosRight) override {
|
||||
// Static variables to maintain drag state between function calls
|
||||
static bool oldTouchDetected = false;
|
||||
static bool oldMinusHeld = false;
|
||||
static bool oldPlusHeld = false;
|
||||
static HidTouchState initialTouchPos = {0};
|
||||
static int initialFrameOffsetX = 0;
|
||||
static int initialFrameOffsetY = 0;
|
||||
static constexpr int TOUCH_THRESHOLD = 8;
|
||||
static bool hasMoved = false;
|
||||
|
||||
// Touch detection
|
||||
const bool currentTouchDetected = (touchPos.x > 0 && touchPos.y > 0 &&
|
||||
touchPos.x < screenWidth && touchPos.y < screenHeight);
|
||||
|
||||
static bool clearOnRelease = false;
|
||||
|
||||
if (clearOnRelease && !isRendering) {
|
||||
clearOnRelease = false;
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
}
|
||||
|
||||
// Use actual dimensions from last render, fallback to estimate if not available
|
||||
size_t totalWidth = actualTotalWidth;
|
||||
size_t totalHeight = actualTotalHeight;
|
||||
|
||||
if (totalWidth == 0) {
|
||||
// Fallback calculation if not yet rendered
|
||||
const s16 refresh_rate_offset = (refreshRate < 100) ? 21 : 28;
|
||||
const s16 info_width = settings.showInfo ? (6 + rectangle_width/2 - 4) : 0;
|
||||
const s16 content_width = rectangle_width + refresh_rate_offset + info_width;
|
||||
const s16 content_height = rectangle_height + 12;
|
||||
totalWidth = content_width + (2 * border);
|
||||
totalHeight = content_height + (2 * border);
|
||||
}
|
||||
|
||||
// Current overlay position (top-left of rounded rect)
|
||||
const int overlayX = base_x + frameOffsetX - border;
|
||||
const int overlayY = base_y + frameOffsetY - border;
|
||||
|
||||
// Touch detection area (with padding for easier interaction)
|
||||
static constexpr int touchPadding = 4;
|
||||
const int touchableX = overlayX - touchPadding;
|
||||
const int touchableY = overlayY - touchPadding;
|
||||
const int touchableWidth = totalWidth + (touchPadding * 2);
|
||||
const int touchableHeight = totalHeight + (touchPadding * 2);
|
||||
|
||||
// Screen boundaries for clamping (accounting for total size)
|
||||
const int minX = -(base_x - border) + framePadding;
|
||||
const int maxX = screenWidth - totalWidth - (base_x - border) - framePadding;
|
||||
const int minY = -(base_y - border) + framePadding;
|
||||
const int maxY = screenHeight - totalHeight - (base_y - border) - framePadding;
|
||||
|
||||
const bool minusDragReady = buttonState.minusDragActive.load(std::memory_order_acquire);
|
||||
const bool plusDragReady = buttonState.plusDragActive.load(std::memory_order_acquire);
|
||||
|
||||
// Check button states
|
||||
const bool currentMinusHeld = (keysHeld & KEY_MINUS) && !(keysHeld & ~KEY_MINUS & ALL_KEYS_MASK) && minusDragReady;
|
||||
const bool currentPlusHeld = (keysHeld & KEY_PLUS) && !(keysHeld & ~KEY_PLUS & ALL_KEYS_MASK) && plusDragReady;
|
||||
|
||||
// Handle touch dragging
|
||||
if (currentTouchDetected && !isDragging) {
|
||||
const int touchX = touchPos.x;
|
||||
const int touchY = touchPos.y;
|
||||
|
||||
if (!oldTouchDetected) {
|
||||
// Touch just started - check if within overlay bounds
|
||||
if (touchX >= touchableX && touchX <= touchableX + touchableWidth &&
|
||||
touchY >= touchableY && touchY <= touchableY + touchableHeight) {
|
||||
|
||||
// Start touch dragging
|
||||
isDragging = true;
|
||||
triggerRumbleClick.store(true, std::memory_order_release);
|
||||
triggerOnSound.store(true, std::memory_order_release);
|
||||
hasMoved = false;
|
||||
initialTouchPos = touchPos;
|
||||
initialFrameOffsetX = frameOffsetX;
|
||||
initialFrameOffsetY = frameOffsetY;
|
||||
}
|
||||
}
|
||||
} else if (currentTouchDetected && isDragging && !currentMinusHeld && !currentPlusHeld) {
|
||||
// Continue touch dragging
|
||||
const int touchX = touchPos.x;
|
||||
const int touchY = touchPos.y;
|
||||
const int deltaX = touchX - initialTouchPos.x;
|
||||
const int deltaY = touchY - initialTouchPos.y;
|
||||
|
||||
// Check if we've moved enough to consider this a drag
|
||||
if (!hasMoved) {
|
||||
const int totalMovement = abs(deltaX) + abs(deltaY);
|
||||
if (totalMovement >= TOUCH_THRESHOLD) {
|
||||
hasMoved = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (hasMoved) {
|
||||
// Update frame offsets with boundary checking
|
||||
frameOffsetX = std::max(minX, std::min(maxX, initialFrameOffsetX + deltaX));
|
||||
frameOffsetY = std::max(minY, std::min(maxY, initialFrameOffsetY + deltaY));
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
}
|
||||
} else if (!currentTouchDetected && oldTouchDetected && isDragging && !currentMinusHeld && !currentPlusHeld) {
|
||||
// Touch just released
|
||||
if (hasMoved) {
|
||||
// Save position when touch drag ends
|
||||
auto iniData = ult::getParsedDataFromIniFile(configIniPath);
|
||||
iniData["fps-graph"]["frame_offset_x"] = std::to_string(frameOffsetX);
|
||||
iniData["fps-graph"]["frame_offset_y"] = std::to_string(frameOffsetY);
|
||||
ult::saveIniFileData(configIniPath, iniData);
|
||||
}
|
||||
|
||||
// Reset touch drag state
|
||||
isDragging = false;
|
||||
hasMoved = false;
|
||||
clearOnRelease = true;
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerOffSound.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
// Handle joystick dragging (MINUS + right joystick OR PLUS + left joystick)
|
||||
if ((currentMinusHeld || currentPlusHeld) && !isDragging) {
|
||||
// Start joystick dragging
|
||||
isDragging = true;
|
||||
triggerRumbleClick.store(true, std::memory_order_release);
|
||||
triggerOnSound.store(true, std::memory_order_release);
|
||||
} else if ((currentMinusHeld || currentPlusHeld) && isDragging) {
|
||||
// Continue joystick dragging
|
||||
static constexpr int JOYSTICK_DEADZONE = 20;
|
||||
|
||||
// Choose the appropriate joystick based on which button is held
|
||||
const HidAnalogStickState& activeJoystick = currentMinusHeld ? joyStickPosRight : joyStickPosLeft;
|
||||
|
||||
// Only move if joystick is outside deadzone
|
||||
if (abs(activeJoystick.x) > JOYSTICK_DEADZONE || abs(activeJoystick.y) > JOYSTICK_DEADZONE) {
|
||||
// Calculate joystick magnitude
|
||||
const float magnitude = sqrt((float)(activeJoystick.x * activeJoystick.x + activeJoystick.y * activeJoystick.y));
|
||||
const float normalizedMagnitude = magnitude / 32767.0f;
|
||||
|
||||
// Smooth curve for sensitivity
|
||||
static constexpr float baseSensitivity = 0.00008f;
|
||||
static constexpr float maxSensitivity = 0.0005f;
|
||||
|
||||
const float curveValue = pow(normalizedMagnitude, 8.0f);
|
||||
const float currentSensitivity = baseSensitivity + (maxSensitivity - baseSensitivity) * curveValue;
|
||||
|
||||
// Calculate movement delta with fractional accumulation
|
||||
static float accumulatedX = 0.0f;
|
||||
static float accumulatedY = 0.0f;
|
||||
|
||||
accumulatedX += (float)activeJoystick.x * currentSensitivity;
|
||||
accumulatedY += -(float)activeJoystick.y * currentSensitivity;
|
||||
|
||||
const int deltaX = (int)accumulatedX;
|
||||
const int deltaY = (int)accumulatedY;
|
||||
accumulatedX -= deltaX;
|
||||
accumulatedY -= deltaY;
|
||||
|
||||
// Update frame offsets with boundary checking
|
||||
frameOffsetX = std::max(minX, std::min(maxX, frameOffsetX + deltaX));
|
||||
frameOffsetY = std::max(minY, std::min(maxY, frameOffsetY + deltaY));
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
}
|
||||
} else if (((!currentMinusHeld && oldMinusHeld) || (!currentPlusHeld && oldPlusHeld)) && isDragging) {
|
||||
// Button just released - stop joystick dragging
|
||||
auto iniData = ult::getParsedDataFromIniFile(configIniPath);
|
||||
iniData["fps-graph"]["frame_offset_x"] = std::to_string(frameOffsetX);
|
||||
iniData["fps-graph"]["frame_offset_y"] = std::to_string(frameOffsetY);
|
||||
ult::saveIniFileData(configIniPath, iniData);
|
||||
isDragging = false;
|
||||
clearOnRelease = true;
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerOffSound.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
// Update state for next frame
|
||||
oldTouchDetected = currentTouchDetected;
|
||||
oldMinusHeld = currentMinusHeld;
|
||||
oldPlusHeld = currentPlusHeld;
|
||||
|
||||
// Handle existing key input logic (but don't interfere with dragging)
|
||||
if (!isDragging) {
|
||||
if (isKeyComboPressed(keysHeld, keysDown)) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
runOnce = true;
|
||||
skipOnce = true;
|
||||
TeslaFPS = 60;
|
||||
lastSelectedItem = "FPS Graph";
|
||||
lastMode = "";
|
||||
if (skipMain) {
|
||||
lastMode = "return";
|
||||
tsl::goBack();
|
||||
}
|
||||
else {
|
||||
tsl::setNextOverlay(filepath.c_str(), "--lastSelectedItem 'FPS Graph'");
|
||||
tsl::Overlay::get()->close();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// Return true if we handled the input (during dragging)
|
||||
return isDragging;
|
||||
}
|
||||
};
|
||||
635
Source/Horizon-OC-Monitor/source/modes/Full.hpp
Normal file
635
Source/Horizon-OC-Monitor/source/modes/Full.hpp
Normal file
@@ -0,0 +1,635 @@
|
||||
class MainMenu;
|
||||
|
||||
class FullOverlay : public tsl::Gui {
|
||||
private:
|
||||
char DeltaCPU_c[12] = "";
|
||||
char DeltaGPU_c[12] = "";
|
||||
char DeltaRAM_c[12] = "";
|
||||
char RealCPU_Hz_c[64] = "";
|
||||
char RealGPU_Hz_c[64] = "";
|
||||
char RealRAM_Hz_c[64] = "";
|
||||
char GPU_Load_c[32] = "";
|
||||
char Rotation_SpeedLevel_c[64] = "";
|
||||
char RAM_compressed_c[64] = "";
|
||||
char RAM_var_compressed_c[128] = "";
|
||||
char RAM_percentage_var_compressed_c[128] = "";
|
||||
char CPU_Hz_c[64] = "";
|
||||
char GPU_Hz_c[64] = "";
|
||||
char RAM_Hz_c[64] = "";
|
||||
char CPU_compressed_c[160] = "";
|
||||
char SOC_temperature_c[32] = "";
|
||||
char PCB_temperature_c[32] = "";
|
||||
char skin_temperature_c[32] = "";
|
||||
char BatteryDraw_c[64] = "";
|
||||
char FPS_var_compressed_c[64] = "";
|
||||
char RAM_load_c[64] = "";
|
||||
char Resolutions_c[64] = "";
|
||||
char readSpeed_c[32] = "";
|
||||
|
||||
// New separated value buffers for CPU cores
|
||||
char CPU_Core0_c[16] = "";
|
||||
char CPU_Core1_c[16] = "";
|
||||
char CPU_Core2_c[16] = "";
|
||||
char CPU_Core3_c[16] = "";
|
||||
|
||||
// New separated value buffers for FPS
|
||||
char PFPS_value_c[16] = "";
|
||||
char FPS_value_c[16] = "";
|
||||
|
||||
static constexpr uint8_t COMMON_MARGIN = 20;
|
||||
FullSettings settings;
|
||||
uint64_t systemtickfrequency_impl = systemtickfrequency;
|
||||
std::string formattedKeyCombo = keyCombo;
|
||||
std::string message;
|
||||
const std::vector<std::string> KEY_SYMBOLS = {
|
||||
"\uE0E4", "\uE0E5", "\uE0E6", "\uE0E7",
|
||||
"\uE0E8", "\uE0E9", "\uE0ED", "\uE0EB",
|
||||
"\uE0EE", "\uE0EC", "\uE0E0", "\uE0E1",
|
||||
"\uE0E2", "\uE0E3", "\uE08A", "\uE08B",
|
||||
"\uE0B6", "\uE0B5"
|
||||
};
|
||||
|
||||
bool skipOnce = true;
|
||||
bool runOnce = true;
|
||||
|
||||
bool originalUseRightAlignment = ult::useRightAlignment;
|
||||
public:
|
||||
FullOverlay() {
|
||||
disableJumpTo = true;
|
||||
GetConfigSettings(&settings);
|
||||
mutexInit(&mutex_BatteryChecker);
|
||||
mutexInit(&mutex_Misc);
|
||||
tsl::hlp::requestForeground(false);
|
||||
TeslaFPS = settings.refreshRate;
|
||||
systemtickfrequency_impl /= settings.refreshRate;
|
||||
idletick0.store(systemtickfrequency_impl, std::memory_order_relaxed);
|
||||
idletick1.store(systemtickfrequency_impl, std::memory_order_relaxed);
|
||||
idletick2.store(systemtickfrequency_impl, std::memory_order_relaxed);
|
||||
idletick3.store(systemtickfrequency_impl, std::memory_order_relaxed);
|
||||
if (settings.setPosRight) {
|
||||
const auto [horizontalUnderscanPixels, verticalUnderscanPixels] = tsl::gfx::getUnderscanPixels();
|
||||
tsl::gfx::Renderer::get().setLayerPos(1280-32 - horizontalUnderscanPixels, 0);
|
||||
ult::useRightAlignment = true;
|
||||
} else {
|
||||
tsl::gfx::Renderer::get().setLayerPos(0, 0);
|
||||
ult::useRightAlignment = false;
|
||||
}
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().removeScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = true;
|
||||
formatButtonCombination(formattedKeyCombo);
|
||||
//message = "Press " + formattedKeyCombo + " to Exit";
|
||||
|
||||
realVoltsPolling = false;
|
||||
StartThreads();
|
||||
}
|
||||
~FullOverlay() {
|
||||
CloseThreads();
|
||||
fixForeground = true;
|
||||
ult::useRightAlignment = originalUseRightAlignment;
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().addScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = false;
|
||||
}
|
||||
|
||||
resolutionCalls m_resolutionRenderCalls[8] = {0};
|
||||
resolutionCalls m_resolutionViewportCalls[8] = {0};
|
||||
resolutionCalls m_resolutionOutput[8] = {0};
|
||||
uint8_t resolutionLookup = 0;
|
||||
|
||||
virtual tsl::elm::Element* createUI() override {
|
||||
|
||||
|
||||
auto Status = new tsl::elm::CustomDrawer([this](tsl::gfx::Renderer *renderer, u16 x, u16 y, u16 w, u16 h) {
|
||||
//static auto targetFreqWidth = renderer->getTextDimensions("Target Frequency", false, 15).first;
|
||||
//static auto realFreqWidth = renderer->getTextDimensions("Real Frequency", false, 15).first;
|
||||
//static auto freqWidth = std::max(targetFreqWidth, realFreqWidth);
|
||||
|
||||
//static auto batteryLabelWidth = renderer->getTextDimensions("Battery Power Flow", false, 15).first;
|
||||
//static auto fanLabelWidth = renderer->getTextDimensions("Fan Rotation Level", false, 15).first;
|
||||
//static auto boardWidth = std::max(batteryLabelWidth, fanLabelWidth);
|
||||
|
||||
static constexpr size_t valueOffset = 150+10;
|
||||
static constexpr size_t deltaOffset = 246+10;
|
||||
static constexpr size_t ramPercentageOffset = 350+10;
|
||||
|
||||
//Print strings
|
||||
///CPU
|
||||
if (R_SUCCEEDED(clkrstCheck) || R_SUCCEEDED(pcvCheck)) {
|
||||
|
||||
uint32_t height_offset = 155;
|
||||
if (realCPU_Hz && settings.showRealFreqs) {
|
||||
height_offset = 162;
|
||||
}
|
||||
renderer->drawString("CPU Usage", false, COMMON_MARGIN, 120, 20, (settings.catColor1));
|
||||
if (settings.showTargetFreqs) {
|
||||
//static auto targetFreqWidth = renderer->getTextDimensions("Target Frequency: ", false, 15).first;
|
||||
renderer->drawString("Target Frequency", false, COMMON_MARGIN, height_offset, 15, (settings.catColor2));
|
||||
renderer->drawString(CPU_Hz_c, false, COMMON_MARGIN + valueOffset, height_offset, 15, (settings.textColor));
|
||||
}
|
||||
if (realCPU_Hz && settings.showRealFreqs) {
|
||||
//static auto realFreqWidth = renderer->getTextDimensions("Real Frequency: ", false, 15).first;
|
||||
renderer->drawString("Real Frequency", false, COMMON_MARGIN, height_offset - 15, 15, (settings.catColor2));
|
||||
renderer->drawString(RealCPU_Hz_c, false, COMMON_MARGIN + valueOffset, height_offset - 15, 15, (settings.textColor));
|
||||
if (settings.showDeltas && settings.showTargetFreqs) {
|
||||
renderer->drawString(DeltaCPU_c, false, COMMON_MARGIN + deltaOffset, height_offset - 7, 15, (settings.textColor));
|
||||
}
|
||||
else if (settings.showDeltas && !settings.showTargetFreqs) {
|
||||
renderer->drawString(DeltaCPU_c, false, COMMON_MARGIN + deltaOffset, height_offset - 15, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
else if (realCPU_Hz && settings.showDeltas && (settings.showRealFreqs || settings.showTargetFreqs)) {
|
||||
renderer->drawString(DeltaCPU_c, false, COMMON_MARGIN + deltaOffset, height_offset, 15, (settings.textColor));
|
||||
}
|
||||
|
||||
// CPU Core labels and values
|
||||
static auto core0Width = renderer->getTextDimensions("Core 0 ", false, 15).first;
|
||||
static auto core1Width = renderer->getTextDimensions("Core 1 ", false, 15).first;
|
||||
static auto core2Width = renderer->getTextDimensions("Core 2 ", false, 15).first;
|
||||
static auto core3Width = renderer->getTextDimensions("Core 3 ", false, 15).first;
|
||||
|
||||
const uint32_t core_height = height_offset + 30;
|
||||
renderer->drawString("Core 0 ", false, COMMON_MARGIN, core_height, 15, (settings.catColor2));
|
||||
renderer->drawString(CPU_Core0_c, false, COMMON_MARGIN + core0Width, core_height, 15, (settings.textColor));
|
||||
|
||||
renderer->drawString("Core 1 ", false, COMMON_MARGIN, core_height + 15, 15, (settings.catColor2));
|
||||
renderer->drawString(CPU_Core1_c, false, COMMON_MARGIN + core1Width, core_height + 15, 15, (settings.textColor));
|
||||
|
||||
renderer->drawString("Core 2 ", false, COMMON_MARGIN, core_height + 30, 15, (settings.catColor2));
|
||||
renderer->drawString(CPU_Core2_c, false, COMMON_MARGIN + core2Width, core_height + 30, 15, (settings.textColor));
|
||||
|
||||
renderer->drawString("Core 3 ", false, COMMON_MARGIN, core_height + 45, 15, (settings.catColor2));
|
||||
renderer->drawString(CPU_Core3_c, false, COMMON_MARGIN + core3Width, core_height + 45, 15, (settings.textColor));
|
||||
}
|
||||
|
||||
///GPU
|
||||
if (R_SUCCEEDED(clkrstCheck) || R_SUCCEEDED(pcvCheck) || R_SUCCEEDED(nvCheck)) {
|
||||
|
||||
uint32_t height_offset = 320-8;
|
||||
if (realGPU_Hz && settings.showRealFreqs) {
|
||||
height_offset = 327-8;
|
||||
}
|
||||
|
||||
renderer->drawString("GPU Usage", false, COMMON_MARGIN, 285-8, 20, (settings.catColor1));
|
||||
if (R_SUCCEEDED(clkrstCheck) || R_SUCCEEDED(pcvCheck)) {
|
||||
if (settings.showTargetFreqs) {
|
||||
//static auto targetFreqWidth = renderer->getTextDimensions("Target Frequency: ", false, 15).first;
|
||||
renderer->drawString("Target Frequency", false, COMMON_MARGIN, height_offset, 15, (settings.catColor2));
|
||||
renderer->drawString(GPU_Hz_c, false, COMMON_MARGIN + valueOffset, height_offset, 15, (settings.textColor));
|
||||
}
|
||||
if (realCPU_Hz && settings.showRealFreqs) {
|
||||
//static auto realFreqWidth = renderer->getTextDimensions("Real Frequency: ", false, 15).first;
|
||||
renderer->drawString("Real Frequency", false, COMMON_MARGIN, height_offset - 15, 15, (settings.catColor2));
|
||||
renderer->drawString(RealGPU_Hz_c, false, COMMON_MARGIN + valueOffset, height_offset - 15, 15, (settings.textColor));
|
||||
if (settings.showDeltas && settings.showTargetFreqs) {
|
||||
renderer->drawString(DeltaGPU_c, false, COMMON_MARGIN + deltaOffset, height_offset - 7, 15, (settings.textColor));
|
||||
}
|
||||
else if (settings.showDeltas && !settings.showTargetFreqs) {
|
||||
renderer->drawString(DeltaGPU_c, false, COMMON_MARGIN + deltaOffset, height_offset - 15, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
else if (realGPU_Hz && settings.showDeltas && (settings.showRealFreqs || settings.showTargetFreqs)) {
|
||||
renderer->drawString(DeltaGPU_c, false, COMMON_MARGIN + deltaOffset, height_offset, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
if (R_SUCCEEDED(nvCheck)) {
|
||||
//static auto loadWidth = renderer->getTextDimensions("Load: ", false, 15).first;
|
||||
renderer->drawString("Load", false, COMMON_MARGIN, height_offset + 15, 15, (settings.catColor2));
|
||||
renderer->drawString(GPU_Load_c, false, COMMON_MARGIN + valueOffset, height_offset + 15, 15, (settings.textColor));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static std::vector<std::string> specialChars = {""};
|
||||
|
||||
///RAM
|
||||
if (R_SUCCEEDED(clkrstCheck) || R_SUCCEEDED(pcvCheck) || R_SUCCEEDED(Hinted)) {
|
||||
|
||||
uint32_t height_offset = 410;
|
||||
if (realRAM_Hz && settings.showRealFreqs) {
|
||||
height_offset += 7;
|
||||
}
|
||||
|
||||
renderer->drawString("RAM Usage", false, COMMON_MARGIN, 375, 20, (settings.catColor1));
|
||||
if (R_SUCCEEDED(clkrstCheck) || R_SUCCEEDED(pcvCheck)) {
|
||||
if (settings.showTargetFreqs) {
|
||||
//static auto targetFreqWidth = renderer->getTextDimensions("Target Frequency: ", false, 15).first;
|
||||
renderer->drawString("Target Frequency", false, COMMON_MARGIN, height_offset, 15, (settings.catColor2));
|
||||
renderer->drawString(RAM_Hz_c, false, COMMON_MARGIN + valueOffset, height_offset, 15, (settings.textColor));
|
||||
}
|
||||
if (realRAM_Hz && settings.showRealFreqs) {
|
||||
//static auto realFreqWidth = renderer->getTextDimensions("Real Frequency: ", false, 15).first;
|
||||
renderer->drawString("Real Frequency", false, COMMON_MARGIN, height_offset - 15, 15, (settings.catColor2));
|
||||
renderer->drawString(RealRAM_Hz_c, false, COMMON_MARGIN + valueOffset, height_offset - 15, 15, (settings.textColor));
|
||||
if (settings.showDeltas && settings.showTargetFreqs) {
|
||||
renderer->drawString(DeltaRAM_c, false, COMMON_MARGIN + deltaOffset, height_offset - 7, 15, (settings.textColor));
|
||||
}
|
||||
else if (settings.showDeltas && !settings.showTargetFreqs) {
|
||||
renderer->drawString(DeltaRAM_c, false, COMMON_MARGIN + deltaOffset, height_offset - 15, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
else if (realRAM_Hz && settings.showDeltas && (settings.showRealFreqs || settings.showTargetFreqs)) {
|
||||
renderer->drawString(DeltaRAM_c, false, COMMON_MARGIN + deltaOffset, height_offset, 15, (settings.textColor));
|
||||
}
|
||||
if (R_SUCCEEDED(sysclkCheck)) {
|
||||
static std::vector<std::string> ramLoadColoredChars = {"CPU", "GPU"};
|
||||
//static auto loadLabelWidth = renderer->getTextDimensions("Load: ", false, 15).first;
|
||||
renderer->drawString("Load", false, COMMON_MARGIN, height_offset+15, 15, (settings.catColor2));
|
||||
renderer->drawStringWithColoredSections(RAM_load_c, false, ramLoadColoredChars, COMMON_MARGIN + valueOffset, height_offset+15, 15, (settings.textColor), settings.catColor2);
|
||||
}
|
||||
}
|
||||
if (R_SUCCEEDED(Hinted)) {
|
||||
//static auto textWidth = renderer->getTextDimensions("Total \nApplication \nApplet \nSystem \nSystem Unsafe ", false, 15).first;
|
||||
renderer->drawString("Total\nApplication\nApplet\nSystem\nSystem Unsafe", false, COMMON_MARGIN, height_offset + 40, 15, (settings.catColor2));
|
||||
renderer->drawString(RAM_var_compressed_c, false, COMMON_MARGIN + valueOffset, height_offset + 40, 15, (settings.textColor));
|
||||
renderer->drawString(RAM_percentage_var_compressed_c, false, ramPercentageOffset, height_offset + 40, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
|
||||
///Thermal
|
||||
if (R_SUCCEEDED(i2cCheck) || R_SUCCEEDED(tcCheck) || R_SUCCEEDED(pwmCheck)) {
|
||||
renderer->drawString("Board", false, 20, 550+2, 20, (settings.catColor1));
|
||||
if (R_SUCCEEDED(i2cCheck)) {
|
||||
renderer->drawString("Battery Power Flow", false, COMMON_MARGIN, 575+2, 15, (settings.catColor2));
|
||||
renderer->drawStringWithColoredSections(BatteryDraw_c, false, specialChars, COMMON_MARGIN + valueOffset, 575+2, 15, (settings.textColor), settings.separatorColor);
|
||||
}
|
||||
if (R_SUCCEEDED(pwmCheck)) {
|
||||
renderer->drawString("Fan Rotation Level", false, COMMON_MARGIN, 590+2, 15, (settings.catColor2));
|
||||
renderer->drawString(Rotation_SpeedLevel_c, false, COMMON_MARGIN + valueOffset, 590+2, 15, (settings.textColor));
|
||||
}
|
||||
if (R_SUCCEEDED(i2cCheck) || R_SUCCEEDED(tcCheck)) {
|
||||
static auto socLabelWidth = renderer->getTextDimensions("SOC ", false, 15).first;
|
||||
static auto pcbLabelWidth = renderer->getTextDimensions("PCB ", false, 15).first;
|
||||
static auto maxLabelWidth = std::max(socLabelWidth, pcbLabelWidth);
|
||||
static auto skinLabelWidth = renderer->getTextDimensions("Skin ", false, 15).first;
|
||||
|
||||
// Compute gradient colors for temperatures
|
||||
const tsl::Color socColor = settings.useDynamicColors ? tsl::GradientColor(SOC_temperatureF) : settings.textColor;
|
||||
const tsl::Color pcbColor = settings.useDynamicColors ? tsl::GradientColor(PCB_temperatureF) : settings.textColor;
|
||||
const tsl::Color skinColor = settings.useDynamicColors ? tsl::GradientColor(static_cast<float>(skin_temperaturemiliC) / 1000.0f) : settings.textColor;
|
||||
|
||||
renderer->drawString("Temperatures", false, COMMON_MARGIN, 605+2, 15, (settings.catColor2));
|
||||
|
||||
// SOC - starts at valueOffset next to "Temperatures"
|
||||
uint32_t current_x = COMMON_MARGIN + valueOffset;
|
||||
renderer->drawString("SOC ", false, current_x, 605+2, 15, (settings.catColor2));
|
||||
current_x += maxLabelWidth;
|
||||
renderer->drawString(SOC_temperature_c, false, current_x, 605+2, 15, socColor);
|
||||
|
||||
// SKIN - same spacing to the right
|
||||
current_x += renderer->getTextDimensions(SOC_temperature_c, false, 15).first + 15;
|
||||
renderer->drawString("Skin ", false, current_x, 605+2, 15, (settings.catColor2));
|
||||
current_x += skinLabelWidth;
|
||||
renderer->drawString(skin_temperature_c, false, current_x, 605+2, 15, skinColor);
|
||||
|
||||
// PCB - below SOC on next line
|
||||
current_x = COMMON_MARGIN + valueOffset;
|
||||
renderer->drawString("PCB ", false, current_x, 620+2, 15, (settings.catColor2));
|
||||
current_x += maxLabelWidth;
|
||||
renderer->drawString(PCB_temperature_c, false, current_x, 620+2, 15, pcbColor);
|
||||
}
|
||||
}
|
||||
|
||||
///FPS
|
||||
if (GameRunning) {
|
||||
const uint32_t width_offset = valueOffset;
|
||||
if (settings.showFPS || settings.showRES || settings.showRDSD) {
|
||||
renderer->drawString("Game", false, COMMON_MARGIN + width_offset, 185+12, 20, (settings.catColor1));
|
||||
}
|
||||
uint32_t height = 210+12;
|
||||
if (settings.showFPS == true) {
|
||||
static auto pfpsWidth = renderer->getTextDimensions("PFPS ", false, 15).first;
|
||||
static auto fpsWidth = renderer->getTextDimensions("FPS ", false, 15).first;
|
||||
|
||||
renderer->drawString("PFPS ", false, COMMON_MARGIN + width_offset, height, 15, (settings.catColor2));
|
||||
renderer->drawString(PFPS_value_c, false, COMMON_MARGIN + width_offset + pfpsWidth, height, 15, (settings.textColor));
|
||||
|
||||
// Calculate position for "FPS " label - add some spacing
|
||||
const uint32_t fps_x_offset = COMMON_MARGIN + width_offset + pfpsWidth + renderer->getTextDimensions(PFPS_value_c, false, 15).first + 15;
|
||||
renderer->drawString("FPS ", false, fps_x_offset, height, 15, (settings.catColor2));
|
||||
renderer->drawString(FPS_value_c, false, fps_x_offset + fpsWidth, height, 15, (settings.textColor));
|
||||
|
||||
height += 15;
|
||||
}
|
||||
if ((settings.showRES == true) && NxFps && SharedMemoryUsed && (NxFps -> API >= 1)) {
|
||||
static auto resLabelWidth = renderer->getTextDimensions("Resolutions ", false, 15).first;
|
||||
renderer->drawString("Resolutions ", false, COMMON_MARGIN + width_offset, height, 15, (settings.catColor2));
|
||||
|
||||
renderer->drawStringWithColoredSections(Resolutions_c, false, specialChars, COMMON_MARGIN + width_offset + resLabelWidth, height, 15, (settings.textColor), settings.separatorColor);
|
||||
height += 15;
|
||||
}
|
||||
if (settings.showRDSD == true) {
|
||||
static auto readLabelWidth = renderer->getTextDimensions("Read Speed ", false, 15).first;
|
||||
renderer->drawString("Read Speed ", false, COMMON_MARGIN + width_offset, height, 15, (settings.catColor2));
|
||||
renderer->drawString(readSpeed_c, false, COMMON_MARGIN + width_offset + readLabelWidth, height, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
|
||||
//renderer->drawStringWithColoredSections(message, false, KEY_SYMBOLS, 30, 693, 23, a(tsl::bottomTextColor), a(tsl::buttonColor));
|
||||
|
||||
|
||||
static const auto pressWidth = renderer->getTextDimensions("Press ", false, 23).first;
|
||||
static const auto keyComboWidth = renderer->getTextDimensions(formattedKeyCombo.c_str(), false, 23).first;
|
||||
|
||||
static constexpr u16 baseX = 30;
|
||||
static constexpr u16 baseY = 693;
|
||||
static constexpr u8 fontSize = 23;
|
||||
|
||||
// Draw "Press "
|
||||
renderer->drawString("Press ", false, baseX, baseY, fontSize, (tsl::bottomTextColor));
|
||||
|
||||
// Draw formatted key combo with colored sections
|
||||
renderer->drawStringWithColoredSections(formattedKeyCombo, false, KEY_SYMBOLS, baseX + pressWidth, baseY, fontSize, (tsl::bottomTextColor), (tsl::buttonColor));
|
||||
|
||||
// Draw " to Exit"
|
||||
renderer->drawString(" to Exit", false, baseX + pressWidth + keyComboWidth, baseY, fontSize, (tsl::bottomTextColor));
|
||||
});
|
||||
|
||||
auto rootFrame = new tsl::elm::HeaderOverlayFrame("Status Monitor", APP_VERSION);
|
||||
rootFrame->setContent(Status);
|
||||
|
||||
return rootFrame;
|
||||
}
|
||||
|
||||
virtual void update() override {
|
||||
//Make stuff ready to print
|
||||
///CPU
|
||||
if (systemtickfrequency_impl > 0) {
|
||||
const uint64_t idle0_val = std::min(idletick0.load(std::memory_order_acquire), systemtickfrequency_impl);
|
||||
const uint64_t idle1_val = std::min(idletick1.load(std::memory_order_acquire), systemtickfrequency_impl);
|
||||
const uint64_t idle2_val = std::min(idletick2.load(std::memory_order_acquire), systemtickfrequency_impl);
|
||||
const uint64_t idle3_val = std::min(idletick3.load(std::memory_order_acquire), systemtickfrequency_impl);
|
||||
|
||||
const float usage0 = std::clamp(100.0f * (1.0f - float(idle0_val) / systemtickfrequency_impl), 0.0f, 100.0f);
|
||||
const float usage1 = std::clamp(100.0f * (1.0f - float(idle1_val) / systemtickfrequency_impl), 0.0f, 100.0f);
|
||||
const float usage2 = std::clamp(100.0f * (1.0f - float(idle2_val) / systemtickfrequency_impl), 0.0f, 100.0f);
|
||||
const float usage3 = std::clamp(100.0f * (1.0f - float(idle3_val) / systemtickfrequency_impl), 0.0f, 100.0f);
|
||||
|
||||
// Format individual core values
|
||||
snprintf(CPU_Core0_c, sizeof(CPU_Core0_c), "%.2f%%", usage0);
|
||||
snprintf(CPU_Core1_c, sizeof(CPU_Core1_c), "%.2f%%", usage1);
|
||||
snprintf(CPU_Core2_c, sizeof(CPU_Core2_c), "%.2f%%", usage2);
|
||||
snprintf(CPU_Core3_c, sizeof(CPU_Core3_c), "%.2f%%", usage3);
|
||||
}
|
||||
|
||||
mutexLock(&mutex_Misc);
|
||||
snprintf(CPU_Hz_c, sizeof(CPU_Hz_c), "%u.%u MHz", CPU_Hz / 1000000, (CPU_Hz / 100000) % 10);
|
||||
if (realCPU_Hz) {
|
||||
snprintf(RealCPU_Hz_c, sizeof(RealCPU_Hz_c), "%u.%u MHz", realCPU_Hz / 1000000, (realCPU_Hz / 100000) % 10);
|
||||
const int32_t deltaCPU = (int32_t)(realCPU_Hz / 1000) - (CPU_Hz / 1000);
|
||||
snprintf(DeltaCPU_c, sizeof(DeltaCPU_c), "Δ %d.%u", deltaCPU / 1000, abs(deltaCPU / 100) % 10);
|
||||
}
|
||||
|
||||
///GPU
|
||||
snprintf(GPU_Hz_c, sizeof GPU_Hz_c, "%u.%u MHz", GPU_Hz / 1000000, (GPU_Hz / 100000) % 10);
|
||||
if (realGPU_Hz) {
|
||||
snprintf(RealGPU_Hz_c, sizeof(RealGPU_Hz_c), "%u.%u MHz", realGPU_Hz / 1000000, (realGPU_Hz / 100000) % 10);
|
||||
const int32_t deltaGPU = (int32_t)(realGPU_Hz / 1000) - (GPU_Hz / 1000);
|
||||
snprintf(DeltaGPU_c, sizeof(DeltaGPU_c), "Δ %d.%u", deltaGPU / 1000, abs(deltaGPU / 100) % 10);
|
||||
}
|
||||
snprintf(GPU_Load_c, sizeof GPU_Load_c, "%u.%u%%", GPU_Load_u / 10, GPU_Load_u % 10);
|
||||
|
||||
///RAM
|
||||
snprintf(RAM_Hz_c, sizeof RAM_Hz_c, "%u.%u MHz", RAM_Hz / 1000000, (RAM_Hz / 100000) % 10);
|
||||
if (realRAM_Hz) {
|
||||
snprintf(RealRAM_Hz_c, sizeof(RealRAM_Hz_c), "%u.%u MHz", realRAM_Hz / 1000000, (realRAM_Hz / 100000) % 10);
|
||||
const int32_t deltaRAM = (int32_t)(realRAM_Hz / 1000) - (RAM_Hz / 1000);
|
||||
snprintf(DeltaRAM_c, sizeof(DeltaRAM_c), "Δ %d.%u", deltaRAM / 1000, abs(deltaRAM / 100) % 10);
|
||||
}
|
||||
|
||||
const float RAM_Total_application_f = (float)RAM_Total_application_u / 1024 / 1024;
|
||||
const float RAM_Total_applet_f = (float)RAM_Total_applet_u / 1024 / 1024;
|
||||
const float RAM_Total_system_f = (float)RAM_Total_system_u / 1024 / 1024;
|
||||
const float RAM_Total_systemunsafe_f = (float)RAM_Total_systemunsafe_u / 1024 / 1024;
|
||||
const float RAM_Total_all_f = RAM_Total_application_f + RAM_Total_applet_f + RAM_Total_system_f + RAM_Total_systemunsafe_f;
|
||||
|
||||
const float RAM_Used_application_f = (float)RAM_Used_application_u / 1024 / 1024;
|
||||
const float RAM_Used_applet_f = (float)RAM_Used_applet_u / 1024 / 1024;
|
||||
const float RAM_Used_system_f = (float)RAM_Used_system_u / 1024 / 1024;
|
||||
const float RAM_Used_systemunsafe_f = (float)RAM_Used_systemunsafe_u / 1024 / 1024;
|
||||
const float RAM_Used_all_f = RAM_Used_application_f + RAM_Used_applet_f + RAM_Used_system_f + RAM_Used_systemunsafe_f;
|
||||
|
||||
// Compute percentages
|
||||
const int RAMPct_all = (int)((RAM_Used_all_f / RAM_Total_all_f) * 100.0f );
|
||||
const int RAMPct_app = (int)((RAM_Used_application_f / RAM_Total_application_f) * 100.0f );
|
||||
const int RAMPct_applet = (int)((RAM_Used_applet_f / RAM_Total_applet_f) * 100.0f );
|
||||
const int RAMPct_system = (int)((RAM_Used_system_f / RAM_Total_system_f) * 100.0f );
|
||||
const int RAMPct_systemunsafe = (int)((RAM_Used_systemunsafe_f/ RAM_Total_systemunsafe_f)* 100.0f );
|
||||
|
||||
snprintf(RAM_var_compressed_c, sizeof(RAM_var_compressed_c),
|
||||
"%.1f MB / %.1f MB\n"
|
||||
"%.1f MB / %.1f MB\n"
|
||||
"%.1f MB / %.1f MB\n"
|
||||
"%.1f MB / %.1f MB\n"
|
||||
"%.1f MB / %.1f MB",
|
||||
RAM_Used_all_f, RAM_Total_all_f,
|
||||
RAM_Used_application_f, RAM_Total_application_f,
|
||||
RAM_Used_applet_f, RAM_Total_applet_f,
|
||||
RAM_Used_system_f, RAM_Total_system_f,
|
||||
RAM_Used_systemunsafe_f, RAM_Total_systemunsafe_f
|
||||
);
|
||||
|
||||
// 2. Percentages only (newlines preserved)
|
||||
snprintf(RAM_percentage_var_compressed_c, sizeof(RAM_percentage_var_compressed_c),
|
||||
"(%d%%)\n"
|
||||
"(%d%%)\n"
|
||||
"(%d%%)\n"
|
||||
"(%d%%)\n"
|
||||
"(%d%%)",
|
||||
RAMPct_all,
|
||||
RAMPct_app,
|
||||
RAMPct_applet,
|
||||
RAMPct_system,
|
||||
RAMPct_systemunsafe
|
||||
);
|
||||
|
||||
if (R_SUCCEEDED(sysclkCheck)) {
|
||||
const int RAM_GPU_Load = ramLoad[SysClkRamLoad_All] - ramLoad[SysClkRamLoad_Cpu];
|
||||
snprintf(RAM_load_c, sizeof RAM_load_c,
|
||||
"%u.%u%% CPU %u.%u%% GPU %u.%u%%",
|
||||
ramLoad[SysClkRamLoad_All] / 10, ramLoad[SysClkRamLoad_All] % 10,
|
||||
ramLoad[SysClkRamLoad_Cpu] / 10, ramLoad[SysClkRamLoad_Cpu] % 10,
|
||||
RAM_GPU_Load / 10, RAM_GPU_Load % 10);
|
||||
}
|
||||
///Thermal
|
||||
snprintf(SOC_temperature_c, sizeof SOC_temperature_c, "%.1f\u00B0C", SOC_temperatureF);
|
||||
snprintf(PCB_temperature_c, sizeof PCB_temperature_c, "%.1f\u00B0C", PCB_temperatureF);
|
||||
snprintf(skin_temperature_c, sizeof skin_temperature_c, "%d.%d\u00B0C", skin_temperaturemiliC / 1000, (skin_temperaturemiliC / 100) % 10);
|
||||
|
||||
snprintf(Rotation_SpeedLevel_c, sizeof Rotation_SpeedLevel_c, "%.1f%%", Rotation_Duty);
|
||||
|
||||
///FPS
|
||||
if (settings.showFPS == true) {
|
||||
snprintf(PFPS_value_c, sizeof PFPS_value_c, "%1u", FPS);
|
||||
snprintf(FPS_value_c, sizeof FPS_value_c, "%.1f", useOldFPSavg ? FPSavg_old : FPSavg);
|
||||
}
|
||||
|
||||
//Resolutions
|
||||
if ((settings.showRES == true) && GameRunning && NxFps) {
|
||||
if (!resolutionLookup) {
|
||||
(NxFps -> renderCalls[0].calls) = 0xFFFF;
|
||||
resolutionLookup = 1;
|
||||
}
|
||||
else if (resolutionLookup == 1) {
|
||||
if ((NxFps -> renderCalls[0].calls) != 0xFFFF) resolutionLookup = 2;
|
||||
}
|
||||
else {
|
||||
if (NxFps && SharedMemoryUsed) {
|
||||
memcpy(&m_resolutionRenderCalls, &(NxFps -> renderCalls), sizeof(m_resolutionRenderCalls));
|
||||
memcpy(&m_resolutionViewportCalls, &(NxFps -> viewportCalls), sizeof(m_resolutionViewportCalls));
|
||||
} else {
|
||||
memset(&m_resolutionRenderCalls, 0, sizeof(m_resolutionRenderCalls));
|
||||
memset(&m_resolutionViewportCalls, 0, sizeof(m_resolutionViewportCalls));
|
||||
}
|
||||
qsort(m_resolutionRenderCalls, 8, sizeof(resolutionCalls), compare);
|
||||
qsort(m_resolutionViewportCalls, 8, sizeof(resolutionCalls), compare);
|
||||
memset(&m_resolutionOutput, 0, sizeof(m_resolutionOutput));
|
||||
size_t out_iter = 0;
|
||||
bool found = false;
|
||||
for (size_t i = 0; i < 8; i++) {
|
||||
for (size_t x = 0; x < 8; x++) {
|
||||
if (m_resolutionRenderCalls[i].width == 0) {
|
||||
break;
|
||||
}
|
||||
if ((m_resolutionRenderCalls[i].width == m_resolutionViewportCalls[x].width) && (m_resolutionRenderCalls[i].height == m_resolutionViewportCalls[x].height)) {
|
||||
m_resolutionOutput[out_iter].width = m_resolutionRenderCalls[i].width;
|
||||
m_resolutionOutput[out_iter].height = m_resolutionRenderCalls[i].height;
|
||||
m_resolutionOutput[out_iter].calls = (m_resolutionRenderCalls[i].calls > m_resolutionViewportCalls[x].calls) ? m_resolutionRenderCalls[i].calls : m_resolutionViewportCalls[x].calls;
|
||||
out_iter++;
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!found && m_resolutionRenderCalls[i].width != 0) {
|
||||
m_resolutionOutput[out_iter].width = m_resolutionRenderCalls[i].width;
|
||||
m_resolutionOutput[out_iter].height = m_resolutionRenderCalls[i].height;
|
||||
m_resolutionOutput[out_iter].calls = m_resolutionRenderCalls[i].calls;
|
||||
out_iter++;
|
||||
}
|
||||
found = false;
|
||||
if (out_iter == 8) break;
|
||||
}
|
||||
if (out_iter < 8) {
|
||||
const size_t out_iter_s = out_iter;
|
||||
for (size_t x = 0; x < 8; x++) {
|
||||
for (size_t y = 0; y < out_iter_s; y++) {
|
||||
if (m_resolutionViewportCalls[x].width == 0) {
|
||||
break;
|
||||
}
|
||||
if ((m_resolutionViewportCalls[x].width == m_resolutionOutput[y].width) && (m_resolutionViewportCalls[x].height == m_resolutionOutput[y].height)) {
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!found && m_resolutionViewportCalls[x].width != 0) {
|
||||
m_resolutionOutput[out_iter].width = m_resolutionViewportCalls[x].width;
|
||||
m_resolutionOutput[out_iter].height = m_resolutionViewportCalls[x].height;
|
||||
m_resolutionOutput[out_iter].calls = m_resolutionViewportCalls[x].calls;
|
||||
out_iter++;
|
||||
}
|
||||
found = false;
|
||||
if (out_iter == 8) break;
|
||||
}
|
||||
}
|
||||
qsort(m_resolutionOutput, 8, sizeof(resolutionCalls), compare);
|
||||
static std::pair<uint16_t, uint16_t> old_res[2];
|
||||
|
||||
// Only swap if BOTH resolutions exist (prevent swapping with empty slot)
|
||||
if (m_resolutionOutput[0].width && m_resolutionOutput[1].width) {
|
||||
if ((m_resolutionOutput[0].width == old_res[1].first && m_resolutionOutput[0].height == old_res[1].second) ||
|
||||
(m_resolutionOutput[1].width == old_res[0].first && m_resolutionOutput[1].height == old_res[0].second)) {
|
||||
const uint16_t swap_width = m_resolutionOutput[0].width;
|
||||
const uint16_t swap_height = m_resolutionOutput[0].height;
|
||||
m_resolutionOutput[0].width = m_resolutionOutput[1].width;
|
||||
m_resolutionOutput[0].height = m_resolutionOutput[1].height;
|
||||
m_resolutionOutput[1].width = swap_width;
|
||||
m_resolutionOutput[1].height = swap_height;
|
||||
}
|
||||
}
|
||||
|
||||
//if (!m_resolutionOutput[1].width) {
|
||||
// snprintf(Resolutions_c, sizeof(Resolutions_c), "%dx%d", m_resolutionOutput[0].width, m_resolutionOutput[0].height);
|
||||
//}
|
||||
//else {
|
||||
// snprintf(Resolutions_c, sizeof(Resolutions_c), "%dx%d%dx%d", m_resolutionOutput[0].width, m_resolutionOutput[0].height, m_resolutionOutput[1].width, m_resolutionOutput[1].height);
|
||||
//}
|
||||
|
||||
if (!m_resolutionOutput[1].width || !m_resolutionOutput[0].width) {
|
||||
if (!m_resolutionOutput[1].width)
|
||||
snprintf(Resolutions_c, sizeof(Resolutions_c), "%dx%d", m_resolutionOutput[0].width, m_resolutionOutput[0].height);
|
||||
else snprintf(Resolutions_c, sizeof(Resolutions_c), "%dx%d", m_resolutionOutput[1].width, m_resolutionOutput[1].height);
|
||||
}
|
||||
else snprintf(Resolutions_c, sizeof(Resolutions_c),"%dx%d%dx%d", m_resolutionOutput[0].width, m_resolutionOutput[0].height, m_resolutionOutput[1].width, m_resolutionOutput[1].height);
|
||||
|
||||
old_res[0] = std::make_pair(m_resolutionOutput[0].width, m_resolutionOutput[0].height);
|
||||
old_res[1] = std::make_pair(m_resolutionOutput[1].width, m_resolutionOutput[1].height);
|
||||
}
|
||||
if (settings.showRDSD == true && GameRunning && NxFps) {
|
||||
if ((NxFps -> readSpeedPerSecond) != 0.f) snprintf(readSpeed_c, sizeof(readSpeed_c), "%.2f MiB/s", (NxFps -> readSpeedPerSecond) / 1048576.f);
|
||||
else snprintf(readSpeed_c, sizeof(readSpeed_c), "n/d");
|
||||
}
|
||||
}
|
||||
else if (!GameRunning && resolutionLookup != 0) {
|
||||
resolutionLookup = 0;
|
||||
}
|
||||
|
||||
mutexUnlock(&mutex_Misc);
|
||||
|
||||
/* ── Battery / power draw ───────────────────────────────────── */
|
||||
char remainingBatteryLife[8];
|
||||
|
||||
/* Normalise "-0.00" → "0.00" W */
|
||||
const float drawW = (fabsf(PowerConsumption) < 0.01f) ? 0.0f
|
||||
: PowerConsumption;
|
||||
|
||||
mutexLock(&mutex_BatteryChecker);
|
||||
|
||||
/* keep "--:--" whenever estimate is negative */
|
||||
if (batTimeEstimate >= 0 && !(drawW <= 0.01f && drawW >= -0.01f)) {
|
||||
snprintf(remainingBatteryLife, sizeof(remainingBatteryLife),
|
||||
"%d:%02d", batTimeEstimate / 60, batTimeEstimate % 60);
|
||||
} else {
|
||||
strcpy(remainingBatteryLife, "--:--");
|
||||
}
|
||||
|
||||
const float batteryPercent = (float)_batteryChargeInfoFields.RawBatteryCharge / 1000.0f;
|
||||
|
||||
snprintf(BatteryDraw_c, sizeof(BatteryDraw_c),
|
||||
"%.2f W%.0f%% [%s]",
|
||||
drawW,
|
||||
batteryPercent,
|
||||
remainingBatteryLife);
|
||||
|
||||
mutexUnlock(&mutex_BatteryChecker);
|
||||
|
||||
if (!skipOnce) {
|
||||
if (runOnce) {
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
runOnce = false;
|
||||
}
|
||||
} else {
|
||||
skipOnce = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
virtual bool handleInput(u64 keysDown, u64 keysHeld, const HidTouchState &touchPos, HidAnalogStickState joyStickPosLeft, HidAnalogStickState joyStickPosRight) override {
|
||||
if (isKeyComboPressed(keysHeld, keysDown)) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerExitSound.store(true, std::memory_order_release);
|
||||
skipOnce = true;
|
||||
runOnce = true;
|
||||
TeslaFPS = 60;
|
||||
lastSelectedItem = "Full";
|
||||
lastMode = "";
|
||||
tsl::swapTo<MainMenu>();
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
};
|
||||
1137
Source/Horizon-OC-Monitor/source/modes/Micro.hpp
Normal file
1137
Source/Horizon-OC-Monitor/source/modes/Micro.hpp
Normal file
File diff suppressed because it is too large
Load Diff
1649
Source/Horizon-OC-Monitor/source/modes/Mini.hpp
Normal file
1649
Source/Horizon-OC-Monitor/source/modes/Mini.hpp
Normal file
File diff suppressed because it is too large
Load Diff
189
Source/Horizon-OC-Monitor/source/modes/Misc.hpp
Normal file
189
Source/Horizon-OC-Monitor/source/modes/Misc.hpp
Normal file
@@ -0,0 +1,189 @@
|
||||
class OtherMenu;
|
||||
|
||||
void StartMiscThread() {
|
||||
// Wait for existing thread to exit
|
||||
threadWaitForExit(&t0);
|
||||
|
||||
// Clear the thread exit event for new thread
|
||||
leventClear(&threadexit);
|
||||
|
||||
// Close and recreate thread
|
||||
threadClose(&t0);
|
||||
threadCreate(&t0, Misc2, NULL, NULL, 0x1000, 0x3F, 3);
|
||||
threadStart(&t0);
|
||||
}
|
||||
|
||||
void EndMiscThread() {
|
||||
// Signal the thread exit event
|
||||
leventSignal(&threadexit);
|
||||
|
||||
// Wait for thread to exit
|
||||
threadWaitForExit(&t0);
|
||||
|
||||
// Close thread handle
|
||||
threadClose(&t0);
|
||||
}
|
||||
|
||||
class MiscOverlay : public tsl::Gui {
|
||||
private:
|
||||
char DSP_Load_c[16];
|
||||
// Separated value buffers for NV clocks
|
||||
char NVDEC_value_c[16] = "";
|
||||
char NVENC_value_c[16] = "";
|
||||
char NVJPG_value_c[16] = "";
|
||||
char Nifm_pass[96];
|
||||
FullSettings settings;
|
||||
public:
|
||||
MiscOverlay() {
|
||||
GetConfigSettings(&settings);
|
||||
disableJumpTo = true;
|
||||
smInitialize();
|
||||
nifmCheck = nifmInitialize(NifmServiceType_Admin);
|
||||
if (R_SUCCEEDED(mmuInitialize())) {
|
||||
nvdecCheck = mmuRequestInitialize(&nvdecRequest, MmuModuleId(5), 8, false);
|
||||
nvencCheck = mmuRequestInitialize(&nvencRequest, MmuModuleId(6), 8, false);
|
||||
nvjpgCheck = mmuRequestInitialize(&nvjpgRequest, MmuModuleId(7), 8, false);
|
||||
}
|
||||
|
||||
if (R_SUCCEEDED(audsnoopInitialize()))
|
||||
audsnoopCheck = audsnoopEnableDspUsageMeasurement();
|
||||
|
||||
smExit();
|
||||
StartMiscThread();
|
||||
//tsl::elm::g_disableMenuCacheOnReturn.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
~MiscOverlay() {
|
||||
EndMiscThread();
|
||||
nifmExit();
|
||||
mmuRequestFinalize(&nvdecRequest);
|
||||
mmuRequestFinalize(&nvencRequest);
|
||||
mmuRequestFinalize(&nvjpgRequest);
|
||||
mmuExit();
|
||||
if (R_SUCCEEDED(audsnoopCheck)) {
|
||||
audsnoopDisableDspUsageMeasurement();
|
||||
}
|
||||
audsnoopExit();
|
||||
}
|
||||
|
||||
virtual tsl::elm::Element* createUI() override {
|
||||
|
||||
auto* Status = new tsl::elm::CustomDrawer([this](tsl::gfx::Renderer *renderer, u16 x, u16 y, u16 w, u16 h) {
|
||||
static constexpr u16 X_OFFSET = 30;
|
||||
static constexpr u16 NV_VALUE_X = 120; // Aligned X position for NV values
|
||||
|
||||
///DSP
|
||||
if (R_SUCCEEDED(audsnoopCheck)) {
|
||||
renderer->drawString(DSP_Load_c, false, X_OFFSET, 120, 20, (settings.textColor));
|
||||
}
|
||||
|
||||
//Multimedia engines
|
||||
if (R_SUCCEEDED(nvdecCheck | nvencCheck | nvjpgCheck)) {
|
||||
renderer->drawString("Multimedia Clock Rates", false, X_OFFSET, 165, 20, (settings.catColor1));
|
||||
|
||||
u16 currentY = 185;
|
||||
|
||||
if (R_SUCCEEDED(nvdecCheck)) {
|
||||
renderer->drawString("NVDEC", false, X_OFFSET+15, currentY, 15, (settings.catColor2));
|
||||
renderer->drawString(NVDEC_value_c, false, NV_VALUE_X, currentY, 15, (settings.textColor));
|
||||
currentY += 15;
|
||||
}
|
||||
if (R_SUCCEEDED(nvencCheck)) {
|
||||
renderer->drawString("NVENC", false, X_OFFSET+15, currentY, 15, (settings.catColor2));
|
||||
renderer->drawString(NVENC_value_c, false, NV_VALUE_X, currentY, 15, (settings.textColor));
|
||||
currentY += 15;
|
||||
}
|
||||
if (R_SUCCEEDED(nvjpgCheck)) {
|
||||
renderer->drawString("NVJPG", false, X_OFFSET+15, currentY, 15, (settings.catColor2));
|
||||
renderer->drawString(NVJPG_value_c, false, NV_VALUE_X, currentY, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
|
||||
if (R_SUCCEEDED(nifmCheck)) {
|
||||
renderer->drawString("Network", false, X_OFFSET, 255, 20, (settings.catColor1));
|
||||
if (!Nifm_internet_rc) {
|
||||
if (NifmConnectionType == NifmInternetConnectionType_WiFi) {
|
||||
renderer->drawString("Type: Wi-Fi", false, X_OFFSET, 280, 18, (settings.catColor2));
|
||||
if (!Nifm_profile_rc) {
|
||||
if (Nifm_showpass)
|
||||
renderer->drawString(Nifm_pass, false, X_OFFSET, 305, 15, (settings.textColor));
|
||||
else
|
||||
renderer->drawString("Press Y to show password", false, X_OFFSET, 305, 15, (settings.textColor));
|
||||
}
|
||||
}
|
||||
else if (NifmConnectionType == NifmInternetConnectionType_Ethernet)
|
||||
renderer->drawString("Type: Ethernet", false, X_OFFSET, 280, 18, (settings.textColor));
|
||||
}
|
||||
else
|
||||
renderer->drawString("Type: Not connected", false, X_OFFSET, 280, 18, (settings.textColor));
|
||||
}
|
||||
|
||||
|
||||
});
|
||||
|
||||
//tsl::elm::g_disableMenuCacheOnReturn.store(true, std::memory_order_release);
|
||||
tsl::elm::HeaderOverlayFrame* rootFrame = new tsl::elm::HeaderOverlayFrame("Status Monitor", APP_VERSION, true);
|
||||
rootFrame->setContent(Status);
|
||||
|
||||
return rootFrame;
|
||||
}
|
||||
|
||||
virtual void update() override {
|
||||
|
||||
snprintf(DSP_Load_c, sizeof DSP_Load_c, "DSP usage: %u%%", DSP_Load_u);
|
||||
|
||||
// Format just the values for NV clocks
|
||||
snprintf(NVDEC_value_c, sizeof(NVDEC_value_c), "%.1f MHz", (float)NVDEC_Hz / 1000000);
|
||||
snprintf(NVENC_value_c, sizeof(NVENC_value_c), "%.1f MHz", (float)NVENC_Hz / 1000000);
|
||||
snprintf(NVJPG_value_c, sizeof(NVJPG_value_c), "%.1f MHz", (float)NVJPG_Hz / 1000000);
|
||||
|
||||
char pass_temp1[25] = "";
|
||||
char pass_temp2[25] = "";
|
||||
char pass_temp3[17] = "";
|
||||
if (Nifm_profile.wireless_setting_data.passphrase_len > 48) {
|
||||
memcpy(&pass_temp1, &(Nifm_profile.wireless_setting_data.passphrase[0]), 24);
|
||||
memcpy(&pass_temp2, &(Nifm_profile.wireless_setting_data.passphrase[24]), 24);
|
||||
memcpy(&pass_temp3, &(Nifm_profile.wireless_setting_data.passphrase[48]), 16);
|
||||
}
|
||||
else if (Nifm_profile.wireless_setting_data.passphrase_len > 24) {
|
||||
memcpy(&pass_temp1, &(Nifm_profile.wireless_setting_data.passphrase[0]), 24);
|
||||
memcpy(&pass_temp2, &(Nifm_profile.wireless_setting_data.passphrase[24]), 24);
|
||||
}
|
||||
else {
|
||||
memcpy(&pass_temp1, &(Nifm_profile.wireless_setting_data.passphrase[0]), 24);
|
||||
}
|
||||
snprintf(Nifm_pass, sizeof Nifm_pass, "%s\n%s\n%s", pass_temp1, pass_temp2, pass_temp3);
|
||||
|
||||
static bool skipOnce = true;
|
||||
|
||||
if (!skipOnce) {
|
||||
static bool runOnce = true;
|
||||
if (runOnce) {
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
runOnce = false;
|
||||
}
|
||||
} else {
|
||||
skipOnce = false;
|
||||
}
|
||||
}
|
||||
|
||||
virtual bool handleInput(u64 keysDown, u64 keysHeld, const HidTouchState &touchPos, HidAnalogStickState joyStickPosLeft, HidAnalogStickState joyStickPosRight) override {
|
||||
if (keysHeld & KEY_Y) {
|
||||
Nifm_showpass = true;
|
||||
}
|
||||
else Nifm_showpass = false;
|
||||
|
||||
if (keysDown & KEY_B) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerExitSound.store(true, std::memory_order_release);
|
||||
lastSelectedItem = "Miscellaneous";
|
||||
lastMode = "";
|
||||
tsl::swapTo<OtherMenu>();
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
};
|
||||
581
Source/Horizon-OC-Monitor/source/modes/Resolutions.hpp
Normal file
581
Source/Horizon-OC-Monitor/source/modes/Resolutions.hpp
Normal file
@@ -0,0 +1,581 @@
|
||||
class MainMenu;
|
||||
|
||||
class ResolutionsOverlay : public tsl::Gui {
|
||||
private:
|
||||
char Resolutions_c[512] = {0};
|
||||
char Resolutions2_c[512] = {0};
|
||||
ResolutionSettings settings;
|
||||
bool skipOnce = true;
|
||||
bool runOnce = true;
|
||||
|
||||
// Repositioning variables (matching Mini)
|
||||
int frameOffsetX = 0;
|
||||
int frameOffsetY = 0;
|
||||
bool isDragging = false;
|
||||
size_t framePadding = 10;
|
||||
static constexpr int screenWidth = 1280;
|
||||
static constexpr int screenHeight = 720;
|
||||
|
||||
bool originalUseRightAlignment = ult::useRightAlignment;
|
||||
|
||||
struct ButtonState {
|
||||
std::atomic<bool> minusDragActive{false};
|
||||
std::atomic<bool> plusDragActive{false};
|
||||
} buttonState;
|
||||
|
||||
Thread touchPollThread;
|
||||
std::atomic<bool> touchPollRunning{false};
|
||||
|
||||
std::atomic<bool> inputDetected{false};
|
||||
|
||||
public:
|
||||
ResolutionsOverlay() {
|
||||
tsl::hlp::requestForeground(false);
|
||||
disableJumpTo = true;
|
||||
GetConfigSettings(&settings);
|
||||
|
||||
// Load saved frame offsets
|
||||
frameOffsetX = settings.frameOffsetX;
|
||||
frameOffsetY = settings.frameOffsetY;
|
||||
framePadding = settings.framePadding;
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().removeScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = true;
|
||||
FullMode = false;
|
||||
TeslaFPS = settings.refreshRate;
|
||||
StartFPSCounterThread();
|
||||
|
||||
// Start touch polling thread for instant response at low FPS
|
||||
touchPollRunning.store(true, std::memory_order_release);
|
||||
threadCreate(&touchPollThread, [](void* arg) -> void {
|
||||
ResolutionsOverlay* overlay = static_cast<ResolutionsOverlay*>(arg);
|
||||
|
||||
// Allow only Player 1 and handheld mode
|
||||
const HidNpadIdType id_list[2] = { HidNpadIdType_No1, HidNpadIdType_Handheld };
|
||||
|
||||
// Configure HID system to only listen to these IDs
|
||||
hidSetSupportedNpadIdType(id_list, 2);
|
||||
|
||||
// Configure input for up to 2 supported controllers (P1 + Handheld)
|
||||
padConfigureInput(2, HidNpadStyleSet_NpadStandard | HidNpadStyleTag_NpadSystemExt);
|
||||
|
||||
// Initialize separate pad states for both controllers
|
||||
PadState pad_p1;
|
||||
PadState pad_handheld;
|
||||
padInitialize(&pad_p1, HidNpadIdType_No1);
|
||||
padInitialize(&pad_handheld, HidNpadIdType_Handheld);
|
||||
|
||||
u64 minusHoldStart = 0;
|
||||
u64 plusHoldStart = 0;
|
||||
static constexpr u64 HOLD_THRESHOLD_NS = 500'000'000ULL;
|
||||
|
||||
HidTouchScreenState state = {0};
|
||||
|
||||
|
||||
while (overlay->touchPollRunning.load(std::memory_order_acquire)) {
|
||||
// Only poll when rendering and not dragging
|
||||
{
|
||||
overlay->inputDetected.store(false, std::memory_order_release);
|
||||
|
||||
// Check touch in bounds
|
||||
if (hidGetTouchScreenStates(&state, 1) && state.count > 0) {
|
||||
const int touchX = state.touches[0].x;
|
||||
const int touchY = state.touches[0].y;
|
||||
|
||||
// Calculate bounds (same logic as handleInput)
|
||||
const int overlayX = overlay->frameOffsetX;
|
||||
const int overlayY = overlay->frameOffsetY;
|
||||
|
||||
// Overlay dimensions based on game state
|
||||
int overlayWidth, overlayHeight;
|
||||
overlayWidth = 360-20;
|
||||
overlayHeight = 200;
|
||||
|
||||
// Add touch padding
|
||||
const int touchPadding = 4;
|
||||
const int touchableX = overlayX - touchPadding;
|
||||
const int touchableY = overlayY - touchPadding;
|
||||
const int touchableWidth = overlayWidth + (touchPadding * 2);
|
||||
const int touchableHeight = overlayHeight + (touchPadding * 2);
|
||||
|
||||
// Check if touch is within bounds
|
||||
if (touchX >= touchableX && touchX <= touchableX + touchableWidth &&
|
||||
touchY >= touchableY && touchY <= touchableY + touchableHeight) {
|
||||
overlay->inputDetected.store(true, std::memory_order_release);
|
||||
}
|
||||
}
|
||||
|
||||
// Poll buttons from both controllers
|
||||
padUpdate(&pad_p1);
|
||||
padUpdate(&pad_handheld);
|
||||
|
||||
// Combine input from both controllers
|
||||
const u64 keysHeld = padGetButtons(&pad_p1) | padGetButtons(&pad_handheld);
|
||||
const u64 now = armTicksToNs(armGetSystemTick());
|
||||
|
||||
// Track MINUS hold duration
|
||||
if ((keysHeld & KEY_MINUS) && !(keysHeld & ~KEY_MINUS & ALL_KEYS_MASK)) {
|
||||
if (minusHoldStart == 0) {
|
||||
minusHoldStart = now;
|
||||
}
|
||||
if (now - minusHoldStart >= HOLD_THRESHOLD_NS) {
|
||||
// Long enough to start drag
|
||||
overlay->inputDetected.store(true, std::memory_order_release);
|
||||
overlay->buttonState.minusDragActive.exchange(true, std::memory_order_acq_rel);
|
||||
}
|
||||
}
|
||||
|
||||
// Track PLUS hold duration
|
||||
else if ((keysHeld & KEY_PLUS) && !(keysHeld & ~KEY_PLUS & ALL_KEYS_MASK)) {
|
||||
if (plusHoldStart == 0) {
|
||||
plusHoldStart = now;
|
||||
}
|
||||
if (now - plusHoldStart >= HOLD_THRESHOLD_NS) {
|
||||
// Long enough to start drag
|
||||
overlay->inputDetected.store(true, std::memory_order_release);
|
||||
overlay->buttonState.plusDragActive.exchange(true, std::memory_order_acq_rel);
|
||||
}
|
||||
}
|
||||
|
||||
else {
|
||||
minusHoldStart = plusHoldStart = 0;
|
||||
overlay->buttonState.minusDragActive.exchange(false, std::memory_order_acq_rel);
|
||||
overlay->buttonState.plusDragActive.exchange(false, std::memory_order_acq_rel);
|
||||
}
|
||||
|
||||
// Disable rendering on any input, re-enable when no input
|
||||
static bool resetOnce = true;
|
||||
if (overlay->inputDetected.load(std::memory_order_acquire)) {
|
||||
if (resetOnce && isRendering) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
resetOnce = false;
|
||||
}
|
||||
} else {
|
||||
resetOnce = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
static auto lastUnderscanPixels = std::make_pair(0, 0);
|
||||
|
||||
if (lastUnderscanPixels != tsl::impl::currentUnderscanPixels) {
|
||||
for (int i = 0; i < 2; i++) {
|
||||
tsl::gfx::Renderer::get().updateLayerSize();
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(overlay->frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
}
|
||||
lastUnderscanPixels = tsl::impl::currentUnderscanPixels;
|
||||
}
|
||||
|
||||
svcSleepThread(16000000ULL*2); // 16ms polling
|
||||
}
|
||||
}, this, NULL, 0x1000, 0x2B, -2);
|
||||
threadStart(&touchPollThread);
|
||||
}
|
||||
|
||||
~ResolutionsOverlay() {
|
||||
// Stop touch polling thread
|
||||
touchPollRunning.store(false, std::memory_order_release);
|
||||
threadWaitForExit(&touchPollThread);
|
||||
threadClose(&touchPollThread);
|
||||
|
||||
EndFPSCounterThread();
|
||||
TeslaFPS = 60;
|
||||
if (settings.disableScreenshots) {
|
||||
tsl::gfx::Renderer::get().addScreenshotStacks();
|
||||
}
|
||||
deactivateOriginalFooter = false;
|
||||
ult::useRightAlignment = originalUseRightAlignment;
|
||||
fixForeground = true;
|
||||
FullMode = true;
|
||||
}
|
||||
|
||||
resolutionCalls m_resolutionRenderCalls[8] = {0};
|
||||
resolutionCalls m_resolutionViewportCalls[8] = {0};
|
||||
bool gameStart = false;
|
||||
uint8_t resolutionLookup = 0;
|
||||
u64 lastGameSeenTick = 0;
|
||||
bool waitingForGame = true;
|
||||
|
||||
virtual tsl::elm::Element* createUI() override {
|
||||
|
||||
auto* Status = new tsl::elm::CustomDrawer([this](tsl::gfx::Renderer *renderer, u16 x, u16 y, u16 w, u16 h) {
|
||||
int base_y = 0;
|
||||
int base_x = 0;
|
||||
int clippingOffsetX = 0, clippingOffsetY = 0;
|
||||
|
||||
int total_width = 360 - 20;
|
||||
int total_height = 200;
|
||||
|
||||
// Check clipping bounds (same as before)
|
||||
if (base_x + frameOffsetX < int(framePadding))
|
||||
clippingOffsetX = framePadding - (base_x + frameOffsetX);
|
||||
else if ((base_x + frameOffsetX + total_width) > static_cast<int>(screenWidth - framePadding))
|
||||
clippingOffsetX = (screenWidth - framePadding) - (base_x + frameOffsetX + total_width);
|
||||
|
||||
if (base_y + frameOffsetY < int(framePadding))
|
||||
clippingOffsetY = framePadding - (base_y + frameOffsetY);
|
||||
else if ((base_y + frameOffsetY + total_height) > static_cast<int>(screenHeight - framePadding))
|
||||
clippingOffsetY = (screenHeight - framePadding) - (base_y + frameOffsetY + total_height);
|
||||
|
||||
int _frameOffsetX = ult::limitedMemory ? std::max(0, frameOffsetX - (1280-448)) : frameOffsetX;
|
||||
|
||||
const int final_base_x = base_x + _frameOffsetX + clippingOffsetX;
|
||||
const int final_base_y = base_y + frameOffsetY + clippingOffsetY;
|
||||
|
||||
const tsl::Color bgColor = !isDragging ? settings.backgroundColor : settings.focusBackgroundColor;
|
||||
|
||||
const u64 curTick = armGetSystemTick();
|
||||
|
||||
// guard: ensure lastGameSeenTick is initialized to something reasonable
|
||||
if (lastGameSeenTick == 0) lastGameSeenTick = curTick;
|
||||
|
||||
// threshold in ns (100 ms)
|
||||
static constexpr u64 CHECK_NS = 2000000000ULL;
|
||||
|
||||
// Game detected
|
||||
if (gameStart && NxFps && NxFps->API >= 1 && (Resolutions_c[0] != '\0' && Resolutions2_c[0] != '\0')) {
|
||||
lastGameSeenTick = curTick;
|
||||
waitingForGame = true; // reset waiting state so next missing cycle shows "Checking..."
|
||||
renderer->drawRoundedRectSingleThreaded(final_base_x, final_base_y, total_width, total_height, 16, aWithOpacity(bgColor));
|
||||
|
||||
int xOffset = 10;
|
||||
int yOffset = 10;
|
||||
renderer->drawString("Depth", false, xOffset + final_base_x + 20, yOffset + final_base_y + 20, 20, settings.catColor);
|
||||
renderer->drawString(Resolutions_c, false, xOffset + final_base_x + 20, yOffset + final_base_y + 55, 18, settings.textColor);
|
||||
renderer->drawString("Viewport", false, xOffset + final_base_x + 180, yOffset + final_base_y + 20, 20, settings.catColor);
|
||||
renderer->drawString(Resolutions2_c, false, xOffset + final_base_x + 180, yOffset + final_base_y + 55, 18, settings.textColor);
|
||||
}
|
||||
// Game not detected
|
||||
else {
|
||||
renderer->drawRoundedRectSingleThreaded(final_base_x, final_base_y, total_width, total_height, 16, aWithOpacity(bgColor));
|
||||
|
||||
// Check elapsed time since last game detection
|
||||
u64 elapsed_ns = armTicksToNs(curTick - lastGameSeenTick);
|
||||
const bool under100ms = (elapsed_ns < CHECK_NS); // 100ms
|
||||
|
||||
std::string msg;
|
||||
if (under100ms && waitingForGame)
|
||||
msg = "Checking for game...";
|
||||
else {
|
||||
msg = "Game is not running\nor is incompatible.";
|
||||
waitingForGame = false;
|
||||
}
|
||||
|
||||
const auto [textWidth, textHeight] = renderer->getTextDimensions(msg, false, 20);
|
||||
const int text_x = final_base_x + (total_width - textWidth) / 2;
|
||||
const int text_y = final_base_y + (total_height) / 2;
|
||||
|
||||
renderer->drawString(msg, false, text_x, (under100ms && waitingForGame) ? text_y+textHeight/2 : text_y, 20, (under100ms && waitingForGame) ? 0xFFFF : 0xF00F);
|
||||
}
|
||||
});
|
||||
|
||||
tsl::elm::HeaderOverlayFrame* rootFrame = new tsl::elm::HeaderOverlayFrame("", "");
|
||||
rootFrame->setContent(Status);
|
||||
|
||||
return rootFrame;
|
||||
}
|
||||
|
||||
virtual void update() override {
|
||||
|
||||
if (gameStart && NxFps) {
|
||||
if (!resolutionLookup) {
|
||||
NxFps -> renderCalls[0].calls = 0xFFFF;
|
||||
resolutionLookup = 1;
|
||||
}
|
||||
else if (resolutionLookup == 1) {
|
||||
if ((NxFps -> renderCalls[0].calls) != 0xFFFF) resolutionLookup = 2;
|
||||
else return;
|
||||
}
|
||||
memcpy(&m_resolutionRenderCalls, &(NxFps -> renderCalls), sizeof(m_resolutionRenderCalls));
|
||||
memcpy(&m_resolutionViewportCalls, &(NxFps -> viewportCalls), sizeof(m_resolutionViewportCalls));
|
||||
qsort(m_resolutionRenderCalls, 8, sizeof(resolutionCalls), compare);
|
||||
qsort(m_resolutionViewportCalls, 8, sizeof(resolutionCalls), compare);
|
||||
snprintf(Resolutions_c, sizeof Resolutions_c,
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d",
|
||||
m_resolutionRenderCalls[0].width, m_resolutionRenderCalls[0].height, m_resolutionRenderCalls[0].calls,
|
||||
m_resolutionRenderCalls[1].width, m_resolutionRenderCalls[1].height, m_resolutionRenderCalls[1].calls,
|
||||
m_resolutionRenderCalls[2].width, m_resolutionRenderCalls[2].height, m_resolutionRenderCalls[2].calls,
|
||||
m_resolutionRenderCalls[3].width, m_resolutionRenderCalls[3].height, m_resolutionRenderCalls[3].calls,
|
||||
m_resolutionRenderCalls[4].width, m_resolutionRenderCalls[4].height, m_resolutionRenderCalls[4].calls,
|
||||
m_resolutionRenderCalls[5].width, m_resolutionRenderCalls[5].height, m_resolutionRenderCalls[5].calls,
|
||||
m_resolutionRenderCalls[6].width, m_resolutionRenderCalls[6].height, m_resolutionRenderCalls[6].calls,
|
||||
m_resolutionRenderCalls[7].width, m_resolutionRenderCalls[7].height, m_resolutionRenderCalls[7].calls
|
||||
);
|
||||
snprintf(Resolutions2_c, sizeof Resolutions2_c,
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d\n"
|
||||
"%dx%d, %d",
|
||||
m_resolutionViewportCalls[0].width, m_resolutionViewportCalls[0].height, m_resolutionViewportCalls[0].calls,
|
||||
m_resolutionViewportCalls[1].width, m_resolutionViewportCalls[1].height, m_resolutionViewportCalls[1].calls,
|
||||
m_resolutionViewportCalls[2].width, m_resolutionViewportCalls[2].height, m_resolutionViewportCalls[2].calls,
|
||||
m_resolutionViewportCalls[3].width, m_resolutionViewportCalls[3].height, m_resolutionViewportCalls[3].calls,
|
||||
m_resolutionViewportCalls[4].width, m_resolutionViewportCalls[4].height, m_resolutionViewportCalls[4].calls,
|
||||
m_resolutionViewportCalls[5].width, m_resolutionViewportCalls[5].height, m_resolutionViewportCalls[5].calls,
|
||||
m_resolutionViewportCalls[6].width, m_resolutionViewportCalls[6].height, m_resolutionViewportCalls[6].calls,
|
||||
m_resolutionViewportCalls[7].width, m_resolutionViewportCalls[7].height, m_resolutionViewportCalls[7].calls
|
||||
);
|
||||
}
|
||||
if (FPSavg < 254) {
|
||||
gameStart = true;
|
||||
}
|
||||
else {
|
||||
gameStart = false;
|
||||
resolutionLookup = false;
|
||||
}
|
||||
|
||||
if (!skipOnce) {
|
||||
if (runOnce) {
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
runOnce = false;
|
||||
}
|
||||
} else {
|
||||
skipOnce = false;
|
||||
}
|
||||
}
|
||||
|
||||
virtual bool handleInput(u64 keysDown, u64 keysHeld, const HidTouchState &touchPos, HidAnalogStickState joyStickPosLeft, HidAnalogStickState joyStickPosRight) override {
|
||||
// Static variables to maintain drag state between function calls
|
||||
static bool oldTouchDetected = false;
|
||||
static bool oldMinusHeld = false;
|
||||
static bool oldPlusHeld = false;
|
||||
static HidTouchState initialTouchPos = {0};
|
||||
static int initialFrameOffsetX = 0;
|
||||
static int initialFrameOffsetY = 0;
|
||||
static constexpr int TOUCH_THRESHOLD = 8;
|
||||
static bool hasMoved = false;
|
||||
|
||||
// Better touch detection - check if coordinates are within reasonable screen bounds
|
||||
const bool currentTouchDetected = (touchPos.x > 0 && touchPos.y > 0 &&
|
||||
touchPos.x < screenWidth && touchPos.y < screenHeight);
|
||||
|
||||
static bool clearOnRelease = false;
|
||||
|
||||
if (clearOnRelease && !isRendering) {
|
||||
clearOnRelease = false;
|
||||
isRendering = true;
|
||||
leventClear(&renderingStopEvent);
|
||||
}
|
||||
|
||||
// Calculate overlay bounds
|
||||
// Cache bounds calculation
|
||||
static int cachedBaseX = 0;
|
||||
static int cachedBaseY = 0;
|
||||
static bool boundsNeedUpdate = true;
|
||||
|
||||
// Only recalculate bounds when needed
|
||||
if (boundsNeedUpdate) {
|
||||
cachedBaseX = 0;
|
||||
cachedBaseY = 0;
|
||||
boundsNeedUpdate = false;
|
||||
}
|
||||
|
||||
const int overlayX = cachedBaseX + frameOffsetX;
|
||||
const int overlayY = cachedBaseY + frameOffsetY;
|
||||
|
||||
// Overlay dimensions based on game state
|
||||
int overlayWidth, overlayHeight;
|
||||
overlayWidth = 360-20;
|
||||
overlayHeight = 200;
|
||||
|
||||
// Add padding to make touch detection more forgiving
|
||||
static constexpr int touchPadding = 4;
|
||||
const int touchableX = overlayX - touchPadding;
|
||||
const int touchableY = overlayY - touchPadding;
|
||||
const int touchableWidth = overlayWidth + (touchPadding * 2);
|
||||
const int touchableHeight = overlayHeight + (touchPadding * 2);
|
||||
|
||||
// Screen boundaries for clamping
|
||||
const int minX = -cachedBaseX + framePadding;
|
||||
const int maxX = screenWidth - overlayWidth - cachedBaseX - framePadding;
|
||||
const int minY = -cachedBaseY + framePadding;
|
||||
const int maxY = screenHeight - overlayHeight - cachedBaseY - framePadding;
|
||||
|
||||
const bool minusDragReady = buttonState.minusDragActive.load(std::memory_order_acquire);
|
||||
const bool plusDragReady = buttonState.plusDragActive.load(std::memory_order_acquire);
|
||||
|
||||
// Check button states
|
||||
const bool currentMinusHeld = (keysHeld & KEY_MINUS) && !(keysHeld & ~KEY_MINUS & ALL_KEYS_MASK) && minusDragReady;
|
||||
const bool currentPlusHeld = (keysHeld & KEY_PLUS) && !(keysHeld & ~KEY_PLUS & ALL_KEYS_MASK) && plusDragReady;
|
||||
|
||||
// Handle touch dragging
|
||||
if (currentTouchDetected && !isDragging) {
|
||||
const int touchX = touchPos.x;
|
||||
const int touchY = touchPos.y;
|
||||
|
||||
if (!oldTouchDetected) {
|
||||
// Touch just started - check if within overlay bounds
|
||||
if (touchX >= touchableX && touchX <= touchableX + touchableWidth &&
|
||||
touchY >= touchableY && touchY <= touchableY + touchableHeight) {
|
||||
|
||||
// Start touch dragging
|
||||
isDragging = true;
|
||||
triggerRumbleClick.store(true, std::memory_order_release);
|
||||
triggerOnSound.store(true, std::memory_order_release);
|
||||
hasMoved = false;
|
||||
initialTouchPos = touchPos;
|
||||
initialFrameOffsetX = frameOffsetX;
|
||||
initialFrameOffsetY = frameOffsetY;
|
||||
}
|
||||
}
|
||||
} else if (currentTouchDetected && isDragging && !currentMinusHeld && !currentPlusHeld) {
|
||||
// Continue touch dragging
|
||||
const int touchX = touchPos.x;
|
||||
const int touchY = touchPos.y;
|
||||
const int deltaX = touchX - initialTouchPos.x;
|
||||
const int deltaY = touchY - initialTouchPos.y;
|
||||
|
||||
// Check if we've moved enough to consider this a drag
|
||||
if (!hasMoved) {
|
||||
const int totalMovement = abs(deltaX) + abs(deltaY);
|
||||
if (totalMovement >= TOUCH_THRESHOLD) {
|
||||
hasMoved = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (hasMoved) {
|
||||
// Update frame offsets with boundary checking
|
||||
const int newFrameOffsetX = std::max(minX, std::min(maxX, initialFrameOffsetX + deltaX));
|
||||
const int newFrameOffsetY = std::max(minY, std::min(maxY, initialFrameOffsetY + deltaY));
|
||||
|
||||
frameOffsetX = newFrameOffsetX;
|
||||
frameOffsetY = newFrameOffsetY;
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
|
||||
boundsNeedUpdate = true;
|
||||
}
|
||||
} else if (!currentTouchDetected && oldTouchDetected && isDragging && !currentMinusHeld && !currentPlusHeld) {
|
||||
// Touch just released
|
||||
if (hasMoved) {
|
||||
// Save position when touch drag ends
|
||||
auto iniData = ult::getParsedDataFromIniFile(configIniPath);
|
||||
iniData["game_resolutions"]["frame_offset_x"] = std::to_string(frameOffsetX);
|
||||
iniData["game_resolutions"]["frame_offset_y"] = std::to_string(frameOffsetY);
|
||||
ult::saveIniFileData(configIniPath, iniData);
|
||||
}
|
||||
|
||||
// Reset touch drag state
|
||||
isDragging = false;
|
||||
hasMoved = false;
|
||||
clearOnRelease = true;
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerOffSound.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
// Handle joystick dragging (MINUS + right joystick OR PLUS + left joystick)
|
||||
if ((currentMinusHeld || currentPlusHeld) && !isDragging) {
|
||||
// Start joystick dragging
|
||||
isDragging = true;
|
||||
triggerRumbleClick.store(true, std::memory_order_release);
|
||||
triggerOnSound.store(true, std::memory_order_release);
|
||||
} else if ((currentMinusHeld || currentPlusHeld) && isDragging) {
|
||||
// Continue joystick dragging
|
||||
static constexpr int JOYSTICK_DEADZONE = 20;
|
||||
|
||||
// Choose the appropriate joystick based on which button is held
|
||||
const HidAnalogStickState& activeJoystick = currentMinusHeld ? joyStickPosRight : joyStickPosLeft;
|
||||
|
||||
// Only move if joystick is outside deadzone
|
||||
if (abs(activeJoystick.x) > JOYSTICK_DEADZONE || abs(activeJoystick.y) > JOYSTICK_DEADZONE) {
|
||||
// Calculate joystick magnitude
|
||||
const float magnitude = sqrt((float)(activeJoystick.x * activeJoystick.x + activeJoystick.y * activeJoystick.y));
|
||||
const float normalizedMagnitude = magnitude / 32767.0f;
|
||||
|
||||
// Smooth curve for sensitivity
|
||||
static constexpr float baseSensitivity = 0.00008f;
|
||||
static constexpr float maxSensitivity = 0.0005f;
|
||||
|
||||
const float curveValue = pow(normalizedMagnitude, 8.0f);
|
||||
const float currentSensitivity = baseSensitivity + (maxSensitivity - baseSensitivity) * curveValue;
|
||||
|
||||
// Calculate movement delta with fractional accumulation
|
||||
static float accumulatedX = 0.0f;
|
||||
static float accumulatedY = 0.0f;
|
||||
|
||||
accumulatedX += (float)activeJoystick.x * currentSensitivity;
|
||||
accumulatedY += -(float)activeJoystick.y * currentSensitivity;
|
||||
|
||||
const int deltaX = (int)accumulatedX;
|
||||
const int deltaY = (int)accumulatedY;
|
||||
accumulatedX -= deltaX;
|
||||
accumulatedY -= deltaY;
|
||||
|
||||
// Update frame offsets with boundary checking
|
||||
const int newFrameOffsetX = std::max(minX, std::min(maxX, frameOffsetX + deltaX));
|
||||
const int newFrameOffsetY = std::max(minY, std::min(maxY, frameOffsetY + deltaY));
|
||||
|
||||
frameOffsetX = newFrameOffsetX;
|
||||
frameOffsetY = newFrameOffsetY;
|
||||
|
||||
if (ult::limitedMemory) {
|
||||
tsl::gfx::Renderer::get().setLayerPos(std::max(std::min((int)(frameOffsetX*1.5 + 0.5) - tsl::impl::currentUnderscanPixels.first, 1280-32 - tsl::impl::currentUnderscanPixels.first), 0), 0);
|
||||
}
|
||||
|
||||
boundsNeedUpdate = true;
|
||||
}
|
||||
} else if (((!currentMinusHeld && oldMinusHeld) || (!currentPlusHeld && oldPlusHeld)) && isDragging) {
|
||||
// Button just released - stop joystick dragging
|
||||
auto iniData = ult::getParsedDataFromIniFile(configIniPath);
|
||||
iniData["game_resolutions"]["frame_offset_x"] = std::to_string(frameOffsetX);
|
||||
iniData["game_resolutions"]["frame_offset_y"] = std::to_string(frameOffsetY);
|
||||
ult::saveIniFileData(configIniPath, iniData);
|
||||
isDragging = false;
|
||||
clearOnRelease = true;
|
||||
triggerRumbleDoubleClick.store(true, std::memory_order_release);
|
||||
triggerOffSound.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
// Update state for next frame
|
||||
oldTouchDetected = currentTouchDetected;
|
||||
oldMinusHeld = currentMinusHeld;
|
||||
oldPlusHeld = currentPlusHeld;
|
||||
|
||||
// Handle existing key input logic (but don't interfere with dragging)
|
||||
if (!isDragging) {
|
||||
if (isKeyComboPressed(keysHeld, keysDown)) {
|
||||
isRendering = false;
|
||||
leventSignal(&renderingStopEvent);
|
||||
runOnce = true;
|
||||
skipOnce = true;
|
||||
TeslaFPS = 60;
|
||||
lastSelectedItem = "Game Resolutions";
|
||||
lastMode = "";
|
||||
if (skipMain) {
|
||||
lastMode = "return";
|
||||
tsl::goBack();
|
||||
}
|
||||
else {
|
||||
tsl::setNextOverlay(filepath.c_str(), "--lastSelectedItem 'Game Resolutions'");
|
||||
tsl::Overlay::get()->close();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// Return true if we handled the input (during dragging)
|
||||
return isDragging;
|
||||
}
|
||||
};
|
||||
35
Source/Horizon-OC-Monitor/source/pwm.c
Normal file
35
Source/Horizon-OC-Monitor/source/pwm.c
Normal file
@@ -0,0 +1,35 @@
|
||||
#define NX_SERVICE_ASSUME_NON_DOMAIN
|
||||
#include <switch.h>
|
||||
#include <service_guard.h>
|
||||
#include "pwm.h"
|
||||
|
||||
static Service g_pwmSrv;
|
||||
|
||||
NX_GENERATE_SERVICE_GUARD(pwm);
|
||||
|
||||
Result _pwmInitialize(void) {
|
||||
return smGetService(&g_pwmSrv, "pwm");
|
||||
}
|
||||
|
||||
void _pwmCleanup(void) {
|
||||
serviceClose(&g_pwmSrv);
|
||||
}
|
||||
|
||||
Service* pwmGetServiceSession(void) {
|
||||
return &g_pwmSrv;
|
||||
}
|
||||
|
||||
Result pwmOpenSession2(PwmChannelSession *out, u32 device_code) {
|
||||
return serviceDispatchIn(&g_pwmSrv, 2, device_code,
|
||||
.out_num_objects = 1,
|
||||
.out_objects = &out->s,
|
||||
);
|
||||
}
|
||||
|
||||
Result pwmChannelSessionGetDutyCycle(PwmChannelSession *c, double* out) {
|
||||
return serviceDispatchOut(&c->s, 7, *out);
|
||||
}
|
||||
|
||||
void pwmChannelSessionClose(PwmChannelSession *c) {
|
||||
serviceClose(&c->s);
|
||||
}
|
||||
43
Source/Horizon-OC-Monitor/source/rgltr_services.cpp
Normal file
43
Source/Horizon-OC-Monitor/source/rgltr_services.cpp
Normal file
@@ -0,0 +1,43 @@
|
||||
// rgltr_services.cpp (no changes needed here—just compile it once)
|
||||
#include <switch.h>
|
||||
#include "rgltr.h"
|
||||
#include "rgltr_services.h" // for extern Service g_rgltrSrv, etc.
|
||||
|
||||
// Global service handle
|
||||
Service g_rgltrSrv;
|
||||
|
||||
Result rgltrInitialize(void) {
|
||||
if (hosversionBefore(8, 0, 0)) {
|
||||
return MAKERESULT(Module_Libnx, LibnxError_IncompatSysVer);
|
||||
}
|
||||
return smGetService(&g_rgltrSrv, "rgltr");
|
||||
}
|
||||
|
||||
void rgltrExit(void) {
|
||||
serviceClose(&g_rgltrSrv);
|
||||
}
|
||||
|
||||
Result rgltrOpenSession(RgltrSession* session_out, PowerDomainId module_id) {
|
||||
const u32 in = (u32)module_id;
|
||||
return serviceDispatchIn(
|
||||
&g_rgltrSrv,
|
||||
0,
|
||||
in,
|
||||
.out_num_objects = 1,
|
||||
.out_objects = &session_out->s
|
||||
);
|
||||
}
|
||||
|
||||
Result rgltrGetVoltage(RgltrSession* session, u32* out_volt) {
|
||||
// Service returns µV (microvolts) in a local u32:
|
||||
u32 temp = 0;
|
||||
Result rc = serviceDispatchOut(&session->s, 4, temp);
|
||||
if (R_SUCCEEDED(rc)) {
|
||||
*out_volt = temp;
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
void rgltrCloseSession(RgltrSession* session) {
|
||||
serviceClose(&session->s);
|
||||
}
|
||||
128
Source/Horizon-OC-Monitor/source/sysclk_ipc.c
Normal file
128
Source/Horizon-OC-Monitor/source/sysclk_ipc.c
Normal file
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
* wrote this file. As long as you retain this notice you can do whatever you
|
||||
* want with this stuff. If you meet any of us some day, and you think this
|
||||
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define NX_SERVICE_ASSUME_NON_DOMAIN
|
||||
#include <sysclk/client/ipc.h>
|
||||
#include <switch.h>
|
||||
#include <string.h>
|
||||
#include <stdatomic.h>
|
||||
|
||||
static Service g_sysclkSrv;
|
||||
static atomic_size_t g_refCnt;
|
||||
|
||||
bool sysclkIpcRunning()
|
||||
{
|
||||
Handle handle;
|
||||
const bool running = R_FAILED(smRegisterService(&handle, smEncodeName(SYSCLK_IPC_SERVICE_NAME), false, 1));
|
||||
|
||||
if (!running)
|
||||
{
|
||||
smUnregisterService(smEncodeName(SYSCLK_IPC_SERVICE_NAME));
|
||||
}
|
||||
|
||||
return running;
|
||||
}
|
||||
|
||||
Result sysclkIpcInitialize(void)
|
||||
{
|
||||
Result rc = 0;
|
||||
|
||||
g_refCnt++;
|
||||
|
||||
if (serviceIsActive(&g_sysclkSrv))
|
||||
return 0;
|
||||
|
||||
rc = smGetService(&g_sysclkSrv, SYSCLK_IPC_SERVICE_NAME);
|
||||
|
||||
if (R_FAILED(rc)) sysclkIpcExit();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
void sysclkIpcExit(void)
|
||||
{
|
||||
if (--g_refCnt == 0)
|
||||
{
|
||||
serviceClose(&g_sysclkSrv);
|
||||
}
|
||||
}
|
||||
|
||||
Result sysclkIpcGetAPIVersion(u32* out_ver)
|
||||
{
|
||||
return serviceDispatchOut(&g_sysclkSrv, SysClkIpcCmd_GetApiVersion, *out_ver);
|
||||
}
|
||||
|
||||
Result sysclkIpcGetVersionString(char* out, size_t len)
|
||||
{
|
||||
return serviceDispatch(&g_sysclkSrv, SysClkIpcCmd_GetVersionString,
|
||||
.buffer_attrs = { SfBufferAttr_HipcMapAlias | SfBufferAttr_Out },
|
||||
.buffers = {{out, len}},
|
||||
);
|
||||
}
|
||||
|
||||
Result sysclkIpcGetCurrentContext(SysClkContext* out_context)
|
||||
{
|
||||
return serviceDispatchOut(&g_sysclkSrv, SysClkIpcCmd_GetCurrentContext, *out_context);
|
||||
}
|
||||
|
||||
Result sysclkIpcGetProfileCount(u64 tid, u8* out_count)
|
||||
{
|
||||
return serviceDispatchInOut(&g_sysclkSrv, SysClkIpcCmd_GetProfileCount, tid, *out_count);
|
||||
}
|
||||
|
||||
Result sysclkIpcSetEnabled(bool enabled)
|
||||
{
|
||||
u8 enabledRaw = (u8)enabled;
|
||||
return serviceDispatchIn(&g_sysclkSrv, SysClkIpcCmd_SetEnabled, enabledRaw);
|
||||
}
|
||||
|
||||
Result sysclkIpcSetOverride(SysClkModule module, u32 hz)
|
||||
{
|
||||
SysClkIpc_SetOverride_Args args = {
|
||||
.module = module,
|
||||
.hz = hz
|
||||
};
|
||||
return serviceDispatchIn(&g_sysclkSrv, SysClkIpcCmd_SetOverride, args);
|
||||
}
|
||||
|
||||
Result sysclkIpcGetProfiles(u64 tid, SysClkTitleProfileList* out_profiles)
|
||||
{
|
||||
return serviceDispatchInOut(&g_sysclkSrv, SysClkIpcCmd_GetProfiles, tid, *out_profiles);
|
||||
}
|
||||
|
||||
Result sysclkIpcSetProfiles(u64 tid, SysClkTitleProfileList* profiles)
|
||||
{
|
||||
SysClkIpc_SetProfiles_Args args;
|
||||
args.tid = tid;
|
||||
memcpy(&args.profiles, profiles, sizeof(SysClkTitleProfileList));
|
||||
return serviceDispatchIn(&g_sysclkSrv, SysClkIpcCmd_SetProfiles, args);
|
||||
}
|
||||
|
||||
Result sysclkIpcGetConfigValues(SysClkConfigValueList* out_configValues)
|
||||
{
|
||||
return serviceDispatchOut(&g_sysclkSrv, SysClkIpcCmd_GetConfigValues, *out_configValues);
|
||||
}
|
||||
|
||||
Result sysclkIpcSetConfigValues(SysClkConfigValueList* configValues)
|
||||
{
|
||||
return serviceDispatchIn(&g_sysclkSrv, SysClkIpcCmd_SetConfigValues, *configValues);
|
||||
}
|
||||
|
||||
Result sysclkIpcGetFreqList(SysClkModule module, u32* list, u32 maxCount, u32* outCount)
|
||||
{
|
||||
SysClkIpc_GetFreqList_Args args = {
|
||||
.module = module,
|
||||
.maxCount = maxCount
|
||||
};
|
||||
return serviceDispatchInOut(&g_sysclkSrv, SysClkIpcCmd_GetFreqList, args, *outCount,
|
||||
.buffer_attrs = { SfBufferAttr_HipcAutoSelect | SfBufferAttr_Out },
|
||||
.buffers = {{list, maxCount * sizeof(u32)}},
|
||||
);
|
||||
}
|
||||
Binary file not shown.
@@ -1,5 +0,0 @@
|
||||
# Horizon OC TimingTool
|
||||
|
||||
A simple tool to dump timings from Linux and scale them
|
||||
|
||||
(c) 2025 Souldbminer & Horizon OC Contributors
|
||||
Binary file not shown.
@@ -1,2 +0,0 @@
|
||||
python -m PyInstaller --onefile --add-data "assets;assets" --noconsole src/main.py
|
||||
move "dist\main.exe" "dist\timingtool.exe"
|
||||
@@ -1,38 +0,0 @@
|
||||
# -*- mode: python ; coding: utf-8 -*-
|
||||
|
||||
|
||||
a = Analysis(
|
||||
['src\\main.py'],
|
||||
pathex=[],
|
||||
binaries=[],
|
||||
datas=[('assets', 'assets')],
|
||||
hiddenimports=[],
|
||||
hookspath=[],
|
||||
hooksconfig={},
|
||||
runtime_hooks=[],
|
||||
excludes=[],
|
||||
noarchive=False,
|
||||
optimize=0,
|
||||
)
|
||||
pyz = PYZ(a.pure)
|
||||
|
||||
exe = EXE(
|
||||
pyz,
|
||||
a.scripts,
|
||||
a.binaries,
|
||||
a.datas,
|
||||
[],
|
||||
name='main',
|
||||
debug=False,
|
||||
bootloader_ignore_signals=False,
|
||||
strip=False,
|
||||
upx=True,
|
||||
upx_exclude=[],
|
||||
runtime_tmpdir=None,
|
||||
console=False,
|
||||
disable_windowed_traceback=False,
|
||||
argv_emulation=False,
|
||||
target_arch=None,
|
||||
codesign_identity=None,
|
||||
entitlements_file=None,
|
||||
)
|
||||
@@ -1 +0,0 @@
|
||||
python src/main.py
|
||||
@@ -1,420 +0,0 @@
|
||||
"""
|
||||
|
||||
HOC Timing Tool
|
||||
|
||||
Copyright (C) Souldbminer
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
"""
|
||||
|
||||
import zipfile
|
||||
import tempfile
|
||||
from pathlib import Path
|
||||
import re
|
||||
import dearpygui.dearpygui as dpg
|
||||
import numpy as np
|
||||
import os
|
||||
import sys
|
||||
from scipy.signal import savgol_filter
|
||||
|
||||
REGISTER_RE = re.compile(r"^(emc|mc)_[A-Za-z0-9_]+\s+0x[0-9A-Fa-f]+$")
|
||||
if getattr(sys, 'frozen', False):
|
||||
assets_path = os.path.join(sys._MEIPASS, 'assets/')
|
||||
else:
|
||||
assets_path = os.path.join(os.path.dirname(__file__), '../assets/')
|
||||
|
||||
def safe_r2(y, y_fit):
|
||||
ss_res = np.sum((y - y_fit) ** 2)
|
||||
ss_tot = np.sum((y - np.mean(y)) ** 2)
|
||||
if ss_tot == 0:
|
||||
return 0.0
|
||||
return max(0.0, 1 - ss_res / ss_tot)
|
||||
|
||||
def find_inflection_points(x, y):
|
||||
x = np.array(x, dtype=float)
|
||||
y = np.array(y, dtype=float)
|
||||
|
||||
if len(x) < 3:
|
||||
return []
|
||||
|
||||
dx = np.diff(x)
|
||||
dy = np.diff(y)
|
||||
slopes = dy / dx
|
||||
|
||||
slope_changes = np.abs(np.diff(slopes))
|
||||
|
||||
if len(slope_changes) > 0:
|
||||
threshold = np.percentile(slope_changes, 40)
|
||||
else:
|
||||
return []
|
||||
|
||||
inflections = []
|
||||
for i in range(len(slope_changes)):
|
||||
if slope_changes[i] > threshold:
|
||||
inflections.append(i + 1)
|
||||
|
||||
inflections = sorted(set(inflections))
|
||||
|
||||
if len(inflections) < 2 and len(slope_changes) > 0:
|
||||
threshold = np.percentile(slope_changes, 60)
|
||||
inflections = []
|
||||
for i in range(len(slope_changes)):
|
||||
if slope_changes[i] > threshold:
|
||||
inflections.append(i + 1)
|
||||
inflections = sorted(set(inflections))
|
||||
|
||||
return inflections
|
||||
|
||||
def fit_piecewise_segments(x, y, reg_name="register"):
|
||||
x = np.array(x, dtype=float)
|
||||
y = np.array(y, dtype=float)
|
||||
|
||||
if len(x) < 3:
|
||||
return None
|
||||
|
||||
inflections = find_inflection_points(x, y)
|
||||
|
||||
breakpoints = [0] + inflections + [len(x) - 1]
|
||||
breakpoints = sorted(set(breakpoints))
|
||||
|
||||
segments = []
|
||||
thresholds = []
|
||||
slopes = []
|
||||
intercepts = []
|
||||
|
||||
for i in range(len(breakpoints) - 1):
|
||||
start_idx = breakpoints[i]
|
||||
end_idx = breakpoints[i + 1]
|
||||
|
||||
x_seg = x[start_idx:end_idx + 1]
|
||||
y_seg = y[start_idx:end_idx + 1]
|
||||
|
||||
if len(x_seg) < 2:
|
||||
continue
|
||||
|
||||
try:
|
||||
p = np.polyfit(x_seg, y_seg, 1)
|
||||
slope, intercept = p[0], p[1]
|
||||
|
||||
thresholds.append(x[end_idx])
|
||||
slopes.append(slope)
|
||||
intercepts.append(intercept)
|
||||
except Exception:
|
||||
continue
|
||||
|
||||
if not thresholds:
|
||||
return None
|
||||
|
||||
def piecewise(t, thresholds_list=thresholds, slopes_list=slopes, intercepts_list=intercepts):
|
||||
if np.isscalar(t):
|
||||
for thresh, slp, intcpt in zip(thresholds_list, slopes_list, intercepts_list):
|
||||
if t <= thresh:
|
||||
return slp * t + intcpt
|
||||
return slopes_list[-1] * t + intercepts_list[-1]
|
||||
else:
|
||||
result = np.zeros_like(t, dtype=float)
|
||||
for i, ti in enumerate(t):
|
||||
for thresh, slp, intcpt in zip(thresholds_list, slopes_list, intercepts_list):
|
||||
if ti <= thresh:
|
||||
result[i] = slp * ti + intcpt
|
||||
break
|
||||
else:
|
||||
result[i] = slopes_list[-1] * ti + intercepts_list[-1]
|
||||
return result
|
||||
|
||||
y_fit = piecewise(x)
|
||||
r2 = safe_r2(y, y_fit)
|
||||
|
||||
formula_lines = []
|
||||
for i, (thresh, slp, intcpt) in enumerate(zip(thresholds, slopes, intercepts)):
|
||||
if abs(slp) < 1e-6:
|
||||
val_str = f"{intcpt:.0f}"
|
||||
else:
|
||||
slp_simple = round(slp, 4)
|
||||
intcpt_simple = round(intcpt, 0)
|
||||
if slp_simple == int(slp_simple):
|
||||
slp_simple = int(slp_simple)
|
||||
if intcpt_simple >= 0:
|
||||
val_str = f"{slp_simple} * x + {intcpt_simple}"
|
||||
else:
|
||||
val_str = f"{slp_simple} * x - {abs(intcpt_simple)}"
|
||||
|
||||
if i == len(thresholds) - 1:
|
||||
formula_lines.append(f" return {val_str};")
|
||||
else:
|
||||
formula_lines.append(f" if (x <= {thresh:.0f}) return {val_str};")
|
||||
|
||||
formula = "float timing(float x) {\n" + "\n".join(formula_lines) + "\n}"
|
||||
|
||||
advanced_lines = []
|
||||
max_freq = max(x) if len(x) > 0 else 0
|
||||
|
||||
for i, (thresh, slp, intcpt) in enumerate(zip(thresholds, slopes, intercepts)):
|
||||
if abs(slp) < 1e-6:
|
||||
val = f"{intcpt:.0f}"
|
||||
else:
|
||||
slp_simple = round(slp, 4)
|
||||
intcpt_simple = round(intcpt, 0)
|
||||
if slp_simple == int(slp_simple):
|
||||
slp_simple = int(slp_simple)
|
||||
if intcpt_simple >= 0:
|
||||
val = f"({slp_simple} * freq + {intcpt_simple})"
|
||||
else:
|
||||
val = f"({slp_simple} * freq - {abs(intcpt_simple)})"
|
||||
|
||||
if thresh >= max_freq - 1:
|
||||
advanced_lines.append(f"WRITE_ALL_PARAM_REG(EMC_{reg_name}, {val});")
|
||||
elif i == 0:
|
||||
advanced_lines.append(f"if (freq <= {thresh:.0f}) {{")
|
||||
advanced_lines.append(f" WRITE_ALL_PARAM_REG(EMC_{reg_name}, {val});")
|
||||
advanced_lines.append("}")
|
||||
else:
|
||||
advanced_lines.append(f"else if (freq <= {thresh:.0f}) {{")
|
||||
advanced_lines.append(f" WRITE_ALL_PARAM_REG(EMC_{reg_name}, {val});")
|
||||
advanced_lines.append("}")
|
||||
|
||||
advanced_formula = "\n".join(advanced_lines)
|
||||
|
||||
return {
|
||||
'fn': piecewise,
|
||||
'formula': formula,
|
||||
'advanced_formula': advanced_formula,
|
||||
'r2': r2,
|
||||
'thresholds': thresholds,
|
||||
'slopes': slopes,
|
||||
'intercepts': intercepts,
|
||||
'reg_name': reg_name
|
||||
}
|
||||
|
||||
|
||||
def parse_dump_file(path: Path):
|
||||
registers = {}
|
||||
try:
|
||||
for line in path.read_text(errors="ignore").splitlines():
|
||||
line = line.strip()
|
||||
if not line or line.startswith("#"):
|
||||
continue
|
||||
parts = line.split()
|
||||
if len(parts) < 2:
|
||||
continue
|
||||
name, val = parts[0], parts[-1]
|
||||
if not (name.lower().startswith("emc_") or name.lower().startswith("mc_")):
|
||||
continue
|
||||
if not val.startswith("0x"):
|
||||
continue
|
||||
try:
|
||||
registers[name] = int(val, 16)
|
||||
except ValueError:
|
||||
pass
|
||||
except Exception:
|
||||
pass
|
||||
return registers
|
||||
|
||||
|
||||
def analyze_zip(zip_path: Path):
|
||||
tmpdir = Path(tempfile.mkdtemp(prefix="timingtool_extract_"))
|
||||
with zipfile.ZipFile(zip_path, "r") as z:
|
||||
z.extractall(tmpdir)
|
||||
|
||||
results = {}
|
||||
for base_dir in tmpdir.iterdir():
|
||||
if not base_dir.is_dir():
|
||||
continue
|
||||
base_latency = base_dir.name
|
||||
results.setdefault(base_latency, {"mc": {}, "emc": {}})
|
||||
|
||||
for typ in ("mc", "emc"):
|
||||
folder = base_dir / typ
|
||||
if not folder.exists():
|
||||
continue
|
||||
for dump in folder.glob("*.txt"):
|
||||
m = re.search(r"(\d+)", dump.name)
|
||||
if not m:
|
||||
continue
|
||||
freq = int(m.group(1))
|
||||
registers = parse_dump_file(dump)
|
||||
for reg, val in registers.items():
|
||||
results[base_latency][typ].setdefault(reg, {})[freq] = val
|
||||
|
||||
return results
|
||||
|
||||
|
||||
|
||||
dpg.create_context()
|
||||
dpg.create_viewport(title="Horizon OC Timing Tool", width=1920, height=1080)
|
||||
dpg.maximize_viewport()
|
||||
|
||||
with dpg.font_registry():
|
||||
lexend = dpg.add_font(assets_path + "Lexend.ttf", 16)
|
||||
|
||||
with dpg.window(label="HOC Timing Tool", width=1920, height=1080, tag="main_window"):
|
||||
with dpg.tab_bar(tag="root_tabs"):
|
||||
with dpg.tab(label=" File", tag="file_tab"):
|
||||
dpg.add_text("Timing Analyzer\nSelect a ZIP file structured as:\n<base_latency>/<mc|emc>/<freq>_mc.txt")
|
||||
dpg.add_button(label="Select ZIP File...", callback=lambda s,a: dpg.show_item("file_dialog"))
|
||||
dpg.add_separator()
|
||||
dpg.add_text("Status:")
|
||||
dpg.add_text("Waiting...", tag="status_text")
|
||||
|
||||
with dpg.tab(label="Graphs", tag="graph_tab"):
|
||||
with dpg.tab_bar(tag="main_tabs"):
|
||||
dpg.add_tab(label="No Data", tag="placeholder_tab")
|
||||
|
||||
with dpg.tab(label="Code", tag="code_tab"):
|
||||
with dpg.tab_bar(tag="code_tabs"):
|
||||
dpg.add_tab(label="No Data", tag="code_placeholder_tab")
|
||||
|
||||
|
||||
def handle_file_selection(sender, app_data):
|
||||
if not app_data["selections"]:
|
||||
return
|
||||
zip_path = list(app_data["selections"].values())[0]
|
||||
dpg.set_value("status_text", f"Analyzing {zip_path} ...")
|
||||
try:
|
||||
data = analyze_zip(Path(zip_path))
|
||||
except Exception as e:
|
||||
dpg.set_value("status_text", f"Error: {e}")
|
||||
return
|
||||
|
||||
dpg.delete_item("main_tabs", children_only=True)
|
||||
|
||||
if not data:
|
||||
dpg.add_tab(label="No valid data", parent="main_tabs")
|
||||
dpg.set_value("status_text", "No valid data found in ZIP.")
|
||||
return
|
||||
|
||||
dpg.delete_item("code_tabs", children_only=True)
|
||||
|
||||
for base_latency, lat_data in sorted(data.items()):
|
||||
with dpg.tab(label=f"{base_latency}bl", parent="main_tabs"):
|
||||
with dpg.tab_bar():
|
||||
for typ in ("mc", "emc"):
|
||||
with dpg.tab(label=typ.upper()):
|
||||
if not lat_data[typ]:
|
||||
dpg.add_text(f"No {typ.upper()} data.")
|
||||
continue
|
||||
|
||||
search_tag = f"search_{base_latency}_{typ}"
|
||||
dpg.add_input_text(label="Search Timings", tag=search_tag, width=500)
|
||||
|
||||
with dpg.child_window(width=-1, height=850, horizontal_scrollbar=True) as scroll_area:
|
||||
for reg_name, freq_map in sorted(lat_data[typ].items()):
|
||||
freqs = sorted(freq_map.keys())
|
||||
vals = [freq_map[f] for f in freqs]
|
||||
if len(freqs) < 2:
|
||||
continue
|
||||
|
||||
x = np.array(freqs, dtype=float)
|
||||
y = np.array(vals, dtype=float)
|
||||
|
||||
fit_result = fit_piecewise_segments(x, y, reg_name)
|
||||
|
||||
if fit_result is None:
|
||||
continue
|
||||
|
||||
plot_tag = f"{base_latency}_{typ}_{reg_name}_plot"
|
||||
container_tag = f"{plot_tag}_container"
|
||||
dropdown_tag = f"{plot_tag}_dropdown"
|
||||
value_tag = f"{plot_tag}_value"
|
||||
|
||||
with dpg.group(tag=container_tag):
|
||||
with dpg.plot(label=reg_name, height=250, width=-1):
|
||||
dpg.add_plot_legend()
|
||||
dpg.add_plot_axis(dpg.mvXAxis, label="Frequency (MHz)")
|
||||
y_axis = dpg.add_plot_axis(dpg.mvYAxis, label="Register")
|
||||
dpg.add_line_series(freqs, vals, label="Data", parent=y_axis)
|
||||
|
||||
fit_x = np.linspace(min(freqs), max(freqs), 100)
|
||||
fit_y = fit_result['fn'](fit_x)
|
||||
dpg.add_line_series(fit_x, fit_y, label=f"Fit (R²={fit_result['r2']:.3f})", parent=y_axis)
|
||||
|
||||
dpg.add_text(f"R² = {fit_result['r2']:.4f}", color=(100, 200, 100))
|
||||
|
||||
with dpg.tab_bar():
|
||||
with dpg.tab(label="Timing Function"):
|
||||
dpg.add_input_text(default_value=fit_result['formula'], readonly=True, width=-1, height=150, multiline=True, tag=f"{container_tag}_formula")
|
||||
with dpg.tab(label="Register Write"):
|
||||
dpg.add_input_text(default_value=fit_result['advanced_formula'], readonly=True, width=-1, height=150, multiline=True, tag=f"{container_tag}_advanced")
|
||||
|
||||
def make_freq_callback(freq_map, val_tag):
|
||||
def _callback(sender, app_data):
|
||||
freq = int(app_data)
|
||||
val = freq_map.get(freq)
|
||||
if val is not None:
|
||||
dpg.set_value(val_tag, f"Value: 0x{val:08X} ({val})")
|
||||
else:
|
||||
dpg.set_value(val_tag, "Value: N/A")
|
||||
return _callback
|
||||
|
||||
dpg.add_combo(
|
||||
items=[str(f) for f in freqs],
|
||||
label="Select Frequency",
|
||||
default_value=str(freqs[0]),
|
||||
width=150,
|
||||
callback=make_freq_callback(freq_map, value_tag),
|
||||
tag=dropdown_tag
|
||||
)
|
||||
dpg.add_text(f"Value: 0x{vals[0]:08X} ({vals[0]})", tag=value_tag)
|
||||
|
||||
def make_filter_closure(scroll_area, search_tag, lat_data=lat_data[typ], base=base_latency, t=typ):
|
||||
def _filter(sender, app_data):
|
||||
query = app_data.strip().lower()
|
||||
for reg_name in lat_data.keys():
|
||||
container_tag = f"{base}_{t}_{reg_name}_plot_container"
|
||||
visible = query in reg_name.lower() if query else True
|
||||
if dpg.does_item_exist(container_tag):
|
||||
dpg.configure_item(container_tag, show=visible)
|
||||
return _filter
|
||||
|
||||
dpg.set_item_callback(search_tag, make_filter_closure(scroll_area, search_tag))
|
||||
|
||||
for base_latency, lat_data in sorted(data.items()):
|
||||
code_content = ""
|
||||
with dpg.tab(label=f"{base_latency}bl", parent="code_tabs"):
|
||||
with dpg.tab_bar():
|
||||
for typ in ("mc", "emc"):
|
||||
with dpg.tab(label=typ.upper()):
|
||||
typ_code = ""
|
||||
if lat_data[typ]:
|
||||
for reg_name, freq_map in sorted(lat_data[typ].items()):
|
||||
freqs = sorted(freq_map.keys())
|
||||
vals = [freq_map[f] for f in freqs]
|
||||
if len(freqs) < 2:
|
||||
continue
|
||||
|
||||
x = np.array(freqs, dtype=float)
|
||||
y = np.array(vals, dtype=float)
|
||||
fit_result = fit_piecewise_segments(x, y, reg_name)
|
||||
|
||||
if fit_result:
|
||||
typ_code += fit_result['advanced_formula'] + "\n\n"
|
||||
|
||||
if typ_code:
|
||||
dpg.add_input_text(default_value=typ_code, readonly=True, width=-1, height=-1, multiline=True)
|
||||
else:
|
||||
dpg.add_text(f"No {typ.upper()} data.")
|
||||
|
||||
dpg.set_value("status_text", "Done.")
|
||||
|
||||
|
||||
with dpg.file_dialog(directory_selector=False, show=False, callback=handle_file_selection, tag="file_dialog", width=500, height=300, modal=True):
|
||||
dpg.add_file_extension(".zip")
|
||||
|
||||
dpg.set_primary_window("main_window", True)
|
||||
|
||||
dpg.bind_font(lexend)
|
||||
dpg.setup_dearpygui()
|
||||
dpg.show_viewport()
|
||||
dpg.start_dearpygui()
|
||||
dpg.destroy_context()
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000060
|
||||
EMC_RFC_0 = 0x000001C0
|
||||
EMC_RAS_0 = 0x00000044
|
||||
EMC_RP_0 = 0x0000001D
|
||||
EMC_R2W_0 = 0x00000029
|
||||
EMC_W2R_0 = 0x00000021
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000001D
|
||||
EMC_WR_RCD_0 = 0x0000001D
|
||||
EMC_RRD_0 = 0x00000010
|
||||
EMC_REXT_0 = 0x00000017
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x0006000C
|
||||
EMC_QSAFE_0 = 0x00000033
|
||||
EMC_RDV_0 = 0x00000039
|
||||
EMC_REFRESH_0 = 0x00001820
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000010
|
||||
EMC_PDEX2RD_0 = 0x00000010
|
||||
EMC_PCHG2PDEN_0 = 0x00000003
|
||||
EMC_ACT2PDEN_0 = 0x00000017
|
||||
EMC_AR2PDEN_0 = 0x00000003
|
||||
EMC_RW2PDEN_0 = 0x00000038
|
||||
EMC_TXSR_0 = 0x000001CC
|
||||
EMC_TCKE_0 = 0x0000000D
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x00000022
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x00000014
|
||||
EMC_TREFBW_0 = 0x00001860
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000002E
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x01900017
|
||||
EMC_MRS_WAIT_CNT_0 = 0x0640002F
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012C0DC
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x0000000E
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0000
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000018
|
||||
EMC_TPD_0 = 0x0000000C
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x00110835
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003B
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000039
|
||||
EMC_RDV_EARLY_0 = 0x00000037
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x00310640
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186190
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000039
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000608
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000308C
|
||||
EMC_TXSRDLL_0 = 0x000001CC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002B
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003B
|
||||
EMC_TR_QSAFE_0 = 0x00000033
|
||||
EMC_TR_QRST_0 = 0x0006000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0B09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x00000008
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC4204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x001F0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x2E2F2F2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2B292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2B2E2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x32323333
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x2F313228
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x252C2D2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A292623
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2C2F2D2E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353134
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2F2E2A2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2D29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232527
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272325
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x070A070A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000070
|
||||
EMC_RFC_0 = 0x0000020B
|
||||
EMC_RAS_0 = 0x0000004F
|
||||
EMC_RP_0 = 0x00000022
|
||||
EMC_R2W_0 = 0x0000002A
|
||||
EMC_W2R_0 = 0x00000022
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000022
|
||||
EMC_WR_RCD_0 = 0x00000022
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070008
|
||||
EMC_QSAFE_0 = 0x00000034
|
||||
EMC_RDV_0 = 0x0000003A
|
||||
EMC_REFRESH_0 = 0x00001C2D
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000013
|
||||
EMC_PDEX2RD_0 = 0x00000013
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001B
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x00000219
|
||||
EMC_TCKE_0 = 0x00000010
|
||||
EMC_TFAW_0 = 0x0000004B
|
||||
EMC_TRPAB_0 = 0x00000028
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x00000017
|
||||
EMC_TREFBW_0 = 0x00001C6D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000037
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x01D3001B
|
||||
EMC_MRS_WAIT_CNT_0 = 0x074A0030
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122A40
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000010
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x00000020
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000001C
|
||||
EMC_TPD_0 = 0x0000000E
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003C
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003A
|
||||
EMC_RDV_EARLY_0 = 0x00000038
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x0039074A
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011861D3
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003A
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000070B
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80003873
|
||||
EMC_TXSRDLL_0 = 0x00000219
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002C
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003C
|
||||
EMC_TR_QSAFE_0 = 0x00000034
|
||||
EMC_TR_QRST_0 = 0x00070008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030A
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002C
|
||||
EMC_QUSE_WIDTH_0 = 0x00000009
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000106
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0009000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00100007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0009000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00100007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00090000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00090000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001F0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x393A3A3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x39353337
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000038
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x37393737
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x35393235
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000034
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x3E3C3E3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3A3C3F32
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x30363736
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x35342F2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x373B393B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x383B3838
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x37353737
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000036
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x42424341
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x3F413D3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3A393436
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x37353833
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000035
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04060506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05070307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060809
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02020303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020101
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040203
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03030200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242526
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x2B262822
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00100010
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080F
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000403A5
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000080
|
||||
EMC_RFC_0 = 0x00000256
|
||||
EMC_RAS_0 = 0x0000005A
|
||||
EMC_RP_0 = 0x00000027
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000025
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000027
|
||||
EMC_WR_RCD_0 = 0x00000027
|
||||
EMC_RRD_0 = 0x00000010
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000035
|
||||
EMC_RDV_0 = 0x0000003B
|
||||
EMC_REFRESH_0 = 0x0000203F
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000016
|
||||
EMC_PDEX2RD_0 = 0x00000016
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001E
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x00000266
|
||||
EMC_TCKE_0 = 0x00000012
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x0000002D
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x0000207F
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000003F
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0216001E
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000020
|
||||
EMC_TPD_0 = 0x00000010
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003D
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003B
|
||||
EMC_RDV_EARLY_0 = 0x00000039
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186216
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003B
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000080F
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004062
|
||||
EMC_TXSRDLL_0 = 0x00000266
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002D
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003D
|
||||
EMC_TR_QSAFE_0 = 0x00000035
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002D
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000012B
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000A0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000A0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00250025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x45454546
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x43403E43
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x42444241
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3F443C3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49474A49
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x4548493C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x38404140
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3E3D3934
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050304
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x00060102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x413F4041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4141413E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0E0E0F0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0B0D080B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x44433E40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x413E433D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03070706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x060A0409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0708090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050507
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06020401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27262629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27292629
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004042B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000082
|
||||
EMC_RFC_0 = 0x0000025F
|
||||
EMC_RAS_0 = 0x0000005B
|
||||
EMC_RP_0 = 0x00000027
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000025
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000027
|
||||
EMC_WR_RCD_0 = 0x00000027
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070006
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x000020BF
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x0000026F
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000041
|
||||
EMC_TRPAB_0 = 0x0000002E
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x000020FF
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000040
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x021E001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012AFC4
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118621E
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000082F
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000415D
|
||||
EMC_TXSRDLL_0 = 0x0000026F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000130
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x8C200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x47474747
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x45413F45
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000045
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x44464342
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x41463E40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49484A4A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x46484A3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x39414242
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x403E3A36
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x01060306
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060202
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x42414142
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4241423F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0E0F100E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0C0E090C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x46443F41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4340443D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0807090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050101
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01030002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04020100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25232828
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29282623
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004043B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000084
|
||||
EMC_RFC_0 = 0x00000268
|
||||
EMC_RAS_0 = 0x0000005D
|
||||
EMC_RP_0 = 0x00000028
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000025
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000028
|
||||
EMC_WR_RCD_0 = 0x00000028
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070006
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x00002144
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x00000279
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000042
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002184
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000041
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0226001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80129FB3
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186226
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000851
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000425F
|
||||
EMC_TXSRDLL_0 = 0x00000279
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x0000024A
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000134
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x8C200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0021002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x07080707
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06020005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x46474543
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x42473F41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4B494C4C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x474A4B3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B434443
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x41403B37
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x03080507
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x04090405
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020300
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1111120F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0E0F0B0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x47454042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4441453F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0807090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272624
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004044C
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000086
|
||||
EMC_RFC_0 = 0x00000272
|
||||
EMC_RAS_0 = 0x0000005E
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000026
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x000021C5
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x00000282
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000043
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002205
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x022F0020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118622F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000871
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000435A
|
||||
EMC_TXSRDLL_0 = 0x00000282
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000252
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000139
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x08090809
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06030106
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06080605
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080103
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4D4B4E4E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x494D4E3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000004A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B444544
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x42413C38
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x05090608
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x05090505
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05030405
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x11131310
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0F110C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08080104
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020601
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2725272A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282625
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004045D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000088
|
||||
EMC_RFC_0 = 0x0000027B
|
||||
EMC_RAS_0 = 0x00000060
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000026
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x00002245
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x0000028C
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000044
|
||||
EMC_TRPAB_0 = 0x00000030
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x00002285
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02370020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x88010054
|
||||
EMC_MRR_0 = 0x8012768A
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00C0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186237
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000891
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004455
|
||||
EMC_TXSRDLL_0 = 0x0000028C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0F0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000013E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0B0A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x08040207
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x07090806
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x040A0203
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0E0C0F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0E0F00
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3C454745
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2B2A2723
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x050A0709
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060B0607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050502
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x13141512
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x11120E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09080305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040702
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x03020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282525
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004046D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008A
|
||||
EMC_RFC_0 = 0x00000284
|
||||
EMC_RAS_0 = 0x00000061
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000026
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070004
|
||||
EMC_QSAFE_0 = 0x00000037
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x000022CA
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x00000296
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000045
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000230A
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x023F0021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80125E72
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000D
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118623F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008B2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004558
|
||||
EMC_TXSRDLL_0 = 0x00000296
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000037
|
||||
EMC_TR_QRST_0 = 0x00070004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000142
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x22004120
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0B0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0A050309
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090A0807
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060B0305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0F0E1011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0C0F1002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3D464746
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x44433E3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x070C090B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x070C0708
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x07060704
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x14151613
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x11130F10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0B0A0406
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08060903
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A0409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252828
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272726
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008C
|
||||
EMC_RFC_0 = 0x0000028E
|
||||
EMC_RAS_0 = 0x00000062
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070003
|
||||
EMC_QSAFE_0 = 0x00000038
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x0000234B
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x0000029F
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000046
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000238B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02480021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80124B5F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186248
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008D2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004653
|
||||
EMC_TXSRDLL_0 = 0x0000029F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000038
|
||||
EMC_TR_QRST_0 = 0x00070003
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000147
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0C0B0C0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x09060509
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0B0A09
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x080C0506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x100F1212
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0D101102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3F484948
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4544403B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x080E0A0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x090E0909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x08070808
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x09080805
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x16161815
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x13151012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0C0B0507
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08060A04
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03040506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040B030B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624292A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29262529
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004048F
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008E
|
||||
EMC_RFC_0 = 0x00000297
|
||||
EMC_RAS_0 = 0x00000064
|
||||
EMC_RP_0 = 0x0000002B
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002B
|
||||
EMC_WR_RCD_0 = 0x0000002B
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x0006000C
|
||||
EMC_QSAFE_0 = 0x00000037
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x000023CB
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002A9
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000047
|
||||
EMC_TRPAB_0 = 0x00000032
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x0000240B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000046
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02500022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122A41
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186250
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008F2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000474E
|
||||
EMC_TXSRDLL_0 = 0x000002A9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000037
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000014C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A00A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0D0D0D0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B07050B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0C0D0B0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x090E0608
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x11111413
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0F121304
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x404A4A49
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4746413C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000044
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A0E0C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0A0F0A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0A080A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0A090A06
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x17181916
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x14161213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0C0708
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0B070C05
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05030104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26242429
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262325
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004049F
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000090
|
||||
EMC_RFC_0 = 0x000002A0
|
||||
EMC_RAS_0 = 0x00000065
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000037
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x00002450
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002B2
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000048
|
||||
EMC_TRPAB_0 = 0x00000033
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002490
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000047
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02580022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122D40
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186258
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000914
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004850
|
||||
EMC_TXSRDLL_0 = 0x000002B2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000037
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0C
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000150
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0E100F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0E0A080D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0D0F0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x12121514
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x10131405
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4747423D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000045
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A100C0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0A090B0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0B0A0A08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x18191A17
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16171315
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0D080A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0B090C07
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B030B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624292A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404B0
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0C
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000092
|
||||
EMC_RFC_0 = 0x000002AA
|
||||
EMC_RAS_0 = 0x00000067
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00070004
|
||||
EMC_QSAFE_0 = 0x00000038
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x000024D1
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002BC
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x00000049
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002511
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000048
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02610023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012283F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000D
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186261
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000000
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000934
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000494B
|
||||
EMC_TXSRDLL_0 = 0x000002BC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000038
|
||||
EMC_TR_QRST_0 = 0x00070004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000155
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x10111010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0E0A080E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0E100E0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0B10080A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x14131516
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x10131505
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x414B4D4B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4848433E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000046
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0B100D0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0B100B0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0C0A0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1C18
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16181416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x110E090A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0D0A0E08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040B040B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02080006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27242927
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282729
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x00000000
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000094
|
||||
EMC_RFC_0 = 0x000002B3
|
||||
EMC_RAS_0 = 0x00000068
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00070004
|
||||
EMC_QSAFE_0 = 0x00000038
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x00002551
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002C5
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004A
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002591
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02690023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80120215
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000D
|
||||
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186190
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000954
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004A46
|
||||
EMC_TXSRDLL_0 = 0x000002C5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000038
|
||||
EMC_TR_QRST_0 = 0x00070004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0C
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015A
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x11131011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2E2B292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10120F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x20221E20
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x15141616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x11151607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x434C4D4C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4A49443F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0C110E10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0C110C0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0E0C0E0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0D0D0E0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1C19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x171A1517
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x12100A0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0E0C0F08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080906
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B040B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28292726
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404D1
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0C
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000096
|
||||
EMC_RFC_0 = 0x000002BC
|
||||
EMC_RAS_0 = 0x00000069
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070003
|
||||
EMC_QSAFE_0 = 0x00000039
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x000025D6
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002CF
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004B
|
||||
EMC_TRPAB_0 = 0x00000035
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002616
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02710023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012F002
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000028
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186271
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000975
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004B49
|
||||
EMC_TXSRDLL_0 = 0x000002CF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000039
|
||||
EMC_TR_QRST_0 = 0x00070003
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x13141313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x110C0A10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x11130F10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0E130B0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x16151718
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x30323328
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0B0A0500
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0E121012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0E130E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0F0D0E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0F0E0E0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1B1C1E1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x191A1617
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14110B0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0F0C100A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0806090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040208
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624232A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292626
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404E2
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000098
|
||||
EMC_RFC_0 = 0x000002C6
|
||||
EMC_RAS_0 = 0x0000006B
|
||||
EMC_RP_0 = 0x0000002E
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002E
|
||||
EMC_WR_RCD_0 = 0x0000002E
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00080001
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x00002657
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002D9
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004C
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002697
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004A
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x027A0024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000B
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118627A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000995
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004C44
|
||||
EMC_TXSRDLL_0 = 0x000002D9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080001
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000163
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A00A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00060000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0021
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x14151414
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x120E0B11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x12141111
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0F140C0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1817191A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x15181909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x040F100E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2B2A2723
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0F141113
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0F150F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x100F1010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x100F100C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1E1E1F1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1A1D181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14120D0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x100E120B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00040505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08030503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242428
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25292825
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404F3
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009A
|
||||
EMC_RFC_0 = 0x000002CF
|
||||
EMC_RAS_0 = 0x0000006C
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080002
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x000026D7
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002E2
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004D
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002717
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02820024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012D4E6
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186282
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009B5
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004D3F
|
||||
EMC_TXSRDLL_0 = 0x000002E2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080002
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000168
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x15151416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x130F0C13
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x13161312
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x10160D0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x19191B1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x16191A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0610110F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0D0C0702
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x10151214
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x10161011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x110F1113
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1110110E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1D1F211C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1B1D181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x15140E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x110F120B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08060307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27232629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28262425
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009C
|
||||
EMC_RFC_0 = 0x000002D8
|
||||
EMC_RAS_0 = 0x0000006E
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080002
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x0000275C
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002EC
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004E
|
||||
EMC_TRPAB_0 = 0x00000037
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000279C
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x028A0025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118628A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009D7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004E41
|
||||
EMC_TXSRDLL_0 = 0x000002EC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080002
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000016C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x16161515
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x140F0E14
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x15161414
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x11170E11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1B1A1C1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x171A1C0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x07111311
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0F0E0903
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x12181416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x12181213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x12111213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353234
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x17160F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020203
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26232528
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040514
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009E
|
||||
EMC_RFC_0 = 0x000002E2
|
||||
EMC_RAS_0 = 0x0000006F
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x0000002A
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080001
|
||||
EMC_QSAFE_0 = 0x0000003D
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x000027DD
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002F5
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004F
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000281D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02930025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012B1C2
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000B
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186293
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009F7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004F3C
|
||||
EMC_TXSRDLL_0 = 0x000002F5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003D
|
||||
EMC_TR_QRST_0 = 0x00080001
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000171
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x18181818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x16120F15
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x16181615
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x12180F12
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1C1C1D1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191C1D0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x08121311
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0F0E0A04
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x12171417
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x13181314
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x13121315
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1312130F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2021231F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1E201A1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x17161011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1411150E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A0A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070E0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x090A0300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08070408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03010101
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2A222428
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x23272726
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040525
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,528 +0,0 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A0
|
||||
EMC_RFC_0 = 0x000002EB
|
||||
EMC_RAS_0 = 0x00000070
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x0000002A
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080001
|
||||
EMC_QSAFE_0 = 0x0000003D
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x0000285D
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000026
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002FF
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x00000050
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000289D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x029B0026
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012A5B6
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000B
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118629B
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A17
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005037
|
||||
EMC_TXSRDLL_0 = 0x000002FF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003D
|
||||
EMC_TR_QRST_0 = 0x00080001
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000176
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x19191818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x17121016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x18191616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323433
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191D1F0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x09141513
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x11100B05
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x131A1618
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x14191516
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x15141516
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x14141511
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x20221C1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x19171113
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1412160F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B050B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0E
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01090B09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090508
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0306050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05040301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24242628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262827
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040535
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DEB251
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000C
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000006
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000D080C
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726C2419
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C511020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80100080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A930850
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000228
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000080
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080016
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x4A005160
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x75C5BF41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000E
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000E090E
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726E2A1D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02013000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000041
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x000000F2
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000335
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001B
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00001501
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x006D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x006D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x006D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x006D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x006D006D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x006D0019
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x006D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x006D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x006D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x006D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x006D0016
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000006D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x006D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x006D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000006D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080013
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x006D0016
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x006D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x006D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD0B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E72431
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80050080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000F0A10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72703021
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00600004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00600038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00600005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00600014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00600060
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00600016
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00600095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00600041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00600080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0060003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00600013
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000060
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00600090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00600004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000060
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080011
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00600013
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00600005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00600018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD8B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E3E631
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000F0A10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713121
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004B
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005E005E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005E0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D49341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713222
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02910800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005D005D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005D0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01011200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E3F551
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80040080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713322
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004E
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005B0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005B0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005B005B
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005B0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005B0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005B0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005B0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005B003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005B
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005B0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005B
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005B0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDBB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E6F6D1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713323
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004F
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005A005A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E4C761
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723423
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000050
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00590038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00590059
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00590095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00590041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00590080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0059003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000059
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00590090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000059
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00590018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x00000000
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC1B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E44061
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723523
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02000000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000051
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00570038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00570057
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00570095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00570041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00570080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0057003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000057
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00570090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000057
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00570011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00570018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCEB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E38391
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000023
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723624
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C151000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000052
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00560038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00560014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00560056
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00560013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00560095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00560041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00560080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0056003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000056
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00560090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000056
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00560018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77CDF531
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723625
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A110000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000053
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00550038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00550014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00550055
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00550013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00550095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00550041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00550080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0055003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000055
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00550090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000055
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00550018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01010200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000007F
|
||||
MC_SMMU_PTB_DATA_0 = 0x00000000
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDFB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7A41F7E1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733725
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000C0800
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8800
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1910A0
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000055
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000120
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000120
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x00000000
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000E
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00540038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00540014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00540054
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00540013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00540095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00540041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00540080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0054003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000054
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00540090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000054
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00540018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCFB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E273C1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80040080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733826
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000056
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00530038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00530014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00530053
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00530013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00530095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00530041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00530080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0053003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000053
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00530090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000053
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00530018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC6B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D351A1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x800C0080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733926
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02910800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000057
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00510038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00510014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00510051
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00510012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00510095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00510041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00510080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0051003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000051
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00510090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000051
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00510018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DCA341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733927
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00023070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000058
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00500038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00500014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00500050
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00500012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00500095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00500041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00500080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0050003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000050
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00500090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000050
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00500018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E72341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743A27
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02110000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000059
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004F0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004F0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004F004F
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004F0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004F0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004F0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004F0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004F003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004F
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004F0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004F
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004F0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E74541
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743B28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004E004E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004E0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
@@ -1,288 +0,0 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0xF4028180
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD3B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E8C4C1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80070080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A930850
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004D004D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004D0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user