hocclk: refactoring and ram pll measurement

This commit is contained in:
souldbminersmwc
2026-04-07 19:48:17 -04:00
parent c6cd863526
commit 90e53b52b2
17 changed files with 427 additions and 201 deletions

View File

@@ -158,6 +158,12 @@ typedef enum {
RamDisplayMode_EnumMax,
} RamDisplayMode;
typedef enum {
MemoryFrequencyMeasurementMode_Actmon = 0,
MemoryFrequencyMeasurementMode_PLL,
MemoryFrequencyMeasurementMode_EnumMax,
} MemoryFrequencyMeasurementMode;
#define HOCCLK_ENUM_VALID(n, v) ((v) < n##_EnumMax)
// Packed u32

View File

@@ -68,6 +68,8 @@ typedef enum {
HocClkConfigValue_CpuGovernorMinimumFreq,
HocClkConfigValue_DisplayVoltage,
HocClkConfigValue_MemoryFrequencyMeasurementMode,
KipConfigValue_custRev,
// KipConfigValue_mtcConf,
KipConfigValue_hpMode,
@@ -257,6 +259,9 @@ static inline const char* hocclkFormatConfigValue(HocClkConfigValue val, bool pr
case HocClkConfigValue_DisplayVoltage:
return pretty ? "Display Voltage" : "display_voltage";
case HocClkConfigValue_MemoryFrequencyMeasurementMode:
return pretty ? "Memory Frequency Measurement Mode" : "mem_freq_measurement_mode";
// KIP config values
case KipConfigValue_custRev:
return pretty ? "Custom Revision" : "kip_cust_rev";
@@ -436,6 +441,7 @@ static inline uint64_t hocclkDefaultConfigValue(HocClkConfigValue val)
case HocClkConfigValue_GPUScheduling:
case HocClkConfigValue_LiveCpuUv:
case HocClkConfigValue_GPUSchedulingMethod:
case HocClkConfigValue_MemoryFrequencyMeasurementMode:
return 0ULL;
case HocClkConfigValue_EristaMaxCpuClock:
return 1785ULL;
@@ -592,6 +598,7 @@ static inline uint64_t hocclkValidConfigValue(HocClkConfigValue val, uint64_t in
case HocClkConfigValue_GPUScheduling:
case HocClkConfigValue_RAMVoltDisplayMode:
case HocClkConfigValue_CpuGovernorMinimumFreq:
case HocClkConfigValue_MemoryFrequencyMeasurementMode:
return true;
case HocClkConfigValue_BatteryChargeCurrent:
return ((input >= 1024) && (input <= 3072)) || !input;

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@@ -525,3 +525,24 @@
#define CL_DVFS_I2C_STS_0 0x48
#define CL_DVFS_INTR_STS_0 0x5C
#define CL_DVFS_I2C_CLK_DIVISOR_REGISTER_0 0x16C
#define CLK_SOURCE_EMC 0x19c
#define PLLC_BASE 0x080
#define PLLM_BASE 0x090
#define PLLP_BASE 0x0a0
#define PLLA_BASE 0x0b0
#define PLLU_BASE 0x0c0
#define _PLLD_BASE 0x0d0
#define PLLX_BASE 0x0e0
#define PLLE_BASE 0x0e8
#define PLLC2_BASE 0x4e8
#define PLLC3_BASE 0x4fc
#define PLLD2_BASE 0x4b8
#define PLLRE_BASE 0x4c4
#define PLLC4_BASE 0x5a4
#define PLLMB_BASE 0x5e8
#define PLLA1_BASE 0x6a4
#define PLLDP_BASE 0x590
#define OSC_HZ 38400000ULL