hocclk: refactoring and ram pll measurement
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@@ -158,6 +158,12 @@ typedef enum {
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RamDisplayMode_EnumMax,
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} RamDisplayMode;
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typedef enum {
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MemoryFrequencyMeasurementMode_Actmon = 0,
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MemoryFrequencyMeasurementMode_PLL,
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MemoryFrequencyMeasurementMode_EnumMax,
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} MemoryFrequencyMeasurementMode;
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#define HOCCLK_ENUM_VALID(n, v) ((v) < n##_EnumMax)
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// Packed u32
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@@ -68,6 +68,8 @@ typedef enum {
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HocClkConfigValue_CpuGovernorMinimumFreq,
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HocClkConfigValue_DisplayVoltage,
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HocClkConfigValue_MemoryFrequencyMeasurementMode,
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KipConfigValue_custRev,
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// KipConfigValue_mtcConf,
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KipConfigValue_hpMode,
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@@ -257,6 +259,9 @@ static inline const char* hocclkFormatConfigValue(HocClkConfigValue val, bool pr
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case HocClkConfigValue_DisplayVoltage:
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return pretty ? "Display Voltage" : "display_voltage";
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case HocClkConfigValue_MemoryFrequencyMeasurementMode:
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return pretty ? "Memory Frequency Measurement Mode" : "mem_freq_measurement_mode";
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// KIP config values
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case KipConfigValue_custRev:
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return pretty ? "Custom Revision" : "kip_cust_rev";
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@@ -436,6 +441,7 @@ static inline uint64_t hocclkDefaultConfigValue(HocClkConfigValue val)
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case HocClkConfigValue_GPUScheduling:
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case HocClkConfigValue_LiveCpuUv:
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case HocClkConfigValue_GPUSchedulingMethod:
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case HocClkConfigValue_MemoryFrequencyMeasurementMode:
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return 0ULL;
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case HocClkConfigValue_EristaMaxCpuClock:
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return 1785ULL;
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@@ -592,6 +598,7 @@ static inline uint64_t hocclkValidConfigValue(HocClkConfigValue val, uint64_t in
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case HocClkConfigValue_GPUScheduling:
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case HocClkConfigValue_RAMVoltDisplayMode:
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case HocClkConfigValue_CpuGovernorMinimumFreq:
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case HocClkConfigValue_MemoryFrequencyMeasurementMode:
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return true;
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case HocClkConfigValue_BatteryChargeCurrent:
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return ((input >= 1024) && (input <= 3072)) || !input;
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@@ -525,3 +525,24 @@
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#define CL_DVFS_I2C_STS_0 0x48
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#define CL_DVFS_INTR_STS_0 0x5C
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#define CL_DVFS_I2C_CLK_DIVISOR_REGISTER_0 0x16C
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#define CLK_SOURCE_EMC 0x19c
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#define PLLC_BASE 0x080
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#define PLLM_BASE 0x090
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#define PLLP_BASE 0x0a0
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#define PLLA_BASE 0x0b0
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#define PLLU_BASE 0x0c0
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#define _PLLD_BASE 0x0d0
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#define PLLX_BASE 0x0e0
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#define PLLE_BASE 0x0e8
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#define PLLC2_BASE 0x4e8
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#define PLLC3_BASE 0x4fc
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#define PLLD2_BASE 0x4b8
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#define PLLRE_BASE 0x4c4
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#define PLLC4_BASE 0x5a4
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#define PLLMB_BASE 0x5e8
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#define PLLA1_BASE 0x6a4
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#define PLLDP_BASE 0x590
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#define OSC_HZ 38400000ULL
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