Merge branch 'master' into high-freq
This commit is contained in:
Souldbminer
45
.clang-format
Normal file
45
.clang-format
Normal file
@@ -0,0 +1,45 @@
|
||||
# A .clang-format file to adhere to the K&R style
|
||||
# - CLANG-FORMAT STYLE OPTIONS: https://clang.llvm.org/docs/ClangFormatStyleOptions.html
|
||||
#
|
||||
# Author: Munseong Jeong <ryan.m.jeong@hotmail.com>
|
||||
|
||||
BasedOnStyle: LLVM
|
||||
IndentWidth: 4
|
||||
UseTab: Never
|
||||
|
||||
BreakBeforeBraces: Linux
|
||||
BraceWrapping:
|
||||
AfterControlStatement: false
|
||||
AfterFunction: true
|
||||
AfterClass: false
|
||||
AfterStruct: false
|
||||
AfterUnion: false
|
||||
AfterNamespace: false
|
||||
AfterEnum: false
|
||||
BeforeCatch: false
|
||||
BeforeElse: false
|
||||
IndentBraces: false
|
||||
|
||||
ContinuationIndentWidth: 0
|
||||
AlignAfterOpenBracket: false
|
||||
AllowShortIfStatementsOnASingleLine: false
|
||||
AllowShortLoopsOnASingleLine: false
|
||||
AllowShortBlocksOnASingleLine: Always
|
||||
IndentCaseLabels: false
|
||||
SpaceAfterCStyleCast: true
|
||||
AllowShortFunctionsOnASingleLine: None
|
||||
ColumnLimit: 80
|
||||
MaxEmptyLinesToKeep: 1
|
||||
Cpp11BracedListStyle: false
|
||||
AlignTrailingComments: true
|
||||
ReflowComments: true
|
||||
|
||||
SpacesBeforeTrailingComments: 2
|
||||
IncludeBlocks: Regroup
|
||||
IncludeCategories:
|
||||
- Regex: '<[[:alnum:].]+>'
|
||||
Priority: 1
|
||||
- Regex: '.*'
|
||||
Priority: 2
|
||||
SortIncludes: CaseSensitive
|
||||
AlignEscapedNewlines: Left
|
||||
3
.github/FUNDING.yml
vendored
Normal file
3
.github/FUNDING.yml
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# Donate to us!
|
||||
|
||||
https://ko-fi.com/souldbminer
|
||||
6
.gitignore
vendored
6
.gitignore
vendored
@@ -1,5 +1,7 @@
|
||||
*.DS_Store
|
||||
.vscode/
|
||||
build/
|
||||
dist/
|
||||
.pyc
|
||||
.pyc
|
||||
build/
|
||||
__pycache__/
|
||||
build
|
||||
|
||||
3
.gitmodules
vendored
3
.gitmodules
vendored
@@ -0,0 +1,3 @@
|
||||
[submodule "source/sys-clk/overlay/lib/libultrahand"]
|
||||
path = source/sys-clk/overlay/lib/libultrahand
|
||||
url = https://github.com/ppkantorski/libultrahand.git
|
||||
|
||||
4
LICENSE
4
LICENSE
@@ -1,10 +1,10 @@
|
||||
- "libstratosphere", "loader" from Atmosphere-NX and "memtester" are licensed under GPL v2.
|
||||
|
||||
- "libultrahand" by b0redtoauth is licensed under the CC-BY-4.0 license, which is compatible with GPLv2
|
||||
- "libultrahand" by b0redt0death is licensed under the CC-BY-4.0 license, which is compatible with GPLv2
|
||||
|
||||
- Tinymembench is under MIT license, which is compatible with GPL v2.
|
||||
|
||||
- Although "sys-clk" uses permissive license, all modifications towards it in this repo ("sys-clk-OC") are licensed under GPL v2.
|
||||
- Although "sys-clk" uses permissive license, all modifications towards it in this repo ("hoc-sys") are licensed under GPL v2.
|
||||
|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
|
||||
10
README.md
10
README.md
@@ -24,7 +24,7 @@
|
||||
|
||||
---
|
||||
|
||||
## 🌀 About
|
||||
## About
|
||||
|
||||
**Horizon OC** is an open-source overclocking tool for Nintendo Switch consoles running **Atmosphere custom firmware**.
|
||||
It enables advanced CPU, GPU, and RAM tuning with user-friendly configuration tools.
|
||||
@@ -40,8 +40,8 @@ It enables advanced CPU, GPU, and RAM tuning with user-friendly configuration to
|
||||
* Built-in configurator
|
||||
* Compatible with most homebrew
|
||||
|
||||
> ⚡ *Higher (potentially dangerous) frequencies are unlockable.*
|
||||
> ⚙️ *Exact maximum values vary per console.*
|
||||
> *Higher (potentially dangerous) frequencies are unlockable.*
|
||||
> *Exact maximum values vary per console.*
|
||||
|
||||
---
|
||||
|
||||
@@ -84,12 +84,14 @@ It enables advanced CPU, GPU, and RAM tuning with user-friendly configuration to
|
||||
```
|
||||
3. Move the cloned folder into `build/`.
|
||||
4. Insert your `Source/stratosphere` folder into `build/`.
|
||||
5. Run:
|
||||
5. Run: (On Windows you need to use "make -j %NUMBER_OF_PROCESSORS%")
|
||||
|
||||
```bash
|
||||
./build.sh
|
||||
```
|
||||
|
||||
|
||||
|
||||
To build the Configurator:
|
||||
|
||||
```bash
|
||||
|
||||
25
Source/Atmosphere-Patches/secmon_define_emc_access_table.inc
Normal file
25
Source/Atmosphere-Patches/secmon_define_emc_access_table.inc
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#define __ACCESS_TABLE_NAME__ EmcAccessTable
|
||||
#define __ACCESS_TABLE_ADDRESS__ MemoryRegionPhysicalDeviceExternalMemoryController.GetAddress()
|
||||
#define __ACCESS_TABLE_INC__ "secmon_emc_access_table_data.inc"
|
||||
|
||||
#include "secmon_define_access_table.inc"
|
||||
|
||||
#undef __ACCESS_TABLE_INC__
|
||||
#undef __ACCESS_TABLE_ADDRESS__
|
||||
#undef __ACCESS_TABLE_NAME__
|
||||
967
Source/Atmosphere-Patches/secmon_emc_access_table_data.inc
Normal file
967
Source/Atmosphere-Patches/secmon_emc_access_table_data.inc
Normal file
@@ -0,0 +1,967 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
SetRegisterAllowed(0x0);
|
||||
SetRegisterAllowed(0x4);
|
||||
SetRegisterAllowed(0x8);
|
||||
SetRegisterAllowed(0xC);
|
||||
SetRegisterAllowed(0x10);
|
||||
SetRegisterAllowed(0x14);
|
||||
SetRegisterAllowed(0x18);
|
||||
SetRegisterAllowed(0x1C);
|
||||
SetRegisterAllowed(0x20);
|
||||
SetRegisterAllowed(0x24);
|
||||
SetRegisterAllowed(0x28);
|
||||
SetRegisterAllowed(0x2C);
|
||||
SetRegisterAllowed(0x30);
|
||||
SetRegisterAllowed(0x34);
|
||||
SetRegisterAllowed(0x38);
|
||||
SetRegisterAllowed(0x3C);
|
||||
SetRegisterAllowed(0x40);
|
||||
SetRegisterAllowed(0x44);
|
||||
SetRegisterAllowed(0x48);
|
||||
SetRegisterAllowed(0x4C);
|
||||
SetRegisterAllowed(0x50);
|
||||
SetRegisterAllowed(0x54);
|
||||
SetRegisterAllowed(0x58);
|
||||
SetRegisterAllowed(0x5C);
|
||||
SetRegisterAllowed(0x60);
|
||||
SetRegisterAllowed(0x64);
|
||||
SetRegisterAllowed(0x68);
|
||||
SetRegisterAllowed(0x6C);
|
||||
SetRegisterAllowed(0x70);
|
||||
SetRegisterAllowed(0x74);
|
||||
SetRegisterAllowed(0x78);
|
||||
SetRegisterAllowed(0x7C);
|
||||
SetRegisterAllowed(0x80);
|
||||
SetRegisterAllowed(0x84);
|
||||
SetRegisterAllowed(0x88);
|
||||
SetRegisterAllowed(0x8C);
|
||||
SetRegisterAllowed(0x90);
|
||||
SetRegisterAllowed(0x94);
|
||||
SetRegisterAllowed(0x98);
|
||||
SetRegisterAllowed(0x9C);
|
||||
SetRegisterAllowed(0xA0);
|
||||
SetRegisterAllowed(0xA4);
|
||||
SetRegisterAllowed(0xA8);
|
||||
SetRegisterAllowed(0xAC);
|
||||
SetRegisterAllowed(0xB0);
|
||||
SetRegisterAllowed(0xB4);
|
||||
SetRegisterAllowed(0xB8);
|
||||
SetRegisterAllowed(0xBC);
|
||||
SetRegisterAllowed(0xC0);
|
||||
SetRegisterAllowed(0xC4);
|
||||
SetRegisterAllowed(0xC8);
|
||||
SetRegisterAllowed(0xCC);
|
||||
SetRegisterAllowed(0xD0);
|
||||
SetRegisterAllowed(0xD4);
|
||||
SetRegisterAllowed(0xD8);
|
||||
SetRegisterAllowed(0xDC);
|
||||
SetRegisterAllowed(0xE0);
|
||||
SetRegisterAllowed(0xE4);
|
||||
SetRegisterAllowed(0xE8);
|
||||
SetRegisterAllowed(0xEC);
|
||||
SetRegisterAllowed(0xF0);
|
||||
SetRegisterAllowed(0xF4);
|
||||
SetRegisterAllowed(0xF8);
|
||||
SetRegisterAllowed(0xFC);
|
||||
SetRegisterAllowed(0x100);
|
||||
SetRegisterAllowed(0x104);
|
||||
SetRegisterAllowed(0x108);
|
||||
SetRegisterAllowed(0x10C);
|
||||
SetRegisterAllowed(0x110);
|
||||
SetRegisterAllowed(0x114);
|
||||
SetRegisterAllowed(0x118);
|
||||
SetRegisterAllowed(0x11C);
|
||||
SetRegisterAllowed(0x120);
|
||||
SetRegisterAllowed(0x124);
|
||||
SetRegisterAllowed(0x128);
|
||||
SetRegisterAllowed(0x12C);
|
||||
SetRegisterAllowed(0x130);
|
||||
SetRegisterAllowed(0x134);
|
||||
SetRegisterAllowed(0x138);
|
||||
SetRegisterAllowed(0x13C);
|
||||
SetRegisterAllowed(0x140);
|
||||
SetRegisterAllowed(0x144);
|
||||
SetRegisterAllowed(0x148);
|
||||
SetRegisterAllowed(0x14C);
|
||||
SetRegisterAllowed(0x150);
|
||||
SetRegisterAllowed(0x154);
|
||||
SetRegisterAllowed(0x158);
|
||||
SetRegisterAllowed(0x15C);
|
||||
SetRegisterAllowed(0x160);
|
||||
SetRegisterAllowed(0x164);
|
||||
SetRegisterAllowed(0x168);
|
||||
SetRegisterAllowed(0x16C);
|
||||
SetRegisterAllowed(0x170);
|
||||
SetRegisterAllowed(0x174);
|
||||
SetRegisterAllowed(0x178);
|
||||
SetRegisterAllowed(0x17C);
|
||||
SetRegisterAllowed(0x180);
|
||||
SetRegisterAllowed(0x184);
|
||||
SetRegisterAllowed(0x188);
|
||||
SetRegisterAllowed(0x18C);
|
||||
SetRegisterAllowed(0x190);
|
||||
SetRegisterAllowed(0x194);
|
||||
SetRegisterAllowed(0x198);
|
||||
SetRegisterAllowed(0x19C);
|
||||
SetRegisterAllowed(0x1A0);
|
||||
SetRegisterAllowed(0x1A4);
|
||||
SetRegisterAllowed(0x1A8);
|
||||
SetRegisterAllowed(0x1AC);
|
||||
SetRegisterAllowed(0x1B0);
|
||||
SetRegisterAllowed(0x1B4);
|
||||
SetRegisterAllowed(0x1B8);
|
||||
SetRegisterAllowed(0x1BC);
|
||||
SetRegisterAllowed(0x1C0);
|
||||
SetRegisterAllowed(0x1C4);
|
||||
SetRegisterAllowed(0x1C8);
|
||||
SetRegisterAllowed(0x1CC);
|
||||
SetRegisterAllowed(0x1D0);
|
||||
SetRegisterAllowed(0x1D4);
|
||||
SetRegisterAllowed(0x1D8);
|
||||
SetRegisterAllowed(0x1DC);
|
||||
SetRegisterAllowed(0x1E0);
|
||||
SetRegisterAllowed(0x1E4);
|
||||
SetRegisterAllowed(0x1E8);
|
||||
SetRegisterAllowed(0x1EC);
|
||||
SetRegisterAllowed(0x1F0);
|
||||
SetRegisterAllowed(0x1F4);
|
||||
SetRegisterAllowed(0x1F8);
|
||||
SetRegisterAllowed(0x1FC);
|
||||
SetRegisterAllowed(0x200);
|
||||
SetRegisterAllowed(0x204);
|
||||
SetRegisterAllowed(0x208);
|
||||
SetRegisterAllowed(0x20C);
|
||||
SetRegisterAllowed(0x210);
|
||||
SetRegisterAllowed(0x214);
|
||||
SetRegisterAllowed(0x218);
|
||||
SetRegisterAllowed(0x21C);
|
||||
SetRegisterAllowed(0x220);
|
||||
SetRegisterAllowed(0x224);
|
||||
SetRegisterAllowed(0x228);
|
||||
SetRegisterAllowed(0x22C);
|
||||
SetRegisterAllowed(0x230);
|
||||
SetRegisterAllowed(0x234);
|
||||
SetRegisterAllowed(0x238);
|
||||
SetRegisterAllowed(0x23C);
|
||||
SetRegisterAllowed(0x240);
|
||||
SetRegisterAllowed(0x244);
|
||||
SetRegisterAllowed(0x248);
|
||||
SetRegisterAllowed(0x24C);
|
||||
SetRegisterAllowed(0x250);
|
||||
SetRegisterAllowed(0x254);
|
||||
SetRegisterAllowed(0x258);
|
||||
SetRegisterAllowed(0x25C);
|
||||
SetRegisterAllowed(0x260);
|
||||
SetRegisterAllowed(0x264);
|
||||
SetRegisterAllowed(0x268);
|
||||
SetRegisterAllowed(0x26C);
|
||||
SetRegisterAllowed(0x270);
|
||||
SetRegisterAllowed(0x274);
|
||||
SetRegisterAllowed(0x278);
|
||||
SetRegisterAllowed(0x27C);
|
||||
SetRegisterAllowed(0x280);
|
||||
SetRegisterAllowed(0x284);
|
||||
SetRegisterAllowed(0x288);
|
||||
SetRegisterAllowed(0x28C);
|
||||
SetRegisterAllowed(0x290);
|
||||
SetRegisterAllowed(0x294);
|
||||
SetRegisterAllowed(0x298);
|
||||
SetRegisterAllowed(0x29C);
|
||||
SetRegisterAllowed(0x2A0);
|
||||
SetRegisterAllowed(0x2A4);
|
||||
SetRegisterAllowed(0x2A8);
|
||||
SetRegisterAllowed(0x2AC);
|
||||
SetRegisterAllowed(0x2B0);
|
||||
SetRegisterAllowed(0x2B4);
|
||||
SetRegisterAllowed(0x2B8);
|
||||
SetRegisterAllowed(0x2BC);
|
||||
SetRegisterAllowed(0x2C0);
|
||||
SetRegisterAllowed(0x2C4);
|
||||
SetRegisterAllowed(0x2C8);
|
||||
SetRegisterAllowed(0x2CC);
|
||||
SetRegisterAllowed(0x2D0);
|
||||
SetRegisterAllowed(0x2D4);
|
||||
SetRegisterAllowed(0x2D8);
|
||||
SetRegisterAllowed(0x2DC);
|
||||
SetRegisterAllowed(0x2E0);
|
||||
SetRegisterAllowed(0x2E4);
|
||||
SetRegisterAllowed(0x2E8);
|
||||
SetRegisterAllowed(0x2EC);
|
||||
SetRegisterAllowed(0x2F0);
|
||||
SetRegisterAllowed(0x2F4);
|
||||
SetRegisterAllowed(0x2F8);
|
||||
SetRegisterAllowed(0x2FC);
|
||||
SetRegisterAllowed(0x300);
|
||||
SetRegisterAllowed(0x304);
|
||||
SetRegisterAllowed(0x308);
|
||||
SetRegisterAllowed(0x30C);
|
||||
SetRegisterAllowed(0x310);
|
||||
SetRegisterAllowed(0x314);
|
||||
SetRegisterAllowed(0x318);
|
||||
SetRegisterAllowed(0x31C);
|
||||
SetRegisterAllowed(0x320);
|
||||
SetRegisterAllowed(0x324);
|
||||
SetRegisterAllowed(0x328);
|
||||
SetRegisterAllowed(0x32C);
|
||||
SetRegisterAllowed(0x330);
|
||||
SetRegisterAllowed(0x334);
|
||||
SetRegisterAllowed(0x338);
|
||||
SetRegisterAllowed(0x33C);
|
||||
SetRegisterAllowed(0x340);
|
||||
SetRegisterAllowed(0x344);
|
||||
SetRegisterAllowed(0x348);
|
||||
SetRegisterAllowed(0x34C);
|
||||
SetRegisterAllowed(0x350);
|
||||
SetRegisterAllowed(0x354);
|
||||
SetRegisterAllowed(0x358);
|
||||
SetRegisterAllowed(0x35C);
|
||||
SetRegisterAllowed(0x360);
|
||||
SetRegisterAllowed(0x364);
|
||||
SetRegisterAllowed(0x368);
|
||||
SetRegisterAllowed(0x36C);
|
||||
SetRegisterAllowed(0x370);
|
||||
SetRegisterAllowed(0x374);
|
||||
SetRegisterAllowed(0x378);
|
||||
SetRegisterAllowed(0x37C);
|
||||
SetRegisterAllowed(0x380);
|
||||
SetRegisterAllowed(0x384);
|
||||
SetRegisterAllowed(0x388);
|
||||
SetRegisterAllowed(0x38C);
|
||||
SetRegisterAllowed(0x390);
|
||||
SetRegisterAllowed(0x394);
|
||||
SetRegisterAllowed(0x398);
|
||||
SetRegisterAllowed(0x39C);
|
||||
SetRegisterAllowed(0x3A0);
|
||||
SetRegisterAllowed(0x3A4);
|
||||
SetRegisterAllowed(0x3A8);
|
||||
SetRegisterAllowed(0x3AC);
|
||||
SetRegisterAllowed(0x3B0);
|
||||
SetRegisterAllowed(0x3B4);
|
||||
SetRegisterAllowed(0x3B8);
|
||||
SetRegisterAllowed(0x3BC);
|
||||
SetRegisterAllowed(0x3C0);
|
||||
SetRegisterAllowed(0x3C4);
|
||||
SetRegisterAllowed(0x3C8);
|
||||
SetRegisterAllowed(0x3CC);
|
||||
SetRegisterAllowed(0x3D0);
|
||||
SetRegisterAllowed(0x3D4);
|
||||
SetRegisterAllowed(0x3D8);
|
||||
SetRegisterAllowed(0x3DC);
|
||||
SetRegisterAllowed(0x3E0);
|
||||
SetRegisterAllowed(0x3E4);
|
||||
SetRegisterAllowed(0x3E8);
|
||||
SetRegisterAllowed(0x3EC);
|
||||
SetRegisterAllowed(0x3F0);
|
||||
SetRegisterAllowed(0x3F4);
|
||||
SetRegisterAllowed(0x3F8);
|
||||
SetRegisterAllowed(0x3FC);
|
||||
SetRegisterAllowed(0x400);
|
||||
SetRegisterAllowed(0x404);
|
||||
SetRegisterAllowed(0x408);
|
||||
SetRegisterAllowed(0x40C);
|
||||
SetRegisterAllowed(0x410);
|
||||
SetRegisterAllowed(0x414);
|
||||
SetRegisterAllowed(0x418);
|
||||
SetRegisterAllowed(0x41C);
|
||||
SetRegisterAllowed(0x420);
|
||||
SetRegisterAllowed(0x424);
|
||||
SetRegisterAllowed(0x428);
|
||||
SetRegisterAllowed(0x42C);
|
||||
SetRegisterAllowed(0x430);
|
||||
SetRegisterAllowed(0x434);
|
||||
SetRegisterAllowed(0x438);
|
||||
SetRegisterAllowed(0x43C);
|
||||
SetRegisterAllowed(0x440);
|
||||
SetRegisterAllowed(0x444);
|
||||
SetRegisterAllowed(0x448);
|
||||
SetRegisterAllowed(0x44C);
|
||||
SetRegisterAllowed(0x450);
|
||||
SetRegisterAllowed(0x454);
|
||||
SetRegisterAllowed(0x458);
|
||||
SetRegisterAllowed(0x45C);
|
||||
SetRegisterAllowed(0x460);
|
||||
SetRegisterAllowed(0x464);
|
||||
SetRegisterAllowed(0x468);
|
||||
SetRegisterAllowed(0x46C);
|
||||
SetRegisterAllowed(0x470);
|
||||
SetRegisterAllowed(0x474);
|
||||
SetRegisterAllowed(0x478);
|
||||
SetRegisterAllowed(0x47C);
|
||||
SetRegisterAllowed(0x480);
|
||||
SetRegisterAllowed(0x484);
|
||||
SetRegisterAllowed(0x488);
|
||||
SetRegisterAllowed(0x48C);
|
||||
SetRegisterAllowed(0x490);
|
||||
SetRegisterAllowed(0x494);
|
||||
SetRegisterAllowed(0x498);
|
||||
SetRegisterAllowed(0x49C);
|
||||
SetRegisterAllowed(0x4A0);
|
||||
SetRegisterAllowed(0x4A4);
|
||||
SetRegisterAllowed(0x4A8);
|
||||
SetRegisterAllowed(0x4AC);
|
||||
SetRegisterAllowed(0x4B0);
|
||||
SetRegisterAllowed(0x4B4);
|
||||
SetRegisterAllowed(0x4B8);
|
||||
SetRegisterAllowed(0x4BC);
|
||||
SetRegisterAllowed(0x4C0);
|
||||
SetRegisterAllowed(0x4C4);
|
||||
SetRegisterAllowed(0x4C8);
|
||||
SetRegisterAllowed(0x4CC);
|
||||
SetRegisterAllowed(0x4D0);
|
||||
SetRegisterAllowed(0x4D4);
|
||||
SetRegisterAllowed(0x4D8);
|
||||
SetRegisterAllowed(0x4DC);
|
||||
SetRegisterAllowed(0x4E0);
|
||||
SetRegisterAllowed(0x4E4);
|
||||
SetRegisterAllowed(0x4E8);
|
||||
SetRegisterAllowed(0x4EC);
|
||||
SetRegisterAllowed(0x4F0);
|
||||
SetRegisterAllowed(0x4F4);
|
||||
SetRegisterAllowed(0x4F8);
|
||||
SetRegisterAllowed(0x4FC);
|
||||
SetRegisterAllowed(0x500);
|
||||
SetRegisterAllowed(0x504);
|
||||
SetRegisterAllowed(0x508);
|
||||
SetRegisterAllowed(0x50C);
|
||||
SetRegisterAllowed(0x510);
|
||||
SetRegisterAllowed(0x514);
|
||||
SetRegisterAllowed(0x518);
|
||||
SetRegisterAllowed(0x51C);
|
||||
SetRegisterAllowed(0x520);
|
||||
SetRegisterAllowed(0x524);
|
||||
SetRegisterAllowed(0x528);
|
||||
SetRegisterAllowed(0x52C);
|
||||
SetRegisterAllowed(0x530);
|
||||
SetRegisterAllowed(0x534);
|
||||
SetRegisterAllowed(0x538);
|
||||
SetRegisterAllowed(0x53C);
|
||||
SetRegisterAllowed(0x540);
|
||||
SetRegisterAllowed(0x544);
|
||||
SetRegisterAllowed(0x548);
|
||||
SetRegisterAllowed(0x54C);
|
||||
SetRegisterAllowed(0x550);
|
||||
SetRegisterAllowed(0x554);
|
||||
SetRegisterAllowed(0x558);
|
||||
SetRegisterAllowed(0x55C);
|
||||
SetRegisterAllowed(0x560);
|
||||
SetRegisterAllowed(0x564);
|
||||
SetRegisterAllowed(0x568);
|
||||
SetRegisterAllowed(0x56C);
|
||||
SetRegisterAllowed(0x570);
|
||||
SetRegisterAllowed(0x574);
|
||||
SetRegisterAllowed(0x578);
|
||||
SetRegisterAllowed(0x57C);
|
||||
SetRegisterAllowed(0x580);
|
||||
SetRegisterAllowed(0x584);
|
||||
SetRegisterAllowed(0x588);
|
||||
SetRegisterAllowed(0x58C);
|
||||
SetRegisterAllowed(0x590);
|
||||
SetRegisterAllowed(0x594);
|
||||
SetRegisterAllowed(0x598);
|
||||
SetRegisterAllowed(0x59C);
|
||||
SetRegisterAllowed(0x5A0);
|
||||
SetRegisterAllowed(0x5A4);
|
||||
SetRegisterAllowed(0x5A8);
|
||||
SetRegisterAllowed(0x5AC);
|
||||
SetRegisterAllowed(0x5B0);
|
||||
SetRegisterAllowed(0x5B4);
|
||||
SetRegisterAllowed(0x5B8);
|
||||
SetRegisterAllowed(0x5BC);
|
||||
SetRegisterAllowed(0x5C0);
|
||||
SetRegisterAllowed(0x5C4);
|
||||
SetRegisterAllowed(0x5C8);
|
||||
SetRegisterAllowed(0x5CC);
|
||||
SetRegisterAllowed(0x5D0);
|
||||
SetRegisterAllowed(0x5D4);
|
||||
SetRegisterAllowed(0x5D8);
|
||||
SetRegisterAllowed(0x5DC);
|
||||
SetRegisterAllowed(0x5E0);
|
||||
SetRegisterAllowed(0x5E4);
|
||||
SetRegisterAllowed(0x5E8);
|
||||
SetRegisterAllowed(0x5EC);
|
||||
SetRegisterAllowed(0x5F0);
|
||||
SetRegisterAllowed(0x5F4);
|
||||
SetRegisterAllowed(0x5F8);
|
||||
SetRegisterAllowed(0x5FC);
|
||||
SetRegisterAllowed(0x600);
|
||||
SetRegisterAllowed(0x604);
|
||||
SetRegisterAllowed(0x608);
|
||||
SetRegisterAllowed(0x60C);
|
||||
SetRegisterAllowed(0x610);
|
||||
SetRegisterAllowed(0x614);
|
||||
SetRegisterAllowed(0x618);
|
||||
SetRegisterAllowed(0x61C);
|
||||
SetRegisterAllowed(0x620);
|
||||
SetRegisterAllowed(0x624);
|
||||
SetRegisterAllowed(0x628);
|
||||
SetRegisterAllowed(0x62C);
|
||||
SetRegisterAllowed(0x630);
|
||||
SetRegisterAllowed(0x634);
|
||||
SetRegisterAllowed(0x638);
|
||||
SetRegisterAllowed(0x63C);
|
||||
SetRegisterAllowed(0x640);
|
||||
SetRegisterAllowed(0x644);
|
||||
SetRegisterAllowed(0x648);
|
||||
SetRegisterAllowed(0x64C);
|
||||
SetRegisterAllowed(0x650);
|
||||
SetRegisterAllowed(0x654);
|
||||
SetRegisterAllowed(0x658);
|
||||
SetRegisterAllowed(0x65C);
|
||||
SetRegisterAllowed(0x660);
|
||||
SetRegisterAllowed(0x664);
|
||||
SetRegisterAllowed(0x668);
|
||||
SetRegisterAllowed(0x66C);
|
||||
SetRegisterAllowed(0x670);
|
||||
SetRegisterAllowed(0x674);
|
||||
SetRegisterAllowed(0x678);
|
||||
SetRegisterAllowed(0x67C);
|
||||
SetRegisterAllowed(0x680);
|
||||
SetRegisterAllowed(0x684);
|
||||
SetRegisterAllowed(0x688);
|
||||
SetRegisterAllowed(0x68C);
|
||||
SetRegisterAllowed(0x690);
|
||||
SetRegisterAllowed(0x694);
|
||||
SetRegisterAllowed(0x698);
|
||||
SetRegisterAllowed(0x69C);
|
||||
SetRegisterAllowed(0x6A0);
|
||||
SetRegisterAllowed(0x6A4);
|
||||
SetRegisterAllowed(0x6A8);
|
||||
SetRegisterAllowed(0x6AC);
|
||||
SetRegisterAllowed(0x6B0);
|
||||
SetRegisterAllowed(0x6B4);
|
||||
SetRegisterAllowed(0x6B8);
|
||||
SetRegisterAllowed(0x6BC);
|
||||
SetRegisterAllowed(0x6C0);
|
||||
SetRegisterAllowed(0x6C4);
|
||||
SetRegisterAllowed(0x6C8);
|
||||
SetRegisterAllowed(0x6CC);
|
||||
SetRegisterAllowed(0x6D0);
|
||||
SetRegisterAllowed(0x6D4);
|
||||
SetRegisterAllowed(0x6D8);
|
||||
SetRegisterAllowed(0x6DC);
|
||||
SetRegisterAllowed(0x6E0);
|
||||
SetRegisterAllowed(0x6E4);
|
||||
SetRegisterAllowed(0x6E8);
|
||||
SetRegisterAllowed(0x6EC);
|
||||
SetRegisterAllowed(0x6F0);
|
||||
SetRegisterAllowed(0x6F4);
|
||||
SetRegisterAllowed(0x6F8);
|
||||
SetRegisterAllowed(0x6FC);
|
||||
SetRegisterAllowed(0x700);
|
||||
SetRegisterAllowed(0x704);
|
||||
SetRegisterAllowed(0x708);
|
||||
SetRegisterAllowed(0x70C);
|
||||
SetRegisterAllowed(0x710);
|
||||
SetRegisterAllowed(0x714);
|
||||
SetRegisterAllowed(0x718);
|
||||
SetRegisterAllowed(0x71C);
|
||||
SetRegisterAllowed(0x720);
|
||||
SetRegisterAllowed(0x724);
|
||||
SetRegisterAllowed(0x728);
|
||||
SetRegisterAllowed(0x72C);
|
||||
SetRegisterAllowed(0x730);
|
||||
SetRegisterAllowed(0x734);
|
||||
SetRegisterAllowed(0x738);
|
||||
SetRegisterAllowed(0x73C);
|
||||
SetRegisterAllowed(0x740);
|
||||
SetRegisterAllowed(0x744);
|
||||
SetRegisterAllowed(0x748);
|
||||
SetRegisterAllowed(0x74C);
|
||||
SetRegisterAllowed(0x750);
|
||||
SetRegisterAllowed(0x754);
|
||||
SetRegisterAllowed(0x758);
|
||||
SetRegisterAllowed(0x75C);
|
||||
SetRegisterAllowed(0x760);
|
||||
SetRegisterAllowed(0x764);
|
||||
SetRegisterAllowed(0x768);
|
||||
SetRegisterAllowed(0x76C);
|
||||
SetRegisterAllowed(0x770);
|
||||
SetRegisterAllowed(0x774);
|
||||
SetRegisterAllowed(0x778);
|
||||
SetRegisterAllowed(0x77C);
|
||||
SetRegisterAllowed(0x780);
|
||||
SetRegisterAllowed(0x784);
|
||||
SetRegisterAllowed(0x788);
|
||||
SetRegisterAllowed(0x78C);
|
||||
SetRegisterAllowed(0x790);
|
||||
SetRegisterAllowed(0x794);
|
||||
SetRegisterAllowed(0x798);
|
||||
SetRegisterAllowed(0x79C);
|
||||
SetRegisterAllowed(0x7A0);
|
||||
SetRegisterAllowed(0x7A4);
|
||||
SetRegisterAllowed(0x7A8);
|
||||
SetRegisterAllowed(0x7AC);
|
||||
SetRegisterAllowed(0x7B0);
|
||||
SetRegisterAllowed(0x7B4);
|
||||
SetRegisterAllowed(0x7B8);
|
||||
SetRegisterAllowed(0x7BC);
|
||||
SetRegisterAllowed(0x7C0);
|
||||
SetRegisterAllowed(0x7C4);
|
||||
SetRegisterAllowed(0x7C8);
|
||||
SetRegisterAllowed(0x7CC);
|
||||
SetRegisterAllowed(0x7D0);
|
||||
SetRegisterAllowed(0x7D4);
|
||||
SetRegisterAllowed(0x7D8);
|
||||
SetRegisterAllowed(0x7DC);
|
||||
SetRegisterAllowed(0x7E0);
|
||||
SetRegisterAllowed(0x7E4);
|
||||
SetRegisterAllowed(0x7E8);
|
||||
SetRegisterAllowed(0x7EC);
|
||||
SetRegisterAllowed(0x7F0);
|
||||
SetRegisterAllowed(0x7F4);
|
||||
SetRegisterAllowed(0x7F8);
|
||||
SetRegisterAllowed(0x7FC);
|
||||
SetRegisterAllowed(0x800);
|
||||
SetRegisterAllowed(0x804);
|
||||
SetRegisterAllowed(0x808);
|
||||
SetRegisterAllowed(0x80C);
|
||||
SetRegisterAllowed(0x810);
|
||||
SetRegisterAllowed(0x814);
|
||||
SetRegisterAllowed(0x818);
|
||||
SetRegisterAllowed(0x81C);
|
||||
SetRegisterAllowed(0x820);
|
||||
SetRegisterAllowed(0x824);
|
||||
SetRegisterAllowed(0x828);
|
||||
SetRegisterAllowed(0x82C);
|
||||
SetRegisterAllowed(0x830);
|
||||
SetRegisterAllowed(0x834);
|
||||
SetRegisterAllowed(0x838);
|
||||
SetRegisterAllowed(0x83C);
|
||||
SetRegisterAllowed(0x840);
|
||||
SetRegisterAllowed(0x844);
|
||||
SetRegisterAllowed(0x848);
|
||||
SetRegisterAllowed(0x84C);
|
||||
SetRegisterAllowed(0x850);
|
||||
SetRegisterAllowed(0x854);
|
||||
SetRegisterAllowed(0x858);
|
||||
SetRegisterAllowed(0x85C);
|
||||
SetRegisterAllowed(0x860);
|
||||
SetRegisterAllowed(0x864);
|
||||
SetRegisterAllowed(0x868);
|
||||
SetRegisterAllowed(0x86C);
|
||||
SetRegisterAllowed(0x870);
|
||||
SetRegisterAllowed(0x874);
|
||||
SetRegisterAllowed(0x878);
|
||||
SetRegisterAllowed(0x87C);
|
||||
SetRegisterAllowed(0x880);
|
||||
SetRegisterAllowed(0x884);
|
||||
SetRegisterAllowed(0x888);
|
||||
SetRegisterAllowed(0x88C);
|
||||
SetRegisterAllowed(0x890);
|
||||
SetRegisterAllowed(0x894);
|
||||
SetRegisterAllowed(0x898);
|
||||
SetRegisterAllowed(0x89C);
|
||||
SetRegisterAllowed(0x8A0);
|
||||
SetRegisterAllowed(0x8A4);
|
||||
SetRegisterAllowed(0x8A8);
|
||||
SetRegisterAllowed(0x8AC);
|
||||
SetRegisterAllowed(0x8B0);
|
||||
SetRegisterAllowed(0x8B4);
|
||||
SetRegisterAllowed(0x8B8);
|
||||
SetRegisterAllowed(0x8BC);
|
||||
SetRegisterAllowed(0x8C0);
|
||||
SetRegisterAllowed(0x8C4);
|
||||
SetRegisterAllowed(0x8C8);
|
||||
SetRegisterAllowed(0x8CC);
|
||||
SetRegisterAllowed(0x8D0);
|
||||
SetRegisterAllowed(0x8D4);
|
||||
SetRegisterAllowed(0x8D8);
|
||||
SetRegisterAllowed(0x8DC);
|
||||
SetRegisterAllowed(0x8E0);
|
||||
SetRegisterAllowed(0x8E4);
|
||||
SetRegisterAllowed(0x8E8);
|
||||
SetRegisterAllowed(0x8EC);
|
||||
SetRegisterAllowed(0x8F0);
|
||||
SetRegisterAllowed(0x8F4);
|
||||
SetRegisterAllowed(0x8F8);
|
||||
SetRegisterAllowed(0x8FC);
|
||||
SetRegisterAllowed(0x900);
|
||||
SetRegisterAllowed(0x904);
|
||||
SetRegisterAllowed(0x908);
|
||||
SetRegisterAllowed(0x90C);
|
||||
SetRegisterAllowed(0x910);
|
||||
SetRegisterAllowed(0x914);
|
||||
SetRegisterAllowed(0x918);
|
||||
SetRegisterAllowed(0x91C);
|
||||
SetRegisterAllowed(0x920);
|
||||
SetRegisterAllowed(0x924);
|
||||
SetRegisterAllowed(0x928);
|
||||
SetRegisterAllowed(0x92C);
|
||||
SetRegisterAllowed(0x930);
|
||||
SetRegisterAllowed(0x934);
|
||||
SetRegisterAllowed(0x938);
|
||||
SetRegisterAllowed(0x93C);
|
||||
SetRegisterAllowed(0x940);
|
||||
SetRegisterAllowed(0x944);
|
||||
SetRegisterAllowed(0x948);
|
||||
SetRegisterAllowed(0x94C);
|
||||
SetRegisterAllowed(0x950);
|
||||
SetRegisterAllowed(0x954);
|
||||
SetRegisterAllowed(0x958);
|
||||
SetRegisterAllowed(0x95C);
|
||||
SetRegisterAllowed(0x960);
|
||||
SetRegisterAllowed(0x964);
|
||||
SetRegisterAllowed(0x968);
|
||||
SetRegisterAllowed(0x96C);
|
||||
SetRegisterAllowed(0x970);
|
||||
SetRegisterAllowed(0x974);
|
||||
SetRegisterAllowed(0x978);
|
||||
SetRegisterAllowed(0x97C);
|
||||
SetRegisterAllowed(0x980);
|
||||
SetRegisterAllowed(0x984);
|
||||
SetRegisterAllowed(0x988);
|
||||
SetRegisterAllowed(0x98C);
|
||||
SetRegisterAllowed(0x990);
|
||||
SetRegisterAllowed(0x994);
|
||||
SetRegisterAllowed(0x998);
|
||||
SetRegisterAllowed(0x99C);
|
||||
SetRegisterAllowed(0x9A0);
|
||||
SetRegisterAllowed(0x9A4);
|
||||
SetRegisterAllowed(0x9A8);
|
||||
SetRegisterAllowed(0x9AC);
|
||||
SetRegisterAllowed(0x9B0);
|
||||
SetRegisterAllowed(0x9B4);
|
||||
SetRegisterAllowed(0x9B8);
|
||||
SetRegisterAllowed(0x9BC);
|
||||
SetRegisterAllowed(0x9C0);
|
||||
SetRegisterAllowed(0x9C4);
|
||||
SetRegisterAllowed(0x9C8);
|
||||
SetRegisterAllowed(0x9CC);
|
||||
SetRegisterAllowed(0x9D0);
|
||||
SetRegisterAllowed(0x9D4);
|
||||
SetRegisterAllowed(0x9D8);
|
||||
SetRegisterAllowed(0x9DC);
|
||||
SetRegisterAllowed(0x9E0);
|
||||
SetRegisterAllowed(0x9E4);
|
||||
SetRegisterAllowed(0x9E8);
|
||||
SetRegisterAllowed(0x9EC);
|
||||
SetRegisterAllowed(0x9F0);
|
||||
SetRegisterAllowed(0x9F4);
|
||||
SetRegisterAllowed(0x9F8);
|
||||
SetRegisterAllowed(0x9FC);
|
||||
SetRegisterAllowed(0xA00);
|
||||
SetRegisterAllowed(0xA04);
|
||||
SetRegisterAllowed(0xA08);
|
||||
SetRegisterAllowed(0xA0C);
|
||||
SetRegisterAllowed(0xA10);
|
||||
SetRegisterAllowed(0xA14);
|
||||
SetRegisterAllowed(0xA18);
|
||||
SetRegisterAllowed(0xA1C);
|
||||
SetRegisterAllowed(0xA20);
|
||||
SetRegisterAllowed(0xA24);
|
||||
SetRegisterAllowed(0xA28);
|
||||
SetRegisterAllowed(0xA2C);
|
||||
SetRegisterAllowed(0xA30);
|
||||
SetRegisterAllowed(0xA34);
|
||||
SetRegisterAllowed(0xA38);
|
||||
SetRegisterAllowed(0xA3C);
|
||||
SetRegisterAllowed(0xA40);
|
||||
SetRegisterAllowed(0xA44);
|
||||
SetRegisterAllowed(0xA48);
|
||||
SetRegisterAllowed(0xA4C);
|
||||
SetRegisterAllowed(0xA50);
|
||||
SetRegisterAllowed(0xA54);
|
||||
SetRegisterAllowed(0xA58);
|
||||
SetRegisterAllowed(0xA5C);
|
||||
SetRegisterAllowed(0xA60);
|
||||
SetRegisterAllowed(0xA64);
|
||||
SetRegisterAllowed(0xA68);
|
||||
SetRegisterAllowed(0xA6C);
|
||||
SetRegisterAllowed(0xA70);
|
||||
SetRegisterAllowed(0xA74);
|
||||
SetRegisterAllowed(0xA78);
|
||||
SetRegisterAllowed(0xA7C);
|
||||
SetRegisterAllowed(0xA80);
|
||||
SetRegisterAllowed(0xA84);
|
||||
SetRegisterAllowed(0xA88);
|
||||
SetRegisterAllowed(0xA8C);
|
||||
SetRegisterAllowed(0xA90);
|
||||
SetRegisterAllowed(0xA94);
|
||||
SetRegisterAllowed(0xA98);
|
||||
SetRegisterAllowed(0xA9C);
|
||||
SetRegisterAllowed(0xAA0);
|
||||
SetRegisterAllowed(0xAA4);
|
||||
SetRegisterAllowed(0xAA8);
|
||||
SetRegisterAllowed(0xAAC);
|
||||
SetRegisterAllowed(0xAB0);
|
||||
SetRegisterAllowed(0xAB4);
|
||||
SetRegisterAllowed(0xAB8);
|
||||
SetRegisterAllowed(0xABC);
|
||||
SetRegisterAllowed(0xAC0);
|
||||
SetRegisterAllowed(0xAC4);
|
||||
SetRegisterAllowed(0xAC8);
|
||||
SetRegisterAllowed(0xACC);
|
||||
SetRegisterAllowed(0xAD0);
|
||||
SetRegisterAllowed(0xAD4);
|
||||
SetRegisterAllowed(0xAD8);
|
||||
SetRegisterAllowed(0xADC);
|
||||
SetRegisterAllowed(0xAE0);
|
||||
SetRegisterAllowed(0xAE4);
|
||||
SetRegisterAllowed(0xAE8);
|
||||
SetRegisterAllowed(0xAEC);
|
||||
SetRegisterAllowed(0xAF0);
|
||||
SetRegisterAllowed(0xAF4);
|
||||
SetRegisterAllowed(0xAF8);
|
||||
SetRegisterAllowed(0xAFC);
|
||||
SetRegisterAllowed(0xB00);
|
||||
SetRegisterAllowed(0xB04);
|
||||
SetRegisterAllowed(0xB08);
|
||||
SetRegisterAllowed(0xB0C);
|
||||
SetRegisterAllowed(0xB10);
|
||||
SetRegisterAllowed(0xB14);
|
||||
SetRegisterAllowed(0xB18);
|
||||
SetRegisterAllowed(0xB1C);
|
||||
SetRegisterAllowed(0xB20);
|
||||
SetRegisterAllowed(0xB24);
|
||||
SetRegisterAllowed(0xB28);
|
||||
SetRegisterAllowed(0xB2C);
|
||||
SetRegisterAllowed(0xB30);
|
||||
SetRegisterAllowed(0xB34);
|
||||
SetRegisterAllowed(0xB38);
|
||||
SetRegisterAllowed(0xB3C);
|
||||
SetRegisterAllowed(0xB40);
|
||||
SetRegisterAllowed(0xB44);
|
||||
SetRegisterAllowed(0xB48);
|
||||
SetRegisterAllowed(0xB4C);
|
||||
SetRegisterAllowed(0xB50);
|
||||
SetRegisterAllowed(0xB54);
|
||||
SetRegisterAllowed(0xB58);
|
||||
SetRegisterAllowed(0xB5C);
|
||||
SetRegisterAllowed(0xB60);
|
||||
SetRegisterAllowed(0xB64);
|
||||
SetRegisterAllowed(0xB68);
|
||||
SetRegisterAllowed(0xB6C);
|
||||
SetRegisterAllowed(0xB70);
|
||||
SetRegisterAllowed(0xB74);
|
||||
SetRegisterAllowed(0xB78);
|
||||
SetRegisterAllowed(0xB7C);
|
||||
SetRegisterAllowed(0xB80);
|
||||
SetRegisterAllowed(0xB84);
|
||||
SetRegisterAllowed(0xB88);
|
||||
SetRegisterAllowed(0xB8C);
|
||||
SetRegisterAllowed(0xB90);
|
||||
SetRegisterAllowed(0xB94);
|
||||
SetRegisterAllowed(0xB98);
|
||||
SetRegisterAllowed(0xB9C);
|
||||
SetRegisterAllowed(0xBA0);
|
||||
SetRegisterAllowed(0xBA4);
|
||||
SetRegisterAllowed(0xBA8);
|
||||
SetRegisterAllowed(0xBAC);
|
||||
SetRegisterAllowed(0xBB0);
|
||||
SetRegisterAllowed(0xBB4);
|
||||
SetRegisterAllowed(0xBB8);
|
||||
SetRegisterAllowed(0xBBC);
|
||||
SetRegisterAllowed(0xBC0);
|
||||
SetRegisterAllowed(0xBC4);
|
||||
SetRegisterAllowed(0xBC8);
|
||||
SetRegisterAllowed(0xBCC);
|
||||
SetRegisterAllowed(0xBD0);
|
||||
SetRegisterAllowed(0xBD4);
|
||||
SetRegisterAllowed(0xBD8);
|
||||
SetRegisterAllowed(0xBDC);
|
||||
SetRegisterAllowed(0xBE0);
|
||||
SetRegisterAllowed(0xBE4);
|
||||
SetRegisterAllowed(0xBE8);
|
||||
SetRegisterAllowed(0xBEC);
|
||||
SetRegisterAllowed(0xBF0);
|
||||
SetRegisterAllowed(0xBF4);
|
||||
SetRegisterAllowed(0xBF8);
|
||||
SetRegisterAllowed(0xBFC);
|
||||
SetRegisterAllowed(0xC00);
|
||||
SetRegisterAllowed(0xC04);
|
||||
SetRegisterAllowed(0xC08);
|
||||
SetRegisterAllowed(0xC0C);
|
||||
SetRegisterAllowed(0xC10);
|
||||
SetRegisterAllowed(0xC14);
|
||||
SetRegisterAllowed(0xC18);
|
||||
SetRegisterAllowed(0xC1C);
|
||||
SetRegisterAllowed(0xC20);
|
||||
SetRegisterAllowed(0xC24);
|
||||
SetRegisterAllowed(0xC28);
|
||||
SetRegisterAllowed(0xC2C);
|
||||
SetRegisterAllowed(0xC30);
|
||||
SetRegisterAllowed(0xC34);
|
||||
SetRegisterAllowed(0xC38);
|
||||
SetRegisterAllowed(0xC3C);
|
||||
SetRegisterAllowed(0xC40);
|
||||
SetRegisterAllowed(0xC44);
|
||||
SetRegisterAllowed(0xC48);
|
||||
SetRegisterAllowed(0xC4C);
|
||||
SetRegisterAllowed(0xC50);
|
||||
SetRegisterAllowed(0xC54);
|
||||
SetRegisterAllowed(0xC58);
|
||||
SetRegisterAllowed(0xC5C);
|
||||
SetRegisterAllowed(0xC60);
|
||||
SetRegisterAllowed(0xC64);
|
||||
SetRegisterAllowed(0xC68);
|
||||
SetRegisterAllowed(0xC6C);
|
||||
SetRegisterAllowed(0xC70);
|
||||
SetRegisterAllowed(0xC74);
|
||||
SetRegisterAllowed(0xC78);
|
||||
SetRegisterAllowed(0xC7C);
|
||||
SetRegisterAllowed(0xC80);
|
||||
SetRegisterAllowed(0xC84);
|
||||
SetRegisterAllowed(0xC88);
|
||||
SetRegisterAllowed(0xC8C);
|
||||
SetRegisterAllowed(0xC90);
|
||||
SetRegisterAllowed(0xC94);
|
||||
SetRegisterAllowed(0xC98);
|
||||
SetRegisterAllowed(0xC9C);
|
||||
SetRegisterAllowed(0xCA0);
|
||||
SetRegisterAllowed(0xCA4);
|
||||
SetRegisterAllowed(0xCA8);
|
||||
SetRegisterAllowed(0xCAC);
|
||||
SetRegisterAllowed(0xCB0);
|
||||
SetRegisterAllowed(0xCB4);
|
||||
SetRegisterAllowed(0xCB8);
|
||||
SetRegisterAllowed(0xCBC);
|
||||
SetRegisterAllowed(0xCC0);
|
||||
SetRegisterAllowed(0xCC4);
|
||||
SetRegisterAllowed(0xCC8);
|
||||
SetRegisterAllowed(0xCCC);
|
||||
SetRegisterAllowed(0xCD0);
|
||||
SetRegisterAllowed(0xCD4);
|
||||
SetRegisterAllowed(0xCD8);
|
||||
SetRegisterAllowed(0xCDC);
|
||||
SetRegisterAllowed(0xCE0);
|
||||
SetRegisterAllowed(0xCE4);
|
||||
SetRegisterAllowed(0xCE8);
|
||||
SetRegisterAllowed(0xCEC);
|
||||
SetRegisterAllowed(0xCF0);
|
||||
SetRegisterAllowed(0xCF4);
|
||||
SetRegisterAllowed(0xCF8);
|
||||
SetRegisterAllowed(0xCFC);
|
||||
SetRegisterAllowed(0xD00);
|
||||
SetRegisterAllowed(0xD04);
|
||||
SetRegisterAllowed(0xD08);
|
||||
SetRegisterAllowed(0xD0C);
|
||||
SetRegisterAllowed(0xD10);
|
||||
SetRegisterAllowed(0xD14);
|
||||
SetRegisterAllowed(0xD18);
|
||||
SetRegisterAllowed(0xD1C);
|
||||
SetRegisterAllowed(0xD20);
|
||||
SetRegisterAllowed(0xD24);
|
||||
SetRegisterAllowed(0xD28);
|
||||
SetRegisterAllowed(0xD2C);
|
||||
SetRegisterAllowed(0xD30);
|
||||
SetRegisterAllowed(0xD34);
|
||||
SetRegisterAllowed(0xD38);
|
||||
SetRegisterAllowed(0xD3C);
|
||||
SetRegisterAllowed(0xD40);
|
||||
SetRegisterAllowed(0xD44);
|
||||
SetRegisterAllowed(0xD48);
|
||||
SetRegisterAllowed(0xD4C);
|
||||
SetRegisterAllowed(0xD50);
|
||||
SetRegisterAllowed(0xD54);
|
||||
SetRegisterAllowed(0xD58);
|
||||
SetRegisterAllowed(0xD5C);
|
||||
SetRegisterAllowed(0xD60);
|
||||
SetRegisterAllowed(0xD64);
|
||||
SetRegisterAllowed(0xD68);
|
||||
SetRegisterAllowed(0xD6C);
|
||||
SetRegisterAllowed(0xD70);
|
||||
SetRegisterAllowed(0xD74);
|
||||
SetRegisterAllowed(0xD78);
|
||||
SetRegisterAllowed(0xD7C);
|
||||
SetRegisterAllowed(0xD80);
|
||||
SetRegisterAllowed(0xD84);
|
||||
SetRegisterAllowed(0xD88);
|
||||
SetRegisterAllowed(0xD8C);
|
||||
SetRegisterAllowed(0xD90);
|
||||
SetRegisterAllowed(0xD94);
|
||||
SetRegisterAllowed(0xD98);
|
||||
SetRegisterAllowed(0xD9C);
|
||||
SetRegisterAllowed(0xDA0);
|
||||
SetRegisterAllowed(0xDA4);
|
||||
SetRegisterAllowed(0xDA8);
|
||||
SetRegisterAllowed(0xDAC);
|
||||
SetRegisterAllowed(0xDB0);
|
||||
SetRegisterAllowed(0xDB4);
|
||||
SetRegisterAllowed(0xDB8);
|
||||
SetRegisterAllowed(0xDBC);
|
||||
SetRegisterAllowed(0xDC0);
|
||||
SetRegisterAllowed(0xDC4);
|
||||
SetRegisterAllowed(0xDC8);
|
||||
SetRegisterAllowed(0xDCC);
|
||||
SetRegisterAllowed(0xDD0);
|
||||
SetRegisterAllowed(0xDD4);
|
||||
SetRegisterAllowed(0xDD8);
|
||||
SetRegisterAllowed(0xDDC);
|
||||
SetRegisterAllowed(0xDE0);
|
||||
SetRegisterAllowed(0xDE4);
|
||||
SetRegisterAllowed(0xDE8);
|
||||
SetRegisterAllowed(0xDEC);
|
||||
SetRegisterAllowed(0xDF0);
|
||||
SetRegisterAllowed(0xDF4);
|
||||
SetRegisterAllowed(0xDF8);
|
||||
SetRegisterAllowed(0xDFC);
|
||||
SetRegisterAllowed(0xE00);
|
||||
SetRegisterAllowed(0xE04);
|
||||
SetRegisterAllowed(0xE08);
|
||||
SetRegisterAllowed(0xE0C);
|
||||
SetRegisterAllowed(0xE10);
|
||||
SetRegisterAllowed(0xE14);
|
||||
SetRegisterAllowed(0xE18);
|
||||
SetRegisterAllowed(0xE1C);
|
||||
SetRegisterAllowed(0xE20);
|
||||
SetRegisterAllowed(0xE24);
|
||||
SetRegisterAllowed(0xE28);
|
||||
SetRegisterAllowed(0xE2C);
|
||||
SetRegisterAllowed(0xE30);
|
||||
SetRegisterAllowed(0xE34);
|
||||
SetRegisterAllowed(0xE38);
|
||||
SetRegisterAllowed(0xE3C);
|
||||
SetRegisterAllowed(0xE40);
|
||||
SetRegisterAllowed(0xE44);
|
||||
SetRegisterAllowed(0xE48);
|
||||
SetRegisterAllowed(0xE4C);
|
||||
SetRegisterAllowed(0xE50);
|
||||
SetRegisterAllowed(0xE54);
|
||||
SetRegisterAllowed(0xE58);
|
||||
SetRegisterAllowed(0xE5C);
|
||||
SetRegisterAllowed(0xE60);
|
||||
SetRegisterAllowed(0xE64);
|
||||
SetRegisterAllowed(0xE68);
|
||||
SetRegisterAllowed(0xE6C);
|
||||
SetRegisterAllowed(0xE70);
|
||||
SetRegisterAllowed(0xE74);
|
||||
SetRegisterAllowed(0xE78);
|
||||
SetRegisterAllowed(0xE7C);
|
||||
SetRegisterAllowed(0xE80);
|
||||
SetRegisterAllowed(0xE84);
|
||||
SetRegisterAllowed(0xE88);
|
||||
SetRegisterAllowed(0xE8C);
|
||||
SetRegisterAllowed(0xE90);
|
||||
SetRegisterAllowed(0xE94);
|
||||
SetRegisterAllowed(0xE98);
|
||||
SetRegisterAllowed(0xE9C);
|
||||
SetRegisterAllowed(0xEA0);
|
||||
SetRegisterAllowed(0xEA4);
|
||||
SetRegisterAllowed(0xEA8);
|
||||
SetRegisterAllowed(0xEAC);
|
||||
SetRegisterAllowed(0xEB0);
|
||||
SetRegisterAllowed(0xEB4);
|
||||
SetRegisterAllowed(0xEB8);
|
||||
SetRegisterAllowed(0xEBC);
|
||||
SetRegisterAllowed(0xEC0);
|
||||
SetRegisterAllowed(0xEC4);
|
||||
SetRegisterAllowed(0xEC8);
|
||||
SetRegisterAllowed(0xECC);
|
||||
SetRegisterAllowed(0xED0);
|
||||
SetRegisterAllowed(0xED4);
|
||||
SetRegisterAllowed(0xED8);
|
||||
348
Source/Atmosphere-Patches/secmon_memory_layout.hpp
Normal file
348
Source/Atmosphere-Patches/secmon_memory_layout.hpp
Normal file
@@ -0,0 +1,348 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours.hpp>
|
||||
#include <exosphere/mmu.hpp>
|
||||
|
||||
namespace ams::secmon {
|
||||
|
||||
using Address = u64;
|
||||
|
||||
struct MemoryRegion {
|
||||
private:
|
||||
Address m_start_address;
|
||||
Address m_end_address;
|
||||
public:
|
||||
consteval MemoryRegion(Address address, size_t size) : m_start_address(address), m_end_address(address + size) {
|
||||
if (m_end_address < m_start_address) {
|
||||
__builtin_unreachable();
|
||||
}
|
||||
}
|
||||
|
||||
constexpr Address GetStartAddress() const {
|
||||
return m_start_address;
|
||||
}
|
||||
|
||||
constexpr Address GetAddress() const {
|
||||
return this->GetStartAddress();
|
||||
}
|
||||
|
||||
constexpr Address GetEndAddress() const {
|
||||
return m_end_address;
|
||||
}
|
||||
|
||||
constexpr Address GetLastAddress() const {
|
||||
return m_end_address - 1;
|
||||
}
|
||||
|
||||
constexpr size_t GetSize() const {
|
||||
return m_end_address - m_start_address;
|
||||
}
|
||||
|
||||
constexpr bool Contains(Address address, size_t size) const {
|
||||
return m_start_address <= address && (address + size - 1) <= this->GetLastAddress();
|
||||
}
|
||||
|
||||
constexpr bool Contains(const MemoryRegion &rhs) const {
|
||||
return this->Contains(rhs.GetStartAddress(), rhs.GetSize());
|
||||
}
|
||||
|
||||
template<typename T = void> requires (std::is_same<T, void>::value || util::is_pod<T>::value)
|
||||
ALWAYS_INLINE T *GetPointer() const {
|
||||
return reinterpret_cast<T *>(this->GetAddress());
|
||||
}
|
||||
|
||||
template<typename T = void> requires (std::is_same<T, void>::value || util::is_pod<T>::value)
|
||||
ALWAYS_INLINE T *GetEndPointer() const {
|
||||
return reinterpret_cast<T *>(this->GetEndAddress());
|
||||
}
|
||||
};
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtual = MemoryRegion(UINT64_C(0x1F0000000), 2_MB);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysical = MemoryRegion(UINT64_C( 0x40000000), 1_GB);
|
||||
constexpr inline const MemoryRegion MemoryRegionDram = MemoryRegion(UINT64_C( 0x80000000), 2_GB);
|
||||
constexpr inline const MemoryRegion MemoryRegionDramHigh = MemoryRegion(MemoryRegionDram.GetEndAddress(), 2_GB);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionDramForMarikoProgram = MemoryRegion(UINT64_C(0xC0000000), 1_GB);
|
||||
constexpr inline const MemoryRegion MemoryRegionDramDcFramebuffer = MemoryRegion(UINT64_C(0xC0000000), 4_MB);
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionDramForMarikoProgram));
|
||||
static_assert(MemoryRegionDramForMarikoProgram.Contains(MemoryRegionDramDcFramebuffer));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionDramGpuCarveout = MemoryRegion(UINT64_C(0x80020000), UINT64_C(0x40000));
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionDramGpuCarveout));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionDramDefaultKernelCarveout = MemoryRegion(UINT64_C(0x80060000), UINT64_C(0x1FFE0000));
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionDramDefaultKernelCarveout));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionDramPackage2Payloads = MemoryRegion(MemoryRegionDram.GetAddress(), 8_MB);
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionDramPackage2Payloads));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionDramPackage2 = MemoryRegion(UINT64_C(0xA9800000), UINT64_C(0x07FC0000));
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionDramPackage2));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIram = MemoryRegion(UINT64_C(0x40000000), 0x40000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzram = MemoryRegion(UINT64_C(0x7C010000), 0x10000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramMariko = MemoryRegion(UINT64_C(0x7C010000), 0x40000);
|
||||
static_assert(MemoryRegionPhysical.Contains(MemoryRegionPhysicalIram));
|
||||
static_assert(MemoryRegionPhysical.Contains(MemoryRegionPhysicalTzram));
|
||||
static_assert(MemoryRegionPhysicalTzramMariko.Contains(MemoryRegionPhysicalTzram));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramVolatile(UINT64_C(0x7C010000), 0x2000);
|
||||
static_assert(MemoryRegionPhysicalTzram.Contains(MemoryRegionPhysicalTzramVolatile));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramNonVolatile(UINT64_C(0x7C012000), 0xE000);
|
||||
static_assert(MemoryRegionPhysicalTzram.Contains(MemoryRegionPhysicalTzramNonVolatile));
|
||||
|
||||
static_assert(MemoryRegionPhysicalTzram.GetSize() == MemoryRegionPhysicalTzramNonVolatile.GetSize() + MemoryRegionPhysicalTzramVolatile.GetSize());
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualL1 = MemoryRegion(util::AlignDown(MemoryRegionVirtual.GetAddress(), mmu::L1EntrySize), mmu::L1EntrySize);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalL1 = MemoryRegion(util::AlignDown(MemoryRegionPhysical.GetAddress(), mmu::L1EntrySize), mmu::L1EntrySize);
|
||||
static_assert(MemoryRegionVirtualL1.Contains(MemoryRegionVirtual));
|
||||
static_assert(MemoryRegionPhysicalL1.Contains(MemoryRegionPhysical));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualL2 = MemoryRegion(util::AlignDown(MemoryRegionVirtual.GetAddress(), mmu::L2EntrySize), mmu::L2EntrySize);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramL2 = MemoryRegion(util::AlignDown(MemoryRegionPhysicalIram.GetAddress(), mmu::L2EntrySize), mmu::L2EntrySize);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramL2 = MemoryRegion(util::AlignDown(MemoryRegionPhysicalTzram.GetAddress(), mmu::L2EntrySize), mmu::L2EntrySize);
|
||||
static_assert(MemoryRegionVirtualL2.Contains(MemoryRegionVirtual));
|
||||
static_assert(MemoryRegionPhysicalIramL2.Contains(MemoryRegionPhysicalIram));
|
||||
static_assert(MemoryRegionPhysicalTzramL2.Contains(MemoryRegionPhysicalTzram));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramBootCode = MemoryRegion(UINT64_C(0x40020000), 0x20000);
|
||||
static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramBootCode));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDevice = MemoryRegion(UINT64_C(0x1F0040000), UINT64_C(0x40000));
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualDevice));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDeviceEmpty = MemoryRegion(MemoryRegionVirtualDevice.GetStartAddress(), 0);
|
||||
|
||||
#define AMS_SECMON_FOREACH_DEVICE_REGION(HANDLER, ...) \
|
||||
HANDLER(GicDistributor, Empty, UINT64_C(0x50041000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(GicCpuInterface, GicDistributor, UINT64_C(0x50042000), UINT64_C(0x2000), true, ## __VA_ARGS__) \
|
||||
HANDLER(Uart, GicCpuInterface, UINT64_C(0x70006000), UINT64_C(0x1000), false, ## __VA_ARGS__) \
|
||||
HANDLER(ClkRst, Uart, UINT64_C(0x60006000), UINT64_C(0x1000), false, ## __VA_ARGS__) \
|
||||
HANDLER(RtcPmc, ClkRst, UINT64_C(0x7000E000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(Timer, RtcPmc, UINT64_C(0x60005000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(System, Timer, UINT64_C(0x6000C000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(SecurityEngine, System, UINT64_C(0x70012000), UINT64_C(0x2000), true, ## __VA_ARGS__) \
|
||||
HANDLER(SecurityEngine2, SecurityEngine, UINT64_C(0x70412000), UINT64_C(0x2000), true, ## __VA_ARGS__) \
|
||||
HANDLER(SysCtr0, SecurityEngine2, UINT64_C(0x700F0000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(MemoryController, SysCtr0, UINT64_C(0x70019000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(ExternalMemoryController, MemoryController, UINT64_C(0x7001b000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(FuseKFuse, ExternalMemoryController, UINT64_C(0x7000F000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(ApbMisc, FuseKFuse, UINT64_C(0x70000000), UINT64_C(0x4000), true, ## __VA_ARGS__) \
|
||||
HANDLER(FlowController, ApbMisc, UINT64_C(0x60007000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(BootloaderParams, FlowController, UINT64_C(0x40000000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(I2c5, BootloaderParams, UINT64_C(0x7000D000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(Gpio, I2c5, UINT64_C(0x6000D000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(I2c1, Gpio, UINT64_C(0x7000C000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(ExceptionVectors, I2c1, UINT64_C(0x6000F000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(MemoryController0, ExceptionVectors, UINT64_C(0x7001C000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(MemoryController1, MemoryController0, UINT64_C(0x7001D000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(Sdmmc, MemoryController1, UINT64_C(0x700B0000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(Disp1, Sdmmc, UINT64_C(0x54200000), UINT64_C(0x3000), true, ## __VA_ARGS__) \
|
||||
HANDLER(Dsi, Disp1, UINT64_C(0x54300000), UINT64_C(0x1000), true, ## __VA_ARGS__) \
|
||||
HANDLER(MipiCal, Dsi, UINT64_C(0x700E3000), UINT64_C(0x1000), true, ## __VA_ARGS__)
|
||||
|
||||
#define DEFINE_DEVICE_REGION(_NAME_, _PREV_, _ADDRESS_, _SIZE_, _SECURE_) \
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDevice##_NAME_ = MemoryRegion(MemoryRegionVirtualDevice##_PREV_.GetEndAddress() + 0x1000, _SIZE_); \
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDevice##_NAME_ = MemoryRegion(_ADDRESS_, _SIZE_); \
|
||||
static_assert(MemoryRegionVirtualDevice.Contains(MemoryRegionVirtualDevice##_NAME_)); \
|
||||
static_assert(MemoryRegionPhysical.Contains(MemoryRegionPhysicalDevice##_NAME_));
|
||||
|
||||
AMS_SECMON_FOREACH_DEVICE_REGION(DEFINE_DEVICE_REGION)
|
||||
|
||||
#undef DEFINE_DEVICE_REGION
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDeviceFuses = MemoryRegion(MemoryRegionVirtualDeviceFuseKFuse.GetAddress() + 0x800, 0x400);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceFuses = MemoryRegion(MemoryRegionPhysicalDeviceFuseKFuse.GetAddress() + 0x800, 0x400);
|
||||
static_assert(MemoryRegionVirtualDeviceFuseKFuse.Contains(MemoryRegionVirtualDeviceFuses));
|
||||
static_assert(MemoryRegionPhysicalDeviceFuseKFuse.Contains(MemoryRegionPhysicalDeviceFuses));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDeviceActivityMonitor = MemoryRegion(MemoryRegionVirtualDeviceSystem.GetAddress() + 0x800, 0x400);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceActivityMonitor = MemoryRegion(MemoryRegionPhysicalDeviceSystem.GetAddress() + 0x800, 0x400);
|
||||
static_assert(MemoryRegionVirtualDeviceSystem.Contains(MemoryRegionVirtualDeviceActivityMonitor));
|
||||
static_assert(MemoryRegionPhysicalDeviceSystem.Contains(MemoryRegionPhysicalDeviceActivityMonitor));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDeviceUartA = MemoryRegion(MemoryRegionVirtualDeviceUart.GetAddress() + 0x000, 0x040);
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDeviceUartB = MemoryRegion(MemoryRegionVirtualDeviceUart.GetAddress() + 0x040, 0x040);
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDeviceUartC = MemoryRegion(MemoryRegionVirtualDeviceUart.GetAddress() + 0x200, 0x100);
|
||||
static_assert(MemoryRegionVirtualDeviceUart.Contains(MemoryRegionVirtualDeviceUartA));
|
||||
static_assert(MemoryRegionVirtualDeviceUart.Contains(MemoryRegionVirtualDeviceUartB));
|
||||
static_assert(MemoryRegionVirtualDeviceUart.Contains(MemoryRegionVirtualDeviceUartC));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceUartA = MemoryRegion(MemoryRegionPhysicalDeviceUart.GetAddress() + 0x000, 0x040);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceUartB = MemoryRegion(MemoryRegionPhysicalDeviceUart.GetAddress() + 0x040, 0x040);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDeviceUartC = MemoryRegion(MemoryRegionPhysicalDeviceUart.GetAddress() + 0x200, 0x100);
|
||||
static_assert(MemoryRegionPhysicalDeviceUart.Contains(MemoryRegionPhysicalDeviceUartA));
|
||||
static_assert(MemoryRegionPhysicalDeviceUart.Contains(MemoryRegionPhysicalDeviceUartB));
|
||||
static_assert(MemoryRegionPhysicalDeviceUart.Contains(MemoryRegionPhysicalDeviceUartC));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDevicePmc = MemoryRegion(MemoryRegionVirtualDeviceRtcPmc.GetAddress() + 0x400, 0xC00);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDevicePmc = MemoryRegion(MemoryRegionPhysicalDeviceRtcPmc.GetAddress() + 0x400, 0xC00);
|
||||
static_assert(MemoryRegionVirtualDeviceRtcPmc.Contains(MemoryRegionVirtualDevicePmc));
|
||||
static_assert(MemoryRegionPhysicalDeviceRtcPmc.Contains(MemoryRegionPhysicalDevicePmc));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramReadOnlyAlias = MemoryRegion(UINT64_C(0x1F00A0000), MemoryRegionPhysicalTzram.GetSize());
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramReadOnlyAlias = MemoryRegion(MemoryRegionPhysicalTzram.GetAddress(), MemoryRegionPhysicalTzram.GetSize());
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramReadOnlyAlias));
|
||||
static_assert(MemoryRegionPhysicalTzram.Contains(MemoryRegionPhysicalTzramReadOnlyAlias));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramProgram(UINT64_C(0x1F00C0000), 0xC000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramProgram));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramProgramExceptionVectors(UINT64_C(0x1F00C0000), 0x800);
|
||||
static_assert(MemoryRegionVirtualTzramProgram.Contains(MemoryRegionVirtualTzramProgramExceptionVectors));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramMarikoProgram(UINT64_C(0x1F00D0000), 0x20000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramMarikoProgram(UINT64_C(0x7C020000), 0x20000);
|
||||
static_assert(MemoryRegionPhysicalTzramMariko.Contains(MemoryRegionPhysicalTzramMarikoProgram));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramMarikoProgramFatalErrorContext(UINT64_C(0x1F00EF000), 0x1000);
|
||||
static_assert(MemoryRegionVirtualTzramMarikoProgram.Contains(MemoryRegionVirtualTzramMarikoProgramFatalErrorContext));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramFatalErrorContext(UINT64_C(0x4003E000), 0x1000);
|
||||
static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramFatalErrorContext));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramMarikoProgramStack(UINT64_C(0x1F00F4000), 0x8000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramMarikoProgramStack(UINT64_C(0x7C040000), 0x8000);
|
||||
static_assert(MemoryRegionPhysicalTzramMariko.Contains(MemoryRegionPhysicalTzramMarikoProgramStack));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalMarikoProgramImage(UINT64_C(0x80020000), 0x20000);
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionPhysicalMarikoProgramImage));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramProgramMain(UINT64_C(0x1F00C0800), 0xB800);
|
||||
static_assert(MemoryRegionVirtualTzramProgram.Contains(MemoryRegionVirtualTzramProgramMain));
|
||||
|
||||
static_assert(MemoryRegionVirtualTzramProgram.GetSize() == MemoryRegionVirtualTzramProgramExceptionVectors.GetSize() + MemoryRegionVirtualTzramProgramMain.GetSize());
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramProgram(UINT64_C(0x7C012000), 0xC000);
|
||||
static_assert(MemoryRegionPhysicalTzramNonVolatile.Contains(MemoryRegionPhysicalTzramProgram));
|
||||
|
||||
constexpr inline const Address PhysicalTzramProgramResetVector = MemoryRegionPhysicalTzramProgram.GetAddress() + MemoryRegionVirtualTzramProgramExceptionVectors.GetSize();
|
||||
static_assert(static_cast<u32>(PhysicalTzramProgramResetVector) == PhysicalTzramProgramResetVector);
|
||||
|
||||
constexpr uintptr_t GetPhysicalTzramProgramAddress(uintptr_t virtual_address) {
|
||||
return virtual_address - MemoryRegionVirtualTzramProgram.GetStartAddress() + MemoryRegionPhysicalTzramNonVolatile.GetStartAddress();
|
||||
}
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualIramSc7Work = MemoryRegion(UINT64_C(0x1F0120000), MemoryRegionPhysicalTzram.GetSize());
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramSc7Work = MemoryRegion( UINT64_C(0x40020000), MemoryRegionPhysicalTzram.GetSize());
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualIramSc7Work));
|
||||
static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramSc7Work));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualIramSc7Firmware = MemoryRegion(UINT64_C(0x1F0140000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramSc7Firmware = MemoryRegion( UINT64_C(0x40003000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualIramSc7Firmware));
|
||||
static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramSc7Firmware));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramSecureMonitorDebug(UINT64_C(0x40034000), 0x4000);
|
||||
static_assert(MemoryRegionPhysicalIram.Contains(MemoryRegionPhysicalIramSecureMonitorDebug));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDebugCode = MemoryRegion(UINT64_C(0x1F0150000), 0x4000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDebugCode = MemoryRegion(UINT64_C(0x40034000), 0x4000);
|
||||
static_assert(MemoryRegionPhysicalIramSecureMonitorDebug.Contains(MemoryRegionPhysicalDebugCode));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDebug = MemoryRegion(UINT64_C(0x1F0160000), 0x10000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualDebug));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramBootCode = MemoryRegion(UINT64_C(0x1F01C0000), 0x2000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramBootCode = MemoryRegion( UINT64_C(0x7C010000), 0x2000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramBootCode));
|
||||
static_assert(MemoryRegionPhysicalTzramVolatile.Contains(MemoryRegionPhysicalTzramBootCode));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramMonitorConfiguration = MemoryRegion( UINT64_C(0x8000F000), 0x1000);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStore = MemoryRegion(UINT64_C(0x1F0100000), 0x10000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStore = MemoryRegion( UINT64_C(0x80010000), 0x10000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualDramSecureDataStore));
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionPhysicalDramSecureDataStore));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramDebugDataStore = MemoryRegion(UINT64_C(0x1F0110000), 0x4000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramDebugDataStore = MemoryRegion( UINT64_C(0x8000C000), 0x4000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualDramSecureDataStore));
|
||||
static_assert(MemoryRegionDram.Contains(MemoryRegionPhysicalDramSecureDataStore));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramSdmmcMappedData = MemoryRegion(UINT64_C(0x1F0100000), 0xC000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramSdmmcMappedData = MemoryRegion(UINT64_C(0x80010000), 0xC000);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramDcL0DevicePageTable = MemoryRegion(UINT64_C(0x1F010C000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramDcL0DevicePageTable = MemoryRegion( UINT64_C(0x8001C000), 0x1000);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramSdmmc1L0DevicePageTable = MemoryRegion(UINT64_C(0x1F010E000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramSdmmc1L0DevicePageTable = MemoryRegion( UINT64_C(0x8001E000), 0x1000);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramSdmmc1L1DevicePageTable = MemoryRegion(UINT64_C(0x1F010F000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramSdmmc1L1DevicePageTable = MemoryRegion( UINT64_C(0x8001F000), 0x1000);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStoreTzram = MemoryRegion(UINT64_C(0x1F0100000), 0xE000);
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStoreWarmbootFirmware = MemoryRegion(UINT64_C(0x1F010E000), 0x17C0);
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualDramSecureDataStoreSecurityEngineState = MemoryRegion(UINT64_C(0x1F010F7C0), 0x0840);
|
||||
static_assert(MemoryRegionVirtualDramSecureDataStore.Contains(MemoryRegionVirtualDramSecureDataStoreTzram));
|
||||
static_assert(MemoryRegionVirtualDramSecureDataStore.Contains(MemoryRegionVirtualDramSecureDataStoreWarmbootFirmware));
|
||||
static_assert(MemoryRegionVirtualDramSecureDataStore.Contains(MemoryRegionVirtualDramSecureDataStoreSecurityEngineState));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStoreTzram = MemoryRegion(UINT64_C(0x80010000), 0xE000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStoreWarmbootFirmware = MemoryRegion(UINT64_C(0x8001E000), 0x17C0);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalDramSecureDataStoreSecurityEngineState = MemoryRegion(UINT64_C(0x8001F7C0), 0x0840);
|
||||
static_assert(MemoryRegionPhysicalDramSecureDataStore.Contains(MemoryRegionPhysicalDramSecureDataStoreTzram));
|
||||
static_assert(MemoryRegionPhysicalDramSecureDataStore.Contains(MemoryRegionPhysicalDramSecureDataStoreWarmbootFirmware));
|
||||
static_assert(MemoryRegionPhysicalDramSecureDataStore.Contains(MemoryRegionPhysicalDramSecureDataStoreSecurityEngineState));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualAtmosphereIramPage = MemoryRegion(UINT64_C(0x1F01F0000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualAtmosphereIramPage));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualAtmosphereUserPage = MemoryRegion(UINT64_C(0x1F01F2000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualAtmosphereUserPage));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualSmcUserPage = MemoryRegion(UINT64_C(0x1F01F4000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualSmcUserPage));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramVolatileData = MemoryRegion(UINT64_C(0x1F01F6000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramVolatileData = MemoryRegion( UINT64_C(0x7C010000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramVolatileData));
|
||||
static_assert(MemoryRegionPhysicalTzramVolatile.Contains(MemoryRegionPhysicalTzramVolatileData));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramVolatileStack = MemoryRegion(UINT64_C(0x1F01F8000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramVolatileStack = MemoryRegion( UINT64_C(0x7C011000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramVolatileStack));
|
||||
static_assert(MemoryRegionPhysicalTzramVolatile.Contains(MemoryRegionPhysicalTzramVolatileStack));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramConfigurationData = MemoryRegion(UINT64_C(0x1F01FA000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramConfigurationData = MemoryRegion( UINT64_C(0x7C01E000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramConfigurationData));
|
||||
static_assert(MemoryRegionPhysicalTzramNonVolatile.Contains(MemoryRegionPhysicalTzramConfigurationData));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramL1PageTable = MemoryRegion(UINT64_C(0x1F01FCFC0), 0x40);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramL1PageTable = MemoryRegion( UINT64_C(0x7C01EFC0), 0x40);
|
||||
static_assert(MemoryRegionPhysicalTzramConfigurationData.Contains(MemoryRegionPhysicalTzramL1PageTable));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionVirtualTzramL2L3PageTable = MemoryRegion(UINT64_C(0x1F01FE000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramL2L3PageTable = MemoryRegion( UINT64_C(0x7C01F000), 0x1000);
|
||||
static_assert(MemoryRegionVirtual.Contains(MemoryRegionVirtualTzramL2L3PageTable));
|
||||
static_assert(MemoryRegionPhysicalTzramNonVolatile.Contains(MemoryRegionPhysicalTzramL2L3PageTable));
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalTzramFullProgramImage = MemoryRegion(UINT64_C(0x7C010800), 0xD800);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramBootCodeImage = MemoryRegion(UINT64_C(0x40032000), 0xC000);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramBootCodeCode = MemoryRegion(UINT64_C(0x40032000), 0x1000);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramBootCodeKeys = MemoryRegion(UINT64_C(0x40033000), 0x1000);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramWarmbootBin = MemoryRegion(UINT64_C(0x4003E000), 0x17F0);
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramBootConfig = MemoryRegion(UINT64_C(0x4003F800), 0x400);
|
||||
|
||||
constexpr inline const MemoryRegion MemoryRegionPhysicalIramRebootStub = MemoryRegion(UINT64_C(0x4003F000), 0x1000);
|
||||
|
||||
}
|
||||
196
Source/Atmosphere-Patches/secmon_smc_register_access.cpp
Normal file
196
Source/Atmosphere-Patches/secmon_smc_register_access.cpp
Normal file
@@ -0,0 +1,196 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <exosphere.hpp>
|
||||
#include "../secmon_error.hpp"
|
||||
#include "secmon_smc_register_access.hpp"
|
||||
|
||||
namespace ams::secmon::smc {
|
||||
|
||||
namespace {
|
||||
|
||||
template<size_t N>
|
||||
constexpr void SetRegisterTableAllowed(std::array<u8, N> &arr, uintptr_t reg) {
|
||||
/* All registers should be four byte aligned. */
|
||||
AMS_ASSUME(reg % sizeof(u32) == 0);
|
||||
|
||||
/* Reduce the register to an index. */
|
||||
reg /= sizeof(u32);
|
||||
|
||||
/* Get the index and mask. */
|
||||
const auto index = reg / BITSIZEOF(u8);
|
||||
const auto mask = (1u << (reg % BITSIZEOF(u8)));
|
||||
|
||||
/* Check that the permission bit isn't already set. */
|
||||
AMS_ASSUME((arr[index] & mask) == 0);
|
||||
|
||||
/* Set the permission bit. */
|
||||
arr[index] |= mask;
|
||||
|
||||
/* Ensure that indices are set in sorted order. */
|
||||
for (auto i = (reg % BITSIZEOF(u8)) + 1; i < 8; ++i) {
|
||||
AMS_ASSUME((arr[index] & (1u << i)) == 0);
|
||||
}
|
||||
|
||||
for (auto i = index + 1; i < arr.size(); ++i) {
|
||||
AMS_ASSUME(arr[i] == 0);
|
||||
}
|
||||
}
|
||||
|
||||
template<size_t N>
|
||||
consteval std::pair<size_t, size_t> GetReducedAccessTableInfo(const std::array<u8, N> &arr) {
|
||||
for (int last = arr.size() - 1; last >= 0; --last) {
|
||||
if (arr[last] != 0) {
|
||||
const int end = last + 1;
|
||||
for (int start = 0; start < end; ++start) {
|
||||
if (arr[start] != 0) {
|
||||
return std::make_pair(static_cast<size_t>(start), static_cast<size_t>(end));
|
||||
}
|
||||
}
|
||||
return std::make_pair(static_cast<size_t>(0), static_cast<size_t>(end));
|
||||
}
|
||||
}
|
||||
|
||||
/* All empty perm table is disallowed. */
|
||||
AMS_ASSUME(false);
|
||||
}
|
||||
|
||||
|
||||
template<u32 _Address, auto RawTable>
|
||||
struct AccessTable {
|
||||
static constexpr inline auto ReducedAccessTableInfo = GetReducedAccessTableInfo(RawTable);
|
||||
static constexpr inline size_t ReducedAccessTableSize = ReducedAccessTableInfo.second - ReducedAccessTableInfo.first;
|
||||
static constexpr inline auto ReducedAccessTable = []() -> std::array<u8, ReducedAccessTableSize> {
|
||||
std::array<u8, ReducedAccessTableSize> reduced = {};
|
||||
|
||||
for (size_t i = ReducedAccessTableInfo.first; i < ReducedAccessTableInfo.second; ++i) {
|
||||
reduced[i - ReducedAccessTableInfo.first] = RawTable[i];
|
||||
}
|
||||
|
||||
return reduced;
|
||||
}();
|
||||
|
||||
static constexpr u32 Address = _Address + (ReducedAccessTableInfo.first * sizeof(u32) * BITSIZEOF(u8));
|
||||
static constexpr u32 Size = static_cast<u32>(ReducedAccessTableSize * sizeof(u32) * BITSIZEOF(u8));
|
||||
|
||||
static_assert(Size <= 0x1000);
|
||||
};
|
||||
|
||||
struct AccessTableEntry {
|
||||
const u8 * const table;
|
||||
uintptr_t virtual_address;
|
||||
u32 address;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
/* Include the access tables. */
|
||||
#include "secmon_define_pmc_access_table.inc"
|
||||
#include "secmon_define_mc_access_table.inc"
|
||||
#include "secmon_define_emc_access_table.inc"
|
||||
#include "secmon_define_mc01_access_table.inc"
|
||||
|
||||
constexpr const AccessTableEntry AccessTables[] = {
|
||||
{ PmcAccessTable::ReducedAccessTable.data(), MemoryRegionVirtualDevicePmc.GetAddress(), PmcAccessTable::Address, PmcAccessTable::Size, },
|
||||
{ McAccessTable::ReducedAccessTable.data(), MemoryRegionVirtualDeviceMemoryController.GetAddress(), McAccessTable::Address, McAccessTable::Size, },
|
||||
{ EmcAccessTable::ReducedAccessTable.data(), MemoryRegionVirtualDeviceExternalMemoryController.GetAddress(), EmcAccessTable::Address, EmcAccessTable::Size, },
|
||||
{ Mc01AccessTable::ReducedAccessTable.data(), Mc01AccessTable::Address + MemoryRegionVirtualDeviceMemoryController0.GetAddress(), Mc01AccessTable::Address + MemoryRegionPhysicalDeviceMemoryController0.GetAddress(), Mc01AccessTable::Size, },
|
||||
{ Mc01AccessTable::ReducedAccessTable.data(), Mc01AccessTable::Address + MemoryRegionVirtualDeviceMemoryController1.GetAddress(), Mc01AccessTable::Address + MemoryRegionPhysicalDeviceMemoryController1.GetAddress(), Mc01AccessTable::Size, },
|
||||
};
|
||||
|
||||
constexpr bool IsAccessAllowed(const AccessTableEntry &entry, uintptr_t address) {
|
||||
/* Check if the address is within range. */
|
||||
if (!(entry.address <= address && address < entry.address + entry.size)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Get the offset. */
|
||||
const auto offset = address - entry.address;
|
||||
|
||||
/* Convert it to an index. */
|
||||
const auto reg_index = offset / sizeof(u32);
|
||||
|
||||
/* Get the bit fields. */
|
||||
const auto index = reg_index / BITSIZEOF(u8);
|
||||
const auto mask = (1u << (reg_index % BITSIZEOF(u8)));
|
||||
|
||||
/* Validate that we're not going out of bounds. */
|
||||
if (index >= entry.size / sizeof(u32)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return (entry.table[index] & mask) != 0;
|
||||
}
|
||||
|
||||
constexpr const AccessTableEntry *GetAccessTableEntry(uintptr_t address) {
|
||||
for (const auto &entry : AccessTables) {
|
||||
if (IsAccessAllowed(entry, address)) {
|
||||
return std::addressof(entry);
|
||||
}
|
||||
}
|
||||
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
SmcResult SmcReadWriteRegister(SmcArguments &args) {
|
||||
/* Get the arguments. */
|
||||
const uintptr_t address = args.r[1];
|
||||
const u32 mask = args.r[2];
|
||||
const u32 value = args.r[3];
|
||||
|
||||
/* Validate that the address is aligned. */
|
||||
SMC_R_UNLESS(util::IsAligned(address, alignof(u32)), InvalidArgument);
|
||||
|
||||
/* Find the access table. */
|
||||
const AccessTableEntry * const entry = GetAccessTableEntry(address);
|
||||
|
||||
/* Translate our entry into an address to access. */
|
||||
uintptr_t virtual_address = 0;
|
||||
if (entry != nullptr) {
|
||||
/* Get the address to read or write. */
|
||||
virtual_address = entry->virtual_address + (address - entry->address);
|
||||
} else {
|
||||
/* For no clearly discernable reason, SmcReadWriteRegister returns success despite not doing the read/write */
|
||||
/* when accessing the SMMU controls for the BPMP and for APB-DMA. */
|
||||
/* This is "probably" to fuck with hackers who got access to the SMC and are trying to get control of the */
|
||||
/* BPMP to exploit jamais vu, deja vu, or other related DMA/wake-from-sleep vulnerabilities. */
|
||||
constexpr uintptr_t MC = MemoryRegionPhysicalDeviceMemoryController.GetAddress();
|
||||
SMC_R_UNLESS((address == (MC + MC_SMMU_AVPC_ASID) || address == (MC + MC_SMMU_PPCS1_ASID)), InvalidArgument);
|
||||
|
||||
/* For backwards compatibility, we'll allow access to these devices on 1.0.0. */
|
||||
if (GetTargetFirmware() < TargetFirmware_2_0_0) {
|
||||
virtual_address = MemoryRegionVirtualDeviceMemoryController.GetAddress() + (address - MC);
|
||||
}
|
||||
}
|
||||
|
||||
/* Perform the read or write, if we should. */
|
||||
if (virtual_address != 0) {
|
||||
u32 out = 0;
|
||||
|
||||
if (mask != ~static_cast<u32>(0)) {
|
||||
out = reg::Read(virtual_address);
|
||||
}
|
||||
if (mask != static_cast<u32>(0)) {
|
||||
reg::Write(virtual_address, (out & ~mask) | (value & mask));
|
||||
}
|
||||
|
||||
args.r[1] = out;
|
||||
}
|
||||
|
||||
return SmcResult::Success;
|
||||
}
|
||||
|
||||
}
|
||||
@@ -22,6 +22,7 @@
|
||||
|
||||
#define ENABLED 1
|
||||
#define DISABLED 0
|
||||
#define CPU_MAX_MAX_VOLT 1375000
|
||||
|
||||
namespace ams::ldr::oc {
|
||||
|
||||
@@ -36,11 +37,11 @@ volatile CustomizeTable C = {
|
||||
|
||||
.commonCpuBoostClock = 1785000, // Default boost clock
|
||||
|
||||
.commonEmcMemVolt = 1175000, // LPDDR4X JEDEC Specification
|
||||
.commonEmcMemVolt = 1125000, // LPDDR4X JEDEC Specification
|
||||
|
||||
.eristaCpuMaxVolt = 1235,
|
||||
|
||||
.eristaEmcMaxClock = 1600001, // Maximum HB-MGCH ram rating
|
||||
.eristaEmcMaxClock = 1862400, // Maximum HB-MGCH ram rating
|
||||
|
||||
.marikoCpuMaxVolt = 1120,
|
||||
|
||||
@@ -56,19 +57,11 @@ volatile CustomizeTable C = {
|
||||
|
||||
.eristaGpuUV = 3,
|
||||
|
||||
.enableMarikoGpuUnsafeFreqs = ENABLED,
|
||||
|
||||
.enableEristaGpuUnsafeFreqs = ENABLED,
|
||||
|
||||
.enableMarikoCpuUnsafeFreqs = ENABLED,
|
||||
|
||||
.enableEristaCpuUnsafeFreqs = ENABLED,
|
||||
|
||||
.commonGpuVoltOffset = 0,
|
||||
|
||||
.EmcDvbShift = 5,
|
||||
|
||||
// Defaults - (3-3-2) 0-1-4-3-6
|
||||
// Defaults - Zeroed
|
||||
|
||||
// Primary
|
||||
.t1_tRCD = 0,
|
||||
@@ -85,7 +78,7 @@ volatile CustomizeTable C = {
|
||||
|
||||
.marikoCpuVmin = 600,
|
||||
|
||||
.eristaGpuVmin = 775,
|
||||
.eristaGpuVmin = 810,
|
||||
|
||||
.marikoGpuVmin = 610,
|
||||
|
||||
@@ -123,19 +116,32 @@ volatile CustomizeTable C = {
|
||||
|
||||
.eristaGpuVoltArray = {
|
||||
750 /* 76 */,
|
||||
750 /* 115 */,
|
||||
750 /* 153 */,
|
||||
750 /* 192 */,
|
||||
750 /* 230 */,
|
||||
750 /* 307 */,
|
||||
775 /* 384 */,
|
||||
800 /* 460 */,
|
||||
825 /* 537 */,
|
||||
850 /* 614 */,
|
||||
875 /* 691 */,
|
||||
900 /* 768 */,
|
||||
775 /* 269 */,
|
||||
775 /* 307 */,
|
||||
800 /* 346 */,
|
||||
800 /* 384 */,
|
||||
825 /* 422 */,
|
||||
825 /* 460 */,
|
||||
850 /* 499 */,
|
||||
850 /* 537 */,
|
||||
875 /* 576 */,
|
||||
875 /* 614 */,
|
||||
900 /* 652 */,
|
||||
900 /* 691 */,
|
||||
925 /* 729 */,
|
||||
925 /* 768 */,
|
||||
950 /* 806 */,
|
||||
950 /* 844 */,
|
||||
887 /* 921 */,
|
||||
950 /* 998 (Disabled by default) */,
|
||||
995 /* 1075 (Disabled by default) */,
|
||||
975 /* 883 */,
|
||||
975 /* 921 */,
|
||||
0 /* 960 (Disabled by default) */,
|
||||
0 /* 998 (Disabled by default) */,
|
||||
0 /* 1036 (Disabled by default) */,
|
||||
0 /* 1075 (Disabled by default) */,
|
||||
},
|
||||
|
||||
|
||||
@@ -160,6 +166,11 @@ volatile CustomizeTable C = {
|
||||
{ 1581000, { 1130000 }, { 2889664, -122173, 1834 } },
|
||||
{ 1683000, { 1168000 }, { 5100873, -279186, 4747 } },
|
||||
{ 1785000, { 1227500 }, { 5100873, -279186, 4747 } },
|
||||
{ 1887000, { CPU_MAX_MAX_VOLT }, { 5100873, -279186, 4747 } },
|
||||
{ 1963500, { CPU_MAX_MAX_VOLT }, { 5100873, -279186, 4747 } },
|
||||
{ 2091000, { CPU_MAX_MAX_VOLT }, { 5100873, -279186, 4747 } },
|
||||
{ 2193000, { CPU_MAX_MAX_VOLT }, { 5100873, -279186, 4747 } },
|
||||
{ 2295000, { CPU_MAX_MAX_VOLT }, { 5100873, -279186, 4747 } },
|
||||
},
|
||||
|
||||
/* - Mariko CPU DVFS Table:
|
||||
@@ -174,94 +185,141 @@ volatile CustomizeTable C = {
|
||||
{ 714000, { 885768, -20215, 27 }, {} },
|
||||
{ 816000, { 929540, -21725, 27 }, {} },
|
||||
{ 918000, { 976958, -23225, 27 }, {} },
|
||||
{ 1020000, { 1028021, -24725, 27 }, { } },
|
||||
{ 1122000, { 1082730, -26235, 27 }, { } },
|
||||
{ 1224000, { 1141084, -27735, 27 }, { } },
|
||||
{ 1326000, { 1203084, -29245, 27 }, { } },
|
||||
{ 1428000, { 1268729, -30745, 27 }, { } },
|
||||
{ 1581000, { 1374032, -33005, 27 }, { } },
|
||||
{ 1683000, { 1448791, -34505, 27 }, { } },
|
||||
{ 1785000, { 1527196, -36015, 27 }, { } },
|
||||
{ 1887000, { 1609246, -37515, 27 }, { } },
|
||||
{ 1963500, { 1675751, -38635, 27 }, { } },
|
||||
{ 1020000, { 1028021, -24725, 27 }, { 1120000 } },
|
||||
{ 1122000, { 1082730, -26235, 27 }, { 1120000 } },
|
||||
{ 1224000, { 1141084, -27735, 27 }, { 1120000 } },
|
||||
{ 1326000, { 1203084, -29245, 27 }, { 1120000 } },
|
||||
{ 1428000, { 1268729, -30745, 27 }, { 1120000 } },
|
||||
{ 1581000, { 1374032, -33005, 27 }, { 1120000 } },
|
||||
{ 1683000, { 1448791, -34505, 27 }, { 1120000 } },
|
||||
{ 1785000, { 1527196, -36015, 27 }, { 1120000 } },
|
||||
{ 1887000, { 1609246, -37515, 27 }, { 1120000 } },
|
||||
{ 1963500, { 1675751, -38635, 27 }, { 1120000 } },
|
||||
|
||||
{ 2091000, { 1716501, -39395, 27 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2193000, { 1775132, -40505, 27 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2295000, { 1866287, -42005, 27 }, { CPU_MAX_MAX_VOLT } },
|
||||
},
|
||||
|
||||
.marikoCpuDvfsTableSLT = {
|
||||
{ 204000, { 732856, -17335, 113 }, { } },
|
||||
{ 306000, { 760024, -18195, 113 }, { } },
|
||||
{ 408000, { 789258, -19055, 113 }, { } },
|
||||
{ 510000, { 789258, -19915, 113 }, { } },
|
||||
// { 204000, { 732856, -17335, 113 }, { } },
|
||||
// { 306000, { 760024, -18195, 113 }, { } },
|
||||
// { 408000, { 789258, -19055, 113 }, { } },
|
||||
// { 510000, { 789258, -19915, 113 }, { } },
|
||||
{ 612000, { 789258, -19055, 113 }, { } },
|
||||
{ 714000, { 820558, -19915, 113 }, { } },
|
||||
{ 816000, { 853926, -20775, 113 }, { } },
|
||||
{ 918000, { 889361, -21625, 113 }, { } },
|
||||
{ 1020000, { 926862, -22485, 113 }, { } },
|
||||
{ 1122000, { 926862, -22485, 113 }, { } },
|
||||
{ 1224000, { 926862, -22485, 113 }, { } },
|
||||
{ 1326000, { 966431, -23345, 113 }, { } },
|
||||
{ 1428000, { 1008066, -24205, 113 }, { } },
|
||||
{ 1581000, { 1051768, -25065, 113 }, { } },
|
||||
{ 1683000, { 1097537, -25925, 113 }, { } },
|
||||
{ 1785000, { 1145373, -26785, 113 }, { } },
|
||||
{ 1887000, { 1195276, -27645, 113 }, { } },
|
||||
{ 1963500, { 1274006, -29795, 113 }, { } },
|
||||
{ 2091000, { 1349076, -33235, 113 }, { } },
|
||||
{ 2193000, { 1386213, -33235, 113 }, { } },
|
||||
{ 2295000, { 1445416, -34095, 113 }, { } },
|
||||
{ 1020000, { 926862, -22485, 113 }, { 1120000 } },
|
||||
{ 1122000, { 926862, -22485, 113 }, { 1120000 } },
|
||||
{ 1224000, { 926862, -22485, 113 }, { 1120000 } },
|
||||
{ 1326000, { 966431, -23345, 113 }, { 1120000 } },
|
||||
{ 1428000, { 1008066, -24205, 113 }, { 1120000 } },
|
||||
{ 1581000, { 1051768, -25065, 113 }, { 1120000 } },
|
||||
{ 1683000, { 1097537, -25925, 113 }, { 1120000 } },
|
||||
{ 1785000, { 1145373, -26785, 113 }, { 1120000 } },
|
||||
{ 1887000, { 1195276, -27645, 113 }, { 1120000 } },
|
||||
{ 1963500, { 1274006, -29795, 113 }, { 1120000 } },
|
||||
{ 2091000, { 1349076, -33235, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2193000, { 1386213, -33235, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2295000, { 1445416, -34095, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2397000, { 1490873, -34955, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2499000, { 1580725, -35815, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2601000, { 1702903, -36675, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2703000, { 1748360, -37535, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2805000, { 1793817, -38395, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 2907000, { 1839274, -39255, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
{ 3009000, { 1884731, -40115, 113 }, { CPU_MAX_MAX_VOLT } },
|
||||
},
|
||||
|
||||
/* - Erista GPU DVFS Table:
|
||||
*/
|
||||
.eristaGpuDvfsTable = {
|
||||
{ 76800, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 115200, { }, { 856185, 8144, -940, 808, -21583, 226 } },
|
||||
{ 153600, { }, { 856185, 8144, -940, 808, -21583, 226 } },
|
||||
{ 192000, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 230400, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 268800, { }, { 939968, 8144, -940, 808, -21583, 226 } },
|
||||
{ 307200, { }, { 939968, 8144, -940, 808, -21583, 226 } },
|
||||
{ 345600, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 384000, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 422400, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 460800, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 499200, { }, { 1065642, 8144, -940, 808, -21583, 226 } },
|
||||
{ 537600, { }, { 1065642, 8144, -940, 808, -21583, 226 } },
|
||||
{ 576000, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 614400, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 652800, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
|
||||
{ 691200, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
|
||||
{ 729600, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 768000, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 806400, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
|
||||
{ 844800, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
|
||||
{ 883200, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
{ 921600, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
{ 998400, { }, { 1316991, 8144, -940, 808, -21583, 226 } },
|
||||
// { 998400, { }, { 1316991, 8144, -940, 808, -21583, 226 } },
|
||||
// { 1075200, { }, { 1358882, 8144, -940, 808, -21583, 226 } },
|
||||
|
||||
},
|
||||
|
||||
.eristaGpuDvfsTableSLT = {
|
||||
{ 76800, { }, { 730512, 8144, -940, 808, -21583, 226 } },
|
||||
{ 153600, { }, { 772403, 8144, -940, 808, -21583, 226 } },
|
||||
{ 230400, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 307200, { }, { 856186, 8144, -940, 808, -21583, 226 } },
|
||||
{ 384000, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 460800, { }, { 939969, 8144, -940, 808, -21583, 226 } },
|
||||
{ 537600, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 614400, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 691200, { }, { 1065643, 8144, -940, 808, -21583, 226 } },
|
||||
{ 768000, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 844800, { }, { 1149426, 8144, -940, 808, -21583, 226 } },
|
||||
{ 921600, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 76800, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 115200, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 153600, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 192000, { }, { 856185, 8144, -940, 808, -21583, 226 } },
|
||||
{ 230400, { }, { 856185, 8144, -940, 808, -21583, 226 } },
|
||||
{ 268800, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 307200, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 345600, { }, { 939968, 8144, -940, 808, -21583, 226 } },
|
||||
{ 384000, { }, { 939968, 8144, -940, 808, -21583, 226 } },
|
||||
{ 422400, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 460800, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 499200, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 537600, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 576000, { }, { 1065642, 8144, -940, 808, -21583, 226 } },
|
||||
{ 614400, { }, { 1065642, 8144, -940, 808, -21583, 226 } },
|
||||
{ 652800, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 691200, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 729600, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
|
||||
{ 768000, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
|
||||
{ 806400, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 844800, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 883200, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
|
||||
{ 921600, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
|
||||
{ 960000, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
{ 998400, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
// { 1075200, { }, { 1316991, 8144, -940, 808, -21583, 226 } },
|
||||
},
|
||||
|
||||
.eristaGpuDvfsTableHigh = {
|
||||
{ 76800, { }, { 646730, 8144, -940, 808, -21583, 226 } },
|
||||
{ 153600, { }, { 688621, 8144, -940, 808, -21583, 226 } },
|
||||
{ 230400, { }, { 730512, 8144, -940, 808, -21583, 226 } },
|
||||
{ 307200, { }, { 772403, 8144, -940, 808, -21583, 226 } },
|
||||
{ 384000, { }, { 814295, 8144, -940, 808, -21583, 226 } },
|
||||
{ 460800, { }, { 856186, 8144, -940, 808, -21583, 226 } },
|
||||
{ 537600, { }, { 898078, 8144, -940, 808, -21583, 226 } },
|
||||
{ 614400, { }, { 939969, 8144, -940, 808, -21583, 226 } },
|
||||
{ 691200, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 768000, { }, { 1023752, 8144, -940, 808, -21583, 226 } },
|
||||
{ 844800, { }, { 1065643, 8144, -940, 808, -21583, 226 } },
|
||||
{ 921600, { }, { 1107535, 8144, -940, 808, -21583, 226 } },
|
||||
// { 998400, { }, { 1149426, 8144, -940, 808, -21583, 226 } },
|
||||
// { 1075200, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
{ 76800, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 115200, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 153600, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 192000, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 230400, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 268800, { }, { 856185, 8144, -940, 808, -21583, 226 } },
|
||||
{ 307200, { }, { 856185, 8144, -940, 808, -21583, 226 } },
|
||||
{ 345600, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 384000, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 422400, { }, { 939968, 8144, -940, 808, -21583, 226 } },
|
||||
{ 460800, { }, { 939968, 8144, -940, 808, -21583, 226 } },
|
||||
{ 499200, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 537600, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 576000, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 614400, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 652800, { }, { 1065642, 8144, -940, 808, -21583, 226 } },
|
||||
{ 691200, { }, { 1065642, 8144, -940, 808, -21583, 226 } },
|
||||
{ 729600, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 768000, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 806400, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
|
||||
{ 844800, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
|
||||
{ 883200, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 921600, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 960000, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
|
||||
{ 998400, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
|
||||
{ 1036800, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
{ 1075200, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
},
|
||||
|
||||
/* - Mariko GPU DVFS Table:
|
||||
@@ -283,31 +341,32 @@ volatile CustomizeTable C = {
|
||||
{ 998400, {}, { 1098475, -13529, -497, -179, 3626, 9 } },
|
||||
{ 1075200, {}, { 1163644, -12688, -648, 0, 1077, 40 } },
|
||||
{ 1152000, {}, { 1204812, -9908, -830, 0, 1469, 110 } },
|
||||
// { 1228800, {}, { 1277303, -11675, -859, 0, 3722, 313 } },
|
||||
{ 1228800, {}, { 1277303, -11675, -859, 0, 3722, 313 } },
|
||||
// { 1267200, {}, { 1335531, -12567, -867, 0, 3681, 559 } },
|
||||
// Appending table
|
||||
//{ 1305600, {}, { 1374130, -13725, -859, 0, 4442, 576 } },
|
||||
},
|
||||
|
||||
.marikoGpuDvfsTableSLT = {
|
||||
{ 76800, { }, { 610000, 0, 0, 0, 0, 0 }, },
|
||||
{ 153600, { }, { 610000, 0, 0, 0, 0, 0 }, },
|
||||
{ 230400, { }, { 610000, 0, 0, 0, 0, 0 }, },
|
||||
{ 307200, { }, { 610000, 0, 0, 0, 0, 0 }, },
|
||||
{ 384000, { }, { 610000, 0, 0, 0, 0, 0 }, },
|
||||
{ 460800, { }, { 610000, 0, 0, 0, 0, 0 }, },
|
||||
{ 537600, { }, { 801688, -10900, -163, 298, -10599, 162 }, },
|
||||
{ 614400, { }, { 824214, -5743, -452, 238, -6325, 81 }, },
|
||||
{ 691200, { }, { 848830, -3903, -552, 119, -4030, -2 }, },
|
||||
{ 768000, { }, { 891575, -4409, -584, 0, -2849, 39 }, },
|
||||
{ 844800, { }, { 940071, -5367, -602, -60, -63, -93 }, },
|
||||
{ 921600, { }, { 986765, -6637, -614, -179, 1905, -13 }, },
|
||||
{ 998400, { }, { 1098475, -13529, -497, -179, 3626, 9 }, },
|
||||
{ 1075200, { }, { 1163644, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1152000, { }, { 1204812, -9908, -830, 0, 1469, 110 }, },
|
||||
{ 1228800, { }, { 1277303, -11675, -859, 0, 3722, 313 }, },
|
||||
// { 1267200, { }, { 1335531, -12567, -867, 0, 3681, 559 }, },
|
||||
{ 76800, {}, { 600000, } },
|
||||
{ 153600, {}, { 600000, } },
|
||||
{ 230400, {}, { 600000, } },
|
||||
{ 307200, {}, { 600000, } },
|
||||
{ 384000, {}, { 600000, } },
|
||||
{ 460800, {}, { 795089, -11096, -163, 298, -10421, 162 } },
|
||||
{ 537600, {}, { 795089, -11096, -163, 298, -10421, 162 } },
|
||||
{ 614400, {}, { 820606, -6285, -452, 238, -6182, 81 } },
|
||||
{ 691200, {}, { 846289, -4565, -552, 119, -3958, -2 } },
|
||||
{ 768000, {}, { 888720, -5110, -584, 0, -2849, 39 } },
|
||||
{ 844800, {}, { 936634, -6089, -602, -60, -99, -93 } },
|
||||
{ 921600, {}, { 982562, -7373, -614, -179, 1797, -13 } },
|
||||
{ 998400, {}, { 1090179, -14125, -497, -179, 3518, 9 } },
|
||||
{ 1075200, {}, { 1155798, -13465, -648, 0, 1077, 40 } },
|
||||
{ 1152000, {}, { 1198568, -10904, -830, 0, 1469, 110 } },
|
||||
{ 1228800, {}, { 1269988, -12707, -859, 0, 3722, 313 } },
|
||||
{ 1267200, {}, { 1308155, -13694, -867, 0, 3681, 559 } },
|
||||
},
|
||||
|
||||
.marikoGpuDvfsTableHiOPT = {
|
||||
{ 76800, { }, { 590000, 0, 0, 0, 0, 0 }, },
|
||||
{ 153600, { }, { 590000, 0, 0, 0, 0, 0 }, },
|
||||
@@ -326,112 +385,18 @@ volatile CustomizeTable C = {
|
||||
{ 1152000, { }, { 1094475, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1228800, { }, { 1124475, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1267200, { }, { 1145060, -12688, -648, 0, 1077, 40 }, },
|
||||
// { 1305600, { }, { 1163644, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1305600, { }, { 1163644, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1344000, { }, { 1182228, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1382400, { }, { 1200812, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1420800, { }, { 1219396, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1459200, { }, { 1237980, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1497600, { }, { 1256564, -12688, -648, 0, 1077, 40 }, },
|
||||
{ 1536000, { }, { 1275148, -12688, -648, 0, 1077, 40 }, },
|
||||
},
|
||||
|
||||
//.eristaMtcTable = const_cast<EristaMtcTable *>(&EristaMtcTablePlaceholder),
|
||||
//.marikoMtcTable = const_cast<MarikoMtcTable *>(&MarikoMtcTablePlaceholder),
|
||||
|
||||
// UV3 tables
|
||||
|
||||
.eristaGpuDvfsTableUv3UnsafeFreqs = {
|
||||
{ 76800, { }, { 814294, 8144, -940, 808, -21583, 226 } },
|
||||
{ 153600, { }, { 856185, 8144, -940, 808, -21583, 226 } },
|
||||
{ 230400, { }, { 898077, 8144, -940, 808, -21583, 226 } },
|
||||
{ 307200, { }, { 939968, 8144, -940, 808, -21583, 226 } },
|
||||
{ 384000, { }, { 981860, 8144, -940, 808, -21583, 226 } },
|
||||
{ 460800, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
|
||||
{ 537600, { }, { 1065642, 8144, -940, 808, -21583, 226 } },
|
||||
{ 614400, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
|
||||
{ 691200, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
|
||||
{ 768000, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
|
||||
{ 844800, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
|
||||
{ 921600, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
|
||||
{ 998400, { }, { 1316991, 8144, -940, 808, -21583, 226 } }, // UNSAFE
|
||||
{ 1075200, { }, { 1358882, 8144, -940, 808, -21583, 226 } }, // UNSAFE
|
||||
// { 1152000, { }, { 1400773, 8144, -940, 808, -21583, 226 } }, // DANGEROUS
|
||||
// { 1228800, { }, { 1440773, 8144, -940, 808, -21583, 226 } }, // Cooler
|
||||
},
|
||||
|
||||
.marikoGpuDvfsTableUv3UnsafeFreqs = {
|
||||
{ 76800, {}, { 590000, } },
|
||||
{ 153600, {}, { 590000, } },
|
||||
{ 230400, {}, { 590000, } },
|
||||
{ 307200, {}, { 590000, } },
|
||||
{ 384000, {}, { 590000, } },
|
||||
{ 460800, {}, { 590000, } },
|
||||
{ 537600, {}, { 590000, } },
|
||||
{ 614400, {}, { 590000, } },
|
||||
{ 691200, {}, { 838712, -7304, -552, 119, -3750, -2 } },
|
||||
{ 768000, {}, { 880210, -7955, -584, 0, -2849, 39 } },
|
||||
{ 844800, {}, { 926398, -8892, -602, -60, -384, -93 } },
|
||||
{ 921600, {}, { 970060, -10108, -614, -179, 1508, -13 } },
|
||||
{ 998400, {}, { 1065665, -16075, -497, -179, 3213, 9 } },
|
||||
{ 1075200, {}, { 1132576, -16093, -648, 0, 1077, 40 } },
|
||||
{ 1152000, {}, { 1180029, -14534, -830, 0, 1469, 110 } },
|
||||
{ 1228800, {}, { 1248293, -16383, -859, 0, 3722, 313 } },
|
||||
{ 1267200, {}, { 1286399, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1305600, {}, { 1286399, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1305600, {}, { 1324505, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1344000, {}, { 1362611, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1382400, {}, { 1400717, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1420800, {}, { 1438823, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1459200, {}, { 1476929, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1497600, {}, { 1515035, -17475, -867, 0, 3681, 559 } },
|
||||
{ 1536000, {}, { 1553141, -17475, -867, 0, 3681, 559 } },
|
||||
},
|
||||
|
||||
.marikoCpuDvfsTableUnsafeFreqs = {
|
||||
{ 204000, { 732856, -17335, 113 }, {} }, // Unneeded, made to make room for new freqs
|
||||
{ 306000, { 760024, -18195, 113 }, {} },
|
||||
{ 408000, { 789258, -19055, 113 }, { } },
|
||||
{ 510000, { 789258, -19915, 113 }, { } },
|
||||
{ 612000, { 789258, -19055, 113 }, { } },
|
||||
{ 714000, { 820558, -19915, 113 }, { } },
|
||||
{ 816000, { 853926, -20775, 113 }, { } },
|
||||
{ 918000, { 889361, -21625, 113 }, { } },
|
||||
{ 1020000, { 926862, -22485, 113 }, { } },
|
||||
{ 1122000, { 926862, -22485, 113 }, { } },
|
||||
{ 1224000, { 926862, -22485, 113 }, { } },
|
||||
{ 1326000, { 966431, -23345, 113 }, { } },
|
||||
{ 1428000, { 1008066, -24205, 113 }, { } },
|
||||
{ 1581000, { 1051768, -25065, 113 }, { } },
|
||||
{ 1683000, { 1097537, -25925, 113 }, { } },
|
||||
{ 1785000, { 1145373, -26785, 113 }, { } },
|
||||
{ 1887000, { 1195276, -27645, 113 }, { } },
|
||||
{ 1963500, { 1274006, -29795, 113 }, { } },
|
||||
{ 2091000, { 1349076, -33235, 113 }, { } },
|
||||
{ 2193000, { 1386213, -33235, 113 }, { } },
|
||||
{ 2295000, { 1445416, -34095, 113 }, { } },
|
||||
{ 2397000, { 1490873, -34955, 113 }, { } },
|
||||
{ 2499000, { 1580725, -35815, 113 }, { } },
|
||||
{ 2601000, { 1702903, -36675, 113 }, { } },
|
||||
},
|
||||
.eristaCpuDvfsTableUnsafeFreqs = {
|
||||
{ 204000, { 721094 }, {} },
|
||||
{ 306000, { 754040 }, {} },
|
||||
{ 408000, { 786986 }, {} },
|
||||
{ 510000, { 819932 }, {} },
|
||||
{ 612000, { 852878 }, {} },
|
||||
{ 714000, { 885824 }, {} },
|
||||
{ 816000, { 918770 }, {} },
|
||||
{ 918000, { 951716 }, {} },
|
||||
{ 1020000, { 984662 }, { -2875621, 358099, -8585 } },
|
||||
{ 1122000, { 1017608 }, { -52225, 104159, -2816 } },
|
||||
{ 1224000, { 1050554 }, { 1076868, 8356, -727 } },
|
||||
{ 1326000, { 1083500 }, { 2208191, -84659, 1240 } },
|
||||
{ 1428000, { 1116446 }, { 2519460, -105063, 1611 } },
|
||||
{ 1581000, { 1130000 }, { 2889664, -122173, 1834 } },
|
||||
{ 1683000, { 1168000 }, { 5100873, -279186, 4747 } },
|
||||
{ 1785000, { 1227500 }, { 5100873, -279186, 4747 } },
|
||||
// Appending table
|
||||
{ 1887000, { 1235000 }, { 5200873, -279186, 4747 } },
|
||||
{ 1963500, { 1235000 }, { 5300873, -279186, 4747 } },
|
||||
{ 2091000, { 1235000 }, { 5400873, -289186, 4847 } },
|
||||
{ 2193000, { 1235000 }, { 5500873, -299186, 4947 } },
|
||||
{ 2295000, { 1235000 }, { 5600873, -239186, 5047 } },
|
||||
// { 2397000, { 1235000 }, { 5700873, -249186, 5047 } },
|
||||
},
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
@@ -60,11 +60,6 @@
|
||||
u32 eristaCpuUV;
|
||||
u32 eristaGpuUV;
|
||||
|
||||
u32 enableMarikoGpuUnsafeFreqs;
|
||||
u32 enableEristaGpuUnsafeFreqs;
|
||||
|
||||
u32 enableMarikoCpuUnsafeFreqs;
|
||||
u32 enableEristaCpuUnsafeFreqs;
|
||||
|
||||
u32 commonGpuVoltOffset;
|
||||
|
||||
@@ -88,7 +83,7 @@
|
||||
u32 marikoGpuVmax;
|
||||
|
||||
u32 marikoGpuVoltArray[24];
|
||||
u32 eristaGpuVoltArray[14];
|
||||
u32 eristaGpuVoltArray[27];
|
||||
|
||||
CustomizeCpuDvfsTable eristaCpuDvfsTable;
|
||||
CustomizeCpuDvfsTable marikoCpuDvfsTable;
|
||||
@@ -104,11 +99,6 @@
|
||||
CustomizeGpuDvfsTable marikoGpuDvfsTableHiOPT;
|
||||
//EristaMtcTable* eristaMtcTable;
|
||||
//MarikoMtcTable* marikoMtcTable;
|
||||
CustomizeGpuDvfsTable eristaGpuDvfsTableUv3UnsafeFreqs;
|
||||
CustomizeGpuDvfsTable marikoGpuDvfsTableUv3UnsafeFreqs;
|
||||
CustomizeCpuDvfsTable marikoCpuDvfsTableUnsafeFreqs;
|
||||
CustomizeCpuDvfsTable eristaCpuDvfsTableUnsafeFreqs;
|
||||
|
||||
} CustomizeTable;
|
||||
//static_assert(sizeof(CustomizeTable) == sizeof(u8) * 4 + sizeof(u32) * 10 + sizeof(CustomizeCpuDvfsTable) * 5 + sizeof(void*) * 2);
|
||||
//static_assert(sizeof(CustomizeTable) == 7000);
|
||||
|
||||
@@ -94,14 +94,8 @@ void SafetyCheck() {
|
||||
R_SUCCEED();
|
||||
}
|
||||
};
|
||||
u32 eristaCpuDvfsMaxFreq;
|
||||
if (C.enableEristaCpuUnsafeFreqs) {
|
||||
eristaCpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaCpuDvfsTableUnsafeFreqs)->freq);
|
||||
} else {
|
||||
eristaCpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaCpuDvfsTable)->freq);
|
||||
}
|
||||
u32 eristaCpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaCpuDvfsTable)->freq);
|
||||
u32 marikoCpuDvfsMaxFreq;
|
||||
if(!C.enableMarikoCpuUnsafeFreqs) {
|
||||
if (C.marikoCpuUV) {
|
||||
marikoCpuDvfsMaxFreq = static_cast<u32>(
|
||||
GetDvfsTableLastEntry(C.marikoCpuDvfsTableSLT)->freq
|
||||
@@ -111,9 +105,6 @@ void SafetyCheck() {
|
||||
GetDvfsTableLastEntry(C.marikoCpuDvfsTable)->freq
|
||||
);
|
||||
}
|
||||
} else {
|
||||
marikoCpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.marikoCpuDvfsTableUnsafeFreqs)->freq);
|
||||
}
|
||||
u32 eristaGpuDvfsMaxFreq;
|
||||
switch (C.eristaGpuUV)
|
||||
{
|
||||
@@ -124,17 +115,8 @@ void SafetyCheck() {
|
||||
eristaGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaGpuDvfsTableSLT)->freq);
|
||||
break;
|
||||
case 2:
|
||||
eristaGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaGpuDvfsTableHigh)->freq);
|
||||
break;
|
||||
case 3:
|
||||
if(C.enableEristaGpuUnsafeFreqs)
|
||||
{
|
||||
eristaGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaGpuDvfsTableUv3UnsafeFreqs)->freq);
|
||||
}
|
||||
else
|
||||
{
|
||||
eristaGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq);
|
||||
}
|
||||
eristaGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaGpuDvfsTableHigh)->freq);
|
||||
break;
|
||||
default:
|
||||
eristaGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq);
|
||||
@@ -150,17 +132,8 @@ void SafetyCheck() {
|
||||
marikoGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.marikoGpuDvfsTableSLT)->freq);
|
||||
break;
|
||||
case 2:
|
||||
marikoGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.marikoGpuDvfsTableHiOPT)->freq);
|
||||
break;
|
||||
case 3:
|
||||
if(C.enableMarikoGpuUnsafeFreqs)
|
||||
{
|
||||
marikoGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.marikoGpuDvfsTableUv3UnsafeFreqs)->freq);
|
||||
}
|
||||
else
|
||||
{
|
||||
marikoGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.marikoGpuDvfsTable)->freq);
|
||||
}
|
||||
marikoGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.marikoGpuDvfsTableHiOPT)->freq);
|
||||
break;
|
||||
default:
|
||||
marikoGpuDvfsMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(C.marikoGpuDvfsTable)->freq);
|
||||
|
||||
@@ -94,7 +94,9 @@ namespace ams::ldr::oc::pcv
|
||||
{},
|
||||
};
|
||||
|
||||
constexpr u32 GpuClkPllLimit = 1300'000'000;
|
||||
constexpr u32 GpuClkPllLimit = 2600'000;
|
||||
|
||||
constexpr u32 GpuClkMax = 1300'000'000;
|
||||
|
||||
/* GPU Max Clock asm Pattern:
|
||||
*
|
||||
@@ -260,21 +262,13 @@ namespace ams::ldr::oc::pcv
|
||||
cvb_entry_t *customize_table = nullptr; // impossible to reach, there will always be a way to set a pointer
|
||||
|
||||
if (isMariko) {
|
||||
if (C.enableMarikoCpuUnsafeFreqs) {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoCpuDvfsTableUnsafeFreqs);
|
||||
if (C.marikoCpuUV) {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoCpuDvfsTableSLT);
|
||||
} else {
|
||||
if (C.marikoCpuUV) {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoCpuDvfsTableSLT);
|
||||
} else {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoCpuDvfsTable);
|
||||
}
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoCpuDvfsTable);
|
||||
}
|
||||
} else {
|
||||
if (C.enableEristaCpuUnsafeFreqs) {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaCpuDvfsTableUnsafeFreqs);
|
||||
} else {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaCpuDvfsTable);
|
||||
}
|
||||
}
|
||||
u32 cpu_max_volt = isMariko ? C.marikoCpuMaxVolt : C.eristaCpuMaxVolt;
|
||||
u32 cpu_freq_threshold = 1020'000;
|
||||
@@ -328,14 +322,8 @@ namespace ams::ldr::oc::pcv
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTableSLT);
|
||||
break;
|
||||
case 2:
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTableHiOPT);
|
||||
break;
|
||||
case 3:
|
||||
if(C.enableMarikoGpuUnsafeFreqs) {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTableUv3UnsafeFreqs);
|
||||
} else {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTable);
|
||||
}
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTableHiOPT);
|
||||
break;
|
||||
default:
|
||||
customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTable);
|
||||
@@ -350,14 +338,8 @@ namespace ams::ldr::oc::pcv
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTableSLT);
|
||||
break;
|
||||
case 2:
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTableHigh);
|
||||
break;
|
||||
case 3:
|
||||
if(C.enableEristaGpuUnsafeFreqs) {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTableUv3UnsafeFreqs);
|
||||
} else {
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTable);
|
||||
}
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTableHigh);
|
||||
break;
|
||||
default:
|
||||
customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTable);
|
||||
|
||||
@@ -26,21 +26,13 @@ namespace ams::ldr::oc::pcv::erista {
|
||||
Result CpuFreqVdd(u32* ptr) {
|
||||
dvfs_rail* entry = reinterpret_cast<dvfs_rail *>(reinterpret_cast<u8 *>(ptr) - offsetof(dvfs_rail, freq));
|
||||
|
||||
R_UNLESS(entry->id == 1, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->min_mv == 250'000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->step_mv == 5000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->max_mv == 1525'000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
|
||||
if (C.eristaCpuUV) {
|
||||
if(!C.enableEristaCpuUnsafeFreqs) {
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.eristaCpuDvfsTable)->freq);
|
||||
} else {
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.eristaCpuDvfsTableUnsafeFreqs)->freq);
|
||||
}
|
||||
} else {
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.eristaCpuDvfsTable)->freq);
|
||||
}
|
||||
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.eristaCpuDvfsTable)->freq);
|
||||
R_SUCCEED();
|
||||
}
|
||||
Result GpuVmin(u32 *ptr) {
|
||||
if (!C.eristaGpuVmin)
|
||||
R_SKIP();
|
||||
PATCH_OFFSET(ptr, (int)C.eristaGpuVmin);
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
@@ -127,14 +119,8 @@ namespace ams::ldr::oc::pcv::erista {
|
||||
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableSLT)->freq;
|
||||
break;
|
||||
case 2:
|
||||
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableHigh)->freq;
|
||||
break;
|
||||
case 3:
|
||||
if(C.enableEristaGpuUnsafeFreqs) {
|
||||
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableUv3UnsafeFreqs)->freq;
|
||||
} else {
|
||||
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq;
|
||||
}
|
||||
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableHigh)->freq;
|
||||
break;
|
||||
default:
|
||||
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq;
|
||||
@@ -732,6 +718,7 @@ namespace ams::ldr::oc::pcv::erista {
|
||||
{"CPU Volt Dfll", &CpuVoltDfll, 1, nullptr, 0xFFEAD0FF },
|
||||
{"GPU Freq Table", GpuFreqCvbTable<false>, 1, nullptr, GpuCvbDefaultMaxFreq},
|
||||
{"GPU Freq Asm", &GpuFreqMaxAsm, 2, &GpuMaxClockPatternFn},
|
||||
{"GPU Volt Thermal", &GpuFreqMaxAsm, 1, &GpuMaxClockPatternFn},
|
||||
{"GPU Freq PLL", &GpuFreqPllLimit, 1, nullptr, GpuClkPllLimit},
|
||||
{"MEM Freq Mtc", &MemFreqMtcTable, 0, nullptr, EmcClkOSLimit},
|
||||
{"MEM Freq Max", &MemFreqMax, 0, nullptr, EmcClkOSLimit},
|
||||
|
||||
@@ -44,19 +44,12 @@ namespace ams::ldr::oc::pcv::mariko {
|
||||
R_UNLESS(entry->min_mv == 250'000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->step_mv == 5000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->max_mv == 1525'000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
if (C.enableMarikoCpuUnsafeFreqs) {
|
||||
if (C.marikoCpuUV)
|
||||
{
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTableSLT)->freq);
|
||||
} else {
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTable)->freq);
|
||||
}
|
||||
else {
|
||||
if (C.marikoCpuUV) {
|
||||
if (!C.enableMarikoCpuUnsafeFreqs) {
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTableSLT)->freq);
|
||||
}
|
||||
else {
|
||||
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTableUnsafeFreqs)->freq);
|
||||
}
|
||||
}
|
||||
}
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
@@ -136,12 +129,12 @@ namespace ams::ldr::oc::pcv::mariko {
|
||||
PATCH_OFFSET(&(entry->tune1_low), 0x021107FF);
|
||||
PATCH_OFFSET(&(entry->tune1_high), 0x026617FF);
|
||||
break;
|
||||
case 8:
|
||||
PATCH_OFFSET(&(entry->tune0_low), 0x0000FFFF); // EOS UV6
|
||||
PATCH_OFFSET(&(entry->tune0_high), 0x0000FFFF);
|
||||
PATCH_OFFSET(&(entry->tune1_low), 0x021107FF);
|
||||
PATCH_OFFSET(&(entry->tune1_high), 0x028817FF);
|
||||
break;
|
||||
// case 8:
|
||||
// PATCH_OFFSET(&(entry->tune0_low), 0x0000FFFF); // EOS UV6
|
||||
// PATCH_OFFSET(&(entry->tune0_high), 0x0000FFFF);
|
||||
// PATCH_OFFSET(&(entry->tune1_low), 0x021107FF);
|
||||
// PATCH_OFFSET(&(entry->tune1_high), 0x028817FF);
|
||||
// break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@@ -168,15 +161,8 @@ namespace ams::ldr::oc::pcv::mariko {
|
||||
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTableSLT)->freq;
|
||||
break;
|
||||
case 2:
|
||||
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTableHiOPT)->freq;
|
||||
break;
|
||||
case 3:
|
||||
if (C.enableMarikoGpuUnsafeFreqs) {
|
||||
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTableUv3UnsafeFreqs)->freq;
|
||||
}
|
||||
else {
|
||||
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTable)->freq;
|
||||
}
|
||||
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTableHiOPT)->freq;
|
||||
break;
|
||||
default:
|
||||
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTable)->freq;
|
||||
@@ -194,16 +180,13 @@ namespace ams::ldr::oc::pcv::mariko {
|
||||
}
|
||||
|
||||
Result GpuFreqPllLimit(u32 *ptr) {
|
||||
clk_pll_param *entry = reinterpret_cast<clk_pll_param *>(ptr);
|
||||
int UPPER_GPU_FREQ = -1; // uncap the gpu frequency
|
||||
PATCH_OFFSET(ptr, UPPER_GPU_FREQ);
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
// All zero except for freq
|
||||
for (size_t i = 1; i < sizeof(clk_pll_param) / sizeof(u32); i++) {
|
||||
R_UNLESS(*(ptr + i) == 0, ldr::ResultInvalidGpuPllEntry());
|
||||
}
|
||||
|
||||
// Double the max clk simply
|
||||
u32 max_clk = entry->freq * 2;
|
||||
entry->freq = max_clk;
|
||||
Result GpuFreqMax(u32 *ptr) {
|
||||
PATCH_OFFSET(ptr, 3600000);
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
@@ -657,7 +640,8 @@ namespace ams::ldr::oc::pcv::mariko {
|
||||
{"CPU Volt Dfll", &CpuVoltDfll, 1, nullptr, 0x0000FFCF},
|
||||
{"GPU Freq Table", GpuFreqCvbTable<true>, 1, nullptr, GpuCvbDefaultMaxFreq},
|
||||
{"GPU Freq Asm", &GpuFreqMaxAsm, 2, &GpuMaxClockPatternFn},
|
||||
{"GPU Freq PLL", &GpuFreqPllLimit, 1, nullptr, GpuClkPllLimit},
|
||||
{"GPU Freq Max (Patch 1)", &GpuFreqMax, 1, nullptr, GpuClkMax},
|
||||
{"GPU Freq PLL (Patch 2)", &GpuFreqPllLimit, 0, nullptr, GpuClkPllLimit},
|
||||
{"MEM Freq Mtc", &MemFreqMtcTable, 0, nullptr, EmcClkOSLimit},
|
||||
{"MEM Freq Dvb", &MemFreqDvbTable, 1, nullptr, EmcClkOSLimit},
|
||||
{"MEM Freq Max", &MemFreqMax, 0, nullptr, EmcClkOSLimit},
|
||||
|
||||
BIN
Source/Configurator/dist/hocconfig.exe
vendored
BIN
Source/Configurator/dist/hocconfig.exe
vendored
Binary file not shown.
BIN
Source/Configurator/loader_edit.kip
Normal file
BIN
Source/Configurator/loader_edit.kip
Normal file
Binary file not shown.
@@ -1 +1 @@
|
||||
python3 src/main.py
|
||||
python src/main.py
|
||||
@@ -51,20 +51,6 @@ def populate():
|
||||
small=True,
|
||||
tag="c_freqs_info"
|
||||
)
|
||||
dpg.add_combo(
|
||||
items=["Disabled (0)", "Enabled (1)"],
|
||||
default_value="Disabled (0)",
|
||||
label="Enable CPU Unsafe Frequencies (Mariko)",
|
||||
callback=k.grab_kip_storage_values_no_mult,
|
||||
tag="enableMarikoCpuUnsafeFreqs"
|
||||
)
|
||||
dpg.add_combo(
|
||||
items=["Disabled (0)", "Enabled (1)"],
|
||||
default_value="Disabled (0)",
|
||||
label="Enable CPU Unsafe Frequencies (Erista)",
|
||||
callback=k.grab_kip_storage_values_no_mult,
|
||||
tag="enableEristaCpuUnsafeFreqs"
|
||||
)
|
||||
|
||||
dpg.add_combo(
|
||||
items=freqs_mhz_cpu_label,
|
||||
|
||||
@@ -36,10 +36,6 @@ class Defaults: # This almost always never needs to be updated as pulling from t
|
||||
self.marikoGpuUV = 0
|
||||
self.eristaCpuUV = 0
|
||||
self.eristaGpuUV = 0
|
||||
self.enableMarikoGpuUnsafeFreqs = 0
|
||||
self.enableEristaGpuUnsafeFreqs = 0
|
||||
self.enableMarikoCpuUnsafeFreqs = 0
|
||||
self.enableEristaCpuUnsafeFreqs = 0
|
||||
self.commonGpuVoltOffset = 0
|
||||
self.marikoEmcDvbShift = 0
|
||||
self.t1_tRCD = 0
|
||||
|
||||
@@ -85,20 +85,6 @@ def populate():
|
||||
tag="freqs_info"
|
||||
)
|
||||
dpg.add_checkbox(label="GPU Scheduling", default_value=True, tag="gpu_sched", callback=toggle_gpu_sched)
|
||||
dpg.add_combo(
|
||||
items=["Disabled (0)", "Enabled (1)"],
|
||||
default_value="Disabled (0)",
|
||||
label="Enable GPU Unsafe Frequencies (Mariko)",
|
||||
callback=k.grab_kip_storage_values_no_mult,
|
||||
tag="enableMarikoGpuUnsafeFreqs"
|
||||
)
|
||||
dpg.add_combo(
|
||||
items=["Disabled (0)", "Enabled (1)"],
|
||||
default_value="Disabled (0)",
|
||||
label="Enable GPU Unsafe Frequencies (Erista)",
|
||||
callback=k.grab_kip_storage_values_no_mult,
|
||||
tag="enableEristaGpuUnsafeFreqs"
|
||||
)
|
||||
|
||||
dpg.add_separator(label="Voltages")
|
||||
|
||||
|
||||
@@ -44,10 +44,10 @@ import misc
|
||||
true = True
|
||||
false = False
|
||||
|
||||
# if getattr(sys, 'frozen', False):
|
||||
assets_path = os.path.join(sys._MEIPASS, 'assets/')
|
||||
# else:
|
||||
# assets_path = os.path.join(os.path.dirname(__file__), '../assets/')
|
||||
if getattr(sys, 'frozen', False):
|
||||
assets_path = os.path.join(sys._MEIPASS, 'assets/')
|
||||
else:
|
||||
assets_path = os.path.join(os.path.dirname(__file__), '../assets/')
|
||||
|
||||
cooler_image_path = assets_path + "coolerhd.png" # coolerHD Emoji from OC server
|
||||
cooler_image = Image.open(cooler_image_path).convert("RGBA")
|
||||
|
||||
@@ -60,6 +60,7 @@ freqs_mhz_cpu = [
|
||||
variables = [
|
||||
("custRev", "u32"),
|
||||
("mtcConf", "u32"),
|
||||
("hpMode", "u32"),
|
||||
("commonCpuBoostClock", "u32"),
|
||||
("commonEmcMemVolt", "u32"),
|
||||
("eristaCpuMaxVolt", "u32"),
|
||||
@@ -71,10 +72,6 @@ variables = [
|
||||
("marikoGpuUV", "u32"),
|
||||
("eristaCpuUV", "u32"),
|
||||
("eristaGpuUV", "u32"),
|
||||
("enableMarikoGpuUnsafeFreqs", "u32"),
|
||||
("enableEristaGpuUnsafeFreqs", "u32"),
|
||||
("enableMarikoCpuUnsafeFreqs", "u32"),
|
||||
("enableEristaCpuUnsafeFreqs", "u32"),
|
||||
("commonGpuVoltOffset", "u32"),
|
||||
("marikoEmcDvbShift", "u32"),
|
||||
# advanced config
|
||||
@@ -156,10 +153,6 @@ def load_all_vars():
|
||||
c.load_entry_object("marikoGpuUV", 4)
|
||||
c.load_entry_object("eristaCpuUV", 5)
|
||||
c.load_entry_object("eristaGpuUV", 4)
|
||||
c.load_entry_object("enableMarikoGpuUnsafeFreqs", 0)
|
||||
c.load_entry_object("enableEristaGpuUnsafeFreqs", 0)
|
||||
c.load_entry_object("enableMarikoCpuUnsafeFreqs", 0)
|
||||
c.load_entry_object("enableEristaCpuUnsafeFreqs", 0)
|
||||
c.load_entry_object("commonGpuVoltOffset", 3)
|
||||
c.load_entry_object("marikoEmcDvbShift", 0)
|
||||
|
||||
|
||||
@@ -13,478 +13,484 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#define __version__ "4.5.1-multithread"
|
||||
#define __version__ "4.5.1-multithread"
|
||||
|
||||
// Include the most common headers from the C standard library
|
||||
#include <stddef.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/time.h>
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "types.h"
|
||||
#include "sizes.h"
|
||||
#include "tests.h"
|
||||
#include <switch.h>
|
||||
|
||||
PadState pad;
|
||||
unsigned short dividend = 1;
|
||||
|
||||
void waitForAnyKey() {
|
||||
while (appletMainLoop())
|
||||
{
|
||||
padUpdate(&pad);
|
||||
|
||||
u64 kDown = padGetButtonsDown(&pad);
|
||||
|
||||
if (kDown)
|
||||
break;
|
||||
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void ShowErr(const char* err, const char* details, Result rc) {
|
||||
AppletStorage errStor;
|
||||
LibAppletArgs args;
|
||||
AppletHolder currentApplet;
|
||||
|
||||
appletCreateLibraryApplet(¤tApplet, AppletId_LibraryAppletError, LibAppletMode_AllForeground);
|
||||
libappletArgsCreate(&args, 1);
|
||||
libappletArgsPush(&args, ¤tApplet);
|
||||
appletCreateStorage(&errStor, 0x1018);
|
||||
u8 argBuf[0x1018] = {0};
|
||||
argBuf[0] = 1;
|
||||
|
||||
*(u64*)&argBuf[8] = (((rc & 0x1ffu) + 2000) | (((rc >> 9) & 0x1fff & 0x1fffll) << 32));
|
||||
strcpy((char*) &argBuf[24], err);
|
||||
strcpy((char*) &argBuf[0x818], details);
|
||||
appletStorageWrite(&errStor, 0, argBuf, 0x1018);
|
||||
appletHolderPushInData(¤tApplet, &errStor);
|
||||
|
||||
appletHolderStart(¤tApplet);
|
||||
appletHolderJoin(¤tApplet);
|
||||
appletHolderClose(¤tApplet);
|
||||
appletHolderRequestExit(¤tApplet);
|
||||
}
|
||||
|
||||
double gettime(void)
|
||||
{
|
||||
struct timeval tv;
|
||||
gettimeofday(&tv, NULL);
|
||||
return (double)((int64_t)tv.tv_sec * 1000000 + tv.tv_usec) / 1000000.;
|
||||
}
|
||||
|
||||
struct test tests[] = {
|
||||
{ "Random Value", test_random_value },
|
||||
{ "Compare XOR", test_xor_comparison },
|
||||
{ "Compare SUB", test_sub_comparison },
|
||||
{ "Compare MUL", test_mul_comparison },
|
||||
{ "Compare DIV",test_div_comparison },
|
||||
{ "Compare OR", test_or_comparison },
|
||||
{ "Compare AND", test_and_comparison },
|
||||
{ "Sequential Increment", test_seqinc_comparison },
|
||||
{ "Solid Bits", test_solidbits_comparison },
|
||||
{ "Block Sequential", test_blockseq_comparison },
|
||||
{ "Checkerboard", test_checkerboard_comparison },
|
||||
{ "Bit Spread", test_bitspread_comparison },
|
||||
{ "Bit Flip (Slow)", test_bitflip_comparison },
|
||||
{ "Walking Ones", test_walkbits1_comparison },
|
||||
{ "Walking Zeroes", test_walkbits0_comparison },
|
||||
#ifdef TEST_NARROW_WRITES
|
||||
{ "8-bit Writes", test_8bit_wide_random },
|
||||
{ "16-bit Writes", test_16bit_wide_random },
|
||||
#endif
|
||||
{ NULL, NULL }
|
||||
};
|
||||
|
||||
struct test stress_tests[] = {
|
||||
{ "Stress memcpy x128", test_stress_memcpy },
|
||||
{ "Stress memset x128", test_stress_memset },
|
||||
{ "Stress memcmp x 32", test_stress_memcmp },
|
||||
{ NULL, NULL }
|
||||
};
|
||||
|
||||
int memtester_pagesize(void) {
|
||||
printf("using pagesize of 4096\n");
|
||||
return 4096;
|
||||
}
|
||||
|
||||
/* Global vars - so tests have access to this information */
|
||||
int use_phys = 0;
|
||||
off_t physaddrbase = 0;
|
||||
int testJobId[4] = {0};
|
||||
int testWorkerReport[4] = {0};
|
||||
size_t bufsize[4], wantbytes[4];
|
||||
void volatile *aligned[4];
|
||||
Thread threads[5];
|
||||
struct test* test_select = tests;
|
||||
|
||||
void testWorker(int div)
|
||||
{
|
||||
// Get ready
|
||||
while (testJobId[div] != -2)
|
||||
svcSleepThread(10000000ULL);
|
||||
|
||||
while (true)
|
||||
{
|
||||
int currentJobId = -1;
|
||||
|
||||
// Stuck address
|
||||
while (testJobId[div] != currentJobId)
|
||||
svcSleepThread(10000000ULL);
|
||||
|
||||
if (!test_stuck_address(aligned[div], bufsize[div]/sizeof(ul)))
|
||||
{
|
||||
testWorkerReport[div] = 1;
|
||||
currentJobId++;
|
||||
}
|
||||
else
|
||||
{
|
||||
testWorkerReport[div] = -1;
|
||||
return;
|
||||
}
|
||||
|
||||
// tests[], currentJobId = 0 here
|
||||
while (test_select[currentJobId].name)
|
||||
{
|
||||
while (testJobId[div] != currentJobId)
|
||||
svcSleepThread(10000000ULL);
|
||||
|
||||
int test_rc = test_select[currentJobId].fp(aligned[div], ((size_t)aligned[div] + bufsize[div]/2), bufsize[div]/sizeof(ul)/2);
|
||||
if (!test_rc)
|
||||
{
|
||||
testWorkerReport[div] = 1;
|
||||
currentJobId++;
|
||||
}
|
||||
else
|
||||
{
|
||||
testWorkerReport[div] = -1;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void testWorker0(void*) { testWorker(0); }
|
||||
void testWorker1(void*) { testWorker(1); }
|
||||
void testWorker2(void*) { testWorker(2); }
|
||||
void testWorker3(void*) { testWorker(3); }
|
||||
|
||||
void* workers[] = {
|
||||
testWorker0,
|
||||
testWorker1,
|
||||
testWorker2,
|
||||
testWorker3,
|
||||
};
|
||||
|
||||
void LblUpdate()
|
||||
{
|
||||
smInitialize();
|
||||
lblInitialize();
|
||||
LblBacklightSwitchStatus lblstatus = LblBacklightSwitchStatus_Disabled;
|
||||
lblGetBacklightSwitchStatus(&lblstatus);
|
||||
if (lblstatus) {
|
||||
lblSwitchBacklightOff(0);
|
||||
} else {
|
||||
lblSwitchBacklightOn(0);
|
||||
}
|
||||
lblExit();
|
||||
smExit();
|
||||
}
|
||||
|
||||
void keyListener()
|
||||
{
|
||||
while (true)
|
||||
{
|
||||
padUpdate(&pad);
|
||||
u64 kDown = padGetButtonsDown(&pad);
|
||||
if (kDown & HidNpadButton_Minus)
|
||||
{
|
||||
LblUpdate();
|
||||
}
|
||||
svcSleepThread(10000000ULL);
|
||||
}
|
||||
}
|
||||
|
||||
// Main program entrypoint
|
||||
int main(int argc, char* argv[])
|
||||
{
|
||||
if(appletGetAppletType() != AppletType_Application) {
|
||||
ShowErr("Running in applet mode\nMemTesterNX requires full memory mode.\nPlease launch hbmenu by holding R on an APP (e.g. a game) NOT an applet (e.g. Gallery)", "", 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
appletReportUserIsActive();
|
||||
|
||||
consoleInit(NULL);
|
||||
|
||||
padConfigureInput(1, HidNpadStyleSet_NpadStandard);
|
||||
|
||||
padInitializeDefault(&pad);
|
||||
|
||||
ull loop, i;
|
||||
unsigned short div, testThreads = 3;
|
||||
size_t pagesize, wantraw, wantbytes_orig;
|
||||
ptrdiff_t pagesizemask;
|
||||
void volatile *buf[4];
|
||||
int memshift;
|
||||
ull totalmem = 0;
|
||||
int numOfMallocs = 0;
|
||||
bool isDevKit8GB = false;
|
||||
|
||||
printf("MemTesterNX version " __version__ " (%d-bit)\n"\
|
||||
"Based on memtester. Copyright (C) 2001-2020 Charles Cazabon, 2021 KazushiMe.\n"\
|
||||
"Licensed under the GNU General Public License version 2 (only).\n\n"\
|
||||
"Support full RAM test (up to 8GB) with 3-4 threads.\n"\
|
||||
"It will be looping forever until error occurs or user exits to HOME screen.\n\n"\
|
||||
"Press A: long test\n"\
|
||||
"Press X: fast test\n"\
|
||||
"Press Y: stress DRAM (memcpy, memset and memcmp)\n"\
|
||||
"Press any other key: exit\n\n",
|
||||
UL_LEN);
|
||||
|
||||
while (appletMainLoop())
|
||||
{
|
||||
padUpdate(&pad);
|
||||
|
||||
u64 kDown = padGetButtonsDown(&pad);
|
||||
|
||||
if (kDown & HidNpadButton_A)
|
||||
{
|
||||
break;
|
||||
}
|
||||
else if (kDown & HidNpadButton_X)
|
||||
{
|
||||
dividend = 4;
|
||||
break;
|
||||
}
|
||||
else if (kDown & HidNpadButton_Y)
|
||||
{
|
||||
dividend = 16;
|
||||
test_select = stress_tests;
|
||||
break;
|
||||
}
|
||||
else if (kDown)
|
||||
{
|
||||
consoleExit(NULL);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
|
||||
// Disable auto sleep and request CPU Boost mode
|
||||
appletSetAutoSleepDisabled(true);
|
||||
appletSetCpuBoostMode(ApmCpuBoostMode_FastLoad);
|
||||
|
||||
pagesize = memtester_pagesize();
|
||||
pagesizemask = (ptrdiff_t) ~(pagesize - 1);
|
||||
printf("pagesizemask is 0x%tx\n", pagesizemask);
|
||||
consoleUpdate(NULL);
|
||||
|
||||
memshift = 20; /* megabytes */
|
||||
wantraw = 2048; // HOS limit
|
||||
|
||||
wantbytes_orig = ((size_t) wantraw << memshift);
|
||||
|
||||
// Allocate as much RAM as possible.
|
||||
for (div = 0; div <= 3; div++)
|
||||
{
|
||||
buf[div] = NULL;
|
||||
wantbytes[div] = wantbytes_orig;
|
||||
|
||||
while (!buf[div] && wantbytes[div]) {
|
||||
buf[div] = (void volatile *) malloc(wantbytes[div]);
|
||||
if (!buf[div])
|
||||
wantbytes[div] -= pagesize;
|
||||
}
|
||||
|
||||
totalmem += wantbytes[div];
|
||||
|
||||
if ((wantbytes[div] >> memshift) < 2047)
|
||||
{
|
||||
numOfMallocs = div + 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (div = 0; div < numOfMallocs; div++)
|
||||
{
|
||||
free((void *)buf[div]);
|
||||
}
|
||||
|
||||
// Unknown: Not sure if devkit could use full 8GB in application space
|
||||
if ((totalmem >> memshift) > 3 * 2047)
|
||||
{
|
||||
isDevKit8GB = true;
|
||||
testThreads = 4;
|
||||
}
|
||||
|
||||
// Create workers
|
||||
for (div = 0; div < testThreads; div++)
|
||||
{
|
||||
Result rc;
|
||||
rc = threadCreate(&threads[div], workers[div], NULL, NULL, 0x1000, 0x2C, div == 3 ? -2 : div);
|
||||
if (R_FAILED(rc))
|
||||
{
|
||||
printf("Fatal: threadCreate[%d] failed: 0x%X\n", div, rc);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
totalmem -= 0x1000;
|
||||
}
|
||||
}
|
||||
|
||||
// keyListener
|
||||
{
|
||||
const int kl = testThreads;
|
||||
Result rc = threadCreate(&threads[kl], keyListener, NULL, NULL, 0x1000, 0x20, -2);
|
||||
if (R_FAILED(rc))
|
||||
{
|
||||
printf("Fatal: threadCreate[%d] failed: 0x%X\n", div, rc);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
threadStart(&threads[kl]);
|
||||
}
|
||||
|
||||
printf("\nTotal RAM available: %lldMB\n\n", totalmem >> memshift);
|
||||
consoleUpdate(NULL);
|
||||
|
||||
// Redistribute RAM allocation equally to testThreads workers
|
||||
for (div = 0; div < testThreads; div++)
|
||||
{
|
||||
buf[div] = NULL;
|
||||
if (isDevKit8GB)
|
||||
{
|
||||
if (div != 3)
|
||||
wantbytes[div] = totalmem / 3;
|
||||
else
|
||||
wantbytes[div] = 2047;
|
||||
}
|
||||
else
|
||||
{
|
||||
wantbytes[div] = totalmem / testThreads;
|
||||
}
|
||||
|
||||
while (!buf[div] && wantbytes[div]) {
|
||||
buf[div] = (void volatile *) malloc(wantbytes[div]);
|
||||
if (!buf[div])
|
||||
wantbytes[div] -= pagesize;
|
||||
}
|
||||
|
||||
bufsize[div] = wantbytes[div];
|
||||
|
||||
/* Do alighnment here as well, as some cases won't trigger above if you
|
||||
define out the use of mlock() (cough HP/UX 10 cough). */
|
||||
if ((size_t) buf[div] % pagesize) {
|
||||
/* printf("aligning to page -- was 0x%tx\n", buf); */
|
||||
aligned[div] = (void volatile *) ((size_t) buf[div] & pagesizemask) + pagesize;
|
||||
/* printf(" now 0x%tx -- lost %d bytes\n", aligned,
|
||||
* (size_t) aligned - (size_t) buf);
|
||||
*/
|
||||
bufsize[div] -= ((size_t) aligned[div] - (size_t) buf[div]);
|
||||
} else {
|
||||
aligned[div] = buf[div];
|
||||
}
|
||||
|
||||
printf("Alloc %d: got %lluMB (%llu bytes)\n", div+1, (ull) wantbytes[div] >> memshift, (ull) wantbytes[div]);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
|
||||
// Start workers
|
||||
for (div = 0; div < testThreads; div++)
|
||||
{
|
||||
Result rc;
|
||||
rc = threadStart(&threads[div]);
|
||||
if (R_FAILED(rc))
|
||||
{
|
||||
printf("Fatal: threadStart[%d] failed: 0x%X\n", div, rc);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
for(loop=1;;loop++)
|
||||
{
|
||||
// Set testJobId to -2(Ready)
|
||||
for (int j = 0; j < testThreads; j++)
|
||||
testJobId[j] = -2;
|
||||
|
||||
printf("Loop %llu:\n", loop);
|
||||
|
||||
// Stuck address (-1)
|
||||
printf(" %-20s: ", "Stuck Address");
|
||||
consoleUpdate(NULL);
|
||||
for (int j = 0; j < testThreads; j++)
|
||||
testJobId[j] = -1;
|
||||
|
||||
for (int j = 0; j < testThreads; )
|
||||
{
|
||||
switch (testWorkerReport[j])
|
||||
{
|
||||
case 0:
|
||||
svcSleepThread(10000000ULL);
|
||||
break;
|
||||
case -1:
|
||||
printf("Alloc %d/%d: Error detected!\nPress any key to exit.\n", j+1, testThreads+1);
|
||||
consoleUpdate(NULL);
|
||||
waitForAnyKey();
|
||||
consoleExit(NULL);
|
||||
return 0;
|
||||
case 1:
|
||||
testWorkerReport[j] = 0;
|
||||
j++;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
printf("ok\n");
|
||||
consoleUpdate(NULL);
|
||||
|
||||
// tests[]
|
||||
for (i = 0 ;; i++) {
|
||||
if (!test_select[i].name)
|
||||
break;
|
||||
|
||||
printf(" %-20s: ...", test_select[i].name);
|
||||
consoleUpdate(NULL);
|
||||
for (int j = 0; j < testThreads; j++)
|
||||
testJobId[j] = i;
|
||||
|
||||
double start_sec = gettime();
|
||||
for (int j = 0; j < testThreads; )
|
||||
{
|
||||
switch (testWorkerReport[j])
|
||||
{
|
||||
case 0:
|
||||
svcSleepThread(10000000ULL);
|
||||
continue;
|
||||
case -1:
|
||||
printf("Alloc %d/%d: Error detected!\nPress any key to exit.\n", j+1, testThreads+1);
|
||||
consoleUpdate(NULL);
|
||||
waitForAnyKey();
|
||||
consoleExit(NULL);
|
||||
return 0;
|
||||
case 1:
|
||||
testWorkerReport[j] = 0;
|
||||
j++;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
double end_sec = gettime();
|
||||
printf("\b\b\bok! finished in %.1fs\n", end_sec - start_sec);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
// Deinitialize and clean up resources used by the console (important!)
|
||||
consoleExit(NULL);
|
||||
return 0;
|
||||
}
|
||||
#include <stddef.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/time.h>
|
||||
#include <fcntl.h>
|
||||
#include <errno.h>
|
||||
#include <stdint.h> // for int64_t etc
|
||||
|
||||
#include "types.h"
|
||||
#include "sizes.h"
|
||||
#include "tests.h"
|
||||
#include <switch.h>
|
||||
|
||||
/* Some helpful typedefs used throughout the file (used by original code) */
|
||||
typedef unsigned long long ull;
|
||||
typedef unsigned long ul;
|
||||
|
||||
/* number of bits in a machine word printed in the header */
|
||||
#define MACHINE_BITS ((int)(sizeof(void*) * 8))
|
||||
|
||||
PadState pad;
|
||||
unsigned short dividend = 1;
|
||||
|
||||
void waitForAnyKey() {
|
||||
while (appletMainLoop())
|
||||
{
|
||||
padUpdate(&pad);
|
||||
|
||||
u64 kDown = padGetButtonsDown(&pad);
|
||||
|
||||
if (kDown)
|
||||
break;
|
||||
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
void ShowErr(const char* err, const char* details, Result rc) {
|
||||
AppletStorage errStor;
|
||||
LibAppletArgs args;
|
||||
AppletHolder currentApplet;
|
||||
|
||||
appletCreateLibraryApplet(¤tApplet, AppletId_LibraryAppletError, LibAppletMode_AllForeground);
|
||||
libappletArgsCreate(&args, 1);
|
||||
libappletArgsPush(&args, ¤tApplet);
|
||||
appletCreateStorage(&errStor, 0x1018);
|
||||
u8 argBuf[0x1018] = {0};
|
||||
argBuf[0] = 1;
|
||||
|
||||
/* keep existing packing used by original code */
|
||||
*(u64*)&argBuf[8] = (((rc & 0x1ffu) + 2000) | (((rc >> 9) & 0x1fff & 0x1fffll) << 32));
|
||||
strcpy((char*) &argBuf[24], err);
|
||||
strcpy((char*) &argBuf[0x818], details);
|
||||
appletStorageWrite(&errStor, 0, argBuf, 0x1018);
|
||||
appletHolderPushInData(¤tApplet, &errStor);
|
||||
|
||||
appletHolderStart(¤tApplet);
|
||||
appletHolderJoin(¤tApplet);
|
||||
appletHolderClose(¤tApplet);
|
||||
appletHolderRequestExit(¤tApplet);
|
||||
}
|
||||
|
||||
double gettime(void)
|
||||
{
|
||||
struct timeval tv;
|
||||
gettimeofday(&tv, NULL);
|
||||
return (double)((int64_t)tv.tv_sec * 1000000 + tv.tv_usec) / 1000000.;
|
||||
}
|
||||
|
||||
struct test tests[] = {
|
||||
{ "Random Value", test_random_value },
|
||||
{ "Compare XOR", test_xor_comparison },
|
||||
{ "Compare SUB", test_sub_comparison },
|
||||
{ "Compare MUL", test_mul_comparison },
|
||||
{ "Compare DIV", test_div_comparison },
|
||||
{ "Compare OR", test_or_comparison },
|
||||
{ "Compare AND", test_and_comparison },
|
||||
{ "Sequential Increment", test_seqinc_comparison },
|
||||
{ "Solid Bits", test_solidbits_comparison },
|
||||
{ "Block Sequential", test_blockseq_comparison },
|
||||
{ "Checkerboard", test_checkerboard_comparison },
|
||||
{ "Bit Spread", test_bitspread_comparison },
|
||||
{ "Bit Flip (Slow)", test_bitflip_comparison },
|
||||
{ "Walking Ones", test_walkbits1_comparison },
|
||||
{ "Walking Zeroes", test_walkbits0_comparison },
|
||||
#ifdef TEST_NARROW_WRITES
|
||||
{ "8-bit Writes", test_8bit_wide_random },
|
||||
{ "16-bit Writes", test_16bit_wide_random },
|
||||
#endif
|
||||
{ NULL, NULL }
|
||||
};
|
||||
|
||||
struct test stress_tests[] = {
|
||||
{ "Stress memcpy x128", test_stress_memcpy },
|
||||
{ "Stress memset x128", test_stress_memset },
|
||||
{ "Stress memcmp x 32", test_stress_memcmp },
|
||||
{ NULL, NULL }
|
||||
};
|
||||
|
||||
int memtester_pagesize(void) {
|
||||
printf("using pagesize of 4096\n");
|
||||
return 4096;
|
||||
}
|
||||
|
||||
/* Global vars - so tests have access to this information */
|
||||
int use_phys = 0;
|
||||
off_t physaddrbase = 0;
|
||||
int testJobId[4] = {0};
|
||||
int testWorkerReport[4] = {0};
|
||||
size_t bufsize[4], wantbytes[4];
|
||||
void volatile *aligned[4];
|
||||
Thread threads[5];
|
||||
struct test* test_select = tests;
|
||||
|
||||
void testWorker(int div)
|
||||
{
|
||||
/* Wait until main sets this worker to ready (-2) */
|
||||
while (testJobId[div] != -2)
|
||||
svcSleepThread(10000000ULL);
|
||||
|
||||
while (true)
|
||||
{
|
||||
int currentJobId = -1;
|
||||
|
||||
/* Wait until main moves us to the stuck-address job (-1) */
|
||||
while (testJobId[div] != currentJobId)
|
||||
svcSleepThread(10000000ULL);
|
||||
|
||||
/* Stuck address test: bufsize is in bytes, test_stuck_address expects count in ul units */
|
||||
if (!test_stuck_address(aligned[div], bufsize[div] / sizeof(ul)))
|
||||
{
|
||||
testWorkerReport[div] = 1;
|
||||
currentJobId++;
|
||||
}
|
||||
else
|
||||
{
|
||||
testWorkerReport[div] = -1;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Now iterate over the selected tests */
|
||||
while (test_select[currentJobId].name)
|
||||
{
|
||||
while (testJobId[div] != currentJobId)
|
||||
svcSleepThread(10000000ULL);
|
||||
|
||||
/* Ensure second pointer argument is a pointer (not integer) */
|
||||
void volatile *second_ptr = (void volatile *)((size_t)aligned[div] + bufsize[div] / 2);
|
||||
int test_rc = test_select[currentJobId].fp(aligned[div], second_ptr, (bufsize[div] / sizeof(ul)) / 2);
|
||||
if (!test_rc)
|
||||
{
|
||||
testWorkerReport[div] = 1;
|
||||
currentJobId++;
|
||||
}
|
||||
else
|
||||
{
|
||||
testWorkerReport[div] = -1;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void testWorker0(void*) { testWorker(0); }
|
||||
void testWorker1(void*) { testWorker(1); }
|
||||
void testWorker2(void*) { testWorker(2); }
|
||||
void testWorker3(void*) { testWorker(3); }
|
||||
|
||||
void* workers[] = {
|
||||
testWorker0,
|
||||
testWorker1,
|
||||
testWorker2,
|
||||
testWorker3,
|
||||
};
|
||||
|
||||
void LblUpdate()
|
||||
{
|
||||
smInitialize();
|
||||
lblInitialize();
|
||||
LblBacklightSwitchStatus lblstatus = LblBacklightSwitchStatus_Disabled;
|
||||
lblGetBacklightSwitchStatus(&lblstatus);
|
||||
if (lblstatus) {
|
||||
lblSwitchBacklightOff(0);
|
||||
} else {
|
||||
lblSwitchBacklightOn(0);
|
||||
}
|
||||
lblExit();
|
||||
smExit();
|
||||
}
|
||||
|
||||
void keyListener()
|
||||
{
|
||||
while (true)
|
||||
{
|
||||
padUpdate(&pad);
|
||||
u64 kDown = padGetButtonsDown(&pad);
|
||||
if (kDown & HidNpadButton_Minus)
|
||||
{
|
||||
LblUpdate();
|
||||
}
|
||||
svcSleepThread(10000000ULL);
|
||||
}
|
||||
}
|
||||
|
||||
// Main program entrypoint
|
||||
int main(int argc, char* argv[])
|
||||
{
|
||||
if(appletGetAppletType() != AppletType_Application) {
|
||||
ShowErr("Running in applet mode\nMemTesterNX requires full memory mode.\nPlease launch hbmenu by holding R on an APP (e.g. a game) NOT an applet (e.g. Gallery)", "", 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
appletReportUserIsActive();
|
||||
|
||||
consoleInit(NULL);
|
||||
|
||||
padConfigureInput(1, HidNpadStyleSet_NpadStandard);
|
||||
|
||||
padInitializeDefault(&pad);
|
||||
|
||||
ull loop;
|
||||
size_t i;
|
||||
unsigned short div, testThreads = 3;
|
||||
size_t pagesize, wantraw, wantbytes_orig;
|
||||
ptrdiff_t pagesizemask;
|
||||
void volatile *buf[4];
|
||||
int memshift;
|
||||
ull totalmem = 0;
|
||||
int numOfMallocs = 0;
|
||||
bool isDevKit8GB = false;
|
||||
|
||||
printf("MemTesterNX version " __version__ " (%d-bit)\n"\
|
||||
"Based on memtester. Copyright (C) 2001-2020 Charles Cazabon, 2021 KazushiMe.\n"\
|
||||
"Licensed under the GNU General Public License version 2 (only).\n\n"\
|
||||
"Support full RAM test (up to 8GB) with 3-4 threads.\n"\
|
||||
"It will be looping forever until error occurs or user exits to HOME screen.\n\n"\
|
||||
"Press A: long test\n"\
|
||||
"Press X: fast test\n"\
|
||||
"Press Y: stress DRAM (memcpy, memset and memcmp)\n"\
|
||||
"Press any other key: exit\n\n",
|
||||
MACHINE_BITS);
|
||||
|
||||
while (appletMainLoop())
|
||||
{
|
||||
padUpdate(&pad);
|
||||
|
||||
u64 kDown = padGetButtonsDown(&pad);
|
||||
|
||||
if (kDown & HidNpadButton_A)
|
||||
{
|
||||
break;
|
||||
}
|
||||
else if (kDown & HidNpadButton_X)
|
||||
{
|
||||
dividend = 4;
|
||||
break;
|
||||
}
|
||||
else if (kDown & HidNpadButton_Y)
|
||||
{
|
||||
dividend = 16;
|
||||
test_select = stress_tests;
|
||||
break;
|
||||
}
|
||||
else if (kDown)
|
||||
{
|
||||
consoleExit(NULL);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
|
||||
// Disable auto sleep and request CPU Boost mode
|
||||
appletSetAutoSleepDisabled(true);
|
||||
appletSetCpuBoostMode(ApmCpuBoostMode_FastLoad);
|
||||
|
||||
pagesize = memtester_pagesize();
|
||||
pagesizemask = (ptrdiff_t) ~(pagesize - 1);
|
||||
printf("pagesizemask is 0x%tx\n", pagesizemask);
|
||||
consoleUpdate(NULL);
|
||||
|
||||
memshift = 20; /* megabytes */
|
||||
wantraw = 2048; // HOS limit
|
||||
|
||||
wantbytes_orig = ((size_t) wantraw << memshift);
|
||||
|
||||
// Allocate as much RAM as possible.
|
||||
for (div = 0; div <= 3; div++)
|
||||
{
|
||||
buf[div] = NULL;
|
||||
wantbytes[div] = wantbytes_orig;
|
||||
|
||||
while (!buf[div] && wantbytes[div]) {
|
||||
buf[div] = (void volatile *) malloc(wantbytes[div]);
|
||||
if (!buf[div])
|
||||
wantbytes[div] -= pagesize;
|
||||
}
|
||||
|
||||
totalmem += wantbytes[div];
|
||||
|
||||
if ((wantbytes[div] >> memshift) < 2047)
|
||||
{
|
||||
numOfMallocs = div + 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (div = 0; div < numOfMallocs; div++)
|
||||
{
|
||||
free((void *)buf[div]);
|
||||
}
|
||||
|
||||
// Unknown: Not sure if devkit could use full 8GB in application space
|
||||
if ((totalmem >> memshift) > 3 * 2047)
|
||||
{
|
||||
isDevKit8GB = true;
|
||||
testThreads = 4;
|
||||
}
|
||||
|
||||
// Create workers
|
||||
for (div = 0; div < testThreads; div++)
|
||||
{
|
||||
Result rc;
|
||||
rc = threadCreate(&threads[div], workers[div], NULL, NULL, 0x1000, 0x2C, div == 3 ? -2 : div);
|
||||
if (R_FAILED(rc))
|
||||
{
|
||||
printf("Fatal: threadCreate[%d] failed: 0x%X\n", div, rc);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
totalmem -= 0x1000;
|
||||
}
|
||||
}
|
||||
|
||||
// keyListener
|
||||
{
|
||||
const int kl = testThreads;
|
||||
Result rc = threadCreate(&threads[kl], keyListener, NULL, NULL, 0x1000, 0x20, -2);
|
||||
if (R_FAILED(rc))
|
||||
{
|
||||
printf("Fatal: threadCreate[%d] failed: 0x%X\n", kl, rc);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
threadStart(&threads[kl]);
|
||||
}
|
||||
|
||||
printf("\nTotal RAM available: %lluMB\n\n", (unsigned long long)(totalmem >> memshift));
|
||||
consoleUpdate(NULL);
|
||||
|
||||
// Redistribute RAM allocation equally to testThreads workers
|
||||
for (div = 0; div < testThreads; div++)
|
||||
{
|
||||
buf[div] = NULL;
|
||||
if (isDevKit8GB)
|
||||
{
|
||||
if (div != 3)
|
||||
wantbytes[div] = totalmem / 3;
|
||||
else
|
||||
wantbytes[div] = 2047 << memshift; /* convert MB to bytes */
|
||||
}
|
||||
else
|
||||
{
|
||||
wantbytes[div] = totalmem / testThreads;
|
||||
}
|
||||
|
||||
while (!buf[div] && wantbytes[div]) {
|
||||
buf[div] = (void volatile *) malloc(wantbytes[div]);
|
||||
if (!buf[div])
|
||||
wantbytes[div] -= pagesize;
|
||||
}
|
||||
|
||||
bufsize[div] = wantbytes[div];
|
||||
|
||||
/* Do alignment here as well */
|
||||
if ((size_t) buf[div] % pagesize) {
|
||||
aligned[div] = (void volatile *) (((size_t) buf[div] & pagesizemask) + pagesize);
|
||||
bufsize[div] -= ((size_t) aligned[div] - (size_t) buf[div]);
|
||||
} else {
|
||||
aligned[div] = buf[div];
|
||||
}
|
||||
|
||||
printf("Alloc %d: got %lluMB (%llu bytes)\n", div+1, (unsigned long long)(wantbytes[div] >> memshift), (unsigned long long)wantbytes[div]);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
|
||||
// Start workers
|
||||
for (div = 0; div < testThreads; div++)
|
||||
{
|
||||
Result rc;
|
||||
rc = threadStart(&threads[div]);
|
||||
if (R_FAILED(rc))
|
||||
{
|
||||
printf("Fatal: threadStart[%d] failed: 0x%X\n", div, rc);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
for(loop=1;;loop++)
|
||||
{
|
||||
// Set testJobId to -2 (Ready)
|
||||
for (int j = 0; j < testThreads; j++)
|
||||
testJobId[j] = -2;
|
||||
|
||||
printf("Loop %llu:\n", (unsigned long long)loop);
|
||||
|
||||
// Stuck address (-1)
|
||||
printf(" %-20s: ", "Stuck Address");
|
||||
consoleUpdate(NULL);
|
||||
for (int j = 0; j < testThreads; j++)
|
||||
testJobId[j] = -1;
|
||||
|
||||
for (int j = 0; j < testThreads; )
|
||||
{
|
||||
switch (testWorkerReport[j])
|
||||
{
|
||||
case 0:
|
||||
svcSleepThread(10000000ULL);
|
||||
break;
|
||||
case -1:
|
||||
printf("Alloc %d/%d: Error detected!\nPress any key to exit.\n", j+1, testThreads);
|
||||
consoleUpdate(NULL);
|
||||
waitForAnyKey();
|
||||
consoleExit(NULL);
|
||||
return 0;
|
||||
case 1:
|
||||
testWorkerReport[j] = 0;
|
||||
j++;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
printf("ok\n");
|
||||
consoleUpdate(NULL);
|
||||
|
||||
// tests[]
|
||||
for (i = 0 ;; i++) {
|
||||
if (!test_select[i].name)
|
||||
break;
|
||||
|
||||
printf(" %-20s: ...", test_select[i].name);
|
||||
consoleUpdate(NULL);
|
||||
for (int j = 0; j < testThreads; j++)
|
||||
testJobId[j] = (int)i;
|
||||
|
||||
double start_sec = gettime();
|
||||
for (int j = 0; j < testThreads; )
|
||||
{
|
||||
switch (testWorkerReport[j])
|
||||
{
|
||||
case 0:
|
||||
svcSleepThread(10000000ULL);
|
||||
continue;
|
||||
case -1:
|
||||
printf("Alloc %d/%d: Error detected!\nPress any key to exit.\n", j+1, testThreads);
|
||||
consoleUpdate(NULL);
|
||||
waitForAnyKey();
|
||||
consoleExit(NULL);
|
||||
return 0;
|
||||
case 1:
|
||||
testWorkerReport[j] = 0;
|
||||
j++;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
double end_sec = gettime();
|
||||
printf("\b\b\bok! finished in %.1fs\n", end_sec - start_sec);
|
||||
consoleUpdate(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
// Deinitialize and clean up resources used by the console (important!)
|
||||
consoleExit(NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -25,10 +25,6 @@ public:
|
||||
data.marikoGpuUV = 0;
|
||||
data.eristaCpuUV = 0;
|
||||
data.eristaGpuUV = 0;
|
||||
data.enableMarikoGpuUnsafeFreqs = 0;
|
||||
data.enableEristaGpuUnsafeFreqs = 0;
|
||||
data.enableMarikoCpuUnsafeFreqs = 0;
|
||||
data.enableEristaCpuUnsafeFreqs = 0;
|
||||
data.commonGpuVoltOffset = 0;
|
||||
data.marikoEmcDvbShift = 0;
|
||||
|
||||
|
||||
@@ -28,10 +28,6 @@ private:
|
||||
uint32_t marikoGpuUV;
|
||||
uint32_t eristaCpuUV;
|
||||
uint32_t eristaGpuUV;
|
||||
uint32_t enableMarikoGpuUnsafeFreqs;
|
||||
uint32_t enableEristaGpuUnsafeFreqs;
|
||||
uint32_t enableMarikoCpuUnsafeFreqs;
|
||||
uint32_t enableEristaCpuUnsafeFreqs;
|
||||
uint32_t commonGpuVoltOffset;
|
||||
uint32_t marikoEmcDvbShift;
|
||||
|
||||
|
||||
@@ -60,10 +60,6 @@ bool KipHandler::readKip() {
|
||||
data.marikoGpuUV = readU32();
|
||||
data.eristaCpuUV = readU32();
|
||||
data.eristaGpuUV = readU32();
|
||||
data.enableMarikoGpuUnsafeFreqs = readU32();
|
||||
data.enableEristaGpuUnsafeFreqs = readU32();
|
||||
data.enableMarikoCpuUnsafeFreqs = readU32();
|
||||
data.enableEristaCpuUnsafeFreqs = readU32();
|
||||
data.commonGpuVoltOffset = readU32();
|
||||
data.marikoEmcDvbShift = readU32();
|
||||
|
||||
@@ -179,10 +175,6 @@ bool KipHandler::writeKip() {
|
||||
writeU32(data.marikoGpuUV);
|
||||
writeU32(data.eristaCpuUV);
|
||||
writeU32(data.eristaGpuUV);
|
||||
writeU32(data.enableMarikoGpuUnsafeFreqs);
|
||||
writeU32(data.enableEristaGpuUnsafeFreqs);
|
||||
writeU32(data.enableMarikoCpuUnsafeFreqs);
|
||||
writeU32(data.enableEristaCpuUnsafeFreqs);
|
||||
writeU32(data.commonGpuVoltOffset);
|
||||
writeU32(data.marikoEmcDvbShift);
|
||||
|
||||
|
||||
@@ -111,8 +111,6 @@ void UI::renderGPUMenu() {
|
||||
|
||||
auto& data = kipHandler->getData();
|
||||
std::vector<std::string> menuItems = {
|
||||
"Enable Unsafe Frequencies (Mariko): " + std::string(data.enableMarikoGpuUnsafeFreqs ? "ON" : "OFF"),
|
||||
"Enable Unsafe Frequencies (Erista): " + std::string(data.enableEristaGpuUnsafeFreqs ? "ON" : "OFF"),
|
||||
"Mariko GPU vMin: " + (data.marikoGpuVmin == 0 ? "Disabled" : std::to_string(data.marikoGpuVmin) + "mV"),
|
||||
"Mariko GPU vMax: " + (data.marikoGpuVmax == 0 ? "Disabled" : std::to_string(data.marikoGpuVmax) + "mV"),
|
||||
"Erista GPU vMin: " + (data.eristaGpuVmin == 0 ? "Disabled" : std::to_string(data.eristaGpuVmin) + "mV"),
|
||||
@@ -144,8 +142,6 @@ void UI::renderCPUMenu() {
|
||||
|
||||
auto& data = kipHandler->getData();
|
||||
std::vector<std::string> menuItems = {
|
||||
"Enable Unsafe Frequencies (Mariko): " + std::string(data.enableMarikoCpuUnsafeFreqs ? "ON" : "OFF"),
|
||||
"Enable Unsafe Frequencies (Erista): " + std::string(data.enableEristaCpuUnsafeFreqs ? "ON" : "OFF"),
|
||||
"CPU Boost Frequency: " + std::to_string(data.commonCpuBoostClock / 1000) + " MHz",
|
||||
"Mariko CPU vMin: " + (data.marikoCpuVmin == 0 ? "Default" : std::to_string(data.marikoCpuVmin) + "mV"),
|
||||
"Mariko CPU vMax: " + (data.marikoCpuMaxVolt == 0 ? "Disabled" : std::to_string(data.marikoCpuMaxVolt) + "mV"),
|
||||
@@ -346,28 +342,6 @@ void UI::handleGPUMenuInput(u64 kDown) {
|
||||
auto& data = kipHandler->getData();
|
||||
|
||||
switch (selectedIndex) {
|
||||
case 0: { // Mariko GPU Unsafe Freqs
|
||||
std::vector<std::string> opts = {"Disabled (0)", "Enabled (1)"};
|
||||
showValueEditor("Enable Unsafe GPU Frequencies (Mariko)", EditorType::LIST,
|
||||
data.enableMarikoGpuUnsafeFreqs,
|
||||
[this, &data](int val) {
|
||||
data.enableMarikoGpuUnsafeFreqs = val;
|
||||
if (autoSave && kipHandler) kipHandler->writeKip();
|
||||
setStatus("Mariko GPU unsafe: " + std::string(val ? "ENABLED" : "DISABLED"));
|
||||
}, opts);
|
||||
break;
|
||||
}
|
||||
case 1: { // Erista GPU Unsafe Freqs
|
||||
std::vector<std::string> opts = {"Disabled (0)", "Enabled (1)"};
|
||||
showValueEditor("Enable Unsafe GPU Frequencies (Erista)", EditorType::LIST,
|
||||
data.enableEristaGpuUnsafeFreqs,
|
||||
[this, &data](int val) {
|
||||
data.enableEristaGpuUnsafeFreqs = val;
|
||||
if (autoSave && kipHandler) kipHandler->writeKip();
|
||||
setStatus("Erista GPU unsafe: " + std::string(val ? "ENABLED" : "DISABLED"));
|
||||
}, opts);
|
||||
break;
|
||||
}
|
||||
case 5: { // Mariko GPU UV
|
||||
std::vector<std::string> opts = {"UV0 (No Table)", "UV1 (Regular)", "UV2 (High)", "UV3 (Custom)"};
|
||||
showValueEditor("Mariko GPU Undervolt Mode", EditorType::LIST,
|
||||
@@ -418,28 +392,6 @@ void UI::handleCPUMenuInput(u64 kDown) {
|
||||
auto& data = kipHandler->getData();
|
||||
|
||||
switch (selectedIndex) {
|
||||
case 0: { // Mariko CPU Unsafe
|
||||
std::vector<std::string> opts = {"Disabled (0)", "Enabled (1)"};
|
||||
showValueEditor("Enable Unsafe CPU Frequencies (Mariko)", EditorType::LIST,
|
||||
data.enableMarikoCpuUnsafeFreqs,
|
||||
[this, &data](int val) {
|
||||
data.enableMarikoCpuUnsafeFreqs = val;
|
||||
if (autoSave && kipHandler) kipHandler->writeKip();
|
||||
setStatus("Mariko CPU unsafe: " + std::string(val ? "ENABLED" : "DISABLED"));
|
||||
}, opts);
|
||||
break;
|
||||
}
|
||||
case 1: { // Erista CPU Unsafe
|
||||
std::vector<std::string> opts = {"Disabled (0)", "Enabled (1)"};
|
||||
showValueEditor("Enable Unsafe CPU Frequencies (Erista)", EditorType::LIST,
|
||||
data.enableEristaCpuUnsafeFreqs,
|
||||
[this, &data](int val) {
|
||||
data.enableEristaCpuUnsafeFreqs = val;
|
||||
if (autoSave && kipHandler) kipHandler->writeKip();
|
||||
setStatus("Erista CPU unsafe: " + std::string(val ? "ENABLED" : "DISABLED"));
|
||||
}, opts);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
setStatus("Feature in development");
|
||||
break;
|
||||
|
||||
BIN
Source/TimingTool/Downloads.zip
Normal file
BIN
Source/TimingTool/Downloads.zip
Normal file
Binary file not shown.
5
Source/TimingTool/README.md
Normal file
5
Source/TimingTool/README.md
Normal file
@@ -0,0 +1,5 @@
|
||||
# Horizon OC TimingTool
|
||||
|
||||
A simple tool to dump timings from Linux and scale them
|
||||
|
||||
(c) 2025 Souldbminer & Horizon OC Contributors
|
||||
BIN
Source/TimingTool/assets/Lexend.ttf
Normal file
BIN
Source/TimingTool/assets/Lexend.ttf
Normal file
Binary file not shown.
2
Source/TimingTool/build.bat
Normal file
2
Source/TimingTool/build.bat
Normal file
@@ -0,0 +1,2 @@
|
||||
python -m PyInstaller --onefile --add-data "assets;assets" --noconsole src/main.py
|
||||
move "dist\main.exe" "dist\timingtool.exe"
|
||||
38
Source/TimingTool/main.spec
Normal file
38
Source/TimingTool/main.spec
Normal file
@@ -0,0 +1,38 @@
|
||||
# -*- mode: python ; coding: utf-8 -*-
|
||||
|
||||
|
||||
a = Analysis(
|
||||
['src\\main.py'],
|
||||
pathex=[],
|
||||
binaries=[],
|
||||
datas=[('assets', 'assets')],
|
||||
hiddenimports=[],
|
||||
hookspath=[],
|
||||
hooksconfig={},
|
||||
runtime_hooks=[],
|
||||
excludes=[],
|
||||
noarchive=False,
|
||||
optimize=0,
|
||||
)
|
||||
pyz = PYZ(a.pure)
|
||||
|
||||
exe = EXE(
|
||||
pyz,
|
||||
a.scripts,
|
||||
a.binaries,
|
||||
a.datas,
|
||||
[],
|
||||
name='main',
|
||||
debug=False,
|
||||
bootloader_ignore_signals=False,
|
||||
strip=False,
|
||||
upx=True,
|
||||
upx_exclude=[],
|
||||
runtime_tmpdir=None,
|
||||
console=False,
|
||||
disable_windowed_traceback=False,
|
||||
argv_emulation=False,
|
||||
target_arch=None,
|
||||
codesign_identity=None,
|
||||
entitlements_file=None,
|
||||
)
|
||||
1
Source/TimingTool/run.bat
Normal file
1
Source/TimingTool/run.bat
Normal file
@@ -0,0 +1 @@
|
||||
python src/main.py
|
||||
420
Source/TimingTool/src/main.py
Normal file
420
Source/TimingTool/src/main.py
Normal file
@@ -0,0 +1,420 @@
|
||||
"""
|
||||
|
||||
HOC Timing Tool
|
||||
|
||||
Copyright (C) Souldbminer
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
"""
|
||||
|
||||
import zipfile
|
||||
import tempfile
|
||||
from pathlib import Path
|
||||
import re
|
||||
import dearpygui.dearpygui as dpg
|
||||
import numpy as np
|
||||
import os
|
||||
import sys
|
||||
from scipy.signal import savgol_filter
|
||||
|
||||
REGISTER_RE = re.compile(r"^(emc|mc)_[A-Za-z0-9_]+\s+0x[0-9A-Fa-f]+$")
|
||||
if getattr(sys, 'frozen', False):
|
||||
assets_path = os.path.join(sys._MEIPASS, 'assets/')
|
||||
else:
|
||||
assets_path = os.path.join(os.path.dirname(__file__), '../assets/')
|
||||
|
||||
def safe_r2(y, y_fit):
|
||||
ss_res = np.sum((y - y_fit) ** 2)
|
||||
ss_tot = np.sum((y - np.mean(y)) ** 2)
|
||||
if ss_tot == 0:
|
||||
return 0.0
|
||||
return max(0.0, 1 - ss_res / ss_tot)
|
||||
|
||||
def find_inflection_points(x, y):
|
||||
x = np.array(x, dtype=float)
|
||||
y = np.array(y, dtype=float)
|
||||
|
||||
if len(x) < 3:
|
||||
return []
|
||||
|
||||
dx = np.diff(x)
|
||||
dy = np.diff(y)
|
||||
slopes = dy / dx
|
||||
|
||||
slope_changes = np.abs(np.diff(slopes))
|
||||
|
||||
if len(slope_changes) > 0:
|
||||
threshold = np.percentile(slope_changes, 40)
|
||||
else:
|
||||
return []
|
||||
|
||||
inflections = []
|
||||
for i in range(len(slope_changes)):
|
||||
if slope_changes[i] > threshold:
|
||||
inflections.append(i + 1)
|
||||
|
||||
inflections = sorted(set(inflections))
|
||||
|
||||
if len(inflections) < 2 and len(slope_changes) > 0:
|
||||
threshold = np.percentile(slope_changes, 60)
|
||||
inflections = []
|
||||
for i in range(len(slope_changes)):
|
||||
if slope_changes[i] > threshold:
|
||||
inflections.append(i + 1)
|
||||
inflections = sorted(set(inflections))
|
||||
|
||||
return inflections
|
||||
|
||||
def fit_piecewise_segments(x, y, reg_name="register"):
|
||||
x = np.array(x, dtype=float)
|
||||
y = np.array(y, dtype=float)
|
||||
|
||||
if len(x) < 3:
|
||||
return None
|
||||
|
||||
inflections = find_inflection_points(x, y)
|
||||
|
||||
breakpoints = [0] + inflections + [len(x) - 1]
|
||||
breakpoints = sorted(set(breakpoints))
|
||||
|
||||
segments = []
|
||||
thresholds = []
|
||||
slopes = []
|
||||
intercepts = []
|
||||
|
||||
for i in range(len(breakpoints) - 1):
|
||||
start_idx = breakpoints[i]
|
||||
end_idx = breakpoints[i + 1]
|
||||
|
||||
x_seg = x[start_idx:end_idx + 1]
|
||||
y_seg = y[start_idx:end_idx + 1]
|
||||
|
||||
if len(x_seg) < 2:
|
||||
continue
|
||||
|
||||
try:
|
||||
p = np.polyfit(x_seg, y_seg, 1)
|
||||
slope, intercept = p[0], p[1]
|
||||
|
||||
thresholds.append(x[end_idx])
|
||||
slopes.append(slope)
|
||||
intercepts.append(intercept)
|
||||
except Exception:
|
||||
continue
|
||||
|
||||
if not thresholds:
|
||||
return None
|
||||
|
||||
def piecewise(t, thresholds_list=thresholds, slopes_list=slopes, intercepts_list=intercepts):
|
||||
if np.isscalar(t):
|
||||
for thresh, slp, intcpt in zip(thresholds_list, slopes_list, intercepts_list):
|
||||
if t <= thresh:
|
||||
return slp * t + intcpt
|
||||
return slopes_list[-1] * t + intercepts_list[-1]
|
||||
else:
|
||||
result = np.zeros_like(t, dtype=float)
|
||||
for i, ti in enumerate(t):
|
||||
for thresh, slp, intcpt in zip(thresholds_list, slopes_list, intercepts_list):
|
||||
if ti <= thresh:
|
||||
result[i] = slp * ti + intcpt
|
||||
break
|
||||
else:
|
||||
result[i] = slopes_list[-1] * ti + intercepts_list[-1]
|
||||
return result
|
||||
|
||||
y_fit = piecewise(x)
|
||||
r2 = safe_r2(y, y_fit)
|
||||
|
||||
formula_lines = []
|
||||
for i, (thresh, slp, intcpt) in enumerate(zip(thresholds, slopes, intercepts)):
|
||||
if abs(slp) < 1e-6:
|
||||
val_str = f"{intcpt:.0f}"
|
||||
else:
|
||||
slp_simple = round(slp, 4)
|
||||
intcpt_simple = round(intcpt, 0)
|
||||
if slp_simple == int(slp_simple):
|
||||
slp_simple = int(slp_simple)
|
||||
if intcpt_simple >= 0:
|
||||
val_str = f"{slp_simple} * x + {intcpt_simple}"
|
||||
else:
|
||||
val_str = f"{slp_simple} * x - {abs(intcpt_simple)}"
|
||||
|
||||
if i == len(thresholds) - 1:
|
||||
formula_lines.append(f" return {val_str};")
|
||||
else:
|
||||
formula_lines.append(f" if (x <= {thresh:.0f}) return {val_str};")
|
||||
|
||||
formula = "float timing(float x) {\n" + "\n".join(formula_lines) + "\n}"
|
||||
|
||||
advanced_lines = []
|
||||
max_freq = max(x) if len(x) > 0 else 0
|
||||
|
||||
for i, (thresh, slp, intcpt) in enumerate(zip(thresholds, slopes, intercepts)):
|
||||
if abs(slp) < 1e-6:
|
||||
val = f"{intcpt:.0f}"
|
||||
else:
|
||||
slp_simple = round(slp, 4)
|
||||
intcpt_simple = round(intcpt, 0)
|
||||
if slp_simple == int(slp_simple):
|
||||
slp_simple = int(slp_simple)
|
||||
if intcpt_simple >= 0:
|
||||
val = f"({slp_simple} * freq + {intcpt_simple})"
|
||||
else:
|
||||
val = f"({slp_simple} * freq - {abs(intcpt_simple)})"
|
||||
|
||||
if thresh >= max_freq - 1:
|
||||
advanced_lines.append(f"WRITE_ALL_PARAM_REG(EMC_{reg_name}, {val});")
|
||||
elif i == 0:
|
||||
advanced_lines.append(f"if (freq <= {thresh:.0f}) {{")
|
||||
advanced_lines.append(f" WRITE_ALL_PARAM_REG(EMC_{reg_name}, {val});")
|
||||
advanced_lines.append("}")
|
||||
else:
|
||||
advanced_lines.append(f"else if (freq <= {thresh:.0f}) {{")
|
||||
advanced_lines.append(f" WRITE_ALL_PARAM_REG(EMC_{reg_name}, {val});")
|
||||
advanced_lines.append("}")
|
||||
|
||||
advanced_formula = "\n".join(advanced_lines)
|
||||
|
||||
return {
|
||||
'fn': piecewise,
|
||||
'formula': formula,
|
||||
'advanced_formula': advanced_formula,
|
||||
'r2': r2,
|
||||
'thresholds': thresholds,
|
||||
'slopes': slopes,
|
||||
'intercepts': intercepts,
|
||||
'reg_name': reg_name
|
||||
}
|
||||
|
||||
|
||||
def parse_dump_file(path: Path):
|
||||
registers = {}
|
||||
try:
|
||||
for line in path.read_text(errors="ignore").splitlines():
|
||||
line = line.strip()
|
||||
if not line or line.startswith("#"):
|
||||
continue
|
||||
parts = line.split()
|
||||
if len(parts) < 2:
|
||||
continue
|
||||
name, val = parts[0], parts[-1]
|
||||
if not (name.lower().startswith("emc_") or name.lower().startswith("mc_")):
|
||||
continue
|
||||
if not val.startswith("0x"):
|
||||
continue
|
||||
try:
|
||||
registers[name] = int(val, 16)
|
||||
except ValueError:
|
||||
pass
|
||||
except Exception:
|
||||
pass
|
||||
return registers
|
||||
|
||||
|
||||
def analyze_zip(zip_path: Path):
|
||||
tmpdir = Path(tempfile.mkdtemp(prefix="timingtool_extract_"))
|
||||
with zipfile.ZipFile(zip_path, "r") as z:
|
||||
z.extractall(tmpdir)
|
||||
|
||||
results = {}
|
||||
for base_dir in tmpdir.iterdir():
|
||||
if not base_dir.is_dir():
|
||||
continue
|
||||
base_latency = base_dir.name
|
||||
results.setdefault(base_latency, {"mc": {}, "emc": {}})
|
||||
|
||||
for typ in ("mc", "emc"):
|
||||
folder = base_dir / typ
|
||||
if not folder.exists():
|
||||
continue
|
||||
for dump in folder.glob("*.txt"):
|
||||
m = re.search(r"(\d+)", dump.name)
|
||||
if not m:
|
||||
continue
|
||||
freq = int(m.group(1))
|
||||
registers = parse_dump_file(dump)
|
||||
for reg, val in registers.items():
|
||||
results[base_latency][typ].setdefault(reg, {})[freq] = val
|
||||
|
||||
return results
|
||||
|
||||
|
||||
|
||||
dpg.create_context()
|
||||
dpg.create_viewport(title="Horizon OC Timing Tool", width=1920, height=1080)
|
||||
dpg.maximize_viewport()
|
||||
|
||||
with dpg.font_registry():
|
||||
lexend = dpg.add_font(assets_path + "Lexend.ttf", 16)
|
||||
|
||||
with dpg.window(label="HOC Timing Tool", width=1920, height=1080, tag="main_window"):
|
||||
with dpg.tab_bar(tag="root_tabs"):
|
||||
with dpg.tab(label=" File", tag="file_tab"):
|
||||
dpg.add_text("Timing Analyzer\nSelect a ZIP file structured as:\n<base_latency>/<mc|emc>/<freq>_mc.txt")
|
||||
dpg.add_button(label="Select ZIP File...", callback=lambda s,a: dpg.show_item("file_dialog"))
|
||||
dpg.add_separator()
|
||||
dpg.add_text("Status:")
|
||||
dpg.add_text("Waiting...", tag="status_text")
|
||||
|
||||
with dpg.tab(label="Graphs", tag="graph_tab"):
|
||||
with dpg.tab_bar(tag="main_tabs"):
|
||||
dpg.add_tab(label="No Data", tag="placeholder_tab")
|
||||
|
||||
with dpg.tab(label="Code", tag="code_tab"):
|
||||
with dpg.tab_bar(tag="code_tabs"):
|
||||
dpg.add_tab(label="No Data", tag="code_placeholder_tab")
|
||||
|
||||
|
||||
def handle_file_selection(sender, app_data):
|
||||
if not app_data["selections"]:
|
||||
return
|
||||
zip_path = list(app_data["selections"].values())[0]
|
||||
dpg.set_value("status_text", f"Analyzing {zip_path} ...")
|
||||
try:
|
||||
data = analyze_zip(Path(zip_path))
|
||||
except Exception as e:
|
||||
dpg.set_value("status_text", f"Error: {e}")
|
||||
return
|
||||
|
||||
dpg.delete_item("main_tabs", children_only=True)
|
||||
|
||||
if not data:
|
||||
dpg.add_tab(label="No valid data", parent="main_tabs")
|
||||
dpg.set_value("status_text", "No valid data found in ZIP.")
|
||||
return
|
||||
|
||||
dpg.delete_item("code_tabs", children_only=True)
|
||||
|
||||
for base_latency, lat_data in sorted(data.items()):
|
||||
with dpg.tab(label=f"{base_latency}bl", parent="main_tabs"):
|
||||
with dpg.tab_bar():
|
||||
for typ in ("mc", "emc"):
|
||||
with dpg.tab(label=typ.upper()):
|
||||
if not lat_data[typ]:
|
||||
dpg.add_text(f"No {typ.upper()} data.")
|
||||
continue
|
||||
|
||||
search_tag = f"search_{base_latency}_{typ}"
|
||||
dpg.add_input_text(label="Search Timings", tag=search_tag, width=500)
|
||||
|
||||
with dpg.child_window(width=-1, height=850, horizontal_scrollbar=True) as scroll_area:
|
||||
for reg_name, freq_map in sorted(lat_data[typ].items()):
|
||||
freqs = sorted(freq_map.keys())
|
||||
vals = [freq_map[f] for f in freqs]
|
||||
if len(freqs) < 2:
|
||||
continue
|
||||
|
||||
x = np.array(freqs, dtype=float)
|
||||
y = np.array(vals, dtype=float)
|
||||
|
||||
fit_result = fit_piecewise_segments(x, y, reg_name)
|
||||
|
||||
if fit_result is None:
|
||||
continue
|
||||
|
||||
plot_tag = f"{base_latency}_{typ}_{reg_name}_plot"
|
||||
container_tag = f"{plot_tag}_container"
|
||||
dropdown_tag = f"{plot_tag}_dropdown"
|
||||
value_tag = f"{plot_tag}_value"
|
||||
|
||||
with dpg.group(tag=container_tag):
|
||||
with dpg.plot(label=reg_name, height=250, width=-1):
|
||||
dpg.add_plot_legend()
|
||||
dpg.add_plot_axis(dpg.mvXAxis, label="Frequency (MHz)")
|
||||
y_axis = dpg.add_plot_axis(dpg.mvYAxis, label="Register")
|
||||
dpg.add_line_series(freqs, vals, label="Data", parent=y_axis)
|
||||
|
||||
fit_x = np.linspace(min(freqs), max(freqs), 100)
|
||||
fit_y = fit_result['fn'](fit_x)
|
||||
dpg.add_line_series(fit_x, fit_y, label=f"Fit (R²={fit_result['r2']:.3f})", parent=y_axis)
|
||||
|
||||
dpg.add_text(f"R² = {fit_result['r2']:.4f}", color=(100, 200, 100))
|
||||
|
||||
with dpg.tab_bar():
|
||||
with dpg.tab(label="Timing Function"):
|
||||
dpg.add_input_text(default_value=fit_result['formula'], readonly=True, width=-1, height=150, multiline=True, tag=f"{container_tag}_formula")
|
||||
with dpg.tab(label="Register Write"):
|
||||
dpg.add_input_text(default_value=fit_result['advanced_formula'], readonly=True, width=-1, height=150, multiline=True, tag=f"{container_tag}_advanced")
|
||||
|
||||
def make_freq_callback(freq_map, val_tag):
|
||||
def _callback(sender, app_data):
|
||||
freq = int(app_data)
|
||||
val = freq_map.get(freq)
|
||||
if val is not None:
|
||||
dpg.set_value(val_tag, f"Value: 0x{val:08X} ({val})")
|
||||
else:
|
||||
dpg.set_value(val_tag, "Value: N/A")
|
||||
return _callback
|
||||
|
||||
dpg.add_combo(
|
||||
items=[str(f) for f in freqs],
|
||||
label="Select Frequency",
|
||||
default_value=str(freqs[0]),
|
||||
width=150,
|
||||
callback=make_freq_callback(freq_map, value_tag),
|
||||
tag=dropdown_tag
|
||||
)
|
||||
dpg.add_text(f"Value: 0x{vals[0]:08X} ({vals[0]})", tag=value_tag)
|
||||
|
||||
def make_filter_closure(scroll_area, search_tag, lat_data=lat_data[typ], base=base_latency, t=typ):
|
||||
def _filter(sender, app_data):
|
||||
query = app_data.strip().lower()
|
||||
for reg_name in lat_data.keys():
|
||||
container_tag = f"{base}_{t}_{reg_name}_plot_container"
|
||||
visible = query in reg_name.lower() if query else True
|
||||
if dpg.does_item_exist(container_tag):
|
||||
dpg.configure_item(container_tag, show=visible)
|
||||
return _filter
|
||||
|
||||
dpg.set_item_callback(search_tag, make_filter_closure(scroll_area, search_tag))
|
||||
|
||||
for base_latency, lat_data in sorted(data.items()):
|
||||
code_content = ""
|
||||
with dpg.tab(label=f"{base_latency}bl", parent="code_tabs"):
|
||||
with dpg.tab_bar():
|
||||
for typ in ("mc", "emc"):
|
||||
with dpg.tab(label=typ.upper()):
|
||||
typ_code = ""
|
||||
if lat_data[typ]:
|
||||
for reg_name, freq_map in sorted(lat_data[typ].items()):
|
||||
freqs = sorted(freq_map.keys())
|
||||
vals = [freq_map[f] for f in freqs]
|
||||
if len(freqs) < 2:
|
||||
continue
|
||||
|
||||
x = np.array(freqs, dtype=float)
|
||||
y = np.array(vals, dtype=float)
|
||||
fit_result = fit_piecewise_segments(x, y, reg_name)
|
||||
|
||||
if fit_result:
|
||||
typ_code += fit_result['advanced_formula'] + "\n\n"
|
||||
|
||||
if typ_code:
|
||||
dpg.add_input_text(default_value=typ_code, readonly=True, width=-1, height=-1, multiline=True)
|
||||
else:
|
||||
dpg.add_text(f"No {typ.upper()} data.")
|
||||
|
||||
dpg.set_value("status_text", "Done.")
|
||||
|
||||
|
||||
with dpg.file_dialog(directory_selector=False, show=False, callback=handle_file_selection, tag="file_dialog", width=500, height=300, modal=True):
|
||||
dpg.add_file_extension(".zip")
|
||||
|
||||
dpg.set_primary_window("main_window", True)
|
||||
|
||||
dpg.bind_font(lexend)
|
||||
dpg.setup_dearpygui()
|
||||
dpg.show_viewport()
|
||||
dpg.start_dearpygui()
|
||||
dpg.destroy_context()
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/1600_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/1600_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000060
|
||||
EMC_RFC_0 = 0x000001C0
|
||||
EMC_RAS_0 = 0x00000044
|
||||
EMC_RP_0 = 0x0000001D
|
||||
EMC_R2W_0 = 0x00000029
|
||||
EMC_W2R_0 = 0x00000021
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000001D
|
||||
EMC_WR_RCD_0 = 0x0000001D
|
||||
EMC_RRD_0 = 0x00000010
|
||||
EMC_REXT_0 = 0x00000017
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x0006000C
|
||||
EMC_QSAFE_0 = 0x00000033
|
||||
EMC_RDV_0 = 0x00000039
|
||||
EMC_REFRESH_0 = 0x00001820
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000010
|
||||
EMC_PDEX2RD_0 = 0x00000010
|
||||
EMC_PCHG2PDEN_0 = 0x00000003
|
||||
EMC_ACT2PDEN_0 = 0x00000017
|
||||
EMC_AR2PDEN_0 = 0x00000003
|
||||
EMC_RW2PDEN_0 = 0x00000038
|
||||
EMC_TXSR_0 = 0x000001CC
|
||||
EMC_TCKE_0 = 0x0000000D
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x00000022
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x00000014
|
||||
EMC_TREFBW_0 = 0x00001860
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000002E
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x01900017
|
||||
EMC_MRS_WAIT_CNT_0 = 0x0640002F
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012C0DC
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x0000000E
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0000
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000018
|
||||
EMC_TPD_0 = 0x0000000C
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x00110835
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003B
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000039
|
||||
EMC_RDV_EARLY_0 = 0x00000037
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x00310640
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186190
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000039
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000608
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000308C
|
||||
EMC_TXSRDLL_0 = 0x000001CC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002B
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003B
|
||||
EMC_TR_QSAFE_0 = 0x00000033
|
||||
EMC_TR_QRST_0 = 0x0006000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0B09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x00000008
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC4204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x001F0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x2E2F2F2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2B292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2B2E2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x32323333
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x2F313228
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x252C2D2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A292623
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2C2F2D2E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353134
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2F2E2A2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2D29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232527
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272325
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x070A070A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/1866_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/1866_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000070
|
||||
EMC_RFC_0 = 0x0000020B
|
||||
EMC_RAS_0 = 0x0000004F
|
||||
EMC_RP_0 = 0x00000022
|
||||
EMC_R2W_0 = 0x0000002A
|
||||
EMC_W2R_0 = 0x00000022
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000022
|
||||
EMC_WR_RCD_0 = 0x00000022
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070008
|
||||
EMC_QSAFE_0 = 0x00000034
|
||||
EMC_RDV_0 = 0x0000003A
|
||||
EMC_REFRESH_0 = 0x00001C2D
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000013
|
||||
EMC_PDEX2RD_0 = 0x00000013
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001B
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x00000219
|
||||
EMC_TCKE_0 = 0x00000010
|
||||
EMC_TFAW_0 = 0x0000004B
|
||||
EMC_TRPAB_0 = 0x00000028
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x00000017
|
||||
EMC_TREFBW_0 = 0x00001C6D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000037
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x01D3001B
|
||||
EMC_MRS_WAIT_CNT_0 = 0x074A0030
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122A40
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000010
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x00000020
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000001C
|
||||
EMC_TPD_0 = 0x0000000E
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003C
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003A
|
||||
EMC_RDV_EARLY_0 = 0x00000038
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x0039074A
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011861D3
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003A
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000070B
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80003873
|
||||
EMC_TXSRDLL_0 = 0x00000219
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002C
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003C
|
||||
EMC_TR_QSAFE_0 = 0x00000034
|
||||
EMC_TR_QRST_0 = 0x00070008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030A
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002C
|
||||
EMC_QUSE_WIDTH_0 = 0x00000009
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000106
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0009000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00100007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0009000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00100007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00090000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00090000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001F0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x393A3A3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x39353337
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000038
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x37393737
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x35393235
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000034
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x3E3C3E3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3A3C3F32
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x30363736
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x35342F2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x373B393B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x383B3838
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x37353737
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000036
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x42424341
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x3F413D3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3A393436
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x37353833
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000035
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04060506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05070307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060809
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02020303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020101
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040203
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03030200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242526
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x2B262822
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00100010
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080F
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000403A5
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2133_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2133_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000080
|
||||
EMC_RFC_0 = 0x00000256
|
||||
EMC_RAS_0 = 0x0000005A
|
||||
EMC_RP_0 = 0x00000027
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000025
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000027
|
||||
EMC_WR_RCD_0 = 0x00000027
|
||||
EMC_RRD_0 = 0x00000010
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000035
|
||||
EMC_RDV_0 = 0x0000003B
|
||||
EMC_REFRESH_0 = 0x0000203F
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000016
|
||||
EMC_PDEX2RD_0 = 0x00000016
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001E
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x00000266
|
||||
EMC_TCKE_0 = 0x00000012
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x0000002D
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x0000207F
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000003F
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0216001E
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000020
|
||||
EMC_TPD_0 = 0x00000010
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003D
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003B
|
||||
EMC_RDV_EARLY_0 = 0x00000039
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186216
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003B
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000080F
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004062
|
||||
EMC_TXSRDLL_0 = 0x00000266
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002D
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003D
|
||||
EMC_TR_QSAFE_0 = 0x00000035
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002D
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000012B
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000A0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000A0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00250025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x45454546
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x43403E43
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x42444241
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3F443C3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49474A49
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x4548493C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x38404140
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3E3D3934
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050304
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x00060102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x413F4041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4141413E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0E0E0F0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0B0D080B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x44433E40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x413E433D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03070706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x060A0409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0708090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050507
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06020401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27262629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27292629
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004042B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2166_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2166_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000082
|
||||
EMC_RFC_0 = 0x0000025F
|
||||
EMC_RAS_0 = 0x0000005B
|
||||
EMC_RP_0 = 0x00000027
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000025
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000027
|
||||
EMC_WR_RCD_0 = 0x00000027
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070006
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x000020BF
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x0000026F
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000041
|
||||
EMC_TRPAB_0 = 0x0000002E
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x000020FF
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000040
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x021E001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012AFC4
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118621E
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000082F
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000415D
|
||||
EMC_TXSRDLL_0 = 0x0000026F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000130
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x8C200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x47474747
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x45413F45
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000045
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x44464342
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x41463E40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49484A4A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x46484A3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x39414242
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x403E3A36
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x01060306
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060202
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x42414142
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4241423F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0E0F100E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0C0E090C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x46443F41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4340443D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0807090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050101
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01030002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04020100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25232828
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29282623
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004043B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2200_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2200_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000084
|
||||
EMC_RFC_0 = 0x00000268
|
||||
EMC_RAS_0 = 0x0000005D
|
||||
EMC_RP_0 = 0x00000028
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000025
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000028
|
||||
EMC_WR_RCD_0 = 0x00000028
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070006
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x00002144
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000039
|
||||
EMC_TXSR_0 = 0x00000279
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000042
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002184
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000041
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0226001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80129FB3
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186226
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000851
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000425F
|
||||
EMC_TXSRDLL_0 = 0x00000279
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x0000024A
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000134
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x8C200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0021002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x07080707
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06020005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x46474543
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x42473F41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4B494C4C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x474A4B3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B434443
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x41403B37
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x03080507
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x04090405
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020300
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1111120F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0E0F0B0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x47454042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4441453F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0807090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272624
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004044C
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2233_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2233_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000086
|
||||
EMC_RFC_0 = 0x00000272
|
||||
EMC_RAS_0 = 0x0000005E
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000026
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x000021C5
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x00000282
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000043
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002205
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x022F0020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118622F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000871
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000435A
|
||||
EMC_TXSRDLL_0 = 0x00000282
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000252
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000139
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x08090809
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06030106
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06080605
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080103
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4D4B4E4E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x494D4E3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000004A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B444544
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x42413C38
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x05090608
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x05090505
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05030405
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x11131310
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0F110C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08080104
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020601
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2725272A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282625
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004045D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2266_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2266_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000088
|
||||
EMC_RFC_0 = 0x0000027B
|
||||
EMC_RAS_0 = 0x00000060
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x0000002B
|
||||
EMC_W2R_0 = 0x00000026
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000036
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x00002245
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x0000028C
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000044
|
||||
EMC_TRPAB_0 = 0x00000030
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x00002285
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02370020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x88010054
|
||||
EMC_MRR_0 = 0x8012768A
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00C0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186237
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000891
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004455
|
||||
EMC_TXSRDLL_0 = 0x0000028C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000036
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0F0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000013E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0B0A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x08040207
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x07090806
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x040A0203
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0E0C0F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0E0F00
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3C454745
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2B2A2723
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x050A0709
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060B0607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050502
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x13141512
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x11120E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09080305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040702
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x03020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282525
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004046D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2300_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2300_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008A
|
||||
EMC_RFC_0 = 0x00000284
|
||||
EMC_RAS_0 = 0x00000061
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000026
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070004
|
||||
EMC_QSAFE_0 = 0x00000037
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x000022CA
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x00000296
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000045
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000230A
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x023F0021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80125E72
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000D
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118623F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008B2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004558
|
||||
EMC_TXSRDLL_0 = 0x00000296
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000037
|
||||
EMC_TR_QRST_0 = 0x00070004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000142
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x22004120
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0B0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0A050309
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090A0807
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060B0305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0F0E1011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0C0F1002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3D464746
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x44433E3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x070C090B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x070C0708
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x07060704
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x14151613
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x11130F10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0B0A0406
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08060903
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A0409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252828
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272726
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2333_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2333_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008C
|
||||
EMC_RFC_0 = 0x0000028E
|
||||
EMC_RAS_0 = 0x00000062
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x00070003
|
||||
EMC_QSAFE_0 = 0x00000038
|
||||
EMC_RDV_0 = 0x0000003C
|
||||
EMC_REFRESH_0 = 0x0000234B
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x0000029F
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000046
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000238B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02480021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80124B5F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003E
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||
EMC_RDV_EARLY_0 = 0x0000003A
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186248
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003C
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008D2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004653
|
||||
EMC_TXSRDLL_0 = 0x0000029F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002E
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||
EMC_TR_QSAFE_0 = 0x00000038
|
||||
EMC_TR_QRST_0 = 0x00070003
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002E
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000147
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0C0B0C0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x09060509
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0B0A09
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x080C0506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x100F1212
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0D101102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3F484948
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4544403B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x080E0A0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x090E0909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x08070808
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x09080805
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x16161815
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x13151012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0C0B0507
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08060A04
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03040506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040B030B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624292A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29262529
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004048F
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2366_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2366_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008E
|
||||
EMC_RFC_0 = 0x00000297
|
||||
EMC_RAS_0 = 0x00000064
|
||||
EMC_RP_0 = 0x0000002B
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002B
|
||||
EMC_WR_RCD_0 = 0x0000002B
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x0006000C
|
||||
EMC_QSAFE_0 = 0x00000037
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x000023CB
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002A9
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000047
|
||||
EMC_TRPAB_0 = 0x00000032
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x0000240B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000046
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02500022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122A41
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186250
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008F2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000474E
|
||||
EMC_TXSRDLL_0 = 0x000002A9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000037
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000014C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A00A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0D0D0D0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B07050B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0C0D0B0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x090E0608
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x11111413
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0F121304
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x404A4A49
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4746413C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000044
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A0E0C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0A0F0A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0A080A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0A090A06
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x17181916
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x14161213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0C0708
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0B070C05
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05030104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26242429
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262325
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004049F
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2400_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2400_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000090
|
||||
EMC_RFC_0 = 0x000002A0
|
||||
EMC_RAS_0 = 0x00000065
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00070005
|
||||
EMC_QSAFE_0 = 0x00000037
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x00002450
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002B2
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000048
|
||||
EMC_TRPAB_0 = 0x00000033
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002490
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000047
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02580022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122D40
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186258
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000914
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004850
|
||||
EMC_TXSRDLL_0 = 0x000002B2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000037
|
||||
EMC_TR_QRST_0 = 0x00070005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0C
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000150
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0E100F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0E0A080D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0D0F0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x12121514
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x10131405
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4747423D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000045
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A100C0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0A090B0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0B0A0A08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x18191A17
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16171315
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0D080A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0B090C07
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B030B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624292A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404B0
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0C
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2433_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2433_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000092
|
||||
EMC_RFC_0 = 0x000002AA
|
||||
EMC_RAS_0 = 0x00000067
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00070004
|
||||
EMC_QSAFE_0 = 0x00000038
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x000024D1
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002BC
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x00000049
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002511
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000048
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02610023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012283F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000D
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186261
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000000
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000934
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000494B
|
||||
EMC_TXSRDLL_0 = 0x000002BC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000038
|
||||
EMC_TR_QRST_0 = 0x00070004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000155
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x10111010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0E0A080E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0E100E0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0B10080A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x14131516
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x10131505
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x414B4D4B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4848433E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000046
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0B100D0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0B100B0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0C0A0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1C18
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16181416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x110E090A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0D0A0E08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040B040B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02080006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27242927
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282729
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x00000000
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2466_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2466_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000094
|
||||
EMC_RFC_0 = 0x000002B3
|
||||
EMC_RAS_0 = 0x00000068
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x0000002C
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00070004
|
||||
EMC_QSAFE_0 = 0x00000038
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x00002551
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002C5
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004A
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002591
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02690023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80120215
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000D
|
||||
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186190
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000954
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004A46
|
||||
EMC_TXSRDLL_0 = 0x000002C5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000038
|
||||
EMC_TR_QRST_0 = 0x00070004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001D
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0C
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015A
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x11131011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2E2B292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10120F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x20221E20
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x15141616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x11151607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x434C4D4C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4A49443F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0C110E10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0C110C0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0E0C0E0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0D0D0E0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1C19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x171A1517
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x12100A0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0E0C0F08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080906
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B040B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28292726
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404D1
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0C
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2500_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2500_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000096
|
||||
EMC_RFC_0 = 0x000002BC
|
||||
EMC_RAS_0 = 0x00000069
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00070003
|
||||
EMC_QSAFE_0 = 0x00000039
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x000025D6
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002CF
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004B
|
||||
EMC_TRPAB_0 = 0x00000035
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002616
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02710023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012F002
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000028
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186271
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000975
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004B49
|
||||
EMC_TXSRDLL_0 = 0x000002CF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x00000039
|
||||
EMC_TR_QRST_0 = 0x00070003
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x13141313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x110C0A10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x11130F10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0E130B0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x16151718
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x30323328
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0B0A0500
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0E121012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0E130E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0F0D0E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0F0E0E0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1B1C1E1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x191A1617
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14110B0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0F0C100A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0806090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040208
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624232A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292626
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404E2
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2533_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2533_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000098
|
||||
EMC_RFC_0 = 0x000002C6
|
||||
EMC_RAS_0 = 0x0000006B
|
||||
EMC_RP_0 = 0x0000002E
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002E
|
||||
EMC_WR_RCD_0 = 0x0000002E
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000025
|
||||
EMC_QRST_0 = 0x00080001
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x0000003D
|
||||
EMC_REFRESH_0 = 0x00002657
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002D9
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004C
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002697
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004A
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x027A0024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000B
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003F
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||
EMC_RDV_EARLY_0 = 0x0000003B
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118627A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003D
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000995
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004C44
|
||||
EMC_TXSRDLL_0 = 0x000002D9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002F
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080001
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001B
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002F
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000163
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A00A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00060000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0021
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x14151414
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x120E0B11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x12141111
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0F140C0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1817191A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x15181909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x040F100E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2B2A2723
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0F141113
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0F150F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x100F1010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x100F100C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1E1E1F1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1A1D181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14120D0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x100E120B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00040505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08030503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242428
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25292825
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404F3
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2566_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2566_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009A
|
||||
EMC_RFC_0 = 0x000002CF
|
||||
EMC_RAS_0 = 0x0000006C
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080002
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x000026D7
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002E2
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004D
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002717
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02820024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012D4E6
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186282
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009B5
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004D3F
|
||||
EMC_TXSRDLL_0 = 0x000002E2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080002
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000168
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x15151416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x130F0C13
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x13161312
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x10160D0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x19191B1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x16191A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0610110F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0D0C0702
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x10151214
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x10161011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x110F1113
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1110110E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1D1F211C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1B1D181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x15140E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x110F120B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08060307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27232629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28262425
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2600_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2600_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009C
|
||||
EMC_RFC_0 = 0x000002D8
|
||||
EMC_RAS_0 = 0x0000006E
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080002
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x0000275C
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002EC
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004E
|
||||
EMC_TRPAB_0 = 0x00000037
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000279C
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x028A0025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118628A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009D7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004E41
|
||||
EMC_TXSRDLL_0 = 0x000002EC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080002
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000016C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x16161515
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x140F0E14
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x15161414
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x11170E11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1B1A1C1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x171A1C0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x07111311
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0F0E0903
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x12181416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x12181213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x12111213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353234
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x17160F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020203
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26232528
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040514
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2633_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2633_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009E
|
||||
EMC_RFC_0 = 0x000002E2
|
||||
EMC_RAS_0 = 0x0000006F
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x0000002A
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080001
|
||||
EMC_QSAFE_0 = 0x0000003D
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x000027DD
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002F5
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004F
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000281D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02930025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012B1C2
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000B
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186293
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009F7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004F3C
|
||||
EMC_TXSRDLL_0 = 0x000002F5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003D
|
||||
EMC_TR_QRST_0 = 0x00080001
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000171
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x18181818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x16120F15
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x16181615
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x12180F12
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1C1C1D1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191C1D0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x08121311
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0F0E0A04
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x12171417
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x13181314
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x13121315
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1312130F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2021231F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1E201A1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x17161011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1411150E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A0A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070E0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x090A0300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08070408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03010101
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2A222428
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x23272726
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040525
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2666_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/emc/2666_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A0
|
||||
EMC_RFC_0 = 0x000002EB
|
||||
EMC_RAS_0 = 0x00000070
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x0000002D
|
||||
EMC_W2R_0 = 0x0000002A
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000026
|
||||
EMC_QRST_0 = 0x00080001
|
||||
EMC_QSAFE_0 = 0x0000003D
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x0000285D
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000026
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x0000003A
|
||||
EMC_TXSR_0 = 0x000002FF
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x00000050
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000289D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x029B0026
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012A5B6
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000B
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118629B
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A17
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005037
|
||||
EMC_TXSRDLL_0 = 0x000002FF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x0000003D
|
||||
EMC_TR_QRST_0 = 0x00080001
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000000
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000176
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x19191818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x17121016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x18191616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323433
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191D1F0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x09141513
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x11100B05
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x131A1618
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x14191516
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x15141516
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x14141511
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x20221C1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x19171113
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1412160F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B050B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0E
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01090B09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090508
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0306050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05040301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24242628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262827
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040535
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/1600_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/1600_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DEB251
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000C
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000006
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000D080C
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726C2419
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C511020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80100080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A930850
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000228
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000080
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080016
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/1866_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/1866_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x4A005160
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x75C5BF41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000E
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000E090E
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726E2A1D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02013000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000041
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x000000F2
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000335
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001B
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00001501
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x006D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x006D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x006D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x006D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x006D006D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x006D0019
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x006D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x006D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x006D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x006D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x006D0016
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000006D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x006D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x006D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000006D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080013
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x006D0016
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x006D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x006D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2133_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2133_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD0B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E72431
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80050080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000F0A10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72703021
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00600004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00600038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00600005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00600014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00600060
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00600016
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00600095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00600041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00600080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0060003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00600013
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000060
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00600090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00600004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000060
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080011
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00600013
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00600005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00600018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2166_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2166_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD8B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E3E631
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000F0A10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713121
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004B
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005E005E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005E0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2200_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2200_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D49341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713222
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02910800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005D005D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005D0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2233_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2233_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01011200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E3F551
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80040080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713322
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004E
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005B0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005B0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005B005B
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005B0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005B0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005B0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005B0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005B003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005B
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005B0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005B
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005B0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2266_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2266_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDBB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E6F6D1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713323
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004F
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005A005A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2300_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2300_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E4C761
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723423
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000050
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00590038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00590059
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00590095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00590041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00590080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0059003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000059
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00590090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000059
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00590018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2333_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2333_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x00000000
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC1B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E44061
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723523
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02000000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000051
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00570038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00570057
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00570095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00570041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00570080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0057003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000057
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00570090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000057
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00570011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00570018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2366_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2366_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCEB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E38391
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000023
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723624
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C151000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000052
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00560038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00560014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00560056
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00560013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00560095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00560041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00560080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0056003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000056
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00560090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000056
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00560018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2400_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2400_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77CDF531
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723625
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A110000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000053
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00550038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00550014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00550055
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00550013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00550095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00550041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00550080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0055003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000055
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00550090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000055
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00550018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2433_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2433_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01010200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000007F
|
||||
MC_SMMU_PTB_DATA_0 = 0x00000000
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDFB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7A41F7E1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733725
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000C0800
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8800
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1910A0
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000055
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000120
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000120
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x00000000
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000E
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00540038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00540014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00540054
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00540013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00540095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00540041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00540080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0054003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000054
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00540090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000054
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00540018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2466_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2466_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCFB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E273C1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80040080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733826
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000056
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00530038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00530014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00530053
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00530013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00530095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00530041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00530080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0053003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000053
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00530090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000053
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00530018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2500_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2500_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC6B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D351A1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x800C0080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733926
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02910800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000057
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00510038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00510014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00510051
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00510012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00510095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00510041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00510080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0051003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000051
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00510090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000051
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00510018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2533_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2533_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DCA341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733927
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00023070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000058
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00500038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00500014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00500050
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00500012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00500095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00500041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00500080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0050003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000050
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00500090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000050
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00500018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2566_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2566_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E72341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743A27
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02110000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000059
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004F0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004F0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004F004F
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004F0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004F0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004F0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004F0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004F003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004F
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004F0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004F
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004F0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2600_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2600_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E74541
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743B28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004E004E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004E0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004E0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2633_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2633_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0xF4028180
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD3B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E8C4C1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80070080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A930850
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004D004D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004D0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2666_mc.txt
Normal file
288
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1600/mc/2666_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x4225CF41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005D
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004C0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004C0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004C0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004C0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004C004C
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004C0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004C0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004C0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004C0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004C003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004C000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004C
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004C0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004C0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004C
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004C000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004C0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004C0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/1866_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/1866_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000070
|
||||
EMC_RFC_0 = 0x0000020B
|
||||
EMC_RAS_0 = 0x0000004F
|
||||
EMC_RP_0 = 0x00000022
|
||||
EMC_R2W_0 = 0x0000002E
|
||||
EMC_W2R_0 = 0x00000025
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000022
|
||||
EMC_WR_RCD_0 = 0x00000022
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000028
|
||||
EMC_QRST_0 = 0x0007000C
|
||||
EMC_QSAFE_0 = 0x00000038
|
||||
EMC_RDV_0 = 0x0000003E
|
||||
EMC_REFRESH_0 = 0x00001C2D
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000013
|
||||
EMC_PDEX2RD_0 = 0x00000013
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001B
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003F
|
||||
EMC_TXSR_0 = 0x00000219
|
||||
EMC_TCKE_0 = 0x00000010
|
||||
EMC_TFAW_0 = 0x0000004B
|
||||
EMC_TRPAB_0 = 0x00000028
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x00000017
|
||||
EMC_TREFBW_0 = 0x00001C6D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000037
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x01D3001B
|
||||
EMC_MRS_WAIT_CNT_0 = 0x074A0034
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000010
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000015
|
||||
EMC_EINPUT_DURATION_0 = 0x00000020
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000001C
|
||||
EMC_TPD_0 = 0x0000000E
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000040
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||
EMC_RDV_EARLY_0 = 0x0000003C
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x0039074A
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011861D3
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003E
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000070B
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80003873
|
||||
EMC_TXSRDLL_0 = 0x00000219
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000030
|
||||
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||
EMC_TR_QSAFE_0 = 0x00000038
|
||||
EMC_TR_QRST_0 = 0x0007000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030A
|
||||
EMC_IBDLY_0 = 0x1000001F
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000030
|
||||
EMC_QUSE_WIDTH_0 = 0x00000009
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000106
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0009000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00100007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0009000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00100007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00090000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00090000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001F0023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x31323332
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x312E2C30
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2F302E2E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2D312A2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x37363837
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3436372B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000035
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x282F302F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2D2D2925
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000002A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x20242123
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2F333030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2F2E2E2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2E2E2E2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x3A3A3B39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x38393638
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000035
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x31312D2E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x302E312C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04060506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05070307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00030205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040106
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000203
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00030002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04030201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25202726
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272322
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00070007
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00100010
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080F
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000403A5
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2133_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2133_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000080
|
||||
EMC_RFC_0 = 0x00000256
|
||||
EMC_RAS_0 = 0x0000005A
|
||||
EMC_RP_0 = 0x00000027
|
||||
EMC_R2W_0 = 0x0000002F
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000027
|
||||
EMC_WR_RCD_0 = 0x00000027
|
||||
EMC_RRD_0 = 0x00000010
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000028
|
||||
EMC_QRST_0 = 0x00070009
|
||||
EMC_QSAFE_0 = 0x00000039
|
||||
EMC_RDV_0 = 0x0000003F
|
||||
EMC_REFRESH_0 = 0x0000203F
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000016
|
||||
EMC_PDEX2RD_0 = 0x00000016
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001E
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003F
|
||||
EMC_TXSR_0 = 0x00000266
|
||||
EMC_TCKE_0 = 0x00000012
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x0000002D
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x0000207F
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000003F
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0216001E
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012273E
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000020
|
||||
EMC_TPD_0 = 0x00000010
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000041
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x0000003F
|
||||
EMC_RDV_EARLY_0 = 0x0000003D
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186216
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x0000003F
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000080F
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004062
|
||||
EMC_TXSRDLL_0 = 0x00000266
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000031
|
||||
EMC_TR_RDV_MASK_0 = 0x00000041
|
||||
EMC_TR_QSAFE_0 = 0x00000039
|
||||
EMC_TR_QRST_0 = 0x00070009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||
EMC_IBDLY_0 = 0x1000001F
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000031
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000012B
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000A0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000A0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00250025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x3E3F3F40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x3D39383D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3A3D3A39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x393D3538
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000036
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x43424443
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3F424336
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x323A3B3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3937332F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000036
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x393D3B3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3A3E3A3B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3A39393A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3A393936
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000039
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08080907
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05070205
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3D3D3839
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3B3A3C37
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000039
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03070706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03060003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03030505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26262629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29292A27
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004042B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2166_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2166_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000082
|
||||
EMC_RFC_0 = 0x0000025F
|
||||
EMC_RAS_0 = 0x0000005B
|
||||
EMC_RP_0 = 0x00000027
|
||||
EMC_R2W_0 = 0x0000002F
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000027
|
||||
EMC_WR_RCD_0 = 0x00000027
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x0007000A
|
||||
EMC_QSAFE_0 = 0x0000003A
|
||||
EMC_RDV_0 = 0x00000040
|
||||
EMC_REFRESH_0 = 0x000020BF
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003F
|
||||
EMC_TXSR_0 = 0x0000026F
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000041
|
||||
EMC_TRPAB_0 = 0x0000002E
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x000020FF
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000040
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x021E001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012AFCD
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000013
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000042
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||
EMC_RDV_EARLY_0 = 0x0000003E
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118621E
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000040
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000082F
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000415D
|
||||
EMC_TXSRDLL_0 = 0x0000026F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000032
|
||||
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||
EMC_TR_QSAFE_0 = 0x0000003A
|
||||
EMC_TR_QRST_0 = 0x0007000A
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000032
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000130
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00250025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x40414141
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x3F3B393E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3C3E3C3B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3B3F373A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000038
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x44434444
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x41434437
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x333B3C3B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3A393431
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000037
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3A3F3D3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3C3F3C3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3B3A3B3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3B3B3B39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x090A0B08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x07080406
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3E3F393C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3D3B3E38
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03060706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x02000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07080A0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060508
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040502
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2823282A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29292628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004043B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2200_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2200_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000084
|
||||
EMC_RFC_0 = 0x00000268
|
||||
EMC_RAS_0 = 0x0000005D
|
||||
EMC_RP_0 = 0x00000028
|
||||
EMC_R2W_0 = 0x0000002F
|
||||
EMC_W2R_0 = 0x00000027
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000028
|
||||
EMC_WR_RCD_0 = 0x00000028
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x0007000A
|
||||
EMC_QSAFE_0 = 0x0000003A
|
||||
EMC_RDV_0 = 0x00000040
|
||||
EMC_REFRESH_0 = 0x00002144
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x0000003F
|
||||
EMC_TXSR_0 = 0x00000279
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000042
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002184
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000041
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0226001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012293F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000013
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000042
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||
EMC_RDV_EARLY_0 = 0x0000003E
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186226
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000040
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000851
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000425F
|
||||
EMC_TXSRDLL_0 = 0x00000279
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000032
|
||||
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||
EMC_TR_QSAFE_0 = 0x0000003A
|
||||
EMC_TR_QRST_0 = 0x0007000A
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000134
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00010014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x41414242
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x403C3A3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3E403D3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3D42393B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x46444747
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x42454638
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x353D3E3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3B3A3532
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000038
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3C413F41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3E423E3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3C3B3C3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3C3C3C39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0B0C0D0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x080A0608
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x40413B3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02030102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040502
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272827
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004044C
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2233_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2233_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000086
|
||||
EMC_RFC_0 = 0x00000272
|
||||
EMC_RAS_0 = 0x0000005E
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x0000002F
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x00070009
|
||||
EMC_QSAFE_0 = 0x0000003A
|
||||
EMC_RDV_0 = 0x00000040
|
||||
EMC_REFRESH_0 = 0x000021C5
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x00000282
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000043
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002205
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x022F0020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012839F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000042
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||
EMC_RDV_EARLY_0 = 0x0000003E
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118622F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000040
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000871
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000435A
|
||||
EMC_TXSRDLL_0 = 0x00000282
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000032
|
||||
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||
EMC_TR_QSAFE_0 = 0x0000003A
|
||||
EMC_TR_QRST_0 = 0x00070009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000032
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000139
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x42424344
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x413D3B40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3F423F3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3E433A3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x48474949
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x4547483B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000046
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x353E403E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3D3B3633
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000039
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3E424042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3F433F3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3E3C3D3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3E3E3E3B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0D0E0E0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0A0B0809
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x42433D3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000204
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2825262A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004045D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2266_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2266_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000088
|
||||
EMC_RFC_0 = 0x0000027B
|
||||
EMC_RAS_0 = 0x00000060
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x0000002F
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x00070009
|
||||
EMC_QSAFE_0 = 0x0000003A
|
||||
EMC_RDV_0 = 0x00000040
|
||||
EMC_REFRESH_0 = 0x00002245
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x0000028C
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000044
|
||||
EMC_TRPAB_0 = 0x00000030
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x00002285
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02370020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012283F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000042
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||
EMC_RDV_EARLY_0 = 0x0000003E
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186237
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000040
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000891
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004455
|
||||
EMC_TXSRDLL_0 = 0x0000028C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000032
|
||||
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||
EMC_TR_QSAFE_0 = 0x0000003A
|
||||
EMC_TR_QRST_0 = 0x00070009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000032
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000013E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x44444545
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x433F3D42
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x4143403F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3F443B3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49484B4A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x474A4A3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000048
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3741413F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3E3D3934
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3F444143
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x40444040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3F3E3F3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x403F3F3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0F0F100D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0B0E090B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x43433E40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4140433D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04050606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02030604
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04020302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26252629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282B29
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004046D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2300_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2300_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008A
|
||||
EMC_RFC_0 = 0x00000284
|
||||
EMC_RAS_0 = 0x00000061
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x00000030
|
||||
EMC_W2R_0 = 0x00000028
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000028
|
||||
EMC_QRST_0 = 0x00070008
|
||||
EMC_QSAFE_0 = 0x0000003A
|
||||
EMC_RDV_0 = 0x00000040
|
||||
EMC_REFRESH_0 = 0x000022CA
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000003
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x00000296
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000230A
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x023F0021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80125975
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000042
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||
EMC_RDV_EARLY_0 = 0x0000003E
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118623F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000040
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008B2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004558
|
||||
EMC_TXSRDLL_0 = 0x00000296
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000032
|
||||
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||
EMC_TR_QSAFE_0 = 0x0000003A
|
||||
EMC_TR_QRST_0 = 0x00070008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001F
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0B09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000032
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000142
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x45464747
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x45403F43
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000044
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x42444141
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x40443D40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4B4A4B4C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x484A4B3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000048
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x38424341
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x403E3936
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x01050102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x41404141
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4240413D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0F10110F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0C0F0A0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x45453F42
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4341443F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050106
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252828
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004047E
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2333_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2333_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008C
|
||||
EMC_RFC_0 = 0x0000028E
|
||||
EMC_RAS_0 = 0x00000062
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x00000030
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000028
|
||||
EMC_QRST_0 = 0x00070007
|
||||
EMC_QSAFE_0 = 0x0000003A
|
||||
EMC_RDV_0 = 0x00000040
|
||||
EMC_REFRESH_0 = 0x0000234B
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x0000029F
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000046
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000238B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02480021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80124762
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000042
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||
EMC_RDV_EARLY_0 = 0x0000003E
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186248
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000040
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008D2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004653
|
||||
EMC_TXSRDLL_0 = 0x0000029F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000032
|
||||
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||
EMC_TR_QSAFE_0 = 0x0000003A
|
||||
EMC_TR_QRST_0 = 0x00070007
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x1000001F
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0B0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000032
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x0000024A
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000147
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x06070707
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06010004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x45464443
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x42473F41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4C4C4D4D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x494B4D3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000004A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3A434442
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x41403B37
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x02070507
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03080304
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x43414243
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4342423F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x11121311
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0F110C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06060102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04020600
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000001
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040A040A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26262929
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29282627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2366_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2366_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008E
|
||||
EMC_RFC_0 = 0x00000297
|
||||
EMC_RAS_0 = 0x00000064
|
||||
EMC_RP_0 = 0x0000002B
|
||||
EMC_R2W_0 = 0x00000030
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002B
|
||||
EMC_WR_RCD_0 = 0x0000002B
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00070009
|
||||
EMC_QSAFE_0 = 0x0000003B
|
||||
EMC_RDV_0 = 0x00000041
|
||||
EMC_REFRESH_0 = 0x000023CB
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002A9
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000047
|
||||
EMC_TRPAB_0 = 0x00000032
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x0000240B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000002E
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02500022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012304B
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000043
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||
EMC_RDV_EARLY_0 = 0x0000003F
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186250
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000041
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008F2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000474E
|
||||
EMC_TXSRDLL_0 = 0x000002A9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000033
|
||||
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||
EMC_TR_QSAFE_0 = 0x0000003B
|
||||
EMC_TR_QRST_0 = 0x00070009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000033
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000014C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x07080909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x07030005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06080504
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04090003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0E0D0F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0D0E00
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B454543
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x42413C38
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x04090608
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x05090506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020404
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040502
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x12131511
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x10110D0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08090204
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040801
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04050506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02030102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252529
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28292629
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2400_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2400_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000090
|
||||
EMC_RFC_0 = 0x000002A0
|
||||
EMC_RAS_0 = 0x00000065
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x00000030
|
||||
EMC_W2R_0 = 0x00000029
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00070009
|
||||
EMC_QSAFE_0 = 0x0000003B
|
||||
EMC_RDV_0 = 0x00000041
|
||||
EMC_REFRESH_0 = 0x00002450
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002B2
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000048
|
||||
EMC_TRPAB_0 = 0x00000033
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002490
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000047
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02580022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80121F39
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000043
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||
EMC_RDV_EARLY_0 = 0x0000003F
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186258
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000041
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000914
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004850
|
||||
EMC_TXSRDLL_0 = 0x000002B2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000033
|
||||
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||
EMC_TR_QSAFE_0 = 0x0000003B
|
||||
EMC_TR_QRST_0 = 0x00070009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000033
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000150
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0A0B0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x09050307
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06090606
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x050A0104
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0F0E1011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0C0F0F01
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3C464745
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x44433D39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x040A070A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060A0607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050503
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x14151713
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x12130F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09090305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050902
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A040A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2724282A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x2A27262B
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404B0
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2433_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2433_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000092
|
||||
EMC_RFC_0 = 0x000002AA
|
||||
EMC_RAS_0 = 0x00000067
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x00000030
|
||||
EMC_W2R_0 = 0x0000002A
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00070008
|
||||
EMC_QSAFE_0 = 0x0000003B
|
||||
EMC_RDV_0 = 0x00000041
|
||||
EMC_REFRESH_0 = 0x000024D1
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002BC
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x00000049
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002511
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000048
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02610023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122A41
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000043
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||
EMC_RDV_EARLY_0 = 0x0000003F
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186261
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000041
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000934
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000494B
|
||||
EMC_TXSRDLL_0 = 0x000002BC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000033
|
||||
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||
EMC_TR_QSAFE_0 = 0x0000003B
|
||||
EMC_TR_QRST_0 = 0x00070008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000033
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000155
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0B0C0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B060409
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080B0807
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070C0306
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x10101112
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0D101102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3D474846
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x45443F3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x050A080A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060A0707
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x07060607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x07070703
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x13151012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0B0B0506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09070A03
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05020302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2723242A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262426
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00050005
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404C1
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2466_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2466_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000094
|
||||
EMC_RFC_0 = 0x000002B3
|
||||
EMC_RAS_0 = 0x00000068
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x00000030
|
||||
EMC_W2R_0 = 0x0000002A
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00070008
|
||||
EMC_QSAFE_0 = 0x0000003B
|
||||
EMC_RDV_0 = 0x00000041
|
||||
EMC_REFRESH_0 = 0x00002551
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000010
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002C5
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004A
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002591
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02690023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012001A
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000043
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||
EMC_RDV_EARLY_0 = 0x0000003F
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186269
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000041
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000954
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004A46
|
||||
EMC_TXSRDLL_0 = 0x000002C5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000033
|
||||
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||
EMC_TR_QSAFE_0 = 0x0000003B
|
||||
EMC_TR_QRST_0 = 0x00070008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000033
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015A
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x20000100
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x00082000
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0C0D0E0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B07050A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0C0909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x080D0407
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x11111313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0E111303
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3F494A48
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4746413C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x070C090B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x080C0808
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x09070909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x09090905
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x18181A16
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x14161214
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0D0D0708
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00040505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2724232A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28292628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E181E18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E181E18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404D1
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2500_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2500_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000096
|
||||
EMC_RFC_0 = 0x000002BC
|
||||
EMC_RAS_0 = 0x00000069
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002A
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x00070007
|
||||
EMC_QSAFE_0 = 0x0000003B
|
||||
EMC_RDV_0 = 0x00000041
|
||||
EMC_REFRESH_0 = 0x000025D6
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002CF
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004B
|
||||
EMC_TRPAB_0 = 0x00000035
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002616
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02710023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012ED06
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x00000028
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000043
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||
EMC_RDV_EARLY_0 = 0x0000003F
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118614D
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000041
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000975
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004B49
|
||||
EMC_TXSRDLL_0 = 0x000002CF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000033
|
||||
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||
EMC_TR_QSAFE_0 = 0x0000003B
|
||||
EMC_TR_QRST_0 = 0x00070007
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000033
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00060000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0F0F1010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0D09070C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0B0D0A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x090E0508
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x12121414
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0F121404
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x252C2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4847423D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000045
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x090D0B0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0A0E0A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0B090A0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0A0A0A07
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1B19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16181415
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0E070A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0C090D07
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07060A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040208
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02040704
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04020403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24232627
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27292B27
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404E2
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2533_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2533_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000098
|
||||
EMC_RFC_0 = 0x000002C6
|
||||
EMC_RAS_0 = 0x0000006B
|
||||
EMC_RP_0 = 0x0000002E
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000001D
|
||||
EMC_WR_RCD_0 = 0x0000002E
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x00080005
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x00000041
|
||||
EMC_REFRESH_0 = 0x00002657
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002D9
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004C
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002697
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004A
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x027A0024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012D7F0
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000043
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||
EMC_RDV_EARLY_0 = 0x0000003F
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118627A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000041
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000995
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004C44
|
||||
EMC_TXSRDLL_0 = 0x000002D9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000033
|
||||
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x1000001F
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000033
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000163
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x10111111
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0F0A080D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0E0F0D0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0C10070A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x14141616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x12141606
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x414C4D4B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4948433E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000046
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A0F0C0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0A0F0B0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0C0B0C08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1B1C1D1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x181A1517
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F10090B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0E0B0E08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07040106
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242428
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404F3
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2566_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2566_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009A
|
||||
EMC_RFC_0 = 0x000002CF
|
||||
EMC_RAS_0 = 0x0000006C
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00080006
|
||||
EMC_QSAFE_0 = 0x0000003C
|
||||
EMC_RDV_0 = 0x00000042
|
||||
EMC_REFRESH_0 = 0x000026D7
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002E2
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004D
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002717
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02820024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012CAE3
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000044
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||
EMC_RDV_EARLY_0 = 0x00000040
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186282
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000042
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009B5
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004D3F
|
||||
EMC_TXSRDLL_0 = 0x000002E2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000034
|
||||
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||
EMC_TR_QSAFE_0 = 0x0000003C
|
||||
EMC_TR_QRST_0 = 0x00080006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000034
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000168
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x11111313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x100C0A0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10110E0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0D12090C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x17161818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x13171808
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x020D0E0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A090500
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0C110E11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0D110D0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0D0C0C0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0D0D0D0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1C1C1E1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x191B1618
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x11120B0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0F0C1009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050106
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2724252B
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x272A2627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040503
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
@@ -0,0 +1,87 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
emc_cfg = 0xF3200000
|
||||
emc_rc = 0x0000009C
|
||||
emc_rfc = 0x000002D8
|
||||
emc_ras = 0x0000006E
|
||||
emc_rp = 0x0000002F
|
||||
emc_r2w = 0x00000031
|
||||
emc_w2r = 0x0000002B
|
||||
emc_r2p = 0x0000000E
|
||||
emc_w2p = 0x00000033
|
||||
emc_rd_rcd = 0x0000002F
|
||||
emc_wr_rcd = 0x0000002F
|
||||
emc_rrd = 0x00000014
|
||||
emc_rext = 0x0000001B
|
||||
emc_qsafe = 0x0000003C
|
||||
emc_refresh = 0x0000275C
|
||||
emc_burst_refresh_num = 0x00000000
|
||||
emc_pdex2wr = 0x0000001B
|
||||
emc_pdex2rd = 0x0000001B
|
||||
emc_pchg2pden = 0x00000005
|
||||
emc_act2pden = 0x00000025
|
||||
emc_ar2pden = 0x00000005
|
||||
emc_rw2pden = 0x00000040
|
||||
emc_txsr = 0x000002EC
|
||||
emc_tcke = 0x00000016
|
||||
emc_tfaw = 0x0000004E
|
||||
emc_trpab = 0x00000037
|
||||
emc_tclkstable = 0x00000004
|
||||
emc_tclkstop = 0x0000001E
|
||||
emc_trefbw = 0x0000279C
|
||||
emc_tppd = 0x00000004
|
||||
emc_odt_write = 0x00000000
|
||||
emc_pdex2mrr = 0x0000004C
|
||||
emc_wext = 0x00000019
|
||||
emc_rfc_slr = 0x00000000
|
||||
emc_mrs_wait_cnt2 = 0x028A0025
|
||||
emc_mrs_wait_cnt = 0x07FF0037
|
||||
emc_mrs = 0x00000000
|
||||
emc_emrs = 0x00000000
|
||||
emc_mrw = 0x00170040
|
||||
emc_fbio_spare = 0x00000012
|
||||
emc_fbio_cfg5 = 0x9160A00D
|
||||
emc_pdex2cke = 0x00000003
|
||||
emc_cke2pden = 0x00000017
|
||||
emc_r2r = 0x00000000
|
||||
emc_einput = 0x00000010
|
||||
emc_einput_duration = 0x00000029
|
||||
emc_puterm_extra = 0x00000001
|
||||
emc_tckesr = 0x00000027
|
||||
emc_tpd = 0x00000014
|
||||
emc_cfg_2 = 0x0011083D
|
||||
emc_cfg_dig_dll = 0x002C03A9
|
||||
emc_cfg_dig_dll_period = 0x00008000
|
||||
emc_rdv_mask = 0x00000044
|
||||
emc_wdv_mask = 0x00000010
|
||||
emc_rdv_early_mask = 0x00000042
|
||||
emc_rdv_early = 0x00000040
|
||||
emc_fdpd_ctrl_dq = 0x8020221F
|
||||
emc_fdpd_ctrl_cmd = 0x0220F40F
|
||||
emc_sel_dpd_ctrl = 0x0004000C
|
||||
emc_pre_refresh_req_cnt = 0x000009D7
|
||||
emc_dyn_self_ref_control = 0x80004E41
|
||||
emc_txsrdll = 0x000002EC
|
||||
emc_ibdly = 0x10000020
|
||||
emc_obdly = 0x10000002
|
||||
emc_txdsrvttgen = 0x00000000
|
||||
emc_we_duration = 0x0000000E
|
||||
emc_ws_duration = 0x00000008
|
||||
emc_wev = 0x0000000C
|
||||
emc_cfg_3 = 0x00000040
|
||||
emc_wdv_chk = 0x00000006
|
||||
emc_cfg_pipe_2 = 0x00000000
|
||||
emc_cfg_pipe_1 = 0x0FFF0000
|
||||
emc_cfg_pipe = 0x0FFF0000
|
||||
emc_quse_width = 0x0000000B
|
||||
emc_puterm_width = 0x80000000
|
||||
emc_fbio_cfg7 = 0x00003BFF
|
||||
emc_rfcpb = 0x0000016C
|
||||
emc_ccdmw = 0x00000020
|
||||
emc_config_sample_delay = 0x00000020
|
||||
emc_wdv = 0x00000010
|
||||
emc_quse = 0x0000002A
|
||||
emc_qrst = 0x00080006
|
||||
emc_rdv = 0x00000042
|
||||
emc_wsv = 0x0000000E
|
||||
emc_qpop = 0x00000034
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2633_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2633_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009E
|
||||
EMC_RFC_0 = 0x000002E2
|
||||
EMC_RAS_0 = 0x0000006F
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002C
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00080005
|
||||
EMC_QSAFE_0 = 0x0000003D
|
||||
EMC_RDV_0 = 0x00000042
|
||||
EMC_REFRESH_0 = 0x000027DD
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002F5
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004F
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000281D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02930025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000044
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||
EMC_RDV_EARLY_0 = 0x00000040
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186293
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000042
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009F7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004F3C
|
||||
EMC_TXSRDLL_0 = 0x000002F5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000034
|
||||
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||
EMC_TR_QSAFE_0 = 0x0000003D
|
||||
EMC_TR_QRST_0 = 0x00080005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D08
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000034
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000171
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x15151516
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x130F0D12
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10141010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0F150B0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1A1A1C1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x171B1B0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x050F110E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0D0C0701
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0E131114
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x10151011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x100E0F10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x100F100C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x201F211F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1C1E191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14150E0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1110130B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05080909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090508
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07080A0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070B09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04030606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04040304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07040106
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08040502
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27262428
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26262627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040525
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D08
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2666_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2666_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A0
|
||||
EMC_RFC_0 = 0x000002EB
|
||||
EMC_RAS_0 = 0x00000070
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002C
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00080005
|
||||
EMC_QSAFE_0 = 0x0000003D
|
||||
EMC_RDV_0 = 0x00000042
|
||||
EMC_REFRESH_0 = 0x0000285D
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000026
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x000002FF
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x00000050
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000289D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x029B0026
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80129EB6
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000035
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||
EMC_RDV_EARLY_0 = 0x00000040
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118629B
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000042
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A17
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005037
|
||||
EMC_TXSRDLL_0 = 0x000002FF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000034
|
||||
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||
EMC_TR_QSAFE_0 = 0x0000003D
|
||||
EMC_TR_QRST_0 = 0x00080005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000034
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000176
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x16171717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x15100D14
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x12151211
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x11160C10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323333
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x181B1C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A2A2624
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x10161315
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x11161212
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x11101112
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1211110E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x21222320
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1E201C1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x16160F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1410140D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B050B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080B08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090508
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03080509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030202
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05020403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08050208
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09050604
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25252729
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040535
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2700_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2700_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A2
|
||||
EMC_RFC_0 = 0x000002F4
|
||||
EMC_RAS_0 = 0x00000072
|
||||
EMC_RP_0 = 0x00000031
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002C
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000031
|
||||
EMC_WR_RCD_0 = 0x00000031
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x00080004
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000042
|
||||
EMC_REFRESH_0 = 0x000028E2
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000026
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x00000309
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000051
|
||||
EMC_TRPAB_0 = 0x00000039
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x00002922
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004F
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02A30026
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80128FA7
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000029
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000044
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||
EMC_RDV_EARLY_0 = 0x00000040
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x00310640
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862A3
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000042
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A38
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000513A
|
||||
EMC_TXSRDLL_0 = 0x00000309
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000034
|
||||
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x00080004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001F
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000034
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000017A
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x17171818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x16110F15
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x14171313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E282B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1C1B1E1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191C1D0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x08131412
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x100F0A04
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x11171517
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x12171313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x13121213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1312130F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x23232422
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1F221C1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x18181112
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1512160E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0509090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070A08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09060000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02020203
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030202
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x03020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24252628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22272725
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040546
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2733_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2733_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A4
|
||||
EMC_RFC_0 = 0x000002FE
|
||||
EMC_RAS_0 = 0x00000073
|
||||
EMC_RP_0 = 0x00000032
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002D
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000032
|
||||
EMC_WR_RCD_0 = 0x00000032
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x00000029
|
||||
EMC_QRST_0 = 0x00080003
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000042
|
||||
EMC_REFRESH_0 = 0x00002963
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000027
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x00000312
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000052
|
||||
EMC_TRPAB_0 = 0x0000003A
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x000029A3
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000050
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02AC0027
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80128198
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000018
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000D
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000029
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000044
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||
EMC_RDV_EARLY_0 = 0x00000040
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862AC
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000042
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A58
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005235
|
||||
EMC_TXSRDLL_0 = 0x00000312
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000034
|
||||
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x00080003
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x1000001F
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000034
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000017F
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000B0005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x191A1A1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x18131016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x16181515
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x14190F13
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1D1E1F1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1A1D1E0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000031
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x09141513
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x12100B05
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x13191619
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x141A1515
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x14131414
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x14141410
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x25252623
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x20231E20
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1A191114
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x16131811
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070C09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09080200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050208
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24232426
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x24262824
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040557
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2766_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2766_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A6
|
||||
EMC_RFC_0 = 0x00000307
|
||||
EMC_RAS_0 = 0x00000075
|
||||
EMC_RP_0 = 0x00000032
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x00000021
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000032
|
||||
EMC_WR_RCD_0 = 0x00000032
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002B
|
||||
EMC_QRST_0 = 0x00080005
|
||||
EMC_QSAFE_0 = 0x00000033
|
||||
EMC_RDV_0 = 0x00000043
|
||||
EMC_REFRESH_0 = 0x000029E3
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000027
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000040
|
||||
EMC_TXSR_0 = 0x0000031C
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000053
|
||||
EMC_TRPAB_0 = 0x0000003B
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002A23
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000050
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02B40027
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012738A
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000018
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002A
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000045
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||
EMC_RDV_EARLY_0 = 0x00000041
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862B4
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000043
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A78
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005330
|
||||
EMC_TXSRDLL_0 = 0x0000031C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000035
|
||||
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x00080005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000035
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000184
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1A1A1B1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x18141218
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x171B1717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x161B1115
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1F1E2121
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1B1F200F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0B161715
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x13110D07
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x151B181B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x161B1717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x16141617
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x15151611
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x27262725
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x22251F22
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000020
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1B1A1314
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x17141811
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0509090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x070A060A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08090B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0B0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01080C0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020202
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07060105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242528
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25252423
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040567
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2800_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2800_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A8
|
||||
EMC_RFC_0 = 0x00000310
|
||||
EMC_RAS_0 = 0x00000076
|
||||
EMC_RP_0 = 0x00000033
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002D
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000033
|
||||
EMC_WR_RCD_0 = 0x00000033
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002B
|
||||
EMC_QRST_0 = 0x00080005
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000043
|
||||
EMC_REFRESH_0 = 0x00002A68
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000028
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000041
|
||||
EMC_TXSR_0 = 0x00000325
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000054
|
||||
EMC_TRPAB_0 = 0x0000003B
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002AA8
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000051
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02BC0028
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012667C
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000018
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002A
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000045
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||
EMC_RDV_EARLY_0 = 0x00000041
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862BC
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000043
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A9A
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005432
|
||||
EMC_TXSRDLL_0 = 0x00000325
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000035
|
||||
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x00080005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000016
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0B09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000035
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000188
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1C1B1C1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1A151319
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x171B1717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x161B1115
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x21202222
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1D202211
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x1B212120
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x15130D08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x161B191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x171B1818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x17161617
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x17161713
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x27282926
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x24262024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000021
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1B1C1416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x18161A13
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0409090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090C060C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x09090C10
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0B0A0B00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x04070308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x09030405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x06030104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050106
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232527
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25272222
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x070B070B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040578
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2833_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2833_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000AA
|
||||
EMC_RFC_0 = 0x0000031A
|
||||
EMC_RAS_0 = 0x00000077
|
||||
EMC_RP_0 = 0x00000033
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002E
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000033
|
||||
EMC_WR_RCD_0 = 0x00000033
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002B
|
||||
EMC_QRST_0 = 0x00080004
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000043
|
||||
EMC_REFRESH_0 = 0x00002AE9
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001D
|
||||
EMC_PDEX2RD_0 = 0x0000001D
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000028
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000041
|
||||
EMC_TXSR_0 = 0x0000032F
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000055
|
||||
EMC_TRPAB_0 = 0x0000003C
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002B29
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000052
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02C50028
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80125A71
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002B
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000045
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||
EMC_RDV_EARLY_0 = 0x00000041
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862C5
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000043
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000ABA
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000552D
|
||||
EMC_TXSRDLL_0 = 0x0000032F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000035
|
||||
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x00080004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D08
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000035
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000018D
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1C1C1C1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2A292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x191C1A19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x22232524
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x2F313328
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0D181917
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x15150F0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x171D1B1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x21232121
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1918181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x19171915
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2A2B2C28
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x26272225
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000023
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1D1D1617
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1A171B15
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x050A0A0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080B060B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x01020304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x09040504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x03020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232427
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x24262325
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040589
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D08
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2866_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2866_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000AC
|
||||
EMC_RFC_0 = 0x00000323
|
||||
EMC_RAS_0 = 0x00000079
|
||||
EMC_RP_0 = 0x00000034
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002E
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000034
|
||||
EMC_WR_RCD_0 = 0x00000034
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002B
|
||||
EMC_QRST_0 = 0x00080004
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000043
|
||||
EMC_REFRESH_0 = 0x00002B69
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001E
|
||||
EMC_PDEX2RD_0 = 0x0000001E
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x00000029
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000041
|
||||
EMC_TXSR_0 = 0x00000338
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000056
|
||||
EMC_TRPAB_0 = 0x0000003D
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002BA9
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000054
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02CD0029
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012475D
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D0000
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002B
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430020
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000045
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||
EMC_RDV_EARLY_0 = 0x00000041
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862CD
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000043
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000ADA
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005628
|
||||
EMC_TXSRDLL_0 = 0x00000338
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000035
|
||||
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x00080004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0F09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000035
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000192
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1F1F1F20
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1D19161D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1B1D1B1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x191D1518
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x25242625
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x21242513
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0E191A19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1816100B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x181F1C1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x191E1A1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1B191A1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1A191B16
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2B2B2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x27282326
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1E1F171A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0C050C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x09090B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0407040A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02030001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0A040505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x06030104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060109
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0A040805
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24242327
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25252225
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040599
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C08
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2900_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2900_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000AE
|
||||
EMC_RFC_0 = 0x0000032C
|
||||
EMC_RAS_0 = 0x0000007A
|
||||
EMC_RP_0 = 0x00000035
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002E
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000035
|
||||
EMC_WR_RCD_0 = 0x00000035
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002B
|
||||
EMC_QRST_0 = 0x00080004
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000043
|
||||
EMC_REFRESH_0 = 0x00002BEE
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001E
|
||||
EMC_PDEX2RD_0 = 0x0000001E
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x00000029
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000041
|
||||
EMC_TXSR_0 = 0x00000342
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000057
|
||||
EMC_TRPAB_0 = 0x0000003D
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002C2E
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000055
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02D50029
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80124258
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000E
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002C
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000045
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||
EMC_RDV_EARLY_0 = 0x00000041
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862D5
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000043
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000AFB
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000572B
|
||||
EMC_TXSRDLL_0 = 0x00000342
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000035
|
||||
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x00080004
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000021
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000035
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000196
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00010006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00060000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x20202021
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1E19171E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1B1E1B1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1A1E1519
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x26262827
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x22252616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0F1A1B1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1717110B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x181F1C1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1A1E1B1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1B1A1B1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1A1A1B16
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2C2D2E2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x292B2428
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000025
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1F20171A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1C191E16
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x050A0A0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x02000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080C050C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A090300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0308040A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08040504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04030004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060108
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09040704
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25212426
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22252123
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000405AA
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2933_emc.txt
Normal file
528
Source/TimingTool/timings/K4U6E3S4AA-MGCL/1866/emc/2933_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B0
|
||||
EMC_RFC_0 = 0x00000336
|
||||
EMC_RAS_0 = 0x0000007C
|
||||
EMC_RP_0 = 0x00000035
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002F
|
||||
EMC_R2P_0 = 0x0000000E
|
||||
EMC_W2P_0 = 0x00000033
|
||||
EMC_RD_RCD_0 = 0x00000035
|
||||
EMC_WR_RCD_0 = 0x00000035
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000010
|
||||
EMC_QUSE_0 = 0x0000002A
|
||||
EMC_QRST_0 = 0x00080002
|
||||
EMC_QSAFE_0 = 0x00000041
|
||||
EMC_RDV_0 = 0x00000043
|
||||
EMC_REFRESH_0 = 0x00002C6F
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001E
|
||||
EMC_PDEX2RD_0 = 0x0000001E
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002A
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000041
|
||||
EMC_TXSR_0 = 0x0000034C
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000058
|
||||
EMC_TRPAB_0 = 0x0000003E
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002CAF
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000055
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02DE002A
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80123147
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x88020036
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000C
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002E
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002C
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000045
|
||||
EMC_WDV_MASK_0 = 0x00000010
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||
EMC_RDV_EARLY_0 = 0x00000041
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862DE
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000043
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B1B
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005826
|
||||
EMC_TXSRDLL_0 = 0x0000034C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000035
|
||||
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||
EMC_TR_QSAFE_0 = 0x00000041
|
||||
EMC_TR_QRST_0 = 0x00080002
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000020
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000C
|
||||
EMC_WSV_0 = 0x0000000E
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000035
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000019B
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001A000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001A000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00260028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x21222122
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1F1B181F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1C201C1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1C20181B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x28272A29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x23262817
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000025
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x101B1E1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1818120C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1B201D21
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1B201C1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1D1C1C1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1C1B1C1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2F2F302E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2A2C272A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000027
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2121191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1E1B1F17
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090D070D
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070B0008
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x090A0C10
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080D0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09080200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0307040A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x06000408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07040604
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04040005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060108
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09040603
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25222426
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22232023
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001A001A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000405BB
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user