Merge branch 'main' of https://github.com/Horizon-OC/Horizon-OC
This commit is contained in:
souldbminersmwc
@@ -173,11 +173,14 @@ namespace ams::ldr::hoc::pcv {
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void Patch(uintptr_t mapped_nso, size_t nso_size) {
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#ifdef ATMOSPHERE_IS_STRATOSPHERE
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SafetyCheck();
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bool isMariko = (spl::GetSocType() == spl::SocType_Mariko);
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if (isMariko)
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if (isMariko) {
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mariko::Patch(mapped_nso, nso_size);
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else
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} else {
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erista::Patch(mapped_nso, nso_size);
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}
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#endif
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}
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@@ -22,253 +22,12 @@
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#include "../oc_common.hpp"
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#include "pcv_common.hpp"
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#include "pcv_erista.hpp"
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#include "pcv_mariko.hpp"
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#include "pcv_asm.hpp"
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namespace ams::ldr::hoc::pcv {
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namespace mariko {
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constexpr cvb_entry_t CpuCvbTableDefault[] = {
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{ 204000, { 721589, -12695, 27 }, { } },
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{ 306000, { 747134, -14195, 27 }, { } },
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{ 408000, { 776324, -15705, 27 }, { } },
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{ 510000, { 809160, -17205, 27 }, { } },
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{ 612000, { 845641, -18715, 27 }, { } },
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{ 714000, { 885768, -20215, 27 }, { } },
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{ 816000, { 929540, -21725, 27 }, { } },
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{ 918000, { 976958, -23225, 27 }, { } },
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{ 1020000, { 1028021, -24725, 27 }, { 1120000 } },
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{ 1122000, { 1082730, -26235, 27 }, { 1120000 } },
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{ 1224000, { 1141084, -27735, 27 }, { 1120000 } },
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{ 1326000, { 1203084, -29245, 27 }, { 1120000 } },
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{ 1428000, { 1268729, -30745, 27 }, { 1120000 } },
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{ 1581000, { 1374032, -33005, 27 }, { 1120000 } },
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{ 1683000, { 1448791, -34505, 27 }, { 1120000 } },
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{ 1785000, { 1527196, -36015, 27 }, { 1120000 } },
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{ 1887000, { 1609246, -37515, 27 }, { 1120000 } },
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{ 1963500, { 1675751, -38635, 27 }, { 1120000 } },
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{ },
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};
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constexpr u32 CpuClkOfficial = 1963'500;
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constexpr u32 CpuVoltOfficial = 1120;
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constexpr u32 CpuVminOfficial = 620;
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static const u32 cpuVoltagePatchValues[] = { 850, 38, 1120, 1000, 100, 1000, 0 };
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static const s32 cpuVoltagePatchOffsets[] = { -2, -1, 5, 6, 7, 8, 9 };
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static_assert(sizeof(cpuVoltagePatchValues) == sizeof(cpuVoltagePatchOffsets), "Invalid cpuVoltagePatch size");
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static const u32 cpuVoltThermalData[] = { 620, 1120, 20000, 620, 1120, 70000, 950, 1132, 0, 950, 1227, 0 };
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static const u32 allowedCpuMaxFrequencies[] = { 1'963'500, 2'091'000, 2'193'000, 2'295'000, 2'397'000, 2'499'000, 2'601'000, 2'703'000, };
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constexpr cvb_entry_t GpuCvbTableDefault[] = {
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// GPUB01_NA_CVB_TABLE
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{ 76800, {}, { 610000, } },
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{ 153600, {}, { 610000, } },
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{ 230400, {}, { 610000, } },
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{ 307200, {}, { 610000, } },
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{ 384000, {}, { 610000, } },
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{ 460800, {}, { 610000, } },
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{ 537600, {}, { 801688, -10900, -163, 298, -10599, 162, } },
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{ 614400, {}, { 824214, -5743, -452, 238, -6325, 81, } },
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{ 691200, {}, { 848830, -3903, -552, 119, -4030, -2, } },
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{ 768000, {}, { 891575, -4409, -584, 0, -2849, 39, } },
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{ 844800, {}, { 940071, -5367, -602, -60, -63, -93, } },
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{ 921600, {}, { 986765, -6637, -614, -179, 1905, -13, } },
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{ 998400, {}, { 1098475, -13529, -497, -179, 3626, 9, } },
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{ 1075200, {}, { 1163644, -12688, -648, 0, 1077, 40, } },
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{ 1152000, {}, { 1204812, -9908, -830, 0, 1469, 110, } },
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{ 1228800, {}, { 1277303, -11675, -859, 0, 3722, 313, } },
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{ 1267200, {}, { 1335531, -12567, -867, 0, 3681, 559, } },
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{ },
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};
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constexpr u32 GpuClkPllMax = 1300'000'000;
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constexpr u32 GpuClkPllLimit = 2'600'000;
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constexpr u32 GpuVminOfficial = 610;
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static const u32 gpuDVFSPattern[] = { 1050, 1000, 100, 1000, 10, };
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static const u32 gpuVoltThermalPattern[] = { 800, 1120, 0, 610, 1120, 20000, 610, 1120, 30000, 610, 1120, 50000, 610, 1120, 70000, 610, 1120, 90000, };
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static_assert(sizeof(gpuVoltThermalPattern) == 72, "Invalid gpuVoltThermalPattern");
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/* GPU Max Clock asm Pattern:
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*
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* MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
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*
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* MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
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*/
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inline constexpr u32 asm_pattern[] = {0x52820000, 0x72A001C0};
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inline auto asm_compare_no_rd = [](u32 ins1, u32 ins2) {
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return ((ins1 ^ ins2) >> 5) == 0;
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};
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inline auto asm_get_rd = [](u32 ins) {
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return ins & ((1 << 5) - 1);
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};
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inline auto asm_set_rd = [](u32 ins, u8 rd) {
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return (ins & 0xFFFFFFE0) | (rd & 0x1F);
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};
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inline auto asm_set_imm16 = [](u32 ins, u16 imm) {
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return (ins & 0xFFE0001F) | ((imm & 0xFFFF) << 5);
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};
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inline auto AsmGetImm16 = [](u32 ins) {
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return static_cast<u16>((ins >> 5) & 0xFFFF);
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};
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inline bool GpuMaxClockPatternFn(u32 *ptr32) {
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return asm_compare_no_rd(*ptr32, asm_pattern[0]);
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}
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constexpr emc_dvb_dvfs_table_t EmcDvbTableDefault[] = {
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{ 204000, { 637, 637, 637, } },
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{ 408000, { 637, 637, 637, } },
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{ 800000, { 637, 637, 637, } },
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{ 1065600, { 637, 637, 637, } },
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{ 1331200, { 650, 637, 637, } },
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{ 1600000, { 675, 650, 637, } },
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};
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constexpr u32 EmcClkOSAlt = 1331'200;
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constexpr u32 EmcClkPllmLimit = 2133'000'000;
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constexpr u32 EmcVddqDefault = 600'000;
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constexpr u32 MemVdd2Default = 1100'000;
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constexpr u32 MTC_TABLE_REV = 3;
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void Patch(uintptr_t mapped_nso, size_t nso_size);
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}
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namespace erista {
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static u32 maxEmcClocks[] = { C.eristaEmcMaxClock2, C.eristaEmcMaxClock1, C.eristaEmcMaxClock, };
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#define GET_MAX_OF_ARR(ARR) (*std::max_element(ARR, ARR + std::size(ARR)))
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constexpr cvb_entry_t CpuCvbTableDefault[] = {
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// CPU_PLL_CVB_TABLE_ODN
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{ 204000, {721094}, { } },
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{ 306000, {754040}, { } },
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{ 408000, {786986}, { } },
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{ 510000, {819932}, { } },
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{ 612000, {852878}, { } },
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{ 714000, {885824}, { } },
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{ 816000, {918770}, { } },
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{ 918000, {951716}, { } },
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{ 1020000, {984662}, { -2875621, 358099, -8585} },
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{ 1122000, {1017608}, { -52225, 104159, -2816} },
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{ 1224000, {1050554}, { 1076868, 8356, -727} },
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{ 1326000, {1083500}, { 2208191, -84659, 1240} },
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{ 1428000, {1116446}, { 2519460, -105063, 1611} },
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{ 1581000, {1130000}, { 2889664, -122173, 1834} },
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{ 1683000, {1168000}, { 5100873, -279186, 4747} },
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{ 1785000, {1227500}, { 5100873, -279186, 4747} },
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{ },
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};
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constexpr u32 CpuVoltOfficial = 1227;
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constexpr u32 CpuVminOfficial = 825;
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constexpr u32 CpuVoltL4T = 1257'000;
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static const u32 cpuVoltDvfsPattern[] = { 1227, 1000, 100, 1000, 0 };
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static_assert(sizeof(cpuVoltDvfsPattern) == 0x14, "invalid cpuVoltDvfsPattern size");
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static const u32 cpuVoltageThermalPattern[] = { 950, 1132, 0, 950, 1227, 0, 825, 1227, 15000, 825, 1170, 60000, 825, 1132, 80000 };
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static_assert(sizeof(cpuVoltageThermalPattern) == 0x3c, "invalid cpuVoltageThermalPattern size");
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constexpr u32 GpuClkPllLimit = 2'600'000;
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constexpr u32 GpuClkPllMax = 921'600'000;
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constexpr u32 GpuVminOfficial = 810;
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constexpr u16 CpuMinVolts[] = { 950, 850, 825, 810 };
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inline bool CpuMaxVoltPatternFn(u32* ptr32) {
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u32 val = *ptr32;
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return (val == 1132 || val == 1170 || val == 1227);
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}
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static const u32 gpuVoltDvfsPattern[] = { 810, 1150, 1000, 100, 1000, 10, };
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static_assert(sizeof(gpuVoltDvfsPattern) == (sizeof(u32) * 6), "Invalid gpuVoltDvfsPattern");
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static const u32 gpuVoltThermalPattern[] = { 950, 1132, 0, 810, 1132, 15000, 810, 1132, 30000, 810, 1132, 50000, 810, 1132, 70000, 810, 1132, 105000 };
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static_assert(sizeof(gpuVoltThermalPattern) == 0x48, "invalid gpuVoltageThermalPattern size");
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/* GPU Max Clock asm Pattern:
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*
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* MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
|
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*
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* MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
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*/
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inline constexpr u32 asm_pattern[] = {
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0x52820000, 0x72A001C0
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};
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inline auto asm_compare_no_rd = [](u32 ins1, u32 ins2) {
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return ((ins1 ^ ins2) >> 5) == 0;
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};
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inline auto asm_get_rd = [](u32 ins) {
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return ins & ((1 << 5) - 1);
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};
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inline auto asm_set_rd = [](u32 ins, u8 rd) {
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return (ins & 0xFFFFFFE0) | (rd & 0x1F);
|
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};
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inline auto asm_set_imm16 = [](u32 ins, u16 imm) {
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return (ins & 0xFFE0001F) | ((imm & 0xFFFF) << 5);
|
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};
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|
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inline auto AsmGetImm16 = [](u32 ins) {
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return static_cast<u16>((ins >> 5) & 0xFFFF);
|
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};
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|
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inline bool GpuMaxClockPatternFn(u32 *ptr32) {
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return asm_compare_no_rd(*ptr32, asm_pattern[0]);
|
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};
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|
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constexpr cvb_entry_t GpuCvbTableDefault[] = {
|
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// NA_FREQ_CVB_TABLE
|
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{ 76800, {}, { 814294, 8144, -940, 808, -21583, 226, } },
|
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{ 153600, {}, { 856185, 8144, -940, 808, -21583, 226, } },
|
||||
{ 230400, {}, { 898077, 8144, -940, 808, -21583, 226, } },
|
||||
{ 307200, {}, { 939968, 8144, -940, 808, -21583, 226, } },
|
||||
{ 384000, {}, { 981860, 8144, -940, 808, -21583, 226, } },
|
||||
{ 460800, {}, { 1023751, 8144, -940, 808, -21583, 226, } },
|
||||
{ 537600, {}, { 1065642, 8144, -940, 808, -21583, 226, } },
|
||||
{ 614400, {}, { 1107534, 8144, -940, 808, -21583, 226, } },
|
||||
{ 691200, {}, { 1149425, 8144, -940, 808, -21583, 226, } },
|
||||
{ 768000, {}, { 1191317, 8144, -940, 808, -21583, 226, } },
|
||||
{ 844800, {}, { 1233208, 8144, -940, 808, -21583, 226, } },
|
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{ 921600, {}, { 1275100, 8144, -940, 808, -21583, 226, } },
|
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{ },
|
||||
};
|
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|
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constexpr u32 MemVoltHOS = 1125'000;
|
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constexpr u32 EmcClkMinFreq = 40800; /* 40.8 MHz table only exists on erista. */
|
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constexpr u32 EmcClkPllmLimit = 1866'000'000;
|
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|
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constexpr u32 MTC_TABLE_REV = 7;
|
||||
|
||||
void Patch(uintptr_t mapped_nso, size_t nso_size);
|
||||
}
|
||||
|
||||
inline auto MatchesPattern = [](u32 *base, const auto &offsets, const auto &values) {
|
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for (size_t i = 0; i < std::size(values); ++i) {
|
||||
if (*(base + offsets[i]) != values[i]) {
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (C) Switch-OC-Suite
|
||||
*
|
||||
* Copyright (c) 2023 hanai3Bi
|
||||
*
|
||||
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "../oc_common.hpp"
|
||||
|
||||
namespace ams::ldr::hoc::pcv {
|
||||
|
||||
inline auto asm_compare_no_rd = [](u32 ins1, u32 ins2) {
|
||||
return ((ins1 ^ ins2) >> 5) == 0;
|
||||
};
|
||||
|
||||
inline auto asm_get_rd = [](u32 ins) {
|
||||
return ins & ((1 << 5) - 1);
|
||||
};
|
||||
|
||||
inline auto asm_set_rd = [](u32 ins, u8 rd) {
|
||||
return (ins & 0xFFFFFFE0) | (rd & 0x1F);
|
||||
};
|
||||
|
||||
inline auto asm_set_imm16 = [](u32 ins, u16 imm) {
|
||||
return (ins & 0xFFE0001F) | ((imm & 0xFFFF) << 5);
|
||||
};
|
||||
|
||||
inline auto AsmGetImm16 = [](u32 ins) {
|
||||
return static_cast<u16>((ins >> 5) & 0xFFFF);
|
||||
};
|
||||
|
||||
}
|
||||
@@ -134,7 +134,7 @@ namespace ams::ldr::hoc::pcv::erista {
|
||||
Result GpuFreqMaxAsm(u32 *ptr32) {
|
||||
// Check if both two instructions match the pattern
|
||||
u32 ins1 = *ptr32, ins2 = *(ptr32 + 1);
|
||||
if (!(asm_compare_no_rd(ins1, asm_pattern[0]) && asm_compare_no_rd(ins2, asm_pattern[1])))
|
||||
if (!(asm_compare_no_rd(ins1, GpuAsmPattern[0]) && asm_compare_no_rd(ins2, GpuAsmPattern[1])))
|
||||
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
|
||||
|
||||
// Both instructions should operate on the same register
|
||||
@@ -142,6 +142,12 @@ namespace ams::ldr::hoc::pcv::erista {
|
||||
if (rd != asm_get_rd(ins2))
|
||||
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
|
||||
|
||||
/* Verify the limit. */
|
||||
/* TODO: Make this a little bit cleaner at some point. */
|
||||
if (AsmGetImm16(ins1) != (GpuClkOsLimit & 0xFFFF) || AsmGetImm16(ins2) != (GpuClkOsLimit >> 16)) {
|
||||
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
|
||||
}
|
||||
|
||||
u32 max_clock;
|
||||
switch (C.eristaGpuUV) {
|
||||
case 0:
|
||||
@@ -158,8 +164,8 @@ namespace ams::ldr::hoc::pcv::erista {
|
||||
break;
|
||||
}
|
||||
u32 asm_patch[2] = {
|
||||
asm_set_rd(asm_set_imm16(asm_pattern[0], max_clock), rd),
|
||||
asm_set_rd(asm_set_imm16(asm_pattern[1], max_clock >> 16), rd)};
|
||||
asm_set_rd(asm_set_imm16(GpuAsmPattern[0], max_clock), rd),
|
||||
asm_set_rd(asm_set_imm16(GpuAsmPattern[1], max_clock >> 16), rd)};
|
||||
PATCH_OFFSET(ptr32, asm_patch[0]);
|
||||
PATCH_OFFSET(ptr32 + 1, asm_patch[1]);
|
||||
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
/*
|
||||
* Copyright (C) Switch-OC-Suite
|
||||
*
|
||||
* Copyright (c) 2023 hanai3Bi
|
||||
*
|
||||
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "../oc_common.hpp"
|
||||
#include "pcv_common.hpp"
|
||||
#include "pcv_asm.hpp"
|
||||
|
||||
namespace ams::ldr::hoc::pcv::erista {
|
||||
|
||||
static u32 maxEmcClocks[] = { C.eristaEmcMaxClock2, C.eristaEmcMaxClock1, C.eristaEmcMaxClock, };
|
||||
#define GET_MAX_OF_ARR(ARR) (*std::max_element(ARR, ARR + std::size(ARR)))
|
||||
|
||||
constexpr cvb_entry_t CpuCvbTableDefault[] = {
|
||||
// CPU_PLL_CVB_TABLE_ODN
|
||||
{ 204000, {721094}, { } },
|
||||
{ 306000, {754040}, { } },
|
||||
{ 408000, {786986}, { } },
|
||||
{ 510000, {819932}, { } },
|
||||
{ 612000, {852878}, { } },
|
||||
{ 714000, {885824}, { } },
|
||||
{ 816000, {918770}, { } },
|
||||
{ 918000, {951716}, { } },
|
||||
{ 1020000, {984662}, { -2875621, 358099, -8585} },
|
||||
{ 1122000, {1017608}, { -52225, 104159, -2816} },
|
||||
{ 1224000, {1050554}, { 1076868, 8356, -727} },
|
||||
{ 1326000, {1083500}, { 2208191, -84659, 1240} },
|
||||
{ 1428000, {1116446}, { 2519460, -105063, 1611} },
|
||||
{ 1581000, {1130000}, { 2889664, -122173, 1834} },
|
||||
{ 1683000, {1168000}, { 5100873, -279186, 4747} },
|
||||
{ 1785000, {1227500}, { 5100873, -279186, 4747} },
|
||||
{ },
|
||||
};
|
||||
|
||||
constexpr u32 CpuVoltOfficial = 1227;
|
||||
|
||||
constexpr u32 CpuVminOfficial = 825;
|
||||
|
||||
constexpr u32 CpuVoltL4T = 1257'000;
|
||||
|
||||
static const u32 cpuVoltDvfsPattern[] = { 1227, 1000, 100, 1000, 0 };
|
||||
static_assert(sizeof(cpuVoltDvfsPattern) == 0x14, "invalid cpuVoltDvfsPattern size");
|
||||
|
||||
static const u32 cpuVoltageThermalPattern[] = { 950, 1132, 0, 950, 1227, 0, 825, 1227, 15000, 825, 1170, 60000, 825, 1132, 80000 };
|
||||
static_assert(sizeof(cpuVoltageThermalPattern) == 0x3c, "invalid cpuVoltageThermalPattern size");
|
||||
|
||||
constexpr u32 GpuClkPllLimit = 2'600'000;
|
||||
constexpr u32 GpuClkPllMax = 921'600'000;
|
||||
constexpr u32 GpuVminOfficial = 810;
|
||||
|
||||
constexpr u16 CpuMinVolts[] = { 950, 850, 825, 810 };
|
||||
|
||||
static const u32 gpuVoltDvfsPattern[] = { 810, 1150, 1000, 100, 1000, 10, };
|
||||
static_assert(sizeof(gpuVoltDvfsPattern) == (sizeof(u32) * 6), "Invalid gpuVoltDvfsPattern");
|
||||
|
||||
static const u32 gpuVoltThermalPattern[] = { 950, 1132, 0, 810, 1132, 15000, 810, 1132, 30000, 810, 1132, 50000, 810, 1132, 70000, 810, 1132, 105000 };
|
||||
static_assert(sizeof(gpuVoltThermalPattern) == 0x48, "invalid gpuVoltageThermalPattern size");
|
||||
|
||||
/* GPU Max Clock asm Pattern:
|
||||
*
|
||||
* MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
|
||||
* sf | opc | | hw | imm16 | Rd
|
||||
* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
||||
* 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
|
||||
*
|
||||
* MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
|
||||
* sf | opc | | hw | imm16 | Rd
|
||||
* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
||||
* 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
|
||||
*/
|
||||
inline constexpr u32 GpuAsmPattern[] = { 0x52820000, 0x72A001C0 };
|
||||
|
||||
inline bool GpuMaxClockPatternFn(u32 *ptr32) {
|
||||
return asm_compare_no_rd(*ptr32, GpuAsmPattern[0]);
|
||||
};
|
||||
|
||||
constexpr cvb_entry_t GpuCvbTableDefault[] = {
|
||||
// NA_FREQ_CVB_TABLE
|
||||
{ 76800, {}, { 814294, 8144, -940, 808, -21583, 226, } },
|
||||
{ 153600, {}, { 856185, 8144, -940, 808, -21583, 226, } },
|
||||
{ 230400, {}, { 898077, 8144, -940, 808, -21583, 226, } },
|
||||
{ 307200, {}, { 939968, 8144, -940, 808, -21583, 226, } },
|
||||
{ 384000, {}, { 981860, 8144, -940, 808, -21583, 226, } },
|
||||
{ 460800, {}, { 1023751, 8144, -940, 808, -21583, 226, } },
|
||||
{ 537600, {}, { 1065642, 8144, -940, 808, -21583, 226, } },
|
||||
{ 614400, {}, { 1107534, 8144, -940, 808, -21583, 226, } },
|
||||
{ 691200, {}, { 1149425, 8144, -940, 808, -21583, 226, } },
|
||||
{ 768000, {}, { 1191317, 8144, -940, 808, -21583, 226, } },
|
||||
{ 844800, {}, { 1233208, 8144, -940, 808, -21583, 226, } },
|
||||
{ 921600, {}, { 1275100, 8144, -940, 808, -21583, 226, } },
|
||||
{ },
|
||||
};
|
||||
|
||||
constexpr u32 MemVoltHOS = 1125'000;
|
||||
constexpr u32 EmcClkMinFreq = 40800; /* 40.8 MHz table only exists on erista. */
|
||||
constexpr u32 EmcClkPllmLimit = 1866'000'000;
|
||||
|
||||
constexpr u32 MTC_TABLE_REV = 7;
|
||||
|
||||
void Patch(uintptr_t mapped_nso, size_t nso_size);
|
||||
|
||||
}
|
||||
@@ -268,7 +268,7 @@ namespace ams::ldr::hoc::pcv::mariko {
|
||||
Result GpuFreqMaxAsm(u32 *ptr32) {
|
||||
// Check if both two instructions match the pattern
|
||||
u32 ins1 = *ptr32, ins2 = *(ptr32 + 1);
|
||||
if (!(asm_compare_no_rd(ins1, asm_pattern[0]) && asm_compare_no_rd(ins2, asm_pattern[1]))) {
|
||||
if (!(asm_compare_no_rd(ins1, GpuAsmPattern[0]) && asm_compare_no_rd(ins2, GpuAsmPattern[1]))) {
|
||||
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
|
||||
}
|
||||
|
||||
@@ -301,8 +301,8 @@ namespace ams::ldr::hoc::pcv::mariko {
|
||||
}
|
||||
|
||||
u32 asm_patch[2] = {
|
||||
asm_set_rd(asm_set_imm16(asm_pattern[0], max_clock), rd),
|
||||
asm_set_rd(asm_set_imm16(asm_pattern[1], max_clock >> 16), rd)
|
||||
asm_set_rd(asm_set_imm16(GpuAsmPattern[0], max_clock), rd),
|
||||
asm_set_rd(asm_set_imm16(GpuAsmPattern[1], max_clock >> 16), rd)
|
||||
};
|
||||
|
||||
PATCH_OFFSET(ptr32, asm_patch[0]);
|
||||
|
||||
@@ -0,0 +1,129 @@
|
||||
/*
|
||||
* Copyright (C) Switch-OC-Suite
|
||||
*
|
||||
* Copyright (c) 2023 hanai3Bi
|
||||
*
|
||||
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "../oc_common.hpp"
|
||||
#include "pcv_common.hpp"
|
||||
#include "pcv_asm.hpp"
|
||||
|
||||
namespace ams::ldr::hoc::pcv::mariko {
|
||||
|
||||
constexpr cvb_entry_t CpuCvbTableDefault[] = {
|
||||
{ 204000, { 721589, -12695, 27 }, { } },
|
||||
{ 306000, { 747134, -14195, 27 }, { } },
|
||||
{ 408000, { 776324, -15705, 27 }, { } },
|
||||
{ 510000, { 809160, -17205, 27 }, { } },
|
||||
{ 612000, { 845641, -18715, 27 }, { } },
|
||||
{ 714000, { 885768, -20215, 27 }, { } },
|
||||
{ 816000, { 929540, -21725, 27 }, { } },
|
||||
{ 918000, { 976958, -23225, 27 }, { } },
|
||||
{ 1020000, { 1028021, -24725, 27 }, { 1120000 } },
|
||||
{ 1122000, { 1082730, -26235, 27 }, { 1120000 } },
|
||||
{ 1224000, { 1141084, -27735, 27 }, { 1120000 } },
|
||||
{ 1326000, { 1203084, -29245, 27 }, { 1120000 } },
|
||||
{ 1428000, { 1268729, -30745, 27 }, { 1120000 } },
|
||||
{ 1581000, { 1374032, -33005, 27 }, { 1120000 } },
|
||||
{ 1683000, { 1448791, -34505, 27 }, { 1120000 } },
|
||||
{ 1785000, { 1527196, -36015, 27 }, { 1120000 } },
|
||||
{ 1887000, { 1609246, -37515, 27 }, { 1120000 } },
|
||||
{ 1963500, { 1675751, -38635, 27 }, { 1120000 } },
|
||||
{ },
|
||||
};
|
||||
|
||||
constexpr u32 CpuClkOfficial = 1963'500;
|
||||
constexpr u32 CpuVoltOfficial = 1120;
|
||||
constexpr u32 CpuVminOfficial = 620;
|
||||
|
||||
static const u32 cpuVoltagePatchValues[] = { 850, 38, 1120, 1000, 100, 1000, 0 };
|
||||
static const s32 cpuVoltagePatchOffsets[] = { -2, -1, 5, 6, 7, 8, 9 };
|
||||
static_assert(sizeof(cpuVoltagePatchValues) == sizeof(cpuVoltagePatchOffsets), "Invalid cpuVoltagePatch size");
|
||||
|
||||
static const u32 cpuVoltThermalData[] = { 620, 1120, 20000, 620, 1120, 70000, 950, 1132, 0, 950, 1227, 0 };
|
||||
|
||||
static const u32 allowedCpuMaxFrequencies[] = { 1'963'500, 2'091'000, 2'193'000, 2'295'000, 2'397'000, 2'499'000, 2'601'000, 2'703'000, };
|
||||
|
||||
constexpr cvb_entry_t GpuCvbTableDefault[] = {
|
||||
// GPUB01_NA_CVB_TABLE
|
||||
{ 76800, {}, { 610000, } },
|
||||
{ 153600, {}, { 610000, } },
|
||||
{ 230400, {}, { 610000, } },
|
||||
{ 307200, {}, { 610000, } },
|
||||
{ 384000, {}, { 610000, } },
|
||||
{ 460800, {}, { 610000, } },
|
||||
{ 537600, {}, { 801688, -10900, -163, 298, -10599, 162, } },
|
||||
{ 614400, {}, { 824214, -5743, -452, 238, -6325, 81, } },
|
||||
{ 691200, {}, { 848830, -3903, -552, 119, -4030, -2, } },
|
||||
{ 768000, {}, { 891575, -4409, -584, 0, -2849, 39, } },
|
||||
{ 844800, {}, { 940071, -5367, -602, -60, -63, -93, } },
|
||||
{ 921600, {}, { 986765, -6637, -614, -179, 1905, -13, } },
|
||||
{ 998400, {}, { 1098475, -13529, -497, -179, 3626, 9, } },
|
||||
{ 1075200, {}, { 1163644, -12688, -648, 0, 1077, 40, } },
|
||||
{ 1152000, {}, { 1204812, -9908, -830, 0, 1469, 110, } },
|
||||
{ 1228800, {}, { 1277303, -11675, -859, 0, 3722, 313, } },
|
||||
{ 1267200, {}, { 1335531, -12567, -867, 0, 3681, 559, } },
|
||||
{ },
|
||||
};
|
||||
|
||||
constexpr u32 GpuClkPllMax = 1300'000'000;
|
||||
constexpr u32 GpuClkPllLimit = 2'600'000;
|
||||
constexpr u32 GpuVminOfficial = 610;
|
||||
|
||||
static const u32 gpuDVFSPattern[] = { 1050, 1000, 100, 1000, 10, };
|
||||
static const u32 gpuVoltThermalPattern[] = { 800, 1120, 0, 610, 1120, 20000, 610, 1120, 30000, 610, 1120, 50000, 610, 1120, 70000, 610, 1120, 90000, };
|
||||
static_assert(sizeof(gpuVoltThermalPattern) == 72, "Invalid gpuVoltThermalPattern");
|
||||
|
||||
/* GPU Max Clock asm Pattern:
|
||||
*
|
||||
* MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
|
||||
* sf | opc | | hw | imm16 | Rd
|
||||
* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
||||
* 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
|
||||
*
|
||||
* MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
|
||||
* sf | opc | | hw | imm16 | Rd
|
||||
* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
||||
* 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
|
||||
*/
|
||||
inline constexpr u32 GpuAsmPattern[] = { 0x52820000, 0x72A001C0 };
|
||||
|
||||
inline bool GpuMaxClockPatternFn(u32 *ptr32) {
|
||||
return asm_compare_no_rd(*ptr32, GpuAsmPattern[0]);
|
||||
}
|
||||
|
||||
constexpr emc_dvb_dvfs_table_t EmcDvbTableDefault[] = {
|
||||
{ 204000, { 637, 637, 637, } },
|
||||
{ 408000, { 637, 637, 637, } },
|
||||
{ 800000, { 637, 637, 637, } },
|
||||
{ 1065600, { 637, 637, 637, } },
|
||||
{ 1331200, { 650, 637, 637, } },
|
||||
{ 1600000, { 675, 650, 637, } },
|
||||
};
|
||||
|
||||
constexpr u32 EmcClkOSAlt = 1331'200;
|
||||
constexpr u32 EmcClkPllmLimit = 2133'000'000;
|
||||
constexpr u32 EmcVddqDefault = 600'000;
|
||||
constexpr u32 MemVdd2Default = 1100'000;
|
||||
|
||||
constexpr u32 MTC_TABLE_REV = 3;
|
||||
|
||||
void Patch(uintptr_t mapped_nso, size_t nso_size);
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user