multiple: fix stuff

loader: fix erista timing
overlay: fix clock setting bug
This commit is contained in:
souldbminersmwc
2025-10-04 19:11:40 -04:00
parent 95027bc317
commit 290329d285
6 changed files with 80 additions and 62 deletions

View File

@@ -44,7 +44,7 @@ volatile CustomizeTable C = {
* Value should be divided evenly by 12'500. * Value should be divided evenly by 12'500.
* Not enabled by default. * Not enabled by default.
*/ */
.commonEmcMemVolt = 1175000, .commonEmcMemVolt = 1237500,
/* Erista CPU: /* Erista CPU:
* - Max Voltage in mV * - Max Voltage in mV
@@ -60,7 +60,7 @@ volatile CustomizeTable C = {
* - System instabilities * - System instabilities
* - NAND corruption * - NAND corruption
*/ */
.eristaEmcMaxClock = 1862400, .eristaEmcMaxClock = 2227000,
/* Mariko CPU: /* Mariko CPU:
* - Max Voltage in mV: * - Max Voltage in mV:
@@ -92,15 +92,15 @@ volatile CustomizeTable C = {
.eristaCpuUV = 0, .eristaCpuUV = 0,
.eristaGpuUV = 0, .eristaGpuUV = 3,
.enableMarikoGpuUnsafeFreqs = DISABLED, .enableMarikoGpuUnsafeFreqs = DISABLED,
.enableEristaGpuUnsafeFreqs = DISABLED, .enableEristaGpuUnsafeFreqs = 1,
.enableMarikoCpuUnsafeFreqs = DISABLED, .enableMarikoCpuUnsafeFreqs = DISABLED,
.enableEristaCpuUnsafeFreqs = DISABLED, .enableEristaCpuUnsafeFreqs = 1,
.commonGpuVoltOffset = 0, .commonGpuVoltOffset = 0,
@@ -115,11 +115,11 @@ volatile CustomizeTable C = {
.t7_tWTR = 0, .t7_tWTR = 0,
.t8_tREFI = 0, .t8_tREFI = 0,
.mem_burst_latency = 0, .mem_burst_latency = 2,
.marikoCpuVmin = 600, .marikoCpuVmin = 600,
.eristaGpuVmin = 810, .eristaGpuVmin = 750,
.marikoGpuVmin = 610, .marikoGpuVmin = 610,
@@ -144,7 +144,7 @@ volatile CustomizeTable C = {
710 /* 1075 */, 710 /* 1075 */,
735 /* 1152 */, 735 /* 1152 */,
785 /* 1228 */, 785 /* 1228 */,
0 /* 1267 (Disabled by default) */, 800 /* 1267 */,
0 /* 1305 (Disabled by default) */, 0 /* 1305 (Disabled by default) */,
0 /* 1344 (Disabled by default) */, 0 /* 1344 (Disabled by default) */,
0 /* 1382 (Disabled by default) */, 0 /* 1382 (Disabled by default) */,
@@ -168,8 +168,8 @@ volatile CustomizeTable C = {
900 /* 768 */, 900 /* 768 */,
950 /* 844 */, 950 /* 844 */,
975 /* 921 */, 975 /* 921 */,
0 /* 998 (Disabled by default) */, 920 /* 998 (Disabled by default) */,
0 /* 1075 (Disabled by default) */, 975 /* 1075 (Disabled by default) */,
}, },
@@ -208,16 +208,16 @@ volatile CustomizeTable C = {
{ 714000, { 885768, -20215, 27 }, {} }, { 714000, { 885768, -20215, 27 }, {} },
{ 816000, { 929540, -21725, 27 }, {} }, { 816000, { 929540, -21725, 27 }, {} },
{ 918000, { 976958, -23225, 27 }, {} }, { 918000, { 976958, -23225, 27 }, {} },
{ 1020000, { 1028021, -24725, 27 }, { 1120000 } }, { 1020000, { 1028021, -24725, 27 }, { } },
{ 1122000, { 1082730, -26235, 27 }, { 1120000 } }, { 1122000, { 1082730, -26235, 27 }, { } },
{ 1224000, { 1141084, -27735, 27 }, { 1120000 } }, { 1224000, { 1141084, -27735, 27 }, { } },
{ 1326000, { 1203084, -29245, 27 }, { 1120000 } }, { 1326000, { 1203084, -29245, 27 }, { } },
{ 1428000, { 1268729, -30745, 27 }, { 1120000 } }, { 1428000, { 1268729, -30745, 27 }, { } },
{ 1581000, { 1374032, -33005, 27 }, { 1120000 } }, { 1581000, { 1374032, -33005, 27 }, { } },
{ 1683000, { 1448791, -34505, 27 }, { 1120000 } }, { 1683000, { 1448791, -34505, 27 }, { } },
{ 1785000, { 1527196, -36015, 27 }, { 1120000 } }, { 1785000, { 1527196, -36015, 27 }, { } },
{ 1887000, { 1609246, -37515, 27 }, { 1120000 } }, { 1887000, { 1609246, -37515, 27 }, { } },
{ 1963500, { 1675751, -38635, 27 }, { 1120000 } }, { 1963500, { 1675751, -38635, 27 }, { } },
}, },
.marikoCpuDvfsTableSLT = { .marikoCpuDvfsTableSLT = {
@@ -229,19 +229,19 @@ volatile CustomizeTable C = {
{ 714000, { 820558, -19915, 113 }, { } }, { 714000, { 820558, -19915, 113 }, { } },
{ 816000, { 853926, -20775, 113 }, { } }, { 816000, { 853926, -20775, 113 }, { } },
{ 918000, { 889361, -21625, 113 }, { } }, { 918000, { 889361, -21625, 113 }, { } },
{ 1020000, { 926862, -22485, 113 }, { 1120000 } }, { 1020000, { 926862, -22485, 113 }, { } },
{ 1122000, { 926862, -22485, 113 }, { 1120000 } }, { 1122000, { 926862, -22485, 113 }, { } },
{ 1224000, { 926862, -22485, 113 }, { 1120000 } }, { 1224000, { 926862, -22485, 113 }, { } },
{ 1326000, { 966431, -23345, 113 }, { 1120000 } }, { 1326000, { 966431, -23345, 113 }, { } },
{ 1428000, { 1008066, -24205, 113 }, { 1120000 } }, { 1428000, { 1008066, -24205, 113 }, { } },
{ 1581000, { 1051768, -25065, 113 }, { 1120000 } }, { 1581000, { 1051768, -25065, 113 }, { } },
{ 1683000, { 1097537, -25925, 113 }, { 1120000 } }, { 1683000, { 1097537, -25925, 113 }, { } },
{ 1785000, { 1145373, -26785, 113 }, { 1120000 } }, { 1785000, { 1145373, -26785, 113 }, { } },
{ 1887000, { 1195276, -27645, 113 }, { 1120000 } }, { 1887000, { 1195276, -27645, 113 }, { } },
{ 1963500, { 1274006, -29795, 113 }, { 1120000 } }, { 1963500, { 1274006, -29795, 113 }, { } },
{ 2091000, { 1349076, -33235, 113 }, { 1235000 } }, { 2091000, { 1349076, -33235, 113 }, { } },
{ 2193000, { 1386213, -33235, 113 }, { 1235000 } }, { 2193000, { 1386213, -33235, 113 }, { } },
{ 2295000, { 1445416, -34095, 113 }, { 1235000 } }, { 2295000, { 1445416, -34095, 113 }, { } },
}, },
/* - Erista GPU DVFS Table: /* - Erista GPU DVFS Table:
@@ -424,22 +424,22 @@ volatile CustomizeTable C = {
{ 714000, { 820558, -19915, 113 }, { } }, { 714000, { 820558, -19915, 113 }, { } },
{ 816000, { 853926, -20775, 113 }, { } }, { 816000, { 853926, -20775, 113 }, { } },
{ 918000, { 889361, -21625, 113 }, { } }, { 918000, { 889361, -21625, 113 }, { } },
{ 1020000, { 926862, -22485, 113 }, { 1120000 } }, { 1020000, { 926862, -22485, 113 }, { } },
{ 1122000, { 926862, -22485, 113 }, { 1120000 } }, { 1122000, { 926862, -22485, 113 }, { } },
{ 1224000, { 926862, -22485, 113 }, { 1120000 } }, { 1224000, { 926862, -22485, 113 }, { } },
{ 1326000, { 966431, -23345, 113 }, { 1120000 } }, { 1326000, { 966431, -23345, 113 }, { } },
{ 1428000, { 1008066, -24205, 113 }, { 1120000 } }, { 1428000, { 1008066, -24205, 113 }, { } },
{ 1581000, { 1051768, -25065, 113 }, { 1120000 } }, { 1581000, { 1051768, -25065, 113 }, { } },
{ 1683000, { 1097537, -25925, 113 }, { 1120000 } }, { 1683000, { 1097537, -25925, 113 }, { } },
{ 1785000, { 1145373, -26785, 113 }, { 1120000 } }, { 1785000, { 1145373, -26785, 113 }, { } },
{ 1887000, { 1195276, -27645, 113 }, { 1120000 } }, { 1887000, { 1195276, -27645, 113 }, { } },
{ 1963500, { 1274006, -29795, 113 }, { 1120000 } }, { 1963500, { 1274006, -29795, 113 }, { } },
{ 2091000, { 1349076, -33235, 113 }, { 1235000 } }, { 2091000, { 1349076, -33235, 113 }, { } },
{ 2193000, { 1386213, -33235, 113 }, { 1235000 } }, { 2193000, { 1386213, -33235, 113 }, { } },
{ 2295000, { 1445416, -34095, 113 }, { 1235000 } }, { 2295000, { 1445416, -34095, 113 }, { } },
{ 2397000, { 1490873, -34955, 113 }, { 1235000 } }, { 2397000, { 1490873, -34955, 113 }, { } },
{ 2499000, { 1580725, -35815, 113 }, { 1235000 } }, { 2499000, { 1580725, -35815, 113 }, { } },
{ 2601000, { 1702903, -36675, 113 }, { 1235000 } }, { 2601000, { 1702903, -36675, 113 }, { } },
}, },
.eristaCpuDvfsTableUnsafeFreqs = { .eristaCpuDvfsTableUnsafeFreqs = {
{ 204000, { 721094 }, {} }, { 204000, { 721094 }, {} },

View File

@@ -147,6 +147,15 @@
// write-to-precharge time for commands to the same bank in cycles // write-to-precharge time for commands to the same bank in cycles
const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8; const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
const u32 numOfRows = 65536;
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
// emc_clk_period = dram_clk / 2;
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.eristaEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
const u32 REFBW = MIN((u32)65536, REFRESH+64);
} }
namespace pcv::mariko { namespace pcv::mariko {
@@ -160,5 +169,14 @@
// write-to-precharge time for commands to the same bank in cycles // write-to-precharge time for commands to the same bank in cycles
const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8; const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
const u32 numOfRows = 131072;
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
// emc_clk_period = dram_clk / 2;
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
const u32 REFBW = MIN((u32)130944, REFRESH+64);
} }
} }

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@@ -204,12 +204,12 @@ Result GpuVmin(u32 *ptr) {
table->burst_mc_regs.mc_emem_arb_timing_ras = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2; table->burst_mc_regs.mc_emem_arb_timing_ras = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2;
table->burst_mc_regs.mc_emem_arb_timing_faw = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1; table->burst_mc_regs.mc_emem_arb_timing_faw = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1;
table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1; table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
//table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV); table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
//table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV); table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
// table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA; table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA; table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA; table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA; table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV); table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
// table->burst_mc_regs.mc_emem_arb_timing_ccdmw = CEIL(tCCDMW / MC_ARB_DIV) -1 + MC_ARB_SFA; // table->burst_mc_regs.mc_emem_arb_timing_ccdmw = CEIL(tCCDMW / MC_ARB_DIV) -1 + MC_ARB_SFA;
} }

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@@ -222,7 +222,7 @@ void ClockManager::Tick()
maxHz = this->GetMaxAllowedHz((SysClkModule)module, this->context->profile); maxHz = this->GetMaxAllowedHz((SysClkModule)module, this->context->profile);
nearestHz = this->GetNearestHz((SysClkModule)module, targetHz, maxHz); nearestHz = this->GetNearestHz((SysClkModule)module, targetHz, maxHz);
if (nearestHz != this->context->freqs[module] && this->context->enabled && !apmExtIsBoostMode(this->context->perfConfId) && !this->config->GetConfigValue(HocClkConfigValue_OverwriteBoostMode)) if (nearestHz != this->context->freqs[module] && this->context->enabled/* && !apmExtIsBoostMode(this->context->perfConfId) && !this->config->GetConfigValue(HocClkConfigValue_OverwriteBoostMode)*/)
{ {
FileUtils::LogLine( FileUtils::LogLine(
"[mgr] %s clock set : %u.%u MHz (target = %u.%u MHz)", "[mgr] %s clock set : %u.%u MHz (target = %u.%u MHz)",
@@ -232,12 +232,12 @@ void ClockManager::Tick()
Board::SetHz((SysClkModule)module, nearestHz); Board::SetHz((SysClkModule)module, nearestHz);
this->context->freqs[module] = nearestHz; this->context->freqs[module] = nearestHz;
} }
else // else
{ // {
Board::ResetToStockCpu(); // Board::ResetToStockCpu();
Board::ResetToStockGpu(); // Board::ResetToStockGpu();
} // }
// } // }
// } else { // } else {
// #define GOVERNOR_LOAD_THRESHOLD 80 // #define GOVERNOR_LOAD_THRESHOLD 80

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