multiple: fix stuff
loader: fix erista timing overlay: fix clock setting bug
This commit is contained in:
@@ -44,7 +44,7 @@ volatile CustomizeTable C = {
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* Value should be divided evenly by 12'500.
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* Not enabled by default.
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*/
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.commonEmcMemVolt = 1175000,
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.commonEmcMemVolt = 1237500,
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/* Erista CPU:
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* - Max Voltage in mV
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@@ -60,7 +60,7 @@ volatile CustomizeTable C = {
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* - System instabilities
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* - NAND corruption
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*/
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.eristaEmcMaxClock = 1862400,
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.eristaEmcMaxClock = 2227000,
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/* Mariko CPU:
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* - Max Voltage in mV:
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@@ -92,15 +92,15 @@ volatile CustomizeTable C = {
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.eristaCpuUV = 0,
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.eristaGpuUV = 0,
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.eristaGpuUV = 3,
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.enableMarikoGpuUnsafeFreqs = DISABLED,
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.enableEristaGpuUnsafeFreqs = DISABLED,
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.enableEristaGpuUnsafeFreqs = 1,
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.enableMarikoCpuUnsafeFreqs = DISABLED,
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.enableEristaCpuUnsafeFreqs = DISABLED,
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.enableEristaCpuUnsafeFreqs = 1,
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.commonGpuVoltOffset = 0,
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@@ -115,11 +115,11 @@ volatile CustomizeTable C = {
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.t7_tWTR = 0,
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.t8_tREFI = 0,
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.mem_burst_latency = 0,
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.mem_burst_latency = 2,
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.marikoCpuVmin = 600,
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.eristaGpuVmin = 810,
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.eristaGpuVmin = 750,
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.marikoGpuVmin = 610,
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@@ -144,7 +144,7 @@ volatile CustomizeTable C = {
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710 /* 1075 */,
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735 /* 1152 */,
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785 /* 1228 */,
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0 /* 1267 (Disabled by default) */,
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800 /* 1267 */,
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0 /* 1305 (Disabled by default) */,
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0 /* 1344 (Disabled by default) */,
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0 /* 1382 (Disabled by default) */,
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@@ -168,8 +168,8 @@ volatile CustomizeTable C = {
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900 /* 768 */,
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950 /* 844 */,
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975 /* 921 */,
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0 /* 998 (Disabled by default) */,
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0 /* 1075 (Disabled by default) */,
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920 /* 998 (Disabled by default) */,
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975 /* 1075 (Disabled by default) */,
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},
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@@ -208,16 +208,16 @@ volatile CustomizeTable C = {
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{ 714000, { 885768, -20215, 27 }, {} },
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{ 816000, { 929540, -21725, 27 }, {} },
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{ 918000, { 976958, -23225, 27 }, {} },
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{ 1020000, { 1028021, -24725, 27 }, { 1120000 } },
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{ 1122000, { 1082730, -26235, 27 }, { 1120000 } },
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{ 1224000, { 1141084, -27735, 27 }, { 1120000 } },
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{ 1326000, { 1203084, -29245, 27 }, { 1120000 } },
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{ 1428000, { 1268729, -30745, 27 }, { 1120000 } },
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{ 1581000, { 1374032, -33005, 27 }, { 1120000 } },
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{ 1683000, { 1448791, -34505, 27 }, { 1120000 } },
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{ 1785000, { 1527196, -36015, 27 }, { 1120000 } },
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{ 1887000, { 1609246, -37515, 27 }, { 1120000 } },
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{ 1963500, { 1675751, -38635, 27 }, { 1120000 } },
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{ 1020000, { 1028021, -24725, 27 }, { } },
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{ 1122000, { 1082730, -26235, 27 }, { } },
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{ 1224000, { 1141084, -27735, 27 }, { } },
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{ 1326000, { 1203084, -29245, 27 }, { } },
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{ 1428000, { 1268729, -30745, 27 }, { } },
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{ 1581000, { 1374032, -33005, 27 }, { } },
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{ 1683000, { 1448791, -34505, 27 }, { } },
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{ 1785000, { 1527196, -36015, 27 }, { } },
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{ 1887000, { 1609246, -37515, 27 }, { } },
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{ 1963500, { 1675751, -38635, 27 }, { } },
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},
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.marikoCpuDvfsTableSLT = {
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@@ -229,19 +229,19 @@ volatile CustomizeTable C = {
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{ 714000, { 820558, -19915, 113 }, { } },
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{ 816000, { 853926, -20775, 113 }, { } },
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{ 918000, { 889361, -21625, 113 }, { } },
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{ 1020000, { 926862, -22485, 113 }, { 1120000 } },
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{ 1122000, { 926862, -22485, 113 }, { 1120000 } },
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{ 1224000, { 926862, -22485, 113 }, { 1120000 } },
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{ 1326000, { 966431, -23345, 113 }, { 1120000 } },
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{ 1428000, { 1008066, -24205, 113 }, { 1120000 } },
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{ 1581000, { 1051768, -25065, 113 }, { 1120000 } },
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{ 1683000, { 1097537, -25925, 113 }, { 1120000 } },
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{ 1785000, { 1145373, -26785, 113 }, { 1120000 } },
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{ 1887000, { 1195276, -27645, 113 }, { 1120000 } },
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{ 1963500, { 1274006, -29795, 113 }, { 1120000 } },
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{ 2091000, { 1349076, -33235, 113 }, { 1235000 } },
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{ 2193000, { 1386213, -33235, 113 }, { 1235000 } },
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{ 2295000, { 1445416, -34095, 113 }, { 1235000 } },
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{ 1020000, { 926862, -22485, 113 }, { } },
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{ 1122000, { 926862, -22485, 113 }, { } },
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{ 1224000, { 926862, -22485, 113 }, { } },
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{ 1326000, { 966431, -23345, 113 }, { } },
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{ 1428000, { 1008066, -24205, 113 }, { } },
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{ 1581000, { 1051768, -25065, 113 }, { } },
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{ 1683000, { 1097537, -25925, 113 }, { } },
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{ 1785000, { 1145373, -26785, 113 }, { } },
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{ 1887000, { 1195276, -27645, 113 }, { } },
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{ 1963500, { 1274006, -29795, 113 }, { } },
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{ 2091000, { 1349076, -33235, 113 }, { } },
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{ 2193000, { 1386213, -33235, 113 }, { } },
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{ 2295000, { 1445416, -34095, 113 }, { } },
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},
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/* - Erista GPU DVFS Table:
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@@ -424,22 +424,22 @@ volatile CustomizeTable C = {
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{ 714000, { 820558, -19915, 113 }, { } },
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{ 816000, { 853926, -20775, 113 }, { } },
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{ 918000, { 889361, -21625, 113 }, { } },
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{ 1020000, { 926862, -22485, 113 }, { 1120000 } },
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{ 1122000, { 926862, -22485, 113 }, { 1120000 } },
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{ 1224000, { 926862, -22485, 113 }, { 1120000 } },
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{ 1326000, { 966431, -23345, 113 }, { 1120000 } },
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{ 1428000, { 1008066, -24205, 113 }, { 1120000 } },
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{ 1581000, { 1051768, -25065, 113 }, { 1120000 } },
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{ 1683000, { 1097537, -25925, 113 }, { 1120000 } },
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{ 1785000, { 1145373, -26785, 113 }, { 1120000 } },
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{ 1887000, { 1195276, -27645, 113 }, { 1120000 } },
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{ 1963500, { 1274006, -29795, 113 }, { 1120000 } },
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{ 2091000, { 1349076, -33235, 113 }, { 1235000 } },
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{ 2193000, { 1386213, -33235, 113 }, { 1235000 } },
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{ 2295000, { 1445416, -34095, 113 }, { 1235000 } },
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{ 2397000, { 1490873, -34955, 113 }, { 1235000 } },
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{ 2499000, { 1580725, -35815, 113 }, { 1235000 } },
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{ 2601000, { 1702903, -36675, 113 }, { 1235000 } },
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{ 1020000, { 926862, -22485, 113 }, { } },
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{ 1122000, { 926862, -22485, 113 }, { } },
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{ 1224000, { 926862, -22485, 113 }, { } },
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{ 1326000, { 966431, -23345, 113 }, { } },
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{ 1428000, { 1008066, -24205, 113 }, { } },
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{ 1581000, { 1051768, -25065, 113 }, { } },
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{ 1683000, { 1097537, -25925, 113 }, { } },
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{ 1785000, { 1145373, -26785, 113 }, { } },
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{ 1887000, { 1195276, -27645, 113 }, { } },
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{ 1963500, { 1274006, -29795, 113 }, { } },
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{ 2091000, { 1349076, -33235, 113 }, { } },
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{ 2193000, { 1386213, -33235, 113 }, { } },
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{ 2295000, { 1445416, -34095, 113 }, { } },
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{ 2397000, { 1490873, -34955, 113 }, { } },
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{ 2499000, { 1580725, -35815, 113 }, { } },
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{ 2601000, { 1702903, -36675, 113 }, { } },
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},
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.eristaCpuDvfsTableUnsafeFreqs = {
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{ 204000, { 721094 }, {} },
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@@ -147,6 +147,15 @@
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// write-to-precharge time for commands to the same bank in cycles
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const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
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const u32 numOfRows = 65536;
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// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
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// emc_clk_period = dram_clk / 2;
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// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
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const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.eristaEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
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const u32 REFBW = MIN((u32)65536, REFRESH+64);
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}
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namespace pcv::mariko {
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@@ -160,5 +169,14 @@
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// write-to-precharge time for commands to the same bank in cycles
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const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
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const u32 numOfRows = 131072;
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// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
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// emc_clk_period = dram_clk / 2;
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// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
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const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
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const u32 REFBW = MIN((u32)130944, REFRESH+64);
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}
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}
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@@ -204,12 +204,12 @@ Result GpuVmin(u32 *ptr) {
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table->burst_mc_regs.mc_emem_arb_timing_ras = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2;
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table->burst_mc_regs.mc_emem_arb_timing_faw = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1;
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table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
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//table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
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//table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
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// table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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// table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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// table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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// table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
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table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
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table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
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table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
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// table->burst_mc_regs.mc_emem_arb_timing_ccdmw = CEIL(tCCDMW / MC_ARB_DIV) -1 + MC_ARB_SFA;
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}
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@@ -222,7 +222,7 @@ void ClockManager::Tick()
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maxHz = this->GetMaxAllowedHz((SysClkModule)module, this->context->profile);
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nearestHz = this->GetNearestHz((SysClkModule)module, targetHz, maxHz);
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if (nearestHz != this->context->freqs[module] && this->context->enabled && !apmExtIsBoostMode(this->context->perfConfId) && !this->config->GetConfigValue(HocClkConfigValue_OverwriteBoostMode))
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if (nearestHz != this->context->freqs[module] && this->context->enabled/* && !apmExtIsBoostMode(this->context->perfConfId) && !this->config->GetConfigValue(HocClkConfigValue_OverwriteBoostMode)*/)
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{
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FileUtils::LogLine(
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"[mgr] %s clock set : %u.%u MHz (target = %u.%u MHz)",
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@@ -232,12 +232,12 @@ void ClockManager::Tick()
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Board::SetHz((SysClkModule)module, nearestHz);
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this->context->freqs[module] = nearestHz;
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}
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else
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{
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Board::ResetToStockCpu();
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Board::ResetToStockGpu();
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}
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}
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// else
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// {
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// Board::ResetToStockCpu();
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// Board::ResetToStockGpu();
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// }
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// }
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// } else {
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// #define GOVERNOR_LOAD_THRESHOLD 80
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BIN
dist/atmosphere/contents/00FF0000636C6BFF/exefs.nsp
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dist/atmosphere/contents/00FF0000636C6BFF/exefs.nsp
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dist/atmosphere/kips/hoc.kip
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dist/atmosphere/kips/hoc.kip
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