pcv/erista: improve timings (rdv & qpop)

This commit is contained in:
Lightos1 committed 2026-08-21 23:52:56 +02:00
1 parent 160e2483a6
commit c5fcc6c051
5 files changed
+67 -28

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@@ -60,10 +60,7 @@ namespace ams::ldr::hoc {
/* Write recovery time. */
const u32 tWR = 18;
/* TODO: Add comments (lazy) */
const double chip_delay = 1.109; /* ns. */
const double round_trip_delay = 0.5; /* ns. */
const double fly_by_time = chip_delay + round_trip_delay;
const double roundTripDelay = 0.5; /* ns. */
namespace pcv::erista {
const std::array<u32, 8> tRCD_values = { 18, 17, 16, 15, 14, 13, 12, 11 };
@@ -96,6 +93,16 @@ namespace ams::ldr::hoc {
inline u32 tR2W;
inline u32 rext;
inline u32 rdv;
inline u32 qpop;
inline u32 quse_width;
inline u32 quse;
inline u32 einput_duration;
inline u32 einput;
inline u32 qrst;
inline u32 ibdly;
inline u32 qsafe;
inline u32 tW2P;
inline u32 tWTPDEN;
inline u32 tW2R;
@@ -113,6 +120,12 @@ namespace ams::ldr::hoc {
inline double pdex2mrr;
inline u8 mrw2;
namespace {
double chipDelay = 1.165; /* Guessed. */
}
const double flyByTime = chipDelay + roundTripDelay;
}
namespace pcv::mariko {
@@ -176,6 +189,13 @@ namespace ams::ldr::hoc {
inline u32 pdex2mrr;
inline u8 mrw2;
/* TODO: Add comments (lazy) */
namespace {
const double chipDelay = 1.109; /* ns. */
}
const double flyByTime = chipDelay + roundTripDelay;
}
}
@@ -95,7 +95,7 @@ namespace ams::ldr::hoc::pcv::erista {
u32 wlIndex = 0;
for (u32 i = 0; i < std::size(rlMapDBI); ++i) {
if (rlMapDBI[i] == 32) {
if (rlMapDBI[i] == RL) {
rlIndex = i;
break;
}
@@ -122,6 +122,19 @@ namespace ams::ldr::hoc::pcv::erista {
tR2P = CEIL((RL * 0.426) - 2.0);
tR2W = FLOOR(FLOOR((5.0 / tCK_avg) + ((FLOOR(48.0 / WL) - 0.478) * 3.0)) / 1.501) + RL - (C.t6_tRTW * 3) + finetRTW;
rdv = RL + 19 + CEIL((flyByTime + tDQSCK_max) / tCK_avg);
qpop = rdv - 16;
quse_width = CEIL(((4.897 / tCK_avg) - FLOOR(2.538 / tCK_avg)) + 3.782);
quse = FLOOR(RL + ((5.082 / tCK_avg) + FLOOR(2.560 / tCK_avg))) - CEIL(4.820 / tCK_avg);
einput_duration = FLOOR(9.936 / tCK_avg) + 5.0 + quse_width;
einput = quse - CEIL(9.928 / tCK_avg);
u32 qrst_duration = FLOOR(8.399 - tCK_avg);
u32 qrstLow = MAX(static_cast<s32>(einput - qrst_duration - 2), static_cast<s32>(0));
qrst = PACK_U32(qrst_duration, qrstLow);
ibdly = PACK_U32_NIBBLE_HIGH_BYTE_LOW(1, quse - qrst_duration - 2.0);
qsafe = (einput_duration + 3) + MAX(MIN(qrstLow * rdv, qrst_duration + qrst_duration), einput);
tW2P = (CEIL(WL * 1.7303) * 2) - 5;
tWTPDEN = CEIL(((1.803 / tCK_avg) + MAX(RL + (2.694 / tCK_avg), static_cast<double>(tW2P))) + (BL / 2));
const s32 wlToRl = static_cast<s32>(WL) - static_cast<s32>(RL);
@@ -112,37 +112,37 @@ namespace ams::ldr::hoc::pcv::erista {
WRITE_PARAM_ALL_REG(table, emc_pchg2pden, GET_CYCLE_CEIL(1.763));
WRITE_PARAM_ALL_REG(table, emc_ar2pden, GET_CYCLE_CEIL(1.75));
WRITE_PARAM_ALL_REG(table, emc_pdex2cke, GET_CYCLE_CEIL(1.05));
WRITE_PARAM_ALL_REG(table, emc_act2pden, GET_CYCLE_CEIL(14.0));
WRITE_PARAM_ALL_REG(table, emc_act2pden, GET_CYCLE_CEIL(1.75)); /* todo verify. guessed. */
WRITE_PARAM_ALL_REG(table, emc_cke2pden, GET_CYCLE_CEIL(8.499));
WRITE_PARAM_ALL_REG(table, emc_pdex2mrr, GET_CYCLE_CEIL(pdex2mrr));
WRITE_PARAM_ALL_REG(table, emc_rw2pden, tWTPDEN);
/* Accept imperfection or prepare for suffering. */
// #if defined(AMS_BUILD_FOR_AUDITING) || defined(AMS_BUILD_FOR_DEBUGGING)
// WRITE_PARAM_ALL_REG(table, emc_einput, einput);
// WRITE_PARAM_ALL_REG(table, emc_einput_duration, einput_duration);
WRITE_PARAM_ALL_REG(table, emc_einput, einput);
WRITE_PARAM_ALL_REG(table, emc_einput_duration, einput_duration);
WRITE_PARAM_ALL_REG(table, emc_obdly, obdly);
// WRITE_PARAM_ALL_REG(table, emc_ibdly, ibdly);
// WRITE_PARAM_ALL_REG(table, emc_wdv_mask, wdv);
// WRITE_PARAM_ALL_REG(table, emc_quse_width, quse_width);
// WRITE_PARAM_ALL_REG(table, emc_quse, quse);
WRITE_PARAM_ALL_REG(table, emc_ibdly, ibdly);
WRITE_PARAM_ALL_REG(table, emc_wdv_mask, wdv);
WRITE_PARAM_ALL_REG(table, emc_quse_width, quse_width);
WRITE_PARAM_ALL_REG(table, emc_quse, quse);
WRITE_PARAM_ALL_REG(table, emc_wdv, wdv);
WRITE_PARAM_ALL_REG(table, emc_wsv, wsv);
WRITE_PARAM_ALL_REG(table, emc_wev, wev);
// WRITE_PARAM_ALL_REG(table, emc_qrst, qrst);
// WRITE_PARAM_ALL_REG(table, emc_tr_qrst, qrst);
// WRITE_PARAM_ALL_REG(table, emc_qsafe, qsafe);
// WRITE_PARAM_ALL_REG(table, emc_tr_qsafe, qsafe);
// WRITE_PARAM_ALL_REG(table, emc_tr_qpop, qpop);
// WRITE_PARAM_ALL_REG(table, emc_qpop, qpop);
// WRITE_PARAM_ALL_REG(table, emc_rdv, rdv);
// WRITE_PARAM_ALL_REG(table, emc_tr_rdv_mask, rdv + 2);
// WRITE_PARAM_ALL_REG(table, emc_rdv_early, rdv - 2);
// WRITE_PARAM_ALL_REG(table, emc_rdv_early_mask, rdv);
// WRITE_PARAM_ALL_REG(table, emc_rdv_mask, rdv + 2);
// WRITE_PARAM_ALL_REG(table, emc_tr_rdv, rdv);
WRITE_PARAM_ALL_REG(table, emc_qrst, qrst);
WRITE_PARAM_ALL_REG(table, emc_tr_qrst, qrst);
WRITE_PARAM_ALL_REG(table, emc_qsafe, qsafe);
WRITE_PARAM_ALL_REG(table, emc_tr_qsafe, qsafe);
WRITE_PARAM_ALL_REG(table, emc_tr_qpop, qpop);
WRITE_PARAM_ALL_REG(table, emc_qpop, qpop);
WRITE_PARAM_ALL_REG(table, emc_rdv, rdv);
WRITE_PARAM_ALL_REG(table, emc_tr_rdv_mask, rdv + 2);
WRITE_PARAM_ALL_REG(table, emc_rdv_early, rdv - 2);
WRITE_PARAM_ALL_REG(table, emc_rdv_early_mask, rdv);
WRITE_PARAM_ALL_REG(table, emc_rdv_mask, rdv + 2);
WRITE_PARAM_ALL_REG(table, emc_tr_rdv, rdv);
table->emc_mrw2 = (table->emc_mrw2 & ~0xFFu) | static_cast<u32>(mrw2);
// table->dram_timings.rl = RL;
table->dram_timings.rl = RL;
// #endif
constexpr double MC_ARB_DIV = 4.0;
@@ -165,7 +165,7 @@ namespace ams::ldr::hoc::pcv::mariko {
tRATM = CEIL((tRTM - 10.0) + (RL * 0.426));
/* Read data valid: Read command -> data ready to be latched into the registers. */
rdv = RL + 16 + CEIL((fly_by_time + tDQSCK_max) / tCK_avg);
rdv = RL + 16 + CEIL((flyByTime + tDQSCK_max) / tCK_avg);
/* Read command -> data poppable at the pad macros, 14 cycles ahead of rdv. */
qpop = rdv - 14;
@@ -1252,6 +1252,11 @@ class RamSubmenuGui : public MiscGui {
NamedValue("2361 MHz", 2361600),
NamedValue("2380 MHz", 2380800),
NamedValue("2400 MHz", 2400000, "JEDEC."),
NamedValue("2419 MHz", 2419200),
NamedValue("2438 MHz", 2438400),
NamedValue("2457 MHz", 2457600),
NamedValue("2476 MHz", 2476800),
NamedValue("2496 MHz", 2496000),
};
} else {
emcMaxClock = {
@@ -1880,7 +1885,8 @@ class RamLatenciesSubmenuGui : public MiscGui {
kFreqOptions = {
1633000, 1666000, 1700000, 1733000, 1800000, 1833000, 1862400, 1881600, 1900800, 1920000, 1939200, 1958400,
1977600, 1996800, 2016000, 2035200, 2054400, 2073600, 2092800, 2112000, 2131200, 2150400, 2169600, 2188800,
2208000, 2227200, 2246400, 2265600, 2284800, 2304000, 2323200, 2342400, 2361600, 2380800, 2400000,
2208000, 2227200, 2246400, 2265600, 2284800, 2304000, 2323200, 2342400, 2361600, 2380800, 2400000, 2419200,
2438400, 2457600, 2476800, 2496000,
};
}
@@ -2730,7 +2736,7 @@ class GpuCustomTableSubmenuGui : public MiscGui {
NamedValue("875mV", 875), NamedValue("880mV", 880), NamedValue("885mV", 885), NamedValue("890mV", 890), NamedValue("895mV", 895),
NamedValue("900mV", 900), NamedValue("905mV", 905), NamedValue("910mV", 910), NamedValue("915mV", 915), NamedValue("920mV", 920),
NamedValue("925mV", 925), NamedValue("930mV", 930), NamedValue("935mV", 935), NamedValue("940mV", 940), NamedValue("945mV", 945),
NamedValue("950mV", 950), NamedValue("955mV", 955), NamedValue("960mV", 960), NamedValue("965mV", 965), NamedValue("970mV", 970),
NamedValue("950mV", 950), NamedValue("955mV", 955), NamedValue("960mV", 960), NamedValue("965mV", 965), NamedValue("970mV", 970),
NamedValue("975mV", 975), NamedValue("980mV", 980), NamedValue("985mV", 985), NamedValue("990mV", 990), NamedValue("995mV", 995),
};