remove t2 cap, add minor timing tweaks
This commit is contained in:
@@ -59,10 +59,6 @@ volatile CustomizeTable C = {
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.t7_tWTR = 0,
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.t8_tREFI = 0,
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/* At 1333WL, for some reason (incorrect ram timing config in mtc table?), tRP causes crashes at high reductions - 2 seems to be the most common limit. */
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/* This is a lazy workaround until I find the issue... */
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.t2_tRP_cap = 1,
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/* Frequency where non low timings gets used. */
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.timingEmcTbreak = DISABLED,
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.low_t1_tRCD = 0,
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@@ -86,8 +86,6 @@ struct CustomizeTable {
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u32 t7_tWTR;
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u32 t8_tREFI;
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u32 t2_tRP_cap;
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u32 timingEmcTbreak;
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u32 low_t1_tRCD;
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u32 low_t2_tRP;
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@@ -135,14 +135,9 @@ namespace ams::ldr::hoc::pcv::mariko {
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/* At 1333WL, for some reason (incorrect ram timing config in mtc table?), tRP causes crashes at high reductions - 2 seems to be the most common limit. */
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/* This is a lazy workaround until I find the issue... */
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const bool lowFreq = freq < C.timingEmcTbreak;
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volatile u32 tRPpbIndex = lowFreq ? C.low_t2_tRP : C.t2_tRP;
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if (WL == WL_1331) {
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tRPpbIndex = MIN(C.t2_tRP_cap, tRPpbIndex);
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}
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tRCD = tRCD_values[lowFreq ? C.low_t1_tRCD : C.t1_tRCD];
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tRPpb = tRP_values[tRPpbIndex];
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tRPpb = tRP_values[lowFreq ? C.low_t2_tRP : C.t2_tRP];
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tRAS = tRAS_values[lowFreq ? C.low_t3_tRAS : C.t3_tRAS];
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tRRD = tRRD_values[lowFreq ? C.low_t4_tRRD : C.t4_tRRD];
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tRFCpb = tRFC_values[lowFreq ? C.low_t5_tRFC : C.t5_tRFC];
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@@ -324,13 +324,13 @@ namespace ams::ldr::hoc::pcv::erista {
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constexpr u32 AtomsPerDvfsPulse = 0x7;
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constexpr u32 McEmcSameFreq = 0x0;
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constexpr u32 ExpiringSoonSlackThreshold = 0xC; /* 0xC? */
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const u32 PriorityInversionIsoThreshold = GET_CYCLE_CEIL(7.5);
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constexpr u32 ExpiringSoonSlackThreshold = 0xC;
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const u32 priorityInversionIsoThreshold = GET_CYCLE_CEIL(7.5);
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constexpr u32 EmcReqB2bXfer = 0x0;
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const u32 PriorityInversionThreshold = GET_CYCLE_CEIL(22.5);
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const u32 Bc2aaHoldoffThreshold = table->burst_mc_regs.mc_emem_arb_timing_rc + 1;
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const u32 priorityInversionThreshold = GET_CYCLE_CEIL(22.5);
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const u32 bc2aaHoldoffThreshold = table->burst_mc_regs.mc_emem_arb_timing_rc + 1;
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const u32 mc_emem_arb_misc0 = (AtomsPerDvfsPulse << 28) | (McEmcSameFreq << 27) | (ExpiringSoonSlackThreshold << 21) | (PriorityInversionIsoThreshold << 16) | (EmcReqB2bXfer << 15) | (PriorityInversionThreshold << 8) | (Bc2aaHoldoffThreshold << 0);
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const u32 mc_emem_arb_misc0 = (AtomsPerDvfsPulse << 28) | (McEmcSameFreq << 27) | (ExpiringSoonSlackThreshold << 21) | (priorityInversionIsoThreshold << 16) | (EmcReqB2bXfer << 15) | (priorityInversionThreshold << 8) | (bc2aaHoldoffThreshold << 0);
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table->burst_mc_regs.mc_emem_arb_misc0 = mc_emem_arb_misc0;
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u32 mpcorer_ptsa_rate = MIN(static_cast<u32>(227), (table->rate_khz / 1600000) * 208);
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@@ -35,7 +35,7 @@ namespace ams::ldr::hoc::pcv::mariko {
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}
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}
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/* Default value is 800mV. */
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/* Default value is 1050mV. */
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if (C.marikoGpuVmax) {
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PATCH_OFFSET(ptr + 1, C.marikoGpuVmax);
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}
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@@ -488,17 +488,26 @@ namespace ams::ldr::hoc::pcv::mariko {
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da_covers |= (w_cover << 16);
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table->burst_mc_regs.mc_emem_arb_da_covers = da_covers;
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constexpr u32 AtomsPerDvfsPulse = 0x7;
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constexpr u32 McEmcSameFreq = 0x0;
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/* On certain frequencies (2966, 3100, 3133 and 3200 MHz), ExpiringSoonSlackThreshold has a value of 0x12. */
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/* But 0x13 is good enough for now. */
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constexpr u32 ExpiringSoonSlackThreshold = 0x13;
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const u32 PriorityInversionIsoThreshold = GET_CYCLE_CEIL(7.5);
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constexpr u32 EmcReqB2bXfer = 0x0;
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const u32 PriorityInversionThreshold = GET_CYCLE_CEIL(22.5);
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const u32 Bc2aaHoldoffThreshold = table->burst_mc_regs.mc_emem_arb_timing_rc + 1;
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constexpr u32 AtomsPerDvfsPulse = 0x7;
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constexpr u32 McEmcSameFreq = 0x0;
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const u32 expiringSoonSlackThreshold = [&] {
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switch (table->rate_khz) {
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case 2966000:
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case 3100000:
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case 3133000:
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case 3200000:
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return 0x12u;
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default:
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return 0x13u;
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}
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}();
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const u32 mc_emem_arb_misc0 = (AtomsPerDvfsPulse << 28) | (McEmcSameFreq << 27) | (ExpiringSoonSlackThreshold << 21) | (PriorityInversionIsoThreshold << 16) | (EmcReqB2bXfer << 15) | (PriorityInversionThreshold << 8) | (Bc2aaHoldoffThreshold << 0);
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const u32 priorityInversionIsoThreshold = GET_CYCLE_CEIL(7.5);
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constexpr u32 EmcReqB2bXfer = 0x0;
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const u32 priorityInversionThreshold = GET_CYCLE_CEIL(22.5);
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const u32 bc2aaHoldoffThreshold = table->burst_mc_regs.mc_emem_arb_timing_rc + 1;
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const u32 mc_emem_arb_misc0 = (AtomsPerDvfsPulse << 28) | (McEmcSameFreq << 27) | (expiringSoonSlackThreshold << 21) | (priorityInversionIsoThreshold << 16) | (EmcReqB2bXfer << 15) | (priorityInversionThreshold << 8) | (bc2aaHoldoffThreshold << 0);
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table->burst_mc_regs.mc_emem_arb_misc0 = mc_emem_arb_misc0;
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table->la_scale_regs.mc_mll_mpcorer_ptsa_rate = 0x115;
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@@ -934,14 +943,11 @@ namespace ams::ldr::hoc::pcv::mariko {
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} __attribute__((packed)) cmd;
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I2cSession _session;
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Result res = i2cOpenSession(&_session, dev);
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if (R_FAILED(res)) {
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return res;
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}
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R_TRY(i2cOpenSession(&_session, dev));
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cmd.reg = reg;
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cmd.val = val;
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res = i2csessionSendAuto(&_session, &cmd, sizeof(cmd), I2cTransactionOption_All);
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cmd.reg = reg;
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cmd.val = val;
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Result res = i2csessionSendAuto(&_session, &cmd, sizeof(cmd), I2cTransactionOption_All);
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i2csessionClose(&_session);
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return res;
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}
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@@ -978,10 +984,6 @@ namespace ams::ldr::hoc::pcv::mariko {
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Result resultI2C = I2cSet_U8(I2cDevice_Max77812_2, 0x25, (emc_uv - uv_min) / uv_step);
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i2cExit();
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if (R_SUCCEEDED(resultI2C)) {
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R_SUCCEED();
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}
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return resultI2C;
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}
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@@ -109,8 +109,6 @@ typedef enum {
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KipConfigValue_low_t7_tWTR,
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KipConfigValue_low_t8_tREFI,
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KipConfigValue_t2_tRP_cap,
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KipConfigValue_read_latency_1333,
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KipConfigValue_read_latency_1600,
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KipConfigValue_read_latency_1866,
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@@ -391,9 +389,6 @@ static inline const char* hocclkFormatConfigValue(HocClkConfigValue val, bool pr
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case KipConfigValue_low_t8_tREFI:
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return pretty ? "Low T8 - tREFI" : "low_t7_tREFI";
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case KipConfigValue_t2_tRP_cap:
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return pretty ? "t2 - trp 1333WL Cap" : "t2_tRP_cap";
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case KipConfigValue_read_latency_1333:
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return pretty ? "1333 Read Latency" : "read_latency_1333";
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case KipConfigValue_read_latency_1600:
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@@ -666,7 +661,6 @@ static inline uint64_t hocclkValidConfigValue(HocClkConfigValue val, uint64_t in
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case KipConfigValue_low_t6_tRTW:
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case KipConfigValue_low_t7_tWTR:
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case KipConfigValue_low_t8_tREFI:
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case KipConfigValue_t2_tRP_cap:
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case KipConfigValue_read_latency_1333:
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case KipConfigValue_read_latency_1600:
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case KipConfigValue_read_latency_1866:
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@@ -320,13 +320,6 @@ std::vector<std::string> ConfigInfoStrings(HocClkConfigValue val, bool isMariko,
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"Write To Read (Low bracket)",
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"Default: 0"
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};
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case KipConfigValue_t2_tRP_cap:
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return {
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"Cap for t2 when 1333WL is used.",
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"The default value is sufficient for most RAMs but some may need a lower value",
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"Default: 2"
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};
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case KipConfigValue_t6_tRTW_fine_tune:
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return {
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"Fine-tunes the raw calculation of t6",
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@@ -1424,12 +1424,10 @@ class RamTimingsSubmenuGui : public MiscGui {
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const s32 t7 = (s32)cfgPtr->values[KipConfigValue_t7_tWTR];
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const s32 lt6 = (s32)cfgPtr->values[KipConfigValue_low_t6_tRTW];
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const s32 lt7 = (s32)cfgPtr->values[KipConfigValue_low_t7_tWTR];
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const s32 t2c = (s32)cfgPtr->values[KipConfigValue_t2_tRP_cap];
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const uint32_t tbk = (uint32_t)cfgPtr->values[KipConfigValue_timingEmcTbreak];
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const tsl::Color cT6 = tsl::Color(4, 14, 15, 15);
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const tsl::Color cT7 = tsl::Color(15, 9, 2, 15);
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const tsl::Color cT2 = tsl::Color(12, 4, 15, 15);
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const tsl::Color cAxis = tsl::Color(5, 5, 5, 15);
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const tsl::Color cTbk = tsl::Color(7, 7, 7, 10);
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@@ -1495,12 +1493,6 @@ class RamTimingsSubmenuGui : public MiscGui {
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drawTimingLine(lt6, t6, cT6);
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drawTimingLine(lt7, t7, cT7);
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// t2 tRP cap: constant line
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s32 yT2 = valY(t2c) + 1;
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renderer->drawRect(gx, yT2, gw, 2, cT2);
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renderer->drawCircle(gx, yT2 + 1, 3, true, cT2);
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renderer->drawCircle(gx + gw - 1, yT2 + 1, 3, true, cT2);
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// X-axis ruler with sideways bitmap-font labels
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static const uint8_t kDigBmp[10][5] = {
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{ 7, 5, 5, 5, 7 }, { 6, 2, 2, 2, 7 }, { 7, 1, 7, 4, 7 }, { 7, 1, 3, 1, 7 }, { 5, 5, 7, 1, 1 },
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@@ -1537,15 +1529,12 @@ class RamTimingsSubmenuGui : public MiscGui {
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renderer->drawString("t6 tRTW", false, gx + 17, ly + 5, 12, cT6);
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renderer->drawRect(gx + 80, ly, 14, 3, cT7);
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renderer->drawString("t7 tWTR", false, gx + 97, ly + 5, 12, cT7);
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renderer->drawRect(gx + 165, ly, 14, 3, cT2);
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renderer->drawString("t2 cap", false, gx + 182, ly + 5, 12, cT2);
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});
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tbreakGraph->setBoundaries(0, 0, tsl::cfg::FramebufferWidth, 150);
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this->listElement->addItem(tbreakGraph);
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}
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addConfigButton(KipConfigValue_timingEmcTbreak, "RAM-Timing tBreak", ValueRange(0, 1, 1, "", 1), "tBreak", &thresholdsDisabled, {},
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timingTbreakFreqs, false, true);
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addConfigButton(KipConfigValue_timingEmcTbreak, "RAM-Timing tBreak", ValueRange(0, 1, 1, "", 1), "tBreak", &thresholdsDisabled, {}, timingTbreakFreqs, false, true);
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addConfigTrackbar(KipConfigValue_low_t1_tRCD, "Low t1 tRCD", ValueRange(0, 7, 1));
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addConfigTrackbar(KipConfigValue_low_t2_tRP, "Low t2 tRP", ValueRange(0, 7, 1));
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addConfigTrackbar(KipConfigValue_low_t3_tRAS, "Low t3 tRAS", ValueRange(0, 9, 1));
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@@ -1559,7 +1548,6 @@ class RamTimingsSubmenuGui : public MiscGui {
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spacer->setBoundaries(0, 0, tsl::cfg::FramebufferWidth, 8);
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this->listElement->addItem(spacer);
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}
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addConfigTrackbar(KipConfigValue_t2_tRP_cap, "1333WL t2 RP Cap", ValueRange(0, 8, 1));
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}
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addMappedConfigTrackbar(KipConfigValue_t6_tRTW_fine_tune, "t6 tRTW Fine Tune", { 0xFFFFFFFEu, 0xFFFFFFFFu, 0u, 1u, 2u },
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{ "-2", "-1", " 0", "+1", "+2" });
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@@ -95,7 +95,6 @@ namespace kip {
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CUST_WRITE_FIELD_BATCH(&table, low_t6_tRTW, config::GetConfigValue(KipConfigValue_low_t6_tRTW));
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CUST_WRITE_FIELD_BATCH(&table, low_t7_tWTR, config::GetConfigValue(KipConfigValue_low_t7_tWTR));
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CUST_WRITE_FIELD_BATCH(&table, low_t8_tREFI, config::GetConfigValue(KipConfigValue_low_t8_tREFI));
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CUST_WRITE_FIELD_BATCH(&table, t2_tRP_cap, config::GetConfigValue(KipConfigValue_t2_tRP_cap));
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CUST_WRITE_FIELD_BATCH(&table, readLatency1333, config::GetConfigValue(KipConfigValue_read_latency_1333));
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CUST_WRITE_FIELD_BATCH(&table, readLatency1600, config::GetConfigValue(KipConfigValue_read_latency_1600));
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@@ -281,7 +280,6 @@ namespace kip {
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configValues.values[KipConfigValue_low_t6_tRTW] = cust_get_low_tRTW(&table);
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configValues.values[KipConfigValue_low_t7_tWTR] = cust_get_low_tWTR(&table);
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configValues.values[KipConfigValue_low_t8_tREFI] = cust_get_low_tREFI(&table);
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configValues.values[KipConfigValue_t2_tRP_cap] = cust_get_tRP_cap(&table);
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configValues.values[KipConfigValue_read_latency_1333] = cust_get_read_latency_1333(&table);
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configValues.values[KipConfigValue_read_latency_1600] = cust_get_read_latency_1600(&table);
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@@ -54,8 +54,6 @@ namespace kip {
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u32 t7_tWTR;
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u32 t8_tREFI;
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u32 t2_tRP_cap;
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u32 timingEmcTbreak;
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u32 low_t1_tRCD;
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u32 low_t2_tRP;
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@@ -269,9 +267,6 @@ namespace kip {
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static inline bool cust_set_tREFI(const char *p, u32 v) {
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CUST_WRITE_FIELD(p, t8_tREFI, v);
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}
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static inline bool cust_set_tRP_cap(const char *p, u32 v) {
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CUST_WRITE_FIELD(p, t2_tRP_cap, v);
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}
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static inline bool cust_set_timing_emc_tbreak(const char *p, u32 v) {
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CUST_WRITE_FIELD(p, timingEmcTbreak, v);
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}
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@@ -484,9 +479,6 @@ namespace kip {
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static inline u32 cust_get_tREFI(const CustomizeTable *t) {
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return CUST_GET_FIELD(t, t8_tREFI);
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}
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static inline u32 cust_get_tRP_cap(const CustomizeTable *t) {
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return CUST_GET_FIELD(t, t2_tRP_cap);
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}
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static inline u32 cust_get_timing_emc_tbreak(const CustomizeTable *t) {
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return CUST_GET_FIELD(t, timingEmcTbreak);
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}
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Block a user