pcv::mariko: change rdv timing formular to match specifications according to t124

Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp

@@ -38,6 +38,7 @@ namespace ams::ldr::hoc {
 
     /* DQS output access time from CK_t/CK_c. */
     const double tDQSCK_max = 3.5;
+
     /* Write preamble. (tCK) */
     const u32 tWPRE = 2;
 
@@ -59,6 +60,11 @@ namespace ams::ldr::hoc {
     /* Write recovery time. */
     const u32 tWR = 18;
 
+    /* TODO: Add comments (lazy) */
+    const double chip_delay       = 1.109; /* ps. */
+    const double round_trip_delay = 0.5;   /* ps. */
+    const double fly_by_time      = chip_delay + round_trip_delay;
+
     namespace pcv::erista {
         const std::array<u32,       8> tRCD_values    = { 18, 17, 16, 15, 14, 13, 12, 11 };
         const std::array<u32,       8> tRP_values     = { 18, 17, 16, 15, 14, 13, 12, 11 };

Source/Atmosphere/stratosphere/loader/source/oc/pcv/mariko/calculate_timings_mariko.cpp

@@ -164,8 +164,12 @@ namespace ams::ldr::hoc::pcv::mariko {
         tRTM  = FLOOR((10.0 + RL) + (3.502 / tCK_avg)) + FLOOR(7.489 / tCK_avg);
         tRATM = CEIL((tRTM - 10.0) + (RL * 0.426));
 
-        rdv               = RL + FLOOR((5.105 / tCK_avg) + 17.017);
+        /* Read data valid: Read command -> data ready to be latched into the registers. */
+        rdv               = RL + 16 + CEIL((fly_by_time + tDQSCK_max) / tCK_avg);
+
+        /* Read command -> data poppable at the pad macros, 14 cycles ahead of rdv. */
         qpop              = rdv - 14;
+
         quse_width        = CEIL(((4.897 / tCK_avg) - FLOOR(2.538 / tCK_avg)) + 3.782);
         quse              = FLOOR(RL + ((5.082 / tCK_avg) + FLOOR(2.560 / tCK_avg))) - CEIL(4.820 / tCK_avg);
         einput_duration   = FLOOR(9.936 / tCK_avg) + 5.0 + quse_width;

Source/Atmosphere/stratosphere/loader/source/oc/pcv/mariko/pcv_mariko_mtc.cpp

@@ -36,6 +36,8 @@ namespace ams::ldr::hoc::pcv::mariko {
          *     https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
          *     Section 18.11.1:  MC Registers
          *     Section 18.11.2: EMC Registers
+         *
+         * Additional information from reverse-engineering public Tegra K1 (T124) memory characterization tools.
          */
 
         #define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \