git subrepo push libraries

subrepo:
  subdir:   "libraries"
  merged:   "0c0bb815"
upstream:
  origin:   "https://github.com/Atmosphere-NX/Atmosphere-libs"
  branch:   "master"
  commit:   "0c0bb815"
git-subrepo:
  version:  "0.4.1"
  origin:   "???"
  commit:   "???"

.gitignore

@@ -95,4 +95,6 @@ dkms.conf
 **/build_nintendo_nx_x64
 **/build_nintendo_nx_x86
 
+package3
+
 stratosphere/test/

Makefile

@@ -13,9 +13,29 @@ ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
     AMSREV := $(AMSREV)-dirty
 endif
 
-COMPONENTS := fusee stratosphere mesosphere exosphere thermosphere troposphere libraries
+COMPONENTS := fusee stratosphere mesosphere exosphere emummc thermosphere troposphere libraries
 
 all: $(COMPONENTS)
+	$(eval MAJORVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MAJOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval MINORVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MINOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval MICROVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MICRO\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval S_MAJORVER = $(shell grep 'define ATMOSPHERE_SUPPORTED_HOS_VERSION_MAJOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval S_MINORVER = $(shell grep 'define ATMOSPHERE_SUPPORTED_HOS_VERSION_MINOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval S_MICROVER = $(shell grep 'define ATMOSPHERE_SUPPORTED_HOS_VERSION_MICRO\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	@python fusee/build_package3.py $(CURDIR) release $(AMSHASH) $(MAJORVER) $(MINORVER) $(MICROVER) 0 $(S_MAJORVER) $(S_MINORVER) $(S_MICROVER) 0
+	@echo "Built package3!"
 
 thermosphere:
 	$(MAKE) -C thermosphere all
@@ -32,6 +52,9 @@ mesosphere: exosphere libraries
 troposphere: stratosphere
 	$(MAKE) -C troposphere all
 
+emummc:
+	$(MAKE) -C emummc all
+
 fusee: exosphere mesosphere stratosphere
 	$(MAKE) -C $@ all
 
@@ -41,6 +64,11 @@ libraries:
 clean:
 	$(MAKE) -C fusee clean
 	$(MAKE) -C emummc clean
+	$(MAKE) -C libraries clean
+	$(MAKE) -C exosphere clean
+	$(MAKE) -C thermosphere clean
+	$(MAKE) -C mesosphere clean
+	$(MAKE) -C stratosphere clean
 	rm -rf out
 
 dist-no-debug: all
@@ -63,13 +91,13 @@ dist-no-debug: all
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/config_templates
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/config
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/flags
-	touch atmosphere-$(AMSVER)/atmosphere/flags/clean_stratosphere_for_0.19.0.flag
-	cp fusee/fusee-primary/fusee-primary.bin atmosphere-$(AMSVER)/atmosphere/reboot_payload.bin
-	cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
-	cp config_templates/BCT.ini atmosphere-$(AMSVER)/atmosphere/config_templates/BCT.ini
+	cp fusee/fusee.bin atmosphere-$(AMSVER)/atmosphere/reboot_payload.bin
+	cp fusee/package3 atmosphere-$(AMSVER)/atmosphere/package3
+	cp config_templates/stratosphere.ini atmosphere-$(AMSVER)/atmosphere/config_templates/stratosphere.ini
 	cp config_templates/override_config.ini atmosphere-$(AMSVER)/atmosphere/config_templates/override_config.ini
 	cp config_templates/system_settings.ini atmosphere-$(AMSVER)/atmosphere/config_templates/system_settings.ini
 	cp config_templates/exosphere.ini atmosphere-$(AMSVER)/atmosphere/config_templates/exosphere.ini
+	mkdir config_templates/kip_patches
 	cp -r config_templates/kip_patches atmosphere-$(AMSVER)/atmosphere/kip_patches
 	cp -r config_templates/hbl_html atmosphere-$(AMSVER)/atmosphere/hbl_html
 	mkdir -p atmosphere-$(AMSVER)/stratosphere_romfs/atmosphere/contents/0100000000000008
@@ -96,13 +124,10 @@ dist-no-debug: all
 	cp troposphere/reboot_to_payload/reboot_to_payload.nro atmosphere-$(AMSVER)/switch/reboot_to_payload.nro
 	cp troposphere/daybreak/daybreak.nro atmosphere-$(AMSVER)/switch/daybreak.nro
 	cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER).zip ./*; cd ../;
-	cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
-	cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip ./*; cd ../;
-	rm -r atmosphere-$(AMSVER)
+	rm -rf atmosphere-$(AMSVER)
 	mkdir out
 	mv atmosphere-$(AMSVER).zip out/atmosphere-$(AMSVER).zip
-	mv atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip out/atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip
-	cp fusee/fusee-primary/fusee-primary.bin out/fusee-primary.bin
+	cp fusee/fusee.bin out/fusee.bin
 
 dist: dist-no-debug
 	$(eval MAJORVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MAJOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
@@ -117,8 +142,8 @@ dist: dist-no-debug
 	$(eval AMSVER = $(MAJORVER).$(MINORVER).$(MICROVER)-$(AMSREV))
 	rm -rf atmosphere-$(AMSVER)-debug
 	mkdir atmosphere-$(AMSVER)-debug
-	cp fusee/fusee-primary/fusee-primary.elf atmosphere-$(AMSVER)-debug/fusee-primary.elf
-	cp fusee/fusee-secondary/fusee-secondary-experimental.elf atmosphere-$(AMSVER)-debug/fusee-secondary.elf
+	cp fusee/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/fusee-loader-stub.elf
+	cp fusee/program/program.elf atmosphere-$(AMSVER)-debug/fusee-program.elf
 	cp exosphere/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/exosphere-loader-stub.elf
 	cp exosphere/program/program.elf atmosphere-$(AMSVER)-debug/exosphere-program.elf
 	cp exosphere/warmboot/warmboot.elf atmosphere-$(AMSVER)-debug/exosphere-warmboot.elf

config_templates/BCT.ini

@@ -1,12 +0,0 @@
-BCT0
-[stage1]
-stage2_path = atmosphere/fusee-secondary.bin
-stage2_mtc_path = atmosphere/fusee-mtc.bin
-stage2_addr = 0xF0000000
-stage2_entrypoint = 0xF0000000
-
-[stratosphere]
-; To force-enable nogc, add nogc = 1
-; To force-disable nogc, add nogc = 0
-
-; To opt out of using Atmosphere's NCM reimplementation, add disable_ncm = 1

config_templates/stratosphere.ini

@@ -0,0 +1,4 @@
+[stratosphere]
+; To force-enable nogc, add nogc = 1
+; To force-disable nogc, add nogc = 0
+

docs/changelog.md

@@ -1,4 +1,22 @@
 # Changelog
+## 1.0.0
++ `fusee` was completely re-written in C++ to use the same atmosphere-libs APIs as the rest of atmosphere's code.
+  + The rewrite was performed with a big emphasis on ensuring a good boot speed, and generally boot should be much faster than it was previously.
+    + Depending on SD card/environment, boot speed may now be slightly faster than, roughly the same as, or slightly slower than when booting with hekate.
+    + The obvious low-hanging fruit for performance improvements has been picked, so hopefully the improved performance is to everybody's liking.
+  + SD card compatibility was improved: fusee should now have SD card compatibility identical to the official OS driver.
+  + **Please Note**: various components were renamed (fusee-primary.bin -> fusee.bin, fusee-secondary.bin -> package3).
+    + If you use another bootloader (like hekate), you may need to update your configuration to use the new layout.
+  + **Please Note**: BCT.ini no longer exists, nogc configuration has been moved to `/atmosphere/stratosphere.ini`.
+    + If you rely on custom nogc configuration, please be sure to update accordingly.
+  + Custom splash screen BMP parsing is no longer supported (as it slows down boot for 99% of users).
+    + To compensate for this, a script to insert a custom splash screen into a `package3` binary has been added to the `utilities` folder of the atmosphere repository.
+    + The release build should be equivalent to running the following command from the root of the atmosphere repository: `python utilities/insert_splash_screen.py img/splash.png fusee/package3`
++ A number of pending changes were made, following the end of the relevant testing periods:
+  + `mesosphere` is no longer opt-out, and stratosphere code will begin depending on its being present/in use.
+  + `NCM` is no longer opt-out.
+  + The cleanup to ease the transition from < 0.19.0 to 0.19.0 has been removed.
++ General system stability improvements to enhance the user's experience.
 ## 0.20.1
 + An issue was fixed that caused severely degraded performance after wake-from-sleep on Mariko hardware.
   + This was due to Mariko MTC resulting in a frequency of 1599.999MHz instead of 1600MHz.

docs/components/fusee.md

@@ -1,22 +1,8 @@
 # fusée
 fusée is a custom bootloader used to start the Atmosphère environment.
-It is divided into three sub-components: fusée-primary, fusée-mtc and fusée-secondary.
 
-fusée is also capable of chainloading other payloads (e.g.: Android).
-
-fusée's behavior can be configured via the [BCT.ini](../features/configurations.md) file located on the SD card.
-
-## fusée-primary
-fusée-primary is the first piece of Atmosphère's code that runs on the hardware.
+## fusée
+fusée is the first piece of Atmosphère's code that runs on the hardware.
 It is distributed as a standalone payload designed to be launched via RCM by abusing the CVE-2018-6242 vulnerability.
 
-This payload is responsible for all the low-level hardware initialization required by the Nintendo Switch, plus the extra task of initializing the SD card and reading the next fusée sub-components from it.
-
-## fusée-mtc
-fusée-mtc is an optional, but heavily recommended sub-component that performs DRAM memory training.
-This ensures a proper environment for running the final fusée sub-component.
-
-## fusée-secondary
-fusée-secondary is the last fusée sub-component that runs on the system.
-It is responsible for configuring and bootstrapping the Atmosphère environment by mimicking the Horizon OS's design.
-This includes setting up the cryptosystem, mounting or emulating the eMMC, injecting or patching system modules and launching the exosphère component.
+This payload is responsible for all the low-level hardware initialization required by the Nintendo Switch, setting up the cryptosystem, mounting/emulating the eMMC, injecting/patching system modules, and launching the exosphère component.

docs/features/configurations.md

@@ -1,21 +1,10 @@
 # Configurations
 Atmosphère provides a variety of customizable configurations to better adjust to users' needs.
 
-## BCT.ini
-This is the configuration file used by fusée.
+## stratosphere.ini
+This is the configuration file used by fusée for configuring user-space system modules.
 This file is located under the `/atmosphere/config/` folder on your SD card and a default template can be found inside the `/atmosphere/config_templates/` folder.
 
-### Adding a Custom Boot Splashscreen
-Atmosphère provides its own default splashscreen which is displayed at boot time. However, this can be replaced at will.
-
-The boot splashscreen must be a BMP file, it must be 720x1280 (1280x720 rotated 90 degrees left/counterclockwise/anti-clockwise) resolution, and be in 32-bit ARGB format. You can use image editing software such as GIMP or Photoshop to export the image in this format.
-
-Add the following lines to BCT.ini and change the value of `custom_splash` to the actual path and filename of your boot splashscreen:
-```
-[stage2]
-custom_splash = /path/to/your/bootlogo.bmp
-```
-
 ### Configuring "nogc" Protection
 "nogc" is a feature provided by fusée-secondary which disables the Nintendo Switch's Game Card reader. Its purpose is to prevent the reader from being updated when the console has been updated, without burning fuses, from a lower firmware version. More specifically, from firmware versions 4.0.0 or 9.0.0 which introduced updates to the Game Card reader's firmware. By default, Atmosphère will protect the Game Card reader automatically, but you are free to change it.
 
@@ -29,32 +18,15 @@ nogc = X
 0 = force-disable nogc, so Atmosphère will always enable the Game Card reader.
 ```
 
-### NCM opt-out
-Atmosphère provides a reimplementation of the [ncm](../components/modules/ncm.md) system module. If you wish to disable this reimplementation add the following line to the `stratosphere` section:
-```
-[stratosphere]
-disable_ncm = 1
-```
+## Adding a Custom Boot Splashscreen
+Atmosphère provides its own default splashscreen which is displayed at boot time. However, this can be replaced at will.
 
-### Logging
-This is an advanced feature aimed at developers trying to debug boot time issues. It enables logging of the fusée stages to be displayed on screen.
+Boot splash screens must be 1280x720 resolution.
 
-Add the following lines to BCT.ini and change the value of `X` according to the following list:
-```
-[config]
-log_level = X
-```
-```
-0 = NONE
-1 = ERROR
-2 = WARNING
-3 = MANDATORY
-4 = INFO
-5 = DEBUG
-```
+A script can be found inside the source tree (`/utilities/insert_splash_screen.py`) for inserting a custom splash screen into a release binary.
 
-A special level is also provided to prevent prefix creation. To use it, do a bitwise OR with this mask:
-`0x100 = NO_PREFIX`
+To do so, execute the following command on the script:
+`python insert_splash_screen.py <path to your splash screen image> <path to /atmosphere/package3 on your SD card>`
 
 ## emummc.ini
 This is the configuration file used for the [emummc](../components/emummc.md) component.

emummc/Makefile

@@ -98,7 +98,10 @@ else
 
 DEPENDS	:=	$(OFILES:.o=.d)
 
-all	:	$(OUTPUT).kip
+all	:	$(OUTPUT)_unpacked.kip
+
+$(OUTPUT)_unpacked.kip	:	$(OUTPUT).kip
+	@hactool -t kip --uncompressed=$(OUTPUT)_unpacked.kip $(OUTPUT).kip
 
 $(OUTPUT).kip	:	$(OUTPUT).elf
 

exosphere/mariko_fatal/source/fatal_display.hpp

@@ -23,6 +23,7 @@ namespace ams::secmon::fatal {
     constexpr inline size_t FrameBufferSize   = FrameBufferHeight * FrameBufferWidth * sizeof(u32);
 
     void InitializeDisplay();
+    void ShowDisplay();
     void ShowDisplay(const ams::impl::FatalErrorContext *f_ctx, const Result save_result);
 
 }

exosphere/mariko_fatal/source/fs/fatal_fs_api.cpp

@@ -104,13 +104,13 @@ namespace ams::fs {
 
     bool MountSdCard() {
         AMS_ASSERT(!g_is_sd_mounted);
-        g_is_sd_mounted = f_mount(std::addressof(g_sd_fs), "", 1) == FR_OK;
+        g_is_sd_mounted = f_mount(std::addressof(g_sd_fs), "sdmc", 1) == FR_OK;
         return g_is_sd_mounted;
     }
 
     void UnmountSdCard() {
         AMS_ASSERT(g_is_sd_mounted);
-        f_unmount("");
+        f_unmount("sdmc");
         g_is_sd_mounted = false;
     }
 

exosphere/program/program.ld

@@ -176,13 +176,11 @@ SECTIONS
         KEEP (*(.warmboot.text.start)) /* Should be first */
         KEEP (*(.warmboot.text*))
         KEEP(secmon_setup_warm.o(.text*))
-        KEEP(tsec_*.o(.text*))
+        KEEP(*(.text._ZN3ams4tsec4LockEv))
         KEEP (*(.warmboot.rodata*))
         KEEP(secmon_setup_warm.o(.rodata*))
-        KEEP(tsec_*.o(.rodata*))
         KEEP (*(.warmboot.data*))
         KEEP(secmon_setup_warm.o(.data*))
-        KEEP(tsec_*.o(.data*))
     } >warmboot_text AT>glob
 
 	.text ORIGIN(main) + SIZEOF(.vectors) + SIZEOF(.warmboot) :

exosphere/program/sc7fw/source/sc7fw_main.cpp

@@ -58,8 +58,8 @@ namespace ams::sc7fw {
 
         void EnterSc7() {
             /* Disable read buffering and write buffering in the BPMP cache. */
-            reg::ReadWrite(AVP_CACHE_ADDRESS(AVP_CACHE_CONFIG), AVP_CACHE_REG_BITS_ENUM(DISABLE_WB, TRUE),
-                                                                AVP_CACHE_REG_BITS_ENUM(DISABLE_RB, TRUE));
+            reg::ReadWrite(AVP_CACHE_ADDR(AVP_CACHE_CONFIG), AVP_CACHE_REG_BITS_ENUM(CONFIG_DISABLE_WB, TRUE),
+                                                             AVP_CACHE_REG_BITS_ENUM(CONFIG_DISABLE_RB, TRUE));
 
             /* Ensure the CPU Rail is turned off. */
             DisableCrail();

exosphere/program/source/boot/secmon_main.cpp

@@ -80,6 +80,8 @@ namespace ams::secmon {
 
             /* Alert the bootloader that we're initialized. */
             secmon_params.secmon_state = pkg1::SecureMonitorState_Initialized;
+            hw::FlushDataCache(std::addressof(secmon_params.secmon_state), sizeof(secmon_params.secmon_state));
+            hw::DataSynchronizationBarrierInnerShareable();
         }
 
         /* Wait for NX Bootloader to finish loading the BootConfig. */

exosphere/program/source/boot/secmon_package2.cpp

@@ -154,8 +154,11 @@ namespace ams::secmon::boot {
     bool VerifyPackage2Payloads(const pkg2::Package2Meta &meta, uintptr_t payload_address) {
         /* Verify hashes match for all payloads. */
         for (int i = 0; i < pkg2::PayloadCount; ++i) {
-            if (!VerifyHash(meta.payload_hashes[i], payload_address, meta.payload_sizes[i])) {
-                return false;
+            /* Allow all-zero bytes to match any payload. */
+            if (!(meta.payload_hashes[i][0] == 0 && std::memcmp(meta.payload_hashes[i] + 0, meta.payload_hashes[i] + 1, sizeof(meta.payload_hashes[i]) - 1) == 0)) {
+                if (!VerifyHash(meta.payload_hashes[i], payload_address, meta.payload_sizes[i])) {
+                    return false;
+                }
             }
 
             payload_address += meta.payload_sizes[i];

exosphere/program/source/secmon_setup.cpp

@@ -475,8 +475,8 @@ namespace ams::secmon {
 
             /* Lock cluster switching, to prevent usage of the A53 cores. */
             reg::Write(FLOW_CTLR + FLOW_CTLR_BPMP_CLUSTER_CONTROL, FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER_LOCK,    ENABLE),
-                                                                FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, DISABLE),
-                                                                FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER,           FAST));
+                                                                   FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, DISABLE),
+                                                                   FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER,           FAST));
 
             /* Enable flow controller debug qualifier for legacy FIQs. */
             reg::Write(FLOW_CTLR + FLOW_CTLR_FLOW_DBG_QUAL, FLOW_REG_BITS_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, ENABLE));
@@ -600,8 +600,8 @@ namespace ams::secmon {
                 g_kernel_carveouts[0].size = 200 * 128_KB;
             }
 
-            /* Configure the two kernel carveouts. */
-            SetupKernelCarveouts();
+            /* NOTE: Here Nintendo configures the two kernel carveouts; we will do this later, to allow fusee to continue using AVP_CACHE. */
+            /* SetupKernelCarveouts(); */
 
             /* Configure slave register security. */
             ConfigureSlaveSecurity();
@@ -833,7 +833,7 @@ namespace ams::secmon {
             #define MC_ENABLE_CLIENT_ACCESS(INDEX, WHICH) MC_REG_BITS_ENUM(CLIENT_ACCESS##INDEX##_##WHICH, ENABLE)
 
             constexpr u32 WarmbootCarveoutClientAccess0     = reg::Encode(MC_ENABLE_CLIENT_ACCESS(0, AVPCARM7R),
-                                                          MC_ENABLE_CLIENT_ACCESS(0, PPCSAHBSLVR));
+                                                                          MC_ENABLE_CLIENT_ACCESS(0, PPCSAHBSLVR));
 
             constexpr u32 WarmbootCarveoutClientAccess1     = reg::Encode(MC_ENABLE_CLIENT_ACCESS(1, AVPCARM7W));
 
@@ -1164,6 +1164,9 @@ namespace ams::secmon {
         /* Setup the GPU carveout. */
         SetupGpuCarveout();
 
+        /* Configure the two kernel carveouts. */
+        SetupKernelCarveouts();
+
         /* Disable the ARC. */
         DisableArc();
 

fusee/Makefile

@@ -1,10 +1,44 @@
-SUBFOLDERS := fusee-primary fusee-secondary
+ATMOSPHERE_BUILD_CONFIGS :=
+all: release
 
-TOPTARGETS := all clean
+define ATMOSPHERE_ADD_TARGET
 
-$(TOPTARGETS): $(SUBFOLDERS)
+ATMOSPHERE_BUILD_CONFIGS += $(strip $1)
 
-$(SUBFOLDERS):
-	$(MAKE) -C $@ $(MAKECMDGOALS)
+$(strip $1): fusee$(strip $2).bin
 
-.PHONY: $(TOPTARGETS) $(SUBFOLDERS)
+fusee$(strip $2).bin: loader_stub/loader_stub$(strip $2).bin
+	@cp loader_stub/loader_stub$(strip $2).bin fusee$(strip $2).bin
+	@echo "Built fusee$(strip $2).bin..."
+
+check_program_$(strip $1):
+	@$$(MAKE) -C program $(strip $1)
+
+loader_stub/loader_stub$(strip $2).bin: check_program_$(strip $1)
+	@$$(MAKE) -C loader_stub $(strip $1)
+
+clean-$(strip $1): clean-program-$(strip $1) clean-loader_stub-$(strip $1)
+	@rm -rf fusee$(strip $2).bin
+
+clean-program-$(strip $1):
+	@$$(MAKE) -C program clean-$(strip $1)
+
+clean-loader_stub-$(strip $1):
+	@$$(MAKE) -C loader_stub clean-$(strip $1)
+
+endef
+
+$(eval $(call ATMOSPHERE_ADD_TARGET, release, ))
+$(eval $(call ATMOSPHERE_ADD_TARGET, debug, _debug))
+$(eval $(call ATMOSPHERE_ADD_TARGET, audit, _audit))
+
+clean: clean-program clean-loader_stub
+	@rm -rf fusee*.bin package3*
+
+clean-program:
+	@$(MAKE) -C program clean
+
+clean-loader_stub:
+	@$(MAKE) -C loader_stub clean
+
+.PHONY: all clean clean-program clean-loader_stub $(foreach config,$(ATMOSPHERE_BUILD_CONFIGS),check_program_$(config) check_warmboot_$(strip $1) clean-$(config) clean-program-$(config) clean-loader_stub-$(config) clean-warmboot-$(config))

fusee/build_package3.py

@@ -0,0 +1,201 @@
+#!/usr/bin/env python
+import sys, lz4, hashlib, os
+from struct import unpack as up, pack as pk
+
+def lz4_compress(data):
+    try:
+        import lz4.block as block
+    except ImportError:
+        block = lz4.LZ4_compress
+    return block.compress(data, 'high_compression', store_size=False)
+
+def read_file(fn):
+    with open(fn, 'rb') as f:
+        return f.read()
+
+def pad(data, size):
+    assert len(data) <= size
+    return (data + '\x00' * size)[:size]
+
+def get_overlay(program, i):
+    return program[0x2B000 + 0x14000 * i:0x2B000 + 0x14000 * (i+1)]
+
+KIP_NAMES = ['Loader', 'NCM', 'ProcessManager', 'sm', 'boot', 'spl', 'ams_mitm']
+
+def get_kips(ams_dir):
+    emummc   = read_file(os.path.join(ams_dir, 'emummc/emummc_unpacked.kip'))
+    loader   = read_file(os.path.join(ams_dir, 'stratosphere/loader/loader.kip'))
+    ncm      = read_file(os.path.join(ams_dir, 'stratosphere/ncm/ncm.kip'))
+    pm       = read_file(os.path.join(ams_dir, 'stratosphere/pm/pm.kip'))
+    sm       = read_file(os.path.join(ams_dir, 'stratosphere/sm/sm.kip'))
+    boot     = read_file(os.path.join(ams_dir, 'stratosphere/boot/boot.kip'))
+    spl      = read_file(os.path.join(ams_dir, 'stratosphere/spl/spl.kip'))
+    ams_mitm = read_file(os.path.join(ams_dir, 'stratosphere/ams_mitm/ams_mitm.kip'))
+    return (emummc, {
+        'Loader' : loader,
+        'NCM' : ncm,
+        'ProcessManager' : pm,
+        'sm' : sm,
+        'boot' : boot,
+        'spl' : spl,
+        'ams_mitm' : ams_mitm,
+    })
+
+def write_kip_meta(f, kip, ofs):
+    # Write program id
+    f.write(kip[0x10:0x18])
+    # Write offset, size
+    f.write(pk('<II', ofs - 0x100000, len(kip)))
+    # Write hash
+    f.write(hashlib.sha256(kip).digest())
+
+def write_header(f, all_kips, wb_size, tk_size, xf_size, ex_size, ms_size, fs_size, rb_size, git_revision, major, minor, micro, relstep, s_major, s_minor, s_micro, s_relstep):
+    # Unpack kips
+    emummc, kips = all_kips
+    # Write magic as PK31 magic.
+    f.write(b'PK31')
+    # Write metadata offset = 0x10
+    f.write(pk('<I', 0x20))
+    # Write flags
+    f.write(pk('<I', 0x00000000))
+    # Write meso_size
+    f.write(pk('<I', ms_size))
+    # Write num_kips
+    f.write(pk('<I', len(KIP_NAMES)))
+    # Write reserved1
+    f.write(b'\xCC' * 0xC)
+    # Write legacy magic
+    f.write(b'FSS0')
+    # Write total size
+    f.write(pk('<I', 0x800000))
+    # Write reserved2
+    f.write(pk('<I', 0xCCCCCCCC))
+    # Write content_header_offset
+    f.write(pk('<I', 0x40))
+    # Write num_content_headers;
+    f.write(pk('<I', 8 + len(KIP_NAMES)))
+    # Write supported_hos_version;
+    f.write(pk('<BBBB', s_relstep, s_micro, s_minor, s_major))
+    # Write release_version;
+    f.write(pk('<BBBB', relstep, micro, minor, major))
+    # Write git_revision;
+    f.write(pk('<I', git_revision))
+    # Write content metas
+    f.write(pk('<IIBBBBI16s', 0x000800, wb_size,  2, 0, 0, 0, 0xCCCCCCCC, 'warmboot'))
+    f.write(pk('<IIBBBBI16s', 0x002000, tk_size, 12, 0, 0, 0, 0xCCCCCCCC, 'tsec_keygen'))
+    f.write(pk('<IIBBBBI16s', 0x004000, xf_size, 11, 0, 0, 0, 0xCCCCCCCC, 'exosphere_fatal'))
+    f.write(pk('<IIBBBBI16s', 0x048000, ex_size,  1, 0, 0, 0, 0xCCCCCCCC, 'exosphere'))
+    f.write(pk('<IIBBBBI16s', 0x056000, ms_size, 10, 0, 0, 0, 0xCCCCCCCC, 'mesosphere'))
+    f.write(pk('<IIBBBBI16s', 0x7C0000, fs_size,  0, 0, 0, 0, 0xCCCCCCCC, 'fusee'))
+    f.write(pk('<IIBBBBI16s', 0x7E0000, rb_size,  3, 0, 0, 0, 0xCCCCCCCC, 'rebootstub'))
+    f.write(pk('<IIBBBBI16s', 0x100000, len(emummc),  8, 0, 0, 0, 0xCCCCCCCC, 'emummc'))
+    ofs = (0x100000 + len(emummc) + 0xF) & ~0xF
+    for kip_name in KIP_NAMES:
+        kip_data = kips[kip_name]
+        f.write(pk('<IIBBBBI16s', ofs, len(kip_data), 6, 0, 0, 0, 0xCCCCCCCC, kip_name))
+        ofs += len(kip_data)
+        ofs += 0xF
+        ofs &= ~0xF
+    # Pad to kip metas.
+    f.write(b'\xCC' * (0x400 - 0x40 - (0x20 * (8 + len(KIP_NAMES)))))
+    # Write emummc_meta. */
+    write_kip_meta(f, emummc, 0x100000)
+    # Write kip metas
+    ofs = (0x100000 + len(emummc) + 0xF) & ~0xF
+    for kip_name in KIP_NAMES:
+        kip_data = kips[kip_name]
+        write_kip_meta(f, kip_data, ofs)
+        ofs += len(kip_data)
+        ofs += 0xF
+        ofs &= ~0xF
+    # Pad to end of header
+    f.write(b'\xCC' * (0x800 - (0x400 + (1 + len(KIP_NAMES)) * 0x30)))
+
+def write_kips(f, all_kips):
+    # Unpack kips
+    emummc, kips = all_kips
+    # Write emummc
+    f.write(emummc)
+    # Write kips
+    tot = len(emummc)
+    if (tot & 0xF):
+        f.write('\xCC' * (0x10 - (tot & 0xF)))
+        tot += 0xF
+        tot &= ~0xF
+    for kip_name in KIP_NAMES:
+        kip_data = kips[kip_name]
+        f.write(kip_data)
+        tot += len(kip_data)
+        if (tot & 0xF):
+            f.write('\xCC' * (0x10 - (tot & 0xF)))
+            tot += 0xF
+            tot &= ~0xF
+    # Pad to 3 MB
+    f.write(b'\xCC' * (0x300000 - tot))
+
+def main(argc, argv):
+    if argc != 12:
+        print('Usage: %s ams_dir target revision major minor micro relstep s_major s_minor s_micro s_relstep' % argv[0])
+        return 1
+    # Parse arguments
+    ams_dir   = argv[1]
+    target    = '' if argv[2] == 'release' else ('_%s' % argv[2])
+    revision  = int(argv[3], 16)
+    major     = int(argv[4])
+    minor     = int(argv[5])
+    micro     = int(argv[6])
+    relstep   = int(argv[7])
+    s_major   = int(argv[8])
+    s_minor   = int(argv[9])
+    s_micro   = int(argv[10])
+    s_relstep = int(argv[11])
+    # Read/parse fusee
+    fusee_program = read_file(os.path.join(ams_dir, 'fusee/program/program%s.bin' % target))
+    fusee_bin     = read_file(os.path.join(ams_dir, 'fusee/fusee%s.bin' % target))
+    erista_mtc = get_overlay(fusee_program, 1)
+    mariko_mtc = get_overlay(fusee_program, 2)
+    erista_hsh = hashlib.sha256(erista_mtc[:-4]).digest()[:4]
+    mariko_hsh = hashlib.sha256(mariko_mtc[:-4]).digest()[:4]
+    # Read other files
+    exosphere    = read_file(os.path.join(ams_dir, 'exosphere/exosphere%s.bin' % target))
+    warmboot     = read_file(os.path.join(ams_dir, 'exosphere/warmboot%s.bin' % target))
+    mariko_fatal = read_file(os.path.join(ams_dir, 'exosphere/mariko_fatal%s.bin' % target))
+    rebootstub   = read_file(os.path.join(ams_dir, 'exosphere/program/rebootstub/rebootstub%s.bin' % target))
+    mesosphere   = read_file(os.path.join(ams_dir, 'mesosphere/mesosphere%s.bin' % target))
+    all_kips     = get_kips(ams_dir)
+    tsec_keygen  = read_file(os.path.join(ams_dir, 'fusee/program/tsec_keygen/tsec_keygen.bin'))
+    splash_bin   = read_file(os.path.join(ams_dir, 'img/splash.bin'))
+    assert len(splash_bin) == 0x3C0000
+    with open(os.path.join(ams_dir, 'fusee/package3%s' % target), 'wb') as f:
+        # Write header
+        write_header(f, all_kips, len(warmboot), len(tsec_keygen), len(mariko_fatal), len(exosphere), len(mesosphere), len(fusee_bin), len(rebootstub), revision, major, minor, micro, relstep, s_major, s_minor, s_micro, s_relstep)
+        # Write warmboot
+        f.write(pad(warmboot, 0x1800))
+        # Write TSEC Keygen
+        f.write(pad(tsec_keygen, 0x2000))
+        # Write Mariko Fatal
+        f.write(pad(mariko_fatal, 0x1C000))
+        # Write Erista MTC
+        f.write(erista_mtc[:-4] + erista_hsh)
+        # Write Mariko MTC
+        f.write(mariko_mtc[:-4] + mariko_hsh)
+        # Write exosphere
+        f.write(pad(exosphere, 0xE000))
+        # Write mesosphere
+        f.write(pad(mesosphere, 0xAA000))
+        # Write kips
+        write_kips(f, all_kips)
+        # Write Splash Screen
+        f.write(splash_bin)
+        # Write fusee
+        f.write(pad(fusee_bin, 0x20000))
+        # Write rebootstub
+        f.write(pad(rebootstub, 0x1000))
+        # Pad to 8 MB
+        f.write(b'\xCC' * (0x800000 - 0x7E1000))
+
+
+    return 0
+
+if __name__ == '__main__':
+    sys.exit(main(len(sys.argv), sys.argv))

fusee/common/display/video_fb.h

@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 1997-2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _VIDEO_FB_H_
-#define _VIDEO_FB_H_
-
-#define CONSOLE_BG_COL            0x00
-#define CONSOLE_FG_COL            0xa0
-
-/* Try using the small font */
-#define CONFIG_VIDEO_FONT_SMALL
-
-/*
- * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
- */
-#define GDF__8BIT_INDEX         0
-#define GDF_15BIT_555RGB        1
-#define GDF_16BIT_565RGB        2
-#define GDF_32BIT_X888RGB       3
-#define GDF_24BIT_888RGB        4
-#define GDF__8BIT_332RGB        5
-
-#define CONFIG_VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_VIDEO_VISIBLE_COLS 720
-#define CONFIG_VIDEO_VISIBLE_ROWS 1280
-#define CONFIG_VIDEO_COLS         768
-#define CONFIG_VIDEO_PIXEL_SIZE   4
-#define CONFIG_VIDEO_DATA_FORMAT  GDF_32BIT_X888RGB /* BGR actually, but w/e */
-
-int video_get_col(void);
-int video_get_row(void);
-
-int video_init(void *fb);
-int video_resume(void *fb, int row, int col);
-void video_putc(char c);
-void video_puts(const char *s);
-
-#endif /*_VIDEO_FB_H_ */

fusee/common/fatfs/00history.txt

@@ -1,340 +0,0 @@
-----------------------------------------------------------------------------
-  Revision history of FatFs module
-----------------------------------------------------------------------------
-
-R0.00 (February 26, 2006)
-
-  Prototype.
-
-
-
-R0.01 (April 29, 2006)
-
-  The first release.
-
-
-
-R0.02 (June 01, 2006)
-
-  Added FAT12 support.
-  Removed unbuffered mode.
-  Fixed a problem on small (<32M) partition.
-
-
-
-R0.02a (June 10, 2006)
-
-  Added a configuration option (_FS_MINIMUM).
-
-
-
-R0.03 (September 22, 2006)
-
-  Added f_rename().
-  Changed option _FS_MINIMUM to _FS_MINIMIZE.
-
-
-
-R0.03a (December 11, 2006)
-
-  Improved cluster scan algorithm to write files fast.
-  Fixed f_mkdir() creates incorrect directory on FAT32.
-
-
-
-R0.04 (February 04, 2007)
-
-  Added f_mkfs().
-  Supported multiple drive system.
-  Changed some interfaces for multiple drive system.
-  Changed f_mountdrv() to f_mount().
-
-
-
-R0.04a (April 01, 2007)
-
-  Supported multiple partitions on a physical drive.
-  Added a capability of extending file size to f_lseek().
-  Added minimization level 3.
-  Fixed an endian sensitive code in f_mkfs().
-
-
-
-R0.04b (May 05, 2007)
-
-  Added a configuration option _USE_NTFLAG.
-  Added FSINFO support.
-  Fixed DBCS name can result FR_INVALID_NAME.
-  Fixed short seek (<= csize) collapses the file object.
-
-
-
-R0.05 (August 25, 2007)
-
-  Changed arguments of f_read(), f_write() and f_mkfs().
-  Fixed f_mkfs() on FAT32 creates incorrect FSINFO.
-  Fixed f_mkdir() on FAT32 creates incorrect directory.
-
-
-
-R0.05a (February 03, 2008)
-
-  Added f_truncate() and f_utime().
-  Fixed off by one error at FAT sub-type determination.
-  Fixed btr in f_read() can be mistruncated.
-  Fixed cached sector is not flushed when create and close without write.
-
-
-
-R0.06 (April 01, 2008)
-
-  Added fputc(), fputs(), fprintf() and fgets().
-  Improved performance of f_lseek() on moving to the same or following cluster.
-
-
-
-R0.07 (April 01, 2009)
-
-  Merged Tiny-FatFs as a configuration option. (_FS_TINY)
-  Added long file name feature. (_USE_LFN)
-  Added multiple code page feature. (_CODE_PAGE)
-  Added re-entrancy for multitask operation. (_FS_REENTRANT)
-  Added auto cluster size selection to f_mkfs().
-  Added rewind option to f_readdir().
-  Changed result code of critical errors.
-  Renamed string functions to avoid name collision.
-
-
-
-R0.07a (April 14, 2009)
-
-  Septemberarated out OS dependent code on reentrant cfg.
-  Added multiple sector size feature.
-
-
-
-R0.07c (June 21, 2009)
-
-  Fixed f_unlink() can return FR_OK on error.
-  Fixed wrong cache control in f_lseek().
-  Added relative path feature.
-  Added f_chdir() and f_chdrive().
-  Added proper case conversion to extended character.
-
-
-
-R0.07e (November 03, 2009)
-
-  Septemberarated out configuration options from ff.h to ffconf.h.
-  Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH.
-  Fixed name matching error on the 13 character boundary.
-  Added a configuration option, _LFN_UNICODE.
-  Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
-
-
-
-R0.08 (May 15, 2010)
-
-  Added a memory configuration option. (_USE_LFN = 3)
-  Added file lock feature. (_FS_SHARE)
-  Added fast seek feature. (_USE_FASTSEEK)
-  Changed some types on the API, XCHAR->TCHAR.
-  Changed .fname in the FILINFO structure on Unicode cfg.
-  String functions support UTF-8 encoding files on Unicode cfg.
-
-
-
-R0.08a (August 16, 2010)
-
-  Added f_getcwd(). (_FS_RPATH = 2)
-  Added sector erase feature. (_USE_ERASE)
-  Moved file lock semaphore table from fs object to the bss.
-  Fixed f_mkfs() creates wrong FAT32 volume.
-
-
-
-R0.08b (January 15, 2011)
-
-  Fast seek feature is also applied to f_read() and f_write().
-  f_lseek() reports required table size on creating CLMP.
-  Extended format syntax of f_printf().
-  Ignores duplicated directory separators in given path name.
-
-
-
-R0.09 (September 06, 2011)
-
-  f_mkfs() supports multiple partition to complete the multiple partition feature.
-  Added f_fdisk().
-
-
-
-R0.09a (August 27, 2012)
-
-  Changed f_open() and f_opendir() reject null object pointer to avoid crash.
-  Changed option name _FS_SHARE to _FS_LOCK.
-  Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
-
-
-
-R0.09b (January 24, 2013)
-
-  Added f_setlabel() and f_getlabel().
-
-
-
-R0.10 (October 02, 2013)
-
-  Added selection of character encoding on the file. (_STRF_ENCODE)
-  Added f_closedir().
-  Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO)
-  Added forced mount feature with changes of f_mount().
-  Improved behavior of volume auto detection.
-  Improved write throughput of f_puts() and f_printf().
-  Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write().
-  Fixed f_write() can be truncated when the file size is close to 4GB.
-  Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error.
-
-
-
-R0.10a (January 15, 2014)
-
-  Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
-  Added a configuration option of minimum sector size. (_MIN_SS)
-  2nd argument of f_rename() can have a drive number and it will be ignored.
-  Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10)
-  Fixed f_close() invalidates the file object without volume lock.
-  Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10)
-  Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07)
-
-
-
-R0.10b (May 19, 2014)
-
-  Fixed a hard error in the disk I/O layer can collapse the directory entry.
-  Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07)
-
-
-
-R0.10c (November 09, 2014)
-
-  Added a configuration option for the platforms without RTC. (_FS_NORTC)
-  Changed option name _USE_ERASE to _USE_TRIM.
-  Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b)
-  Fixed a potential problem of FAT access that can appear on disk error.
-  Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
-
-
-
-R0.11 (February 09, 2015)
-
-  Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND)
-  Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c)
-  Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
-
-
-
-R0.11a (September 05, 2015)
-
-  Fixed wrong media change can lead a deadlock at thread-safe configuration.
-  Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE)
-  Removed some code pages actually not exist on the standard systems. (_CODE_PAGE)
-  Fixed errors in the case conversion teble of code page 437 and 850 (ff.c).
-  Fixed errors in the case conversion teble of Unicode (cc*.c).
-
-
-
-R0.12 (April 12, 2016)
-
-  Added support for exFAT file system. (_FS_EXFAT)
-  Added f_expand(). (_USE_EXPAND)
-  Changed some members in FINFO structure and behavior of f_readdir().
-  Added an option _USE_CHMOD.
-  Removed an option _WORD_ACCESS.
-  Fixed errors in the case conversion table of Unicode (cc*.c).
-
-
-
-R0.12a (July 10, 2016)
-
-  Added support for creating exFAT volume with some changes of f_mkfs().
-  Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed.
-  f_forward() is available regardless of _FS_TINY.
-  Fixed f_mkfs() creates wrong volume. (appeared at R0.12)
-  Fixed wrong memory read in create_name(). (appeared at R0.12)
-  Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD.
-
-
-
-R0.12b (September 04, 2016)
-
-  Made f_rename() be able to rename objects with the same name but case.
-  Fixed an error in the case conversion teble of code page 866. (ff.c)
-  Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)
-  Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)
-  Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12)
-  Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)
-  Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)
-  Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12)
-
-
-
-R0.12c (March 04, 2017)
-
-  Improved write throughput at the fragmented file on the exFAT volume.
-  Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN.
-  Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12)
-  Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c)
-
-
-
-R0.13 (May 21, 2017)
-
-  Changed heading character of configuration keywords "_" to "FF_".
-  Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead.
-  Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0)
-  Improved cluster allocation time on stretch a deep buried cluster chain.
-  Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3.
-  Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous.
-  Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)
-  Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)
-  Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)
-
-
-
-R0.13a (October 14, 2017)
-
-  Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2)
-  Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF).
-  Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk().
-  Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09)
-  Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)
-  Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12)
-
-
-
-R0.13b (April 07, 2018)
-
-  Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3)
-  Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2)
-  Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)
-  Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b)
-
-
-
-R0.13c (October 14, 2018)
-  Supported stdint.h for C99 and later. (integer.h was included in ff.h)
-  Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12)
-  Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)
-  Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)
-
-
-
-R0.14 (October 14, 2019)
-  Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1)
-  Changed some API functions, f_mkfs() and f_fdisk().
-  Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters.
-  Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters.
-  Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12)
-  Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12)
-

fusee/common/fatfs/00readme.txt

@@ -1,21 +0,0 @@
-FatFs Module Source Files R0.14
-
-
-FILES
-
-  00readme.txt   This file.
-  00history.txt  Revision history.
-  ff.c           FatFs module.
-  ffconf.h       Configuration file of FatFs module.
-  ff.h           Common include file for FatFs and application module.
-  diskio.h       Common include file for FatFs and disk I/O module.
-  diskio.c       An example of glue function to attach existing disk I/O module to FatFs.
-  ffunicode.c    Optional Unicode utility functions.
-  ffsystem.c     An example of optional O/S related functions.
-
-
-  Low level disk I/O module is not included in this archive because the FatFs
-  module is only a generic file system layer and it does not depend on any specific
-  storage device. You need to provide a low level disk I/O module written to
-  control the storage device that attached to the target system.
-

fusee/common/ini.c

@@ -1,272 +0,0 @@
-/* inih -- simple .INI file parser
-
-inih is released under the New BSD license (see LICENSE.txt). Go to the project
-home page for more info:
-
-https://github.com/benhoyt/inih
-
-*/
-
-#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS)
-#define _CRT_SECURE_NO_WARNINGS
-#endif
-
-#include <stdio.h>
-#include <ctype.h>
-#include <string.h>
-
-#include "ini.h"
-
-#if !INI_USE_STACK
-#include <stdlib.h>
-#endif
-
-#define MAX_SECTION 50
-#define MAX_NAME 50
-
-/* Used by ini_parse_string() to keep track of string parsing state. */
-typedef struct {
-    const char* ptr;
-    size_t num_left;
-} ini_parse_string_ctx;
-
-/* Strip whitespace chars off end of given string, in place. Return s. */
-static char* rstrip(char* s)
-{
-    char* p = s + strlen(s);
-    while (p > s && isspace((unsigned char)(*--p)))
-        *p = '\0';
-    return s;
-}
-
-/* Return pointer to first non-whitespace char in given string. */
-static char* lskip(const char* s)
-{
-    while (*s && isspace((unsigned char)(*s)))
-        s++;
-    return (char*)s;
-}
-
-/* Return pointer to first char (of chars) or inline comment in given string,
-   or pointer to null at end of string if neither found. Inline comment must
-   be prefixed by a whitespace character to register as a comment. */
-static char* find_chars_or_comment(const char* s, const char* chars)
-{
-#if INI_ALLOW_INLINE_COMMENTS
-    int was_space = 0;
-    while (*s && (!chars || !strchr(chars, *s)) &&
-           !(was_space && strchr(INI_INLINE_COMMENT_PREFIXES, *s))) {
-        was_space = isspace((unsigned char)(*s));
-        s++;
-    }
-#else
-    while (*s && (!chars || !strchr(chars, *s))) {
-        s++;
-    }
-#endif
-    return (char*)s;
-}
-
-/* Version of strncpy that ensures dest (size bytes) is null-terminated. */
-static char* strncpy0(char* dest, const char* src, size_t size)
-{
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstringop-truncation"
-    strncpy(dest, src, size - 1);
-#pragma GCC diagnostic pop
-    dest[size - 1] = '\0';
-    return dest;
-}
-
-/* See documentation in header file. */
-int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler,
-                     void* user)
-{
-    /* Uses a fair bit of stack (use heap instead if you need to) */
-#if INI_USE_STACK
-    char line[INI_MAX_LINE];
-    int max_line = INI_MAX_LINE;
-#else
-    char* line;
-    int max_line = INI_INITIAL_ALLOC;
-#endif
-#if INI_ALLOW_REALLOC
-    char* new_line;
-    int offset;
-#endif
-    char section[MAX_SECTION] = "";
-    char prev_name[MAX_NAME] = "";
-
-    char* start;
-    char* end;
-    char* name;
-    char* value;
-    int lineno = 0;
-    int error = 0;
-
-#if !INI_USE_STACK
-    line = (char*)malloc(INI_INITIAL_ALLOC);
-    if (!line) {
-        return -2;
-    }
-#endif
-
-#if INI_HANDLER_LINENO
-#define HANDLER(u, s, n, v) handler(u, s, n, v, lineno)
-#else
-#define HANDLER(u, s, n, v) handler(u, s, n, v)
-#endif
-
-    /* Scan through stream line by line */
-    while (reader(line, max_line, stream) != NULL) {
-#if INI_ALLOW_REALLOC
-        offset = strlen(line);
-        while (offset == max_line - 1 && line[offset - 1] != '\n') {
-            max_line *= 2;
-            if (max_line > INI_MAX_LINE)
-                max_line = INI_MAX_LINE;
-            new_line = realloc(line, max_line);
-            if (!new_line) {
-                free(line);
-                return -2;
-            }
-            line = new_line;
-            if (reader(line + offset, max_line - offset, stream) == NULL)
-                break;
-            if (max_line >= INI_MAX_LINE)
-                break;
-            offset += strlen(line + offset);
-        }
-#endif
-
-        lineno++;
-
-        start = line;
-#if INI_ALLOW_BOM
-        if (lineno == 1 && (unsigned char)start[0] == 0xEF &&
-                           (unsigned char)start[1] == 0xBB &&
-                           (unsigned char)start[2] == 0xBF) {
-            start += 3;
-        }
-#endif
-        start = lskip(rstrip(start));
-
-        if (strchr(INI_START_COMMENT_PREFIXES, *start)) {
-            /* Start-of-line comment */
-        }
-#if INI_ALLOW_MULTILINE
-        else if (*prev_name && *start && start > line) {
-            /* Non-blank line with leading whitespace, treat as continuation
-               of previous name's value (as per Python configparser). */
-            if (!HANDLER(user, section, prev_name, start) && !error)
-                error = lineno;
-        }
-#endif
-        else if (*start == '[') {
-            /* A "[section]" line */
-            end = find_chars_or_comment(start + 1, "]");
-            if (*end == ']') {
-                *end = '\0';
-                strncpy0(section, start + 1, sizeof(section));
-                *prev_name = '\0';
-            }
-            else if (!error) {
-                /* No ']' found on section line */
-                error = lineno;
-            }
-        }
-        else if (*start) {
-            /* Not a comment, must be a name[=:]value pair */
-            end = find_chars_or_comment(start, "=:");
-            if (*end == '=' || *end == ':') {
-                *end = '\0';
-                name = rstrip(start);
-                value = end + 1;
-#if INI_ALLOW_INLINE_COMMENTS
-                end = find_chars_or_comment(value, NULL);
-                if (*end)
-                    *end = '\0';
-#endif
-                value = lskip(value);
-                rstrip(value);
-
-                /* Valid name[=:]value pair found, call handler */
-                strncpy0(prev_name, name, sizeof(prev_name));
-                if (!HANDLER(user, section, name, value) && !error)
-                    error = lineno;
-            }
-            else if (!error) {
-                /* No '=' or ':' found on name[=:]value line */
-                error = lineno;
-            }
-        }
-
-#if INI_STOP_ON_FIRST_ERROR
-        if (error)
-            break;
-#endif
-    }
-
-#if !INI_USE_STACK
-    free(line);
-#endif
-
-    return error;
-}
-
-/* See documentation in header file. */
-int ini_parse_file(FILE* file, ini_handler handler, void* user)
-{
-    return ini_parse_stream((ini_reader)fgets, file, handler, user);
-}
-
-/* See documentation in header file. */
-int ini_parse(const char* filename, ini_handler handler, void* user)
-{
-    FILE* file;
-    int error;
-
-    file = fopen(filename, "r");
-    if (!file)
-        return -1;
-    error = ini_parse_file(file, handler, user);
-    fclose(file);
-    return error;
-}
-
-/* An ini_reader function to read the next line from a string buffer. This
-   is the fgets() equivalent used by ini_parse_string(). */
-static char* ini_reader_string(char* str, int num, void* stream) {
-    ini_parse_string_ctx* ctx = (ini_parse_string_ctx*)stream;
-    const char* ctx_ptr = ctx->ptr;
-    size_t ctx_num_left = ctx->num_left;
-    char* strp = str;
-    char c;
-
-    if (ctx_num_left == 0 || num < 2)
-        return NULL;
-
-    while (num > 1 && ctx_num_left != 0) {
-        c = *ctx_ptr++;
-        ctx_num_left--;
-        *strp++ = c;
-        if (c == '\n')
-            break;
-        num--;
-    }
-
-    *strp = '\0';
-    ctx->ptr = ctx_ptr;
-    ctx->num_left = ctx_num_left;
-    return str;
-}
-
-/* See documentation in header file. */
-int ini_parse_string(const char* string, ini_handler handler, void* user) {
-    ini_parse_string_ctx ctx;
-
-    ctx.ptr = string;
-    ctx.num_left = strlen(string);
-    return ini_parse_stream((ini_reader)ini_reader_string, &ctx, handler,
-                            user);
-}

fusee/common/ini.h

@@ -1,130 +0,0 @@
-/* inih -- simple .INI file parser
-
-inih is released under the New BSD license (see LICENSE.txt). Go to the project
-home page for more info:
-
-https://github.com/benhoyt/inih
-
-*/
-
-#ifndef __INI_H__
-#define __INI_H__
-
-/* Make this header file easier to include in C++ code */
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdio.h>
-
-/* Nonzero if ini_handler callback should accept lineno parameter. */
-#ifndef INI_HANDLER_LINENO
-#define INI_HANDLER_LINENO 0
-#endif
-
-/* Typedef for prototype of handler function. */
-#if INI_HANDLER_LINENO
-typedef int (*ini_handler)(void* user, const char* section,
-                           const char* name, const char* value,
-                           int lineno);
-#else
-typedef int (*ini_handler)(void* user, const char* section,
-                           const char* name, const char* value);
-#endif
-
-/* Typedef for prototype of fgets-style reader function. */
-typedef char* (*ini_reader)(char* str, int num, void* stream);
-
-/* Parse given INI-style file. May have [section]s, name=value pairs
-   (whitespace stripped), and comments starting with ';' (semicolon). Section
-   is "" if name=value pair parsed before any section heading. name:value
-   pairs are also supported as a concession to Python's configparser.
-
-   For each name=value pair parsed, call handler function with given user
-   pointer as well as section, name, and value (data only valid for duration
-   of handler call). Handler should return nonzero on success, zero on error.
-
-   Returns 0 on success, line number of first error on parse error (doesn't
-   stop on first error), -1 on file open error, or -2 on memory allocation
-   error (only when INI_USE_STACK is zero).
-*/
-int ini_parse(const char* filename, ini_handler handler, void* user);
-
-/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't
-   close the file when it's finished -- the caller must do that. */
-int ini_parse_file(FILE* file, ini_handler handler, void* user);
-
-/* Same as ini_parse(), but takes an ini_reader function pointer instead of
-   filename. Used for implementing custom or string-based I/O (see also
-   ini_parse_string). */
-int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler,
-                     void* user);
-
-/* Same as ini_parse(), but takes a zero-terminated string with the INI data
-instead of a file. Useful for parsing INI data from a network socket or
-already in memory. */
-int ini_parse_string(const char* string, ini_handler handler, void* user);
-
-/* Nonzero to allow multi-line value parsing, in the style of Python's
-   configparser. If allowed, ini_parse() will call the handler with the same
-   name for each subsequent line parsed. */
-#ifndef INI_ALLOW_MULTILINE
-#define INI_ALLOW_MULTILINE 1
-#endif
-
-/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of
-   the file. See http://code.google.com/p/inih/issues/detail?id=21 */
-#ifndef INI_ALLOW_BOM
-#define INI_ALLOW_BOM 1
-#endif
-
-/* Chars that begin a start-of-line comment. Per Python configparser, allow
-   both ; and # comments at the start of a line by default. */
-#ifndef INI_START_COMMENT_PREFIXES
-#define INI_START_COMMENT_PREFIXES ";#"
-#endif
-
-/* Nonzero to allow inline comments (with valid inline comment characters
-   specified by INI_INLINE_COMMENT_PREFIXES). Set to 0 to turn off and match
-   Python 3.2+ configparser behaviour. */
-#ifndef INI_ALLOW_INLINE_COMMENTS
-#define INI_ALLOW_INLINE_COMMENTS 1
-#endif
-#ifndef INI_INLINE_COMMENT_PREFIXES
-#define INI_INLINE_COMMENT_PREFIXES ";"
-#endif
-
-/* Nonzero to use stack for line buffer, zero to use heap (malloc/free). */
-#ifndef INI_USE_STACK
-#define INI_USE_STACK 1
-#endif
-
-/* Maximum line length for any line in INI file (stack or heap). Note that
-   this must be 3 more than the longest line (due to '\r', '\n', and '\0'). */
-#ifndef INI_MAX_LINE
-#define INI_MAX_LINE 200
-#endif
-
-/* Nonzero to allow heap line buffer to grow via realloc(), zero for a
-   fixed-size buffer of INI_MAX_LINE bytes. Only applies if INI_USE_STACK is
-   zero. */
-#ifndef INI_ALLOW_REALLOC
-#define INI_ALLOW_REALLOC 0
-#endif
-
-/* Initial size in bytes for heap line buffer. Only applies if INI_USE_STACK
-   is zero. */
-#ifndef INI_INITIAL_ALLOC
-#define INI_INITIAL_ALLOC 200
-#endif
-
-/* Stop parsing on first error (default is to keep parsing). */
-#ifndef INI_STOP_ON_FIRST_ERROR
-#define INI_STOP_ON_FIRST_ERROR 0
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __INI_H__ */

fusee/common/log.c

@@ -1,141 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "log.h"
-
-#ifdef FUSEE_STAGE2_SRC
-#include "../../../fusee/fusee-secondary/src/console.h"
-#include <stdio.h>
-#else
-#include "display/video_fb.h"
-#include "vsprintf.h"
-#endif
-
-/* Default log level for screen output. */
-ScreenLogLevel g_screen_log_level = SCREEN_LOG_LEVEL_NONE;
-
-void log_set_log_level(ScreenLogLevel log_level) {
-    g_screen_log_level = log_level;
-}
-
-ScreenLogLevel log_get_log_level() {
-    return g_screen_log_level;
-}
-
-void log_to_uart(const char *message) {
-    /* TODO: Add UART logging. */
-}
-
-static void print_to_screen(ScreenLogLevel screen_log_level, char *message) {
-    /* Don't print to screen if below log level */
-    if(screen_log_level > g_screen_log_level) return;
-    
-    #ifdef FUSEE_STAGE2_SRC
-    printf(message);
-    #else
-    video_puts(message);
-    #endif
-}
-
-/**
- * vprintk - logs a message and prints it to screen based on its screen_log_level
- *
- * If the level is below g_screen_log_level it will not be shown but logged to UART
- * This text will not be colored or prefixed
- * UART is TODO
- */
-void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args)
-{
-    char buf[PRINT_MESSAGE_MAX_LENGTH];
-    vsnprintf(buf, PRINT_MESSAGE_MAX_LENGTH, fmt, args);
-
-    /* We don't need that flag here, but if it gets used, strip it so we print correctly. */
-    screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
-
-    /* Log to UART. */
-    log_to_uart(buf);
-
-    print_to_screen(screen_log_level, buf);
-}
-
-static void add_prefix(ScreenLogLevel screen_log_level, const char *fmt, char *buf) {
-    char typebuf[] = "[%s] %s";
-
-    /* Apply prefix and append message format. */
-    /* TODO: Add coloring to the output. */
-    switch(screen_log_level)
-    {
-        case SCREEN_LOG_LEVEL_ERROR:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "ERROR", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_WARNING:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "WARNING", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_MANDATORY:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_INFO:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "INFO", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_DEBUG:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "DEBUG", fmt);
-            break;
-        default:
-            break;
-    }
-}
-
-/**
- * print - logs a message and prints it to screen based on its screen_log_level
- * 
- * If the level is below g_screen_log_level it will not be shown but logged to UART
- * Use SCREEN_LOG_LEVEL_NO_PREFIX if you don't want a prefix to be added
- * UART is TODO
- */
-void print(ScreenLogLevel screen_log_level, const char * fmt, ...)
-{
-    char buf[PRINT_MESSAGE_MAX_LENGTH] = {};
-    char message[PRINT_MESSAGE_MAX_LENGTH] = {};
-
-    /* Make splash disappear if level is ERROR or WARNING. */
-    #ifdef FUSEE_STAGE2_SRC
-    if (screen_log_level < SCREEN_LOG_LEVEL_MANDATORY) {
-        console_resume();
-    }
-    #endif
-
-    /* Make prefix free messages with log_level possible. */
-    if(screen_log_level & SCREEN_LOG_LEVEL_NO_PREFIX) {
-        /* Remove the NO_PREFIX flag so the enum can be recognized later on. */
-        screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
-
-        snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
-    }
-    else {
-        add_prefix(screen_log_level, fmt, buf);
-    }
-
-    /* Input arguments. */
-    va_list args;
-    va_start(args, fmt);
-    vsnprintf(message, PRINT_MESSAGE_MAX_LENGTH, buf, args);
-    va_end(args);
-
-    /* Log to UART. */
-    log_to_uart(message);
-
-    print_to_screen(screen_log_level, message);
-}

fusee/common/log.h

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_LOG_H
-#define FUSEE_LOG_H
-
-#define PRINT_MESSAGE_MAX_LENGTH 1024
-
-#include <stdarg.h>
-
-typedef enum {
-    SCREEN_LOG_LEVEL_NONE       = 0,
-    SCREEN_LOG_LEVEL_ERROR      = 1,
-    SCREEN_LOG_LEVEL_WARNING    = 2,
-    SCREEN_LOG_LEVEL_MANDATORY  = 3,    /* No log prefix. */
-    SCREEN_LOG_LEVEL_INFO       = 4,
-    SCREEN_LOG_LEVEL_DEBUG      = 5,
-    SCREEN_LOG_LEVEL_SD_DEBUG   = 6,
-
-    SCREEN_LOG_LEVEL_NO_PREFIX  = 0x100 /* OR this to your LOG_LEVEL to prevent prefix creation. */
-} ScreenLogLevel;
-
-extern ScreenLogLevel g_screen_log_level;
-
-void log_set_log_level(ScreenLogLevel screen_log_level);
-ScreenLogLevel log_get_log_level();
-void log_to_uart(const char *message);
-void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args);
-void print(ScreenLogLevel screen_log_level, const char* fmt, ...);
-
-#endif

fusee/common/lz.c

@@ -1,377 +0,0 @@
-/*************************************************************************
-* Name:        lz.c
-* Author:      Marcus Geelnard
-* Description: LZ77 coder/decoder implementation.
-* Reentrant:   Yes
-*
-* The LZ77 compression scheme is a substitutional compression scheme
-* proposed by Abraham Lempel and Jakob Ziv in 1977. It is very simple in
-* its design, and uses no fancy bit level compression.
-*
-* This is my first attempt at an implementation of a LZ77 code/decoder.
-*
-* The principle of the LZ77 compression algorithm is to store repeated
-* occurrences of strings as references to previous occurrences of the same
-* string. The point is that the reference consumes less space than the
-* string itself, provided that the string is long enough (in this
-* implementation, the string has to be at least 4 bytes long, since the
-* minimum coded reference is 3 bytes long). Also note that the term
-* "string" refers to any kind of byte sequence (it does not have to be
-* an ASCII string, for instance).
-*
-* The coder uses a brute force approach to finding string matches in the
-* history buffer (or "sliding window", if you wish), which is very, very
-* slow. I recon the complexity is somewhere between O(n^2) and O(n^3),
-* depending on the input data.
-*
-* There is also a faster implementation that uses a large working buffer
-* in which a "jump table" is stored, which is used to quickly find
-* possible string matches (see the source code for LZ_CompressFast() for
-* more information). The faster method is an order of magnitude faster,
-* but still quite slow compared to other compression methods.
-*
-* The upside is that decompression is very fast, and the compression ratio
-* is often very good.
-*
-* The reference to a string is coded as a (length,offset) pair, where the
-* length indicates the length of the string, and the offset gives the
-* offset from the current data position. To distinguish between string
-* references and literal strings (uncompressed bytes), a string reference
-* is preceded by a marker byte, which is chosen as the least common byte
-* symbol in the input data stream (this marker byte is stored in the
-* output stream as the first byte).
-*
-* Occurrences of the marker byte in the stream are encoded as the marker
-* byte followed by a zero byte, which means that occurrences of the marker
-* byte have to be coded with two bytes.
-*
-* The lengths and offsets are coded in a variable length fashion, allowing
-* values of any magnitude (up to 4294967295 in this implementation).
-*
-* With this compression scheme, the worst case compression result is
-* (257/256)*insize + 1.
-*
-*-------------------------------------------------------------------------
-* Copyright (c) 2003-2006 Marcus Geelnard
-*
-* This software is provided 'as-is', without any express or implied
-* warranty. In no event will the authors be held liable for any damages
-* arising from the use of this software.
-*
-* Permission is granted to anyone to use this software for any purpose,
-* including commercial applications, and to alter it and redistribute it
-* freely, subject to the following restrictions:
-*
-* 1. The origin of this software must not be misrepresented; you must not
-*    claim that you wrote the original software. If you use this software
-*    in a product, an acknowledgment in the product documentation would
-*    be appreciated but is not required.
-*
-* 2. Altered source versions must be plainly marked as such, and must not
-*    be misrepresented as being the original software.
-*
-* 3. This notice may not be removed or altered from any source
-*    distribution.
-*
-* Marcus Geelnard
-* marcus.geelnard at home.se
-*************************************************************************/
-
-
-/*************************************************************************
-* Constants used for LZ77 coding
-*************************************************************************/
-
-/* Maximum offset (can be any size < 2^31). Lower values give faster
-   compression, while higher values gives better compression. The default
-   value of 100000 is quite high. Experiment to see what works best for
-   you. */
-#define LZ_MAX_OFFSET 100000
-
-
-
-/*************************************************************************
-*                           INTERNAL FUNCTIONS                           *
-*************************************************************************/
-
-
-/*************************************************************************
-* _LZ_StringCompare() - Return maximum length string match.
-*************************************************************************/
-
-static unsigned int _LZ_StringCompare( const unsigned char * str1,
-  const unsigned char * str2, unsigned int minlen, unsigned int maxlen )
-{
-    unsigned int len;
-
-    for( len = minlen; (len < maxlen) && (str1[len] == str2[len]); ++ len );
-
-    return len;
-}
-
-
-/*************************************************************************
-* _LZ_WriteVarSize() - Write unsigned integer with variable number of
-* bytes depending on value.
-*************************************************************************/
-
-static int _LZ_WriteVarSize( unsigned int x, unsigned char * buf )
-{
-    unsigned int y;
-    int num_bytes, i, b;
-
-    /* Determine number of bytes needed to store the number x */
-    y = x >> 3;
-    for( num_bytes = 5; num_bytes >= 2; -- num_bytes )
-    {
-        if( y & 0xfe000000 ) break;
-        y <<= 7;
-    }
-
-    /* Write all bytes, seven bits in each, with 8:th bit set for all */
-    /* but the last byte. */
-    for( i = num_bytes-1; i >= 0; -- i )
-    {
-        b = (x >> (i*7)) & 0x0000007f;
-        if( i > 0 )
-        {
-            b |= 0x00000080;
-        }
-        *buf ++ = (unsigned char) b;
-    }
-
-    /* Return number of bytes written */
-    return num_bytes;
-}
-
-
-/*************************************************************************
-* _LZ_ReadVarSize() - Read unsigned integer with variable number of
-* bytes depending on value.
-*************************************************************************/
-
-static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf )
-{
-    unsigned int y, b, num_bytes;
-
-    /* Read complete value (stop when byte contains zero in 8:th bit) */
-    y = 0;
-    num_bytes = 0;
-    do
-    {
-        b = (unsigned int) (*buf ++);
-        y = (y << 7) | (b & 0x0000007f);
-        ++ num_bytes;
-    }
-    while( b & 0x00000080 );
-
-    /* Store value in x */
-    *x = y;
-
-    /* Return number of bytes read */
-    return num_bytes;
-}
-
-
-
-/*************************************************************************
-*                            PUBLIC FUNCTIONS                            *
-*************************************************************************/
-
-
-/*************************************************************************
-* LZ_Compress() - Compress a block of data using an LZ77 coder.
-*  in     - Input (uncompressed) buffer.
-*  out    - Output (compressed) buffer. This buffer must be 0.4% larger
-*           than the input buffer, plus one byte.
-*  insize - Number of input bytes.
-* The function returns the size of the compressed data.
-*************************************************************************/
-
-int LZ_Compress( const unsigned char *in, unsigned char *out, unsigned int insize )
-{
-    unsigned char marker, symbol;
-    unsigned int  inpos, outpos, bytesleft, i;
-    unsigned int  maxoffset, offset, bestoffset;
-    unsigned int  maxlength, length, bestlength;
-    unsigned int  histogram[ 256 ];
-    const unsigned char *ptr1, *ptr2;
-
-    /* Do we have anything to compress? */
-    if( insize < 1 )
-    {
-        return 0;
-    }
-
-    /* Create histogram */
-    for( i = 0; i < 256; ++ i )
-    {
-        histogram[ i ] = 0;
-    }
-    for( i = 0; i < insize; ++ i )
-    {
-        ++ histogram[ in[ i ] ];
-    }
-
-    /* Find the least common byte, and use it as the marker symbol */
-    marker = 0;
-    for( i = 1; i < 256; ++ i )
-    {
-        if( histogram[ i ] < histogram[ marker ] )
-        {
-            marker = (unsigned char) i;
-        }
-    }
-
-    /* Remember the marker symbol for the decoder */
-    out[ 0 ] = marker;
-
-    /* Start of compression */
-    inpos = 0;
-    outpos = 1;
-
-    /* Main compression loop */
-    bytesleft = insize;
-    do
-    {
-        /* Determine most distant position */
-        if( inpos > LZ_MAX_OFFSET ) maxoffset = LZ_MAX_OFFSET;
-        else                        maxoffset = inpos;
-
-        /* Get pointer to current position */
-        ptr1 = &in[ inpos ];
-
-        /* Search history window for maximum length string match */
-        bestlength = 3;
-        bestoffset = 0;
-        for( offset = 3; offset <= maxoffset; ++ offset )
-        {
-            /* Get pointer to candidate string */
-            ptr2 = &ptr1[ -(int)offset ];
-
-            /* Quickly determine if this is a candidate (for speed) */
-            if( (ptr1[ 0 ] == ptr2[ 0 ]) &&
-                (ptr1[ bestlength ] == ptr2[ bestlength ]) )
-            {
-                /* Determine maximum length for this offset */
-                maxlength = (bytesleft < offset ? bytesleft : offset);
-
-                /* Count maximum length match at this offset */
-                length = _LZ_StringCompare( ptr1, ptr2, 0, maxlength );
-
-                /* Better match than any previous match? */
-                if( length > bestlength )
-                {
-                    bestlength = length;
-                    bestoffset = offset;
-                }
-            }
-        }
-
-        /* Was there a good enough match? */
-        if( (bestlength >= 8) ||
-            ((bestlength == 4) && (bestoffset <= 0x0000007f)) ||
-            ((bestlength == 5) && (bestoffset <= 0x00003fff)) ||
-            ((bestlength == 6) && (bestoffset <= 0x001fffff)) ||
-            ((bestlength == 7) && (bestoffset <= 0x0fffffff)) )
-        {
-            out[ outpos ++ ] = (unsigned char) marker;
-            outpos += _LZ_WriteVarSize( bestlength, &out[ outpos ] );
-            outpos += _LZ_WriteVarSize( bestoffset, &out[ outpos ] );
-            inpos += bestlength;
-            bytesleft -= bestlength;
-        }
-        else
-        {
-            /* Output single byte (or two bytes if marker byte) */
-            symbol = in[ inpos ++ ];
-            out[ outpos ++ ] = symbol;
-            if( symbol == marker )
-            {
-                out[ outpos ++ ] = 0;
-            }
-            -- bytesleft;
-        }
-    }
-    while( bytesleft > 3 );
-
-    /* Dump remaining bytes, if any */
-    while( inpos < insize )
-    {
-        if( in[ inpos ] == marker )
-        {
-            out[ outpos ++ ] = marker;
-            out[ outpos ++ ] = 0;
-        }
-        else
-        {
-            out[ outpos ++ ] = in[ inpos ];
-        }
-        ++ inpos;
-    }
-
-    return outpos;
-}
-
-
-/*************************************************************************
-* LZ_Uncompress() - Uncompress a block of data using an LZ77 decoder.
-*  in      - Input (compressed) buffer.
-*  out     - Output (uncompressed) buffer. This buffer must be large
-*            enough to hold the uncompressed data.
-*  insize  - Number of input bytes.
-*************************************************************************/
-
-int LZ_Uncompress( const unsigned char *in, unsigned char *out, unsigned int insize )
-{
-    unsigned char marker, symbol;
-    unsigned int  i, inpos, outpos, length, offset;
-
-    /* Do we have anything to uncompress? */
-    if( insize < 1 )
-    {
-        return 0;
-    }
-
-    /* Get marker symbol from input stream */
-    marker = in[ 0 ];
-    inpos = 1;
-
-    /* Main decompression loop */
-    outpos = 0;
-    do
-    {
-        symbol = in[ inpos ++ ];
-        if( symbol == marker )
-        {
-            /* We had a marker byte */
-            if( in[ inpos ] == 0 )
-            {
-                /* It was a single occurrence of the marker byte */
-                out[ outpos ++ ] = marker;
-                ++ inpos;
-            }
-            else
-            {
-                /* Extract true length and offset */
-                inpos += _LZ_ReadVarSize( &length, &in[ inpos ] );
-                inpos += _LZ_ReadVarSize( &offset, &in[ inpos ] );
-
-                /* Copy corresponding data from history window */
-                for( i = 0; i < length; ++ i )
-                {
-                    out[ outpos ] = out[ outpos - offset ];
-                    ++ outpos;
-                }
-            }
-        }
-        else
-        {
-            /* No marker, plain copy */
-            out[ outpos ++ ] = symbol;
-        }
-    }
-    while( inpos < insize );
-
-    return outpos;
-}

fusee/common/lz.h

@@ -1,51 +0,0 @@
-/*************************************************************************
-* Name:        lz.h
-* Author:      Marcus Geelnard
-* Description: LZ77 coder/decoder interface.
-* Reentrant:   Yes
-*-------------------------------------------------------------------------
-* Copyright (c) 2003-2006 Marcus Geelnard
-*
-* This software is provided 'as-is', without any express or implied
-* warranty. In no event will the authors be held liable for any damages
-* arising from the use of this software.
-*
-* Permission is granted to anyone to use this software for any purpose,
-* including commercial applications, and to alter it and redistribute it
-* freely, subject to the following restrictions:
-*
-* 1. The origin of this software must not be misrepresented; you must not
-*    claim that you wrote the original software. If you use this software
-*    in a product, an acknowledgment in the product documentation would
-*    be appreciated but is not required.
-*
-* 2. Altered source versions must be plainly marked as such, and must not
-*    be misrepresented as being the original software.
-*
-* 3. This notice may not be removed or altered from any source
-*    distribution.
-*
-* Marcus Geelnard
-* marcus.geelnard at home.se
-*************************************************************************/
-
-#ifndef _lz_h_
-#define _lz_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*************************************************************************
-* Function prototypes
-*************************************************************************/
-
-int LZ_Compress(const unsigned char *in, unsigned char *out, unsigned int insize);
-int LZ_Uncompress(const unsigned char *in, unsigned char *out, unsigned int insize);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _lz_h_ */

fusee/common/sdmmc/mmc.h

@@ -1,449 +0,0 @@
-/*
- * Header for MultiMediaCard (MMC)
- *
- * Copyright 2002 Hewlett-Packard Company
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * Use consistent with the GNU GPL is permitted,
- * provided that this copyright notice is
- * preserved in its entirety in all copies and derived works.
- *
- * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
- * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
- * FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- * Many thanks to Alessandro Rubini and Jonathan Corbet!
- *
- * Based strongly on code by:
- *
- * Author: Yong-iL Joh <tolkien@mizi.com>
- *
- * Author:  Andrew Christian
- *          15 May 2002
- */
-
-#ifndef LINUX_MMC_MMC_H
-#define LINUX_MMC_MMC_H
-
-/* Standard MMC commands (4.1)           type  argument     response */
-   /* class 1 */
-#define MMC_GO_IDLE_STATE         0   /* bc                          */
-#define MMC_SEND_OP_COND          1   /* bcr  [31:0] OCR         R3  */
-#define MMC_ALL_SEND_CID          2   /* bcr                     R2  */
-#define MMC_SET_RELATIVE_ADDR     3   /* ac   [31:16] RCA        R1  */
-#define MMC_SET_DSR               4   /* bc   [31:16] RCA            */
-#define MMC_SLEEP_AWAKE           5   /* ac   [31:16] RCA 15:flg R1b */
-#define MMC_SWITCH                6   /* ac   [31:0] See below   R1b */
-#define MMC_SELECT_CARD           7   /* ac   [31:16] RCA        R1  */
-#define MMC_SEND_EXT_CSD          8   /* adtc                    R1  */
-#define MMC_SEND_CSD              9   /* ac   [31:16] RCA        R2  */
-#define MMC_SEND_CID             10   /* ac   [31:16] RCA        R2  */
-#define MMC_READ_DAT_UNTIL_STOP  11   /* adtc [31:0] dadr        R1  */
-#define MMC_STOP_TRANSMISSION    12   /* ac                      R1b */
-#define MMC_SEND_STATUS          13   /* ac   [31:16] RCA        R1  */
-#define MMC_BUS_TEST_R           14   /* adtc                    R1  */
-#define MMC_GO_INACTIVE_STATE    15   /* ac   [31:16] RCA            */
-#define MMC_BUS_TEST_W           19   /* adtc                    R1  */
-#define MMC_SPI_READ_OCR         58   /* spi                  spi_R3 */
-#define MMC_SPI_CRC_ON_OFF       59   /* spi  [0:0] flag      spi_R1 */
-
-  /* class 2 */
-#define MMC_SET_BLOCKLEN            16   /* ac   [31:0] block len   R1  */
-#define MMC_READ_SINGLE_BLOCK       17   /* adtc [31:0] data addr   R1  */
-#define MMC_READ_MULTIPLE_BLOCK     18   /* adtc [31:0] data addr   R1  */
-#define MMC_SEND_TUNING_BLOCK       19   /* adtc                    R1  */
-#define MMC_SEND_TUNING_BLOCK_HS200 21   /* adtc R1  */
-
-  /* class 3 */
-#define MMC_WRITE_DAT_UNTIL_STOP 20   /* adtc [31:0] data addr   R1  */
-
-  /* class 4 */
-#define MMC_SET_BLOCK_COUNT      23   /* adtc [31:0] data addr   R1  */
-#define MMC_WRITE_BLOCK          24   /* adtc [31:0] data addr   R1  */
-#define MMC_WRITE_MULTIPLE_BLOCK 25   /* adtc                    R1  */
-#define MMC_PROGRAM_CID          26   /* adtc                    R1  */
-#define MMC_PROGRAM_CSD          27   /* adtc                    R1  */
-
-  /* class 6 */
-#define MMC_SET_WRITE_PROT       28   /* ac   [31:0] data addr   R1b */
-#define MMC_CLR_WRITE_PROT       29   /* ac   [31:0] data addr   R1b */
-#define MMC_SEND_WRITE_PROT      30   /* adtc [31:0] wpdata addr R1  */
-
-  /* class 5 */
-#define MMC_ERASE_GROUP_START    35   /* ac   [31:0] data addr   R1  */
-#define MMC_ERASE_GROUP_END      36   /* ac   [31:0] data addr   R1  */
-#define MMC_ERASE                38   /* ac                      R1b */
-
-  /* class 9 */
-#define MMC_FAST_IO              39   /* ac   <Complex>          R4  */
-#define MMC_GO_IRQ_STATE         40   /* bcr                     R5  */
-
-  /* class 7 */
-#define MMC_LOCK_UNLOCK          42   /* adtc                    R1b */
-
-  /* class 8 */
-#define MMC_APP_CMD              55   /* ac   [31:16] RCA        R1  */
-#define MMC_GEN_CMD              56   /* adtc [0] RD/WR          R1  */
-
-  /* class 11 */
-#define MMC_QUE_TASK_PARAMS      44   /* ac   [20:16] task id    R1  */
-#define MMC_QUE_TASK_ADDR        45   /* ac   [31:0] data addr   R1  */
-#define MMC_EXECUTE_READ_TASK    46   /* adtc [20:16] task id    R1  */
-#define MMC_EXECUTE_WRITE_TASK   47   /* adtc [20:16] task id    R1  */
-#define MMC_CMDQ_TASK_MGMT       48   /* ac   [20:16] task id    R1b */
-
-/*
- * MMC_SWITCH argument format:
- *
- *  [31:26] Always 0
- *  [25:24] Access Mode
- *  [23:16] Location of target Byte in EXT_CSD
- *  [15:08] Value Byte
- *  [07:03] Always 0
- *  [02:00] Command Set
- */
-
-/*
-  MMC status in R1, for native mode (SPI bits are different)
-  Type
-    e : error bit
-    s : status bit
-    r : detected and set for the actual command response
-    x : detected and set during command execution. the host must poll
-            the card by sending status command in order to read these bits.
-  Clear condition
-    a : according to the card state
-    b : always related to the previous command. Reception of
-            a valid command will clear it (with a delay of one command)
-    c : clear by read
- */
-
-#define R1_OUT_OF_RANGE     (1 << 31)   /* er, c */
-#define R1_ADDRESS_ERROR    (1 << 30)   /* erx, c */
-#define R1_BLOCK_LEN_ERROR  (1 << 29)   /* er, c */
-#define R1_ERASE_SEQ_ERROR      (1 << 28)   /* er, c */
-#define R1_ERASE_PARAM      (1 << 27)   /* ex, c */
-#define R1_WP_VIOLATION     (1 << 26)   /* erx, c */
-#define R1_CARD_IS_LOCKED   (1 << 25)   /* sx, a */
-#define R1_LOCK_UNLOCK_FAILED   (1 << 24)   /* erx, c */
-#define R1_COM_CRC_ERROR    (1 << 23)   /* er, b */
-#define R1_ILLEGAL_COMMAND  (1 << 22)   /* er, b */
-#define R1_CARD_ECC_FAILED  (1 << 21)   /* ex, c */
-#define R1_CC_ERROR     (1 << 20)   /* erx, c */
-#define R1_ERROR        (1 << 19)   /* erx, c */
-#define R1_UNDERRUN     (1 << 18)   /* ex, c */
-#define R1_OVERRUN      (1 << 17)   /* ex, c */
-#define R1_CID_CSD_OVERWRITE    (1 << 16)   /* erx, c, CID/CSD overwrite */
-#define R1_WP_ERASE_SKIP    (1 << 15)   /* sx, c */
-#define R1_CARD_ECC_DISABLED    (1 << 14)   /* sx, a */
-#define R1_ERASE_RESET      (1 << 13)   /* sr, c */
-#define R1_STATUS(x)            (x & 0xFFFFE000)
-#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
-#define R1_READY_FOR_DATA   (1 << 8)    /* sx, a */
-#define R1_SWITCH_ERROR     (1 << 7)    /* sx, c */
-#define R1_EXCEPTION_EVENT  (1 << 6)    /* sr, a */
-#define R1_APP_CMD      (1 << 5)    /* sr, c */
-
-#define R1_STATE_IDLE   0
-#define R1_STATE_READY  1
-#define R1_STATE_IDENT  2
-#define R1_STATE_STBY   3
-#define R1_STATE_TRAN   4
-#define R1_STATE_DATA   5
-#define R1_STATE_RCV    6
-#define R1_STATE_PRG    7
-#define R1_STATE_DIS    8
-
-/*
- * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
- * R1 is the low order byte; R2 is the next highest byte, when present.
- */
-#define R1_SPI_IDLE     (1 << 0)
-#define R1_SPI_ERASE_RESET  (1 << 1)
-#define R1_SPI_ILLEGAL_COMMAND  (1 << 2)
-#define R1_SPI_COM_CRC      (1 << 3)
-#define R1_SPI_ERASE_SEQ    (1 << 4)
-#define R1_SPI_ADDRESS      (1 << 5)
-#define R1_SPI_PARAMETER    (1 << 6)
-/* R1 bit 7 is always zero */
-#define R2_SPI_CARD_LOCKED  (1 << 8)
-#define R2_SPI_WP_ERASE_SKIP    (1 << 9)    /* or lock/unlock fail */
-#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
-#define R2_SPI_ERROR        (1 << 10)
-#define R2_SPI_CC_ERROR     (1 << 11)
-#define R2_SPI_CARD_ECC_ERROR   (1 << 12)
-#define R2_SPI_WP_VIOLATION (1 << 13)
-#define R2_SPI_ERASE_PARAM  (1 << 14)
-#define R2_SPI_OUT_OF_RANGE (1 << 15)   /* or CSD overwrite */
-#define R2_SPI_CSD_OVERWRITE    R2_SPI_OUT_OF_RANGE
-
-/*
- * OCR bits are mostly in host.h
- */
-#define MMC_CARD_BUSY       0x80000000  /* Card Power up status bit */
-#define MMC_VDD_165_195     0x00000080  /* VDD voltage 1.65 - 1.95 */
-#define MMC_VDD_20_21       0x00000100  /* VDD voltage 2.0 ~ 2.1 */
-#define MMC_VDD_21_22       0x00000200  /* VDD voltage 2.1 ~ 2.2 */
-#define MMC_VDD_22_23       0x00000400  /* VDD voltage 2.2 ~ 2.3 */
-#define MMC_VDD_23_24       0x00000800  /* VDD voltage 2.3 ~ 2.4 */
-#define MMC_VDD_24_25       0x00001000  /* VDD voltage 2.4 ~ 2.5 */
-#define MMC_VDD_25_26       0x00002000  /* VDD voltage 2.5 ~ 2.6 */
-#define MMC_VDD_26_27       0x00004000  /* VDD voltage 2.6 ~ 2.7 */
-#define MMC_VDD_27_28       0x00008000  /* VDD voltage 2.7 ~ 2.8 */
-#define MMC_VDD_28_29       0x00010000  /* VDD voltage 2.8 ~ 2.9 */
-#define MMC_VDD_29_30       0x00020000  /* VDD voltage 2.9 ~ 3.0 */
-#define MMC_VDD_30_31       0x00040000  /* VDD voltage 3.0 ~ 3.1 */
-#define MMC_VDD_31_32       0x00080000  /* VDD voltage 3.1 ~ 3.2 */
-#define MMC_VDD_32_33       0x00100000  /* VDD voltage 3.2 ~ 3.3 */
-#define MMC_VDD_33_34       0x00200000  /* VDD voltage 3.3 ~ 3.4 */
-#define MMC_VDD_34_35       0x00400000  /* VDD voltage 3.4 ~ 3.5 */
-#define MMC_VDD_35_36       0x00800000  /* VDD voltage 3.5 ~ 3.6 */
-
-/*
- * Card Command Classes (CCC)
- */
-#define CCC_BASIC       (1<<0)  /* (0) Basic protocol functions */
-                    /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
-                    /* (and for SPI, CMD58,59) */
-#define CCC_STREAM_READ     (1<<1)  /* (1) Stream read commands */
-                    /* (CMD11) */
-#define CCC_BLOCK_READ      (1<<2)  /* (2) Block read commands */
-                    /* (CMD16,17,18) */
-#define CCC_STREAM_WRITE    (1<<3)  /* (3) Stream write commands */
-                    /* (CMD20) */
-#define CCC_BLOCK_WRITE     (1<<4)  /* (4) Block write commands */
-                    /* (CMD16,24,25,26,27) */
-#define CCC_ERASE       (1<<5)  /* (5) Ability to erase blocks */
-                    /* (CMD32,33,34,35,36,37,38,39) */
-#define CCC_WRITE_PROT      (1<<6)  /* (6) Able to write protect blocks */
-                    /* (CMD28,29,30) */
-#define CCC_LOCK_CARD       (1<<7)  /* (7) Able to lock down card */
-                    /* (CMD16,CMD42) */
-#define CCC_APP_SPEC        (1<<8)  /* (8) Application specific */
-                    /* (CMD55,56,57,ACMD*) */
-#define CCC_IO_MODE     (1<<9)  /* (9) I/O mode */
-                    /* (CMD5,39,40,52,53) */
-#define CCC_SWITCH      (1<<10) /* (10) High speed switch */
-                    /* (CMD6,34,35,36,37,50) */
-                    /* (11) Reserved */
-                    /* (CMD?) */
-
-/*
- * CSD field definitions
- */
-
-#define CSD_STRUCT_VER_1_0  0           /* Valid for system specification 1.0 - 1.2 */
-#define CSD_STRUCT_VER_1_1  1           /* Valid for system specification 1.4 - 2.2 */
-#define CSD_STRUCT_VER_1_2  2           /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
-#define CSD_STRUCT_EXT_CSD  3           /* Version is coded in CSD_STRUCTURE in EXT_CSD */
-
-#define CSD_SPEC_VER_0      0           /* Implements system specification 1.0 - 1.2 */
-#define CSD_SPEC_VER_1      1           /* Implements system specification 1.4 */
-#define CSD_SPEC_VER_2      2           /* Implements system specification 2.0 - 2.2 */
-#define CSD_SPEC_VER_3      3           /* Implements system specification 3.1 - 3.2 - 3.31 */
-#define CSD_SPEC_VER_4      4           /* Implements system specification 4.0 - 4.1 */
-
-/*
- * EXT_CSD fields
- */
-
-#define EXT_CSD_CMDQ_MODE_EN        15  /* R/W */
-#define EXT_CSD_FLUSH_CACHE     32      /* W */
-#define EXT_CSD_CACHE_CTRL      33      /* R/W */
-#define EXT_CSD_POWER_OFF_NOTIFICATION  34  /* R/W */
-#define EXT_CSD_PACKED_FAILURE_INDEX    35  /* RO */
-#define EXT_CSD_PACKED_CMD_STATUS   36  /* RO */
-#define EXT_CSD_EXP_EVENTS_STATUS   54  /* RO, 2 bytes */
-#define EXT_CSD_EXP_EVENTS_CTRL     56  /* R/W, 2 bytes */
-#define EXT_CSD_DATA_SECTOR_SIZE    61  /* R */
-#define EXT_CSD_GP_SIZE_MULT        143 /* R/W */
-#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
-#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
-#define EXT_CSD_PARTITION_SUPPORT   160 /* RO */
-#define EXT_CSD_HPI_MGMT        161 /* R/W */
-#define EXT_CSD_RST_N_FUNCTION      162 /* R/W */
-#define EXT_CSD_BKOPS_EN        163 /* R/W */
-#define EXT_CSD_BKOPS_START     164 /* W */
-#define EXT_CSD_SANITIZE_START      165     /* W */
-#define EXT_CSD_WR_REL_PARAM        166 /* RO */
-#define EXT_CSD_RPMB_MULT       168 /* RO */
-#define EXT_CSD_FW_CONFIG       169 /* R/W */
-#define EXT_CSD_BOOT_WP         173 /* R/W */
-#define EXT_CSD_ERASE_GROUP_DEF     175 /* R/W */
-#define EXT_CSD_PART_CONFIG     179 /* R/W */
-#define EXT_CSD_ERASED_MEM_CONT     181 /* RO */
-#define EXT_CSD_BUS_WIDTH       183 /* R/W */
-#define EXT_CSD_STROBE_SUPPORT      184 /* RO */
-#define EXT_CSD_HS_TIMING       185 /* R/W */
-#define EXT_CSD_POWER_CLASS     187 /* R/W */
-#define EXT_CSD_REV         192 /* RO */
-#define EXT_CSD_STRUCTURE       194 /* RO */
-#define EXT_CSD_CARD_TYPE       196 /* RO */
-#define EXT_CSD_DRIVER_STRENGTH     197 /* RO */
-#define EXT_CSD_OUT_OF_INTERRUPT_TIME   198 /* RO */
-#define EXT_CSD_PART_SWITCH_TIME        199     /* RO */
-#define EXT_CSD_PWR_CL_52_195       200 /* RO */
-#define EXT_CSD_PWR_CL_26_195       201 /* RO */
-#define EXT_CSD_PWR_CL_52_360       202 /* RO */
-#define EXT_CSD_PWR_CL_26_360       203 /* RO */
-#define EXT_CSD_SEC_CNT         212 /* RO, 4 bytes */
-#define EXT_CSD_S_A_TIMEOUT     217 /* RO */
-#define EXT_CSD_REL_WR_SEC_C        222 /* RO */
-#define EXT_CSD_HC_WP_GRP_SIZE      221 /* RO */
-#define EXT_CSD_ERASE_TIMEOUT_MULT  223 /* RO */
-#define EXT_CSD_HC_ERASE_GRP_SIZE   224 /* RO */
-#define EXT_CSD_BOOT_MULT       226 /* RO */
-#define EXT_CSD_SEC_TRIM_MULT       229 /* RO */
-#define EXT_CSD_SEC_ERASE_MULT      230 /* RO */
-#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
-#define EXT_CSD_TRIM_MULT       232 /* RO */
-#define EXT_CSD_PWR_CL_200_195      236 /* RO */
-#define EXT_CSD_PWR_CL_200_360      237 /* RO */
-#define EXT_CSD_PWR_CL_DDR_52_195   238 /* RO */
-#define EXT_CSD_PWR_CL_DDR_52_360   239 /* RO */
-#define EXT_CSD_BKOPS_STATUS        246 /* RO */
-#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
-#define EXT_CSD_GENERIC_CMD6_TIME   248 /* RO */
-#define EXT_CSD_CACHE_SIZE      249 /* RO, 4 bytes */
-#define EXT_CSD_PWR_CL_DDR_200_360  253 /* RO */
-#define EXT_CSD_FIRMWARE_VERSION    254 /* RO, 8 bytes */
-#define EXT_CSD_PRE_EOL_INFO        267 /* RO */
-#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A  268 /* RO */
-#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B  269 /* RO */
-#define EXT_CSD_CMDQ_DEPTH      307 /* RO */
-#define EXT_CSD_CMDQ_SUPPORT        308 /* RO */
-#define EXT_CSD_SUPPORTED_MODE      493 /* RO */
-#define EXT_CSD_TAG_UNIT_SIZE       498 /* RO */
-#define EXT_CSD_DATA_TAG_SUPPORT    499 /* RO */
-#define EXT_CSD_MAX_PACKED_WRITES   500 /* RO */
-#define EXT_CSD_MAX_PACKED_READS    501 /* RO */
-#define EXT_CSD_BKOPS_SUPPORT       502 /* RO */
-#define EXT_CSD_HPI_FEATURES        503 /* RO */
-
-/*
- * EXT_CSD field definitions
- */
-
-#define EXT_CSD_WR_REL_PARAM_EN     (1<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
-
-#define EXT_CSD_PART_SETTING_COMPLETED  (0x1)
-#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1)
-
-#define EXT_CSD_CMD_SET_NORMAL      (1<<0)
-#define EXT_CSD_CMD_SET_SECURE      (1<<1)
-#define EXT_CSD_CMD_SET_CPSECURE    (1<<2)
-
-#define EXT_CSD_CARD_TYPE_HS_26 (1<<0)  /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_HS_52 (1<<1)  /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_HS    (EXT_CSD_CARD_TYPE_HS_26 | \
-                 EXT_CSD_CARD_TYPE_HS_52)
-#define EXT_CSD_CARD_TYPE_DDR_1_8V  (1<<2)   /* Card can run at 52MHz */
-                         /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V  (1<<3)   /* Card can run at 52MHz */
-                         /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52       (EXT_CSD_CARD_TYPE_DDR_1_8V  \
-                    | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_HS200_1_8V    (1<<4)  /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_HS200_1_2V    (1<<5)  /* Card can run at 200MHz */
-                        /* SDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_HS200     (EXT_CSD_CARD_TYPE_HS200_1_8V | \
-                     EXT_CSD_CARD_TYPE_HS200_1_2V)
-#define EXT_CSD_CARD_TYPE_HS400_1_8V    (1<<6)  /* Card can run at 200MHz DDR, 1.8V */
-#define EXT_CSD_CARD_TYPE_HS400_1_2V    (1<<7)  /* Card can run at 200MHz DDR, 1.2V */
-#define EXT_CSD_CARD_TYPE_HS400     (EXT_CSD_CARD_TYPE_HS400_1_8V | \
-                     EXT_CSD_CARD_TYPE_HS400_1_2V)
-#define EXT_CSD_CARD_TYPE_HS400ES   (1<<8)  /* Card can run at HS400ES */
-
-#define EXT_CSD_BUS_WIDTH_1 0   /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4 1   /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8 2   /* Card is in 8 bit mode */
-#define EXT_CSD_DDR_BUS_WIDTH_4 5   /* Card is in 4 bit DDR mode */
-#define EXT_CSD_DDR_BUS_WIDTH_8 6   /* Card is in 8 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
-
-#define EXT_CSD_TIMING_BC   0   /* Backwards compatility */
-#define EXT_CSD_TIMING_HS   1   /* High speed */
-#define EXT_CSD_TIMING_HS200    2   /* HS200 */
-#define EXT_CSD_TIMING_HS400    3   /* HS400 */
-#define EXT_CSD_DRV_STR_SHIFT   4   /* Driver Strength shift */
-
-#define EXT_CSD_SEC_ER_EN   BIT(0)
-#define EXT_CSD_SEC_BD_BLK_EN   BIT(2)
-#define EXT_CSD_SEC_GB_CL_EN    BIT(4)
-#define EXT_CSD_SEC_SANITIZE    BIT(6)  /* v4.5 only */
-
-#define EXT_CSD_RST_N_EN_MASK   0x3
-#define EXT_CSD_RST_N_ENABLED   1   /* RST_n is enabled on card */
-
-#define EXT_CSD_NO_POWER_NOTIFICATION   0
-#define EXT_CSD_POWER_ON        1
-#define EXT_CSD_POWER_OFF_SHORT     2
-#define EXT_CSD_POWER_OFF_LONG      3
-
-#define EXT_CSD_PWR_CL_8BIT_MASK    0xF0    /* 8 bit PWR CLS */
-#define EXT_CSD_PWR_CL_4BIT_MASK    0x0F    /* 8 bit PWR CLS */
-#define EXT_CSD_PWR_CL_8BIT_SHIFT   4
-#define EXT_CSD_PWR_CL_4BIT_SHIFT   0
-
-#define EXT_CSD_PACKED_EVENT_EN BIT(3)
-
-/*
- * EXCEPTION_EVENT_STATUS field
- */
-#define EXT_CSD_URGENT_BKOPS        BIT(0)
-#define EXT_CSD_DYNCAP_NEEDED       BIT(1)
-#define EXT_CSD_SYSPOOL_EXHAUSTED   BIT(2)
-#define EXT_CSD_PACKED_FAILURE      BIT(3)
-
-#define EXT_CSD_PACKED_GENERIC_ERROR    BIT(0)
-#define EXT_CSD_PACKED_INDEXED_ERROR    BIT(1)
-
-/*
- * BKOPS status level
- */
-#define EXT_CSD_BKOPS_LEVEL_2       0x2
-
-/*
- * BKOPS modes
- */
-#define EXT_CSD_MANUAL_BKOPS_MASK   0x01
-#define EXT_CSD_AUTO_BKOPS_MASK     0x02
-
-/*
- * Command Queue
- */
-#define EXT_CSD_CMDQ_MODE_ENABLED   BIT(0)
-#define EXT_CSD_CMDQ_DEPTH_MASK     GENMASK(4, 0)
-#define EXT_CSD_CMDQ_SUPPORTED      BIT(0)
-
-/*
- * MMC_SWITCH access modes
- */
-#define MMC_SWITCH_MODE_CMD_SET     0x00    /* Change the command set */
-#define MMC_SWITCH_MODE_SET_BITS    0x01    /* Set bits which are 1 in value */
-#define MMC_SWITCH_MODE_CLEAR_BITS  0x02    /* Clear bits which are 1 in value */
-#define MMC_SWITCH_MODE_WRITE_BYTE  0x03    /* Set target to value */
-
-/*
- * Erase/trim/discard
- */
-#define MMC_ERASE_ARG           0x00000000
-#define MMC_SECURE_ERASE_ARG        0x80000000
-#define MMC_TRIM_ARG            0x00000001
-#define MMC_DISCARD_ARG         0x00000003
-#define MMC_SECURE_TRIM1_ARG        0x80000001
-#define MMC_SECURE_TRIM2_ARG        0x80008000
-#define MMC_SECURE_ARGS         0x80000000
-#define MMC_TRIM_ARGS           0x00008001
-
-#endif /* LINUX_MMC_MMC_H */

fusee/common/sdmmc/sd.h

@@ -1,155 +0,0 @@
-/*
- *  include/linux/mmc/sd.h
- *
- *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
- *  Copyright (C) 2018 CTCaer
- *  Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-
-#ifndef LINUX_MMC_SD_H
-#define LINUX_MMC_SD_H
-
-/* SD commands                           type  argument     response */
-/* class 0 */
-/* This is basically the same command as for MMC with some quirks. */
-#define SD_SEND_RELATIVE_ADDR     3   /* bcr                     R6  */
-#define SD_SEND_IF_COND           8   /* bcr  [11:0] See below   R7  */
-#define SD_SWITCH_VOLTAGE         11  /* ac                      R1  */
-
-/* class 10 */
-#define SD_SWITCH                 6   /* adtc [31:0] See below   R1  */
-
-/* class 5 */
-#define SD_ERASE_WR_BLK_START    32   /* ac   [31:0] data addr   R1  */
-#define SD_ERASE_WR_BLK_END      33   /* ac   [31:0] data addr   R1  */
-
-/* Application commands */
-#define SD_APP_SET_BUS_WIDTH        6   /* ac   [1:0] bus width    R1  */
-#define SD_APP_SD_STATUS            13  /* adtc                    R1  */
-#define SD_APP_SEND_NUM_WR_BLKS     22  /* adtc                    R1  */
-#define SD_APP_OP_COND              41  /* bcr  [31:0] OCR         R3  */
-#define SD_APP_SET_CLR_CARD_DETECT  42  /* ac   [0] set cd         R1  */
-#define SD_APP_SEND_SCR             51  /* adtc                    R1  */
-
-/* OCR bit definitions */
-#define SD_OCR_S18R             (1 << 24)                   /* 1.8V switching request */
-#define SD_ROCR_S18A            SD_OCR_S18R                 /* 1.8V switching accepted by card */
-#define SD_OCR_XPC              (1 << 28)                   /* SDXC power control */
-#define SD_OCR_CCS              (1 << 30)                   /* Card Capacity Status */
-#define SD_OCR_VDD_LOW          (1 << 7)                    /* SD: Reserved for Low Voltage Range */
-#define SD_OCR_VDD_20_21        (1 << 8)
-#define SD_OCR_VDD_21_22        (1 << 9)
-#define SD_OCR_VDD_22_23        (1 << 10)
-#define SD_OCR_VDD_23_24        (1 << 11)
-#define SD_OCR_VDD_24_25        (1 << 12)
-#define SD_OCR_VDD_25_26        (1 << 13)
-#define SD_OCR_VDD_26_27        (1 << 14)
-#define SD_OCR_VDD_27_28        (1 << 15)
-#define SD_OCR_VDD_28_29        (1 << 16)
-#define SD_OCR_VDD_29_30        (1 << 17)
-#define SD_OCR_VDD_30_31        (1 << 18)
-#define SD_OCR_VDD_31_32        (1 << 19)
-#define SD_OCR_VDD_32_33        (1 << 20)
-#define SD_OCR_VDD_33_34        (1 << 21)
-#define SD_OCR_VDD_34_35        (1 << 22)
-#define SD_OCR_VDD_35_36        (1 << 23)
-
-/*
- * SD_SWITCH argument format:
- *
- *      [31] Check (0) or switch (1)
- *      [30:24] Reserved (0)
- *      [23:20] Function group 6
- *      [19:16] Function group 5
- *      [15:12] Function group 4
- *      [11:8] Function group 3
- *      [7:4] Function group 2
- *      [3:0] Function group 1
- */
-
-/*
- * SD_SEND_IF_COND argument format:
- *
- *  [31:12] Reserved (0)
- *  [11:8] Host Voltage Supply Flags
- *  [7:0] Check Pattern (0xAA)
- */
-
-/*
- * SCR field definitions
- */
-
-#define SD_SCR_SPEC_VER_0       0   /* Implements system specification 1.0 - 1.01 */
-#define SD_SCR_SPEC_VER_1       1   /* Implements system specification 1.10 */
-#define SD_SCR_SPEC_VER_2       2   /* Implements system specification 2.00-3.0X */
-#define SD_SCR_BUS_WIDTH_1      1
-#define SD_SCR_BUS_WIDTH_4      4
-#define SD_SCR_CMD20_SUPPORT    1
-#define SD_SCR_CMD23_SUPPORT    2
-
-/*
- * SD bus widths
- */
-#define SD_BUS_WIDTH_1      0
-#define SD_BUS_WIDTH_4      2
-
-/*
- * SD bus speed modes
- */
-#define UHS_SDR12_BUS_SPEED     0
-#define HIGH_SPEED_BUS_SPEED    1
-#define UHS_SDR25_BUS_SPEED     1
-#define UHS_SDR50_BUS_SPEED     2
-#define UHS_SDR104_BUS_SPEED    3
-#define UHS_DDR50_BUS_SPEED     4
-#define SD_MODE_HIGH_SPEED      (1 << HIGH_SPEED_BUS_SPEED)
-#define SD_MODE_UHS_SDR12       (1 << UHS_SDR12_BUS_SPEED)
-#define SD_MODE_UHS_SDR25       (1 << UHS_SDR25_BUS_SPEED)
-#define SD_MODE_UHS_SDR50       (1 << UHS_SDR50_BUS_SPEED)
-#define SD_MODE_UHS_SDR104      (1 << UHS_SDR104_BUS_SPEED)
-#define SD_MODE_UHS_DDR50       (1 << UHS_DDR50_BUS_SPEED)
-
-/*
- * SD bus driver types
- */
-#define SD_DRIVER_TYPE_B    0x01
-#define SD_DRIVER_TYPE_A    0x02
-#define SD_DRIVER_TYPE_C    0x04
-#define SD_DRIVER_TYPE_D    0x08
-
-/*
- * SD bus current limits
- */
-#define SD_SET_CURRENT_LIMIT_200    0
-#define SD_SET_CURRENT_LIMIT_400    1
-#define SD_SET_CURRENT_LIMIT_600    2
-#define SD_SET_CURRENT_LIMIT_800    3
-#define SD_SET_CURRENT_NO_CHANGE    (-1)
-#define SD_MAX_CURRENT_200          (1 << SD_SET_CURRENT_LIMIT_200)
-#define SD_MAX_CURRENT_400          (1 << SD_SET_CURRENT_LIMIT_400)
-#define SD_MAX_CURRENT_600          (1 << SD_SET_CURRENT_LIMIT_600)
-#define SD_MAX_CURRENT_800          (1 << SD_SET_CURRENT_LIMIT_800)
-
-/*
- * SD_SWITCH mode
- */
-#define SD_SWITCH_CHECK     0
-#define SD_SWITCH_SET       1
-
-/*
- * SD_SWITCH function groups
- */
-#define SD_SWITCH_GRP_ACCESS    0
-
-/*
- * SD_SWITCH access modes
- */
-#define SD_SWITCH_ACCESS_DEF    0
-#define SD_SWITCH_ACCESS_HS     1
-
-#endif /* LINUX_MMC_SD_H */

fusee/common/sdmmc/sdmmc.h

@@ -1,179 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_SDMMC_H
-#define FUSEE_SDMMC_H
-
-#include "sdmmc_core.h"
-
-/* Structure for storing the MMC CID (adapted from Linux headers) */
-typedef struct {
-    uint32_t    manfid;
-    uint8_t     prod_name[8];
-    uint8_t     prv;
-    uint32_t    serial;
-    uint16_t    oemid;
-    uint16_t    year;
-    uint8_t     hwrev;
-    uint8_t     fwrev;
-    uint8_t     month;
-} mmc_cid_t;
-
-/* Structure for storing the MMC CSD (adapted from Linux headers) */
-typedef struct {
-    uint8_t     structure;
-    uint8_t     mmca_vsn;
-    uint16_t    cmdclass;
-    uint16_t    taac_clks;
-    uint32_t    taac_ns;
-    uint32_t    c_size;
-    uint32_t    r2w_factor;
-    uint32_t    max_dtr;
-    uint32_t    erase_size;     /* In sectors */
-    uint32_t    read_blkbits;
-    uint32_t    write_blkbits;
-    uint32_t    capacity;
-    uint32_t    read_partial:1,
-                read_misalign:1,
-                write_partial:1,
-                write_misalign:1,
-                dsr_imp:1;
-} mmc_csd_t;
-
-/* Structure for storing the MMC extended CSD (adapted from Linux headers) */
-typedef struct {
-    uint8_t     rev;
-    uint8_t     erase_group_def;
-    uint8_t     sec_feature_support;
-    uint8_t     rel_sectors;
-    uint8_t     rel_param;
-    uint8_t     part_config;
-    uint8_t     cache_ctrl;
-    uint8_t     rst_n_function;
-    uint8_t     max_packed_writes;
-    uint8_t     max_packed_reads;
-    uint8_t     packed_event_en;
-    uint32_t    part_time;                      /* Units: ms */
-    uint32_t    sa_timeout;                     /* Units: 100ns */
-    uint32_t    generic_cmd6_time;              /* Units: 10ms */
-    uint32_t    power_off_longtime;             /* Units: ms */
-    uint8_t     power_off_notification;         /* state */
-    uint32_t    hs_max_dtr;
-    uint32_t    hs200_max_dtr;
-    uint32_t    sectors;
-    uint32_t    hc_erase_size;                  /* In sectors */
-    uint32_t    hc_erase_timeout;               /* In milliseconds */
-    uint32_t    sec_trim_mult;                  /* Secure trim multiplier  */
-    uint32_t    sec_erase_mult;                 /* Secure erase multiplier */
-    uint32_t    trim_timeout;                   /* In milliseconds */
-    uint32_t    partition_setting_completed;    /* enable bit */
-    uint64_t    enhanced_area_offset;           /* Units: Byte */
-    uint32_t    enhanced_area_size;             /* Units: KB */
-    uint32_t    cache_size;                     /* Units: KB */
-    uint32_t    hpi_en;                         /* HPI enablebit */
-    uint32_t    hpi;                            /* HPI support bit */
-    uint32_t    hpi_cmd;                        /* cmd used as HPI */
-    uint32_t    bkops;                          /* background support bit */
-    uint32_t    man_bkops_en;                   /* manual bkops enable bit */
-    uint32_t    auto_bkops_en;                  /* auto bkops enable bit */
-    uint32_t    data_sector_size;               /* 512 bytes or 4KB */
-    uint32_t    data_tag_unit_size;             /* DATA TAG UNIT size */
-    uint32_t    boot_ro_lock;                   /* ro lock support */
-    uint32_t    boot_ro_lockable;
-    uint32_t    ffu_capable;                    /* Firmware upgrade support */
-    uint32_t    cmdq_en;                        /* Command Queue enabled */
-    uint32_t    cmdq_support;                   /* Command Queue supported */
-    uint32_t    cmdq_depth;                     /* Command Queue depth */
-    uint8_t     fwrev[8];                       /* FW version */
-    uint8_t     raw_exception_status;           /* 54 */
-    uint8_t     raw_partition_support;          /* 160 */
-    uint8_t     raw_rpmb_size_mult;             /* 168 */
-    uint8_t     raw_erased_mem_count;           /* 181 */
-    uint8_t     strobe_support;                 /* 184 */
-    uint8_t     raw_ext_csd_structure;          /* 194 */
-    uint8_t     raw_card_type;                  /* 196 */
-    uint8_t     raw_driver_strength;            /* 197 */
-    uint8_t     out_of_int_time;                /* 198 */
-    uint8_t     raw_pwr_cl_52_195;              /* 200 */
-    uint8_t     raw_pwr_cl_26_195;              /* 201 */
-    uint8_t     raw_pwr_cl_52_360;              /* 202 */
-    uint8_t     raw_pwr_cl_26_360;              /* 203 */
-    uint8_t     raw_s_a_timeout;                /* 217 */
-    uint8_t     raw_hc_erase_gap_size;          /* 221 */
-    uint8_t     raw_erase_timeout_mult;         /* 223 */
-    uint8_t     raw_hc_erase_grp_size;          /* 224 */
-    uint8_t     raw_sec_trim_mult;              /* 229 */
-    uint8_t     raw_sec_erase_mult;             /* 230 */
-    uint8_t     raw_sec_feature_support;        /* 231 */
-    uint8_t     raw_trim_mult;                  /* 232 */
-    uint8_t     raw_pwr_cl_200_195;             /* 236 */
-    uint8_t     raw_pwr_cl_200_360;             /* 237 */
-    uint8_t     raw_pwr_cl_ddr_52_195;          /* 238 */
-    uint8_t     raw_pwr_cl_ddr_52_360;          /* 239 */
-    uint8_t     raw_pwr_cl_ddr_200_360;         /* 253 */
-    uint8_t     raw_bkops_status;               /* 246 */
-    uint8_t     raw_sectors[4];                 /* 212 - 4 bytes */
-    uint8_t     pre_eol_info;                   /* 267 */
-    uint8_t     device_life_time_est_typ_a;     /* 268 */
-    uint8_t     device_life_time_est_typ_b;     /* 269 */
-    uint32_t    feature_support;
-} mmc_ext_csd_t;
-
-/* Structure for storing the SD SCR (adapted from Linux headers) */
-typedef struct  {
-    uint8_t     sda_vsn;
-    uint8_t     sda_spec3;
-    uint8_t     bus_widths;
-    uint8_t     cmds;
-} sd_scr_t;
-
-/* Structure for storing the SD SSR (adapted from Linux headers) */
-typedef struct  {
-    uint8_t     dat_bus_width;
-    uint8_t     secured_mode;
-    uint16_t    sd_card_type;
-    uint8_t     speed_class;
-    uint8_t     uhs_speed_grade;
-    uint8_t     uhs_au_size;
-    uint8_t     video_speed_class;
-    uint8_t     app_perf_class;
-} sd_ssr_t;
-
-/* Structure describing a SDMMC device's context. */
-typedef struct {
-    /* Underlying driver context. */
-    sdmmc_t *sdmmc;
-    
-    bool is_180v;
-    bool is_block_sdhc;
-    uint32_t rca;
-    mmc_cid_t cid;
-    mmc_csd_t csd;
-    mmc_ext_csd_t ext_csd;
-    sd_scr_t scr;
-    sd_ssr_t ssr;
-} sdmmc_device_t;
-
-int sdmmc_device_sd_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
-int sdmmc_device_mmc_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
-int sdmmc_device_read(sdmmc_device_t *device, uint32_t sector, uint32_t num_sectors, void *data);
-int sdmmc_device_write(sdmmc_device_t *device, uint32_t sector, uint32_t num_sectors, void *data);
-int sdmmc_device_finish(sdmmc_device_t *device);
-int sdmmc_mmc_select_partition(sdmmc_device_t *device, SdmmcPartitionNum partition);
-
-#endif

fusee/common/sdmmc/sdmmc_core.h

@@ -1,312 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_SDMMC_CORE_H
-#define FUSEE_SDMMC_CORE_H
-
-#include "sdmmc_tegra.h"
-
-/* Bounce buffer */
-#define SDMMC_BOUNCE_BUFFER_ADDRESS     0x90000000
-
-/* Present state */
-#define SDHCI_CMD_INHIBIT       0x00000001
-#define SDHCI_DATA_INHIBIT      0x00000002
-#define SDHCI_DOING_WRITE       0x00000100
-#define SDHCI_DOING_READ        0x00000200
-#define SDHCI_SPACE_AVAILABLE   0x00000400
-#define SDHCI_DATA_AVAILABLE    0x00000800
-#define SDHCI_CARD_PRESENT      0x00010000
-#define SDHCI_WRITE_PROTECT     0x00080000
-#define SDHCI_DATA_LVL_MASK     0x00F00000
-#define SDHCI_DATA_LVL_SHIFT    20
-#define SDHCI_DATA_0_LVL_MASK   0x00100000
-#define SDHCI_CMD_LVL           0x01000000
-
-/* SDHCI clock control */
-#define SDHCI_DIVIDER_SHIFT     8
-#define SDHCI_DIVIDER_HI_SHIFT  6
-#define SDHCI_DIV_MASK          0xFF
-#define SDHCI_DIV_MASK_LEN      8
-#define SDHCI_DIV_HI_MASK       0x300
-#define SDHCI_PROG_CLOCK_MODE   0x0020
-#define SDHCI_CLOCK_CARD_EN     0x0004
-#define SDHCI_CLOCK_INT_STABLE  0x0002
-#define SDHCI_CLOCK_INT_EN      0x0001
-
-/* SDHCI host control */
-#define SDHCI_CTRL_LED          0x01
-#define SDHCI_CTRL_4BITBUS      0x02
-#define SDHCI_CTRL_HISPD        0x04
-#define SDHCI_CTRL_DMA_MASK     0x18
-#define SDHCI_CTRL_SDMA         0x00
-#define SDHCI_CTRL_ADMA1        0x08
-#define SDHCI_CTRL_ADMA32       0x10
-#define SDHCI_CTRL_ADMA64       0x18
-#define SDHCI_CTRL_8BITBUS      0x20
-#define SDHCI_CTRL_CDTEST_INS   0x40
-#define SDHCI_CTRL_CDTEST_EN    0x80
-
-/* SDHCI host control 2 */
-#define SDHCI_CTRL_UHS_MASK             0x0007
-#define SDHCI_CTRL_UHS_SDR12            0x0000
-#define SDHCI_CTRL_UHS_SDR25            0x0001
-#define SDHCI_CTRL_UHS_SDR50            0x0002
-#define SDHCI_CTRL_UHS_SDR104           0x0003
-#define SDHCI_CTRL_UHS_DDR50            0x0004
-#define SDHCI_CTRL_HS400                0x0005
-#define SDHCI_CTRL_VDD_180              0x0008
-#define SDHCI_CTRL_DRV_TYPE_MASK        0x0030
-#define SDHCI_CTRL_DRV_TYPE_B           0x0000
-#define SDHCI_CTRL_DRV_TYPE_A           0x0010
-#define SDHCI_CTRL_DRV_TYPE_C           0x0020
-#define SDHCI_CTRL_DRV_TYPE_D           0x0030
-#define SDHCI_CTRL_EXEC_TUNING          0x0040
-#define SDHCI_CTRL_TUNED_CLK            0x0080
-#define SDHCI_UHS2_IF_EN                0x0100
-#define SDHCI_HOST_VERSION_4_EN         0x1000
-#define SDHCI_ADDRESSING_64BIT_EN       0x2000
-#define SDHCI_ASYNC_INTR_EN             0x4000
-#define SDHCI_CTRL_PRESET_VAL_ENABLE    0x8000
-
-/* SDHCI capabilities */
-#define SDHCI_CAN_DO_8BIT   0x00040000
-#define SDHCI_CAN_DO_ADMA2  0x00080000
-#define SDHCI_CAN_DO_ADMA1  0x00100000
-#define SDHCI_CAN_DO_HISPD  0x00200000
-#define SDHCI_CAN_DO_SDMA   0x00400000
-#define SDHCI_CAN_VDD_330   0x01000000
-#define SDHCI_CAN_VDD_300   0x02000000
-#define SDHCI_CAN_VDD_180   0x04000000
-#define SDHCI_CAN_64BIT     0x10000000
-#define SDHCI_ASYNC_INTR    0x20000000
-
-/* Vendor clock control */
-#define SDMMC_CLOCK_TAP_MASK                    (0xFF << 16)
-#define SDMMC_CLOCK_TAP_SDMMC1                  (0x04 << 16)
-#define SDMMC_CLOCK_TAP_SDMMC2                  (0x00 << 16)
-#define SDMMC_CLOCK_TAP_SDMMC3                  (0x03 << 16)
-#define SDMMC_CLOCK_TAP_SDMMC4                  (0x00 << 16)
-#define SDMMC_CLOCK_TRIM_MASK                   (0xFF << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC1_ERISTA          (0x02 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC1_MARIKO          (0x0E << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC2_ERISTA          (0x08 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC2_MARIKO          (0x0D << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC3                 (0x03 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC4_ERISTA          (0x08 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC4_MARIKO          (0x0D << 24)
-#define SDMMC_CLOCK_SPI_MODE_CLKEN_OVERRIDE     (1 << 2)
-#define SDMMC_CLOCK_PADPIPE_CLKEN_OVERRIDE      (1 << 3)
-
-/* Autocal configuration */
-#define SDMMC_AUTOCAL_PDPU_CONFIG_MASK          0x7F7F
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_ERISTA    0x7B7B
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_MARIKO    0x0606
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_ERISTA    0x7D00
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_MARIKO    0x0000
-#define SDMMC_AUTOCAL_PDPU_SDMMC4_1V8           0x0505
-#define SDMMC_AUTOCAL_START                     (1 << 31)
-#define SDMMC_AUTOCAL_ENABLE                    (1 << 29)
-
-/* Autocal status */
-#define SDMMC_AUTOCAL_ACTIVE                    (1 << 31)
-
-/* Vendor tuning control 0*/
-#define SDMMC_VENDOR_TUNING_TRIES_MASK          (0x7 << 13)
-#define SDMMC_VENDOR_TUNING_TRIES_SHIFT          13
-#define SDMMC_VENDOR_TUNING_MULTIPLIER_MASK     (0x7F << 6)
-#define SDMMC_VENDOR_TUNING_MULTIPLIER_UNITY    (1 << 6)
-#define SDMMC_VENDOR_TUNING_DIVIDER_MASK        (0x7 << 3)
-#define SDMMC_VENDOR_TUNING_SET_BY_HW           (1 << 17)
-
-/* Vendor tuning control 1*/
-#define SDMMC_VENDOR_TUNING_STEP_SIZE_SDR50_DEFAULT     (0 << 0)
-#define SDMMC_VENDOR_TUNING_STEP_SIZE_SDR104_DEFAULT    (0 << 4)
-
-/* Vendor capability overrides */
-#define SDMMC_VENDOR_CAPABILITY_DQS_TRIM_MASK           (0x3F << 8)
-#define SDMMC_VENDOR_CAPABILITY_DQS_TRIM_HS400          (0x11 << 8)
-
-/* Timeouts */
-#define SDMMC_AUTOCAL_TIMEOUT                           (10 * 1000)
-#define SDMMC_TUNING_TIMEOUT                            (150 * 1000)
-
-/* Command response flags */
-#define SDMMC_RSP_PRESENT                               (1 << 0)
-#define SDMMC_RSP_136                                   (1 << 1)
-#define SDMMC_RSP_CRC                                   (1 << 2)
-#define SDMMC_RSP_BUSY                                  (1 << 3)
-#define SDMMC_RSP_OPCODE                                (1 << 4)
-
-/* Command types */
-#define SDMMC_CMD_MASK                                  (3 << 5)
-#define SDMMC_CMD_AC                                    (0 << 5)
-#define SDMMC_CMD_ADTC                                  (1 << 5)
-#define SDMMC_CMD_BC                                    (2 << 5)
-#define SDMMC_CMD_BCR                                   (3 << 5)
-
-/* SPI command response flags */
-#define SDMMC_RSP_SPI_S1                                (1 << 7)
-#define SDMMC_RSP_SPI_S2                                (1 << 8)
-#define SDMMC_RSP_SPI_B4                                (1 << 9)
-#define SDMMC_RSP_SPI_BUSY                              (1 << 10)
-
-/* Native response types for commands */
-#define SDMMC_RSP_NONE          (0)
-#define SDMMC_RSP_R1            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R1B           (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE|SDMMC_RSP_BUSY)
-#define SDMMC_RSP_R2            (SDMMC_RSP_PRESENT|SDMMC_RSP_136|SDMMC_RSP_CRC)
-#define SDMMC_RSP_R3            (SDMMC_RSP_PRESENT)
-#define SDMMC_RSP_R4            (SDMMC_RSP_PRESENT)
-#define SDMMC_RSP_R5            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R6            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R7            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R1_NO_CRC     (SDMMC_RSP_PRESENT|SDMMC_RSP_OPCODE)
-
-/* SPI response types for commands */
-#define SDMMC_RSP_SPI_R1        (SDMMC_RSP_SPI_S1)
-#define SDMMC_RSP_SPI_R1B       (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_BUSY)
-#define SDMMC_RSP_SPI_R2        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_S2)
-#define SDMMC_RSP_SPI_R3        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
-#define SDMMC_RSP_SPI_R4        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
-#define SDMMC_RSP_SPI_R5        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_S2)
-#define SDMMC_RSP_SPI_R7        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
-
-/* SDMMC controllers */
-typedef enum {
-    SDMMC_1 = 0,
-    SDMMC_2 = 1,
-    SDMMC_3 = 2,
-    SDMMC_4 = 3
-} SdmmcControllerNum;
-
-typedef enum {
-    SDMMC_PARTITION_INVALID = -1,
-    SDMMC_PARTITION_USER    = 0,
-    SDMMC_PARTITION_BOOT0   = 1,
-    SDMMC_PARTITION_BOOT1   = 2,
-    SDMMC_PARTITION_RPMB    = 3
-} SdmmcPartitionNum;
-
-typedef enum {
-    SDMMC_VOLTAGE_NONE  = 0,
-    SDMMC_VOLTAGE_1V8   = 1,
-    SDMMC_VOLTAGE_3V3   = 2
-} SdmmcBusVoltage;
-
-typedef enum {
-    SDMMC_BUS_WIDTH_1BIT  = 0,
-    SDMMC_BUS_WIDTH_4BIT  = 1,
-    SDMMC_BUS_WIDTH_8BIT  = 2
-} SdmmcBusWidth;
-
-typedef enum {
-    SDMMC_SPEED_MMC_IDENT       = 0,
-    SDMMC_SPEED_MMC_LEGACY      = 1,
-    SDMMC_SPEED_MMC_HS          = 2,
-    SDMMC_SPEED_MMC_HS200       = 3,
-    SDMMC_SPEED_MMC_HS400       = 4,
-    SDMMC_SPEED_SD_IDENT        = 5,
-    SDMMC_SPEED_SD_DS           = 6,
-    SDMMC_SPEED_SD_HS           = 7,
-    SDMMC_SPEED_SD_SDR12        = 8,
-    SDMMC_SPEED_SD_SDR25        = 9,
-    SDMMC_SPEED_SD_SDR50        = 10,
-    SDMMC_SPEED_SD_SDR104       = 11,
-    SDMMC_SPEED_SD_DDR50        = 12,
-    SDMMC_SPEED_GC_ASIC_FPGA    = 13,
-    SDMMC_SPEED_GC_ASIC         = 14,
-    SDMMC_SPEED_EMU_SDR104      = 255, /* Custom speed mode. Prevents low voltage switch in MMC emulation. */
-} SdmmcBusSpeed;
-
-typedef enum {
-    SDMMC_CAR_DIVIDER_MMC_LEGACY        = 30, /* (16 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_MMC_HS            = 14, /* (8 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_MMC_HS200         = 3,  /* (2.5 * 2) - 2 (for PLLP_OUT0, same as HS400) */
-    SDMMC_CAR_DIVIDER_SD_SDR12          = 31, /* (16.5 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_SD_SDR25          = 15, /* (8.5 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_SD_SDR50          = 7,  /* (4.5 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_SD_SDR104         = 2,  /* (2 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_GC_ASIC_FPGA      = 18, /* (5 * 2 * 2) - 2 */
-} SdmmcCarDivider;
-
-/* Structure for describing a SDMMC device. */
-typedef struct {
-    /* Controller number */
-    SdmmcControllerNum controller;
-    
-    /* Backing register space */
-    volatile tegra_sdmmc_t *regs;
-    
-    /* Controller properties */
-    const char *name;
-    bool has_sd;
-    bool is_clk_running;
-    bool is_sd_clk_enabled;
-    bool is_tuning_tap_val_set;
-    bool use_adma;
-    uint32_t tap_val;
-    uint32_t internal_divider;
-    uint32_t resp[4];
-    uint32_t resp_auto_cmd12;
-    uint32_t next_dma_addr;
-    uint8_t* dma_bounce_buf;
-    SdmmcBusVoltage bus_voltage;
-    SdmmcBusWidth bus_width;
-    
-    /* Per-controller operations. */
-    int (*sdmmc_config)();
-} sdmmc_t;
-
-/* Structure for describing a SDMMC command. */
-typedef struct {
-    uint32_t    opcode;
-    uint32_t    arg;
-    uint32_t    resp[4];
-    uint32_t    flags;      /* Expected response type. */
-} sdmmc_command_t;
-
-/* Structure for describing a SDMMC request. */
-typedef struct {
-    void*       data;
-    uint32_t    blksz;
-    uint32_t    num_blocks;
-    bool        is_multi_block;
-    bool        is_read;
-    bool        is_auto_cmd12;
-} sdmmc_request_t;
-
-int sdmmc_init(sdmmc_t *sdmmc, SdmmcControllerNum controller, SdmmcBusVoltage bus_voltage, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
-void sdmmc_finish(sdmmc_t *sdmmc);
-int sdmmc_select_speed(sdmmc_t *sdmmc, SdmmcBusSpeed bus_speed);
-void sdmmc_select_bus_width(sdmmc_t *sdmmc, SdmmcBusWidth width);
-void sdmmc_select_voltage(sdmmc_t *sdmmc, SdmmcBusVoltage voltage);
-void sdmmc_adjust_sd_clock(sdmmc_t *sdmmc);
-int sdmmc_switch_voltage(sdmmc_t *sdmmc);
-void sdmmc_set_tuning_tap_val(sdmmc_t *sdmmc);
-int sdmmc_execute_tuning(sdmmc_t *sdmmc, SdmmcBusSpeed bus_speed, uint32_t opcode);
-int sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_command_t *cmd, sdmmc_request_t *req, uint32_t *num_blocks_out);
-int sdmmc_load_response(sdmmc_t *sdmmc, uint32_t flags, uint32_t *resp);
-int sdmmc_abort(sdmmc_t *sdmmc, uint32_t opcode);
-void sdmmc_error(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_warn(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_info(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_debug(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_dump_regs(sdmmc_t *sdmmc);
-
-#endif

fusee/common/sdmmc/sdmmc_tegra.h

@@ -1,172 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_SDMMC_TEGRA_H
-#define FUSEE_SDMMC_TEGRA_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#define TEGRA_MMC_PWRCTL_SD_BUS_POWER                           (1 << 0)
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8                    (5 << 1)
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0                    (6 << 1)
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3                    (7 << 1)
-
-#define TEGRA_MMC_HOSTCTL_DMASEL_MASK                           (3 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                           (0 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                    (2 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT                    (3 << 3)
-
-#define TEGRA_MMC_TRNMOD_DMA_ENABLE                             (1 << 0)
-#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE                     (1 << 1)
-#define TEGRA_MMC_TRNMOD_AUTO_CMD12                             (1 << 2)
-#define TEGRA_MMC_TRNMOD_AUTO_CMD23                             (1 << 3)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE                (0 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ                 (1 << 4)
-#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT                     (1 << 5)
-
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK                  (3 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE           (0 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136            (1 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48             (2 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY        (3 << 0)
-
-#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK                          (1 << 3)
-#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK                        (1 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER      (1 << 5)
-
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD                        (1 << 0)
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT                        (1 << 1)
-
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE                  (1 << 0)
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE                  (1 << 1)
-#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE                        (1 << 2)
-#define TEGRA_MMC_CLKCON_PROG_CLOCK_MODE                        (1 << 5)
-
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT                   8
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK                    (0xff << 8)
-
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL                        (1 << 0)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE                   (1 << 1)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE                   (1 << 2)
-
-#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE                        (1 << 0)
-#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE                       (1 << 1)
-#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT                       (1 << 3)
-#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT                       (1 << 15)
-#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT                         (1 << 16)
-
-#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE                      (1 << 0)
-#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE                     (1 << 1)
-#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT                     (1 << 3)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY                (1 << 4)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY                 (1 << 5)
-
-#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                     (1 << 1)
-
-typedef struct {
-    /* SDHCI standard registers */
-    uint32_t dma_address;
-    uint16_t block_size;
-    uint16_t block_count;
-    uint32_t argument;
-    uint16_t transfer_mode;
-    uint16_t command;
-    uint32_t response[0x4];
-    uint32_t buffer;
-    uint32_t present_state;
-    uint8_t host_control;
-    uint8_t power_control;
-    uint8_t block_gap_control;
-    uint8_t wake_up_control;
-    uint16_t clock_control;
-    uint8_t timeout_control;
-    uint8_t software_reset;
-    uint32_t int_status;
-    uint32_t int_enable;
-    uint32_t signal_enable;
-    uint16_t acmd12_err;
-    uint16_t host_control2;
-    uint32_t capabilities;
-    uint32_t capabilities_1;
-    uint32_t max_current;
-    uint32_t _0x4c;
-    uint16_t set_acmd12_error;
-    uint16_t set_int_error;
-    uint8_t adma_error;
-    uint8_t _0x56[0x3];
-    uint32_t adma_address;
-    uint32_t upper_adma_address;
-    uint16_t preset_for_init;
-    uint16_t preset_for_default;
-    uint16_t preset_for_high;
-    uint16_t preset_for_sdr12;
-    uint16_t preset_for_sdr25;
-    uint16_t preset_for_sdr50;
-    uint16_t preset_for_sdr104;
-    uint16_t preset_for_ddr50;
-    uint32_t _0x70[0x23];
-    uint16_t slot_int_status;
-    uint16_t host_version;
-
-    /* Vendor specific registers */
-    uint32_t vendor_clock_cntrl;
-    uint32_t vendor_sys_sw_cntrl;
-    uint32_t vendor_err_intr_status;
-    uint32_t vendor_cap_overrides;
-    uint32_t vendor_boot_cntrl;
-    uint32_t vendor_boot_ack_timeout;
-    uint32_t vendor_boot_dat_timeout;
-    uint32_t vendor_debounce_count;
-    uint32_t vendor_misc_cntrl;
-    uint32_t max_current_override;
-    uint32_t max_current_override_hi;
-    uint32_t _0x12c[0x20];
-    uint32_t vendor_io_trim_cntrl;
-
-    /* Start of sdmmc2/sdmmc4 only */
-    uint32_t vendor_dllcal_cfg;
-    uint32_t vendor_dll_ctrl0;
-    uint32_t vendor_dll_ctrl1;
-    uint32_t vendor_dllcal_cfg_sta;
-    /* End of sdmmc2/sdmmc4 only */
-
-    uint32_t vendor_tuning_cntrl0;
-    uint32_t vendor_tuning_cntrl1;
-    uint32_t vendor_tuning_status0;
-    uint32_t vendor_tuning_status1;
-    uint32_t vendor_clk_gate_hysteresis_count;
-    uint32_t vendor_preset_val0;
-    uint32_t vendor_preset_val1;
-    uint32_t vendor_preset_val2;
-    uint32_t sdmemcomppadctrl;
-    uint32_t auto_cal_config;
-    uint32_t auto_cal_interval;
-    uint32_t auto_cal_status;
-    uint32_t io_spare;
-    uint32_t sdmmca_mccif_fifoctrl;
-    uint32_t timeout_wcoal_sdmmca;
-    uint32_t _0x1fc;
-} tegra_sdmmc_t;
-
-static inline volatile tegra_sdmmc_t *sdmmc_get_regs(uint32_t idx)
-{
-    return (volatile tegra_sdmmc_t *)(0x700B0000 + (idx * 0x200));
-}
-
-#endif

fusee/common/vsprintf.h

@@ -1,28 +0,0 @@
-/*
- *  Copyright (C) 2011 Andrei Warkentin <andrey.warkentin@gmail.com>
- *
- * This program is free software ; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <stdarg.h>
-#include <stdlib.h>
-
-#ifndef VSPRINTF_H
-#define VSPRINTF_H
-
-struct va_format {
-        const char *fmt;
-        va_list *va;
-};
-
-unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base);
-
-int sprintf(char *buf, const char *fmt, ...);
-int scnprintf(char *buf, size_t size, const char *fmt, ...);
-int snprintf(char *buf, size_t size, const char *fmt, ...);
-int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
-int sscanf(const char *buf, const char *fmt, ...);
-
-#endif /* VSPRINTF_H */

fusee/fusee-primary/Makefile

@@ -1,192 +0,0 @@
-#---------------------------------------------------------------------------------
-.SUFFIXES:
-#---------------------------------------------------------------------------------
-
-ifeq ($(strip $(DEVKITARM)),)
-$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
-endif
-
-TOPDIR ?= $(CURDIR)
-
-AMS		:= $(TOPDIR)/../../../
-include $(DEVKITARM)/base_rules
-
-AMSBRANCH := $(shell git symbolic-ref --short HEAD)
-AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
-
-ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
-    AMSREV := $(AMSREV)-dirty
-endif
-
-define _bin2o
-	bin2s $< | $(AS) -o $(@)
-	echo "extern const u8" `(echo $(<F) | sed -e 's/^\([0-9]\)/_\1/' | tr . _ | tr - _)`"_end[];" > `(echo $(<F) | tr . _ | tr - _)`.h
-	echo "extern const u8" `(echo $(<F) | sed -e 's/^\([0-9]\)/_\1/' | tr . _ | tr - _)`"[];" >> `(echo $(<F) | tr . _ | tr - _)`.h
-	echo "extern const u32" `(echo $(<F) | sed -e 's/^\([0-9]\)/_\1/' | tr . _ | tr - _)`_size";" >> `(echo $(<F) | tr . _ | tr - _)`.h
-endef
-
-#---------------------------------------------------------------------------------
-# TARGET is the name of the output
-# BUILD is the directory where object files & intermediate files will be placed
-# SOURCES is a list of directories containing source code
-# DATA is a list of directories containing data files
-# INCLUDES is a list of directories containing header files
-#---------------------------------------------------------------------------------
-TARGET		:=	$(notdir $(CURDIR))
-BUILD		:=	build
-SOURCES		:=	src
-DATA		:=	data
-INCLUDES	:=	include  ../../../libraries/libvapours/include
-
-#---------------------------------------------------------------------------------
-# options for code generation
-#---------------------------------------------------------------------------------
-ARCH	:=	-march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-DEFINES :=	-D__BPMP__ -DFUSEE_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
-
-CFLAGS	:= \
-	-g \
-	-gdwarf-4 \
-	-O2 \
-	-fomit-frame-pointer \
-	-ffunction-sections \
-	-fdata-sections \
-	-std=gnu11 \
-	-Werror \
-	-Wall \
-	-Wno-array-bounds \
-	-Wno-stringop-overflow \
-	-Wno-stringop-overread \
-	-fstrict-volatile-bitfields \
-	$(ARCH) $(DEFINES)
-
-CFLAGS	+=	$(INCLUDE)
-
-CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
-
-ASFLAGS	:=	-g -gdwarf-4 $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map)
-
-LIBS	:=
-
-#---------------------------------------------------------------------------------
-# list of directories containing libraries, this must be the top level containing
-# include and lib
-#---------------------------------------------------------------------------------
-LIBDIRS	:=
-
-
-#---------------------------------------------------------------------------------
-# no real need to edit anything past this point unless you need to add additional
-# rules for different file extensions
-#---------------------------------------------------------------------------------
-ifneq ($(BUILD),$(notdir $(CURDIR)))
-#---------------------------------------------------------------------------------
-
-export OUTPUT	:=	$(CURDIR)/$(TARGET)
-export TOPDIR	:=	$(CURDIR)
-
-export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
-			$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
-			$(CURDIR)/fusee-primary-main
-
-export DEPSDIR	:=	$(CURDIR)/$(BUILD)
-
-CFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
-CPPFILES	:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
-SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
-BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) fusee-primary-main.lz4
-
-#---------------------------------------------------------------------------------
-# use CXX for linking C++ projects, CC for standard C
-#---------------------------------------------------------------------------------
-ifeq ($(strip $(CPPFILES)),)
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CC)
-#---------------------------------------------------------------------------------
-else
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CXX)
-#---------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------
-
-export OFILES_BIN	:=	$(addsuffix .o,$(subst -,_,$(BINFILES)))
-export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
-export OFILES 		:=	$(OFILES_BIN) $(OFILES_SRC)
-export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(subst -,_,$(BINFILES))))
-
-export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
-			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-			-I$(CURDIR)/$(BUILD)
-
-export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
-
-.PHONY: $(BUILD) clean all check_main
-
-#---------------------------------------------------------------------------------
-all: $(BUILD)
-
-fusee-primary-main/fusee-primary-main.lz4: check_main
-
-check_main:
-	@$(MAKE) -C fusee-primary-main all
-
-$(BUILD): fusee-primary-main/fusee-primary-main.lz4
-	@[ -d $@ ] || mkdir -p $@
-	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
-
-#---------------------------------------------------------------------------------
-clean:
-	@echo clean ...
-	@$(MAKE) -C fusee-primary-main clean
-	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
-
-
-#---------------------------------------------------------------------------------
-else
-.PHONY:	all
-
-DEPENDS	:=	$(OFILES:.o=.d)
-
-#---------------------------------------------------------------------------------
-# main targets
-#---------------------------------------------------------------------------------
-all	:	$(OUTPUT).bin
-
-$(OUTPUT).bin	:	$(OUTPUT).elf
-	$(OBJCOPY) -S -O binary $< $@
-	@echo built ... $(notdir $@)
-
-$(OUTPUT).elf	:	$(OFILES)
-
-%.elf: $(OFILES)
-	@echo linking $(notdir $@)
-	@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
-	@$(NM) -CSn $@ > $(notdir $*.lst)
-
-utils.o: CFLAGS += -fno-builtin
-
-$(OFILES_SRC)	: $(HFILES_BIN)
-
-#---------------------------------------------------------------------------------
-# you need a rule like this for each extension you use as binary data
-#---------------------------------------------------------------------------------
-%.bin.o	%_bin.h:	%.bin
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(bin2o)
-
-#---------------------------------------------------------------------------------
-# you need a rule like this for each extension you use as binary data
-#---------------------------------------------------------------------------------
-fusee_primary_main.lz4.o	fusee_primary_main_lz4.h:	fusee-primary-main.lz4
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(_bin2o)
-
--include $(DEPENDS)
-
-#---------------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------------

fusee/fusee-primary/fusee-primary-main/Makefile

@@ -1,177 +0,0 @@
-#---------------------------------------------------------------------------------
-.SUFFIXES:
-#---------------------------------------------------------------------------------
-
-ifeq ($(strip $(DEVKITARM)),)
-$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
-endif
-
-TOPDIR ?= $(CURDIR)
-
-AMS		?= $(TOPDIR)/../../../
-include $(DEVKITARM)/base_rules
-
-AMSBRANCH := $(shell git symbolic-ref --short HEAD)
-AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
-
-ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
-    AMSREV := $(AMSREV)-dirty
-endif
-
-#---------------------------------------------------------------------------------
-# TARGET is the name of the output
-# BUILD is the directory where object files & intermediate files will be placed
-# SOURCES is a list of directories containing source code
-# DATA is a list of directories containing data files
-# INCLUDES is a list of directories containing header files
-#---------------------------------------------------------------------------------
-TARGET		:=	$(notdir $(CURDIR))
-BUILD		:=	build
-SOURCES		:=	src ../../../fusee/common ../../../fusee/common/display ../../../fusee/common/fatfs ../../../fusee/common/sdmmc
-DATA		:=	data
-INCLUDES	:=	include  ../../../libraries/libvapours/include
-
-#---------------------------------------------------------------------------------
-# options for code generation
-#---------------------------------------------------------------------------------
-ARCH	:=	-march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-DEFINES :=	-D__BPMP__ -DFUSEE_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
-
-CFLAGS	:= \
-	-g \
-	-gdwarf-4 \
-	-O2 \
-	-fomit-frame-pointer \
-	-ffunction-sections \
-	-fdata-sections \
-	-std=gnu11 \
-	-Werror \
-	-Wall \
-	-Wno-array-bounds \
-	-Wno-stringop-overflow \
-	-Wno-stringop-overread \
-	-fstrict-volatile-bitfields \
-	$(ARCH) $(DEFINES)
-
-CFLAGS	+=	$(INCLUDE)
-
-CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
-
-ASFLAGS	:=	-g -gdwarf-4 $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map)
-
-LIBS	:=
-
-#---------------------------------------------------------------------------------
-# list of directories containing libraries, this must be the top level containing
-# include and lib
-#---------------------------------------------------------------------------------
-LIBDIRS	:=
-
-
-#---------------------------------------------------------------------------------
-# no real need to edit anything past this point unless you need to add additional
-# rules for different file extensions
-#---------------------------------------------------------------------------------
-ifneq ($(BUILD),$(notdir $(CURDIR)))
-#---------------------------------------------------------------------------------
-
-export OUTPUT	:=	$(CURDIR)/$(TARGET)
-export TOPDIR	:=	$(CURDIR)
-
-export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
-			$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
-			$(AMS)/exosphere/program/rebootstub
-
-export DEPSDIR	:=	$(CURDIR)/$(BUILD)
-
-CFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
-CPPFILES	:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
-SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
-BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) rebootstub.bin
-
-#---------------------------------------------------------------------------------
-# use CXX for linking C++ projects, CC for standard C
-#---------------------------------------------------------------------------------
-ifeq ($(strip $(CPPFILES)),)
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CC)
-#---------------------------------------------------------------------------------
-else
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CXX)
-#---------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------
-
-export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
-export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
-export OFILES 		:=	$(OFILES_BIN) $(OFILES_SRC)
-export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(BINFILES)))
-
-export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
-			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-			-I$(CURDIR)/$(BUILD)
-
-export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
-
-.PHONY: $(BUILD) clean all check_rebootstub
-
-#---------------------------------------------------------------------------------
-all: check_rebootstub $(BUILD)
-
-check_rebootstub:
-	@$(MAKE) -C $(AMS)/exosphere/program/rebootstub all
-
-$(BUILD): check_rebootstub
-	@[ -d $@ ] || mkdir -p $@
-	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
-
-#---------------------------------------------------------------------------------
-clean:
-	@echo clean ...
-	@$(MAKE) -C $(AMS)/exosphere/program/rebootstub clean
-	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
-
-
-#---------------------------------------------------------------------------------
-else
-.PHONY:	all
-
-DEPENDS	:=	$(OFILES:.o=.d)
-
-#---------------------------------------------------------------------------------
-# main targets
-#---------------------------------------------------------------------------------
-all	:	$(OUTPUT).lz4
-
-$(OUTPUT).lz4	:	$(OUTPUT).bin
-	@python ../lz4_compress.py $(OUTPUT).bin $(OUTPUT).lz4
-	@echo built ... $(notdir $@)
-
-$(OUTPUT).bin	:	$(OUTPUT).elf
-	$(OBJCOPY) -S -O binary $< $@
-	@echo built ... $(notdir $@)
-
-$(OUTPUT).elf	:	$(OFILES)
-
-%.elf: $(OFILES)
-	@echo linking $(notdir $@)
-	@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
-	@$(NM) -CSn $@ > $(notdir $*.lst)
-
-$(OFILES_SRC)	: $(HFILES_BIN)
-
-#---------------------------------------------------------------------------------
-# you need a rule like this for each extension you use as binary data
-#---------------------------------------------------------------------------------
-%.bin.o	%_bin.h:	%.bin
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(bin2o)
-
--include $(DEPENDS)
-
-#---------------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------------

fusee/fusee-primary/fusee-primary-main/linker.ld

@@ -1,198 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-
-PHDRS
-{
-    crt0        PT_LOAD;
-    chainloader PT_LOAD;
-    main        PT_LOAD;
-}
-
-/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */
-MEMORY
-{
-    NULL        : ORIGIN = 0x00000000, LENGTH = 0x1000
-    main        : ORIGIN = 0x40008000, LENGTH = 0x38000
-    low_iram    : ORIGIN = 0x40000000, LENGTH = 0x6000
-}
-
-SECTIONS
-{
-    PROVIDE(__start__           = 0x40008000);
-    PROVIDE(__stack_top__       = 0x40008000);
-    PROVIDE(__stack_bottom__    = 0x40006000);
-    PROVIDE(__heap_start__      = 0);
-    PROVIDE(__heap_end__        = 0);
-
-    . = __start__;
-
-    .crt0 :
-    {
-        KEEP( *(.text.start) )
-        KEEP( *(.init) )
-        . = ALIGN(32);
-        PROVIDE (__reboot_start__ = ABSOLUTE(.));
-        KEEP( *(.reboot*) )
-        . = ALIGN(4);
-        PROVIDE (__reboot_end__   = ABSOLUTE(.));
-        . = ALIGN(32);
-    } >main :crt0
-
-    .chainloader_loadable :
-    {
-        . = ALIGN(32);
-        PROVIDE (__chainloader_start__  = ABSOLUTE(.));
-        PROVIDE (__chainloader_lma__    = LOADADDR(.chainloader_loadable));
-        KEEP(*(.chainloader.text.start))
-        chainloader.o(.text*)
-        chainloader.o(.rodata*)
-        chainloader.o(.data*)
-        . = ALIGN(32);
-    } >low_iram AT>main :chainloader
-
-    .chainloader_bss (NOLOAD) :
-    {
-        . = ALIGN(32);
-        PROVIDE (__chainloader_bss_start__ = ABSOLUTE(.));
-        chainloader.o(.bss* COMMON)
-        . = ALIGN(32);
-        PROVIDE (__chainloader_end__ = ABSOLUTE(.));
-    } >low_iram :NONE
-
-    .text :
-    {
-        . = ALIGN(32);
-        /* .text */
-        *(.text.reboot_to_self)
-        *(.text)
-        *(.text.*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.stub)
-        *(.gnu.warning)
-        *(.gnu.linkonce.t*)
-
-        /* .fini */
-        KEEP( *(.fini) )
-        . = ALIGN(8);
-    } >main :main
-
-    .rodata :
-    {
-        *(.rodata)
-        *(.roda)
-        *(.rodata.*)
-        *all.rodata*(*)
-        *(.gnu.linkonce.r*)
-        SORT(CONSTRUCTORS)
-        . = ALIGN(8);
-    } >main
-
-    .preinit_array :
-    {
-        PROVIDE (__preinit_array_start = .);
-        KEEP (*(.preinit_array))
-        PROVIDE (__preinit_array_end = .);
-    } >main
-
-    .init_array ALIGN(4) :
-    {
-        PROVIDE (__init_array_start = .);
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        PROVIDE (__init_array_end = .);
-    } >main
-
-    .fini_array ALIGN(4) :
-    {
-        PROVIDE (__fini_array_start = .);
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        PROVIDE (__fini_array_end = .);
-    } >main
-
-    .ctors ALIGN(4) :
-    {
-        KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*(.ctors))
-        . = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-    } >main
-
-    .dtors ALIGN(4) :
-    {
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*(.dtors))
-        . = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-    } >main
-
-    .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main
-    ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*)  __exidx_end = ABSOLUTE(.);} >main
-
-    .data :
-    {
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d*)
-        CONSTRUCTORS
-        . = ALIGN(32);
-    } >main
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(32);
-        PROVIDE (__bss_start__ = ABSOLUTE(.));
-        *(.dynbss)
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b*)
-        *(COMMON)
-        . = ALIGN(32);
-        PROVIDE (__bss_end__ = ABSOLUTE(.));
-    } >main :NONE
-    __end__ = ABSOLUTE(.) ;
-
-    /* ==================
-       ==== Metadata ====
-       ================== */
-
-    /* Discard sections that difficult post-processing */
-    /DISCARD/ : { *(.group .comment .note) }
-
-    /* Stabs debugging sections. */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-
-    /* DWARF debug sections.
-       Symbols in the DWARF debugging sections are relative to the beginning
-       of the section so we begin them at 0. */
-
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-}

fusee/fusee-primary/fusee-primary-main/linker.specs

@@ -1,7 +0,0 @@
-%rename link                old_link
-
-*link:
-%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections
-
-*startfile:
-crti%O%s crtbegin%O%s

fusee/fusee-primary/fusee-primary-main/lz4_compress.py

@@ -1,23 +0,0 @@
-#!/usr/bin/env python
-import sys, lz4
-from struct import unpack as up
-
-def lz4_compress(data):
-    try:
-        import lz4.block as block
-    except ImportError:
-        block = lz4.LZ4_compress
-    return block.compress(data, 'high_compression', store_size=False)
-
-def main(argc, argv):
-    if argc != 3:
-        print('Usage: %s in out' % argv[0])
-        return 1
-    with open(argv[1], 'rb') as f:
-        data = f.read()
-    with open(argv[2], 'wb') as f:
-        f.write(lz4_compress(data))
-    return 0
-
-if __name__ == '__main__':
-    sys.exit(main(len(sys.argv), sys.argv))

fusee/fusee-primary/fusee-primary-main/src/apb_misc.h

@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_APB_MISC_H
-#define FUSEE_APB_MISC_H
-
-#include <stdint.h>
-
-#define APB_MISC_BASE 0x70000000
-#define APB_PADCTL_BASE 0x70000810
-#define MAKE_APB_MISC_REG(n) MAKE_REG32(APB_MISC_BASE + n)
-#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
-
-#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
-#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0)
-#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
-#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
-
-#define SDMMC1_PAD_CAL_DRVUP_SHIFT              (20)
-#define SDMMC1_PAD_CAL_DRVDN_SHIFT              (12)
-#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT     (28)
-#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT     (30)
-#define SDMMC1_PAD_CAL_DRVUP_MASK               (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
-#define SDMMC1_PAD_CAL_DRVDN_MASK               (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
-#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK      (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
-#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK      (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT)
-
-#define EMMC2_PAD_DRVUP_COMP_SHIFT      (8)
-#define EMMC2_PAD_DRVDN_COMP_SHIFT      (2)
-#define EMMC2_PAD_DRVUP_COMP_MASK       (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT)
-#define EMMC2_PAD_DRVDN_COMP_MASK       (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT)
-
-#define SDMMC2_PAD_CAL_DRVUP_SHIFT      (20)
-#define SDMMC2_PAD_CAL_DRVDN_SHIFT      (12)
-#define SDMMC2_PAD_CAL_DRVUP_MASK       (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT)
-#define SDMMC2_PAD_CAL_DRVDN_MASK       (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT)
-
-#define EMMC4_PAD_DRVUP_COMP_SHIFT      (8)
-#define EMMC4_PAD_DRVDN_COMP_SHIFT      (2)
-#define EMMC4_PAD_DRVUP_COMP_MASK       (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT)
-#define EMMC4_PAD_DRVDN_COMP_MASK       (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT)
-
-#define PADCTL_SDMMC1_DEEP_LOOPBACK     (1 << 0)
-#define PADCTL_SDMMC3_DEEP_LOOPBACK     (1 << 0)
-#define PADCTL_SDMMC2_ENABLE_DATA_IN    (0xFF << 8)
-#define PADCTL_SDMMC2_ENABLE_CLK_IN     (0x3 << 4)
-#define PADCTL_SDMMC2_DEEP_LOOPBACK     (1 << 0)
-#define PADCTL_SDMMC4_ENABLE_DATA_IN    (0xFF << 8)
-#define PADCTL_SDMMC4_ENABLE_CLK_IN     (0x3 << 4)
-#define PADCTL_SDMMC4_DEEP_LOOPBACK     (1 << 0)
-#define PADCTL_SDMMC1_CD_SOURCE         (1 << 0)
-#define PADCTL_SDMMC1_WP_SOURCE         (1 << 1)
-#define PADCTL_SDMMC3_CD_SOURCE         (1 << 2)
-#define PADCTL_SDMMC3_WP_SOURCE         (1 << 3)
-
-typedef struct {
-    uint32_t asdbgreg;                      /* 0x810 */
-    uint32_t _0x814[0x31];
-    uint32_t sdmmc1_clk_lpbk_control;       /* 0x8D4 */
-    uint32_t sdmmc3_clk_lpbk_control;       /* 0x8D8 */
-    uint32_t emmc2_pad_cfg_control;         /* 0x8DC */
-    uint32_t emmc4_pad_cfg_control;         /* 0x8E0 */
-    uint32_t _0x8E4[0x6E];
-    uint32_t sdmmc1_pad_cfgpadctrl;         /* 0xA98 */
-    uint32_t emmc2_pad_cfgpadctrl;          /* 0xA9C */
-    uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
-    uint32_t emmc2_pad_pupd_cfgpadctrl;     /* 0xAA4 */
-    uint32_t _0xAA8[0x03];
-    uint32_t sdmmc3_pad_cfgpadctrl;         /* 0xAB0 */
-    uint32_t emmc4_pad_cfgpadctrl;          /* 0xAB4 */
-    uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
-    uint32_t emmc4_pad_pupd_cfgpadctrl;     /* 0xABC */
-    uint32_t _0xAC0[0x2E];
-    uint32_t vgpio_gpio_mux_sel;            /* 0xB74 */
-    uint32_t qspi_sck_lpbk_control;         /* 0xB78 */
-} tegra_padctl_t;
-
-static inline volatile tegra_padctl_t *padctl_get_regs(void)
-{
-    return (volatile tegra_padctl_t *)APB_PADCTL_BASE;
-}
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/btn.c

@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdint.h>
-
-#include "btn.h"
-#include "i2c.h"
-#include "gpio.h"
-#include "timers.h"
-
-uint32_t btn_read()
-{
-    uint32_t res = 0;
-    
-    if (!gpio_read(GPIO_BUTTON_VOL_DOWN))
-        res |= BTN_VOL_DOWN;
-    
-    if (!gpio_read(GPIO_BUTTON_VOL_UP))
-        res |= BTN_VOL_UP;
-    
-    uint32_t val = 0;
-    if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x15, &val, 1))
-    {
-        if (val & 0x4)
-            res |= BTN_POWER;
-    }
-    
-    return res;
-}
-
-uint32_t btn_wait()
-{
-    uint32_t res = 0, btn = btn_read();
-    int pwr = 0;
-
-    if (btn & BTN_POWER)
-    {
-        pwr = 1;
-        btn &= ~BTN_POWER;
-    }
-
-    do
-    {
-        res = btn_read();
-
-        if (!(res & BTN_POWER) && pwr)
-            pwr = 0;
-        else if (pwr)
-            res &= ~BTN_POWER;
-    } while (btn == res);
-
-    return res;
-}
-
-uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask)
-{
-    uint32_t timeout = get_time_ms() + time_ms;
-    uint32_t res = btn_read() & mask;
-
-    do
-    {
-        if (!(res & mask))
-            res = btn_read() & mask;
-    } while (get_time_ms() < timeout);
-
-    return res;
-}

fusee/fusee-primary/fusee-primary-main/src/btn.h

@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_BTN_H_
-#define FUSEE_BTN_H_
-
-#define BTN_POWER 0x1
-#define BTN_VOL_DOWN 0x2
-#define BTN_VOL_UP 0x4
-
-uint32_t btn_read();
-uint32_t btn_wait();
-uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask);
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/car.c

@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "car.h"
-#include "timers.h"
-#include "utils.h"
-
-static inline uint32_t get_clk_source_reg(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0x178;
-        case CARDEVICE_UARTB: return 0x17C;
-        case CARDEVICE_UARTC: return 0x1A0;
-        case CARDEVICE_I2C1: return 0x124;
-        case CARDEVICE_I2C5: return 0x128;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0x42C;
-        case CARDEVICE_HOST1X: return 0x180;
-        case CARDEVICE_TSEC: return 0x1F4;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 0x410;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 0x1D4;
-        case CARDEVICE_MSELECT: return 0x3B4;
-        case CARDEVICE_ACTMON: return 0x3E8;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-} 
-
-static inline uint32_t get_clk_source_val(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0;
-        case CARDEVICE_UARTB: return 0;
-        case CARDEVICE_UARTC: return 0;
-        case CARDEVICE_I2C1: return 6;
-        case CARDEVICE_I2C5: return 6;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0;
-        case CARDEVICE_HOST1X: return 4;
-        case CARDEVICE_TSEC: return 0;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 0;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 0;
-        case CARDEVICE_MSELECT: return 0;
-        case CARDEVICE_ACTMON: return 6;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-}
-
-static inline uint32_t get_clk_source_div(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0;
-        case CARDEVICE_UARTB: return 0;
-        case CARDEVICE_UARTC: return 0;
-        case CARDEVICE_I2C1: return 0;
-        case CARDEVICE_I2C5: return 0;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0;
-        case CARDEVICE_HOST1X: return 3;
-        case CARDEVICE_TSEC: return 2;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 2;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 4;
-        case CARDEVICE_MSELECT: return 6;
-        case CARDEVICE_ACTMON: return 0;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-}
-
-static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
-static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; 
-
-void clk_enable(CarDevice dev) {
-    uint32_t clk_source_reg;
-    if ((clk_source_reg = get_clk_source_reg(dev))) {
-        MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev);
-    }
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void clk_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void rst_enable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void rst_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void clkrst_enable(CarDevice dev) {
-    clk_enable(dev);
-    rst_disable(dev);
-}
-
-void clkrst_disable(CarDevice dev) {
-    rst_enable(dev);
-    clk_disable(dev);
-}
-
-void clkrst_reboot(CarDevice dev) {
-    clkrst_disable(dev);
-    if (dev == CARDEVICE_KFUSE) {
-        /* Workaround for KFUSE clock. */
-        clk_enable(dev);
-        udelay(100);
-        rst_disable(dev);
-        udelay(200);
-    } else {
-        clkrst_enable(dev);
-    }
-}
-
-void clkrst_enable_fuse_regs(bool enable) {
-    volatile tegra_car_t *car = car_get_regs();
-    car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28));
-}

fusee/fusee-primary/fusee-primary-main/src/car.h

@@ -1,510 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_CAR_H
-#define FUSEE_CAR_H
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#define CAR_BASE 0x60006000
-#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n)
-
-#define CLK_L_SDMMC1    (1 << 14)
-#define CLK_L_SDMMC2    (1 << 9)
-#define CLK_U_SDMMC3    (1 << 5)
-#define CLK_L_SDMMC4    (1 << 15)
-
-#define CLK_SOURCE_MASK             (0b111 << 29)
-#define CLK_SOURCE_FIRST            (0b000 << 29)
-#define CLK_DIVIDER_MASK            (0xff << 0)
-#define CLK_DIVIDER_UNITY           (0x00 << 0)
-
-#define NUM_CAR_BANKS 7
-
-/* Clock and reset devices. */
-typedef enum {
-    CARDEVICE_BPMP      = ((0 << 5) | 0x1),
-    CARDEVICE_UARTA     = ((0 << 5) | 0x6),
-    CARDEVICE_UARTB     = ((0 << 5) | 0x7),
-    CARDEVICE_I2C1      = ((0 << 5) | 0xC),
-    CARDEVICE_USBD      = ((0 << 5) | 0x16),
-    CARDEVICE_HOST1X    = ((0 << 5) | 0x1C),
-    CARDEVICE_AHBDMA    = ((1 << 5) | 0x1),
-    CARDEVICE_APBDMA    = ((1 << 5) | 0x2),
-    CARDEVICE_KFUSE     = ((1 << 5) | 0x8),
-    CARDEVICE_I2C5      = ((1 << 5) | 0xF),
-    CARDEVICE_UARTC     = ((1 << 5) | 0x17),
-    CARDEVICE_USB2      = ((1 << 5) | 0x1A),
-    CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
-    CARDEVICE_TSEC      = ((2 << 5) | 0x13),
-    CARDEVICE_MSELECT   = ((3 << 5) | 0x8),
-    CARDEVICE_ACTMON    = ((3 << 5) | 0x17),
-    CARDEVICE_TZRAM     = ((3 << 5) | 0x1E),
-    CARDEVICE_SE        = ((3 << 5) | 0x1F),
-    CARDEVICE_CL_DVFS   = ((4 << 5) | 0x1B),
-    CARDEVICE_SOR0      = ((5 << 5) | 0x16),
-    CARDEVICE_SOR1      = ((5 << 5) | 0x17),
-    CARDEVICE_SOR_SAFE  = ((6 << 5) | 0x1E),
-} CarDevice;
-
-/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-typedef struct {
-    uint32_t rst_src;           /* _RST_SOURCE_0,   0x00 */
-
-    /* _RST_DEVICES_L/H/U_0     0x4-0xc */
-    uint32_t rst_dev_l;
-    uint32_t rst_dev_h;
-    uint32_t rst_dev_u;
-
-    /* _CLK_OUT_ENB_L/H/U_0     0x10-0x18 */
-    uint32_t clk_out_enb_l;
-    uint32_t clk_out_enb_h;
-    uint32_t clk_out_enb_u;
-
-    uint32_t _0x1C;
-    uint32_t cclk_brst_pol;     /* _CCLK_BURST_POLICY_0,    0x20 */
-    uint32_t super_cclk_div;    /* _SUPER_CCLK_DIVIDER_0,   0x24 */
-    uint32_t sclk_brst_pol;     /* _SCLK_BURST_POLICY_0,    0x28 */
-    uint32_t super_sclk_div;    /* _SUPER_SCLK_DIVIDER_0,   0x2c */
-    uint32_t clk_sys_rate;      /* _CLK_SYSTEM_RATE_0,      0x30 */
-    uint32_t prog_dly_clk;      /* _PROG_DLY_CLK_0,         0x34 */
-    uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,  0x38 */
-    uint32_t _0x3C;
-    uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,  0x40 */
-    uint32_t clk_mask_arm;      /* _CLK_MASK_ARM_0,         0x44 */
-    uint32_t misc_clk_enb;      /* _MISC_CLK_ENB_0,         0x48 */
-    uint32_t clk_cpu_cmplx;     /* _CLK_CPU_CMPLX_0,        0x4c */
-    uint32_t osc_ctrl;          /* _OSC_CTRL_0,             0x50 */
-    uint32_t pll_lfsr;          /* _PLL_LFSR_0,             0x54 */
-    uint32_t osc_freq_det;      /* _OSC_FREQ_DET_0,         0x58 */
-    uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,  0x5c */
-    uint32_t _0x60[2];
-    uint32_t plle_ss_cntl;      /* _PLLE_SS_CNTL_0,         0x68 */
-    uint32_t plle_misc1;        /* _PLLE_MISC1_0,           0x6c */
-    uint32_t _0x70[4];
-
-    /* PLLC 0x80-0x8c */
-    uint32_t pllc_base;
-    uint32_t pllc_out;
-    uint32_t pllc_misc0;
-    uint32_t pllc_misc1;
-
-    /* PLLM 0x90-0x9c */
-    uint32_t pllm_base;
-    uint32_t pllm_out;
-    uint32_t pllm_misc1;
-    uint32_t pllm_misc2;
-
-    /* PLLP 0xa0-0xac */
-    uint32_t pllp_base;
-    uint32_t pllp_outa;
-    uint32_t pllp_outb;
-    uint32_t pllp_misc;
-
-    /* PLLA 0xb0-0xbc */
-    uint32_t plla_base;
-    uint32_t plla_out;
-    uint32_t plla_misc0;
-    uint32_t plla_misc1;
-
-    /* PLLU 0xc0-0xcc */
-    uint32_t pllu_base;
-    uint32_t pllu_out;
-    uint32_t pllu_misc1;
-    uint32_t pllu_misc2;
-
-    /* PLLD 0xd0-0xdc */
-    uint32_t plld_base;
-    uint32_t plld_out;
-    uint32_t plld_misc1;
-    uint32_t plld_misc2;
-
-    /* PLLX 0xe0-0xe4 */
-    uint32_t pllx_base;
-    uint32_t pllx_misc;
-
-    /* PLLE 0xe8-0xf4 */
-    uint32_t plle_base;
-    uint32_t plle_misc;
-    uint32_t plle_ss_cntl1;
-    uint32_t plle_ss_cntl2;
-
-    uint32_t lvl2_clk_gate_ovra;            /* _LVL2_CLK_GATE_OVRA_0,   0xf8 */
-    uint32_t lvl2_clk_gate_ovrb;            /* _LVL2_CLK_GATE_OVRB_0,   0xfc */
-
-    uint32_t clk_source_i2s2;               /* _CLK_SOURCE_I2S2_0,      0x100 */
-    uint32_t clk_source_i2s3;               /* _CLK_SOURCE_I2S3_0,      0x104 */
-    uint32_t clk_source_spdif_out;          /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */
-    uint32_t clk_source_spdif_in;           /* _CLK_SOURCE_SPDIF_IN_0,  0x10c */
-    uint32_t clk_source_pwm;                /* _CLK_SOURCE_PWM_0,       0x110 */
-    uint32_t _0x114;
-    uint32_t clk_source_spi2;               /* _CLK_SOURCE_SPI2_0,      0x118 */
-    uint32_t clk_source_spi3;               /* _CLK_SOURCE_SPI3_0,      0x11c */
-    uint32_t _0x120;
-    uint32_t clk_source_i2c1;               /* _CLK_SOURCE_I2C1_0,      0x124 */
-    uint32_t clk_source_i2c5;               /* _CLK_SOURCE_I2C5_0,      0x128 */
-    uint32_t _0x12c[2];
-    uint32_t clk_source_spi1;               /* _CLK_SOURCE_SPI1_0,      0x134 */
-    uint32_t clk_source_disp1;              /* _CLK_SOURCE_DISP1_0,     0x138 */
-    uint32_t clk_source_disp2;              /* _CLK_SOURCE_DISP2_0,     0x13c */
-    uint32_t _0x140;
-    uint32_t clk_source_isp;                /* _CLK_SOURCE_ISP_0,       0x144 */
-    uint32_t clk_source_vi;                 /* _CLK_SOURCE_VI_0,        0x148 */
-    uint32_t _0x14c;
-    uint32_t clk_source_sdmmc1;             /* _CLK_SOURCE_SDMMC1_0,    0x150 */
-    uint32_t clk_source_sdmmc2;             /* _CLK_SOURCE_SDMMC2_0,    0x154 */
-    uint32_t _0x158[3];
-    uint32_t clk_source_sdmmc4;             /* _CLK_SOURCE_SDMMC4_0,    0x164 */
-    uint32_t _0x168[4];
-    uint32_t clk_source_uarta;              /* _CLK_SOURCE_UARTA_0,     0x178 */
-    uint32_t clk_source_uartb;              /* _CLK_SOURCE_UARTB_0,     0x17c */
-    uint32_t clk_source_host1x;             /* _CLK_SOURCE_HOST1X_0,    0x180 */
-    uint32_t _0x184[5];
-    uint32_t clk_source_i2c2;               /* _CLK_SOURCE_I2C2_0,      0x198 */
-    uint32_t clk_source_emc;                /* _CLK_SOURCE_EMC_0,       0x19c */
-    uint32_t clk_source_uartc;              /* _CLK_SOURCE_UARTC_0,     0x1a0 */
-    uint32_t _0x1a4;
-    uint32_t clk_source_vi_sensor;          /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */
-    uint32_t _0x1ac[2];
-    uint32_t clk_source_spi4;               /* _CLK_SOURCE_SPI4_0,      0x1b4 */
-    uint32_t clk_source_i2c3;               /* _CLK_SOURCE_I2C3_0,      0x1b8 */
-    uint32_t clk_source_sdmmc3;             /* _CLK_SOURCE_SDMMC3_0,    0x1bc */
-    uint32_t clk_source_uartd;              /* _CLK_SOURCE_UARTD_0,     0x1c0 */
-    uint32_t _0x1c4[2];
-    uint32_t clk_source_owr;                /* _CLK_SOURCE_OWR_0,       0x1cc */
-    uint32_t _0x1d0;
-    uint32_t clk_source_csite;              /* _CLK_SOURCE_CSITE_0,     0x1d4 */
-    uint32_t clk_source_i2s1;               /* _CLK_SOURCE_I2S1_0,      0x1d8 */
-    uint32_t clk_source_dtv;                /* _CLK_SOURCE_DTV_0,       0x1dc */
-    uint32_t _0x1e0[5];
-    uint32_t clk_source_tsec;               /* _CLK_SOURCE_TSEC_0,      0x1f4 */
-    uint32_t _0x1f8;
-
-    uint32_t clk_spare2;                    /* _CLK_SPARE2_0,       0x1fc */
-    uint32_t _0x200[32];
-
-    uint32_t clk_out_enb_x;                 /* _CLK_OUT_ENB_X_0,    0x280 */
-    uint32_t clk_enb_x_set;                 /* _CLK_ENB_X_SET_0,    0x284 */
-    uint32_t clk_enb_x_clr;                 /* _CLK_ENB_X_CLR_0,    0x288 */
-
-    uint32_t rst_devices_x;                 /* _RST_DEVICES_X_0,    0x28c */
-    uint32_t rst_dev_x_set;                 /* _RST_DEV_X_SET_0,    0x290 */
-    uint32_t rst_dev_x_clr;                 /* _RST_DEV_X_CLR_0,    0x294 */
-
-    uint32_t clk_out_enb_y;                 /* _CLK_OUT_ENB_Y_0,    0x298 */
-    uint32_t clk_enb_y_set;                 /* _CLK_ENB_Y_SET_0,    0x29c */
-    uint32_t clk_enb_y_clr;                 /* _CLK_ENB_Y_CLR_0,    0x2a0 */
-
-    uint32_t rst_devices_y;                 /* _RST_DEVICES_Y_0,    0x2a4 */
-    uint32_t rst_dev_y_set;                 /* _RST_DEV_Y_SET_0,    0x2a8 */
-    uint32_t rst_dev_y_clr;                 /* _RST_DEV_Y_CLR_0,    0x2ac */
-
-    uint32_t _0x2b0[17];
-    uint32_t dfll_base;                     /* _DFLL_BASE_0,        0x2f4 */
-    uint32_t _0x2f8[2];
-
-    /* _RST_DEV_L/H/U_SET_0 0x300-0x314 */
-    uint32_t rst_dev_l_set;
-    uint32_t rst_dev_l_clr;
-    uint32_t rst_dev_h_set;
-    uint32_t rst_dev_h_clr;
-    uint32_t rst_dev_u_set;
-    uint32_t rst_dev_u_clr;
-
-    uint32_t _0x318[2];
-
-    /* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */
-    uint32_t clk_enb_l_set;
-    uint32_t clk_enb_l_clr;
-    uint32_t clk_enb_h_set;
-    uint32_t clk_enb_h_clr;
-    uint32_t clk_enb_u_set;
-    uint32_t clk_enb_u_clr;
-
-    uint32_t _0x338;
-    uint32_t ccplex_pg_sm_ovrd;         /* _CCPLEX_PG_SM_OVRD_0,    0x33c */
-    uint32_t rst_cpu_cmplx_set;         /* _RST_CPU_CMPLX_SET_0,    0x340 */
-    uint32_t rst_cpu_cmplx_clr;         /* _RST_CPU_CMPLX_CLR_0,    0x344 */
-
-    /* Additional (T30) registers */
-    uint32_t clk_cpu_cmplx_set;         /* _CLK_CPU_CMPLX_SET_0,    0x348 */
-    uint32_t clk_cpu_cmplx_clr;         /* _CLK_CPU_CMPLX_SET_0,    0x34c */
-
-    uint32_t _0x350[2];
-    uint32_t rst_dev_v;                 /* _RST_DEVICES_V_0,        0x358 */
-    uint32_t rst_dev_w;                 /* _RST_DEVICES_W_0,        0x35c */
-    uint32_t clk_out_enb_v;             /* _CLK_OUT_ENB_V_0,        0x360 */
-    uint32_t clk_out_enb_w;             /* _CLK_OUT_ENB_W_0,        0x364 */
-    uint32_t cclkg_brst_pol;            /* _CCLKG_BURST_POLICY_0,   0x368 */
-    uint32_t super_cclkg_div;           /* _SUPER_CCLKG_DIVIDER_0,  0x36c */
-    uint32_t cclklp_brst_pol;           /* _CCLKLP_BURST_POLICY_0,  0x370 */
-    uint32_t super_cclkp_div;           /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
-    uint32_t clk_cpug_cmplx;            /* _CLK_CPUG_CMPLX_0,       0x378 */
-    uint32_t clk_cpulp_cmplx;           /* _CLK_CPULP_CMPLX_0,      0x37c */
-    uint32_t cpu_softrst_ctrl;          /* _CPU_SOFTRST_CTRL_0,     0x380 */
-    uint32_t cpu_softrst_ctrl1;         /* _CPU_SOFTRST_CTRL1_0,    0x384 */
-    uint32_t cpu_softrst_ctrl2;         /* _CPU_SOFTRST_CTRL2_0,    0x388 */
-    uint32_t _0x38c[5];
-    uint32_t lvl2_clk_gate_ovrc;        /* _LVL2_CLK_GATE_OVRC,     0x3a0 */
-    uint32_t lvl2_clk_gate_ovrd;        /* _LVL2_CLK_GATE_OVRD,     0x3a4 */
-    uint32_t _0x3a8[2];
-
-    uint32_t _0x3b0;
-    uint32_t clk_source_mselect;        /* _CLK_SOURCE_MSELECT_0,       0x3b4 */
-    uint32_t clk_source_tsensor;        /* _CLK_SOURCE_TSENSOR_0,       0x3b8 */
-    uint32_t clk_source_i2s4;           /* _CLK_SOURCE_I2S4_0,          0x3bc */
-    uint32_t clk_source_i2s5;           /* _CLK_SOURCE_I2S5_0,          0x3c0 */
-    uint32_t clk_source_i2c4;           /* _CLK_SOURCE_I2C4_0,          0x3c4 */
-    uint32_t _0x3c8[2];
-    uint32_t clk_source_ahub;           /* _CLK_SOURCE_AHUB_0,          0x3d0 */
-    uint32_t _0x3d4[4];
-    uint32_t clk_source_hda2codec_2x;   /* _CLK_SOURCE_HDA2CODEC_2X_0,  0x3e4 */
-    uint32_t clk_source_actmon;         /* _CLK_SOURCE_ACTMON_0,        0x3e8 */
-    uint32_t clk_source_extperiph1;     /* _CLK_SOURCE_EXTPERIPH1_0,    0x3ec */
-    uint32_t clk_source_extperiph2;     /* _CLK_SOURCE_EXTPERIPH2_0,    0x3f0 */
-    uint32_t clk_source_extperiph3;     /* _CLK_SOURCE_EXTPERIPH3_0,    0x3f4 */
-    uint32_t _0x3f8;
-    uint32_t clk_source_i2c_slow;       /* _CLK_SOURCE_I2C_SLOW_0,      0x3fc */
-    uint32_t clk_source_sys;            /* _CLK_SOURCE_SYS_0,           0x400 */
-    uint32_t clk_source_ispb;           /* _CLK_SOURCE_ISPB_0,          0x404 */
-    uint32_t _0x408[2];
-    uint32_t clk_source_sor1;           /* _CLK_SOURCE_SOR1_0,          0x410 */
-    uint32_t clk_source_sor0;           /* _CLK_SOURCE_SOR0_0,          0x414 */
-    uint32_t _0x418[2];
-    uint32_t clk_source_sata_oob;       /* _CLK_SOURCE_SATA_OOB_0,      0x420 */
-    uint32_t clk_source_sata;           /* _CLK_SOURCE_SATA_0,          0x424 */
-    uint32_t clk_source_hda;            /* _CLK_SOURCE_HDA_0,           0x428 */
-    uint32_t clk_source_se;             /* _CLK_SOURCE_SE_0,            0x42c */
-
-    /* _RST_DEV_V/W_SET_0 0x430-0x43c */
-    uint32_t rst_dev_v_set;
-    uint32_t rst_dev_v_clr;
-    uint32_t rst_dev_w_set;
-    uint32_t rst_dev_w_clr;
-
-    /* _CLK_ENB_V/W_CLR_0 0x440-0x44c */
-    uint32_t clk_enb_v_set;
-    uint32_t clk_enb_v_clr;
-    uint32_t clk_enb_w_set;
-    uint32_t clk_enb_w_clr;
-
-    /* Additional (T114+) registers */
-    uint32_t rst_cpug_cmplx_set;    /* _RST_CPUG_CMPLX_SET_0,   0x450 */
-    uint32_t rst_cpug_cmplx_clr;    /* _RST_CPUG_CMPLX_CLR_0,   0x454 */
-    uint32_t rst_cpulp_cmplx_set;   /* _RST_CPULP_CMPLX_SET_0,  0x458 */
-    uint32_t rst_cpulp_cmplx_clr;   /* _RST_CPULP_CMPLX_CLR_0,  0x45c */
-    uint32_t clk_cpug_cmplx_set;    /* _CLK_CPUG_CMPLX_SET_0,   0x460 */
-    uint32_t clk_cpug_cmplx_clr;    /* _CLK_CPUG_CMPLX_CLR_0,   0x464 */
-    uint32_t clk_cpulp_cmplx_set;   /* _CLK_CPULP_CMPLX_SET_0,  0x468 */
-    uint32_t clk_cpulp_cmplx_clr;   /* _CLK_CPULP_CMPLX_CLR_0,  0x46c */
-    uint32_t cpu_cmplx_status;      /* _CPU_CMPLX_STATUS_0,     0x470 */
-    uint32_t _0x474;
-    uint32_t intstatus;             /* _INTSTATUS_0,            0x478 */
-    uint32_t intmask;               /* _INTMASK_0,              0x47c */
-    uint32_t utmip_pll_cfg0;        /* _UTMIP_PLL_CFG0_0,       0x480 */
-    uint32_t utmip_pll_cfg1;        /* _UTMIP_PLL_CFG1_0,       0x484 */
-    uint32_t utmip_pll_cfg2;        /* _UTMIP_PLL_CFG2_0,       0x488 */
-
-    uint32_t plle_aux;              /* _PLLE_AUX_0,             0x48c */
-    uint32_t sata_pll_cfg0;         /* _SATA_PLL_CFG0_0,        0x490 */
-    uint32_t sata_pll_cfg1;         /* _SATA_PLL_CFG1_0,        0x494 */
-    uint32_t pcie_pll_cfg0;         /* _PCIE_PLL_CFG0_0,        0x498 */
-
-    uint32_t prog_audio_dly_clk;    /* _PROG_AUDIO_DLY_CLK_0,   0x49c */
-    uint32_t audio_sync_clk_i2s0;   /* _AUDIO_SYNC_CLK_I2S0_0,  0x4a0 */
-    uint32_t audio_sync_clk_i2s1;   /* _AUDIO_SYNC_CLK_I2S1_0,  0x4a4 */
-    uint32_t audio_sync_clk_i2s2;   /* _AUDIO_SYNC_CLK_I2S2_0,  0x4a8 */
-    uint32_t audio_sync_clk_i2s3;   /* _AUDIO_SYNC_CLK_I2S3_0,  0x4ac */
-    uint32_t audio_sync_clk_i2s4;   /* _AUDIO_SYNC_CLK_I2S4_0,  0x4b0 */
-    uint32_t audio_sync_clk_spdif;  /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */
-
-    uint32_t plld2_base;            /* _PLLD2_BASE_0, 0x4b8 */
-    uint32_t plld2_misc;            /* _PLLD2_MISC_0, 0x4bc */
-    uint32_t utmip_pll_cfg3;        /* _UTMIP_PLL_CFG3_0, 0x4c0 */
-    uint32_t pllrefe_base;          /* _PLLREFE_BASE_0, 0x4c4 */
-    uint32_t pllrefe_misc;          /* _PLLREFE_MISC_0, 0x4c8 */
-    uint32_t pllrefe_out;           /* _PLLREFE_OUT_0, 0x4cc */
-    uint32_t cpu_finetrim_byp;      /* _CPU_FINETRIM_BYP_0, 0x4d0 */
-    uint32_t cpu_finetrim_select;   /* _CPU_FINETRIM_SELECT_0, 0x4d4 */
-    uint32_t cpu_finetrim_dr;       /* _CPU_FINETRIM_DR_0, 0x4d8 */
-    uint32_t cpu_finetrim_df;       /* _CPU_FINETRIM_DF_0, 0x4dc */
-    uint32_t cpu_finetrim_f;        /* _CPU_FINETRIM_F_0, 0x4e0 */
-    uint32_t cpu_finetrim_r;        /* _CPU_FINETRIM_R_0, 0x4e4 */
-    uint32_t pllc2_base;            /* _PLLC2_BASE_0, 0x4e8 */
-    uint32_t pllc2_misc0;           /* _PLLC2_MISC_0_0, 0x4ec */
-    uint32_t pllc2_misc1;           /* _PLLC2_MISC_1_0, 0x4f0 */
-    uint32_t pllc2_misc2;           /* _PLLC2_MISC_2_0, 0x4f4 */
-    uint32_t pllc2_misc3;           /* _PLLC2_MISC_3_0, 0x4f8 */
-    uint32_t pllc3_base;            /* _PLLC3_BASE_0, 0x4fc */
-    uint32_t pllc3_misc0;           /* _PLLC3_MISC_0_0, 0x500 */
-    uint32_t pllc3_misc1;           /* _PLLC3_MISC_1_0, 0x504 */
-    uint32_t pllc3_misc2;           /* _PLLC3_MISC_2_0, 0x508 */
-    uint32_t pllc3_misc3;           /* _PLLC3_MISC_3_0, 0x50c */
-    uint32_t pllx_misc1;            /* _PLLX_MISC_1_0, 0x510 */
-    uint32_t pllx_misc2;            /* _PLLX_MISC_2_0, 0x514 */
-    uint32_t pllx_misc3;            /* _PLLX_MISC_3_0, 0x518 */
-    uint32_t xusbio_pll_cfg0;       /* _XUSBIO_PLL_CFG0_0, 0x51c */
-    uint32_t xusbio_pll_cfg1;       /* _XUSBIO_PLL_CFG0_1, 0x520 */
-    uint32_t plle_aux1;             /* _PLLE_AUX1_0, 0x524 */
-    uint32_t pllp_reshift;          /* _PLLP_RESHIFT_0, 0x528 */
-    uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */
-    uint32_t pllu_hw_pwrdn_cfg0;    /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
-    uint32_t xusb_pll_cfg0;         /* _XUSB_PLL_CFG0_0, 0x534 */
-    uint32_t _0x538;
-    uint32_t clk_cpu_misc;          /* _CLK_CPU_MISC_0, 0x53c */
-    uint32_t clk_cpug_misc;         /* _CLK_CPUG_MISC_0, 0x540 */
-    uint32_t clk_cpulp_misc;        /* _CLK_CPULP_MISC_0, 0x544 */
-    uint32_t pllx_hw_ctrl_cfg;      /* _PLLX_HW_CTRL_CFG_0, 0x548 */
-    uint32_t pllx_sw_ramp_cfg;      /* _PLLX_SW_RAMP_CFG_0, 0x54c */
-    uint32_t pllx_hw_ctrl_status;   /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
-    uint32_t lvl2_clk_gate_ovre;    /* _LVL2_CLK_GATE_OVRE, 0x554 */
-    uint32_t super_gr3d_clk_div;    /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
-    uint32_t spare_reg0;            /* _SPARE_REG0_0, 0x55c */
-    uint32_t audio_sync_clk_dmic1;  /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
-    uint32_t audio_sync_clk_dmic2;  /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
-
-    uint32_t _0x568[2];
-    uint32_t plld2_ss_cfg;          /* _PLLD2_SS_CFG,           0x570 */
-    uint32_t plld2_ss_ctrl1;        /* _PLLD2_SS_CTRL1_0,       0x574 */
-    uint32_t plld2_ss_ctrl2;        /* _PLLD2_SS_CTRL2_0,       0x578 */
-    uint32_t _0x57c[5];
-
-    uint32_t plldp_base;            /* _PLLDP_BASE, 0x590*/
-    uint32_t plldp_misc;            /* _PLLDP_MISC, 0x594 */
-    uint32_t plldp_ss_cfg;          /* _PLLDP_SS_CFG, 0x598 */
-    uint32_t plldp_ss_ctrl1;        /* _PLLDP_SS_CTRL1_0, 0x59c */
-    uint32_t plldp_ss_ctrl2;        /* _PLLDP_SS_CTRL2_0, 0x5a0 */
-    uint32_t pllc4_base;            /* _PLLC4_BASE_0, 0x5a4 */
-    uint32_t pllc4_misc;            /* _PLLC4_MISC_0, 0x5a8 */
-    uint32_t _0x5ac[6];
-    uint32_t clk_spare0;            /* _CLK_SPARE0_0, 0x5c4 */
-    uint32_t clk_spare1;            /* _CLK_SPARE1_0, 0x5c8 */
-    uint32_t gpu_isob_ctrl;         /* _GPU_ISOB_CTRL_0, 0x5cc */
-    uint32_t pllc_misc2;            /* _PLLC_MISC_2_0, 0x5d0 */
-    uint32_t pllc_misc3;            /* _PLLC_MISC_3_0, 0x5d4 */
-    uint32_t plla_misc2;            /* _PLLA_MISC2_0, 0x5d8 */
-    uint32_t _0x5dc[2];
-    uint32_t pllc4_out;             /* _PLLC4_OUT_0, 0x5e4 */
-    uint32_t pllmb_base;            /* _PLLMB_BASE_0, 0x5e8 */
-    uint32_t pllmb_misc1;           /* _PLLMB_MISC1_0, 0x5ec */
-    uint32_t pllx_misc4;            /* _PLLX_MISC_4_0, 0x5f0 */
-    uint32_t pllx_misc5;            /* _PLLX_MISC_5_0, 0x5f4 */
-    uint32_t _0x5f8[2];
-
-    uint32_t clk_source_xusb_core_host;             /* _CLK_SOURCE_XUSB_CORE_HOST_0,    0x600 */
-    uint32_t clk_source_xusb_falcon;                /* _CLK_SOURCE_XUSB_FALCON_0,    0x604 */
-    uint32_t clk_source_xusb_fs;                    /* _CLK_SOURCE_XUSB_FS_0,    0x608 */
-    uint32_t clk_source_xusb_core_dev;              /* _CLK_SOURCE_XUSB_CORE_DEV_0,    0x60c */
-    uint32_t clk_source_xusb_ss;                    /* _CLK_SOURCE_XUSB_SS_0,    0x610 */
-    uint32_t clk_source_cilab;                      /* _CLK_SOURCE_CILAB_0,    0x614 */
-    uint32_t clk_source_cilcd;                      /* _CLK_SOURCE_CILCD_0,    0x618 */
-    uint32_t clk_source_cilef;                      /* _CLK_SOURCE_CILEF_0,    0x61c */
-    uint32_t clk_source_dsia_lp;                    /* _CLK_SOURCE_DSIA_LP_0,    0x620 */
-    uint32_t clk_source_dsib_lp;                    /* _CLK_SOURCE_DSIB_LP_0,    0x624 */
-    uint32_t clk_source_entropy;                    /* _CLK_SOURCE_ENTROPY_0,    0x628 */
-    uint32_t clk_source_dvfs_ref;                   /* _CLK_SOURCE_DVFS_REF_0,    0x62c */
-    uint32_t clk_source_dvfs_soc;                   /* _CLK_SOURCE_DVFS_SOC_0,    0x630 */
-    uint32_t _0x634[3];
-    uint32_t clk_source_emc_latency;                /* _CLK_SOURCE_EMC_LATENCY_0,    0x640 */
-    uint32_t clk_source_soc_therm;                  /* _CLK_SOURCE_SOC_THERM_0,    0x644 */
-    uint32_t _0x648;
-    uint32_t clk_source_dmic1;                      /* _CLK_SOURCE_DMIC1_0,    0x64c */
-    uint32_t clk_source_dmic2;                      /* _CLK_SOURCE_DMIC2_0,    0x650 */
-    uint32_t _0x654;
-    uint32_t clk_source_vi_sensor2;                 /* _CLK_SOURCE_VI_SENSOR2_0,    0x658 */
-    uint32_t clk_source_i2c6;                       /* _CLK_SOURCE_I2C6_0,    0x65c */
-    uint32_t clk_source_mipibif;                    /* _CLK_SOURCE_MIPIBIF_0,    0x660 */
-    uint32_t clk_source_emc_dll;                    /* _CLK_SOURCE_EMC_DLL_0,    0x664 */
-    uint32_t _0x668;
-    uint32_t clk_source_uart_fst_mipi_cal;          /* _CLK_SOURCE_UART_FST_MIPI_CAL_0,    0x66c */
-    uint32_t _0x670[2];
-    uint32_t clk_source_vic;                        /* _CLK_SOURCE_VIC_0,    0x678 */
-
-    uint32_t pllp_outc;                             /* _PLLP_OUTC_0, 0x67c */
-    uint32_t pllp_misc1;                            /* _PLLP_MISC1_0, 0x680 */
-    uint32_t _0x684[2];
-    uint32_t emc_div_clk_shaper_ctrl;               /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */
-    uint32_t emc_pllc_shaper_ctrl;                  /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */
-
-    uint32_t clk_source_sdmmc_legacy_tm;            /* _CLK_SOURCE_SDMMC_LEGACY_TM_0,    0x694 */
-    uint32_t clk_source_nvdec;                      /* _CLK_SOURCE_NVDEC_0,    0x698 */
-    uint32_t clk_source_nvjpg;                      /* _CLK_SOURCE_NVJPG_0,    0x69c */
-    uint32_t clk_source_nvenc;                      /* _CLK_SOURCE_NVENC_0,    0x6a0 */
-
-    uint32_t plla1_base;                            /* _PLLA1_BASE_0, 0x6a4 */
-    uint32_t plla1_misc0;                           /* _PLLA1_MISC_0_0, 0x6a8 */
-    uint32_t plla1_misc1;                           /* _PLLA1_MISC_1_0, 0x6ac */
-    uint32_t plla1_misc2;                           /* _PLLA1_MISC_2_0, 0x6b0 */
-    uint32_t plla1_misc3;                           /* _PLLA1_MISC_3_0, 0x6b4 */
-    uint32_t audio_sync_clk_dmic3;                  /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
-
-    uint32_t clk_source_dmic3;                      /* _CLK_SOURCE_DMIC3_0,    0x6bc */
-    uint32_t clk_source_ape;                        /* _CLK_SOURCE_APE_0,    0x6c0 */
-    uint32_t clk_source_qspi;                       /* _CLK_SOURCE_QSPI_0,    0x6c4 */
-    uint32_t clk_source_vi_i2c;                     /* _CLK_SOURCE_VI_I2C_0,    0x6c8 */
-    uint32_t clk_source_usb2_hsic_trk;              /* _CLK_SOURCE_USB2_HSIC_TRK_0,    0x6cc */
-    uint32_t clk_source_pex_sata_usb_rx_byp;        /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0,    0x6d0 */
-    uint32_t clk_source_maud;                       /* _CLK_SOURCE_MAUD_0,    0x6d4 */
-    uint32_t clk_source_tsecb;                      /* _CLK_SOURCE_TSECB_0,    0x6d8 */
-
-    uint32_t clk_cpug_misc1;                        /* _CLK_CPUG_MISC1_0, 0x6dc */
-    uint32_t aclk_burst_policy;                     /* _ACLK_BURST_POLICY_0, 0x6e0 */
-    uint32_t super_aclk_divider;                    /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
-
-    uint32_t nvenc_super_clk_divider;               /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
-    uint32_t vi_super_clk_divider;                  /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
-    uint32_t vic_super_clk_divider;                 /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
-    uint32_t nvdec_super_clk_divider;               /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */
-    uint32_t isp_super_clk_divider;                 /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */
-    uint32_t ispb_super_clk_divider;                /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */
-    uint32_t nvjpg_super_clk_divider;               /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */
-    uint32_t se_super_clk_divider;                  /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
-    uint32_t tsec_super_clk_divider;                /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
-    uint32_t tsecb_super_clk_divider;               /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
-
-    uint32_t clk_source_uartape;                    /* _CLK_SOURCE_UARTAPE_0, 0x710 */
-    uint32_t clk_cpug_misc2;                        /* _CLK_CPUG_MISC2_0, 0x714 */
-    uint32_t clk_source_dbgapb;                     /* _CLK_SOURCE_DBGAPB_0, 0x718 */
-    uint32_t clk_ccplex_cc4_ret_clk_enb;            /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */
-    uint32_t actmon_cpu_clk;                        /* _ACTMON_CPU_CLK_0, 0x720 */
-    uint32_t clk_source_emc_safe;                   /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */
-    uint32_t sdmmc2_pllc4_out0_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */
-    uint32_t sdmmc2_pllc4_out1_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */
-    uint32_t sdmmc2_pllc4_out2_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */
-    uint32_t sdmmc2_div_clk_shaper_ctrl;            /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */
-    uint32_t sdmmc4_pllc4_out0_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
-    uint32_t sdmmc4_pllc4_out1_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
-    uint32_t sdmmc4_pllc4_out2_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
-    uint32_t sdmmc4_div_clk_shaper_ctrl;            /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */    
-} tegra_car_t;
-
-static inline volatile tegra_car_t *car_get_regs(void) {
-    return (volatile tegra_car_t *)CAR_BASE;
-}
-
-void clk_enable(CarDevice dev);
-void clk_disable(CarDevice dev);
-void rst_enable(CarDevice dev);
-void rst_disable(CarDevice dev);
-
-void clkrst_enable(CarDevice dev);
-void clkrst_disable(CarDevice dev);
-void clkrst_reboot(CarDevice dev);
-
-void clkrst_enable_fuse_regs(bool enable);
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/chainloader.c

@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "chainloader.h"
-
-int g_chainloader_argc = 0;
-char g_chainloader_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE] = {0};
-chainloader_entry_t g_chainloader_entries[CHAINLOADER_MAX_ENTRIES] = {0}; /* keep them sorted */
-size_t g_chainloader_num_entries = 0;
-uintptr_t g_chainloader_entrypoint = 0;
-
-#pragma GCC optimize (3)
-
-static void *xmemmove(void *dst, const void *src, size_t len)
-{
-    const uint8_t *src8 = (const uint8_t *)src;
-    uint8_t *dst8 = (uint8_t *)dst;
-
-    if (dst8 < src8) {
-        for (size_t i = 0; i < len; i++) {
-            dst8[i] = src8[i];
-        }
-    } else if (dst8 > src8) {
-        for (size_t i = len; len > 0; len--)
-            dst8[i - 1] = src8[i - 1];
-    }
-
-    return dst;
-}
-
-void relocate_and_chainload_main(void) {
-    for(size_t i = 0; i < g_chainloader_num_entries; i++) {
-        chainloader_entry_t *entry = &g_chainloader_entries[i];
-        xmemmove((void *)entry->load_address, (const void *)entry->src_address, entry->size);
-    }
-
-    ((void (*)(int, void *))g_chainloader_entrypoint)(g_chainloader_argc, g_chainloader_arg_data);
-}

fusee/fusee-primary/fusee-primary-main/src/chainloader.h

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_CHAINLOADER_H
-#define FUSEE_CHAINLOADER_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
-#define CHAINLOADER_MAX_ENTRIES       128
-
-typedef struct chainloader_entry_t {
-    uintptr_t load_address;
-    uintptr_t src_address;
-    size_t size;
-    size_t num;
-} chainloader_entry_t;
-
-extern int g_chainloader_argc;
-extern chainloader_entry_t g_chainloader_entries[CHAINLOADER_MAX_ENTRIES]; /* keep them sorted */
-extern size_t g_chainloader_num_entries;
-extern uintptr_t g_chainloader_entrypoint;
-
-extern char g_chainloader_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE];
-
-void relocate_and_chainload(void);
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/di.c

@@ -1,465 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <string.h>
-
-#include "di.h"
-#include "fuse.h"
-#include "timers.h"
-#include "i2c.h"
-#include "pmc.h"
-#include "max77620.h"
-#include "gpio.h"
-#include "pinmux.h"
-#include "car.h"
-#include "apb_misc.h"
-
-#include "di.inl"
-
-static uint32_t g_lcd_vendor = 0;
-
-/* Determine the current SoC for Mariko specific code. */
-static bool is_soc_mariko() {
-    return (fuse_get_soc_type() == 1);
-}
-
-static void do_dsi_sleep_or_register_writes(const dsi_sleep_or_register_write_t *writes, uint32_t num_writes) {
-    for (uint32_t i = 0; i < num_writes; i++) {
-        if (writes[i].kind == 1) {
-            udelay(1000 * writes[i].offset);
-        } else {
-            *(volatile uint32_t *)(DSI_BASE + sizeof(uint32_t) * writes[i].offset) = writes[i].value;
-        }
-    }
-}
-
-static void do_register_writes(uint32_t base_address, const register_write_t *writes, uint32_t num_writes) {
-    for (uint32_t i = 0; i < num_writes; i++) {
-        *(volatile uint32_t *)(base_address + writes[i].offset) = writes[i].value;
-    }
-}
-
-static void dsi_wait(uint32_t timeout, uint32_t offset, uint32_t mask, uint32_t delay) {
-    uint32_t end = get_time_us() + timeout;
-    while ((get_time_us() < end) && (MAKE_DSI_REG(offset) & mask)) {
-        /* Wait. */
-    }
-    udelay(delay);
-}
-
-void display_init(void) {
-    volatile tegra_car_t *car = car_get_regs();
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
-    bool is_mariko = is_soc_mariko();
-    uint32_t hardware_type = fuse_get_hardware_type();
-    
-    /* Power on. */
-    if (is_mariko) {
-        uint8_t val = 0x3A;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2, &val, 1);
-        val = 0x71;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2_CFG, &val, 1);
-        val = 0xD0;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1);
-    } else {
-        uint8_t val = 0xD0;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1);
-    } 
-    
-    /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */
-    car->rst_dev_h_clr = 0x1010000;
-    car->clk_enb_h_set = 0x1010000;
-    car->rst_dev_l_clr = 0x18000000;
-    car->clk_enb_l_set = 0x18000000;
-    car->clk_enb_x_set = 0x20000;
-    car->clk_source_uart_fst_mipi_cal = 0xA;
-    car->clk_enb_w_set = 0x80000;
-    car->clk_source_dsia_lp = 0xA;
-
-    /* DPD idle. */
-    pmc->io_dpd_req = 0x40000000;
-    pmc->io_dpd2_req = 0x40000000;
-
-    /* Configure pins. */
-    pinmux->nfc_en &= ~PINMUX_TRISTATE;
-    pinmux->nfc_int &= ~PINMUX_TRISTATE;
-    pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE;
-    pinmux->lcd_bl_en &= ~PINMUX_TRISTATE;
-    pinmux->lcd_rst &= ~PINMUX_TRISTATE;
-    
-    if (is_mariko && (hardware_type == 5)) {
-        /* HardwareType_Five only configures GPIO_LCD_BL_RST. */
-        gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
-        gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
-    } else {
-        /* Configure Backlight +-5V GPIOs. */
-        gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
-        gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
-        gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
-        gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
-            
-        /* Enable Backlight +5V. */
-        gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); 
-
-        udelay(10000);
-
-        /* Enable Backlight -5V. */
-        gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); 
-
-        udelay(10000);
-
-        /* Configure Backlight PWM, EN and RST GPIOs. */
-        gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
-        gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
-        gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);    
-        gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
-        gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
-        gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
-        
-        /* Enable Backlight EN. */
-        gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
-    }
-
-    /* Configure display interface and display. */
-    MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
-    if (is_mariko) {
-        MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0;
-        APB_MISC_GP_DSI_PAD_CONTROL_0 = 0;
-    }
-    
-    if (is_mariko) {
-        do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
-    } else {
-        do_register_writes(CAR_BASE, display_config_plld_01_erista, 4);
-    }
-    do_register_writes(DI_BASE, display_config_dc_01, 94);
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
-    if (is_mariko) {
-        do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1);
-    } else {
-        do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
-    if (is_mariko) {
-        do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7);
-    } else {
-        do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
-    if (is_mariko) {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
-    } else {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
-    if (is_mariko) {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
-    } else {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14);
-
-    udelay(10000);
-    
-    /* Enable Backlight RST. */
-    gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH);
-
-    udelay(60000);
-
-    if (is_mariko && (hardware_type == 5)) {
-        MAKE_DSI_REG(DSI_BTA_TIMING) = 0x40103;
-    } else {
-        MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
-    }
-    MAKE_DSI_REG(DSI_WR_DATA) = 0x337;
-    MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
-    dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5);
-
-    MAKE_DSI_REG(DSI_WR_DATA) = 0x406;
-    MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
-    dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5);
-
-    MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC);
-    dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000);
-
-    /* Parse LCD vendor. */
-    uint32_t host_response[3];
-    for (uint32_t i = 0; i < 3; i++) {
-        host_response[i] = MAKE_DSI_REG(DSI_RD_DATA);
-    }
-
-    /* The last word from host response is:
-        Bits 0-7: FAB
-        Bits 8-15: REV
-        Bits 16-23: Minor REV
-    */
-    if ((host_response[2] & 0xFF) == 0x10) {
-        g_lcd_vendor = 0;
-    } else {
-        g_lcd_vendor = (host_response[2] >> 8) & 0xFF00;
-    }
-    g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF);
-    
-    /* LCD vendor specific configuration. */
-    switch (g_lcd_vendor) {
-        case 0x10: /* Japan Display Inc screens. */
-            do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
-            break;
-        case 0xF20: /* Innolux nx-abca2 screens. */
-            do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
-            break;
-        case 0xF30: /* AUO nx-abca2 screens. */
-            do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
-            break;
-        case 0x2050: /* Unknown nx-abcd screens. */
-            do_dsi_sleep_or_register_writes(display_config_50_nx_abcd_specific_init_01, 13);
-            break;
-        case 0x1020: /* Innolux nx-abcc screens. */
-        case 0x1030: /* AUO nx-abcc screens. */
-        case 0x1040: /* Unknown nx-abcc screens. */
-        default:
-            do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
-            break;
-    }
-    
-    udelay(20000);
-    
-    if (is_mariko) {
-        do_register_writes(CAR_BASE, display_config_plld_02_mariko, 3);
-    } else {
-        do_register_writes(CAR_BASE, display_config_plld_02_erista, 3);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1);
-    if (is_mariko) {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
-    } else {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19);
-    MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4;
-    do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10);
-
-    udelay(10000);
-    
-    if (is_mariko) {
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2);
-        do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2);
-        do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10);
-    } else {
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_erista, 2);
-        do_register_writes(DSI_BASE, display_config_dsi_01_init_11_erista, 4);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_erista, 6);
-        do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10);
-    }
-    
-    udelay(10000);
-
-    do_register_writes(DI_BASE, display_config_dc_02, 113);
-}
-
-void display_end(void) {
-    volatile tegra_car_t *car = car_get_regs();
-    volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
-    bool is_mariko = is_soc_mariko();
-    
-    /* Disable Backlight. */
-    display_backlight(false);
-    
-    MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
-    MAKE_DSI_REG(DSI_WR_DATA) = 0x2805;
-    
-    /* Wait 5 frames. */
-    uint32_t start_val = MAKE_HOST1X_REG(0x30A4);
-    while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) {
-        /* Wait. */
-    }
-
-    MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
-    MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
-    
-    do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
-    udelay(40000);
-    
-    if (is_mariko) {
-        do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
-    } else {
-        do_register_writes(CAR_BASE, display_config_plld_01_erista, 4);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
-    if (is_mariko) {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
-    } else {
-        do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
-    }
-    do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13);
-
-    if (g_lcd_vendor != 0x2050) {
-        udelay(10000);
-    }
-    
-    /* LCD vendor specific shutdown. */
-    switch (g_lcd_vendor) {
-        case 0x10: /* Japan Display Inc screens. */
-            do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
-            break;
-        case 0xF30: /* AUO nx-abca2 screens. */
-            do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
-            break;
-        case 0x1020: /* Innolux nx-abcc screens. */
-            do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
-            break;
-        case 0x1030: /* AUO nx-abcc screens. */
-            do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
-            break;
-        case 0x1040: /* Unknown nx-abcc screens. */
-            do_dsi_sleep_or_register_writes(display_config_40_nx_abcc_specific_fini_01, 10);
-            break;
-        default:
-            break;
-    }
-    
-    MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
-    MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
-    udelay((g_lcd_vendor == 0x2050) ? 120000 : 50000);
-    
-    /* Disable Backlight RST. */
-    gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); 
-
-    if (g_lcd_vendor == 0x2050) {
-        udelay(30000);
-    } else {
-        udelay(10000);
-    
-        /* Disable Backlight -5V. */
-        gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); 
-
-        udelay(10000);
-
-        /* Disable Backlight +5V. */
-        gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); 
-
-        udelay(10000);
-    }
-
-    /* Disable clocks. */
-    car->rst_dev_h_set = 0x1010000;
-    car->clk_enb_h_clr = 0x1010000;
-    car->rst_dev_l_set = 0x18000000;
-    car->clk_enb_l_clr = 0x18000000;
-
-    MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
-    MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
-    
-    if (!is_mariko) {
-        /* Backlight PWM. */
-        gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO);
-        
-        pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE);
-        pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1);
-    }
-}
-
-void display_backlight(bool enable) {
-    if (g_lcd_vendor == 0x2050) {
-        int brightness = enable ? 100 : 0;
-        
-        /* Enable FRAME_END_INT */
-        MAKE_DI_REG(DC_CMD_INT_ENABLE) = 2;
-        
-        /* Configure DSI_LINE_TYPE as FOUR */
-        MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
-        MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 9;
-
-        /* Set and wait for FRAME_END_INT */
-        MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
-        while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
-            /* Wait */
-        }
-        
-        /* Configure display brightness. */
-        const uint32_t brightness_val = ((0x7FF * brightness) / 100);
-        MAKE_DSI_REG(DSI_WR_DATA) = 0x339;
-        MAKE_DSI_REG(DSI_WR_DATA) = (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51;
-
-        /* Set and wait for FRAME_END_INT */
-        MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
-        while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
-            /* Wait */
-        }
-
-        /* Set client sync point block reset. */
-        MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 1;
-        udelay(300000);
-
-        /* Clear client sync point block resest. */
-        MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 0;
-        udelay(300000);
-
-        /* Clear DSI_LINE_TYPE config. */
-        MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
-
-        /* Disable FRAME_END_INT */
-        MAKE_DI_REG(DC_CMD_INT_ENABLE) = 0;
-        MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
-    } else {
-        /* Enable Backlight PWM. */
-        gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
-    }
-}
-
-void display_color_screen(uint32_t color) {
-    do_register_writes(DI_BASE, display_config_solid_color, 8);
-
-    /* Configure display to show single color. */
-    MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0;
-    MAKE_DI_REG(DC_WIN_BD_WIN_OPTIONS) = 0;
-    MAKE_DI_REG(DC_WIN_CD_WIN_OPTIONS) = 0;
-    MAKE_DI_REG(DC_DISP_BLEND_BACKGROUND_COLOR) = color;
-    MAKE_DI_REG(DC_CMD_STATE_CONTROL) = ((MAKE_DI_REG(DC_CMD_STATE_CONTROL) & 0xFFFFFFFE) | GENERAL_ACT_REQ);
-
-    udelay(35000);
-
-    display_backlight(true);
-}
-
-uint32_t *display_init_framebuffer(void *address) {
-    static register_write_t conf[sizeof(display_config_frame_buffer)/sizeof(register_write_t)] = {0};
-    if (conf[0].value == 0) {
-        for (uint32_t i = 0; i < sizeof(display_config_frame_buffer)/sizeof(register_write_t); i++) {
-            conf[i] = display_config_frame_buffer[i];
-        }
-    }
-
-    uint32_t *lfb_addr = (uint32_t *)address;
-    conf[19].value = (uint32_t)address;
-    
-    /* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */
-    do_register_writes(DI_BASE, conf, 32);
-
-    udelay(35000);
-
-    return lfb_addr;
-}

fusee/fusee-primary/fusee-primary-main/src/di.inl

@@ -1,773 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX 
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-typedef struct {
-    uint32_t offset;
-    uint32_t value;
-} register_write_t;
-
-typedef struct {
-    uint16_t kind;
-    uint16_t offset;
-    uint32_t value;
-} dsi_sleep_or_register_write_t;
-
-static const uint32_t display_config_frame_buffer_address = 0xC0000000;
-
-static const register_write_t display_config_plld_01_erista[4] = {
-    {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000},
-    {CLK_RST_CONTROLLER_PLLD_BASE,        0x4830A001},
-    {CLK_RST_CONTROLLER_PLLD_MISC1,       0x00000020},
-    {CLK_RST_CONTROLLER_PLLD_MISC,        0x002D0AAA},
-};
-
-static const register_write_t display_config_plld_01_mariko[4] = {
-    {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000},
-    {CLK_RST_CONTROLLER_PLLD_BASE,        0x4830A001},
-    {CLK_RST_CONTROLLER_PLLD_MISC1,       0x00000000},
-    {CLK_RST_CONTROLLER_PLLD_MISC,        0x002DFC00},
-};
-
-static const register_write_t display_config_dc_01[94] = {
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_REG_ACT_CONTROL, 0x54},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_DISP_DC_MCCIF_FIFOCTRL, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
-    {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
-    {sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_CSC_YOF,   0xF0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUR,   0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVR,   0x198},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUG,   0x39B},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVG,   0x32F},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUB,   0x204},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVB,   0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_CSC_YOF,   0xF0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUR,   0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVR,   0x198},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUG,   0x39B},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVG,   0x32F},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUB,   0x204},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVB,   0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_CSC_YOF,   0xF0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUR,   0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVR,   0x198},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUG,   0x39B},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVG,   0x32F},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUB,   0x204},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVB,   0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
-    {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
-    {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
-    {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-    {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0},
-    {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-};
-
-static const register_write_t display_config_dsi_01_init_01[8] = {
-    {sizeof(uint32_t) * DSI_WR_DATA,         0x0},
-    {sizeof(uint32_t) * DSI_INT_ENABLE,      0x0},
-    {sizeof(uint32_t) * DSI_INT_STATUS,      0x0},
-    {sizeof(uint32_t) * DSI_INT_MASK,        0x0},
-    {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_0, 0x0},
-    {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_1, 0x0},
-    {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_2, 0x0},
-    {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_3, 0x0},
-};
-
-static const register_write_t display_config_dsi_01_init_02_erista[1] = {
-    {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15, 0x0},
-};
-
-static const register_write_t display_config_dsi_01_init_02_mariko[1] = {
-    {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0},
-};
-
-static const register_write_t display_config_dsi_01_init_03[14] = {
-    {sizeof(uint32_t) * DSI_DCS_CMDS,     0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_0_HI, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_1_HI, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_2_HI, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0},
-    {sizeof(uint32_t) * DSI_CONTROL,      0},
-};
-
-static const register_write_t display_config_dsi_01_init_04_erista[0] = {
-    /* No register writes. */
-};
-
-static const register_write_t display_config_dsi_01_init_04_mariko[7] = {
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_1,        0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_2,        0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_3,        0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_4,        0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, 0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0},
-};
-
-static const register_write_t display_config_dsi_01_init_05[10] = {
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_CD,   0},
-    {sizeof(uint32_t) * DSI_SOL_DELAY,        0x18},
-    {sizeof(uint32_t) * DSI_MAX_THRESHOLD,    0x1E0},
-    {sizeof(uint32_t) * DSI_TRIGGER,          0},
-    {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0},
-    {sizeof(uint32_t) * DSI_PKT_LEN_0_1,      0},
-    {sizeof(uint32_t) * DSI_PKT_LEN_2_3,      0},
-    {sizeof(uint32_t) * DSI_PKT_LEN_4_5,      0},
-    {sizeof(uint32_t) * DSI_PKT_LEN_6_7,      0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_1,    0},
-};
-
-static const register_write_t display_config_dsi_01_init_06[12] = {
-    {sizeof(uint32_t) * DSI_PHY_TIMING_1,  0x40A0E05},
-    {sizeof(uint32_t) * DSI_PHY_TIMING_2,  0x30109},
-    {sizeof(uint32_t) * DSI_BTA_TIMING,    0x190A14},
-    {sizeof(uint32_t) * DSI_TIMEOUT_0,     DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
-    {sizeof(uint32_t) * DSI_TIMEOUT_1,     DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
-    {sizeof(uint32_t) * DSI_TO_TALLY,      0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
-};
-
-static const register_write_t display_config_dsi_01_init_07[14] = {
-    {sizeof(uint32_t) * DSI_PHY_TIMING_1,        0x40A0E05},
-    {sizeof(uint32_t) * DSI_PHY_TIMING_2,        0x30118},
-    {sizeof(uint32_t) * DSI_BTA_TIMING,          0x190A14},
-    {sizeof(uint32_t) * DSI_TIMEOUT_0,           DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
-    {sizeof(uint32_t) * DSI_TIMEOUT_1,           DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
-    {sizeof(uint32_t) * DSI_TO_TALLY,            0},
-    {sizeof(uint32_t) * DSI_HOST_CONTROL,        DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-    {sizeof(uint32_t) * DSI_CONTROL,             DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL,       DSI_POWER_CONTROL_ENABLE},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL,       DSI_POWER_CONTROL_ENABLE},
-    {sizeof(uint32_t) * DSI_MAX_THRESHOLD,       0x40},
-    {sizeof(uint32_t) * DSI_TRIGGER,             0},
-    {sizeof(uint32_t) * DSI_TX_CRC,              0},
-    {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL,    0},
-};
-
-static const register_write_t display_config_dsi_phy_timing_erista[1] = {
-    {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070601},
-};
-
-static const register_write_t display_config_dsi_phy_timing_mariko[1] = {
-    {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070603},
-};
-
-static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[48] = {
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0xBD15},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x1939},
-    {0, DSI_WR_DATA, 0xAAAAAAD8},
-    {0, DSI_WR_DATA, 0xAAAAAAEB},
-    {0, DSI_WR_DATA, 0xAAEBAAAA},
-    {0, DSI_WR_DATA, 0xAAAAAAAA},
-    {0, DSI_WR_DATA, 0xAAAAAAEB},
-    {0, DSI_WR_DATA, 0xAAEBAAAA},
-    {0, DSI_WR_DATA, 0xAA},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x1BD15},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x2739},
-    {0, DSI_WR_DATA, 0xFFFFFFD8},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFF},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x2BD15},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0xF39},
-    {0, DSI_WR_DATA, 0xFFFFFFD8},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFFFF},
-    {0, DSI_WR_DATA, 0xFFFFFF},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0xBD15},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x6D915},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0xB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x1105},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0xB4, 0},
-    {0, DSI_WR_DATA, 0x2905},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-};
-
-static const dsi_sleep_or_register_write_t display_config_innolux_nx_abca2_specific_init_01[14] = {
-    {0, DSI_WR_DATA, 0x1105},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0xB4, 0},
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0x739},
-    {0, DSI_WR_DATA, 0x751548B1},
-    {0, DSI_WR_DATA, 0x143209},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0x2905},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-};
-
-static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_init_01[14] = {
-    {0, DSI_WR_DATA, 0x1105},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0xB4, 0},
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0x739},
-    {0, DSI_WR_DATA, 0x711148B1},
-    {0, DSI_WR_DATA, 0x143209},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0x2905},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-};
-
-static const dsi_sleep_or_register_write_t display_config_innolux_auo_40_nx_abcc_specific_init_01[5] = {
-    {0, DSI_WR_DATA, 0x1105},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x78, 0},
-    {0, DSI_WR_DATA, 0x2905},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-};
-
-static const dsi_sleep_or_register_write_t display_config_50_nx_abcd_specific_init_01[13] = {
-    {0, DSI_WR_DATA, 0x1105},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0xB4, 0},
-    {0, DSI_WR_DATA, 0xA015},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x205315},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x339},
-    {0, DSI_WR_DATA, 0xFF0751},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0x2905},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-};
-
-static const register_write_t display_config_plld_02_erista[3] = {
-    {CLK_RST_CONTROLLER_PLLD_BASE,        0x4810c001},
-    {CLK_RST_CONTROLLER_PLLD_MISC1,       0x00000020},
-    {CLK_RST_CONTROLLER_PLLD_MISC,        0x002D0AAA},
-};
-
-static const register_write_t display_config_plld_02_mariko[3] = {
-    {CLK_RST_CONTROLLER_PLLD_BASE,        0x4810c001},
-    {CLK_RST_CONTROLLER_PLLD_MISC1,       0x00000000},
-    {CLK_RST_CONTROLLER_PLLD_MISC,        0x002DFC00},
-};
-
-static const register_write_t display_config_dsi_01_init_08[1] = {
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
-};
-
-static const register_write_t display_config_dsi_01_init_09[19] = {
-    {sizeof(uint32_t) * DSI_PHY_TIMING_1,    0x40A0E05},
-    {sizeof(uint32_t) * DSI_PHY_TIMING_2,    0x30172},
-    {sizeof(uint32_t) * DSI_BTA_TIMING,      0x190A14},
-    {sizeof(uint32_t) * DSI_TIMEOUT_0,       DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
-    {sizeof(uint32_t) * DSI_TIMEOUT_1,       DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
-    {sizeof(uint32_t) * DSI_TO_TALLY,        0},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO,    0x40000208},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO,    0x40000308},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO,    0x40000308},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO,    0x40000308},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO,    0x3F3B2B08},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI,    0x2CC},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO,    0x3F3B2B08},
-    {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI,    0x2CC},
-    {sizeof(uint32_t) * DSI_PKT_LEN_0_1,     0xCE0000},
-    {sizeof(uint32_t) * DSI_PKT_LEN_2_3,     0x87001A2},
-    {sizeof(uint32_t) * DSI_PKT_LEN_4_5,     0x190},
-    {sizeof(uint32_t) * DSI_PKT_LEN_6_7,     0x190},
-    {sizeof(uint32_t) * DSI_HOST_CONTROL,    0},
-};
-
-static const register_write_t display_config_dsi_01_init_10[10] = {
-    {sizeof(uint32_t) * DSI_TRIGGER,         0},
-    {sizeof(uint32_t) * DSI_CONTROL,         0},
-    {sizeof(uint32_t) * DSI_SOL_DELAY,       6},
-    {sizeof(uint32_t) * DSI_MAX_THRESHOLD,   0x1E0},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL,   DSI_POWER_CONTROL_ENABLE},
-    {sizeof(uint32_t) * DSI_CONTROL,         DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
-    {sizeof(uint32_t) * DSI_HOST_CONTROL,    DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-    {sizeof(uint32_t) * DSI_CONTROL,         DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
-    {sizeof(uint32_t) * DSI_HOST_CONTROL,    DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-    {sizeof(uint32_t) * DSI_HOST_CONTROL,    DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
-};
-
-static const register_write_t display_config_dsi_01_init_11_erista[4] = {
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0}
-};
-
-static const register_write_t display_config_dsi_01_init_11_mariko[7] = {
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_1,        0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_2,        0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_3,        0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_4,        0x77777},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0x77777},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0},
-};
-
-static const register_write_t display_config_mipi_cal_01[4] = {
-    {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0},
-    {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000},
-    {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 1},
-    {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0},
-};
-
-static const register_write_t display_config_mipi_cal_02_erista[2] = {
-    {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010},
-    {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300},
-};
-
-static const register_write_t display_config_mipi_cal_02_mariko[2] = {
-    {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010},
-    {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0},
-};
-
-static const register_write_t display_config_mipi_cal_03_erista[6] = {
-    {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200},
-    {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200},
-    {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002},
-    {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002},
-    {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0},
-};
-
-static const register_write_t display_config_mipi_cal_03_mariko[6] = {
-    {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006},
-    {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006},
-    {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000},
-    {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000},
-    {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0},
-};
-
-static const register_write_t display_config_mipi_cal_04[10] = {
-    {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0},
-    {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0},
-    {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0},
-    {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0},
-    {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001},
-};
-
-static const register_write_t display_config_dc_02[113] = {
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_CSC_YOF,   0xF0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUR,   0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVR,   0x198},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUG,   0x39B},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVG,   0x32F},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUB,   0x204},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVB,   0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_CSC_YOF,   0xF0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUR,   0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVR,   0x198},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUG,   0x39B},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVG,   0x32F},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUB,   0x204},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVB,   0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_CSC_YOF,   0xF0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUR,   0},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVR,   0x198},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUG,   0x39B},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVG,   0x32F},
-    {sizeof(uint32_t) * DC_WIN_CSC_KUB,   0x204},
-    {sizeof(uint32_t) * DC_WIN_CSC_KVB,   0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
-    {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
-    {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
-    {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0},
-    {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0},
-    {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_TIMING_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_REF_TO_SYNC, (1 << 16)},
-    {sizeof(uint32_t) * DC_DISP_SYNC_WIDTH,  0x10048},
-    {sizeof(uint32_t) * DC_DISP_BACK_PORCH,  0x90048},
-    {sizeof(uint32_t) * DC_DISP_ACTIVE,      0x50002D0},
-    {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
-    {sizeof(uint32_t) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
-    {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_ENABLE(1), 0},
-    {sizeof(uint32_t) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
-    {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
-    {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
-    {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-    {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
-    {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
-};
-
-static const register_write_t display_config_frame_buffer[32] = {
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-    {sizeof(uint32_t) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_WIN_POSITION, 0},
-    {sizeof(uint32_t) * DC_WIN_H_INITIAL_DDA, 0},
-    {sizeof(uint32_t) * DC_WIN_V_INITIAL_DDA, 0},
-    {sizeof(uint32_t) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)},
-    {sizeof(uint32_t) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
-    {sizeof(uint32_t) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
-    {sizeof(uint32_t) * DC_WIN_LINE_STRIDE, 0x6000C00},
-    {sizeof(uint32_t) * DC_WIN_BUFFER_CONTROL, 0},
-    {sizeof(uint32_t) * DC_WINBUF_SURFACE_KIND, 0},
-    {sizeof(uint32_t) * DC_WINBUF_START_ADDR, display_config_frame_buffer_address},
-    {sizeof(uint32_t) * DC_WINBUF_ADDR_H_OFFSET, 0},
-    {sizeof(uint32_t) * DC_WINBUF_ADDR_V_OFFSET, 0},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, WIN_ENABLE},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ},
-};
-
-static const register_write_t display_config_solid_color[8] = {
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
-    {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
-    {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
-};
-
-static const register_write_t display_config_dc_01_fini_01[13] = {
-    {sizeof(uint32_t) * DC_DISP_FRONT_PORCH,        0xA0088},
-    {sizeof(uint32_t) * DC_CMD_INT_MASK,            0},
-    {sizeof(uint32_t) * DC_CMD_STATE_ACCESS,        0},
-    {sizeof(uint32_t) * DC_CMD_INT_ENABLE,          0},
-    {sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC,   0},
-    {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND,     DISP_CTRL_MODE_STOP},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL,       GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL,       GENERAL_ACT_REQ},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL,       GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-    {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL,       GENERAL_UPDATE},
-    {sizeof(uint32_t) * DC_CMD_STATE_CONTROL,       GENERAL_ACT_REQ},
-};
-
-static const register_write_t display_config_dsi_01_fini_01[2] = {
-    {sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
-    {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
-};
-
-static const register_write_t display_config_dsi_01_fini_02[13] = {
-    {sizeof(uint32_t) * DSI_PHY_TIMING_1,      0x40A0E05},
-    {sizeof(uint32_t) * DSI_PHY_TIMING_2,      0x30109},
-    {sizeof(uint32_t) * DSI_BTA_TIMING,        0x190A14},
-    {sizeof(uint32_t) * DSI_TIMEOUT_0,         DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
-    {sizeof(uint32_t) * DSI_TIMEOUT_1,         DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
-    {sizeof(uint32_t) * DSI_TO_TALLY,          0},
-    {sizeof(uint32_t) * DSI_HOST_CONTROL,      DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
-    {sizeof(uint32_t) * DSI_CONTROL,           DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
-    {sizeof(uint32_t) * DSI_POWER_CONTROL,     DSI_POWER_CONTROL_ENABLE},
-    {sizeof(uint32_t) * DSI_MAX_THRESHOLD,     0x40},
-    {sizeof(uint32_t) * DSI_TRIGGER,           0},
-    {sizeof(uint32_t) * DSI_TX_CRC,            0},
-    {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL,  0}
-};
-
-static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[22] = {
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x2139},
-    {0, DSI_WR_DATA, 0x191919D5},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0xB39},
-    {0, DSI_WR_DATA, 0x4F0F41B1},
-    {0, DSI_WR_DATA, 0xF179A433},
-    {0, DSI_WR_DATA, 0x2D81},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0xB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-};
-
-static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_fini_01[38] = {
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x2C39},
-    {0, DSI_WR_DATA, 0x191919D5},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x2C39},
-    {0, DSI_WR_DATA, 0x191919D6},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_WR_DATA, 0x19191919},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0xB39},
-    {0, DSI_WR_DATA, 0x711148B1},
-    {0, DSI_WR_DATA, 0x71143209},
-    {0, DSI_WR_DATA, 0x114D31},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0xB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-};
-
-static const dsi_sleep_or_register_write_t display_config_innolux_nx_abcc_specific_fini_01[10] = {
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0xB39},
-    {0, DSI_WR_DATA, 0x751548B1},
-    {0, DSI_WR_DATA, 0x71143209},
-    {0, DSI_WR_DATA, 0x115631},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-};
-
-static const dsi_sleep_or_register_write_t display_config_auo_nx_abcc_specific_fini_01[10] = {
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0xB39},
-    {0, DSI_WR_DATA, 0x711148B1},
-    {0, DSI_WR_DATA, 0x71143209},
-    {0, DSI_WR_DATA, 0x114D31},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-};
-
-static const dsi_sleep_or_register_write_t display_config_40_nx_abcc_specific_fini_01[10] = {
-    {0, DSI_WR_DATA, 0x439},
-    {0, DSI_WR_DATA, 0x9483FFB9},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-    {0, DSI_WR_DATA, 0xB39},
-    {0, DSI_WR_DATA, 0x731348B1},
-    {0, DSI_WR_DATA, 0x71243209},
-    {0, DSI_WR_DATA, 0x4C31},
-    {0, DSI_TRIGGER, DSI_TRIGGER_HOST},
-    {1, 0x5, 0},
-};

fusee/fusee-primary/fusee-primary-main/src/exception_handlers.c

@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <inttypes.h>
-
-#include "exception_handlers.h"
-#include "utils.h"
-#include "../../../fusee/common/log.h"
-#include "../../../fusee/common/vsprintf.h"
-
-#define CODE_DUMP_SIZE      0x30
-#define STACK_DUMP_SIZE     0x30
-
-extern const uint32_t exception_handler_table[];
-
-static const char *exception_names[] = {
-    "Reset", "Undefined instruction", "SWI", "Prefetch abort", "Data abort", "Reserved", "IRQ", "FIQ",
-};
-
-static const char *register_names[] = {
-    "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "R10", "R11", "R12",
-    "SP", "LR", "PC", "CPSR",
-};
-
-/* Adapted from https://gist.github.com/ccbrown/9722406 */
-static void hexdump(const void* data, size_t size, uintptr_t addrbase, char* strbuf) {
-    const uint8_t *d = (const uint8_t *)data;
-    char ascii[17] = {0};
-    ascii[16] = '\0';
-
-    for (size_t i = 0; i < size; i++) {
-        if (i % 16 == 0) {
-            strbuf += sprintf(strbuf, "%0*" PRIXPTR ": | ", 2 * sizeof(addrbase), addrbase + i);
-        }
-        strbuf += sprintf(strbuf, "%02X ", d[i]);
-        if (d[i] >= ' ' && d[i] <= '~') {
-            ascii[i % 16] = d[i];
-        } else {
-            ascii[i % 16] = '.';
-        }
-        if ((i+1) % 8 == 0 || i+1 == size) {
-            strbuf += sprintf(strbuf, " ");
-            if ((i+1) % 16 == 0) {
-                strbuf += sprintf(strbuf, "|  %s \n", ascii);
-            } else if (i+1 == size) {
-                ascii[(i+1) % 16] = '\0';
-                if ((i+1) % 16 <= 8) {
-                    strbuf += sprintf(strbuf, " ");
-                }
-                for (size_t j = (i+1) % 16; j < 16; j++) {
-                    strbuf += sprintf(strbuf, "   ");
-                }
-                strbuf += sprintf(strbuf, "|  %s \n", ascii);
-            }
-        }
-    }
-}
-
-void setup_exception_handlers(void) {
-    volatile uint32_t *bpmp_exception_handler_table = (volatile uint32_t *)0x6000F200;
-    for (int i = 0; i < 8; i++) {
-        if (exception_handler_table[i] != 0) {
-            bpmp_exception_handler_table[i] = exception_handler_table[i];
-        }
-    } 
-}
-
-void exception_handler_main(uint32_t *registers, unsigned int exception_type) {
-    char exception_log[0x400] = {0};
-    uint8_t code_dump[CODE_DUMP_SIZE] = {0};
-    uint8_t stack_dump[STACK_DUMP_SIZE] = {0};
-    size_t code_dump_size = 0;
-    size_t stack_dump_size = 0;
-
-    uint32_t pc = registers[15];
-    uint32_t cpsr = registers[16];
-    uint32_t instr_addr = pc + ((cpsr & 0x20) ? 2 : 4) - CODE_DUMP_SIZE;
-
-    sprintf(exception_log, "An exception occurred!\n");
-    
-    code_dump_size = safecpy(code_dump, (const void *)instr_addr, CODE_DUMP_SIZE);
-    stack_dump_size = safecpy(stack_dump, (const void *)registers[13], STACK_DUMP_SIZE);
-
-    sprintf(exception_log + strlen(exception_log), "\nException type: %s\n", exception_names[exception_type]);
-    sprintf(exception_log + strlen(exception_log), "\nRegisters:\n");
-
-    /* Print r0 to pc. */
-    for (int i = 0; i < 16; i += 2) {
-        sprintf(exception_log + strlen(exception_log), "%-7s%08"PRIX32"       %-7s%08"PRIX32"\n",
-                register_names[i], registers[i], register_names[i+1], registers[i+1]);
-    }
-
-    /* Print cpsr. */
-    sprintf(exception_log + strlen(exception_log), "%-7s%08"PRIX32"\n", register_names[16], registers[16]);
-    
-    /* Print code and stack regions. */
-    sprintf(exception_log + strlen(exception_log), "\nCode dump:\n");    
-    hexdump(code_dump, code_dump_size, instr_addr, exception_log + strlen(exception_log));
-    sprintf(exception_log + strlen(exception_log), "\nStack dump:\n");
-    hexdump(stack_dump, stack_dump_size, registers[13], exception_log + strlen(exception_log));
-    sprintf(exception_log + strlen(exception_log), "\n");
-    
-    /* Throw fatal error with the full exception log. */
-    fatal_error(exception_log);
-}

fusee/fusee-primary/fusee-primary-main/src/exception_handlers_asm.s

@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-.macro GEN_USUAL_HANDLER name, index, lr_arm_displ, lr_thumb_displ
-    _exception_handler_\name:
-        ldr     sp, =_regs
-        stmia   sp!, {r0-r7}
-
-        /* Adjust lr to make it point to the location where the exception occured. */
-        mrs     r1, spsr
-        tst     r1, #0x20
-        subeq   lr, lr, #\lr_arm_displ
-        subne   lr, lr, #\lr_thumb_displ
-
-        mov     r0, sp
-        mov     r1, #\index
-        b       _exception_handler_common
-.endm
-
-.section    .text.exception_handlers_asm, "ax", %progbits
-.arm
-.align      5
-
-_exception_handler_common:
-    mrs     r2, spsr
-    mrs     r3, cpsr
-
-    /* Mask interrupts. */
-    orr     r3, #0xC0
-    msr     cpsr_cx, r3
-
-    /* Switch to the mode that triggered the interrupt, get the remaining regs, switch back. */
-    ands    r4, r2, #0xF
-    moveq   r4, #0xF             /* usr => sys */
-    bic     r5, r3, #0xF
-    orr     r5, r4
-    msr     cpsr_c, r5
-    stmia   r0!, {r8-lr}
-    msr     cpsr_c, r3
-
-    str     lr, [r0], #4
-    str     r2, [r0]
-
-    /* Finally, switch to system mode, setting interrupts and clearing the flags; set sp as well. */
-    msr     cpsr_cxsf, #0xDF
-    ldr     sp, =(_exception_handler_stack + 0x1000)
-    ldr     r0, =_regs
-    bl      exception_handler_main
-    b       .
-
-GEN_USUAL_HANDLER undefined_instruction, 1, 4, 2
-GEN_USUAL_HANDLER swi, 2, 4, 2
-GEN_USUAL_HANDLER prefetch_abort, 3, 4, 4
-GEN_USUAL_HANDLER data_abort_normal, 4, 8, 8
-GEN_USUAL_HANDLER fiq, 7, 4, 4
-
-_exception_handler_data_abort:
-    /* Mask interrupts (abort mode). */
-    msr     cpsr_cx, #0xD7
-
-    adr     sp, safecpy+8
-    cmp     lr, sp
-    blo     _exception_handler_data_abort_normal
-    adr     sp, _safecpy_end+8
-    cmp     lr, sp
-    bhs     _exception_handler_data_abort_normal
-
-    /* Set the flags, set r12 to 0 for safecpy, return from exception. */
-    msr     spsr_f, #(1 << 30)
-    mov     r12, #0
-    subs    pc, lr, #4
-
-.global safecpy
-.type   safecpy, %function
-safecpy:
-    push    {r4, lr}
-    mov     r3, #0
-    movs    r12, #1
-
-    _safecpy_loop:
-        ldrb    r4, [r1, r3]
-        cmp     r12, #0
-        beq     _safecpy_loop_end
-        strb    r4, [r0, r3]
-        add     r3, #1
-        cmp     r3, r2
-        blo     _safecpy_loop
-
-    _safecpy_loop_end:
-    mov     r0, r3
-    pop     {r4, lr}
-    bx      lr         /* Need to do that separately on ARMv4. */
-
-_safecpy_end:
-
-.section    .rodata.exception_handlers_asm, "a", %progbits
-.align      2
-.global     exception_handler_table
-exception_handler_table:
-    .word   0   /* Reset */
-    .word   _exception_handler_undefined_instruction
-    .word   _exception_handler_swi
-    .word   _exception_handler_prefetch_abort
-    .word   _exception_handler_data_abort
-    .word   0   /* Reserved */
-    .word   0   /* IRQ */
-    .word   _exception_handler_fiq
-
-.section    .bss.exception_handlers_asm, "w", %nobits
-.align      4
-_exception_handler_stack: .skip 0x1000
-_regs: .skip (4 * 17)

fusee/fusee-primary/fusee-primary-main/src/fs_utils.c

@@ -1,139 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "fs_utils.h"
-#include "mc.h"
-#include "../../../fusee/common/fatfs/ff.h"
-#include "../../../fusee/common/log.h"
-
-FATFS sd_fs;
-static bool g_sd_mounted = false;
-static bool g_sd_initialized = false;
-static bool g_ahb_redirect_enabled = false;
-sdmmc_t g_sd_sdmmc;
-sdmmc_device_t g_sd_device;
-
-
-bool mount_sd(void)
-{
-    /* Already mounted. */
-    if (g_sd_mounted)
-        return true;
-
-    /* Enable AHB redirection if necessary. */
-    if (!g_ahb_redirect_enabled) {
-        mc_enable_ahb_redirect();
-        g_ahb_redirect_enabled = true;
-    }
-
-    if (!g_sd_initialized) {
-        /* Initialize SD. */
-        if (sdmmc_device_sd_init(&g_sd_device, &g_sd_sdmmc, SDMMC_BUS_WIDTH_4BIT, SDMMC_SPEED_SD_SDR104))
-        {
-            g_sd_initialized = true;
-
-            /* Mount SD. */
-            if (f_mount(&sd_fs, "", 1) == FR_OK) {
-                print(SCREEN_LOG_LEVEL_INFO, "Mounted SD card!\n");
-                g_sd_mounted = true;
-            }
-        }
-        else
-            fatal_error("Failed to initialize the SD card!.\n");
-    }
-
-    return g_sd_mounted;
-}
-
-void unmount_sd(void)
-{
-    if (g_sd_mounted)
-    {
-        f_mount(NULL, "", 1);
-        sdmmc_device_finish(&g_sd_device);
-        g_sd_mounted = false;
-    }
-
-    /* Disable AHB redirection if necessary. */
-    if (g_ahb_redirect_enabled) {
-        mc_disable_ahb_redirect();
-        g_ahb_redirect_enabled = false;
-    }
-}
-
-uint32_t get_file_size(const char *filename)
-{
-    /* SD card hasn't been mounted yet. */
-    if (!g_sd_mounted)
-        return 0;
-
-    /* Open the file for reading. */
-    FIL f;
-    if (f_open(&f, filename, FA_READ) != FR_OK)
-        return 0;
-
-    /* Get the file size. */
-    uint32_t file_size = f_size(&f);
-
-    /* Close the file. */
-    f_close(&f);
-
-    return file_size;
-}
-
-int read_from_file(void *dst, uint32_t dst_size, const char *filename)
-{
-    /* SD card hasn't been mounted yet. */
-    if (!g_sd_mounted)
-        return 0;
-
-    /* Open the file for reading. */
-    FIL f;
-    if (f_open(&f, filename, FA_READ) != FR_OK)
-        return 0;
-
-    /* Sync. */
-    f_sync(&f);
-
-    /* Read from file. */
-    UINT br = 0;
-    int res = f_read(&f, dst, dst_size, &br);
-    f_close(&f);
-
-    return (res == FR_OK) ? (int)br : 0;
-}
-
-int write_to_file(void *src, uint32_t src_size, const char *filename)
-{
-    /* SD card hasn't been mounted yet. */
-    if (!g_sd_mounted)
-        return 0;
-
-    /* Open the file for writing. */
-    FIL f;
-    if (f_open(&f, filename, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK)
-        return 0;
-
-    /* Sync. */
-    f_sync(&f);
-
-    /* Write to file. */
-    UINT bw = 0;
-    int res = f_write(&f, src, src_size, &bw);
-    f_close(&f);
-
-    return (res == FR_OK) ? (int)bw : 0;
-}

fusee/fusee-primary/fusee-primary-main/src/fuse.c

@@ -1,346 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-#include <vapours/ams_version.h>
-
-#include "car.h"
-#include "fuse.h"
-#include "pmc.h"
-#include "timers.h"
-
-/* Initialize the fuse driver */
-void fuse_init(void) {
-    /* Make all fuse registers visible, disable the private key and disable programming. */
-    clkrst_enable_fuse_regs(true);
-    fuse_disable_private_key();
-    fuse_disable_programming();
-}
-
-/* Disable access to the private key and set the TZ sticky bit. */
-void fuse_disable_private_key(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
-}
-
-/* Disable all fuse programming. */
-void fuse_disable_programming(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    fuse->FUSE_DISABLEREGPROGRAM = 1;
-}
-
-/* Enable power to the fuse hardware array. */
-void fuse_enable_power(void) {
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    pmc->fuse_control &= ~(0x200);      /* Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
-    mdelay(1);
-    pmc->fuse_control |= 0x100;         /* Set PMC_FUSE_CTRL_PS18_LATCH_SET. */
-    mdelay(1);
-}
-
-/* Disable power to the fuse hardware array. */
-void fuse_disable_power(void) {
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    pmc->fuse_control &= ~(0x100);      /* Clear PMC_FUSE_CTRL_PS18_LATCH_SET. */
-    mdelay(1);
-    pmc->fuse_control |= 0x200;         /* Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
-    mdelay(1);
-}
-
-/* Wait for the fuse driver to go idle. */
-static void fuse_wait_idle(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    uint32_t ctrl_val = 0;
-
-    /* Wait for STATE_IDLE */
-    while ((ctrl_val & (0xF0000)) != 0x40000) {
-        ctrl_val = fuse->FUSE_FUSECTRL;
-    }
-}
-
-/* Read a fuse from the hardware array. */
-uint32_t fuse_hw_read(uint32_t addr) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Program the target address. */
-    fuse->FUSE_FUSEADDR = addr;
-
-    /* Enable read operation in control register. */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x1;    /* Set READ command. */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    return fuse->FUSE_FUSERDATA;
-}
-
-/* Write a fuse in the hardware array. */
-void fuse_hw_write(uint32_t value, uint32_t addr) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Program the target address and value. */
-    fuse->FUSE_FUSEADDR = addr;
-    fuse->FUSE_FUSEWDATA = value;
-
-    /* Enable write operation in control register. */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x2;    /* Set WRITE command. */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-}
-
-/* Sense the fuse hardware array into the fuse cache. */
-void fuse_hw_sense(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Enable sense operation in control register */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x3;    /* Set SENSE_CTRL command */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-}
-
-/* Read the SKU info register. */
-uint32_t fuse_get_sku_info(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    return fuse_chip->FUSE_SKU_INFO;
-}
-
-/* Read the bootrom patch version. */
-uint32_t fuse_get_bootrom_patch_version(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
-}
-
-/* Read a spare bit register. */
-uint32_t fuse_get_spare_bit(uint32_t index) {
-    uint32_t soc_type = fuse_get_soc_type();
-    if (soc_type == 0) {
-        if (index < 32) {
-            volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs();
-            return fuse_chip->FUSE_SPARE_BIT[index];
-        }
-    } else if (soc_type == 1) {
-        if (index < 30) {
-            volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
-            return fuse_chip->FUSE_SPARE_BIT[index];
-        }
-    }
-    return 0;
-}
-
-/* Read a reserved ODM register. */
-uint32_t fuse_get_reserved_odm(uint32_t index) {
-    if (index < 8) {
-        volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-        return fuse_chip->FUSE_RESERVED_ODM0[index];
-    } else {
-        uint32_t soc_type = fuse_get_soc_type();
-        if (soc_type == 1) {
-            volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
-            if (index < 22) {
-                return fuse_chip->FUSE_RESERVED_ODM8[index - 8];
-            } else if (index < 25) {
-                return fuse_chip->FUSE_RESERVED_ODM22[index - 22];
-            } else if (index < 26) {
-                return fuse_chip->FUSE_RESERVED_ODM25;
-            } else if (index < 29) {
-                return fuse_chip->FUSE_RESERVED_ODM26[index - 26];
-            } else if (index < 30) {
-                return fuse_chip->FUSE_RESERVED_ODM29;
-            }
-        }
-    }
-    return 0;
-}
-
-/* Get the DramId. */
-uint32_t fuse_get_dram_id(void) {
-    return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
-}
-
-/* Derive the DeviceId. */
-uint64_t fuse_get_device_id(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-
-    uint64_t device_id = 0;
-    uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
-    uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
-    uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
-    uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0;
-    uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
-
-    uint64_t derived_lot_code = 0;
-    for (unsigned int i = 0; i < 5; i++) {
-        derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
-    }
-    derived_lot_code &= 0x03FFFFFF;
-
-    device_id |= y_coord << 0;
-    device_id |= x_coord << 9;
-    device_id |= wafer_id << 18;
-    device_id |= derived_lot_code << 24;
-    device_id |= fab_code << 50;
-
-    return device_id;
-}
-
-/* Derive the HardwareType with firmware specific checks. */
-uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) {
-    uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
-    uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
-
-    if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) {
-        volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-        uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1);
-
-        switch (hardware_type) {
-            case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3;
-            case 0x01: return 0;        /* HardwareType_Icosa */
-            case 0x02: return 1;        /* HardwareType_Copper */
-            default:   return 3;        /* HardwareType_Undefined */
-        }
-    } else {
-        hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
-
-        if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
-            switch (hardware_type) {
-                case 0x01: return 0;        /* HardwareType_Icosa */
-                case 0x02: return 1;        /* HardwareType_Copper */
-                case 0x04: return 3;        /* HardwareType_Iowa */
-                default:   return 4;        /* HardwareType_Undefined */
-            }
-        } else {
-            if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) {
-                switch (hardware_type) {
-                    case 0x01: return 0;        /* HardwareType_Icosa */
-                    case 0x02: return 4;        /* HardwareType_Calcio */
-                    case 0x04: return 3;        /* HardwareType_Iowa */
-                    case 0x08: return 2;        /* HardwareType_Hoag */
-                    default:   return 0xF;      /* HardwareType_Undefined */
-                }
-            } else {
-                switch (hardware_type) {
-                    case 0x01: return 0;        /* HardwareType_Icosa */
-                    case 0x02: return 4;        /* HardwareType_Calcio */
-                    case 0x04: return 3;        /* HardwareType_Iowa */
-                    case 0x08: return 2;        /* HardwareType_Hoag */
-                    case 0x10: return 5;        /* HardwareType_Five */
-                    default:   return 0xF;      /* HardwareType_Undefined */
-                }
-            }
-        }
-    }
-}
-
-/* Derive the HardwareType. */
-uint32_t fuse_get_hardware_type(void) {
-    return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT);
-}
-
-/* Derive the HardwareState. */
-uint32_t fuse_get_hardware_state(void) {
-    uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
-    uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
-
-    switch (hardware_state) {
-        case 0x03: return 0;        /* HardwareState_Development */
-        case 0x04: return 1;        /* HardwareState_Production */
-        default:   return 2;        /* HardwareState_Undefined */
-    }
-}
-
-/* Derive the 16-byte HardwareInfo and copy to output buffer. */
-void fuse_get_hardware_info(void *dst) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    uint32_t hw_info[0x4];
-
-    uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
-    uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
-    uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
-    uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
-    uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0;
-    uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF;
-    uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
-    uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF;
-
-    /* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
-    hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved));
-    hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
-    hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
-    hw_info[3] = (uint32_t)(vendor_code);
-
-    memcpy(dst, hw_info, 0x10);
-}
-
-/* Check if have a new ODM fuse format. */
-bool fuse_is_new_format(void) {
-    return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2));
-}
-
-/* Get the DeviceUniqueKeyGeneration. */
-uint32_t fuse_get_device_unique_key_generation(void) {
-    if (fuse_is_new_format()) {
-        return (fuse_get_reserved_odm(2) & 0x1F);
-    } else {
-        return 0;
-    }
-}
-
-/* Get the SocType from the HardwareType. */
-uint32_t fuse_get_soc_type(void) {
-    switch (fuse_get_hardware_type()) {
-        case 0:
-        case 1:
-            return 0;           /* SocType_Erista */
-        case 3:
-        case 2:
-        case 4:
-        case 5:
-            return 1;           /* SocType_Mariko */
-        default:
-            return 0xF;         /* SocType_Undefined */
-    }
-}
-
-/* Get the Regulator type. */
-uint32_t fuse_get_regulator(void) {
-    if (fuse_get_soc_type() == 1) {
-        return ((fuse_get_reserved_odm(28) & 1) + 1);   /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */
-    } else {
-        return 0;               /* Regulator_Erista_Max77621 */
-    }
-}

fusee/fusee-primary/fusee-primary-main/src/fuse.h

@@ -1,484 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_FUSE_H
-#define FUSEE_FUSE_H
-
-#define FUSE_BASE 0x7000F800
-#define FUSE_CHIP_BASE (FUSE_BASE + 0x98)
-#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
-#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
-
-typedef struct {
-    uint32_t FUSE_FUSECTRL;
-    uint32_t FUSE_FUSEADDR;
-    uint32_t FUSE_FUSERDATA;
-    uint32_t FUSE_FUSEWDATA;
-    uint32_t FUSE_FUSETIME_RD1;
-    uint32_t FUSE_FUSETIME_RD2;
-    uint32_t FUSE_FUSETIME_PGM1;
-    uint32_t FUSE_FUSETIME_PGM2;
-    uint32_t FUSE_PRIV2INTFC_START;
-    uint32_t FUSE_FUSEBYPASS;
-    uint32_t FUSE_PRIVATEKEYDISABLE;
-    uint32_t FUSE_DISABLEREGPROGRAM;
-    uint32_t FUSE_WRITE_ACCESS_SW;
-    uint32_t FUSE_PWR_GOOD_SW;
-    uint32_t _0x38;
-    uint32_t FUSE_PRIV2RESHIFT;
-    uint32_t _0x40[0x3];
-    uint32_t FUSE_FUSETIME_RD3;
-    uint32_t _0x50[0xC];
-    uint32_t FUSE_PRIVATE_KEY0_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY1_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY2_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY3_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY4_NONZERO;
-    uint32_t _0x94;
-} tegra_fuse_t;
-
-typedef struct {
-    uint32_t _0x98[0x1A];
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t _0x11C[0x3];
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t _0x144;
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t _0x18C;
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t _0x224;
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t _0x238[0x3];
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t _0x268[0x5];
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t _0x294;
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC[0x5];
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t _0x324[0x5];
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x20];
-} tegra_fuse_chip_common_t;
-
-typedef struct {
-    uint32_t _0x98[0x1A];
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t _0x11C[0x3];
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t _0x144;
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t _0x18C;
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t FUSE_SATA_CALIB;               /* Erista only. */
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t _0x238[0x3];
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t FUSE_PKC_DISABLE;              /* Erista only. */
-    uint32_t _0x26C[0x4];
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t _0x294;
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC[0x5];
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t FUSE_OPT_RAM_SVOP_DP;          /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_PDP;         /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_REG;         /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_SP;          /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_SMPDP;       /* Erista only. */
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x20];
-} tegra_fuse_chip_erista_t;
-
-typedef struct {
-    uint32_t FUSE_RESERVED_ODM8[0xE];       /* Mariko only. */
-    uint32_t FUSE_KEK[0x4];                 /* Mariko only. */
-    uint32_t FUSE_BEK[0x4];                 /* Mariko only. */
-    uint32_t _0xF0;                         /* Mariko only. */
-    uint32_t _0xF4;                         /* Mariko only. */
-    uint32_t _0xF8;                         /* Mariko only. */
-    uint32_t _0xFC;                         /* Mariko only. */
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t FUSE_RESERVED_ODM22[0x3];      /* Mariko only. */
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t FUSE_RESERVED_ODM25;           /* Mariko only. */
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t FUSE_OPT_SECURE_SCC_DIS;       /* Mariko only. */
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;                        /* Mariko only. */
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t _0x224;                        /* Mariko only. */
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t FUSE_RESERVED_ODM26[0x3];      /* Mariko only. */
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t FUSE_BOOT_SECURITY_INFO;       /* Mariko only. */
-    uint32_t _0x26C;                        /* Mariko only. */
-    uint32_t _0x270;                        /* Mariko only. */
-    uint32_t _0x274;                        /* Mariko only. */
-    uint32_t _0x278;                        /* Mariko only. */
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t FUSE_RESERVED_ODM29;           /* Mariko only. */
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC;
-    uint32_t _0x2B0;                        /* Mariko only. */
-    uint32_t _0x2B4;                        /* Mariko only. */
-    uint32_t _0x2B8;                        /* Mariko only. */
-    uint32_t _0x2BC;                        /* Mariko only. */
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t _0x324;                        /* Mariko only. */
-    uint32_t _0x328;                        /* Mariko only. */
-    uint32_t _0x32C;                        /* Mariko only. */
-    uint32_t _0x330;                        /* Mariko only. */
-    uint32_t _0x334;                        /* Mariko only. */
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x1E];
-} tegra_fuse_chip_mariko_t;
-
-static inline volatile tegra_fuse_t *fuse_get_regs(void)
-{
-    return (volatile tegra_fuse_t *)FUSE_BASE;
-}
-
-static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE;
-}
-
-static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE;
-}
-
-static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE;
-}
-
-void fuse_init(void);
-void fuse_disable_programming(void);
-void fuse_disable_private_key(void);
-void fuse_enable_power(void);
-void fuse_disable_power(void);
-
-uint32_t fuse_get_sku_info(void);
-uint32_t fuse_get_spare_bit(uint32_t index);
-uint32_t fuse_get_reserved_odm(uint32_t index);
-uint32_t fuse_get_bootrom_patch_version(void);
-uint64_t fuse_get_device_id(void);
-uint32_t fuse_get_dram_id(void);
-uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
-uint32_t fuse_get_hardware_type(void);
-uint32_t fuse_get_retail_type(void);
-void fuse_get_hardware_info(void *dst);
-bool fuse_is_new_format(void);
-uint32_t fuse_get_device_unique_key_generation(void);
-uint32_t fuse_get_soc_type(void);
-uint32_t fuse_get_regulator(void);
-
-uint32_t fuse_hw_read(uint32_t addr);
-void fuse_hw_write(uint32_t value, uint32_t addr);
-void fuse_hw_sense(void);
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/gpio.c

@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <string.h>
-#include <stdint.h>
-#include <errno.h>
-
-#include "gpio.h"
-#include "utils.h"
-
-/* Set GPIO's value. */
-static void gpio_register_set(uint32_t pin, bool do_set, uint32_t offset) {
-    volatile tegra_gpio_t *gpio = gpio_get_regs();
-    
-    /* Retrieve the register set that corresponds to the given pin and offset. */
-    volatile uint32_t *cluster = (uint32_t *)((uintptr_t)&gpio->bank[(pin >> GPIO_BANK_SHIFT)] + offset);
-
-    /* Figure out the offset into the cluster, and the mask to be used. */
-    uint32_t port = ((pin >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK);
-    uint32_t mask = (1 << (pin & GPIO_PIN_MASK));
-
-    /* Set or clear the bit, as appropriate. */
-    if (do_set)
-        cluster[port] |= mask;
-    else
-        cluster[port] &= ~mask;
-    
-    /* Dummy read. */
-    cluster[port];
-}
-
-/* Get GPIO's value. */
-static bool gpio_register_get(uint32_t pin, uint32_t offset) {
-    volatile tegra_gpio_t *gpio = gpio_get_regs();
-    
-    /* Retrieve the register set that corresponds to the given pin and offset. */
-    volatile uint32_t *cluster = (uint32_t *)((uintptr_t)&gpio->bank[(pin >> GPIO_BANK_SHIFT)] + offset);
-
-    /* Figure out the offset into the cluster, and the mask to be used. */
-    uint32_t port = ((pin >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK);
-    uint32_t mask = (1 << (pin & GPIO_PIN_MASK));
-
-    /* Convert the given value to a boolean. */
-    return !!(cluster[port] & mask);
-}
-
-/* Configure GPIO's mode. */
-void gpio_configure_mode(uint32_t pin, uint32_t mode) {
-    gpio_register_set(pin, mode == GPIO_MODE_GPIO, offsetof(tegra_gpio_bank_t, config));
-}
-
-/* Configure GPIO's direction. */
-void gpio_configure_direction(uint32_t pin, uint32_t dir) {
-    gpio_register_set(pin, dir == GPIO_DIRECTION_OUTPUT, offsetof(tegra_gpio_bank_t, direction)); 
-}
-
-/* Write to GPIO. */
-void gpio_write(uint32_t pin, uint32_t value) {
-    gpio_register_set(pin, value == GPIO_LEVEL_HIGH, offsetof(tegra_gpio_bank_t, out)); 
-}
-
-/* Read from GPIO. */
-uint32_t gpio_read(uint32_t pin) {
-    return gpio_register_get(pin, offsetof(tegra_gpio_bank_t, in)); 
-}

fusee/fusee-primary/fusee-primary-main/src/gpio.h

@@ -1,127 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_GPIO_H
-#define FUSEE_GPIO_H
-
-#include <stdint.h>
-
-#define GPIO_BASE  0x6000D000
-#define MAKE_GPIO_REG(n) MAKE_REG32(GPIO_BASE + n)
-
-#define TEGRA_GPIO_PORTS        4
-#define TEGRA_GPIO_BANKS        8
-#define GPIO_BANK_SHIFT         5  
-#define GPIO_PORT_SHIFT         3
-#define GPIO_PORT_MASK          0x03
-#define GPIO_PIN_MASK           0x07
-    
-typedef enum {
-    TEGRA_GPIO_PORT_A = 0,
-    TEGRA_GPIO_PORT_B = 1,
-    TEGRA_GPIO_PORT_C = 2,
-    TEGRA_GPIO_PORT_D = 3,
-    TEGRA_GPIO_PORT_E = 4,
-    TEGRA_GPIO_PORT_F = 5,
-    TEGRA_GPIO_PORT_G = 6,
-    TEGRA_GPIO_PORT_H = 7,
-    TEGRA_GPIO_PORT_I = 8,
-    TEGRA_GPIO_PORT_J = 9,
-    TEGRA_GPIO_PORT_K = 10,
-    TEGRA_GPIO_PORT_L = 11,
-    TEGRA_GPIO_PORT_M = 12,
-    TEGRA_GPIO_PORT_N = 13,
-    TEGRA_GPIO_PORT_O = 14,
-    TEGRA_GPIO_PORT_P = 15,
-    TEGRA_GPIO_PORT_Q = 16,
-    TEGRA_GPIO_PORT_R = 17,
-    TEGRA_GPIO_PORT_S = 18,
-    TEGRA_GPIO_PORT_T = 19,
-    TEGRA_GPIO_PORT_U = 20,
-    TEGRA_GPIO_PORT_V = 21,
-    TEGRA_GPIO_PORT_W = 22,
-    TEGRA_GPIO_PORT_X = 23,
-    TEGRA_GPIO_PORT_Y = 24,
-    TEGRA_GPIO_PORT_Z = 25,
-    TEGRA_GPIO_PORT_AA = 26,
-    TEGRA_GPIO_PORT_BB = 27,
-    TEGRA_GPIO_PORT_CC = 28,
-    TEGRA_GPIO_PORT_DD = 29,
-    TEGRA_GPIO_PORT_EE = 30,
-    TEGRA_GPIO_PORT_FF = 31,
-} tegra_gpio_port;
-
-typedef struct {
-    uint32_t config[TEGRA_GPIO_PORTS];
-    uint32_t direction[TEGRA_GPIO_PORTS];
-    uint32_t out[TEGRA_GPIO_PORTS];
-    uint32_t in[TEGRA_GPIO_PORTS];
-    uint32_t int_status[TEGRA_GPIO_PORTS];
-    uint32_t int_enable[TEGRA_GPIO_PORTS];
-    uint32_t int_level[TEGRA_GPIO_PORTS];
-    uint32_t int_clear[TEGRA_GPIO_PORTS];
-    uint32_t masked_config[TEGRA_GPIO_PORTS];
-    uint32_t masked_dir_out[TEGRA_GPIO_PORTS];
-    uint32_t masked_out[TEGRA_GPIO_PORTS];
-    uint32_t masked_in[TEGRA_GPIO_PORTS];
-    uint32_t masked_int_status[TEGRA_GPIO_PORTS];
-    uint32_t masked_int_enable[TEGRA_GPIO_PORTS];
-    uint32_t masked_int_level[TEGRA_GPIO_PORTS];
-    uint32_t masked_int_clear[TEGRA_GPIO_PORTS];
-} tegra_gpio_bank_t;
-
-typedef struct {
-    tegra_gpio_bank_t bank[TEGRA_GPIO_BANKS];
-} tegra_gpio_t;
-
-static inline volatile tegra_gpio_t *gpio_get_regs(void)
-{
-    return (volatile tegra_gpio_t *)GPIO_BASE;
-}
-
-#define TEGRA_GPIO(port, offset) \
-    ((TEGRA_GPIO_PORT_##port * 8) + offset)
-
-/* Mode select */
-#define GPIO_MODE_SFIO          0
-#define GPIO_MODE_GPIO          1
-
-/* Direction */
-#define GPIO_DIRECTION_INPUT    0
-#define GPIO_DIRECTION_OUTPUT   1
-
-/* Level */
-#define GPIO_LEVEL_LOW          0
-#define GPIO_LEVEL_HIGH         1
-
-/* Named GPIOs */
-#define GPIO_BUTTON_VOL_DOWN            TEGRA_GPIO(X, 7)
-#define GPIO_BUTTON_VOL_UP              TEGRA_GPIO(X, 6)
-#define GPIO_MICROSD_CARD_DETECT        TEGRA_GPIO(Z, 1)
-#define GPIO_MICROSD_WRITE_PROTECT      TEGRA_GPIO(Z, 4)
-#define GPIO_MICROSD_SUPPLY_ENABLE      TEGRA_GPIO(E, 4)
-#define GPIO_LCD_BL_P5V                 TEGRA_GPIO(I, 0)
-#define GPIO_LCD_BL_N5V                 TEGRA_GPIO(I, 1)
-#define GPIO_LCD_BL_PWM                 TEGRA_GPIO(V, 0)
-#define GPIO_LCD_BL_EN                  TEGRA_GPIO(V, 1)
-#define GPIO_LCD_BL_RST                 TEGRA_GPIO(V, 2)
-
-void gpio_configure_mode(uint32_t pin, uint32_t mode);
-void gpio_configure_direction(uint32_t pin, uint32_t dir);
-void gpio_write(uint32_t pin, uint32_t value);
-uint32_t gpio_read(uint32_t pin);
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/hwinit.c

@@ -1,319 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "hwinit.h"
-#include "apb_misc.h"
-#include "car.h"
-#include "di.h"
-#include "fuse.h"
-#include "gpio.h"
-#include "i2c.h"
-#include "max77620.h"
-#include "mc.h"
-#include "pinmux.h"
-#include "pmc.h"
-#include "se.h"
-#include "sdram.h"
-#include "sysctr0.h"
-#include "sysreg.h"
-#include "timers.h"
-#include "uart.h"
-
-/* Determine the current SoC for Mariko specific code. */
-static bool is_soc_mariko() {
-    return (fuse_get_soc_type() == 1);
-}
-
-static void config_oscillators(void) {
-    volatile tegra_car_t *car = car_get_regs();
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-
-    car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
-
-    SYSCTR0_CNTFID0_0 = 19200000;
-    TIMERUS_USEC_CFG_0 = 0x45F;
-
-    car->osc_ctrl = 0x50000071;
-    pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);
-    pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000);
-    pmc->cntrl2 = ((pmc->cntrl2 & 0xFFFFEFFF) | 0x1000);
-    pmc->scratch188 = ((pmc->scratch188 & 0xFCFFFFFF) | 0x2000000);
-    car->clk_sys_rate = 0x10;
-    car->pllmb_base &= 0xBFFFFFFF;
-    pmc->tsc_mult = ((pmc->tsc_mult & 0xFFFF0000) | 0x249F);      /* 0x249F = 19200000 * (16 / 32.768 kHz) */
-    car->sclk_brst_pol = 0x20004444;
-    car->super_sclk_div = 0x80000000;
-    car->clk_sys_rate = 2;
-}
-
-static void config_gpios(void) {
-    volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
-
-    /* NOTE: This is also not done for calcio/copper. */
-    if (fuse_get_hardware_type() != 2) {
-        pinmux->uart2_tx = 0;
-        pinmux->uart3_tx = 0;
-        gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO);
-        gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO);
-        gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT);
-        gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT);
-    }
-
-    pinmux->pe6 = PINMUX_INPUT;
-    pinmux->ph6 = PINMUX_INPUT;
-    gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO);
-    gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO);
-    gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT);
-    gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT);
-
-    i2c_config(I2C_1);
-    i2c_config(I2C_5);
-    uart_config(UART_A);
-
-    /* Configure volume up/down buttons as inputs. */
-    gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO);
-    gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
-    gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
-    gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
-
-    /* Configure home button as input. */
-    gpio_configure_mode(TEGRA_GPIO(Y, 1), GPIO_MODE_GPIO);
-    gpio_configure_direction(TEGRA_GPIO(Y, 1), GPIO_DIRECTION_INPUT);
-}
-
-static void mbist_workaround(void) {
-    volatile tegra_car_t *car = car_get_regs();
-
-    car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
-    car->plld_base |= 0x40800000u;
-    car->rst_dev_y_clr = 0x40;
-    car->rst_dev_x_clr = 0x40000;
-    car->rst_dev_l_clr = 0x18000000;
-    udelay(2);
-
-    /* Setup I2S. */
-    MAKE_I2S_REG(0x0A0) |= 0x400;
-    MAKE_I2S_REG(0x088) &= 0xFFFFFFFE;
-    MAKE_I2S_REG(0x1A0) |= 0x400;
-    MAKE_I2S_REG(0x188) &= 0xFFFFFFFE;
-    MAKE_I2S_REG(0x2A0) |= 0x400;
-    MAKE_I2S_REG(0x288) &= 0xFFFFFFFE;
-    MAKE_I2S_REG(0x3A0) |= 0x400;
-    MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
-    MAKE_I2S_REG(0x4A0) |= 0x400;
-    MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
-
-    MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
-    MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
-    udelay(2);
-
-    /* Set devices in reset. */
-    car->rst_dev_y_set = 0x40;
-    car->rst_dev_l_set = 0x18000000;
-    car->rst_dev_x_set = 0x40000;
-
-    /* Clock out enables. */
-    car->clk_out_enb_h = 0xC0;
-    car->clk_out_enb_l = 0x80000130;
-    car->clk_out_enb_u = 0x1F00200;
-    car->clk_out_enb_v = 0x80400808;
-    car->clk_out_enb_w = 0x402000FC;
-    car->clk_out_enb_x = 0x23000780;
-    car->clk_out_enb_y = 0x300;
-
-    /* LVL2 clock gate overrides. */
-    car->lvl2_clk_gate_ovra = 0;
-    car->lvl2_clk_gate_ovrb = 0;
-    car->lvl2_clk_gate_ovrc = 0;
-    car->lvl2_clk_gate_ovrd = 0;
-    car->lvl2_clk_gate_ovre = 0;
-
-    /* Configure clock sources. */
-    car->plld_base &= 0x1F7FFFFF;
-    car->clk_source_sor1 &= 0xFFFF3FFF;
-    car->clk_source_vi = ((car->clk_source_vi & 0x1FFFFFFF) | 0x80000000);
-    car->clk_source_host1x = ((car->clk_source_host1x & 0x1FFFFFFF) | 0x80000000);
-    car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000);
-}
-
-static void config_se_brom(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    volatile tegra_se_t *se = se_get_regs();
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-
-    /* Bootrom part we skipped. */
-    uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]};
-    for (int i = 0; i < 4; ++i) {
-        if (sbk[i] != 0xFFFFFFFF) {
-            set_aes_keyslot(0xE, sbk, 0x10);
-            break;
-        }
-    }
-
-    /* Lock SBK from being read. */
-    se->SE_CRYPTO_KEYTABLE_ACCESS[0xE] = 0x7E;
-
-    /* This memset needs to happen here, else TZRAM will behave weirdly later on. */
-    memset((void *)0x7C010000, 0, 0x10000);
-
-    pmc->crypto_op = 0;
-    se->SE_INT_STATUS = 0x1F;
-
-    /* Lock SSK (although it's not set and unused anyways). */
-    se->SE_CRYPTO_KEYTABLE_ACCESS[0xF] = 0x7E;
-
-    /* Clear the boot reason to avoid problems later */
-    pmc->scratch200 = 0;
-    pmc->rst_status = 0;
-}
-
-void nx_hwinit(bool enable_log) {
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    volatile tegra_car_t *car = car_get_regs();
-    bool is_mariko = is_soc_mariko();
-
-    if (!is_mariko) {
-        /* Bootrom stuff we skipped by going through RCM. */
-        config_se_brom();
-
-        AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
-        pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
-
-        /* Apply the memory built-in self test workaround. */
-        mbist_workaround();
-    }
-
-    /* Enable SE clock. */
-    clkrst_reboot(CARDEVICE_SE);
-    if (is_mariko) {
-        /* Lock the SE clock. */
-        car->clk_source_se |= 0x100;
-    }
-
-    /* Initialize the fuse driver. */
-    fuse_init();
-
-    if (!is_mariko) {
-        /* Initialize the memory controller. */
-        mc_enable();
-    }
-
-    /* Configure oscillators. */
-    config_oscillators();
-
-    /* Disable pinmux tristate input clamping. */
-    APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
-
-    /* Configure GPIOs. */
-    config_gpios();
-
-    /* UART debugging. */
-    if (enable_log) {
-        clkrst_reboot(CARDEVICE_UARTA);
-        uart_init(UART_A, 115200);
-    }
-
-    /* Enable CL-DVFS clock. */
-    clkrst_reboot(CARDEVICE_CL_DVFS);
-
-    /* Enable I2C1 clock. */
-    clkrst_reboot(CARDEVICE_I2C1);
-
-    /* Enable I2C5 clock. */
-    clkrst_reboot(CARDEVICE_I2C5);
-
-    /* Enable TZRAM clock. */
-    clkrst_reboot(CARDEVICE_TZRAM);
-
-    /* Initialize I2C5. */
-    i2c_init(I2C_5);
-
-    /* Configure the PMIC. */
-    if (is_mariko) {
-        uint8_t val = 0x40;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
-        val = 0x78;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
-    } else {
-        uint8_t val = 0x40;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
-        val = 0x58;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
-        val = 0x38;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1);
-        val = 0x3A;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG1, &val, 1);
-        val = 0x38;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG2, &val, 1);
-        val = 0xF;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO4, &val, 1);
-        val = 0xC7;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO8, &val, 1);
-        val = 0x4F;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD0, &val, 1);
-        val = 0x29;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
-        val = 0x1B;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
-
-        /* NOTE: [3.0.0+] This was added. */
-        val = 0x22;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
-
-        /* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
-        /*
-        i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
-        val |= 0x40;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
-        */
-    }
-
-    /* Configure SD0 voltage as 1.125v for erista, 1.050v for mariko. */
-    if (is_mariko) {
-        uint8_t val = 0x24;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
-    } else {
-        uint8_t val = 0x2A;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
-    }
-
-    /* Enable LDO8 in HardwareType_Hoag only. */
-    if (fuse_get_hardware_type() == 2) {
-        uint8_t val = 0xE8;
-        i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO8_CFG, &val, 1);
-    }
-
-    /* Initialize I2C1. */
-    i2c_init(I2C_1);
-
-    /* Set super clock burst policy. */
-    car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
-
-    if (is_mariko) {
-        /* Mariko only PMC configuration for TZRAM. */
-        pmc->tzram_pwr_cntrl &= 0xFFFFFFFE;
-        pmc->tzram_non_sec_disable = 0x3;
-        pmc->tzram_sec_disable = 0x3;
-    }
-
-    /* Save SDRAM parameters to scratch. */
-    sdram_save_params(sdram_get_params(fuse_get_dram_id()));
-
-    /* Initialize SDRAM. */
-    sdram_init();
-}

fusee/fusee-primary/fusee-primary-main/src/i2c.c

@@ -1,252 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "i2c.h"
-#include "utils.h"
-#include "timers.h"
-#include "pinmux.h"
-
-/* Prototypes for internal commands. */
-volatile tegra_i2c_t *i2c_get_registers_from_id(I2CDevice id);
-void i2c_load_config(volatile tegra_i2c_t *regs);
-
-bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size);
-bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size);
-
-bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size);
-bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size);
-
-/* Configure I2C pinmux. */
-void i2c_config(I2CDevice id) {
-    volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
-    
-    switch (id) {
-        case I2C_1:
-            pinmux->gen1_i2c_scl = PINMUX_INPUT;
-            pinmux->gen1_i2c_sda = PINMUX_INPUT;
-            break;
-        case I2C_2:
-            pinmux->gen2_i2c_scl = PINMUX_INPUT;
-            pinmux->gen2_i2c_sda = PINMUX_INPUT;
-            break;
-        case I2C_3:
-            pinmux->gen3_i2c_scl = PINMUX_INPUT;
-            pinmux->gen3_i2c_sda = PINMUX_INPUT;
-            break;
-        case I2C_4:
-            pinmux->cam_i2c_scl = PINMUX_INPUT;
-            pinmux->cam_i2c_sda = PINMUX_INPUT;
-            break;
-        case I2C_5:
-            pinmux->pwr_i2c_scl = PINMUX_INPUT;
-            pinmux->pwr_i2c_sda = PINMUX_INPUT;
-            break;
-        case I2C_6:
-            /* Unused. */
-            break;
-        default: break;
-    }
-}
-
-/* Initialize I2C based on registers. */
-void i2c_init(I2CDevice id) {
-    volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id);
-
-    /* Setup divisor, and clear the bus. */
-    regs->I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001;
-    regs->I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003;
-
-    /* Load hardware configuration. */
-    i2c_load_config(regs);
-
-    /* Wait a while until BUS_CLEAR_DONE is set. */
-    for (unsigned int i = 0; i < 10; i++) {
-        udelay(20000);
-        if (regs->I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) {
-            break;
-        }
-    }
-
-    /* Read the BUS_CLEAR_STATUS. Result doesn't matter. */
-    regs->I2C_I2C_BUS_CLEAR_STATUS_0;
-
-    /* Read and set the Interrupt Status. */
-    uint32_t int_status = regs->I2C_INTERRUPT_STATUS_REGISTER_0;
-    regs->I2C_INTERRUPT_STATUS_REGISTER_0 = int_status;
-}
-
-/* Sets a bit in a PMIC register over I2C during CPU shutdown. */ 
-void i2c_send_pmic_cpu_shutdown_cmd(void) {
-    uint32_t val = 0;
-    /* PMIC == Device 4:3C. */
-    i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1);
-    val |= 4;
-    i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1);
-}
-
-/* Queries the value of TI charger bit over I2C. */
-bool i2c_query_ti_charger_bit_7(void) {
-    uint32_t val = 0;
-    /* TI Charger = Device 0:6B. */
-    i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
-    return (val & 0x80) != 0;
-}
-
-/* Clears TI charger bit over I2C. */
-void i2c_clear_ti_charger_bit_7(void) {
-    uint32_t val = 0;
-    /* TI Charger = Device 0:6B. */
-    i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
-    val &= 0x7F;
-    i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
-}
-
-/* Sets TI charger bit over I2C. */
-void i2c_set_ti_charger_bit_7(void) {
-    uint32_t val = 0;
-    /* TI Charger = Device 0:6B. */
-    i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
-    val |= 0x80;
-    i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
-}
-
-/* Get registers pointer based on I2C ID. */
-volatile tegra_i2c_t *i2c_get_registers_from_id(I2CDevice id) {
-    switch (id) {
-        case I2C_1:
-            return I2C1_REGS;
-        case I2C_2:
-            return I2C2_REGS;
-        case I2C_3:
-            return I2C3_REGS;
-        case I2C_4:
-            return I2C4_REGS;
-        case I2C_5:
-            return I2C5_REGS;
-        case I2C_6:
-            return I2C6_REGS;
-        default:
-            generic_panic();
-    }
-    return NULL;
-}
-
-/* Load hardware config for I2C4. */
-void i2c_load_config(volatile tegra_i2c_t *regs) {
-    /* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */
-    regs->I2C_I2C_CONFIG_LOAD_0 = 0x25;
-
-    /* Wait a bit for master config to be loaded. */
-    for (unsigned int i = 0; i < 20; i++) {
-        udelay(1);
-        if (!(regs->I2C_I2C_CONFIG_LOAD_0 & 1)) {
-            break;
-        }
-    }
-}
-
-/* Reads a register from a device over I2C, writes result to output. */
-bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size) {
-    volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id);
-    uint32_t val = r;
-    
-    /* Write single byte register ID to device. */
-    if (!i2c_write(regs, device, &val, 1)) {
-        return false;
-    }
-    /* Limit output size to 32-bits. */
-    if (dst_size > 4) {
-        return false;
-    }
-    
-    return i2c_read(regs, device, dst, dst_size);
-}
-
-/* Writes a value to a register over I2C. */
-bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size) {    
-    uint32_t val = r;
-    if (src_size == 0) {
-        return true;
-    } else if (src_size <= 3) {
-        memcpy(((uint8_t *)&val) + 1, src, src_size);
-        return i2c_write(i2c_get_registers_from_id(id), device, &val, src_size + 1);
-    } else {
-        return false;
-    }
-}
-
-/* Writes bytes to device over I2C. */
-bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size) {
-    if (src_size > 4) {
-        return false;
-    } else if (src_size == 0) {
-        return true;
-    }
-
-    /* Set device for 7-bit write mode. */
-    regs->I2C_I2C_CMD_ADDR0_0 = device << 1;
-
-    /* Load in data to write. */
-    regs->I2C_I2C_CMD_DATA1_0 = read32le(src, 0);
-
-    /* Set config with LENGTH = src_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
-    regs->I2C_I2C_CNFG_0 = ((src_size << 1) - 2) | 0x2800;
-
-    i2c_load_config(regs);
-
-    /* Config |= SEND; */
-    regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200);
-
-    while (regs->I2C_I2C_STATUS_0 & 0x100) {
-        /* Wait until not busy. */
-    }
-
-    /* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */
-    return (regs->I2C_I2C_STATUS_0 & 0xF) == 0;
-}
-
-/* Reads bytes from device over I2C. */
-bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size) {
-    if (dst_size > 4) {
-        return false;
-    } else if (dst_size == 0) {
-        return true;
-    }
-
-    /* Set device for 7-bit read mode. */
-    regs->I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1;
-
-    /* Set config with LENGTH = dst_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
-    regs->I2C_I2C_CNFG_0 = ((dst_size << 1) - 2) | 0x2840;
-
-    i2c_load_config(regs);
-
-    /* Config |= SEND; */
-    regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200);
-
-    while (regs->I2C_I2C_STATUS_0 & 0x100) {
-        /* Wait until not busy. */
-    }
-    
-    /* Ensure success. */
-    if ((regs->I2C_I2C_STATUS_0 & 0xF) != 0) {
-        return false;
-    }
-
-    uint32_t val = regs->I2C_I2C_CMD_DATA1_0;
-    memcpy(dst, &val, dst_size);
-    return true;
-}

fusee/fusee-primary/fusee-primary-main/src/i2c.h

@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_I2C_H
-#define FUSEE_I2C_H
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-
-#define I2C1234_BASE    0x7000C000
-#define I2C56_BASE      0x7000D000
-
-#define MAX77621_CPU_I2C_ADDR               0x1B
-#define MAX77621_GPU_I2C_ADDR               0x1C
-#define MAX77812_PHASE31_CPU_I2C_ADDR       0x31
-#define MAX77812_PHASE211_CPU_I2C_ADDR      0x33
-#define MAX17050_I2C_ADDR                   0x36
-#define MAX77620_PWR_I2C_ADDR               0x3C
-#define MAX77620_RTC_I2C_ADDR               0x68
-#define BQ24193_I2C_ADDR                    0x6B
-
-typedef enum {
-    I2C_1 = 0,
-    I2C_2 = 1,
-    I2C_3 = 2,
-    I2C_4 = 3,
-    I2C_5 = 4,
-    I2C_6 = 5,
-} I2CDevice;
-
-typedef struct {
-    uint32_t I2C_I2C_CNFG_0;
-    uint32_t I2C_I2C_CMD_ADDR0_0;
-    uint32_t I2C_I2C_CMD_ADDR1_0;
-    uint32_t I2C_I2C_CMD_DATA1_0;
-    uint32_t I2C_I2C_CMD_DATA2_0;
-    uint32_t _0x14;
-    uint32_t _0x18;
-    uint32_t I2C_I2C_STATUS_0;
-    uint32_t I2C_I2C_SL_CNFG_0;
-    uint32_t I2C_I2C_SL_RCVD_0;
-    uint32_t I2C_I2C_SL_STATUS_0;
-    uint32_t I2C_I2C_SL_ADDR1_0;
-    uint32_t I2C_I2C_SL_ADDR2_0;
-    uint32_t I2C_I2C_TLOW_SEXT_0;
-    uint32_t _0x38;
-    uint32_t I2C_I2C_SL_DELAY_COUNT_0;
-    uint32_t I2C_I2C_SL_INT_MASK_0;
-    uint32_t I2C_I2C_SL_INT_SOURCE_0;
-    uint32_t I2C_I2C_SL_INT_SET_0;
-    uint32_t _0x4C;
-    uint32_t I2C_I2C_TX_PACKET_FIFO_0;
-    uint32_t I2C_I2C_RX_FIFO_0;
-    uint32_t I2C_PACKET_TRANSFER_STATUS_0;
-    uint32_t I2C_FIFO_CONTROL_0;
-    uint32_t I2C_FIFO_STATUS_0;
-    uint32_t I2C_INTERRUPT_MASK_REGISTER_0;
-    uint32_t I2C_INTERRUPT_STATUS_REGISTER_0;
-    uint32_t I2C_I2C_CLK_DIVISOR_REGISTER_0;
-    uint32_t I2C_I2C_INTERRUPT_SOURCE_REGISTER_0;
-    uint32_t I2C_I2C_INTERRUPT_SET_REGISTER_0;
-    uint32_t I2C_I2C_SLV_TX_PACKET_FIFO_0;
-    uint32_t I2C_I2C_SLV_RX_FIFO_0;
-    uint32_t I2C_I2C_SLV_PACKET_STATUS_0;
-    uint32_t I2C_I2C_BUS_CLEAR_CONFIG_0;
-    uint32_t I2C_I2C_BUS_CLEAR_STATUS_0;
-    uint32_t I2C_I2C_CONFIG_LOAD_0;
-    uint32_t _0x90;
-    uint32_t I2C_I2C_INTERFACE_TIMING_0_0;
-    uint32_t I2C_I2C_INTERFACE_TIMING_1_0;
-    uint32_t I2C_I2C_HS_INTERFACE_TIMING_0_0;
-    uint32_t I2C_I2C_HS_INTERFACE_TIMING_1_0;
-} tegra_i2c_t;
-
-#define I2C1_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x000))
-#define I2C2_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x400))
-#define I2C3_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x500))
-#define I2C4_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x700))
-#define I2C5_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x000))
-#define I2C6_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x100))
-
-void i2c_config(I2CDevice id);
-
-void i2c_init(I2CDevice id);
-bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size);
-bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size);
-
-void i2c_send_pmic_cpu_shutdown_cmd(void);
-bool i2c_query_ti_charger_bit_7(void);
-void i2c_clear_ti_charger_bit_7(void);
-void i2c_set_ti_charger_bit_7(void);
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/init.c

@@ -1,146 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
-#include <stddef.h>
-#include <string.h>
-#include <malloc.h>
-#include <sys/iosupport.h>
-#include "utils.h"
-
-void __libc_init_array(void);
-void __libc_fini_array(void);
-
-extern uint8_t __bss_start__[], __bss_end__[];
-extern uint8_t __heap_start__[], __heap_end__[];
-
-extern char *fake_heap_start;
-extern char *fake_heap_end;
-
-int __program_argc;
-void **__program_argv;
-
-void __attribute__((noreturn)) __program_exit(int rc);
-void __attribute__((noreturn)) (*__program_exit_callback)(int rc) = NULL;
-
-static void __program_parse_argc_argv(int argc, char *argdata);
-static void __program_cleanup_argv(void);
-
-static void __program_init_heap(void) {
-    fake_heap_start = (char*)__heap_start__;
-    fake_heap_end   = (char*)__heap_end__;
-}
-
-static void __program_init_newlib_hooks(void) {
-    __syscalls.exit = __program_exit; /* For exit, etc. */
-}
-
-static void __program_move_additional_sections(void) {
-#if defined(FUSEE_STAGE1_SRC) || defined(FUSEE_STAGE2_SRC)
-    extern uint8_t __chainloader_lma__[], __chainloader_start__[], __chainloader_bss_start__[], __chainloader_end__[];
-    memcpy(__chainloader_start__, __chainloader_lma__, __chainloader_bss_start__ - __chainloader_start__);
-    memset(__chainloader_bss_start__, 0, __chainloader_end__ - __chainloader_bss_start__);
-#endif
-}
-
-void __program_init(int argc, char *argdata) {
-    /* Zero-fill the .bss section */
-    memset(__bss_start__, 0, __bss_end__ - __bss_start__);
-
-    __program_init_heap();
-    __program_init_newlib_hooks();
-    __program_parse_argc_argv(argc, argdata);
-
-    /* Once argv is parsed, we can discard the low IRAM region */
-    __program_move_additional_sections();
-    __libc_init_array();
-}
-
-void __program_exit(int rc) {
-    __libc_fini_array();
-    __program_cleanup_argv();
-    if (__program_exit_callback == NULL) {
-        /* Default callback */
-        generic_panic();
-    } else {
-        __program_exit_callback(rc);
-    }
-    for (;;);
-}
-
-#ifdef FUSEE_STAGE1_SRC
-static void __program_parse_argc_argv(int argc, char *argdata) {
-    __program_argc = 0;
-    __program_argv = NULL;
-}
-#elif defined(FUSEE_STAGE2_SRC)
-#include "stage2.h"
-static void __program_parse_argc_argv(int argc, char *argdata) {
-    size_t pos = 0, len;
-
-    __program_argc = argc;
-
-    __program_argv = malloc(argc * sizeof(void **));
-    if (__program_argv == NULL) {
-        generic_panic();
-    }
-
-    len = strlen(argdata);
-    __program_argv[0] = malloc(len + 1);
-    if (__program_argv[0] == NULL) {
-        generic_panic();
-    }
-    strcpy((char *)__program_argv[0], argdata);
-    pos += len + 1;
-
-    __program_argv[1] = malloc(sizeof(stage2_args_t));
-    if (__program_argv[1] == NULL) {
-        generic_panic();
-    }
-    memcpy(__program_argv[1], argdata + pos, sizeof(stage2_args_t));
-}
-#else
-static void __program_parse_argc_argv(int argc, char *argdata) {
-    size_t pos = 0, len;
-
-    __program_argc = argc;
-
-    __program_argv = malloc(argc * sizeof(void **));
-    if (__program_argv == NULL) {
-        generic_panic();
-    }
-
-    for (int i = 0; i < argc; i++) {
-        len = strlen(argdata + pos);
-        __program_argv[i] = malloc(len + 1);
-        if (__program_argv[i] == NULL) {
-            generic_panic();
-        }
-        strcpy((char *)__program_argv[i], argdata + pos);
-        pos += len + 1;
-    }
-}
-#endif
-
-static void __program_cleanup_argv(void) {
-#ifndef FUSEE_STAGE1_SRC
-    for (int i = 0; i < __program_argc; i++) {
-        free(__program_argv[i]);
-        __program_argv[i] = NULL;
-    }
-    free(__program_argv);
-#endif
-}

fusee/fusee-primary/fusee-primary-main/src/main.c

@@ -1,200 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "utils.h"
-#include "exception_handlers.h"
-#include "panic.h"
-#include "fuse.h"
-#include "hwinit.h"
-#include "di.h"
-#include "timers.h"
-#include "fs_utils.h"
-#include "stage2.h"
-#include "chainloader.h"
-#include "../../../fusee/common/sdmmc/sdmmc.h"
-#include "../../../fusee/common/fatfs/ff.h"
-#include "../../../fusee/common/log.h"
-#include "../../../fusee/common/vsprintf.h"
-#include "../../../fusee/common/ini.h"
-#include "../../../fusee/common/display/video_fb.h"
-
-extern void (*__program_exit_callback)(int rc);
-
-static void *g_framebuffer;
-static char g_bct0_buffer[BCTO_MAX_SIZE];
-
-#define CONFIG_LOG_LEVEL_KEY "log_level"
-
-static const char *get_default_bct0(void) {
-    return "BCT0\n"
-           "[stage1]\n"
-           "stage2_path = atmosphere/fusee-secondary.bin\n"
-           "stage2_mtc_path = atmosphere/fusee-mtc.bin\n"
-           "stage2_addr = 0xF0000000\n"
-           "stage2_entrypoint = 0xF0000000\n"
-           "\n"
-           "[stratosphere]\n"
-           "\n";
-}
-
-static const char *load_config(void) {
-    if (!read_from_file(g_bct0_buffer, BCTO_MAX_SIZE, "atmosphere/config/BCT.ini")) {
-        print(SCREEN_LOG_LEVEL_DEBUG, "Failed to read BCT0 from SD!\n");
-        print(SCREEN_LOG_LEVEL_DEBUG, "Using default BCT0!\n");
-
-        const char * const default_bct0 = get_default_bct0();
-        memcpy(g_bct0_buffer, default_bct0, strlen(default_bct0));
-    }
-
-    if (memcmp(g_bct0_buffer, "BCT0", 4) != 0) {
-        fatal_error("Unexpected magic in BCT.ini!\n");
-    }
-
-    /* Return pointer to first line of the ini. */
-    const char *bct0 = g_bct0_buffer;
-    while (*bct0 && *bct0 != '\n') {
-        bct0++;
-    }
-
-    if (!bct0) {
-        fatal_error("BCT.ini has no newline!\n");
-    }
-
-    return bct0;
-}
-
-static int config_ini_handler(void *user, const char *section, const char *name, const char *value) {
-    if (strcmp(section, "config") == 0) {
-        if (strcmp(name, CONFIG_LOG_LEVEL_KEY) == 0) {
-            ScreenLogLevel *config_log_level = (ScreenLogLevel *)user;
-            int log_level = 0;
-            sscanf(value, "%d", &log_level);
-            *config_log_level = (ScreenLogLevel)log_level;
-        } else {
-            return 0;
-        }
-    } else {
-        return 0;
-    }
-    return 1;
-}
-
-static void setup_display(void) {
-    g_framebuffer = (void *)0xC0000000;
-
-    /* Zero-fill the framebuffer and register it as printk provider. */
-    video_init(g_framebuffer);
-
-    /* Initialize the display. */
-    display_init();
-
-    /* Set the framebuffer. */
-    display_init_framebuffer(g_framebuffer);
-
-    /* Turn on the backlight after initializing the lfb */
-    /* to avoid flickering. */
-    display_backlight(true);
-}
-
-static void cleanup_display(void) {
-    /* Turn off the backlight. */
-    display_backlight(false);
-
-    /* Terminate the display. */
-    display_end();
-}
-
-static void setup_env(void) {
-    /* Initialize hardware. */
-    nx_hwinit(false);
-
-    /* Set up the exception handlers. */
-    setup_exception_handlers();
-
-    /* Mount the SD card. */
-    mount_sd();
-}
-
-static void cleanup_env(void) {
-    /* Unmount the SD card. */
-    unmount_sd();
-}
-
-static void exit_callback(int rc) {
-    (void)rc;
-    relocate_and_chainload();
-}
-
-int main(void) {
-    const char *bct0;
-    const char *stage2_path;
-    stage2_args_t *stage2_args;
-    uint32_t stage2_version = 0;
-    ScreenLogLevel log_level = SCREEN_LOG_LEVEL_NONE;
-
-    /* Initialize the boot environment. */
-    setup_env();
-
-    /* Check for panics. */
-    check_and_display_panic();
-
-    /* Load the BCT0 configuration ini off of the SD. */
-    bct0 = load_config();
-
-    /* Extract the logging level from the BCT.ini file. */
-    if (ini_parse_string(bct0, config_ini_handler, &log_level) < 0) {
-        fatal_error("Failed to parse BCT.ini!\n");
-    }
-
-    /* Override the global logging level. */
-    log_set_log_level(log_level);
-
-    if (log_level != SCREEN_LOG_LEVEL_NONE) {
-        /* Initialize the display for debugging. */
-        setup_display();
-    }
-
-    /* Say hello. */
-    print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, "Welcome to Atmosph\xe8re Fus\xe9" "e!\n");
-    print(SCREEN_LOG_LEVEL_DEBUG, "Using color linear framebuffer at 0x%p!\n", g_framebuffer);
-
-    /* Load the loader payload into DRAM. */
-    load_stage2(bct0);
-
-    /* Setup argument data. */
-    stage2_path = stage2_get_program_path();
-    strcpy(g_chainloader_arg_data, stage2_path);
-    stage2_args = (stage2_args_t *)(g_chainloader_arg_data + strlen(stage2_path) + 1); /* May be unaligned. */
-    memcpy(&stage2_args->version, &stage2_version, 4);
-    memcpy(&stage2_args->log_level, &log_level, sizeof(log_level));
-    strcpy(stage2_args->bct0, bct0);
-    g_chainloader_argc = 2;
-
-    /* Terminate the boot environment. */
-    cleanup_env();
-
-    if (log_level != SCREEN_LOG_LEVEL_NONE) {
-        /* Wait a while for debugging. */
-        mdelay(1000);
-
-        /* Terminate the display for debugging. */
-        cleanup_display();
-    }
-
-    /* Finally, after the cleanup routines (__libc_fini_array, etc.) are called, jump to Stage2. */
-    __program_exit_callback = exit_callback;
-    return 0;
-}

fusee/fusee-primary/fusee-primary-main/src/max77620.h

@@ -1,357 +0,0 @@
-/*
- * Defining registers address and its bit definitions of MAX77620 and MAX20024
- *
- * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- */
-
-#ifndef _MFD_MAX77620_H_
-#define _MFD_MAX77620_H_
-
-/* RTC Registers */
-#define MAX77620_REG_RTCINT     0x00
-#define MAX77620_REG_RTCINTM        0x01
-#define MAX77620_REG_RTCCNTLM       0x02
-#define MAX77620_REG_RTCCNTL        0x03
-#define MAX77620_REG_RTCUPDATE0     0x04
-#define MAX77620_REG_RTCUPDATE1     0x05
-#define MAX77620_REG_RTCSMPL        0x06
-#define MAX77620_REG_RTCSEC     0x07
-#define MAX77620_REG_RTCMIN     0x08
-#define MAX77620_REG_RTCHOUR        0x09
-#define MAX77620_REG_RTCDOW     0x0A
-#define MAX77620_REG_RTCMONTH       0x0B
-#define MAX77620_REG_RTCYEAR        0x0C
-#define MAX77620_REG_RTCDOM     0x0D
-#define MAX77620_REG_RTCSECA1       0x0E
-#define MAX77620_REG_RTCMINA1       0x0F
-#define MAX77620_REG_RTCHOURA1      0x10
-#define MAX77620_REG_RTCDOWA1       0x11
-#define MAX77620_REG_RTCMONTHA1     0x12
-#define MAX77620_REG_RTCYEARA1      0x13
-#define MAX77620_REG_RTCDOMA1       0x14
-#define MAX77620_REG_RTCSECA2       0x15
-#define MAX77620_REG_RTCMINA2       0x16
-#define MAX77620_REG_RTCHOURA2      0x17
-#define MAX77620_REG_RTCDOWA2       0x18
-#define MAX77620_REG_RTCMONTHA2     0x19
-#define MAX77620_REG_RTCYEARA2      0x1A
-#define MAX77620_REG_RTCDOMA2       0x1B
-
-/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
-#define MAX77620_REG_CNFGGLBL1          0x00
-#define MAX77620_REG_CNFGGLBL2          0x01
-#define MAX77620_REG_CNFGGLBL3          0x02
-#define MAX77620_REG_CNFG1_32K          0x03
-#define MAX77620_REG_CNFGBBC            0x04
-#define MAX77620_REG_IRQTOP         0x05
-#define MAX77620_REG_INTLBT         0x06
-#define MAX77620_REG_IRQSD          0x07
-#define MAX77620_REG_IRQ_LVL2_L0_7      0x08
-#define MAX77620_REG_IRQ_LVL2_L8        0x09
-#define MAX77620_REG_IRQ_LVL2_GPIO      0x0A
-#define MAX77620_REG_ONOFFIRQ           0x0B
-#define MAX77620_REG_NVERC          0x0C
-#define MAX77620_REG_IRQTOPM            0x0D
-#define MAX77620_REG_INTENLBT           0x0E
-#define MAX77620_REG_IRQMASKSD          0x0F
-#define MAX77620_REG_IRQ_MSK_L0_7       0x10
-#define MAX77620_REG_IRQ_MSK_L8         0x11
-#define MAX77620_REG_ONOFFIRQM          0x12
-#define MAX77620_REG_STATLBT            0x13
-#define MAX77620_REG_STATSD         0x14
-#define MAX77620_REG_ONOFFSTAT          0x15
-
-/* SD and LDO Registers */
-#define MAX77620_REG_SD0            0x16
-#define MAX77620_REG_SD1            0x17
-#define MAX77620_REG_SD2            0x18
-#define MAX77620_REG_SD3            0x19
-#define MAX77620_REG_SD4            0x1A
-#define MAX77620_REG_DVSSD0         0x1B
-#define MAX77620_REG_DVSSD1         0x1C
-#define MAX77620_REG_SD0_CFG            0x1D
-#define MAX77620_REG_SD1_CFG            0x1E
-#define MAX77620_REG_SD2_CFG            0x1F
-#define MAX77620_REG_SD3_CFG            0x20
-#define MAX77620_REG_SD4_CFG            0x21
-#define MAX77620_REG_SD_CFG2            0x22
-#define MAX77620_REG_LDO0_CFG           0x23
-#define MAX77620_REG_LDO0_CFG2          0x24
-#define MAX77620_REG_LDO1_CFG           0x25
-#define MAX77620_REG_LDO1_CFG2          0x26
-#define MAX77620_REG_LDO2_CFG           0x27
-#define MAX77620_REG_LDO2_CFG2          0x28
-#define MAX77620_REG_LDO3_CFG           0x29
-#define MAX77620_REG_LDO3_CFG2          0x2A
-#define MAX77620_REG_LDO4_CFG           0x2B
-#define MAX77620_REG_LDO4_CFG2          0x2C
-#define MAX77620_REG_LDO5_CFG           0x2D
-#define MAX77620_REG_LDO5_CFG2          0x2E
-#define MAX77620_REG_LDO6_CFG           0x2F
-#define MAX77620_REG_LDO6_CFG2          0x30
-#define MAX77620_REG_LDO7_CFG           0x31
-#define MAX77620_REG_LDO7_CFG2          0x32
-#define MAX77620_REG_LDO8_CFG           0x33
-#define MAX77620_REG_LDO8_CFG2          0x34
-#define MAX77620_REG_LDO_CFG3           0x35
-
-#define MAX77620_LDO_SLEW_RATE_MASK     0x1
-
-/* LDO Configuration 3 */
-#define MAX77620_TRACK4_MASK            (1 << 5)
-#define MAX77620_TRACK4_SHIFT           5
-
-/* Voltage */
-#define MAX77620_SDX_VOLT_MASK          0xFF
-#define MAX77620_SD0_VOLT_MASK          0x3F
-#define MAX77620_SD1_VOLT_MASK          0x7F
-#define MAX77620_LDO_VOLT_MASK          0x3F
-
-#define MAX77620_REG_GPIO0          0x36
-#define MAX77620_REG_GPIO1          0x37
-#define MAX77620_REG_GPIO2          0x38
-#define MAX77620_REG_GPIO3          0x39
-#define MAX77620_REG_GPIO4          0x3A
-#define MAX77620_REG_GPIO5          0x3B
-#define MAX77620_REG_GPIO6          0x3C
-#define MAX77620_REG_GPIO7          0x3D
-#define MAX77620_REG_PUE_GPIO           0x3E
-#define MAX77620_REG_PDE_GPIO           0x3F
-#define MAX77620_REG_AME_GPIO           0x40
-#define MAX77620_REG_ONOFFCNFG1         0x41
-#define MAX77620_REG_ONOFFCNFG2         0x42
-
-/* FPS Registers */
-#define MAX77620_REG_FPS_CFG0           0x43
-#define MAX77620_REG_FPS_CFG1           0x44
-#define MAX77620_REG_FPS_CFG2           0x45
-#define MAX77620_REG_FPS_LDO0           0x46
-#define MAX77620_REG_FPS_LDO1           0x47
-#define MAX77620_REG_FPS_LDO2           0x48
-#define MAX77620_REG_FPS_LDO3           0x49
-#define MAX77620_REG_FPS_LDO4           0x4A
-#define MAX77620_REG_FPS_LDO5           0x4B
-#define MAX77620_REG_FPS_LDO6           0x4C
-#define MAX77620_REG_FPS_LDO7           0x4D
-#define MAX77620_REG_FPS_LDO8           0x4E
-#define MAX77620_REG_FPS_SD0            0x4F
-#define MAX77620_REG_FPS_SD1            0x50
-#define MAX77620_REG_FPS_SD2            0x51
-#define MAX77620_REG_FPS_SD3            0x52
-#define MAX77620_REG_FPS_SD4            0x53
-#define MAX77620_REG_FPS_NONE           0
-
-#define MAX77620_FPS_SRC_MASK           0xC0
-#define MAX77620_FPS_SRC_SHIFT          6
-#define MAX77620_FPS_PU_PERIOD_MASK     0x38
-#define MAX77620_FPS_PU_PERIOD_SHIFT        3
-#define MAX77620_FPS_PD_PERIOD_MASK     0x07
-#define MAX77620_FPS_PD_PERIOD_SHIFT        0
-#define MAX77620_FPS_TIME_PERIOD_MASK       0x38
-#define MAX77620_FPS_TIME_PERIOD_SHIFT      3
-#define MAX77620_FPS_EN_SRC_MASK        0x06
-#define MAX77620_FPS_EN_SRC_SHIFT       1
-#define MAX77620_FPS_ENFPS_SW_MASK      0x01
-#define MAX77620_FPS_ENFPS_SW           0x01
-
-/* Minimum and maximum FPS period time (in microseconds) are
- * different for MAX77620 and Max20024.
- */
-#define MAX77620_FPS_PERIOD_MIN_US      40
-#define MAX20024_FPS_PERIOD_MIN_US      20
-
-#define MAX77620_FPS_PERIOD_MAX_US      2560
-#define MAX20024_FPS_PERIOD_MAX_US      5120
-
-#define MAX77620_REG_FPS_GPIO1          0x54
-#define MAX77620_REG_FPS_GPIO2          0x55
-#define MAX77620_REG_FPS_GPIO3          0x56
-#define MAX77620_REG_FPS_RSO            0x57
-#define MAX77620_REG_CID0           0x58
-#define MAX77620_REG_CID1           0x59
-#define MAX77620_REG_CID2           0x5A
-#define MAX77620_REG_CID3           0x5B
-#define MAX77620_REG_CID4           0x5C
-#define MAX77620_REG_CID5           0x5D
-
-#define MAX77620_REG_DVSSD4         0x5E
-#define MAX20024_REG_MAX_ADD            0x70
-
-#define MAX77620_CID_DIDM_MASK          0xF0
-#define MAX77620_CID_DIDM_SHIFT         4
-
-/* CNCG2SD */
-#define MAX77620_SD_CNF2_ROVS_EN_SD1        (1 << 1)
-#define MAX77620_SD_CNF2_ROVS_EN_SD0        (1 << 2)
-
-/* Device Identification Metal */
-#define MAX77620_CID5_DIDM(n)           (((n) >> 4) & 0xF)
-/* Device Indentification OTP */
-#define MAX77620_CID5_DIDO(n)           ((n) & 0xF)
-
-/* SD CNFG1 */
-#define MAX77620_SD_SR_MASK         0xC0
-#define MAX77620_SD_SR_SHIFT            6
-#define MAX77620_SD_POWER_MODE_MASK     0x30
-#define MAX77620_SD_POWER_MODE_SHIFT        4
-#define MAX77620_SD_CFG1_ADE_MASK       (1 << 3)
-#define MAX77620_SD_CFG1_ADE_DISABLE        0
-#define MAX77620_SD_CFG1_ADE_ENABLE     (1 << 3)
-#define MAX77620_SD_FPWM_MASK           0x04
-#define MAX77620_SD_FPWM_SHIFT          2
-#define MAX77620_SD_FSRADE_MASK         0x01
-#define MAX77620_SD_FSRADE_SHIFT        0
-#define MAX77620_SD_CFG1_FPWM_SD_MASK       (1 << 2)
-#define MAX77620_SD_CFG1_FPWM_SD_SKIP       0
-#define MAX77620_SD_CFG1_FPWM_SD_FPWM       (1 << 2)
-#define MAX20024_SD_CFG1_MPOK_MASK      (1 << 1)
-#define MAX77620_SD_CFG1_FSRADE_SD_MASK     (1 << 0)
-#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE  0
-#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE   (1 << 0)
-
-/* LDO_CNFG2 */
-#define MAX77620_LDO_POWER_MODE_MASK        0xC0
-#define MAX77620_LDO_POWER_MODE_SHIFT       6
-#define MAX20024_LDO_CFG2_MPOK_MASK     (1 << 2)
-#define MAX77620_LDO_CFG2_ADE_MASK      (1 << 1)
-#define MAX77620_LDO_CFG2_ADE_DISABLE       0
-#define MAX77620_LDO_CFG2_ADE_ENABLE        (1 << 1)
-#define MAX77620_LDO_CFG2_SS_MASK       (1 << 0)
-#define MAX77620_LDO_CFG2_SS_FAST       (1 << 0)
-#define MAX77620_LDO_CFG2_SS_SLOW       0
-
-#define MAX77620_IRQ_TOP_GLBL_MASK      (1 << 7)
-#define MAX77620_IRQ_TOP_SD_MASK        (1 << 6)
-#define MAX77620_IRQ_TOP_LDO_MASK       (1 << 5)
-#define MAX77620_IRQ_TOP_GPIO_MASK      (1 << 4)
-#define MAX77620_IRQ_TOP_RTC_MASK       (1 << 3)
-#define MAX77620_IRQ_TOP_32K_MASK       (1 << 2)
-#define MAX77620_IRQ_TOP_ONOFF_MASK     (1 << 1)
-
-#define MAX77620_IRQ_LBM_MASK           (1 << 3)
-#define MAX77620_IRQ_TJALRM1_MASK       (1 << 2)
-#define MAX77620_IRQ_TJALRM2_MASK       (1 << 1)
-
-#define MAX77620_CNFG_GPIO_DRV_MASK     (1 << 0)
-#define MAX77620_CNFG_GPIO_DRV_PUSHPULL     (1 << 0)
-#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN    0
-#define MAX77620_CNFG_GPIO_DIR_MASK     (1 << 1)
-#define MAX77620_CNFG_GPIO_DIR_INPUT        (1 << 1)
-#define MAX77620_CNFG_GPIO_DIR_OUTPUT       0
-#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK   (1 << 2)
-#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK  (1 << 3)
-#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH  (1 << 3)
-#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW   0
-#define MAX77620_CNFG_GPIO_INT_MASK     (0x3 << 4)
-#define MAX77620_CNFG_GPIO_INT_FALLING      (1 << 4)
-#define MAX77620_CNFG_GPIO_INT_RISING       (1 << 5)
-#define MAX77620_CNFG_GPIO_DBNC_MASK        (0x3 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_None        (0x0 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_8ms     (0x1 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_16ms        (0x2 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_32ms        (0x3 << 6)
-
-#define MAX77620_IRQ_LVL2_GPIO_EDGE0        (1 << 0)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE1        (1 << 1)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE2        (1 << 2)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE3        (1 << 3)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE4        (1 << 4)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE5        (1 << 5)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE6        (1 << 6)
-#define MAX77620_IRQ_LVL2_GPIO_EDGE7        (1 << 7)
-
-#define MAX77620_CNFG1_32K_OUT0_EN      (1 << 2)
-
-#define MAX77620_ONOFFCNFG1_SFT_RST     (1 << 7)
-#define MAX77620_ONOFFCNFG1_MRT_MASK        0x38
-#define MAX77620_ONOFFCNFG1_MRT_SHIFT       0x3
-#define MAX77620_ONOFFCNFG1_SLPEN       (1 << 2)
-#define MAX77620_ONOFFCNFG1_PWR_OFF     (1 << 1)
-#define MAX20024_ONOFFCNFG1_CLRSE       0x18
-
-#define MAX77620_ONOFFCNFG2_SFT_RST_WK      (1 << 7)
-#define MAX77620_ONOFFCNFG2_WD_RST_WK       (1 << 6)
-#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK     (1 << 5)
-#define MAX77620_ONOFFCNFG2_WK_ALARM1       (1 << 2)
-#define MAX77620_ONOFFCNFG2_WK_EN0      (1 << 0)
-
-#define MAX77620_GLBLM_MASK         (1 << 0)
-
-#define MAX77620_WDTC_MASK          0x3
-#define MAX77620_WDTOFFC            (1 << 4)
-#define MAX77620_WDTSLPC            (1 << 3)
-#define MAX77620_WDTEN              (1 << 2)
-
-#define MAX77620_TWD_MASK           0x3
-#define MAX77620_TWD_2s             0x0
-#define MAX77620_TWD_16s            0x1
-#define MAX77620_TWD_64s            0x2
-#define MAX77620_TWD_128s           0x3
-
-#define MAX77620_CNFGGLBL1_LBDAC_EN     (1 << 7)
-#define MAX77620_CNFGGLBL1_MPPLD        (1 << 6)
-#define MAX77620_CNFGGLBL1_LBHYST       ((1 << 5) | (1 << 4))
-#define MAX77620_CNFGGLBL1_LBHYST_N     (1 << 4)
-#define MAX77620_CNFGGLBL1_LBDAC        0x0E
-#define MAX77620_CNFGGLBL1_LBDAC_N      (1 << 1)
-#define MAX77620_CNFGGLBL1_LBRSTEN      (1 << 0)
-
-/* CNFG BBC registers */
-#define MAX77620_CNFGBBC_ENABLE         (1 << 0)
-#define MAX77620_CNFGBBC_CURRENT_MASK       0x06
-#define MAX77620_CNFGBBC_CURRENT_SHIFT      1
-#define MAX77620_CNFGBBC_VOLTAGE_MASK       0x18
-#define MAX77620_CNFGBBC_VOLTAGE_SHIFT      3
-#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE    (1 << 5)
-#define MAX77620_CNFGBBC_RESISTOR_MASK      0xC0
-#define MAX77620_CNFGBBC_RESISTOR_SHIFT     6
-
-#define MAX77620_FPS_COUNT          3
-
-/* Interrupts */
-enum {
-    MAX77620_IRQ_TOP_GLBL,      /* Low-Battery */
-    MAX77620_IRQ_TOP_SD,        /* SD power fail */
-    MAX77620_IRQ_TOP_LDO,       /* LDO power fail */
-    MAX77620_IRQ_TOP_GPIO,      /* TOP GPIO internal int to MAX77620 */
-    MAX77620_IRQ_TOP_RTC,       /* RTC */
-    MAX77620_IRQ_TOP_32K,       /* 32kHz oscillator */
-    MAX77620_IRQ_TOP_ONOFF,     /* ON/OFF oscillator */
-    MAX77620_IRQ_LBT_MBATLOW,   /* Thermal alarm status, > 120C */
-    MAX77620_IRQ_LBT_TJALRM1,   /* Thermal alarm status, > 120C */
-    MAX77620_IRQ_LBT_TJALRM2,   /* Thermal alarm status, > 140C */
-};
-
-/* GPIOs */
-enum {
-    MAX77620_GPIO0,
-    MAX77620_GPIO1,
-    MAX77620_GPIO2,
-    MAX77620_GPIO3,
-    MAX77620_GPIO4,
-    MAX77620_GPIO5,
-    MAX77620_GPIO6,
-    MAX77620_GPIO7,
-    MAX77620_GPIO_NR,
-};
-
-/* FPS Source */
-enum max77620_fps_src {
-    MAX77620_FPS_SRC_0,
-    MAX77620_FPS_SRC_1,
-    MAX77620_FPS_SRC_2,
-    MAX77620_FPS_SRC_NONE,
-    MAX77620_FPS_SRC_DEF,
-};
-
-enum max77620_chip_id {
-    MAX77620,
-    MAX20024,
-};
-
-#endif /* _MFD_MAX77620_H_ */

fusee/fusee-primary/fusee-primary-main/src/max7762x.c

@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
- 
-#include "max7762x.h"
-#include "max77620.h"
-#include "i2c.h"
-#include "timers.h"
-
-#define REGULATOR_SD 0
-#define REGULATOR_LDO 1
-
-typedef struct _max77620_regulator_t
-{
-    uint8_t type;
-    const char *name;
-    uint8_t reg_sd;
-    uint32_t mv_step;
-    uint32_t mv_min;
-    uint32_t mv_default;
-    uint32_t mv_max;
-    uint8_t volt_addr;
-    uint8_t cfg_addr;
-    uint8_t volt_mask;
-    uint8_t enable_mask;
-    uint8_t enable_shift;
-    uint8_t status_mask;
-
-    uint8_t fps_addr;
-    uint8_t fps_src;
-    uint8_t pd_period;
-    uint8_t pu_period;
-} max77620_regulator_t;
-
-static const max77620_regulator_t _pmic_regulators[] = {
-    {  REGULATOR_SD,  "sd0", 0x16, 12500, 600000,  625000, 1400000,      MAX77620_REG_SD0,   MAX77620_REG_SD0_CFG, 0x3F, 0x30, 4, 0x80, 0x4F, 1, 7, 1 },
-    {  REGULATOR_SD,  "sd1", 0x17, 12500, 600000, 1125000, 1125000,      MAX77620_REG_SD1,   MAX77620_REG_SD1_CFG, 0x3F, 0x30, 4, 0x40, 0x50, 0, 1, 5 },
-    {  REGULATOR_SD,  "sd2", 0x18, 12500, 600000, 1325000, 1350000,      MAX77620_REG_SD2,   MAX77620_REG_SD2_CFG, 0xFF, 0x30, 4, 0x20, 0x51, 1, 5, 2 },
-    {  REGULATOR_SD,  "sd3", 0x19, 12500, 600000, 1800000, 1800000,      MAX77620_REG_SD3,   MAX77620_REG_SD3_CFG, 0xFF, 0x30, 4, 0x10, 0x52, 0, 3, 3 },
-    { REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, 0x3F, 0xC0, 6, 0x00, 0x46, 3, 7, 0 },
-    { REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, 0x3F, 0xC0, 6, 0x00, 0x47, 3, 7, 0 },
-    { REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, 0x3F, 0xC0, 6, 0x00, 0x48, 3, 7, 0 },
-    { REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, 0x3F, 0xC0, 6, 0x00, 0x49, 3, 7, 0 },
-    { REGULATOR_LDO, "ldo4", 0x00, 12500, 800000,  850000,  850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4A, 0, 7, 1 },
-    { REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4B, 3, 7, 0 },
-    { REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4C, 3, 7, 0 },
-    { REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4D, 1, 4, 3 },
-    { REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4E, 3, 7, 0 }
-};
-
-int max77620_regulator_get_status(uint32_t id)
-{
-    if (id > REGULATOR_MAX)
-        return 0;
-
-    const max77620_regulator_t *reg = &_pmic_regulators[id];
-    uint8_t val = 0;
-
-    if (reg->type == REGULATOR_SD) {
-        if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_STATSD, &val, 1))
-            return (val & reg->status_mask) ? 0 : 1;
-    }
-    
-    if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1))
-        return (val & 8) ? 1 : 0;
-    
-    return 0;
-}
-
-int max77620_regulator_config_fps(uint32_t id)
-{
-    if (id > REGULATOR_MAX)
-        return 0;
-
-    const max77620_regulator_t *reg = &_pmic_regulators[id];
-    uint8_t val = ((reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period));
-
-    if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->fps_addr, &val, 1)) {
-        return 1;
-    }
-
-    return 0;
-}
-
-int max77620_regulator_set_voltage(uint32_t id, uint32_t mv)
-{
-    if (id > REGULATOR_MAX)
-        return 0;
-
-    const max77620_regulator_t *reg = &_pmic_regulators[id];
-
-    if ((mv < reg->mv_default) || (mv > reg->mv_max))
-        return 0;
-
-    uint32_t mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
-    uint8_t val = 0;
-    
-    if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1))
-    {
-        val = ((val & ~reg->volt_mask) | (mult & reg->volt_mask));
-        
-        if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1))
-        {
-            udelay(1000);
-            return 1;
-        }
-    }
-    
-    return 0;
-}
-
-int max77620_regulator_enable(uint32_t id, int enable)
-{
-    if (id > REGULATOR_MAX)
-        return 0;
-
-    const max77620_regulator_t *reg = &_pmic_regulators[id];
-
-    uint32_t addr = (reg->type == REGULATOR_SD) ? reg->cfg_addr : reg->volt_addr;
-    uint8_t val = 0;
-    
-    if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1))
-    {
-        if (enable)
-            val = ((val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask));
-        else
-            val &= ~reg->enable_mask;
-        
-        if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1))
-        {
-            udelay(1000);
-            return 1;
-        }
-    }
-
-    return 0;
-}
-
-void max77620_config_default()
-{
-    for (uint32_t i = 1; i <= REGULATOR_MAX; i++)
-    {
-        uint8_t val = 0;
-        if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CID4, &val, 1))
-        {
-            max77620_regulator_config_fps(i);
-            max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
-            
-            if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) {
-                max77620_regulator_enable(i, 1);
-            }
-        }       
-    }
-    
-    uint8_t val = 4;
-    i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1);
-}
-
-void max77620_low_battery_monitor_config()
-{
-    uint8_t val = (MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N);
-    i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
-}

fusee/fusee-primary/fusee-primary-main/src/max7762x.h

@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_MAX7762X_H_
-#define FUSEE_MAX7762X_H_
-
-/*
-* Switch Power domains (max77620):
-* Name  | Usage         | uV step | uV min | uV default | uV max  | Init
-*-------+---------------+---------+--------+------------+---------+------------------
-*  sd0  | core          | 12500   | 600000 |  625000    | 1400000 | 1.125V (pkg1.1)
-*  sd1  | SDRAM         | 12500   | 600000 | 1125000    | 1125000 | 1.1V   (pkg1.1)
-*  sd2  | ldo{0-1, 7-8} | 12500   | 600000 | 1325000    | 1350000 | 1.325V (pcv)
-*  sd3  | 1.8V general  | 12500   | 600000 | 1800000    | 1800000 |
-*  ldo0 | Display Panel | 25000   | 800000 | 1200000    | 1200000 | 1.2V   (pkg1.1)
-*  ldo1 | XUSB, PCIE    | 25000   | 800000 | 1050000    | 1050000 | 1.05V  (pcv)
-*  ldo2 | SDMMC1        | 50000   | 800000 | 1800000    | 3300000 |
-*  ldo3 |               | 50000   | 800000 | 3100000    | 3100000 |
-*  ldo4 | RTC           | 12500   | 800000 |  850000    |  850000 |
-*  ldo5 |               | 50000   | 800000 | 1800000    | 1800000 |
-*  ldo6 |               | 50000   | 800000 | 2900000    | 2900000 |
-*  ldo7 | XUSB          | 50000   | 800000 | 1050000    | 1050000 |
-*  ldo8 | XUSB, DC      | 50000   | 800000 | 1050000    | 1050000 |
-*/
-
-/*
-* MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode
-* MAX77620_REG_GPIOx: 0x9 sets output and enable
-*/
-
-/*! MAX77620 partitions. */
-#define REGULATOR_SD0 0
-#define REGULATOR_SD1 1
-#define REGULATOR_SD2 2
-#define REGULATOR_SD3 3
-#define REGULATOR_LDO0 4
-#define REGULATOR_LDO1 5
-#define REGULATOR_LDO2 6
-#define REGULATOR_LDO3 7
-#define REGULATOR_LDO4 8
-#define REGULATOR_LDO5 9
-#define REGULATOR_LDO6 10
-#define REGULATOR_LDO7 11
-#define REGULATOR_LDO8 12
-#define REGULATOR_MAX 12
-
-int max77620_regulator_get_status(uint32_t id);
-int max77620_regulator_config_fps(uint32_t id);
-int max77620_regulator_set_voltage(uint32_t id, uint32_t mv);
-int max77620_regulator_enable(uint32_t id, int enable);
-void max77620_config_default();
-void max77620_low_battery_monitor_config();
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/max77812.h

@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_MAX77812_H_
-#define FUSEE_MAX77812_H_
-
-#define MAX77812_REG_RESET          0x00
-#define MAX77812_REG_INT_SRC        0x01
-#define MAX77812_REG_INT_SRC_M      0x02
-#define MAX77812_REG_TOPSYS_INT     0x03
-#define MAX77812_REG_TOPSYS_INT_M   0x04
-#define MAX77812_REG_TOPSYS_STAT    0x05
-#define MAX77812_REG_EN_CTRL        0x06
-#define MAX77812_REG_STUP_DLY1      0x07
-#define MAX77812_REG_STUP_DLY2      0x08
-#define MAX77812_REG_STUP_DLY3      0x09
-#define MAX77812_REG_SHDN_DLY1      0x0A
-#define MAX77812_REG_SHDN_DLY2      0x0B
-#define MAX77812_REG_SHDN_DLY3      0x0C
-#define MAX77812_REG_SHDN_DLY4      0x0D
-#define MAX77812_REG_WDTRSTB_DEB    0x0E
-#define MAX77812_REG_GPI_FUNC       0x0F
-#define MAX77812_REG_GPI_DEB1       0x10
-#define MAX77812_REG_GPI_DEB2       0x11
-#define MAX77812_REG_GPI_PD_CTRL    0x12
-#define MAX77812_REG_PROT_CFG       0x13
-#define MAX77812_REG_I2C_CFG        0x15
-#define MAX77812_REG_BUCK_INT       0x20
-#define MAX77812_REG_BUCK_INT_M     0x21
-#define MAX77812_REG_BUCK_STAT      0x22
-#define MAX77812_REG_M1_VOUT        0x23
-#define MAX77812_REG_M2_VOUT        0x24
-#define MAX77812_REG_M3_VOUT        0x25
-#define MAX77812_REG_M4_VOUT        0x26
-#define MAX77812_REG_M1_VOUT_D      0x27
-#define MAX77812_REG_M2_VOUT_D      0x28
-#define MAX77812_REG_M3_VOUT_D      0x29
-#define MAX77812_REG_M4_VOUT_D      0x2A
-#define MAX77812_REG_M1_VOUT_S      0x2B
-#define MAX77812_REG_M2_VOUT_S      0x2C
-#define MAX77812_REG_M3_VOUT_S      0x2D
-#define MAX77812_REG_M4_VOUT_S      0x2E
-#define MAX77812_REG_M1_CGF         0x2F
-#define MAX77812_REG_M2_CGF         0x30
-#define MAX77812_REG_M3_CGF         0x31
-#define MAX77812_REG_M4_CGF         0x32
-#define MAX77812_REG_GLB_CFG1       0x33
-#define MAX77812_REG_GLB_CFG2       0x34
-#define MAX77812_REG_GLB_CFG3       0x35
-
-#define MAX77812_REG_EN_CTRL_MASK(n)        BIT(n)
-#define MAX77812_START_SLEW_RATE_MASK       0x07
-#define MAX77812_SHDN_SLEW_RATE_MASK        0x70
-#define MAX77812_RAMPDOWN_SLEW_RATE_MASK    0x07
-#define MAX77812_RAMPUP_SLEW_RATE_MASK      0x70
-
-#define MAX77812_VOUT_MASK          0xFF
-#define MAX77812_VOUT_N_VOLTAGE     0xFF
-#define MAX77812_VOUT_VMIN          250000
-#define MAX77812_VOUT_VMAX          1525000
-#define MAX77812_VOUT_STEP          5000
-
-#define MAX77812_REGULATOR_ID_M1    0
-#define MAX77812_REGULATOR_ID_M2    1
-#define MAX77812_REGULATOR_ID_M3    2
-#define MAX77812_REGULATOR_ID_M4    3
-
-#endif

fusee/fusee-primary/fusee-primary-main/src/mc.c

@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "mc.h"
-#include "car.h"
-#include "timers.h"
-
-void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock)
-{
-    MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom;
-    MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
-    
-    if (lock)
-        MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1;
-}
-
-void mc_config_carveout()
-{
-    *(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
-    
-    MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
-
-    mc_config_tsec_carveout(0, 0, true);
-
-    MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
-
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
-}
-
-void mc_config_carveout_finalize()
-{
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
-}
-
-void mc_enable_ahb_redirect()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000);
-    
-    MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000;
-    MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000;
-}
-
-void mc_disable_ahb_redirect()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    
-    MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000;
-    MAKE_MC_REG(MC_IRAM_TOM) = 0;
-    
-    car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF;
-}
-
-void mc_enable()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    
-    /* Set EMC clock source. */
-    car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000);
-    
-    /* Enable MIPI CAL clock. */
-    car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000);
-    
-    /* Enable MC clock. */
-    car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1);
-
-    /* Enable EMC DLL clock. */
-    car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000);
-    
-    /* Clear EMC and MC reset. */
-    /* NOTE: [4.0.0+] This was changed to use the right register. */
-    /* car->rst_dev_h_set = 0x2000001; */
-    car->rst_dev_h_clr = 0x2000001; 
-    udelay(5);
-
-    mc_disable_ahb_redirect();
-}

fusee/fusee-primary/fusee-primary-main/src/mc.h

@@ -1,606 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_MC_H_
-#define FUSEE_MC_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#define MC_BASE  0x70019000
-#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
-
-#define MC_INTSTATUS                                            0x0
-#define MC_INTMASK                                              0x4
-#define MC_ERR_STATUS                                           0x8
-#define MC_ERR_ADR                                              0xc
-#define MC_SMMU_CONFIG                                          0x10
-#define MC_SMMU_TLB_CONFIG                                      0x14
-#define MC_SMMU_PTC_CONFIG                                      0x18
-#define MC_SMMU_PTB_ASID                                        0x1c
-#define MC_SMMU_PTB_DATA                                        0x20
-#define MC_SMMU_TLB_FLUSH                                       0x30
-#define MC_SMMU_PTC_FLUSH                                       0x34
-#define MC_SMMU_ASID_SECURITY                                   0x38
-#define MC_SMMU_ASID_SECURITY_1                                 0x3c
-#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
-#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
-#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
-#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
-#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
-#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
-#define MC_SMMU_AFI_ASID                                        0x238
-#define MC_SMMU_AVPC_ASID                                       0x23c
-#define MC_SMMU_TSEC_ASID                                       0x294
-#define MC_SMMU_PPCS1_ASID                                      0x298
-#define MC_SMMU_TRANSLATION_ENABLE_0                            0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1                            0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2                            0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3                            0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4                            0xb98
-#define MC_PCFIFO_CLIENT_CONFIG0                                0xdd0
-#define MC_PCFIFO_CLIENT_CONFIG1                                0xdd4
-#define MC_PCFIFO_CLIENT_CONFIG2                                0xdd8
-#define MC_PCFIFO_CLIENT_CONFIG3                                0xddc
-#define MC_PCFIFO_CLIENT_CONFIG4                                0xde0
-#define MC_EMEM_CFG                                             0x50
-#define MC_EMEM_ADR_CFG                                         0x54
-#define MC_EMEM_ADR_CFG_DEV0                                    0x58
-#define MC_EMEM_ADR_CFG_DEV1                                    0x5c
-#define MC_EMEM_ADR_CFG_CHANNEL_MASK                            0x60
-#define MC_EMEM_ADR_CFG_BANK_MASK_0                             0x64
-#define MC_EMEM_ADR_CFG_BANK_MASK_1                             0x68
-#define MC_EMEM_ADR_CFG_BANK_MASK_2                             0x6c
-#define MC_SECURITY_CFG0                                        0x70
-#define MC_SECURITY_CFG1                                        0x74
-#define MC_SECURITY_CFG3                                        0x9bc
-#define MC_SECURITY_RSV                                         0x7c
-#define MC_EMEM_ARB_CFG                                         0x90
-#define MC_EMEM_ARB_OUTSTANDING_REQ                             0x94
-#define MC_EMEM_ARB_TIMING_RCD                                  0x98
-#define MC_EMEM_ARB_TIMING_RP                                   0x9c
-#define MC_EMEM_ARB_TIMING_RC                                   0xa0
-#define MC_EMEM_ARB_TIMING_RAS                                  0xa4
-#define MC_EMEM_ARB_TIMING_FAW                                  0xa8
-#define MC_EMEM_ARB_TIMING_RRD                                  0xac
-#define MC_EMEM_ARB_TIMING_RAP2PRE                              0xb0
-#define MC_EMEM_ARB_TIMING_WAP2PRE                              0xb4
-#define MC_EMEM_ARB_TIMING_R2R                                  0xb8
-#define MC_EMEM_ARB_TIMING_W2W                                  0xbc
-#define MC_EMEM_ARB_TIMING_R2W                                  0xc0
-#define MC_EMEM_ARB_TIMING_W2R                                  0xc4
-#define MC_EMEM_ARB_TIMING_RFCPB                                0x6c0
-#define MC_EMEM_ARB_TIMING_CCDMW                                0x6c4
-#define MC_EMEM_ARB_REFPB_HP_CTRL                               0x6f0
-#define MC_EMEM_ARB_REFPB_BANK_CTRL                             0x6f4
-#define MC_EMEM_ARB_DA_TURNS                                    0xd0
-#define MC_EMEM_ARB_DA_COVERS                                   0xd4
-#define MC_EMEM_ARB_MISC0                                       0xd8
-#define MC_EMEM_ARB_MISC1                                       0xdc
-#define MC_EMEM_ARB_MISC2                                       0xc8
-#define MC_EMEM_ARB_RING1_THROTTLE                              0xe0
-#define MC_EMEM_ARB_RING3_THROTTLE                              0xe4
-#define MC_EMEM_ARB_NISO_THROTTLE                               0x6b0
-#define MC_EMEM_ARB_OVERRIDE                                    0xe8
-#define MC_EMEM_ARB_RSV                                         0xec
-#define MC_CLKEN_OVERRIDE                                       0xf4
-#define MC_TIMING_CONTROL_DBG                                   0xf8
-#define MC_TIMING_CONTROL                                       0xfc
-#define MC_STAT_CONTROL                                         0x100
-#define MC_STAT_STATUS                                          0x104
-#define MC_STAT_EMC_CLOCK_LIMIT                                 0x108
-#define MC_STAT_EMC_CLOCK_LIMIT_MSBS                            0x10c
-#define MC_STAT_EMC_CLOCKS                                      0x110
-#define MC_STAT_EMC_CLOCKS_MSBS                                 0x114
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO                    0x118
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO                    0x158
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI                    0x11c
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI                    0x15c
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER                 0xa20
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER                 0xa24
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO            0x198
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO            0x1a8
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI            0x19c
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI            0x1ac
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER         0xa28
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER         0xa2c
-#define MC_STAT_EMC_FILTER_SET0_ASID                            0x1a0
-#define MC_STAT_EMC_FILTER_SET1_ASID                            0x1b0
-#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT                     0x120
-#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT                     0x160
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_0                        0x128
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_0                        0x168
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_1                        0x12c
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_1                        0x16c
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_2                        0x130
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_2                        0x170
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_3                        0x134
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_4                        0xb88
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_3                        0x174
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_4                        0xb8c
-#define MC_STAT_EMC_SET0_COUNT                                  0x138
-#define MC_STAT_EMC_SET0_COUNT_MSBS                             0x13c
-#define MC_STAT_EMC_SET1_COUNT                                  0x178
-#define MC_STAT_EMC_SET1_COUNT_MSBS                             0x17c
-#define MC_STAT_EMC_SET0_SLACK_ACCUM                            0x140
-#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS                       0x144
-#define MC_STAT_EMC_SET1_SLACK_ACCUM                            0x180
-#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS                       0x184
-#define MC_STAT_EMC_SET0_HISTO_COUNT                            0x148
-#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS                       0x14c
-#define MC_STAT_EMC_SET1_HISTO_COUNT                            0x188
-#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS                       0x18c
-#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED                 0x150
-#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED                 0x190
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT                       0x1b8
-#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS                   0x1bc
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT                       0x1c8
-#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS                   0x1cc
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT            0x1c0
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT            0x1d0
-#define MC_CLIENT_HOTRESET_CTRL                                 0x200
-#define MC_CLIENT_HOTRESET_CTRL_1                               0x970
-#define MC_CLIENT_HOTRESET_STATUS                               0x204
-#define MC_CLIENT_HOTRESET_STATUS_1                             0x974
-#define MC_EMEM_ARB_ISOCHRONOUS_0                               0x208
-#define MC_EMEM_ARB_ISOCHRONOUS_1                               0x20c
-#define MC_EMEM_ARB_ISOCHRONOUS_2                               0x210
-#define MC_EMEM_ARB_ISOCHRONOUS_3                               0x214
-#define MC_EMEM_ARB_ISOCHRONOUS_4                               0xb94
-#define MC_EMEM_ARB_HYSTERESIS_0                                0x218
-#define MC_EMEM_ARB_HYSTERESIS_1                                0x21c
-#define MC_EMEM_ARB_HYSTERESIS_2                                0x220
-#define MC_EMEM_ARB_HYSTERESIS_3                                0x224
-#define MC_EMEM_ARB_HYSTERESIS_4                                0xb84
-#define MC_EMEM_ARB_DHYSTERESIS_0                               0xbb0
-#define MC_EMEM_ARB_DHYSTERESIS_1                               0xbb4
-#define MC_EMEM_ARB_DHYSTERESIS_2                               0xbb8
-#define MC_EMEM_ARB_DHYSTERESIS_3                               0xbbc
-#define MC_EMEM_ARB_DHYSTERESIS_4                               0xbc0
-#define MC_EMEM_ARB_DHYST_CTRL                                  0xbcc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0                        0xbd0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1                        0xbd4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2                        0xbd8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3                        0xbdc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4                        0xbe0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5                        0xbe4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6                        0xbe8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7                        0xbec
-#define MC_RESERVED_RSV                                         0x3fc
-#define MC_DISB_EXTRA_SNAP_LEVELS                               0x408
-#define MC_APB_EXTRA_SNAP_LEVELS                                0x2a4
-#define MC_AHB_EXTRA_SNAP_LEVELS                                0x2a0
-#define MC_USBD_EXTRA_SNAP_LEVELS                               0xa18
-#define MC_ISP_EXTRA_SNAP_LEVELS                                0xa08
-#define MC_AUD_EXTRA_SNAP_LEVELS                                0xa10
-#define MC_MSE_EXTRA_SNAP_LEVELS                                0x40c
-#define MC_GK2_EXTRA_SNAP_LEVELS                                0xa40
-#define MC_A9AVPPC_EXTRA_SNAP_LEVELS                            0x414
-#define MC_FTOP_EXTRA_SNAP_LEVELS                               0x2bc
-#define MC_JPG_EXTRA_SNAP_LEVELS                                0xa3c
-#define MC_HOST_EXTRA_SNAP_LEVELS                               0xa14
-#define MC_SAX_EXTRA_SNAP_LEVELS                                0x2c0
-#define MC_DIS_EXTRA_SNAP_LEVELS                                0x2ac
-#define MC_VICPC_EXTRA_SNAP_LEVELS                              0xa1c
-#define MC_HDAPC_EXTRA_SNAP_LEVELS                              0xa48
-#define MC_AVP_EXTRA_SNAP_LEVELS                                0x2a8
-#define MC_USBX_EXTRA_SNAP_LEVELS                               0x404
-#define MC_PCX_EXTRA_SNAP_LEVELS                                0x2b8
-#define MC_SD_EXTRA_SNAP_LEVELS                                 0xa04
-#define MC_DFD_EXTRA_SNAP_LEVELS                                0xa4c
-#define MC_VE_EXTRA_SNAP_LEVELS                                 0x2d8
-#define MC_GK_EXTRA_SNAP_LEVELS                                 0xa00
-#define MC_VE2_EXTRA_SNAP_LEVELS                                0x410
-#define MC_SDM_EXTRA_SNAP_LEVELS                                0xa44
-#define MC_VIDEO_PROTECT_BOM                                    0x648
-#define MC_VIDEO_PROTECT_SIZE_MB                                0x64c
-#define MC_VIDEO_PROTECT_BOM_ADR_HI                             0x978
-#define MC_VIDEO_PROTECT_REG_CTRL                               0x650
-#define MC_ERR_VPR_STATUS                                       0x654
-#define MC_ERR_VPR_ADR                                          0x658
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE                           0x418
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE1                          0x590
-#define MC_IRAM_BOM                                             0x65c
-#define MC_IRAM_TOM                                             0x660
-#define MC_IRAM_ADR_HI                                          0x980
-#define MC_IRAM_REG_CTRL                                        0x964
-#define MC_EMEM_CFG_ACCESS_CTRL                                 0x664
-#define MC_TZ_SECURITY_CTRL                                     0x668
-#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3                       0x66c
-#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO                        0x6b4
-#define MC_EMEM_ARB_RING0_THROTTLE_MASK                         0x6bc
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK                          0x6b8
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1                        0xb80
-#define MC_SEC_CARVEOUT_BOM                                     0x670
-#define MC_SEC_CARVEOUT_SIZE_MB                                 0x674
-#define MC_SEC_CARVEOUT_ADR_HI                                  0x9d4
-#define MC_SEC_CARVEOUT_REG_CTRL                                0x678
-#define MC_ERR_SEC_STATUS                                       0x67c
-#define MC_ERR_SEC_ADR                                          0x680
-#define MC_PC_IDLE_CLOCK_GATE_CONFIG                            0x684
-#define MC_STUTTER_CONTROL                                      0x688
-#define MC_RESERVED_RSV_1                                       0x958
-#define MC_DVFS_PIPE_SELECT                                     0x95c
-#define MC_AHB_PTSA_MIN                                         0x4e0
-#define MC_AUD_PTSA_MIN                                         0x54c
-#define MC_MLL_MPCORER_PTSA_RATE                                0x44c
-#define MC_RING2_PTSA_RATE                                      0x440
-#define MC_USBD_PTSA_RATE                                       0x530
-#define MC_USBX_PTSA_MIN                                        0x528
-#define MC_USBD_PTSA_MIN                                        0x534
-#define MC_APB_PTSA_MAX                                         0x4f0
-#define MC_JPG_PTSA_RATE                                        0x584
-#define MC_DIS_PTSA_MIN                                         0x420
-#define MC_AVP_PTSA_MAX                                         0x4fc
-#define MC_AVP_PTSA_RATE                                        0x4f4
-#define MC_RING1_PTSA_MIN                                       0x480
-#define MC_DIS_PTSA_MAX                                         0x424
-#define MC_SD_PTSA_MAX                                          0x4d8
-#define MC_MSE_PTSA_RATE                                        0x4c4
-#define MC_VICPC_PTSA_MIN                                       0x558
-#define MC_PCX_PTSA_MAX                                         0x4b4
-#define MC_ISP_PTSA_RATE                                        0x4a0
-#define MC_A9AVPPC_PTSA_MIN                                     0x48c
-#define MC_RING2_PTSA_MAX                                       0x448
-#define MC_AUD_PTSA_RATE                                        0x548
-#define MC_HOST_PTSA_MIN                                        0x51c
-#define MC_MLL_MPCORER_PTSA_MAX                                 0x454
-#define MC_SD_PTSA_MIN                                          0x4d4
-#define MC_RING1_PTSA_RATE                                      0x47c
-#define MC_JPG_PTSA_MIN                                         0x588
-#define MC_HDAPC_PTSA_MIN                                       0x62c
-#define MC_AVP_PTSA_MIN                                         0x4f8
-#define MC_JPG_PTSA_MAX                                         0x58c
-#define MC_VE_PTSA_MAX                                          0x43c
-#define MC_DFD_PTSA_MAX                                         0x63c
-#define MC_VICPC_PTSA_RATE                                      0x554
-#define MC_GK_PTSA_MAX                                          0x544
-#define MC_VICPC_PTSA_MAX                                       0x55c
-#define MC_SDM_PTSA_MAX                                         0x624
-#define MC_SAX_PTSA_RATE                                        0x4b8
-#define MC_PCX_PTSA_MIN                                         0x4b0
-#define MC_APB_PTSA_MIN                                         0x4ec
-#define MC_GK2_PTSA_MIN                                         0x614
-#define MC_PCX_PTSA_RATE                                        0x4ac
-#define MC_RING1_PTSA_MAX                                       0x484
-#define MC_HDAPC_PTSA_RATE                                      0x628
-#define MC_MLL_MPCORER_PTSA_MIN                                 0x450
-#define MC_GK2_PTSA_MAX                                         0x618
-#define MC_AUD_PTSA_MAX                                         0x550
-#define MC_GK2_PTSA_RATE                                        0x610
-#define MC_ISP_PTSA_MAX                                         0x4a8
-#define MC_DISB_PTSA_RATE                                       0x428
-#define MC_VE2_PTSA_MAX                                         0x49c
-#define MC_DFD_PTSA_MIN                                         0x638
-#define MC_FTOP_PTSA_RATE                                       0x50c
-#define MC_A9AVPPC_PTSA_RATE                                    0x488
-#define MC_VE2_PTSA_MIN                                         0x498
-#define MC_USBX_PTSA_MAX                                        0x52c
-#define MC_DIS_PTSA_RATE                                        0x41c
-#define MC_USBD_PTSA_MAX                                        0x538
-#define MC_A9AVPPC_PTSA_MAX                                     0x490
-#define MC_USBX_PTSA_RATE                                       0x524
-#define MC_FTOP_PTSA_MAX                                        0x514
-#define MC_HDAPC_PTSA_MAX                                       0x630
-#define MC_SD_PTSA_RATE                                         0x4d0
-#define MC_DFD_PTSA_RATE                                        0x634
-#define MC_FTOP_PTSA_MIN                                        0x510
-#define MC_SDM_PTSA_RATE                                        0x61c
-#define MC_AHB_PTSA_RATE                                        0x4dc
-#define MC_SMMU_SMMU_PTSA_MAX                                   0x460
-#define MC_RING2_PTSA_MIN                                       0x444
-#define MC_SDM_PTSA_MIN                                         0x620
-#define MC_APB_PTSA_RATE                                        0x4e8
-#define MC_MSE_PTSA_MIN                                         0x4c8
-#define MC_HOST_PTSA_RATE                                       0x518
-#define MC_VE_PTSA_RATE                                         0x434
-#define MC_AHB_PTSA_MAX                                         0x4e4
-#define MC_SAX_PTSA_MIN                                         0x4bc
-#define MC_SMMU_SMMU_PTSA_MIN                                   0x45c
-#define MC_ISP_PTSA_MIN                                         0x4a4
-#define MC_HOST_PTSA_MAX                                        0x520
-#define MC_SAX_PTSA_MAX                                         0x4c0
-#define MC_VE_PTSA_MIN                                          0x438
-#define MC_GK_PTSA_MIN                                          0x540
-#define MC_MSE_PTSA_MAX                                         0x4cc
-#define MC_DISB_PTSA_MAX                                        0x430
-#define MC_DISB_PTSA_MIN                                        0x42c
-#define MC_SMMU_SMMU_PTSA_RATE                                  0x458
-#define MC_VE2_PTSA_RATE                                        0x494
-#define MC_GK_PTSA_RATE                                         0x53c
-#define MC_PTSA_GRANT_DECREMENT                                 0x960
-#define MC_LATENCY_ALLOWANCE_AVPC_0                             0x2e4
-#define MC_LATENCY_ALLOWANCE_AXIAP_0                            0x3a0
-#define MC_LATENCY_ALLOWANCE_XUSB_1                             0x380
-#define MC_LATENCY_ALLOWANCE_ISP2B_0                            0x384
-#define MC_LATENCY_ALLOWANCE_SDMMCAA_0                          0x3bc
-#define MC_LATENCY_ALLOWANCE_SDMMCA_0                           0x3b8
-#define MC_LATENCY_ALLOWANCE_ISP2_0                             0x370
-#define MC_LATENCY_ALLOWANCE_SE_0                               0x3e0
-#define MC_LATENCY_ALLOWANCE_ISP2_1                             0x374
-#define MC_LATENCY_ALLOWANCE_DC_0                               0x2e8
-#define MC_LATENCY_ALLOWANCE_VIC_0                              0x394
-#define MC_LATENCY_ALLOWANCE_DCB_1                              0x2f8
-#define MC_LATENCY_ALLOWANCE_NVDEC_0                            0x3d8
-#define MC_LATENCY_ALLOWANCE_DCB_2                              0x2fc
-#define MC_LATENCY_ALLOWANCE_TSEC_0                             0x390
-#define MC_LATENCY_ALLOWANCE_DC_2                               0x2f0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB                  0x694
-#define MC_LATENCY_ALLOWANCE_PPCS_1                             0x348
-#define MC_LATENCY_ALLOWANCE_XUSB_0                             0x37c
-#define MC_LATENCY_ALLOWANCE_PPCS_0                             0x344
-#define MC_LATENCY_ALLOWANCE_TSECB_0                            0x3f0
-#define MC_LATENCY_ALLOWANCE_AFI_0                              0x2e0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B                   0x698
-#define MC_LATENCY_ALLOWANCE_DC_1                               0x2ec
-#define MC_LATENCY_ALLOWANCE_APE_0                              0x3dc
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C                   0x6a0
-#define MC_LATENCY_ALLOWANCE_A9AVP_0                            0x3a4
-#define MC_LATENCY_ALLOWANCE_GPU2_0                             0x3e8
-#define MC_LATENCY_ALLOWANCE_DCB_0                              0x2f4
-#define MC_LATENCY_ALLOWANCE_HC_1                               0x314
-#define MC_LATENCY_ALLOWANCE_SDMMC_0                            0x3c0
-#define MC_LATENCY_ALLOWANCE_NVJPG_0                            0x3e4
-#define MC_LATENCY_ALLOWANCE_PTC_0                              0x34c
-#define MC_LATENCY_ALLOWANCE_ETR_0                              0x3ec
-#define MC_LATENCY_ALLOWANCE_MPCORE_0                           0x320
-#define MC_LATENCY_ALLOWANCE_VI2_0                              0x398
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB                  0x69c
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB                  0x6a4
-#define MC_LATENCY_ALLOWANCE_SATA_0                             0x350
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A                   0x690
-#define MC_LATENCY_ALLOWANCE_HC_0                               0x310
-#define MC_LATENCY_ALLOWANCE_DC_3                               0x3c8
-#define MC_LATENCY_ALLOWANCE_GPU_0                              0x3ac
-#define MC_LATENCY_ALLOWANCE_SDMMCAB_0                          0x3c4
-#define MC_LATENCY_ALLOWANCE_ISP2B_1                            0x388
-#define MC_LATENCY_ALLOWANCE_NVENC_0                            0x328
-#define MC_LATENCY_ALLOWANCE_HDA_0                              0x318
-#define MC_MIN_LENGTH_APE_0                                     0xb34
-#define MC_MIN_LENGTH_DCB_2                                     0x8a8
-#define MC_MIN_LENGTH_A9AVP_0                                   0x950
-#define MC_MIN_LENGTH_TSEC_0                                    0x93c
-#define MC_MIN_LENGTH_DC_1                                      0x898
-#define MC_MIN_LENGTH_AXIAP_0                                   0x94c
-#define MC_MIN_LENGTH_ISP2B_0                                   0x930
-#define MC_MIN_LENGTH_VI2_0                                     0x944
-#define MC_MIN_LENGTH_DCB_0                                     0x8a0
-#define MC_MIN_LENGTH_DCB_1                                     0x8a4
-#define MC_MIN_LENGTH_PPCS_1                                    0x8f4
-#define MC_MIN_LENGTH_NVJPG_0                                   0xb3c
-#define MC_MIN_LENGTH_HDA_0                                     0x8c4
-#define MC_MIN_LENGTH_NVENC_0                                   0x8d4
-#define MC_MIN_LENGTH_SDMMC_0                                   0xb18
-#define MC_MIN_LENGTH_ISP2B_1                                   0x934
-#define MC_MIN_LENGTH_HC_1                                      0x8c0
-#define MC_MIN_LENGTH_DC_3                                      0xb20
-#define MC_MIN_LENGTH_AVPC_0                                    0x890
-#define MC_MIN_LENGTH_VIC_0                                     0x940
-#define MC_MIN_LENGTH_ISP2_0                                    0x91c
-#define MC_MIN_LENGTH_HC_0                                      0x8bc
-#define MC_MIN_LENGTH_SE_0                                      0xb38
-#define MC_MIN_LENGTH_NVDEC_0                                   0xb30
-#define MC_MIN_LENGTH_SATA_0                                    0x8fc
-#define MC_MIN_LENGTH_DC_0                                      0x894
-#define MC_MIN_LENGTH_XUSB_1                                    0x92c
-#define MC_MIN_LENGTH_DC_2                                      0x89c
-#define MC_MIN_LENGTH_SDMMCAA_0                                 0xb14
-#define MC_MIN_LENGTH_GPU_0                                     0xb04
-#define MC_MIN_LENGTH_ETR_0                                     0xb44
-#define MC_MIN_LENGTH_AFI_0                                     0x88c
-#define MC_MIN_LENGTH_PPCS_0                                    0x8f0
-#define MC_MIN_LENGTH_ISP2_1                                    0x920
-#define MC_MIN_LENGTH_XUSB_0                                    0x928
-#define MC_MIN_LENGTH_MPCORE_0                                  0x8cc
-#define MC_MIN_LENGTH_TSECB_0                                   0xb48
-#define MC_MIN_LENGTH_SDMMCA_0                                  0xb10
-#define MC_MIN_LENGTH_GPU2_0                                    0xb40
-#define MC_MIN_LENGTH_SDMMCAB_0                                 0xb1c
-#define MC_MIN_LENGTH_PTC_0                                     0x8f8
-#define MC_EMEM_ARB_OVERRIDE_1                                  0x968
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0                         0x984
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1                         0x988
-#define MC_EMEM_ARB_STATS_0                                     0x990
-#define MC_EMEM_ARB_STATS_1                                     0x994
-#define MC_MTS_CARVEOUT_BOM                                     0x9a0
-#define MC_MTS_CARVEOUT_SIZE_MB                                 0x9a4
-#define MC_MTS_CARVEOUT_ADR_HI                                  0x9a8
-#define MC_MTS_CARVEOUT_REG_CTRL                                0x9ac
-#define MC_ERR_MTS_STATUS                                       0x9b0
-#define MC_ERR_MTS_ADR                                          0x9b4
-#define MC_ERR_GENERALIZED_CARVEOUT_STATUS                      0xc00
-#define MC_ERR_GENERALIZED_CARVEOUT_ADR                         0xc04
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2     0xd74
-#define MC_SECURITY_CARVEOUT4_CFG0                              0xcf8
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2                    0xd10
-#define MC_SECURITY_CARVEOUT4_SIZE_128KB                        0xd04
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4                    0xc28
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1     0xc30
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4     0xc8c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0     0xd1c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1     0xd70
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0     0xc2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4     0xd7c
-#define MC_SECURITY_CARVEOUT3_SIZE_128KB                        0xcb4
-#define MC_SECURITY_CARVEOUT2_CFG0                              0xc58
-#define MC_SECURITY_CARVEOUT1_CFG0                              0xc08
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2     0xc84
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0                    0xc68
-#define MC_SECURITY_CARVEOUT3_BOM                               0xcac
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2                    0xc70
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3     0xd78
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0     0xc7c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4                    0xd18
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1                    0xcbc
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3     0xc38
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2     0xc34
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2                    0xcc0
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2                    0xd60
-#define MC_SECURITY_CARVEOUT3_CFG0                              0xca8
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0                    0xcb8
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3     0xc88
-#define MC_SECURITY_CARVEOUT2_SIZE_128KB                        0xc64
-#define MC_SECURITY_CARVEOUT5_BOM_HI                            0xd50
-#define MC_SECURITY_CARVEOUT1_SIZE_128KB                        0xc14
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3                    0xd14
-#define MC_SECURITY_CARVEOUT1_BOM                               0xc0c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4     0xd2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4                    0xd68
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4                    0xcc8
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0                    0xd58
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2     0xd24
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3                    0xcc4
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4                    0xc78
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1                    0xc1c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0                    0xc18
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3     0xd28
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1                    0xd5c
-#define MC_SECURITY_CARVEOUT3_BOM_HI                            0xcb0
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3     0xcd8
-#define MC_SECURITY_CARVEOUT2_BOM_HI                            0xc60
-#define MC_SECURITY_CARVEOUT4_BOM_HI                            0xd00
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3                    0xd64
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4     0xcdc
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1     0xc80
-#define MC_SECURITY_CARVEOUT5_SIZE_128KB                        0xd54
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1     0xd20
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2     0xcd4
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1                    0xd0c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3                    0xc74
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0     0xccc
-#define MC_SECURITY_CARVEOUT4_BOM                               0xcfc
-#define MC_SECURITY_CARVEOUT5_CFG0                              0xd48
-#define MC_SECURITY_CARVEOUT2_BOM                               0xc5c
-#define MC_SECURITY_CARVEOUT5_BOM                               0xd4c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3                    0xc24
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0     0xd6c
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1     0xcd0
-#define MC_SECURITY_CARVEOUT1_BOM_HI                            0xc10
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2                    0xc20
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4     0xc3c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1                    0xc6c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0                    0xd08
-#define MC_ERR_APB_ASID_UPDATE_STATUS                           0x9d0
-#define MC_DA_CONFIG0                                           0x9dc
-#define MC_UNTRANSLATED_REGION_CHECK                            0x948
-
-/* Memory Controller clients */
-#define CLIENT_ACCESS_NUM_CLIENTS   32
-typedef enum {
-    /* _ACCESS0 */
-    CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    
-    /* _ACCESS1 */
-    CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    
-    /* _ACCESS2 */
-    CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    
-    /* _ACCESS3 */
-    CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    
-    /* _ACCESS4 */
-    CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
-} McClient;
-
-void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
-void mc_config_carveout();
-void mc_config_carveout_finalize();
-void mc_enable_ahb_redirect();
-void mc_disable_ahb_redirect();
-void mc_enable();
-
-#endif