niklascfw/hekate
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497 Commits

Author SHA1 Message Date
CTCaer
b3194f6379 bdk: mc: fix warning for arbiter check 2025-04-30 09:14:32 +03:00
CTCaer
129a70c32d bdk: se: heap is not used anymore 2025-04-30 09:13:55 +03:00
CTCaer
811971dfa0 bdk: als: no need to check above 255 with u8 2025-04-30 09:13:19 +03:00
CTCaer
08872325c8 bdk: se: add 0 byte sha256 support 2025-04-30 08:15:15 +03:00
CTCaer
c07a155cc1 bdk: small refactoring 2025-04-30 08:14:32 +03:00
CTCaer
1d75c30c61 bdk: display: update color mode definitions 2025-04-30 08:11:51 +03:00
CTCaer
b9496f81b1 bdk: sdmmc: add extention regs read/parse 2025-01-24 16:42:14 +02:00
CTCaer
94b36f658c bdk: utils: added qsort compare functions 
int qsort_compare_int(const void *a, const void *b);
int qsort_compare_char(const void *a, const void *b);
int qsort_compare_char_case(const void *a, const void *b);
 2025-01-24 16:33:51 +02:00
CTCaer
7ac47b9ffe bdk: dirlist: switch to alphabetical ordering 2025-01-24 15:46:27 +02:00
CTCaer
595ac2c11e bdk: sdmmc: refactor error checking on rw 
And also check if card status is ok after a read/write.
 2025-01-24 15:44:33 +02:00
CTCaer
dcd4e4c4ec bdk: sdmmc: check that cmd timed out if SDSC 
Instead of assuming that, check it.
This fix will make SDUC not to be assumed as SDSC.
 2025-01-24 15:40:38 +02:00
CTCaer
018ed3f38a bdk: sdmmc: update unstuff_bits to use mod 
Since unstuff_bits only supports 128bits, instead of subtracting the correct amount of bits with the offset array, use % 128.
 2025-01-24 15:39:17 +02:00
CTCaer
e030a4ad6d bdk: sdmmc: small refactor 2025-01-24 15:30:10 +02:00
CTCaer
5ce22a67dc bdk: sdmmc: check for out bounds access 2025-01-24 15:21:20 +02:00
CTCaer
6c958f16b8 bdk: ff: check for cltbl malloc success 2025-01-24 15:18:35 +02:00
CTCaer
9ba94bae2d bdk: se: remove malloc usage 2025-01-24 15:15:03 +02:00
CTCaer
a47a6d32c6 bdk: display: remove malloc usage 2025-01-24 15:13:28 +02:00
CTCaer
14413ae6bd bdk: timer: restore rtc timer spinlock 2024-10-10 18:22:03 +03:00
CTCaer
d2fc6379c6 bdk: utils: improve dirlist 
Stop doing unnecessary copies during reordering and use pointers for that.
 2024-10-09 15:14:44 +03:00
CTCaer
edf00d8e51 bdk: bpmp: add state set function 
Some states are controlled via software. So add a function for that.
 2024-10-04 21:54:58 +03:00
CTCaer
1a98e3a702 bdk: irq: disable irq if handler error 2024-10-04 21:53:17 +03:00
CTCaer
8bf3bee08b bdk: uart: fix fifo clear 
- Do not clear fifo for everything if not needed
- Correct fifo clear checks
 2024-10-04 21:52:24 +03:00
CTCaer
f2be59888b bdk: add irq header to bdk header 2024-10-04 21:48:44 +03:00
CTCaer
5c77601f7a bdk: ums: always allow finish reply 
Parse scsi cmd failures are handled internally.
 2024-10-04 21:47:26 +03:00
CTCaer
9e239df39e bdk: constify various args 2024-10-04 21:45:57 +03:00
CTCaer
b1bc6ebdd8 bdk: joycon: utilize packet id per joycon 
Also fix a possible infinite loop
 2024-10-04 21:39:35 +03:00
CTCaer
716cfbfbaf bdk: sdram: refactor init 2024-07-02 18:02:05 +03:00
CTCaer
e47b6ec19b bdk: hwinit: display changes 
Do not display ldo0 if enabled here as it's not needed.
Make sure PLLP_OUTB is properly reset in case of coming out of warmboot.
 2024-07-02 17:59:14 +03:00
CTCaer
acb3997a7d bdk: hwinit: reorder no io power 
And make sure sdmmc iopower is not enabled after vdd disable.
 2024-07-02 17:56:20 +03:00
CTCaer
4c5cc6d567 bdk: display: small refactor 2024-07-02 17:52:12 +03:00
CTCaer
75a4a8ba1d bdk: sdmmc: remove higher power limits 
UHS-I Cards force a max of 1.44W even if higher modes are selected.
This does not change functionality, so remove them as unused.
 2024-06-10 13:37:28 +03:00
CTCaer
a37b5c7841 bdk: sdmmc: no need to raise power limit for HS25 2024-06-10 13:24:07 +03:00
CTCaer
48334779a5 bdk: sdmmc: error reporting changes 
- Correct transfer error message
- Add debug print for deinit
 2024-06-08 17:41:11 +03:00
CTCaer
054c68f251 bdk: hwinit: power on all relevant rails 
Since that doesn't happen via sdram init anymore, do it in hwinit.
It only matters if we came out of warmboot.
 2024-06-08 12:21:15 +03:00
CTCaer
655209bedc bdk: sdram: keep sdmmc1 no iopower state 2024-06-08 12:19:24 +03:00
CTCaer
85eb5489fe bdk: pmc: rename io/det power defines 2024-06-08 12:16:07 +03:00
CTCaer
8b4f776c9d bdk: fan: rename functions and add set from temp 
- Rename functions to proper style (drivername_)
- Add fan_set_from_temp for managing the fan with passed SoC temperature.
 2024-06-07 17:14:05 +03:00
CTCaer
a34206df5b bdk: sdmmc: small changes 
- Log warning for comp pad calibration timeout
- Rename some func/defines
- Increase SDMMC1 power disable wait to 10ms
 No real perceived functionality change.
 2024-06-07 17:09:30 +03:00
CTCaer
4a24fe0b35 bdk: display: add useful functions 
- Window disable
- Window framebuffer address set
- Window framebuffer move to new address
 2024-06-06 06:27:30 +03:00
CTCaer
14c482ddce bdk: display: remove max77620 gpio 7 enable 
It is actually not used at all.
So do not configure it to save power.
 2024-06-05 15:20:27 +03:00
CTCaer
8d49bc3c33 bdk: hwinit: move LDO8 init in regulators init 
And also reorder it above I2C1 init (because of HOAG).
 2024-06-05 01:35:05 +03:00
CTCaer
39c614a3ab bdk: hwinit: move sd2 to hw init 
SD2 powers LDO0/1/8 on T210B01 so there's no need to be in display init.
Also there's not need to power it down first so configure it in one go.
 2024-06-05 01:33:15 +03:00
CTCaer
7652d9cdb1 bdk: display: use mipi cal sw war on T210 also 
As per Nvidia, the pad brick separates clock and data terminations.
This necessitates doing the calibration twice.

Nvidia/Nintendo probably never updated that part on T210 since it's from around
2015/2016. T210B01 is based on 2017 codebase so it has it.
HOS (nvservices, not boot) is probably updated to also do that.
If not, then they should fix it.

There are 0 known issue reports with that on T210, but well.
 2024-06-05 01:11:04 +03:00
CTCaer
48ef1826e9 bdk: display: rename functions 
display_init_framebuffer_pitch -> display_init_window_a_pitch
display_init_framebuffer_pitch_vic -> display_init_window_a_pitch_vic
display_init_framebuffer_pitch_inv -> display_init_window_a_pitch_inv
display_init_framebuffer_block -> display_init_window_a_block
display_init_framebuffer_log -> display_init_window_d_console
display_activate_console -> display_window_d_console_enable
display_deactivate_console -> display_window_d_console_disable
display_init_cursor -> display_cursor_init
display_set_pos_cursor -> display_cursor_set_pos
display_deinit_cursor -> display_cursor_deinit
 2024-06-05 01:00:58 +03:00
CTCaer
4fef1890aa bdk: rename exec_cfg to reg_write_array 
And cfg_op_t to reg_cfg_t.
 2024-06-05 00:49:15 +03:00
CTCaer
320b91a767 bdk: display: return duty for oled panel properly 
For display_get_backlight_brightness.
 2024-06-02 08:23:58 +03:00
CTCaer
c5f6837c35 bdk: display: wait 1 frame after display off cmd 2024-06-02 08:23:13 +03:00
CTCaer
72f980d0f4 bdk: display: fully streamline dc/win setup 
As explained before, Nvidia just grabbed the whole dynamic init and made arrays
of it, without actually optimizing it.
The second part of the streamline aims to fully de-duplicate that.
- Completely remove all already set registers for DC/DISP/WIN.
- Do not touch other windows when a specific window is setup.
- Init Window D also together with A/B/C since code is made for DISPA.
- Add missing increase for syncpt 1.
 2024-06-02 08:22:20 +03:00
CTCaer
b3be7e7a41 bdk: display: use the same HS exit threshold 
No need to use minimum on T210.
Use the same byte clocks as T210B01 to simplify init.
 2024-06-02 08:11:22 +03:00
CTCaer
26c6c6372d bdk: display: rename window setup arrays 
Add window number info and remove the fb naming
 2024-06-02 08:05:50 +03:00