General bugfixes + hardcoded name replacement
This commit is contained in:
@@ -351,7 +351,7 @@ void config_hw()
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clock_enable_se();
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// Enable fuse clock.
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clock_enable_fuse(1);
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clock_enable_fuse(true);
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// Disable fuse programming.
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fuse_disable_program();
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@@ -369,33 +369,30 @@ void config_hw()
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clock_enable_i2c(I2C_1);
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clock_enable_i2c(I2C_5);
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static const clock_t clock_unk1 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0x42C, 0x1F, 0, 0 };
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static const clock_t clock_unk2 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0, 0x1E, 0, 0 };
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clock_enable(&clock_unk1);
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clock_enable(&clock_unk2);
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clock_enable_unk2();
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i2c_init(I2C_1);
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i2c_init(I2C_5);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_CNFGBBC, 0x40);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_ONOFFCNFG1, 0x78);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, 0x40);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, 0x78);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_CFG0, 0x38);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_CFG1, 0x3A);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_CFG2, 0x38);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_LDO4, 0xF);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_LDO8, 0xC7);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_SD0, 0x4F);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_SD1, 0x29);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_FPS_SD3, 0x1B);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0, 0x38);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1, 0x3A);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2, 0x38);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_LDO4, 0xF);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_LDO8, 0xC7);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD0, 0x4F);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD1, 0x29);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_SD3, 0x1B);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD0, 42); //42 = (1125000 - 600000) / 12500 -> 1.125V
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD0, 42); //42 = (1125000 - 600000) / 12500 -> 1.125V
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config_pmc_scratch();
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config_pmc_scratch(); // Missing from 4.x+
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = (CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333;
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mc_config_carveout();
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mc_config_carveout(); // Missing from 4.x+
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sdram_init();
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}
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@@ -1754,9 +1751,9 @@ void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR;
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void reloc_patcher(u32 payload_size)
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{
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const u32 START_OFF = 0x7C;
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const u32 PAYLOAD_END_OFF = 0x84;
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const u32 IPL_START_OFF = 0x88;
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static const u32 START_OFF = 0x7C;
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static const u32 PAYLOAD_END_OFF = 0x84;
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static const u32 IPL_START_OFF = 0x88;
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memcpy((u8 *)EXT_PAYLOAD_ADDR, (u8 *)IPL_START, PATCHED_RELOC_SZ);
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@@ -1807,7 +1804,12 @@ int launch_payload(char *path, bool update)
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}
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f_close(&fp);
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free(path);
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if (!update)
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{
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free(path);
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path = NULL;
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}
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if (update)
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{
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@@ -1834,14 +1836,14 @@ int launch_payload(char *path, bool update)
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{
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if (!update)
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reloc_patcher(ALIGN(size, 0x10));
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reconfig_hw_workaround(0);
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reconfig_hw_workaround(false);
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}
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else
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{
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reloc_patcher(0x7000);
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if (*(vu32 *)CBFS_SDRAM_EN_ADDR != 0x4452414D)
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return 1;
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reconfig_hw_workaround(1);
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reconfig_hw_workaround(true);
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}
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// Launch our payload.
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@@ -1958,7 +1960,10 @@ void launch_tools(u8 type)
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if (!type)
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{
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if (launch_payload(dir, false))
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{
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EPRINTF("Failed to launch payload.");
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free(dir);
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}
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}
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else
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ianos_loader(true, dir, DRAM_LIB, NULL);
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@@ -2145,8 +2150,8 @@ void launch_firmware()
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if (!cfg_sec)
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{
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gfx_printf(&gfx_con, "\nUsing default launch configuration...\n\n");
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gfx_puts(&gfx_con, "Press POWER to Continue.\nPress VOL to go to the menu.\n\n\n");
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gfx_puts(&gfx_con, "\nPress POWER to Continue.\nPress VOL to go to the menu.\n\n");
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gfx_printf(&gfx_con, "\nUsing default launch configuration...\n\n\n");
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u32 btn = btn_wait();
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if (!(btn & BTN_POWER))
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@@ -2261,7 +2266,6 @@ void auto_launch_firmware()
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if (h_cfg.autoboot_list)
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{
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ini_free(&ini_sections);
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list_init(&ini_sections);
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ini_free_section(cfg_sec);
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boot_entry_id = 1;
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bootlogoCustomEntry = NULL;
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@@ -3052,6 +3056,7 @@ ment_t ment_cinfo[] = {
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MDEF_BACK(),
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MDEF_CHGLINE(),
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MDEF_CAPTION("---- SoC Info ----", 0xFF0AB9E6),
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MDEF_HANDLER("Ipatches & bootrom info", bootrom_ipatches_info),
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MDEF_HANDLER("Print fuse info", print_fuseinfo),
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MDEF_HANDLER("Print kfuse info", print_kfuseinfo),
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MDEF_HANDLER("Print TSEC keys", print_tsec_key),
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@@ -3117,7 +3122,6 @@ ment_t ment_tools[] = {
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MDEF_HANDLER("Fix battery de-sync", fix_battery_desync),
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MDEF_HANDLER("Unset archive bit (switch folder)", fix_sd_switch_attr),
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MDEF_HANDLER("Unset archive bit (all sd files)", fix_sd_all_attr),
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MDEF_HANDLER("Ipatches & bootrom info", bootrom_ipatches_info),
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//MDEF_HANDLER("Fix fuel gauge configuration", fix_fuel_gauge_configuration),
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//MDEF_HANDLER("Reset all battery cfg", reset_pmic_fuel_gauge_charger_config),
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MDEF_CHGLINE(),
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@@ -3155,7 +3159,7 @@ extern void pivot_stack(u32 stack_top);
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void ipl_main()
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{
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// Skip config if we just updated the bootloader.
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if (*(u32 *)BOOTLOADER_UPDATED_MAGIC_ADDR != BOOTLOADER_UPDATED_MAGIC)
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if (*(vu32 *)BOOTLOADER_UPDATED_MAGIC_ADDR != BOOTLOADER_UPDATED_MAGIC)
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config_hw();
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//Pivot the stack so we have enough space.
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@@ -3167,6 +3171,9 @@ void ipl_main()
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//uart_send(UART_C, (u8 *)0x40000000, 0x10000);
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//uart_wait_idle(UART_C, UART_TX_IDLE);
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// Set bootloader's default configuration.
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set_default_configuration();
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// Save sdram lp0 config.
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ianos_loader(true, "bootloader/sys/libsys_lp0.bso", DRAM_LIB, (void *)sdram_get_params());
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@@ -3185,13 +3192,12 @@ void ipl_main()
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// Enable backlight after initializing gfx
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//display_backlight(true);
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set_default_configuration();
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// Load saved configuration and auto boot if enabled.
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auto_launch_firmware();
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while (1)
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while (true)
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tui_do_menu(&gfx_con, &menu_top);
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while (1)
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while (true)
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;
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}
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