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bdk: clock: add ext peripheral clock control

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This commit is contained in:
CTCaer
2022-05-09 06:08:39 +03:00
parent 47d06d0e8a
commit f452d916c9
3 changed files with 49 additions and 0 deletions
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35
bdk/soc/clock.c
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@@ -17,6 +17,7 @@
#include <soc/clock.h>
#include <soc/hw_init.h>
#include <soc/pmc.h>
#include <soc/t210.h>
#include <storage/sdmmc.h>
#include <utils/util.h>
@@ -109,6 +110,12 @@ static clock_t _clock_ahbdma = {
static clock_t _clock_actmon = {
CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON, CLK_V_ACTMON, 6, 0 // 19.2MHz.
};
static clock_t _clock_extperiph1 = {
CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1, CLK_V_EXTPERIPH1, 0, 0
};
static clock_t _clock_extperiph2 = {
CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2, CLK_V_EXTPERIPH2, 2, 202 // 4.0MHz
};
void clock_enable(const clock_t *clk)
{
@@ -341,6 +348,34 @@ void clock_disable_actmon()
clock_disable(&_clock_actmon);
}
void clock_enable_extperiph1()
{
clock_enable(&_clock_extperiph1);
PMC(APBDEV_PMC_CLK_OUT_CNTRL) |= PMC_CLK_OUT_CNTRL_CLK1_SRC_SEL(OSC_CAR) | PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN;
usleep(5);
}
void clock_disable_extperiph1()
{
PMC(APBDEV_PMC_CLK_OUT_CNTRL) &= ~((PMC_CLK_OUT_CNTRL_CLK1_SRC_SEL(OSC_CAR)) | PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN);
clock_disable(&_clock_extperiph1);
}
void clock_enable_extperiph2()
{
clock_enable(&_clock_extperiph2);
PMC(APBDEV_PMC_CLK_OUT_CNTRL) |= PMC_CLK_OUT_CNTRL_CLK2_SRC_SEL(OSC_CAR) | PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN;
usleep(5);
}
void clock_disable_extperiph2()
{
PMC(APBDEV_PMC_CLK_OUT_CNTRL) &= ~((PMC_CLK_OUT_CNTRL_CLK2_SRC_SEL(OSC_CAR)) | PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN);
clock_disable(&_clock_extperiph2);
}
void clock_enable_plld(u32 divp, u32 divn, bool lowpower, bool tegra_t210)
{
u32 plld_div = (divp << 20) | (divn << 11) | 1;