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clk: Refactor CLK devices bits

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This commit is contained in:
CTCaer
2020-07-17 16:50:17 +03:00
parent 3ddd1c26ad
commit e158d9bc00
10 changed files with 414 additions and 140 deletions
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16
bdk/usb/usbd.c
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@@ -351,15 +351,15 @@ int usb_device_init()
CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) | 0x2600000 | 0x800000;
// Enable USBD clock.
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = (1 << 22);
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD);
usleep(2);
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = (1 << 22);
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_USBD);
usleep(2);
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = (1 << 22);
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_USBD);
usleep(2);
// Clear XUSB_PADCTL reset
CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_CLR) = (1 << 14);
CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_CLR) = BIT(CLK_W_XUSB_PADCTL);
// Enable USB PHY and reset for programming.
u32 usb_susp_ctrl = USB(USB1_IF_USB_SUSP_CTRL);
@@ -419,7 +419,7 @@ int usb_device_init()
// Enable crystal clock.
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= 0x40000000;
// Enable USB2 tracking.
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= 0x40000;
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK);
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) & 0xFFFFFF00) | 6; // Set trank divisor to 4.
USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFC03F07) | 0x78000 | 0x50; // Set delays.
@@ -442,7 +442,7 @@ int usb_device_init()
USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFF7FFFFF) | 1;
// Disable USB2_TRK clock and configure UTMIP misc.
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) &= 0xFFFBFFFF;
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_CLR) = BIT(CLK_Y_USB2_TRK);
CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) = (CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) & 0xFEFFFFEA) | 0x2000000 | 0x28 | 2;
usleep(1);
@@ -535,10 +535,10 @@ static void _usb_device_power_down()
CLOCK(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0) |= 2;
// Set XUSB_PADCTL reset
CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = (1 << 14);
CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB_PADCTL);
// Disable USBD clock.
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = (1 << 22);
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_USBD);
// Completely disable PLLU.
CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x2E00000; // Disable PLLU USB/HSIC/ICUSB/48M.